1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char *p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 125fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 131fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 133fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 135fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 137dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 139dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 143fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 144fcf5ef2aSThomas Huth "reserve_addr"); 145253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 146253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 147253ce7b2SNikunj A Dadhania "reserve_val"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 150fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 153efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 154efe843d8SDavid Gibson "access_type"); 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth /* internal defines */ 158fcf5ef2aSThomas Huth struct DisasContext { 159b6bac4bcSEmilio G. Cota DisasContextBase base; 1602c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 161fcf5ef2aSThomas Huth uint32_t opcode; 162fcf5ef2aSThomas Huth uint32_t exception; 163fcf5ef2aSThomas Huth /* Routine used to access memory */ 164fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 165fcf5ef2aSThomas Huth bool lazy_tlb_flush; 166fcf5ef2aSThomas Huth bool need_access_type; 167fcf5ef2aSThomas Huth int mem_idx; 168fcf5ef2aSThomas Huth int access_type; 169fcf5ef2aSThomas Huth /* Translation flags */ 17014776ab5STony Nguyen MemOp default_tcg_memop_mask; 171fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 172fcf5ef2aSThomas Huth bool sf_mode; 173fcf5ef2aSThomas Huth bool has_cfar; 174fcf5ef2aSThomas Huth #endif 175fcf5ef2aSThomas Huth bool fpu_enabled; 176fcf5ef2aSThomas Huth bool altivec_enabled; 177fcf5ef2aSThomas Huth bool vsx_enabled; 178fcf5ef2aSThomas Huth bool spe_enabled; 179fcf5ef2aSThomas Huth bool tm_enabled; 180c6fd28fdSSuraj Jitindar Singh bool gtse; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 189fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 190fcf5ef2aSThomas Huth { 191fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 192fcf5ef2aSThomas Huth return ctx->le_mode; 193fcf5ef2aSThomas Huth #else 194fcf5ef2aSThomas Huth return !ctx->le_mode; 195fcf5ef2aSThomas Huth #endif 196fcf5ef2aSThomas Huth } 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 199fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 200fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 201fcf5ef2aSThomas Huth #else 202fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 203fcf5ef2aSThomas Huth #endif 204fcf5ef2aSThomas Huth 205fcf5ef2aSThomas Huth struct opc_handler_t { 206fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 207fcf5ef2aSThomas Huth uint32_t inval1; 208fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 209fcf5ef2aSThomas Huth uint32_t inval2; 210fcf5ef2aSThomas Huth /* instruction type */ 211fcf5ef2aSThomas Huth uint64_t type; 212fcf5ef2aSThomas Huth /* extended instruction type */ 213fcf5ef2aSThomas Huth uint64_t type2; 214fcf5ef2aSThomas Huth /* handler */ 215fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 216fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 217fcf5ef2aSThomas Huth const char *oname; 218fcf5ef2aSThomas Huth #endif 219fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 220fcf5ef2aSThomas Huth uint64_t count; 221fcf5ef2aSThomas Huth #endif 222fcf5ef2aSThomas Huth }; 223fcf5ef2aSThomas Huth 2240e3bf489SRoman Kapl /* SPR load/store helpers */ 2250e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2260e3bf489SRoman Kapl { 2270e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2280e3bf489SRoman Kapl } 2290e3bf489SRoman Kapl 2300e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2310e3bf489SRoman Kapl { 2320e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2330e3bf489SRoman Kapl } 2340e3bf489SRoman Kapl 235fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 236fcf5ef2aSThomas Huth { 237fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 238fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 239fcf5ef2aSThomas Huth ctx->access_type = access_type; 240fcf5ef2aSThomas Huth } 241fcf5ef2aSThomas Huth } 242fcf5ef2aSThomas Huth 243fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 244fcf5ef2aSThomas Huth { 245fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 246fcf5ef2aSThomas Huth nip = (uint32_t)nip; 247fcf5ef2aSThomas Huth } 248fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 249fcf5ef2aSThomas Huth } 250fcf5ef2aSThomas Huth 251fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 252fcf5ef2aSThomas Huth { 253fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 254fcf5ef2aSThomas Huth 255efe843d8SDavid Gibson /* 256efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 257efe843d8SDavid Gibson * faulting instruction 258fcf5ef2aSThomas Huth */ 259fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 2602c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 261fcf5ef2aSThomas Huth } 262fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 263fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 264fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 265fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 266fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 267*3d8a5b69SRichard Henderson ctx->exception = excp; 268*3d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 269fcf5ef2aSThomas Huth } 270fcf5ef2aSThomas Huth 271fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 272fcf5ef2aSThomas Huth { 273fcf5ef2aSThomas Huth TCGv_i32 t0; 274fcf5ef2aSThomas Huth 275efe843d8SDavid Gibson /* 276efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 277efe843d8SDavid Gibson * faulting instruction 278fcf5ef2aSThomas Huth */ 279fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 2802c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 281fcf5ef2aSThomas Huth } 282fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 283fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 284fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 285*3d8a5b69SRichard Henderson ctx->exception = excp; 286*3d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 287fcf5ef2aSThomas Huth } 288fcf5ef2aSThomas Huth 289fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 290fcf5ef2aSThomas Huth target_ulong nip) 291fcf5ef2aSThomas Huth { 292fcf5ef2aSThomas Huth TCGv_i32 t0; 293fcf5ef2aSThomas Huth 294fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 295fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 296fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 297fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 298*3d8a5b69SRichard Henderson ctx->exception = excp; 299*3d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 300fcf5ef2aSThomas Huth } 301fcf5ef2aSThomas Huth 302e150ac89SRoman Kapl /* 303e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 304e150ac89SRoman Kapl * SPR registers for this exception. 305e150ac89SRoman Kapl * 306e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 307e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3080e3bf489SRoman Kapl */ 309e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3100e3bf489SRoman Kapl { 3110e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3120e3bf489SRoman Kapl target_ulong dbsr = 0; 313e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3140e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 315e150ac89SRoman Kapl } else { 316e150ac89SRoman Kapl /* Must have been branch */ 3170e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3180e3bf489SRoman Kapl } 3190e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3200e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3210e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3220e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3230e3bf489SRoman Kapl tcg_temp_free(t0); 3240e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3250e3bf489SRoman Kapl } else { 326e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3270e3bf489SRoman Kapl } 3280e3bf489SRoman Kapl } 3290e3bf489SRoman Kapl 330fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 331fcf5ef2aSThomas Huth { 332fcf5ef2aSThomas Huth TCGv_i32 t0; 333fcf5ef2aSThomas Huth 334efe843d8SDavid Gibson /* 335efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 336efe843d8SDavid Gibson * faulting instruction 337fcf5ef2aSThomas Huth */ 338fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 339fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 340b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 341fcf5ef2aSThomas Huth } 342fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 343fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 344fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 345*3d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 346fcf5ef2aSThomas Huth } 347fcf5ef2aSThomas Huth 348fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 351fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 352fcf5ef2aSThomas Huth } 353fcf5ef2aSThomas Huth 354fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 355fcf5ef2aSThomas Huth { 356fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 357fcf5ef2aSThomas Huth } 358fcf5ef2aSThomas Huth 359fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 360fcf5ef2aSThomas Huth { 361fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 362fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 363fcf5ef2aSThomas Huth } 364fcf5ef2aSThomas Huth 365fcf5ef2aSThomas Huth /* Stop translation */ 366fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 367fcf5ef2aSThomas Huth { 368b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 369fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 370fcf5ef2aSThomas Huth } 371fcf5ef2aSThomas Huth 372fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 373fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 374fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 375fcf5ef2aSThomas Huth { 376fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 377fcf5ef2aSThomas Huth } 378fcf5ef2aSThomas Huth #endif 379fcf5ef2aSThomas Huth 38037f219c8SBruno Larsen (billionai) /*****************************************************************************/ 38137f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 38237f219c8SBruno Larsen (billionai) 383a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 38437f219c8SBruno Larsen (billionai) { 38537f219c8SBruno Larsen (billionai) #if 0 38637f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 38737f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 38837f219c8SBruno Larsen (billionai) #endif 38937f219c8SBruno Larsen (billionai) } 39037f219c8SBruno Larsen (billionai) 39137f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 39237f219c8SBruno Larsen (billionai) 39337f219c8SBruno Larsen (billionai) /* 39437f219c8SBruno Larsen (billionai) * Generic callbacks: 39537f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 39637f219c8SBruno Larsen (billionai) */ 39737f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 39837f219c8SBruno Larsen (billionai) { 39937f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 40037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 40137f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 40237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 40337f219c8SBruno Larsen (billionai) #endif 40437f219c8SBruno Larsen (billionai) } 40537f219c8SBruno Larsen (billionai) 406a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 40737f219c8SBruno Larsen (billionai) { 40837f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 40937f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 41037f219c8SBruno Larsen (billionai) } 41137f219c8SBruno Larsen (billionai) 41237f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 41337f219c8SBruno Larsen (billionai) { 41437f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 41537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 41637f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 41737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 41837f219c8SBruno Larsen (billionai) #endif 41937f219c8SBruno Larsen (billionai) } 42037f219c8SBruno Larsen (billionai) 421a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 42237f219c8SBruno Larsen (billionai) { 42337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 42437f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42537f219c8SBruno Larsen (billionai) } 42637f219c8SBruno Larsen (billionai) 42737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 428a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 42937f219c8SBruno Larsen (billionai) { 43037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 43537f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43637f219c8SBruno Larsen (billionai) #else 43737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43837f219c8SBruno Larsen (billionai) #endif 43937f219c8SBruno Larsen (billionai) } 44037f219c8SBruno Larsen (billionai) 441a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 44237f219c8SBruno Larsen (billionai) { 44337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44537f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 44637f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 44737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 44837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 45037f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 45137f219c8SBruno Larsen (billionai) } 45237f219c8SBruno Larsen (billionai) 453a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 45437f219c8SBruno Larsen (billionai) { 45537f219c8SBruno Larsen (billionai) } 45637f219c8SBruno Larsen (billionai) 45737f219c8SBruno Larsen (billionai) #endif 45837f219c8SBruno Larsen (billionai) 45937f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 46037f219c8SBruno Larsen (billionai) /* XER */ 461a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 46237f219c8SBruno Larsen (billionai) { 46337f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 46437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 46537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 46637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 46737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 46837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 46937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 47037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 47137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 47237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 47337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47437f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 47537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 47637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 47837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47937f219c8SBruno Larsen (billionai) } 48037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 48137f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 48237f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 48337f219c8SBruno Larsen (billionai) } 48437f219c8SBruno Larsen (billionai) 485a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 48637f219c8SBruno Larsen (billionai) { 48737f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 48837f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 48937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 49037f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 49137f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 49237f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 49337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 49437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 49537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 49637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 49737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 49837f219c8SBruno Larsen (billionai) } 49937f219c8SBruno Larsen (billionai) 50037f219c8SBruno Larsen (billionai) /* LR */ 501a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 50237f219c8SBruno Larsen (billionai) { 50337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 50437f219c8SBruno Larsen (billionai) } 50537f219c8SBruno Larsen (billionai) 506a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 50737f219c8SBruno Larsen (billionai) { 50837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 50937f219c8SBruno Larsen (billionai) } 51037f219c8SBruno Larsen (billionai) 51137f219c8SBruno Larsen (billionai) /* CFAR */ 51237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 513a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 51437f219c8SBruno Larsen (billionai) { 51537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 51637f219c8SBruno Larsen (billionai) } 51737f219c8SBruno Larsen (billionai) 518a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 51937f219c8SBruno Larsen (billionai) { 52037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 52137f219c8SBruno Larsen (billionai) } 52237f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 52337f219c8SBruno Larsen (billionai) 52437f219c8SBruno Larsen (billionai) /* CTR */ 525a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 52637f219c8SBruno Larsen (billionai) { 52737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 52837f219c8SBruno Larsen (billionai) } 52937f219c8SBruno Larsen (billionai) 530a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 53137f219c8SBruno Larsen (billionai) { 53237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 53337f219c8SBruno Larsen (billionai) } 53437f219c8SBruno Larsen (billionai) 53537f219c8SBruno Larsen (billionai) /* User read access to SPR */ 53637f219c8SBruno Larsen (billionai) /* USPRx */ 53737f219c8SBruno Larsen (billionai) /* UMMCRx */ 53837f219c8SBruno Larsen (billionai) /* UPMCx */ 53937f219c8SBruno Larsen (billionai) /* USIA */ 54037f219c8SBruno Larsen (billionai) /* UDECR */ 541a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 54237f219c8SBruno Larsen (billionai) { 54337f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 54437f219c8SBruno Larsen (billionai) } 54537f219c8SBruno Larsen (billionai) 54637f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 547a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 54837f219c8SBruno Larsen (billionai) { 54937f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 55037f219c8SBruno Larsen (billionai) } 55137f219c8SBruno Larsen (billionai) #endif 55237f219c8SBruno Larsen (billionai) 55337f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 55437f219c8SBruno Larsen (billionai) /* DECR */ 55537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 556a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 55737f219c8SBruno Larsen (billionai) { 55837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 55937f219c8SBruno Larsen (billionai) gen_io_start(); 56037f219c8SBruno Larsen (billionai) } 56137f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 56237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 56337f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 56437f219c8SBruno Larsen (billionai) } 56537f219c8SBruno Larsen (billionai) } 56637f219c8SBruno Larsen (billionai) 567a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 56837f219c8SBruno Larsen (billionai) { 56937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 57037f219c8SBruno Larsen (billionai) gen_io_start(); 57137f219c8SBruno Larsen (billionai) } 57237f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 57337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 57437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 57537f219c8SBruno Larsen (billionai) } 57637f219c8SBruno Larsen (billionai) } 57737f219c8SBruno Larsen (billionai) #endif 57837f219c8SBruno Larsen (billionai) 57937f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 58037f219c8SBruno Larsen (billionai) /* Time base */ 581a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 58237f219c8SBruno Larsen (billionai) { 58337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 58437f219c8SBruno Larsen (billionai) gen_io_start(); 58537f219c8SBruno Larsen (billionai) } 58637f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 58737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 58837f219c8SBruno Larsen (billionai) gen_io_end(); 58937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 59037f219c8SBruno Larsen (billionai) } 59137f219c8SBruno Larsen (billionai) } 59237f219c8SBruno Larsen (billionai) 593a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 59437f219c8SBruno Larsen (billionai) { 59537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 59637f219c8SBruno Larsen (billionai) gen_io_start(); 59737f219c8SBruno Larsen (billionai) } 59837f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 59937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 60037f219c8SBruno Larsen (billionai) gen_io_end(); 60137f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 60237f219c8SBruno Larsen (billionai) } 60337f219c8SBruno Larsen (billionai) } 60437f219c8SBruno Larsen (billionai) 605a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 60637f219c8SBruno Larsen (billionai) { 60737f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 60837f219c8SBruno Larsen (billionai) } 60937f219c8SBruno Larsen (billionai) 610a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 61137f219c8SBruno Larsen (billionai) { 61237f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 61337f219c8SBruno Larsen (billionai) } 61437f219c8SBruno Larsen (billionai) 61537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 616a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 61737f219c8SBruno Larsen (billionai) { 61837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 61937f219c8SBruno Larsen (billionai) gen_io_start(); 62037f219c8SBruno Larsen (billionai) } 62137f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 62237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 62337f219c8SBruno Larsen (billionai) gen_io_end(); 62437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 62537f219c8SBruno Larsen (billionai) } 62637f219c8SBruno Larsen (billionai) } 62737f219c8SBruno Larsen (billionai) 628a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 62937f219c8SBruno Larsen (billionai) { 63037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 63137f219c8SBruno Larsen (billionai) gen_io_start(); 63237f219c8SBruno Larsen (billionai) } 63337f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 63437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 63537f219c8SBruno Larsen (billionai) gen_io_end(); 63637f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 63737f219c8SBruno Larsen (billionai) } 63837f219c8SBruno Larsen (billionai) } 63937f219c8SBruno Larsen (billionai) 640a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 64137f219c8SBruno Larsen (billionai) { 64237f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 64337f219c8SBruno Larsen (billionai) } 64437f219c8SBruno Larsen (billionai) 645a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 64637f219c8SBruno Larsen (billionai) { 64737f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 64837f219c8SBruno Larsen (billionai) } 64937f219c8SBruno Larsen (billionai) 65037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 651a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 65237f219c8SBruno Larsen (billionai) { 65337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 65437f219c8SBruno Larsen (billionai) gen_io_start(); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 65737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 65837f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 65937f219c8SBruno Larsen (billionai) } 66037f219c8SBruno Larsen (billionai) } 66137f219c8SBruno Larsen (billionai) 662a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 66337f219c8SBruno Larsen (billionai) { 66437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 66537f219c8SBruno Larsen (billionai) gen_io_start(); 66637f219c8SBruno Larsen (billionai) } 66737f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 66837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 66937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 67037f219c8SBruno Larsen (billionai) } 67137f219c8SBruno Larsen (billionai) } 67237f219c8SBruno Larsen (billionai) 67337f219c8SBruno Larsen (billionai) /* HDECR */ 674a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 67537f219c8SBruno Larsen (billionai) { 67637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 67737f219c8SBruno Larsen (billionai) gen_io_start(); 67837f219c8SBruno Larsen (billionai) } 67937f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 68037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 68137f219c8SBruno Larsen (billionai) gen_io_end(); 68237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) } 68537f219c8SBruno Larsen (billionai) 686a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 68737f219c8SBruno Larsen (billionai) { 68837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 68937f219c8SBruno Larsen (billionai) gen_io_start(); 69037f219c8SBruno Larsen (billionai) } 69137f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 69237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 69337f219c8SBruno Larsen (billionai) gen_io_end(); 69437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 69537f219c8SBruno Larsen (billionai) } 69637f219c8SBruno Larsen (billionai) } 69737f219c8SBruno Larsen (billionai) 698a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 69937f219c8SBruno Larsen (billionai) { 70037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 70137f219c8SBruno Larsen (billionai) gen_io_start(); 70237f219c8SBruno Larsen (billionai) } 70337f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 70437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 70537f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) } 70837f219c8SBruno Larsen (billionai) 709a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 71037f219c8SBruno Larsen (billionai) { 71137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 71237f219c8SBruno Larsen (billionai) gen_io_start(); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 71537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 71637f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 71737f219c8SBruno Larsen (billionai) } 71837f219c8SBruno Larsen (billionai) } 71937f219c8SBruno Larsen (billionai) 720a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 72137f219c8SBruno Larsen (billionai) { 72237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 72337f219c8SBruno Larsen (billionai) gen_io_start(); 72437f219c8SBruno Larsen (billionai) } 72537f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 72737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 72837f219c8SBruno Larsen (billionai) } 72937f219c8SBruno Larsen (billionai) } 73037f219c8SBruno Larsen (billionai) 73137f219c8SBruno Larsen (billionai) #endif 73237f219c8SBruno Larsen (billionai) #endif 73337f219c8SBruno Larsen (billionai) 73437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 73537f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 73637f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 737a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 73837f219c8SBruno Larsen (billionai) { 73937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 74237f219c8SBruno Larsen (billionai) } 74337f219c8SBruno Larsen (billionai) 744a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74837f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 74937f219c8SBruno Larsen (billionai) } 75037f219c8SBruno Larsen (billionai) 751a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 75237f219c8SBruno Larsen (billionai) { 75337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 75437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 75537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75637f219c8SBruno Larsen (billionai) } 75737f219c8SBruno Larsen (billionai) 758a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 75937f219c8SBruno Larsen (billionai) { 76037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 76137f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 76237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 76337f219c8SBruno Larsen (billionai) } 76437f219c8SBruno Larsen (billionai) 765a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 76637f219c8SBruno Larsen (billionai) { 76737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 76837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 76937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 77037f219c8SBruno Larsen (billionai) } 77137f219c8SBruno Larsen (billionai) 772a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 77337f219c8SBruno Larsen (billionai) { 77437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 77537f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 77637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 77737f219c8SBruno Larsen (billionai) } 77837f219c8SBruno Larsen (billionai) 77937f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 78037f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 781a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 78237f219c8SBruno Larsen (billionai) { 78337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 78437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 78537f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 78637f219c8SBruno Larsen (billionai) } 78737f219c8SBruno Larsen (billionai) 788a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 78937f219c8SBruno Larsen (billionai) { 79037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 79137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 79237f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) 795a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 79637f219c8SBruno Larsen (billionai) { 79737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 79837f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 79937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 80037f219c8SBruno Larsen (billionai) } 80137f219c8SBruno Larsen (billionai) 802a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 80337f219c8SBruno Larsen (billionai) { 80437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 80537f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 80637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 80737f219c8SBruno Larsen (billionai) } 80837f219c8SBruno Larsen (billionai) 809a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 81037f219c8SBruno Larsen (billionai) { 81137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 81237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 81337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 81437f219c8SBruno Larsen (billionai) } 81537f219c8SBruno Larsen (billionai) 816a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 81737f219c8SBruno Larsen (billionai) { 81837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 81937f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 82037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 82137f219c8SBruno Larsen (billionai) } 82237f219c8SBruno Larsen (billionai) 82337f219c8SBruno Larsen (billionai) /* SDR1 */ 824a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 82537f219c8SBruno Larsen (billionai) { 82637f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 82737f219c8SBruno Larsen (billionai) } 82837f219c8SBruno Larsen (billionai) 82937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 83037f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 83137f219c8SBruno Larsen (billionai) /* PIDR */ 832a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 83337f219c8SBruno Larsen (billionai) { 83437f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) 837a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 83837f219c8SBruno Larsen (billionai) { 83937f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 84037f219c8SBruno Larsen (billionai) } 84137f219c8SBruno Larsen (billionai) 842a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 84337f219c8SBruno Larsen (billionai) { 84437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 84537f219c8SBruno Larsen (billionai) } 84637f219c8SBruno Larsen (billionai) 847a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 84837f219c8SBruno Larsen (billionai) { 84937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 85037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 85137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 85237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 85337f219c8SBruno Larsen (billionai) } 854a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 85537f219c8SBruno Larsen (billionai) { 85637f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 85737f219c8SBruno Larsen (billionai) } 85837f219c8SBruno Larsen (billionai) 859a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 86037f219c8SBruno Larsen (billionai) { 86137f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 86237f219c8SBruno Larsen (billionai) } 86337f219c8SBruno Larsen (billionai) 86437f219c8SBruno Larsen (billionai) /* DPDES */ 865a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 86637f219c8SBruno Larsen (billionai) { 86737f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 86837f219c8SBruno Larsen (billionai) } 86937f219c8SBruno Larsen (billionai) 870a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 87137f219c8SBruno Larsen (billionai) { 87237f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 87337f219c8SBruno Larsen (billionai) } 87437f219c8SBruno Larsen (billionai) #endif 87537f219c8SBruno Larsen (billionai) #endif 87637f219c8SBruno Larsen (billionai) 87737f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 87837f219c8SBruno Larsen (billionai) /* RTC */ 879a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 88037f219c8SBruno Larsen (billionai) { 88137f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 88237f219c8SBruno Larsen (billionai) } 88337f219c8SBruno Larsen (billionai) 884a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 88537f219c8SBruno Larsen (billionai) { 88637f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 88737f219c8SBruno Larsen (billionai) } 88837f219c8SBruno Larsen (billionai) 88937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 890a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 89137f219c8SBruno Larsen (billionai) { 89237f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 89337f219c8SBruno Larsen (billionai) } 89437f219c8SBruno Larsen (billionai) 895a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 89637f219c8SBruno Larsen (billionai) { 89737f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 89837f219c8SBruno Larsen (billionai) } 89937f219c8SBruno Larsen (billionai) 900a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 90137f219c8SBruno Larsen (billionai) { 90237f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 90337f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 90437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 90537f219c8SBruno Larsen (billionai) } 90637f219c8SBruno Larsen (billionai) #endif 90737f219c8SBruno Larsen (billionai) 90837f219c8SBruno Larsen (billionai) /* Unified bats */ 90937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 910a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 91137f219c8SBruno Larsen (billionai) { 91237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 91337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 91437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 91537f219c8SBruno Larsen (billionai) } 91637f219c8SBruno Larsen (billionai) 917a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 91837f219c8SBruno Larsen (billionai) { 91937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 92037f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 92137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92237f219c8SBruno Larsen (billionai) } 92337f219c8SBruno Larsen (billionai) 924a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 92537f219c8SBruno Larsen (billionai) { 92637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 92737f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 92837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92937f219c8SBruno Larsen (billionai) } 93037f219c8SBruno Larsen (billionai) #endif 93137f219c8SBruno Larsen (billionai) 93237f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 93337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 934a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 93537f219c8SBruno Larsen (billionai) { 93637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 93737f219c8SBruno Larsen (billionai) gen_io_start(); 93837f219c8SBruno Larsen (billionai) } 93937f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 94037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 94137f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 94237f219c8SBruno Larsen (billionai) } 94337f219c8SBruno Larsen (billionai) } 94437f219c8SBruno Larsen (billionai) 945a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 94637f219c8SBruno Larsen (billionai) { 94737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 94837f219c8SBruno Larsen (billionai) gen_io_start(); 94937f219c8SBruno Larsen (billionai) } 95037f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 95137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 95237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 95337f219c8SBruno Larsen (billionai) } 95437f219c8SBruno Larsen (billionai) } 95537f219c8SBruno Larsen (billionai) 956a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 95737f219c8SBruno Larsen (billionai) { 95837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 95937f219c8SBruno Larsen (billionai) gen_io_start(); 96037f219c8SBruno Larsen (billionai) } 96137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 96237f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 96337f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 96437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 96537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 96637f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 96737f219c8SBruno Larsen (billionai) } 96837f219c8SBruno Larsen (billionai) } 96937f219c8SBruno Larsen (billionai) 970a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 97137f219c8SBruno Larsen (billionai) { 97237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 97337f219c8SBruno Larsen (billionai) gen_io_start(); 97437f219c8SBruno Larsen (billionai) } 97537f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 97637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 97737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 97837f219c8SBruno Larsen (billionai) } 97937f219c8SBruno Larsen (billionai) } 98037f219c8SBruno Larsen (billionai) 981a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 98237f219c8SBruno Larsen (billionai) { 98337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 98437f219c8SBruno Larsen (billionai) gen_io_start(); 98537f219c8SBruno Larsen (billionai) } 98637f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 98737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 98837f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 98937f219c8SBruno Larsen (billionai) } 99037f219c8SBruno Larsen (billionai) } 99137f219c8SBruno Larsen (billionai) 992a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 99337f219c8SBruno Larsen (billionai) { 99437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 99537f219c8SBruno Larsen (billionai) gen_io_start(); 99637f219c8SBruno Larsen (billionai) } 99737f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 99837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 99937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 100037f219c8SBruno Larsen (billionai) } 100137f219c8SBruno Larsen (billionai) } 100237f219c8SBruno Larsen (billionai) #endif 100337f219c8SBruno Larsen (billionai) 100437f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 100537f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 100637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1007a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 100837f219c8SBruno Larsen (billionai) { 100937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 101037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 101137f219c8SBruno Larsen (billionai) } 101237f219c8SBruno Larsen (billionai) 1013a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 101437f219c8SBruno Larsen (billionai) { 101537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 101637f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 101737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 101837f219c8SBruno Larsen (billionai) } 101937f219c8SBruno Larsen (billionai) 1020a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 102137f219c8SBruno Larsen (billionai) { 102237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 102337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 102437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 102537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102637f219c8SBruno Larsen (billionai) } 102737f219c8SBruno Larsen (billionai) #endif 102837f219c8SBruno Larsen (billionai) 102937f219c8SBruno Larsen (billionai) /* SPE specific registers */ 1030a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 103137f219c8SBruno Larsen (billionai) { 103237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 103337f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 103437f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 103537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 103637f219c8SBruno Larsen (billionai) } 103737f219c8SBruno Larsen (billionai) 1038a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 103937f219c8SBruno Larsen (billionai) { 104037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 104137f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 104237f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 104337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 104437f219c8SBruno Larsen (billionai) } 104537f219c8SBruno Larsen (billionai) 104637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 104737f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 1048a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 104937f219c8SBruno Larsen (billionai) { 105037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 105137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 105237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 105337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 105437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 105537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105637f219c8SBruno Larsen (billionai) } 105737f219c8SBruno Larsen (billionai) 1058a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 105937f219c8SBruno Larsen (billionai) { 106037f219c8SBruno Larsen (billionai) int sprn_offs; 106137f219c8SBruno Larsen (billionai) 106237f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 106337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 106437f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 106537f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 106637f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 106737f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 106837f219c8SBruno Larsen (billionai) } else { 106937f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 107037f219c8SBruno Larsen (billionai) sprn, sprn); 107137f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 107237f219c8SBruno Larsen (billionai) return; 107337f219c8SBruno Larsen (billionai) } 107437f219c8SBruno Larsen (billionai) 107537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 107737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 107837f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 107937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 108137f219c8SBruno Larsen (billionai) } 108237f219c8SBruno Larsen (billionai) #endif 108337f219c8SBruno Larsen (billionai) 108437f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 108537f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1086a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 108737f219c8SBruno Larsen (billionai) { 108837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 109037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 109137f219c8SBruno Larsen (billionai) 109237f219c8SBruno Larsen (billionai) /* 109337f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 109437f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 109537f219c8SBruno Larsen (billionai) */ 109637f219c8SBruno Larsen (billionai) 109737f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 109837f219c8SBruno Larsen (billionai) if (ctx->pr) { 109937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 110037f219c8SBruno Larsen (billionai) } else { 110137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 110237f219c8SBruno Larsen (billionai) } 110337f219c8SBruno Larsen (billionai) 110437f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 110537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 110637f219c8SBruno Larsen (billionai) 110737f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 110837f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 110937f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 111037f219c8SBruno Larsen (billionai) 111137f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 111237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 111337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 111437f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 111537f219c8SBruno Larsen (billionai) 111637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 111737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 111837f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 111937f219c8SBruno Larsen (billionai) } 112037f219c8SBruno Larsen (billionai) 1121a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 112237f219c8SBruno Larsen (billionai) { 112337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 112437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 112537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 112637f219c8SBruno Larsen (billionai) 112737f219c8SBruno Larsen (billionai) /* 112837f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 112937f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 113037f219c8SBruno Larsen (billionai) */ 113137f219c8SBruno Larsen (billionai) 113237f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 113337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 113437f219c8SBruno Larsen (billionai) 113537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 113637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 113737f219c8SBruno Larsen (billionai) 113837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 113937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 114037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 114137f219c8SBruno Larsen (billionai) 114237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 114337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 114437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 114537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 114637f219c8SBruno Larsen (billionai) 114737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 114837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 114937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 115037f219c8SBruno Larsen (billionai) } 115137f219c8SBruno Larsen (billionai) 1152a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 115337f219c8SBruno Larsen (billionai) { 115437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 115537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 115637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 115737f219c8SBruno Larsen (billionai) 115837f219c8SBruno Larsen (billionai) /* 115937f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 116037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 116137f219c8SBruno Larsen (billionai) */ 116237f219c8SBruno Larsen (billionai) 116337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 116437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 116537f219c8SBruno Larsen (billionai) 116637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 116737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 116837f219c8SBruno Larsen (billionai) 116937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 117037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 117137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 117237f219c8SBruno Larsen (billionai) 117337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 117437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 117537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 117637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 117737f219c8SBruno Larsen (billionai) 117837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 117937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 118037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 118137f219c8SBruno Larsen (billionai) } 118237f219c8SBruno Larsen (billionai) #endif 118337f219c8SBruno Larsen (billionai) #endif 118437f219c8SBruno Larsen (billionai) 118537f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1186a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 118737f219c8SBruno Larsen (billionai) { 118837f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 118937f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 119037f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 119137f219c8SBruno Larsen (billionai) } 119237f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 119337f219c8SBruno Larsen (billionai) 119437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1195a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 119637f219c8SBruno Larsen (billionai) { 119737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 119837f219c8SBruno Larsen (billionai) 119937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 120037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 120137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 120237f219c8SBruno Larsen (billionai) } 120337f219c8SBruno Larsen (billionai) 1204a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 120537f219c8SBruno Larsen (billionai) { 120637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 120737f219c8SBruno Larsen (billionai) 120837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 120937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 121037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 121137f219c8SBruno Larsen (billionai) } 121237f219c8SBruno Larsen (billionai) 1213a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 121437f219c8SBruno Larsen (billionai) { 121537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 121637f219c8SBruno Larsen (billionai) 121737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 121837f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 121937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 122037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 122137f219c8SBruno Larsen (billionai) } 122237f219c8SBruno Larsen (billionai) 1223a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 122437f219c8SBruno Larsen (billionai) { 122537f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 122637f219c8SBruno Larsen (billionai) } 122737f219c8SBruno Larsen (billionai) 1228a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 122937f219c8SBruno Larsen (billionai) { 123037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 123137f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 123237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 123337f219c8SBruno Larsen (billionai) } 1234a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 123537f219c8SBruno Larsen (billionai) { 123637f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 123737f219c8SBruno Larsen (billionai) } 1238a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 123937f219c8SBruno Larsen (billionai) { 124037f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 124137f219c8SBruno Larsen (billionai) } 124237f219c8SBruno Larsen (billionai) 124337f219c8SBruno Larsen (billionai) #endif 124437f219c8SBruno Larsen (billionai) 124537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1246a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 124737f219c8SBruno Larsen (billionai) { 124837f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 124937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 125037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 125137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 125237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 125337f219c8SBruno Larsen (billionai) tcg_temp_free(val); 125437f219c8SBruno Larsen (billionai) } 125537f219c8SBruno Larsen (billionai) 1256a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 125737f219c8SBruno Larsen (billionai) { 125837f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 125937f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 126037f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 126137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 126237f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 126337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 126437f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 126537f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 126637f219c8SBruno Larsen (billionai) } 126737f219c8SBruno Larsen (billionai) 126837f219c8SBruno Larsen (billionai) #endif 126937f219c8SBruno Larsen (billionai) 127037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 127137f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 127237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 127337f219c8SBruno Larsen (billionai) { 127437f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 127537f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 127637f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 127737f219c8SBruno Larsen (billionai) 127837f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 127937f219c8SBruno Larsen (billionai) 128037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 128137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 128237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 128337f219c8SBruno Larsen (billionai) } 128437f219c8SBruno Larsen (billionai) 128537f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 128637f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 128737f219c8SBruno Larsen (billionai) { 128837f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 128937f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 129037f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 129137f219c8SBruno Larsen (billionai) 129237f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 129337f219c8SBruno Larsen (billionai) 129437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 129537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 129637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 129737f219c8SBruno Larsen (billionai) } 129837f219c8SBruno Larsen (billionai) 1299a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 130037f219c8SBruno Larsen (billionai) { 130137f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 130237f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 130337f219c8SBruno Larsen (billionai) 130437f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 130537f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 130637f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 130737f219c8SBruno Larsen (billionai) 130837f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 130937f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 131037f219c8SBruno Larsen (billionai) } 131137f219c8SBruno Larsen (billionai) 1312a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 131337f219c8SBruno Larsen (billionai) { 131437f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 131537f219c8SBruno Larsen (billionai) 131637f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 131737f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 131837f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 131937f219c8SBruno Larsen (billionai) 132037f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 132137f219c8SBruno Larsen (billionai) } 132237f219c8SBruno Larsen (billionai) 132337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1324a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 132537f219c8SBruno Larsen (billionai) { 132637f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 132737f219c8SBruno Larsen (billionai) 132837f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 132937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 133037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 133137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 133237f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 133337f219c8SBruno Larsen (billionai) } 133437f219c8SBruno Larsen (billionai) 1335a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 133637f219c8SBruno Larsen (billionai) { 133737f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 133837f219c8SBruno Larsen (billionai) } 133937f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 134037f219c8SBruno Larsen (billionai) 1341a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 134237f219c8SBruno Larsen (billionai) { 134337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 134437f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 134537f219c8SBruno Larsen (billionai) } 134637f219c8SBruno Larsen (billionai) 1347a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 134837f219c8SBruno Larsen (billionai) { 134937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 135037f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 135137f219c8SBruno Larsen (billionai) } 135237f219c8SBruno Larsen (billionai) 1353a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 135437f219c8SBruno Larsen (billionai) { 135537f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 135637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 135737f219c8SBruno Larsen (billionai) } 135837f219c8SBruno Larsen (billionai) 1359a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 136037f219c8SBruno Larsen (billionai) { 136137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 136237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 136337f219c8SBruno Larsen (billionai) } 136437f219c8SBruno Larsen (billionai) 1365a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 136637f219c8SBruno Larsen (billionai) { 136737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 136837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 136937f219c8SBruno Larsen (billionai) } 137037f219c8SBruno Larsen (billionai) 1371a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 137237f219c8SBruno Larsen (billionai) { 137337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 137437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 137537f219c8SBruno Larsen (billionai) } 137637f219c8SBruno Larsen (billionai) 1377a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 137837f219c8SBruno Larsen (billionai) { 137937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 138037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 138137f219c8SBruno Larsen (billionai) } 138237f219c8SBruno Larsen (billionai) 1383a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 138437f219c8SBruno Larsen (billionai) { 138537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 138637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 138737f219c8SBruno Larsen (billionai) } 138837f219c8SBruno Larsen (billionai) 1389a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 139037f219c8SBruno Larsen (billionai) { 139137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 139237f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 139337f219c8SBruno Larsen (billionai) } 139437f219c8SBruno Larsen (billionai) 1395a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 139637f219c8SBruno Larsen (billionai) { 139737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 139837f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 139937f219c8SBruno Larsen (billionai) } 140037f219c8SBruno Larsen (billionai) #endif 140137f219c8SBruno Larsen (billionai) 1402fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1403fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1404fcf5ef2aSThomas Huth 1405fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1406fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1407fcf5ef2aSThomas Huth 1408fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1409fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1410fcf5ef2aSThomas Huth 1411fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1412fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1413fcf5ef2aSThomas Huth 1414fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1415fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1416fcf5ef2aSThomas Huth 1417fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1418fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1419fcf5ef2aSThomas Huth 1420fcf5ef2aSThomas Huth typedef struct opcode_t { 1421fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1422fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1423fcf5ef2aSThomas Huth unsigned char pad[4]; 1424fcf5ef2aSThomas Huth #endif 1425fcf5ef2aSThomas Huth opc_handler_t handler; 1426fcf5ef2aSThomas Huth const char *oname; 1427fcf5ef2aSThomas Huth } opcode_t; 1428fcf5ef2aSThomas Huth 1429fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1430fcf5ef2aSThomas Huth #define GEN_PRIV \ 1431fcf5ef2aSThomas Huth do { \ 1432fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1433fcf5ef2aSThomas Huth } while (0) 1434fcf5ef2aSThomas Huth 1435fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1436fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1437fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1438fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1439fcf5ef2aSThomas Huth #else 1440fcf5ef2aSThomas Huth #define CHK_HV \ 1441fcf5ef2aSThomas Huth do { \ 1442fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1443fcf5ef2aSThomas Huth GEN_PRIV; \ 1444fcf5ef2aSThomas Huth } \ 1445fcf5ef2aSThomas Huth } while (0) 1446fcf5ef2aSThomas Huth #define CHK_SV \ 1447fcf5ef2aSThomas Huth do { \ 1448fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1449fcf5ef2aSThomas Huth GEN_PRIV; \ 1450fcf5ef2aSThomas Huth } \ 1451fcf5ef2aSThomas Huth } while (0) 1452fcf5ef2aSThomas Huth #define CHK_HVRM \ 1453fcf5ef2aSThomas Huth do { \ 1454fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1455fcf5ef2aSThomas Huth GEN_PRIV; \ 1456fcf5ef2aSThomas Huth } \ 1457fcf5ef2aSThomas Huth } while (0) 1458fcf5ef2aSThomas Huth #endif 1459fcf5ef2aSThomas Huth 1460fcf5ef2aSThomas Huth #define CHK_NONE 1461fcf5ef2aSThomas Huth 1462fcf5ef2aSThomas Huth /*****************************************************************************/ 1463fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1464fcf5ef2aSThomas Huth 1465fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 1466fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1467fcf5ef2aSThomas Huth { \ 1468fcf5ef2aSThomas Huth .opc1 = op1, \ 1469fcf5ef2aSThomas Huth .opc2 = op2, \ 1470fcf5ef2aSThomas Huth .opc3 = op3, \ 1471fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1472fcf5ef2aSThomas Huth .handler = { \ 1473fcf5ef2aSThomas Huth .inval1 = invl, \ 1474fcf5ef2aSThomas Huth .type = _typ, \ 1475fcf5ef2aSThomas Huth .type2 = _typ2, \ 1476fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1477fcf5ef2aSThomas Huth .oname = stringify(name), \ 1478fcf5ef2aSThomas Huth }, \ 1479fcf5ef2aSThomas Huth .oname = stringify(name), \ 1480fcf5ef2aSThomas Huth } 1481fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1482fcf5ef2aSThomas Huth { \ 1483fcf5ef2aSThomas Huth .opc1 = op1, \ 1484fcf5ef2aSThomas Huth .opc2 = op2, \ 1485fcf5ef2aSThomas Huth .opc3 = op3, \ 1486fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1487fcf5ef2aSThomas Huth .handler = { \ 1488fcf5ef2aSThomas Huth .inval1 = invl1, \ 1489fcf5ef2aSThomas Huth .inval2 = invl2, \ 1490fcf5ef2aSThomas Huth .type = _typ, \ 1491fcf5ef2aSThomas Huth .type2 = _typ2, \ 1492fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1493fcf5ef2aSThomas Huth .oname = stringify(name), \ 1494fcf5ef2aSThomas Huth }, \ 1495fcf5ef2aSThomas Huth .oname = stringify(name), \ 1496fcf5ef2aSThomas Huth } 1497fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1498fcf5ef2aSThomas Huth { \ 1499fcf5ef2aSThomas Huth .opc1 = op1, \ 1500fcf5ef2aSThomas Huth .opc2 = op2, \ 1501fcf5ef2aSThomas Huth .opc3 = op3, \ 1502fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1503fcf5ef2aSThomas Huth .handler = { \ 1504fcf5ef2aSThomas Huth .inval1 = invl, \ 1505fcf5ef2aSThomas Huth .type = _typ, \ 1506fcf5ef2aSThomas Huth .type2 = _typ2, \ 1507fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1508fcf5ef2aSThomas Huth .oname = onam, \ 1509fcf5ef2aSThomas Huth }, \ 1510fcf5ef2aSThomas Huth .oname = onam, \ 1511fcf5ef2aSThomas Huth } 1512fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1513fcf5ef2aSThomas Huth { \ 1514fcf5ef2aSThomas Huth .opc1 = op1, \ 1515fcf5ef2aSThomas Huth .opc2 = op2, \ 1516fcf5ef2aSThomas Huth .opc3 = op3, \ 1517fcf5ef2aSThomas Huth .opc4 = op4, \ 1518fcf5ef2aSThomas Huth .handler = { \ 1519fcf5ef2aSThomas Huth .inval1 = invl, \ 1520fcf5ef2aSThomas Huth .type = _typ, \ 1521fcf5ef2aSThomas Huth .type2 = _typ2, \ 1522fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1523fcf5ef2aSThomas Huth .oname = stringify(name), \ 1524fcf5ef2aSThomas Huth }, \ 1525fcf5ef2aSThomas Huth .oname = stringify(name), \ 1526fcf5ef2aSThomas Huth } 1527fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1528fcf5ef2aSThomas Huth { \ 1529fcf5ef2aSThomas Huth .opc1 = op1, \ 1530fcf5ef2aSThomas Huth .opc2 = op2, \ 1531fcf5ef2aSThomas Huth .opc3 = op3, \ 1532fcf5ef2aSThomas Huth .opc4 = op4, \ 1533fcf5ef2aSThomas Huth .handler = { \ 1534fcf5ef2aSThomas Huth .inval1 = invl, \ 1535fcf5ef2aSThomas Huth .type = _typ, \ 1536fcf5ef2aSThomas Huth .type2 = _typ2, \ 1537fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1538fcf5ef2aSThomas Huth .oname = onam, \ 1539fcf5ef2aSThomas Huth }, \ 1540fcf5ef2aSThomas Huth .oname = onam, \ 1541fcf5ef2aSThomas Huth } 1542fcf5ef2aSThomas Huth #else 1543fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1544fcf5ef2aSThomas Huth { \ 1545fcf5ef2aSThomas Huth .opc1 = op1, \ 1546fcf5ef2aSThomas Huth .opc2 = op2, \ 1547fcf5ef2aSThomas Huth .opc3 = op3, \ 1548fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1549fcf5ef2aSThomas Huth .handler = { \ 1550fcf5ef2aSThomas Huth .inval1 = invl, \ 1551fcf5ef2aSThomas Huth .type = _typ, \ 1552fcf5ef2aSThomas Huth .type2 = _typ2, \ 1553fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1554fcf5ef2aSThomas Huth }, \ 1555fcf5ef2aSThomas Huth .oname = stringify(name), \ 1556fcf5ef2aSThomas Huth } 1557fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1558fcf5ef2aSThomas Huth { \ 1559fcf5ef2aSThomas Huth .opc1 = op1, \ 1560fcf5ef2aSThomas Huth .opc2 = op2, \ 1561fcf5ef2aSThomas Huth .opc3 = op3, \ 1562fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1563fcf5ef2aSThomas Huth .handler = { \ 1564fcf5ef2aSThomas Huth .inval1 = invl1, \ 1565fcf5ef2aSThomas Huth .inval2 = invl2, \ 1566fcf5ef2aSThomas Huth .type = _typ, \ 1567fcf5ef2aSThomas Huth .type2 = _typ2, \ 1568fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1569fcf5ef2aSThomas Huth }, \ 1570fcf5ef2aSThomas Huth .oname = stringify(name), \ 1571fcf5ef2aSThomas Huth } 1572fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1573fcf5ef2aSThomas Huth { \ 1574fcf5ef2aSThomas Huth .opc1 = op1, \ 1575fcf5ef2aSThomas Huth .opc2 = op2, \ 1576fcf5ef2aSThomas Huth .opc3 = op3, \ 1577fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1578fcf5ef2aSThomas Huth .handler = { \ 1579fcf5ef2aSThomas Huth .inval1 = invl, \ 1580fcf5ef2aSThomas Huth .type = _typ, \ 1581fcf5ef2aSThomas Huth .type2 = _typ2, \ 1582fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1583fcf5ef2aSThomas Huth }, \ 1584fcf5ef2aSThomas Huth .oname = onam, \ 1585fcf5ef2aSThomas Huth } 1586fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1587fcf5ef2aSThomas Huth { \ 1588fcf5ef2aSThomas Huth .opc1 = op1, \ 1589fcf5ef2aSThomas Huth .opc2 = op2, \ 1590fcf5ef2aSThomas Huth .opc3 = op3, \ 1591fcf5ef2aSThomas Huth .opc4 = op4, \ 1592fcf5ef2aSThomas Huth .handler = { \ 1593fcf5ef2aSThomas Huth .inval1 = invl, \ 1594fcf5ef2aSThomas Huth .type = _typ, \ 1595fcf5ef2aSThomas Huth .type2 = _typ2, \ 1596fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1597fcf5ef2aSThomas Huth }, \ 1598fcf5ef2aSThomas Huth .oname = stringify(name), \ 1599fcf5ef2aSThomas Huth } 1600fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1601fcf5ef2aSThomas Huth { \ 1602fcf5ef2aSThomas Huth .opc1 = op1, \ 1603fcf5ef2aSThomas Huth .opc2 = op2, \ 1604fcf5ef2aSThomas Huth .opc3 = op3, \ 1605fcf5ef2aSThomas Huth .opc4 = op4, \ 1606fcf5ef2aSThomas Huth .handler = { \ 1607fcf5ef2aSThomas Huth .inval1 = invl, \ 1608fcf5ef2aSThomas Huth .type = _typ, \ 1609fcf5ef2aSThomas Huth .type2 = _typ2, \ 1610fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1611fcf5ef2aSThomas Huth }, \ 1612fcf5ef2aSThomas Huth .oname = onam, \ 1613fcf5ef2aSThomas Huth } 1614fcf5ef2aSThomas Huth #endif 1615fcf5ef2aSThomas Huth 1616fcf5ef2aSThomas Huth /* Invalid instruction */ 1617fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1618fcf5ef2aSThomas Huth { 1619fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1620fcf5ef2aSThomas Huth } 1621fcf5ef2aSThomas Huth 1622fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1623fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1624fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1625fcf5ef2aSThomas Huth .type = PPC_NONE, 1626fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1627fcf5ef2aSThomas Huth .handler = gen_invalid, 1628fcf5ef2aSThomas Huth }; 1629fcf5ef2aSThomas Huth 1630fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1631fcf5ef2aSThomas Huth 1632fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1633fcf5ef2aSThomas Huth { 1634fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1635b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1636b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1637fcf5ef2aSThomas Huth 1638b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1639b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1640efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1641efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1642b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1643efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1644efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1645b62b3686Spbonzini@redhat.com 1646b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1647fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1648b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1649fcf5ef2aSThomas Huth 1650fcf5ef2aSThomas Huth tcg_temp_free(t0); 1651b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1652b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1653fcf5ef2aSThomas Huth } 1654fcf5ef2aSThomas Huth 1655fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1656fcf5ef2aSThomas Huth { 1657fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1658fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1659fcf5ef2aSThomas Huth tcg_temp_free(t0); 1660fcf5ef2aSThomas Huth } 1661fcf5ef2aSThomas Huth 1662fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1663fcf5ef2aSThomas Huth { 1664fcf5ef2aSThomas Huth TCGv t0, t1; 1665fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1666fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1667fcf5ef2aSThomas Huth if (s) { 1668fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1669fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1670fcf5ef2aSThomas Huth } else { 1671fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1672fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1673fcf5ef2aSThomas Huth } 1674fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1675fcf5ef2aSThomas Huth tcg_temp_free(t1); 1676fcf5ef2aSThomas Huth tcg_temp_free(t0); 1677fcf5ef2aSThomas Huth } 1678fcf5ef2aSThomas Huth 1679fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1680fcf5ef2aSThomas Huth { 1681fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1682fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1683fcf5ef2aSThomas Huth tcg_temp_free(t0); 1684fcf5ef2aSThomas Huth } 1685fcf5ef2aSThomas Huth 1686fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1687fcf5ef2aSThomas Huth { 1688fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1689fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1690fcf5ef2aSThomas Huth } else { 1691fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1692fcf5ef2aSThomas Huth } 1693fcf5ef2aSThomas Huth } 1694fcf5ef2aSThomas Huth 1695fcf5ef2aSThomas Huth /* cmp */ 1696fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1697fcf5ef2aSThomas Huth { 1698fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1699fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1700fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1701fcf5ef2aSThomas Huth } else { 1702fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1703fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1704fcf5ef2aSThomas Huth } 1705fcf5ef2aSThomas Huth } 1706fcf5ef2aSThomas Huth 1707fcf5ef2aSThomas Huth /* cmpi */ 1708fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1709fcf5ef2aSThomas Huth { 1710fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1711fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1712fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1713fcf5ef2aSThomas Huth } else { 1714fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1715fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1716fcf5ef2aSThomas Huth } 1717fcf5ef2aSThomas Huth } 1718fcf5ef2aSThomas Huth 1719fcf5ef2aSThomas Huth /* cmpl */ 1720fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1721fcf5ef2aSThomas Huth { 1722fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1723fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1724fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1725fcf5ef2aSThomas Huth } else { 1726fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1727fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1728fcf5ef2aSThomas Huth } 1729fcf5ef2aSThomas Huth } 1730fcf5ef2aSThomas Huth 1731fcf5ef2aSThomas Huth /* cmpli */ 1732fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1733fcf5ef2aSThomas Huth { 1734fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1735fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1736fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1737fcf5ef2aSThomas Huth } else { 1738fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1739fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1740fcf5ef2aSThomas Huth } 1741fcf5ef2aSThomas Huth } 1742fcf5ef2aSThomas Huth 1743fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1744fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1745fcf5ef2aSThomas Huth { 1746fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1747fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1748fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1749fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1750fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1751fcf5ef2aSThomas Huth 1752fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1753fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1754fcf5ef2aSThomas Huth 1755fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1756fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1757fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1758fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1759fcf5ef2aSThomas Huth 1760fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1761fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1762fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1763fcf5ef2aSThomas Huth 1764fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1765fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1766fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1767fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1768fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1769fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1770fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1771fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1772fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1773fcf5ef2aSThomas Huth } 1774efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1775fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1776fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1777fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1778fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1779fcf5ef2aSThomas Huth } 1780fcf5ef2aSThomas Huth 1781fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1782fcf5ef2aSThomas Huth /* cmpeqb */ 1783fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1784fcf5ef2aSThomas Huth { 1785fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1786fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1787fcf5ef2aSThomas Huth } 1788fcf5ef2aSThomas Huth #endif 1789fcf5ef2aSThomas Huth 1790fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1791fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1792fcf5ef2aSThomas Huth { 1793fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1794fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1795fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1796fcf5ef2aSThomas Huth TCGv zr; 1797fcf5ef2aSThomas Huth 1798fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1799fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1800fcf5ef2aSThomas Huth 1801fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1802fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1803fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1804fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1805fcf5ef2aSThomas Huth tcg_temp_free(zr); 1806fcf5ef2aSThomas Huth tcg_temp_free(t0); 1807fcf5ef2aSThomas Huth } 1808fcf5ef2aSThomas Huth 1809fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1810fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1811fcf5ef2aSThomas Huth { 1812fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1813fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1814fcf5ef2aSThomas Huth } 1815fcf5ef2aSThomas Huth 1816fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1817fcf5ef2aSThomas Huth 1818fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1819fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1820fcf5ef2aSThomas Huth { 1821fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1822fcf5ef2aSThomas Huth 1823fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1824fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1825fcf5ef2aSThomas Huth if (sub) { 1826fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1827fcf5ef2aSThomas Huth } else { 1828fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1829fcf5ef2aSThomas Huth } 1830fcf5ef2aSThomas Huth tcg_temp_free(t0); 1831fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1832dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1833dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1834dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1835fcf5ef2aSThomas Huth } 1836dc0ad844SNikunj A Dadhania } else { 1837dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1838dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1839dc0ad844SNikunj A Dadhania } 184038a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1841dc0ad844SNikunj A Dadhania } 1842fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1843fcf5ef2aSThomas Huth } 1844fcf5ef2aSThomas Huth 18456b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 18466b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 18474c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 18486b10d008SNikunj A Dadhania { 18496b10d008SNikunj A Dadhania TCGv t0; 18506b10d008SNikunj A Dadhania 18516b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 18526b10d008SNikunj A Dadhania return; 18536b10d008SNikunj A Dadhania } 18546b10d008SNikunj A Dadhania 18556b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 185633903d0aSNikunj A Dadhania if (sub) { 185733903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 185833903d0aSNikunj A Dadhania } else { 18596b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 186033903d0aSNikunj A Dadhania } 18616b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 18624c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 18636b10d008SNikunj A Dadhania tcg_temp_free(t0); 18646b10d008SNikunj A Dadhania } 18656b10d008SNikunj A Dadhania 1866fcf5ef2aSThomas Huth /* Common add function */ 1867fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 18684c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 18694c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1870fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1871fcf5ef2aSThomas Huth { 1872fcf5ef2aSThomas Huth TCGv t0 = ret; 1873fcf5ef2aSThomas Huth 1874fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1875fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1876fcf5ef2aSThomas Huth } 1877fcf5ef2aSThomas Huth 1878fcf5ef2aSThomas Huth if (compute_ca) { 1879fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1880efe843d8SDavid Gibson /* 1881efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1882efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1883efe843d8SDavid Gibson * produce the carry into bit 32. 1884efe843d8SDavid Gibson */ 1885fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1886fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1887fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1888fcf5ef2aSThomas Huth if (add_ca) { 18894c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1890fcf5ef2aSThomas Huth } 18914c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1892fcf5ef2aSThomas Huth tcg_temp_free(t1); 18934c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 18946b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 18954c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 18966b10d008SNikunj A Dadhania } 1897fcf5ef2aSThomas Huth } else { 1898fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1899fcf5ef2aSThomas Huth if (add_ca) { 19004c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 19014c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1902fcf5ef2aSThomas Huth } else { 19034c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1904fcf5ef2aSThomas Huth } 19054c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1906fcf5ef2aSThomas Huth tcg_temp_free(zero); 1907fcf5ef2aSThomas Huth } 1908fcf5ef2aSThomas Huth } else { 1909fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1910fcf5ef2aSThomas Huth if (add_ca) { 19114c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1912fcf5ef2aSThomas Huth } 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth 1915fcf5ef2aSThomas Huth if (compute_ov) { 1916fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1917fcf5ef2aSThomas Huth } 1918fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1919fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1920fcf5ef2aSThomas Huth } 1921fcf5ef2aSThomas Huth 192211f4e8f8SRichard Henderson if (t0 != ret) { 1923fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1924fcf5ef2aSThomas Huth tcg_temp_free(t0); 1925fcf5ef2aSThomas Huth } 1926fcf5ef2aSThomas Huth } 1927fcf5ef2aSThomas Huth /* Add functions with two operands */ 19284c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1929fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1930fcf5ef2aSThomas Huth { \ 1931fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1932fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 19334c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1934fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1935fcf5ef2aSThomas Huth } 1936fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 19374c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1938fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1939fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1940fcf5ef2aSThomas Huth { \ 1941fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1942fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1943fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 19444c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1945fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1946fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1947fcf5ef2aSThomas Huth } 1948fcf5ef2aSThomas Huth 1949fcf5ef2aSThomas Huth /* add add. addo addo. */ 19504c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 19514c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1952fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 19534c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 19544c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1955fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 19564c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 19574c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1958fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 19594c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 19604c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 19614c5920afSSuraj Jitindar Singh /* addex */ 19624c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1963fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 19644c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 19654c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1966fcf5ef2aSThomas Huth /* addi */ 1967fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 1968fcf5ef2aSThomas Huth { 1969fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1970fcf5ef2aSThomas Huth 1971fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1972fcf5ef2aSThomas Huth /* li case */ 1973fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 1974fcf5ef2aSThomas Huth } else { 1975fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1976fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 1977fcf5ef2aSThomas Huth } 1978fcf5ef2aSThomas Huth } 1979fcf5ef2aSThomas Huth /* addic addic.*/ 1980fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1981fcf5ef2aSThomas Huth { 1982fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1983fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 19844c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1985fcf5ef2aSThomas Huth tcg_temp_free(c); 1986fcf5ef2aSThomas Huth } 1987fcf5ef2aSThomas Huth 1988fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1989fcf5ef2aSThomas Huth { 1990fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1991fcf5ef2aSThomas Huth } 1992fcf5ef2aSThomas Huth 1993fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1994fcf5ef2aSThomas Huth { 1995fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1996fcf5ef2aSThomas Huth } 1997fcf5ef2aSThomas Huth 1998fcf5ef2aSThomas Huth /* addis */ 1999fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 2000fcf5ef2aSThomas Huth { 2001fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2002fcf5ef2aSThomas Huth 2003fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2004fcf5ef2aSThomas Huth /* lis case */ 2005fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 2006fcf5ef2aSThomas Huth } else { 2007fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 2008fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 2009fcf5ef2aSThomas Huth } 2010fcf5ef2aSThomas Huth } 2011fcf5ef2aSThomas Huth 2012fcf5ef2aSThomas Huth /* addpcis */ 2013fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 2014fcf5ef2aSThomas Huth { 2015fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 2016fcf5ef2aSThomas Huth 2017b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 2018fcf5ef2aSThomas Huth } 2019fcf5ef2aSThomas Huth 2020fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 2021fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2022fcf5ef2aSThomas Huth { 2023fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2024fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2025fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2026fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2027fcf5ef2aSThomas Huth 2028fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2029fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2030fcf5ef2aSThomas Huth if (sign) { 2031fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2032fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2033fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2034fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2035fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2036fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2037fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2038fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 2039fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2040fcf5ef2aSThomas Huth } else { 2041fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 2042fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2043fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2044fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 2045fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2046fcf5ef2aSThomas Huth } 2047fcf5ef2aSThomas Huth if (compute_ov) { 2048fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 2049c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2050c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 2051c44027ffSNikunj A Dadhania } 2052fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2053fcf5ef2aSThomas Huth } 2054fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2055fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2056fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2057fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2058fcf5ef2aSThomas Huth 2059efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2060fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2061fcf5ef2aSThomas Huth } 2062efe843d8SDavid Gibson } 2063fcf5ef2aSThomas Huth /* Div functions */ 2064fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 2065fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2066fcf5ef2aSThomas Huth { \ 2067fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2068fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2069fcf5ef2aSThomas Huth sign, compute_ov); \ 2070fcf5ef2aSThomas Huth } 2071fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 2072fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 2073fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 2074fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 2075fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 2076fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 2077fcf5ef2aSThomas Huth 2078fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 2079fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 2080fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 2081fcf5ef2aSThomas Huth { \ 2082fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 2083fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 2084fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 2085fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 2086fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 2087fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 2088fcf5ef2aSThomas Huth } \ 2089fcf5ef2aSThomas Huth } 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 2092fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 2093fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 2094fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 2095fcf5ef2aSThomas Huth 2096fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2097fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 2098fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2099fcf5ef2aSThomas Huth { 2100fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2101fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2102fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2103fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2104fcf5ef2aSThomas Huth 2105fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2106fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2107fcf5ef2aSThomas Huth if (sign) { 2108fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2109fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2110fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2111fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2112fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2113fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2114fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2115fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 2116fcf5ef2aSThomas Huth } else { 2117fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 2118fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2119fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2120fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 2121fcf5ef2aSThomas Huth } 2122fcf5ef2aSThomas Huth if (compute_ov) { 2123fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 2124c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2125c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 2126c44027ffSNikunj A Dadhania } 2127fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2128fcf5ef2aSThomas Huth } 2129fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2130fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2131fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2132fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2133fcf5ef2aSThomas Huth 2134efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2135fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2136fcf5ef2aSThomas Huth } 2137efe843d8SDavid Gibson } 2138fcf5ef2aSThomas Huth 2139fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 2140fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2141fcf5ef2aSThomas Huth { \ 2142fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2143fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2144fcf5ef2aSThomas Huth sign, compute_ov); \ 2145fcf5ef2aSThomas Huth } 2146c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 2147fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 2148fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 2149c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 2150fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 2151fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 2152fcf5ef2aSThomas Huth 2153fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 2154fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 2155fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 2156fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 2157fcf5ef2aSThomas Huth #endif 2158fcf5ef2aSThomas Huth 2159fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 2160fcf5ef2aSThomas Huth TCGv arg2, int sign) 2161fcf5ef2aSThomas Huth { 2162fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2163fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2164fcf5ef2aSThomas Huth 2165fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2166fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2167fcf5ef2aSThomas Huth if (sign) { 2168fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2169fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2170fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2171fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2172fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2173fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2174fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2175fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2176fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2177fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 2178fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 2179fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2180fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2181fcf5ef2aSThomas Huth } else { 2182fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 2183fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 2184fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 2185fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 2186fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2187fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2188fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2189fcf5ef2aSThomas Huth } 2190fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2191fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2192fcf5ef2aSThomas Huth } 2193fcf5ef2aSThomas Huth 2194fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 2195fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2196fcf5ef2aSThomas Huth { \ 2197fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2198fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2199fcf5ef2aSThomas Huth sign); \ 2200fcf5ef2aSThomas Huth } 2201fcf5ef2aSThomas Huth 2202fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 2203fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 2204fcf5ef2aSThomas Huth 2205fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2206fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 2207fcf5ef2aSThomas Huth TCGv arg2, int sign) 2208fcf5ef2aSThomas Huth { 2209fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2210fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2211fcf5ef2aSThomas Huth 2212fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2213fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2214fcf5ef2aSThomas Huth if (sign) { 2215fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2216fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2217fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2218fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2219fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2220fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2221fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2222fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2223fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2224fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 2225fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2226fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2227fcf5ef2aSThomas Huth } else { 2228fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 2229fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2230fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2231fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2232fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2233fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2234fcf5ef2aSThomas Huth } 2235fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2236fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2237fcf5ef2aSThomas Huth } 2238fcf5ef2aSThomas Huth 2239fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2240fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2241fcf5ef2aSThomas Huth { \ 2242fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2243fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2244fcf5ef2aSThomas Huth sign); \ 2245fcf5ef2aSThomas Huth } 2246fcf5ef2aSThomas Huth 2247fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2248fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2249fcf5ef2aSThomas Huth #endif 2250fcf5ef2aSThomas Huth 2251fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2252fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2253fcf5ef2aSThomas Huth { 2254fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2255fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2256fcf5ef2aSThomas Huth 2257fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2258fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2259fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2260fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2261fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2262fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2263efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2264fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2265fcf5ef2aSThomas Huth } 2266efe843d8SDavid Gibson } 2267fcf5ef2aSThomas Huth 2268fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2269fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2270fcf5ef2aSThomas Huth { 2271fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2272fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2273fcf5ef2aSThomas Huth 2274fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2275fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2276fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2277fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2278fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2279fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2280efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2281fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2282fcf5ef2aSThomas Huth } 2283efe843d8SDavid Gibson } 2284fcf5ef2aSThomas Huth 2285fcf5ef2aSThomas Huth /* mullw mullw. */ 2286fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2287fcf5ef2aSThomas Huth { 2288fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2289fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2290fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2291fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2292fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2293fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2294fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2295fcf5ef2aSThomas Huth tcg_temp_free(t0); 2296fcf5ef2aSThomas Huth tcg_temp_free(t1); 2297fcf5ef2aSThomas Huth #else 2298fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2299fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2300fcf5ef2aSThomas Huth #endif 2301efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2302fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2303fcf5ef2aSThomas Huth } 2304efe843d8SDavid Gibson } 2305fcf5ef2aSThomas Huth 2306fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2307fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2308fcf5ef2aSThomas Huth { 2309fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2310fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2311fcf5ef2aSThomas Huth 2312fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2313fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2314fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2315fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2316fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2317fcf5ef2aSThomas Huth #else 2318fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2319fcf5ef2aSThomas Huth #endif 2320fcf5ef2aSThomas Huth 2321fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2322fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2323fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 232461aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 232561aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 232661aa9a69SNikunj A Dadhania } 2327fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2328fcf5ef2aSThomas Huth 2329fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2330fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2331efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2332fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2333fcf5ef2aSThomas Huth } 2334efe843d8SDavid Gibson } 2335fcf5ef2aSThomas Huth 2336fcf5ef2aSThomas Huth /* mulli */ 2337fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2338fcf5ef2aSThomas Huth { 2339fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2340fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2341fcf5ef2aSThomas Huth } 2342fcf5ef2aSThomas Huth 2343fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2344fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2345fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2346fcf5ef2aSThomas Huth { 2347fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2348fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2349fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2350fcf5ef2aSThomas Huth tcg_temp_free(lo); 2351fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2352fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2353fcf5ef2aSThomas Huth } 2354fcf5ef2aSThomas Huth } 2355fcf5ef2aSThomas Huth 2356fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2357fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2358fcf5ef2aSThomas Huth { 2359fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2360fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2361fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2362fcf5ef2aSThomas Huth tcg_temp_free(lo); 2363fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2364fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2365fcf5ef2aSThomas Huth } 2366fcf5ef2aSThomas Huth } 2367fcf5ef2aSThomas Huth 2368fcf5ef2aSThomas Huth /* mulld mulld. */ 2369fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2370fcf5ef2aSThomas Huth { 2371fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2372fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2373efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2374fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2375fcf5ef2aSThomas Huth } 2376efe843d8SDavid Gibson } 2377fcf5ef2aSThomas Huth 2378fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2379fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2380fcf5ef2aSThomas Huth { 2381fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2382fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2383fcf5ef2aSThomas Huth 2384fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2385fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2386fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2387fcf5ef2aSThomas Huth 2388fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2389fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 239061aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 239161aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 239261aa9a69SNikunj A Dadhania } 2393fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2394fcf5ef2aSThomas Huth 2395fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2396fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2397fcf5ef2aSThomas Huth 2398fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2399fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2400fcf5ef2aSThomas Huth } 2401fcf5ef2aSThomas Huth } 2402fcf5ef2aSThomas Huth #endif 2403fcf5ef2aSThomas Huth 2404fcf5ef2aSThomas Huth /* Common subf function */ 2405fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2406fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2407fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2408fcf5ef2aSThomas Huth { 2409fcf5ef2aSThomas Huth TCGv t0 = ret; 2410fcf5ef2aSThomas Huth 2411fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2412fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2413fcf5ef2aSThomas Huth } 2414fcf5ef2aSThomas Huth 2415fcf5ef2aSThomas Huth if (compute_ca) { 2416fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2417fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2418efe843d8SDavid Gibson /* 2419efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2420efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2421efe843d8SDavid Gibson * produce the carry into bit 32. 2422efe843d8SDavid Gibson */ 2423fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2424fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2425fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2426fcf5ef2aSThomas Huth if (add_ca) { 2427fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2428fcf5ef2aSThomas Huth } else { 2429fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2430fcf5ef2aSThomas Huth } 2431fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2432fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2433fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2434fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2435fcf5ef2aSThomas Huth tcg_temp_free(t1); 2436e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 243733903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 243833903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 243933903d0aSNikunj A Dadhania } 2440fcf5ef2aSThomas Huth } else if (add_ca) { 2441fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2442fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2443fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2444fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2445fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 24464c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2447fcf5ef2aSThomas Huth tcg_temp_free(zero); 2448fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2449fcf5ef2aSThomas Huth } else { 2450fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2451fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 24524c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2453fcf5ef2aSThomas Huth } 2454fcf5ef2aSThomas Huth } else if (add_ca) { 2455efe843d8SDavid Gibson /* 2456efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2457efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2458efe843d8SDavid Gibson */ 2459fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2460fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2461fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2462fcf5ef2aSThomas Huth } else { 2463fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2464fcf5ef2aSThomas Huth } 2465fcf5ef2aSThomas Huth 2466fcf5ef2aSThomas Huth if (compute_ov) { 2467fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2468fcf5ef2aSThomas Huth } 2469fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2470fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2471fcf5ef2aSThomas Huth } 2472fcf5ef2aSThomas Huth 247311f4e8f8SRichard Henderson if (t0 != ret) { 2474fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2475fcf5ef2aSThomas Huth tcg_temp_free(t0); 2476fcf5ef2aSThomas Huth } 2477fcf5ef2aSThomas Huth } 2478fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2479fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2480fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2481fcf5ef2aSThomas Huth { \ 2482fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2483fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2484fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2485fcf5ef2aSThomas Huth } 2486fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2487fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2488fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2489fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2490fcf5ef2aSThomas Huth { \ 2491fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2492fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2493fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2494fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2495fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2496fcf5ef2aSThomas Huth } 2497fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2498fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2499fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2500fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2501fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2502fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2503fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2504fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2505fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2506fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2507fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2508fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2509fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2510fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2511fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2512fcf5ef2aSThomas Huth 2513fcf5ef2aSThomas Huth /* subfic */ 2514fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2515fcf5ef2aSThomas Huth { 2516fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2517fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2518fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2519fcf5ef2aSThomas Huth tcg_temp_free(c); 2520fcf5ef2aSThomas Huth } 2521fcf5ef2aSThomas Huth 2522fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2523fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2524fcf5ef2aSThomas Huth { 2525fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2526fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2527fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2528fcf5ef2aSThomas Huth tcg_temp_free(zero); 2529fcf5ef2aSThomas Huth } 2530fcf5ef2aSThomas Huth 2531fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2532fcf5ef2aSThomas Huth { 25331480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 25341480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 25351480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 25361480d71cSNikunj A Dadhania } 2537fcf5ef2aSThomas Huth } 2538fcf5ef2aSThomas Huth 2539fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2540fcf5ef2aSThomas Huth { 2541fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2542fcf5ef2aSThomas Huth } 2543fcf5ef2aSThomas Huth 2544fcf5ef2aSThomas Huth /*** Integer logical ***/ 2545fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2546fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2547fcf5ef2aSThomas Huth { \ 2548fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2549fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2550fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2551fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2552fcf5ef2aSThomas Huth } 2553fcf5ef2aSThomas Huth 2554fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2555fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2556fcf5ef2aSThomas Huth { \ 2557fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2558fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2559fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2560fcf5ef2aSThomas Huth } 2561fcf5ef2aSThomas Huth 2562fcf5ef2aSThomas Huth /* and & and. */ 2563fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2564fcf5ef2aSThomas Huth /* andc & andc. */ 2565fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2566fcf5ef2aSThomas Huth 2567fcf5ef2aSThomas Huth /* andi. */ 2568fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2569fcf5ef2aSThomas Huth { 2570efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2571efe843d8SDavid Gibson UIMM(ctx->opcode)); 2572fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2573fcf5ef2aSThomas Huth } 2574fcf5ef2aSThomas Huth 2575fcf5ef2aSThomas Huth /* andis. */ 2576fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2577fcf5ef2aSThomas Huth { 2578efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2579efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2580fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2581fcf5ef2aSThomas Huth } 2582fcf5ef2aSThomas Huth 2583fcf5ef2aSThomas Huth /* cntlzw */ 2584fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2585fcf5ef2aSThomas Huth { 25869b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 25879b8514e5SRichard Henderson 25889b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 25899b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 25909b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 25919b8514e5SRichard Henderson tcg_temp_free_i32(t); 25929b8514e5SRichard Henderson 2593efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2594fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2595fcf5ef2aSThomas Huth } 2596efe843d8SDavid Gibson } 2597fcf5ef2aSThomas Huth 2598fcf5ef2aSThomas Huth /* cnttzw */ 2599fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2600fcf5ef2aSThomas Huth { 26019b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 26029b8514e5SRichard Henderson 26039b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 26049b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 26059b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 26069b8514e5SRichard Henderson tcg_temp_free_i32(t); 26079b8514e5SRichard Henderson 2608fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2609fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2610fcf5ef2aSThomas Huth } 2611fcf5ef2aSThomas Huth } 2612fcf5ef2aSThomas Huth 2613fcf5ef2aSThomas Huth /* eqv & eqv. */ 2614fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2615fcf5ef2aSThomas Huth /* extsb & extsb. */ 2616fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2617fcf5ef2aSThomas Huth /* extsh & extsh. */ 2618fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2619fcf5ef2aSThomas Huth /* nand & nand. */ 2620fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2621fcf5ef2aSThomas Huth /* nor & nor. */ 2622fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2623fcf5ef2aSThomas Huth 2624fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2625fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2626fcf5ef2aSThomas Huth { 2627fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2628fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2629fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2630fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2631fcf5ef2aSThomas Huth 2632fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2633b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2634fcf5ef2aSThomas Huth } 2635fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2636fcf5ef2aSThomas Huth 2637fcf5ef2aSThomas Huth /* or & or. */ 2638fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2639fcf5ef2aSThomas Huth { 2640fcf5ef2aSThomas Huth int rs, ra, rb; 2641fcf5ef2aSThomas Huth 2642fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2643fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2644fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2645fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2646fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2647efe843d8SDavid Gibson if (rs != rb) { 2648fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2649efe843d8SDavid Gibson } else { 2650fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2651efe843d8SDavid Gibson } 2652efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2653fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2654efe843d8SDavid Gibson } 2655fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2656fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2657fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2658fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2659fcf5ef2aSThomas Huth int prio = 0; 2660fcf5ef2aSThomas Huth 2661fcf5ef2aSThomas Huth switch (rs) { 2662fcf5ef2aSThomas Huth case 1: 2663fcf5ef2aSThomas Huth /* Set process priority to low */ 2664fcf5ef2aSThomas Huth prio = 2; 2665fcf5ef2aSThomas Huth break; 2666fcf5ef2aSThomas Huth case 6: 2667fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2668fcf5ef2aSThomas Huth prio = 3; 2669fcf5ef2aSThomas Huth break; 2670fcf5ef2aSThomas Huth case 2: 2671fcf5ef2aSThomas Huth /* Set process priority to normal */ 2672fcf5ef2aSThomas Huth prio = 4; 2673fcf5ef2aSThomas Huth break; 2674fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2675fcf5ef2aSThomas Huth case 31: 2676fcf5ef2aSThomas Huth if (!ctx->pr) { 2677fcf5ef2aSThomas Huth /* Set process priority to very low */ 2678fcf5ef2aSThomas Huth prio = 1; 2679fcf5ef2aSThomas Huth } 2680fcf5ef2aSThomas Huth break; 2681fcf5ef2aSThomas Huth case 5: 2682fcf5ef2aSThomas Huth if (!ctx->pr) { 2683fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2684fcf5ef2aSThomas Huth prio = 5; 2685fcf5ef2aSThomas Huth } 2686fcf5ef2aSThomas Huth break; 2687fcf5ef2aSThomas Huth case 3: 2688fcf5ef2aSThomas Huth if (!ctx->pr) { 2689fcf5ef2aSThomas Huth /* Set process priority to high */ 2690fcf5ef2aSThomas Huth prio = 6; 2691fcf5ef2aSThomas Huth } 2692fcf5ef2aSThomas Huth break; 2693fcf5ef2aSThomas Huth case 7: 2694fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2695fcf5ef2aSThomas Huth /* Set process priority to very high */ 2696fcf5ef2aSThomas Huth prio = 7; 2697fcf5ef2aSThomas Huth } 2698fcf5ef2aSThomas Huth break; 2699fcf5ef2aSThomas Huth #endif 2700fcf5ef2aSThomas Huth default: 2701fcf5ef2aSThomas Huth break; 2702fcf5ef2aSThomas Huth } 2703fcf5ef2aSThomas Huth if (prio) { 2704fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2705fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2706fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2707fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2708fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2709fcf5ef2aSThomas Huth tcg_temp_free(t0); 2710fcf5ef2aSThomas Huth } 2711fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2712efe843d8SDavid Gibson /* 2713efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2714efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2715efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2716efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2717fcf5ef2aSThomas Huth */ 2718fcf5ef2aSThomas Huth gen_pause(ctx); 2719fcf5ef2aSThomas Huth #endif 2720fcf5ef2aSThomas Huth #endif 2721fcf5ef2aSThomas Huth } 2722fcf5ef2aSThomas Huth } 2723fcf5ef2aSThomas Huth /* orc & orc. */ 2724fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2725fcf5ef2aSThomas Huth 2726fcf5ef2aSThomas Huth /* xor & xor. */ 2727fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2728fcf5ef2aSThomas Huth { 2729fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2730efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2731efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2732efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2733efe843d8SDavid Gibson } else { 2734fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2735efe843d8SDavid Gibson } 2736efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2737fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2738fcf5ef2aSThomas Huth } 2739efe843d8SDavid Gibson } 2740fcf5ef2aSThomas Huth 2741fcf5ef2aSThomas Huth /* ori */ 2742fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2743fcf5ef2aSThomas Huth { 2744fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2745fcf5ef2aSThomas Huth 2746fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2747fcf5ef2aSThomas Huth return; 2748fcf5ef2aSThomas Huth } 2749fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2750fcf5ef2aSThomas Huth } 2751fcf5ef2aSThomas Huth 2752fcf5ef2aSThomas Huth /* oris */ 2753fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2754fcf5ef2aSThomas Huth { 2755fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2756fcf5ef2aSThomas Huth 2757fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2758fcf5ef2aSThomas Huth /* NOP */ 2759fcf5ef2aSThomas Huth return; 2760fcf5ef2aSThomas Huth } 2761efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2762efe843d8SDavid Gibson uimm << 16); 2763fcf5ef2aSThomas Huth } 2764fcf5ef2aSThomas Huth 2765fcf5ef2aSThomas Huth /* xori */ 2766fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2767fcf5ef2aSThomas Huth { 2768fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2769fcf5ef2aSThomas Huth 2770fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2771fcf5ef2aSThomas Huth /* NOP */ 2772fcf5ef2aSThomas Huth return; 2773fcf5ef2aSThomas Huth } 2774fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2775fcf5ef2aSThomas Huth } 2776fcf5ef2aSThomas Huth 2777fcf5ef2aSThomas Huth /* xoris */ 2778fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2779fcf5ef2aSThomas Huth { 2780fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2781fcf5ef2aSThomas Huth 2782fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2783fcf5ef2aSThomas Huth /* NOP */ 2784fcf5ef2aSThomas Huth return; 2785fcf5ef2aSThomas Huth } 2786efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2787efe843d8SDavid Gibson uimm << 16); 2788fcf5ef2aSThomas Huth } 2789fcf5ef2aSThomas Huth 2790fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2791fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2792fcf5ef2aSThomas Huth { 2793fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2794fcf5ef2aSThomas Huth } 2795fcf5ef2aSThomas Huth 2796fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2797fcf5ef2aSThomas Huth { 279879770002SRichard Henderson #if defined(TARGET_PPC64) 2799fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 280079770002SRichard Henderson #else 280179770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 280279770002SRichard Henderson #endif 2803fcf5ef2aSThomas Huth } 2804fcf5ef2aSThomas Huth 2805fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2806fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2807fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2808fcf5ef2aSThomas Huth { 280979770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2810fcf5ef2aSThomas Huth } 2811fcf5ef2aSThomas Huth #endif 2812fcf5ef2aSThomas Huth 2813fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2814fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2815fcf5ef2aSThomas Huth { 2816fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2817fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2818fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2819fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2820fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2821fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2822fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2823fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2824fcf5ef2aSThomas Huth tcg_temp_free(t0); 2825fcf5ef2aSThomas Huth } 2826fcf5ef2aSThomas Huth 2827fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2828fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2829fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2830fcf5ef2aSThomas Huth { 2831fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2832fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2833fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2834fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2835fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2836fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2837fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2838fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2839fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2840fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2841fcf5ef2aSThomas Huth tcg_temp_free(t0); 2842fcf5ef2aSThomas Huth } 2843fcf5ef2aSThomas Huth #endif 2844fcf5ef2aSThomas Huth 2845fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2846fcf5ef2aSThomas Huth /* bpermd */ 2847fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2848fcf5ef2aSThomas Huth { 2849fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2850fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2851fcf5ef2aSThomas Huth } 2852fcf5ef2aSThomas Huth #endif 2853fcf5ef2aSThomas Huth 2854fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2855fcf5ef2aSThomas Huth /* extsw & extsw. */ 2856fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2857fcf5ef2aSThomas Huth 2858fcf5ef2aSThomas Huth /* cntlzd */ 2859fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2860fcf5ef2aSThomas Huth { 28619b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2862efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2863fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2864fcf5ef2aSThomas Huth } 2865efe843d8SDavid Gibson } 2866fcf5ef2aSThomas Huth 2867fcf5ef2aSThomas Huth /* cnttzd */ 2868fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2869fcf5ef2aSThomas Huth { 28709b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2871fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2872fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2873fcf5ef2aSThomas Huth } 2874fcf5ef2aSThomas Huth } 2875fcf5ef2aSThomas Huth 2876fcf5ef2aSThomas Huth /* darn */ 2877fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2878fcf5ef2aSThomas Huth { 2879fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2880fcf5ef2aSThomas Huth 28817e4357f6SRichard Henderson if (l > 2) { 28827e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 28837e4357f6SRichard Henderson } else { 28847e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28857e4357f6SRichard Henderson gen_io_start(); 28867e4357f6SRichard Henderson } 2887fcf5ef2aSThomas Huth if (l == 0) { 2888fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 28897e4357f6SRichard Henderson } else { 2890fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2891fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 28927e4357f6SRichard Henderson } 28937e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28947e4357f6SRichard Henderson gen_stop_exception(ctx); 28957e4357f6SRichard Henderson } 2896fcf5ef2aSThomas Huth } 2897fcf5ef2aSThomas Huth } 2898fcf5ef2aSThomas Huth #endif 2899fcf5ef2aSThomas Huth 2900fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2901fcf5ef2aSThomas Huth 2902fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2903fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2904fcf5ef2aSThomas Huth { 2905fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2906fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2907fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2908fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2909fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2910fcf5ef2aSThomas Huth 2911fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2912fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2913fcf5ef2aSThomas Huth } else { 2914fcf5ef2aSThomas Huth target_ulong mask; 2915c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2916fcf5ef2aSThomas Huth TCGv t1; 2917fcf5ef2aSThomas Huth 2918fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2919fcf5ef2aSThomas Huth mb += 32; 2920fcf5ef2aSThomas Huth me += 32; 2921fcf5ef2aSThomas Huth #endif 2922fcf5ef2aSThomas Huth mask = MASK(mb, me); 2923fcf5ef2aSThomas Huth 2924c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2925c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2926c4f6a4a3SDaniele Buono mask_in_32b = false; 2927c4f6a4a3SDaniele Buono } 2928c4f6a4a3SDaniele Buono #endif 2929fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2930c4f6a4a3SDaniele Buono if (mask_in_32b) { 2931fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2932fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2933fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2934fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2935fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2936fcf5ef2aSThomas Huth } else { 2937fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2938fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2939fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2940fcf5ef2aSThomas Huth #else 2941fcf5ef2aSThomas Huth g_assert_not_reached(); 2942fcf5ef2aSThomas Huth #endif 2943fcf5ef2aSThomas Huth } 2944fcf5ef2aSThomas Huth 2945fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2946fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2947fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2948fcf5ef2aSThomas Huth tcg_temp_free(t1); 2949fcf5ef2aSThomas Huth } 2950fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2951fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2952fcf5ef2aSThomas Huth } 2953fcf5ef2aSThomas Huth } 2954fcf5ef2aSThomas Huth 2955fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2956fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2957fcf5ef2aSThomas Huth { 2958fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2959fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 29607b4d326fSRichard Henderson int sh = SH(ctx->opcode); 29617b4d326fSRichard Henderson int mb = MB(ctx->opcode); 29627b4d326fSRichard Henderson int me = ME(ctx->opcode); 29637b4d326fSRichard Henderson int len = me - mb + 1; 29647b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2965fcf5ef2aSThomas Huth 29667b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 29677b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 29687b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 29697b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2970fcf5ef2aSThomas Huth } else { 2971fcf5ef2aSThomas Huth target_ulong mask; 2972c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2973fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2974fcf5ef2aSThomas Huth mb += 32; 2975fcf5ef2aSThomas Huth me += 32; 2976fcf5ef2aSThomas Huth #endif 2977fcf5ef2aSThomas Huth mask = MASK(mb, me); 2978c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2979c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2980c4f6a4a3SDaniele Buono mask_in_32b = false; 2981c4f6a4a3SDaniele Buono } 2982c4f6a4a3SDaniele Buono #endif 2983c4f6a4a3SDaniele Buono if (mask_in_32b) { 29847b4d326fSRichard Henderson if (sh == 0) { 29857b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 298694f040aaSVitaly Chikunov } else { 2987fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2988fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2989fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2990fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2991fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2992fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 299394f040aaSVitaly Chikunov } 2994fcf5ef2aSThomas Huth } else { 2995fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2996fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2997fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2998fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2999fcf5ef2aSThomas Huth #else 3000fcf5ef2aSThomas Huth g_assert_not_reached(); 3001fcf5ef2aSThomas Huth #endif 3002fcf5ef2aSThomas Huth } 3003fcf5ef2aSThomas Huth } 3004fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3005fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3006fcf5ef2aSThomas Huth } 3007fcf5ef2aSThomas Huth } 3008fcf5ef2aSThomas Huth 3009fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 3010fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 3011fcf5ef2aSThomas Huth { 3012fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3013fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3014fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3015fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 3016fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 3017fcf5ef2aSThomas Huth target_ulong mask; 3018c4f6a4a3SDaniele Buono bool mask_in_32b = true; 3019fcf5ef2aSThomas Huth 3020fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3021fcf5ef2aSThomas Huth mb += 32; 3022fcf5ef2aSThomas Huth me += 32; 3023fcf5ef2aSThomas Huth #endif 3024fcf5ef2aSThomas Huth mask = MASK(mb, me); 3025fcf5ef2aSThomas Huth 3026c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 3027c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 3028c4f6a4a3SDaniele Buono mask_in_32b = false; 3029c4f6a4a3SDaniele Buono } 3030c4f6a4a3SDaniele Buono #endif 3031c4f6a4a3SDaniele Buono if (mask_in_32b) { 3032fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3033fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3034fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 3035fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 3036fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 3037fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 3038fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 3039fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3040fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3041fcf5ef2aSThomas Huth } else { 3042fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3043fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 3044fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 3045fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 3046fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 3047fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 3048fcf5ef2aSThomas Huth #else 3049fcf5ef2aSThomas Huth g_assert_not_reached(); 3050fcf5ef2aSThomas Huth #endif 3051fcf5ef2aSThomas Huth } 3052fcf5ef2aSThomas Huth 3053fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 3054fcf5ef2aSThomas Huth 3055fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3056fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3057fcf5ef2aSThomas Huth } 3058fcf5ef2aSThomas Huth } 3059fcf5ef2aSThomas Huth 3060fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3061fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 3062fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3063fcf5ef2aSThomas Huth { \ 3064fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 3065fcf5ef2aSThomas Huth } \ 3066fcf5ef2aSThomas Huth \ 3067fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3068fcf5ef2aSThomas Huth { \ 3069fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 3070fcf5ef2aSThomas Huth } 3071fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 3072fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3073fcf5ef2aSThomas Huth { \ 3074fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 3075fcf5ef2aSThomas Huth } \ 3076fcf5ef2aSThomas Huth \ 3077fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3078fcf5ef2aSThomas Huth { \ 3079fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 3080fcf5ef2aSThomas Huth } \ 3081fcf5ef2aSThomas Huth \ 3082fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 3083fcf5ef2aSThomas Huth { \ 3084fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 3085fcf5ef2aSThomas Huth } \ 3086fcf5ef2aSThomas Huth \ 3087fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 3088fcf5ef2aSThomas Huth { \ 3089fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 3090fcf5ef2aSThomas Huth } 3091fcf5ef2aSThomas Huth 3092fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 3093fcf5ef2aSThomas Huth { 3094fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3095fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 30967b4d326fSRichard Henderson int len = me - mb + 1; 30977b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 3098fcf5ef2aSThomas Huth 30997b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 31007b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 31017b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 31027b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 3103fcf5ef2aSThomas Huth } else { 3104fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 3105fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3106fcf5ef2aSThomas Huth } 3107fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3108fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3109fcf5ef2aSThomas Huth } 3110fcf5ef2aSThomas Huth } 3111fcf5ef2aSThomas Huth 3112fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 3113fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 3114fcf5ef2aSThomas Huth { 3115fcf5ef2aSThomas Huth uint32_t sh, mb; 3116fcf5ef2aSThomas Huth 3117fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3118fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3119fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 3120fcf5ef2aSThomas Huth } 3121fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 3122fcf5ef2aSThomas Huth 3123fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 3124fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 3125fcf5ef2aSThomas Huth { 3126fcf5ef2aSThomas Huth uint32_t sh, me; 3127fcf5ef2aSThomas Huth 3128fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3129fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3130fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 3131fcf5ef2aSThomas Huth } 3132fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 3133fcf5ef2aSThomas Huth 3134fcf5ef2aSThomas Huth /* rldic - rldic. */ 3135fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 3136fcf5ef2aSThomas Huth { 3137fcf5ef2aSThomas Huth uint32_t sh, mb; 3138fcf5ef2aSThomas Huth 3139fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3140fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3141fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 3142fcf5ef2aSThomas Huth } 3143fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 3144fcf5ef2aSThomas Huth 3145fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 3146fcf5ef2aSThomas Huth { 3147fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3148fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3149fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3150fcf5ef2aSThomas Huth TCGv t0; 3151fcf5ef2aSThomas Huth 3152fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3153fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 3154fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 3155fcf5ef2aSThomas Huth tcg_temp_free(t0); 3156fcf5ef2aSThomas Huth 3157fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3158fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3159fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3160fcf5ef2aSThomas Huth } 3161fcf5ef2aSThomas Huth } 3162fcf5ef2aSThomas Huth 3163fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 3164fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 3165fcf5ef2aSThomas Huth { 3166fcf5ef2aSThomas Huth uint32_t mb; 3167fcf5ef2aSThomas Huth 3168fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3169fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 3170fcf5ef2aSThomas Huth } 3171fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 3172fcf5ef2aSThomas Huth 3173fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 3174fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 3175fcf5ef2aSThomas Huth { 3176fcf5ef2aSThomas Huth uint32_t me; 3177fcf5ef2aSThomas Huth 3178fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3179fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 3180fcf5ef2aSThomas Huth } 3181fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 3182fcf5ef2aSThomas Huth 3183fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 3184fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 3185fcf5ef2aSThomas Huth { 3186fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3187fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3188fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 3189fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 3190fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 3191fcf5ef2aSThomas Huth 3192fcf5ef2aSThomas Huth if (mb <= me) { 3193fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 3194fcf5ef2aSThomas Huth } else { 3195fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 3196fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3197fcf5ef2aSThomas Huth 3198fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 3199fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 3200fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 3201fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 3202fcf5ef2aSThomas Huth tcg_temp_free(t1); 3203fcf5ef2aSThomas Huth } 3204fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3205fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3206fcf5ef2aSThomas Huth } 3207fcf5ef2aSThomas Huth } 3208fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 3209fcf5ef2aSThomas Huth #endif 3210fcf5ef2aSThomas Huth 3211fcf5ef2aSThomas Huth /*** Integer shift ***/ 3212fcf5ef2aSThomas Huth 3213fcf5ef2aSThomas Huth /* slw & slw. */ 3214fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 3215fcf5ef2aSThomas Huth { 3216fcf5ef2aSThomas Huth TCGv t0, t1; 3217fcf5ef2aSThomas Huth 3218fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3219fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3220fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3221fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3222fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3223fcf5ef2aSThomas Huth #else 3224fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3225fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3226fcf5ef2aSThomas Huth #endif 3227fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3228fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3229fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3230fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3231fcf5ef2aSThomas Huth tcg_temp_free(t1); 3232fcf5ef2aSThomas Huth tcg_temp_free(t0); 3233fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 3234efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3235fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3236fcf5ef2aSThomas Huth } 3237efe843d8SDavid Gibson } 3238fcf5ef2aSThomas Huth 3239fcf5ef2aSThomas Huth /* sraw & sraw. */ 3240fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3241fcf5ef2aSThomas Huth { 3242fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3243fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3244efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3245fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3246fcf5ef2aSThomas Huth } 3247efe843d8SDavid Gibson } 3248fcf5ef2aSThomas Huth 3249fcf5ef2aSThomas Huth /* srawi & srawi. */ 3250fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3251fcf5ef2aSThomas Huth { 3252fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3253fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3254fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3255fcf5ef2aSThomas Huth if (sh == 0) { 3256fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3257fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3258af1c259fSSandipan Das if (is_isa300(ctx)) { 3259af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3260af1c259fSSandipan Das } 3261fcf5ef2aSThomas Huth } else { 3262fcf5ef2aSThomas Huth TCGv t0; 3263fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3264fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3265fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3266fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3267fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3268fcf5ef2aSThomas Huth tcg_temp_free(t0); 3269fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3270af1c259fSSandipan Das if (is_isa300(ctx)) { 3271af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3272af1c259fSSandipan Das } 3273fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3274fcf5ef2aSThomas Huth } 3275fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3276fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3277fcf5ef2aSThomas Huth } 3278fcf5ef2aSThomas Huth } 3279fcf5ef2aSThomas Huth 3280fcf5ef2aSThomas Huth /* srw & srw. */ 3281fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3282fcf5ef2aSThomas Huth { 3283fcf5ef2aSThomas Huth TCGv t0, t1; 3284fcf5ef2aSThomas Huth 3285fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3286fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3287fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3288fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3289fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3290fcf5ef2aSThomas Huth #else 3291fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3292fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3293fcf5ef2aSThomas Huth #endif 3294fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3295fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3296fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3297fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3298fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3299fcf5ef2aSThomas Huth tcg_temp_free(t1); 3300fcf5ef2aSThomas Huth tcg_temp_free(t0); 3301efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3302fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3303fcf5ef2aSThomas Huth } 3304efe843d8SDavid Gibson } 3305fcf5ef2aSThomas Huth 3306fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3307fcf5ef2aSThomas Huth /* sld & sld. */ 3308fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3309fcf5ef2aSThomas Huth { 3310fcf5ef2aSThomas Huth TCGv t0, t1; 3311fcf5ef2aSThomas Huth 3312fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3313fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3314fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3315fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3316fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3317fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3318fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3319fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3320fcf5ef2aSThomas Huth tcg_temp_free(t1); 3321fcf5ef2aSThomas Huth tcg_temp_free(t0); 3322efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3323fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3324fcf5ef2aSThomas Huth } 3325efe843d8SDavid Gibson } 3326fcf5ef2aSThomas Huth 3327fcf5ef2aSThomas Huth /* srad & srad. */ 3328fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3329fcf5ef2aSThomas Huth { 3330fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3331fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3332efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3333fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3334fcf5ef2aSThomas Huth } 3335efe843d8SDavid Gibson } 3336fcf5ef2aSThomas Huth /* sradi & sradi. */ 3337fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3338fcf5ef2aSThomas Huth { 3339fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3340fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3341fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3342fcf5ef2aSThomas Huth if (sh == 0) { 3343fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3344fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3345af1c259fSSandipan Das if (is_isa300(ctx)) { 3346af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3347af1c259fSSandipan Das } 3348fcf5ef2aSThomas Huth } else { 3349fcf5ef2aSThomas Huth TCGv t0; 3350fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3351fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3352fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3353fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3354fcf5ef2aSThomas Huth tcg_temp_free(t0); 3355fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3356af1c259fSSandipan Das if (is_isa300(ctx)) { 3357af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3358af1c259fSSandipan Das } 3359fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3360fcf5ef2aSThomas Huth } 3361fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3362fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3363fcf5ef2aSThomas Huth } 3364fcf5ef2aSThomas Huth } 3365fcf5ef2aSThomas Huth 3366fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3367fcf5ef2aSThomas Huth { 3368fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3369fcf5ef2aSThomas Huth } 3370fcf5ef2aSThomas Huth 3371fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3372fcf5ef2aSThomas Huth { 3373fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3374fcf5ef2aSThomas Huth } 3375fcf5ef2aSThomas Huth 3376fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3377fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3378fcf5ef2aSThomas Huth { 3379fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3380fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3381fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3382fcf5ef2aSThomas Huth 3383fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3384fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3385fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3386fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3387fcf5ef2aSThomas Huth } 3388fcf5ef2aSThomas Huth } 3389fcf5ef2aSThomas Huth 3390fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3391fcf5ef2aSThomas Huth { 3392fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3393fcf5ef2aSThomas Huth } 3394fcf5ef2aSThomas Huth 3395fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3396fcf5ef2aSThomas Huth { 3397fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3398fcf5ef2aSThomas Huth } 3399fcf5ef2aSThomas Huth 3400fcf5ef2aSThomas Huth /* srd & srd. */ 3401fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3402fcf5ef2aSThomas Huth { 3403fcf5ef2aSThomas Huth TCGv t0, t1; 3404fcf5ef2aSThomas Huth 3405fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3406fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3407fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3408fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3409fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3410fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3411fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3412fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3413fcf5ef2aSThomas Huth tcg_temp_free(t1); 3414fcf5ef2aSThomas Huth tcg_temp_free(t0); 3415efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3416fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3417fcf5ef2aSThomas Huth } 3418efe843d8SDavid Gibson } 3419fcf5ef2aSThomas Huth #endif 3420fcf5ef2aSThomas Huth 3421fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3422fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3423fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3424fcf5ef2aSThomas Huth target_long maskl) 3425fcf5ef2aSThomas Huth { 3426fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3427fcf5ef2aSThomas Huth 3428fcf5ef2aSThomas Huth simm &= ~maskl; 3429fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3430fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3431fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3432fcf5ef2aSThomas Huth } 3433fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3434fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3435fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3436fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3437fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3438fcf5ef2aSThomas Huth } 3439fcf5ef2aSThomas Huth } else { 3440fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3441fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3442fcf5ef2aSThomas Huth } else { 3443fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3444fcf5ef2aSThomas Huth } 3445fcf5ef2aSThomas Huth } 3446fcf5ef2aSThomas Huth } 3447fcf5ef2aSThomas Huth 3448fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3449fcf5ef2aSThomas Huth { 3450fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3451fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3452fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3453fcf5ef2aSThomas Huth } else { 3454fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3455fcf5ef2aSThomas Huth } 3456fcf5ef2aSThomas Huth } else { 3457fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3458fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3459fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3460fcf5ef2aSThomas Huth } 3461fcf5ef2aSThomas Huth } 3462fcf5ef2aSThomas Huth } 3463fcf5ef2aSThomas Huth 3464fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3465fcf5ef2aSThomas Huth { 3466fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3467fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3468fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3469fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3470fcf5ef2aSThomas Huth } else { 3471fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3472fcf5ef2aSThomas Huth } 3473fcf5ef2aSThomas Huth } 3474fcf5ef2aSThomas Huth 3475fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3476fcf5ef2aSThomas Huth target_long val) 3477fcf5ef2aSThomas Huth { 3478fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3479fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3480fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3481fcf5ef2aSThomas Huth } 3482fcf5ef2aSThomas Huth } 3483fcf5ef2aSThomas Huth 3484fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3485fcf5ef2aSThomas Huth { 3486fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3487fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3488fcf5ef2aSThomas Huth } 3489fcf5ef2aSThomas Huth 3490fcf5ef2aSThomas Huth /*** Integer load ***/ 3491fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3492fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3493fcf5ef2aSThomas Huth 3494fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3495fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3496fcf5ef2aSThomas Huth TCGv val, \ 3497fcf5ef2aSThomas Huth TCGv addr) \ 3498fcf5ef2aSThomas Huth { \ 3499fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3500fcf5ef2aSThomas Huth } 3501fcf5ef2aSThomas Huth 3502fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3503fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3504fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3505fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3506fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3507fcf5ef2aSThomas Huth 3508fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3509fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3510fcf5ef2aSThomas Huth 3511fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3512fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3513fcf5ef2aSThomas Huth TCGv_i64 val, \ 3514fcf5ef2aSThomas Huth TCGv addr) \ 3515fcf5ef2aSThomas Huth { \ 3516fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3517fcf5ef2aSThomas Huth } 3518fcf5ef2aSThomas Huth 3519fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3520fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3521fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3522fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3523fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3524fcf5ef2aSThomas Huth 3525fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3526fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3527fcf5ef2aSThomas Huth #endif 3528fcf5ef2aSThomas Huth 3529fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3530fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3531fcf5ef2aSThomas Huth TCGv val, \ 3532fcf5ef2aSThomas Huth TCGv addr) \ 3533fcf5ef2aSThomas Huth { \ 3534fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3535fcf5ef2aSThomas Huth } 3536fcf5ef2aSThomas Huth 3537fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3538fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3539fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3540fcf5ef2aSThomas Huth 3541fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3542fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3543fcf5ef2aSThomas Huth 3544fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3545fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3546fcf5ef2aSThomas Huth TCGv_i64 val, \ 3547fcf5ef2aSThomas Huth TCGv addr) \ 3548fcf5ef2aSThomas Huth { \ 3549fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3550fcf5ef2aSThomas Huth } 3551fcf5ef2aSThomas Huth 3552fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3553fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3554fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3555fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3556fcf5ef2aSThomas Huth 3557fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3558fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3559fcf5ef2aSThomas Huth #endif 3560fcf5ef2aSThomas Huth 3561fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 3562fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3563fcf5ef2aSThomas Huth { \ 3564fcf5ef2aSThomas Huth TCGv EA; \ 3565fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3566fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3567fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3568fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3569fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3570fcf5ef2aSThomas Huth } 3571fcf5ef2aSThomas Huth 3572fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 3573fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 3574fcf5ef2aSThomas Huth { \ 3575fcf5ef2aSThomas Huth TCGv EA; \ 3576fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3577fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3578fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3579fcf5ef2aSThomas Huth return; \ 3580fcf5ef2aSThomas Huth } \ 3581fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3582fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3583fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3584fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3585fcf5ef2aSThomas Huth else \ 3586fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3587fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3588fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3589fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3590fcf5ef2aSThomas Huth } 3591fcf5ef2aSThomas Huth 3592fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 3593fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3594fcf5ef2aSThomas Huth { \ 3595fcf5ef2aSThomas Huth TCGv EA; \ 3596fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3597fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3598fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3599fcf5ef2aSThomas Huth return; \ 3600fcf5ef2aSThomas Huth } \ 3601fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3602fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3603fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3604fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3605fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3606fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3607fcf5ef2aSThomas Huth } 3608fcf5ef2aSThomas Huth 3609fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3610fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3611fcf5ef2aSThomas Huth { \ 3612fcf5ef2aSThomas Huth TCGv EA; \ 3613fcf5ef2aSThomas Huth chk; \ 3614fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3615fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3616fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3617fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3618fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3619fcf5ef2aSThomas Huth } 3620fcf5ef2aSThomas Huth 3621fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3622fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3623fcf5ef2aSThomas Huth 3624fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3625fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3626fcf5ef2aSThomas Huth 3627fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 3628fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 3629fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 3630fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 3631fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 3632fcf5ef2aSThomas Huth 3633fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 3634fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 3635fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 3636fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 3637fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 3638fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 3639fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 3640fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 364150728199SRoman Kapl 364250728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 364350728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 364450728199SRoman Kapl { \ 364550728199SRoman Kapl TCGv EA; \ 364650728199SRoman Kapl CHK_SV; \ 364750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 364850728199SRoman Kapl EA = tcg_temp_new(); \ 364950728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 365050728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 365150728199SRoman Kapl tcg_temp_free(EA); \ 365250728199SRoman Kapl } 365350728199SRoman Kapl 365450728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 365550728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 365650728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 365750728199SRoman Kapl #if defined(TARGET_PPC64) 365850728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 365950728199SRoman Kapl #endif 366050728199SRoman Kapl 3661fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3662fcf5ef2aSThomas Huth /* lwaux */ 3663fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 3664fcf5ef2aSThomas Huth /* lwax */ 3665fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 3666fcf5ef2aSThomas Huth /* ldux */ 3667fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 3668fcf5ef2aSThomas Huth /* ldx */ 3669fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 3670fcf5ef2aSThomas Huth 3671fcf5ef2aSThomas Huth /* CI load/store variants */ 3672fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3673fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3674fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3675fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3676fcf5ef2aSThomas Huth 3677fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 3678fcf5ef2aSThomas Huth { 3679fcf5ef2aSThomas Huth TCGv EA; 3680fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3681fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 3682fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 3683fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3684fcf5ef2aSThomas Huth return; 3685fcf5ef2aSThomas Huth } 3686fcf5ef2aSThomas Huth } 3687fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3688fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3689fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3690fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 3691fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 3692fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3693fcf5ef2aSThomas Huth } else { 3694fcf5ef2aSThomas Huth /* ld - ldu */ 3695fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3696fcf5ef2aSThomas Huth } 3697efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3698fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3699efe843d8SDavid Gibson } 3700fcf5ef2aSThomas Huth tcg_temp_free(EA); 3701fcf5ef2aSThomas Huth } 3702fcf5ef2aSThomas Huth 3703fcf5ef2aSThomas Huth /* lq */ 3704fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3705fcf5ef2aSThomas Huth { 3706fcf5ef2aSThomas Huth int ra, rd; 370794bf2658SRichard Henderson TCGv EA, hi, lo; 3708fcf5ef2aSThomas Huth 3709fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3710fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3711fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3712fcf5ef2aSThomas Huth 3713fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3714fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3715fcf5ef2aSThomas Huth return; 3716fcf5ef2aSThomas Huth } 3717fcf5ef2aSThomas Huth 3718fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3719fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3720fcf5ef2aSThomas Huth return; 3721fcf5ef2aSThomas Huth } 3722fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3723fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3724fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3725fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3726fcf5ef2aSThomas Huth return; 3727fcf5ef2aSThomas Huth } 3728fcf5ef2aSThomas Huth 3729fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3730fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3731fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3732fcf5ef2aSThomas Huth 373394bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 373494bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 373594bf2658SRichard Henderson hi = cpu_gpr[rd]; 373694bf2658SRichard Henderson 373794bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3738f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 373994bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 374094bf2658SRichard Henderson if (ctx->le_mode) { 374194bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 374294bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3743fcf5ef2aSThomas Huth } else { 374494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 374594bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 374694bf2658SRichard Henderson } 374794bf2658SRichard Henderson tcg_temp_free_i32(oi); 374894bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3749f34ec0f6SRichard Henderson } else { 375094bf2658SRichard Henderson /* Restart with exclusive lock. */ 375194bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 375294bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3753f34ec0f6SRichard Henderson } 375494bf2658SRichard Henderson } else if (ctx->le_mode) { 375594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3756fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 375794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 375894bf2658SRichard Henderson } else { 375994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 376094bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 376194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3762fcf5ef2aSThomas Huth } 3763fcf5ef2aSThomas Huth tcg_temp_free(EA); 3764fcf5ef2aSThomas Huth } 3765fcf5ef2aSThomas Huth #endif 3766fcf5ef2aSThomas Huth 3767fcf5ef2aSThomas Huth /*** Integer store ***/ 3768fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3769fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3770fcf5ef2aSThomas Huth { \ 3771fcf5ef2aSThomas Huth TCGv EA; \ 3772fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3773fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3774fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3775fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3776fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3777fcf5ef2aSThomas Huth } 3778fcf5ef2aSThomas Huth 3779fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3780fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3781fcf5ef2aSThomas Huth { \ 3782fcf5ef2aSThomas Huth TCGv EA; \ 3783fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3784fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3785fcf5ef2aSThomas Huth return; \ 3786fcf5ef2aSThomas Huth } \ 3787fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3788fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3789fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3790fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3791fcf5ef2aSThomas Huth else \ 3792fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3793fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3794fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3795fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3796fcf5ef2aSThomas Huth } 3797fcf5ef2aSThomas Huth 3798fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3799fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3800fcf5ef2aSThomas Huth { \ 3801fcf5ef2aSThomas Huth TCGv EA; \ 3802fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3803fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3804fcf5ef2aSThomas Huth return; \ 3805fcf5ef2aSThomas Huth } \ 3806fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3807fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3808fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3809fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3810fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3811fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3812fcf5ef2aSThomas Huth } 3813fcf5ef2aSThomas Huth 3814fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3815fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3816fcf5ef2aSThomas Huth { \ 3817fcf5ef2aSThomas Huth TCGv EA; \ 3818fcf5ef2aSThomas Huth chk; \ 3819fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3820fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3821fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3822fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3823fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3824fcf5ef2aSThomas Huth } 3825fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3826fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3827fcf5ef2aSThomas Huth 3828fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3829fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3830fcf5ef2aSThomas Huth 3831fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3832fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3833fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3834fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3835fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3836fcf5ef2aSThomas Huth 3837fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3838fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3839fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3840fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3841fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3842fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 384350728199SRoman Kapl 384450728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 384550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 384650728199SRoman Kapl { \ 384750728199SRoman Kapl TCGv EA; \ 384850728199SRoman Kapl CHK_SV; \ 384950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 385050728199SRoman Kapl EA = tcg_temp_new(); \ 385150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 385250728199SRoman Kapl tcg_gen_qemu_st_tl( \ 385350728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 385450728199SRoman Kapl tcg_temp_free(EA); \ 385550728199SRoman Kapl } 385650728199SRoman Kapl 385750728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 385850728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 385950728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 386050728199SRoman Kapl #if defined(TARGET_PPC64) 386150728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 386250728199SRoman Kapl #endif 386350728199SRoman Kapl 3864fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3865fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3866fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3867fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3868fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3869fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3870fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3871fcf5ef2aSThomas Huth 3872fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3873fcf5ef2aSThomas Huth { 3874fcf5ef2aSThomas Huth int rs; 3875fcf5ef2aSThomas Huth TCGv EA; 3876fcf5ef2aSThomas Huth 3877fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3878fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3879fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3880fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3881f89ced5fSRichard Henderson TCGv hi, lo; 3882fcf5ef2aSThomas Huth 3883fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3884fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3885fcf5ef2aSThomas Huth } 3886fcf5ef2aSThomas Huth 3887fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3888fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3889fcf5ef2aSThomas Huth return; 3890fcf5ef2aSThomas Huth } 3891fcf5ef2aSThomas Huth 3892fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3893fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3894fcf5ef2aSThomas Huth return; 3895fcf5ef2aSThomas Huth } 3896fcf5ef2aSThomas Huth 3897fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3898fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3899fcf5ef2aSThomas Huth return; 3900fcf5ef2aSThomas Huth } 3901fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3902fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3903fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3904fcf5ef2aSThomas Huth 3905f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3906f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3907f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3908f89ced5fSRichard Henderson 3909f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3910f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3911f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3912f89ced5fSRichard Henderson if (ctx->le_mode) { 3913f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3914f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3915fcf5ef2aSThomas Huth } else { 3916f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3917f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3918f89ced5fSRichard Henderson } 3919f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3920f34ec0f6SRichard Henderson } else { 3921f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3922f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3923f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3924f34ec0f6SRichard Henderson } 3925f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3926f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3927fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3928f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3929f89ced5fSRichard Henderson } else { 3930f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3931f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3932f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3933fcf5ef2aSThomas Huth } 3934fcf5ef2aSThomas Huth tcg_temp_free(EA); 3935fcf5ef2aSThomas Huth } else { 3936fcf5ef2aSThomas Huth /* std / stdu */ 3937fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3938fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3939fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3940fcf5ef2aSThomas Huth return; 3941fcf5ef2aSThomas Huth } 3942fcf5ef2aSThomas Huth } 3943fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3944fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3945fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3946fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3947efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3948fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3949efe843d8SDavid Gibson } 3950fcf5ef2aSThomas Huth tcg_temp_free(EA); 3951fcf5ef2aSThomas Huth } 3952fcf5ef2aSThomas Huth } 3953fcf5ef2aSThomas Huth #endif 3954fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3955fcf5ef2aSThomas Huth 3956fcf5ef2aSThomas Huth /* lhbrx */ 3957fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3958fcf5ef2aSThomas Huth 3959fcf5ef2aSThomas Huth /* lwbrx */ 3960fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3961fcf5ef2aSThomas Huth 3962fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3963fcf5ef2aSThomas Huth /* ldbrx */ 3964fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3965fcf5ef2aSThomas Huth /* stdbrx */ 3966fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3967fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3968fcf5ef2aSThomas Huth 3969fcf5ef2aSThomas Huth /* sthbrx */ 3970fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3971fcf5ef2aSThomas Huth /* stwbrx */ 3972fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3973fcf5ef2aSThomas Huth 3974fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3975fcf5ef2aSThomas Huth 3976fcf5ef2aSThomas Huth /* lmw */ 3977fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3978fcf5ef2aSThomas Huth { 3979fcf5ef2aSThomas Huth TCGv t0; 3980fcf5ef2aSThomas Huth TCGv_i32 t1; 3981fcf5ef2aSThomas Huth 3982fcf5ef2aSThomas Huth if (ctx->le_mode) { 3983fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3984fcf5ef2aSThomas Huth return; 3985fcf5ef2aSThomas Huth } 3986fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3987fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3988fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3989fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3990fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3991fcf5ef2aSThomas Huth tcg_temp_free(t0); 3992fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3993fcf5ef2aSThomas Huth } 3994fcf5ef2aSThomas Huth 3995fcf5ef2aSThomas Huth /* stmw */ 3996fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3997fcf5ef2aSThomas Huth { 3998fcf5ef2aSThomas Huth TCGv t0; 3999fcf5ef2aSThomas Huth TCGv_i32 t1; 4000fcf5ef2aSThomas Huth 4001fcf5ef2aSThomas Huth if (ctx->le_mode) { 4002fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4003fcf5ef2aSThomas Huth return; 4004fcf5ef2aSThomas Huth } 4005fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4006fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4007fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 4008fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 4009fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 4010fcf5ef2aSThomas Huth tcg_temp_free(t0); 4011fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4012fcf5ef2aSThomas Huth } 4013fcf5ef2aSThomas Huth 4014fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 4015fcf5ef2aSThomas Huth 4016fcf5ef2aSThomas Huth /* lswi */ 4017efe843d8SDavid Gibson /* 4018efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 4019efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 4020efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 4021efe843d8SDavid Gibson * spec... 4022fcf5ef2aSThomas Huth */ 4023fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 4024fcf5ef2aSThomas Huth { 4025fcf5ef2aSThomas Huth TCGv t0; 4026fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4027fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4028fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 4029fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 4030fcf5ef2aSThomas Huth int nr; 4031fcf5ef2aSThomas Huth 4032fcf5ef2aSThomas Huth if (ctx->le_mode) { 4033fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4034fcf5ef2aSThomas Huth return; 4035fcf5ef2aSThomas Huth } 4036efe843d8SDavid Gibson if (nb == 0) { 4037fcf5ef2aSThomas Huth nb = 32; 4038efe843d8SDavid Gibson } 4039f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 4040fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 4041fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 4042fcf5ef2aSThomas Huth return; 4043fcf5ef2aSThomas Huth } 4044fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4045fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4046fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4047fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4048fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 4049fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 4050fcf5ef2aSThomas Huth tcg_temp_free(t0); 4051fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4052fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4053fcf5ef2aSThomas Huth } 4054fcf5ef2aSThomas Huth 4055fcf5ef2aSThomas Huth /* lswx */ 4056fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 4057fcf5ef2aSThomas Huth { 4058fcf5ef2aSThomas Huth TCGv t0; 4059fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 4060fcf5ef2aSThomas Huth 4061fcf5ef2aSThomas Huth if (ctx->le_mode) { 4062fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4063fcf5ef2aSThomas Huth return; 4064fcf5ef2aSThomas Huth } 4065fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4066fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4067fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4068fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 4069fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 4070fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 4071fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 4072fcf5ef2aSThomas Huth tcg_temp_free(t0); 4073fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4074fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4075fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4076fcf5ef2aSThomas Huth } 4077fcf5ef2aSThomas Huth 4078fcf5ef2aSThomas Huth /* stswi */ 4079fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 4080fcf5ef2aSThomas Huth { 4081fcf5ef2aSThomas Huth TCGv t0; 4082fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4083fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4084fcf5ef2aSThomas Huth 4085fcf5ef2aSThomas Huth if (ctx->le_mode) { 4086fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4087fcf5ef2aSThomas Huth return; 4088fcf5ef2aSThomas Huth } 4089fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4090fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4091fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4092efe843d8SDavid Gibson if (nb == 0) { 4093fcf5ef2aSThomas Huth nb = 32; 4094efe843d8SDavid Gibson } 4095fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4096fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4097fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4098fcf5ef2aSThomas Huth tcg_temp_free(t0); 4099fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4100fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4101fcf5ef2aSThomas Huth } 4102fcf5ef2aSThomas Huth 4103fcf5ef2aSThomas Huth /* stswx */ 4104fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 4105fcf5ef2aSThomas Huth { 4106fcf5ef2aSThomas Huth TCGv t0; 4107fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4108fcf5ef2aSThomas Huth 4109fcf5ef2aSThomas Huth if (ctx->le_mode) { 4110fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4111fcf5ef2aSThomas Huth return; 4112fcf5ef2aSThomas Huth } 4113fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4114fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4115fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4116fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4117fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 4118fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 4119fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4120fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4121fcf5ef2aSThomas Huth tcg_temp_free(t0); 4122fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4123fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4124fcf5ef2aSThomas Huth } 4125fcf5ef2aSThomas Huth 4126fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 4127fcf5ef2aSThomas Huth /* eieio */ 4128fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 4129fcf5ef2aSThomas Huth { 4130c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 4131c8fd8373SCédric Le Goater 4132c8fd8373SCédric Le Goater /* 4133c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 4134c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 4135c8fd8373SCédric Le Goater */ 4136c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 4137c8fd8373SCédric Le Goater /* 4138c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 4139c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 4140c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 4141c8fd8373SCédric Le Goater * complain to the user. 4142c8fd8373SCédric Le Goater */ 4143c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 4144c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 41452c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 4146c8fd8373SCédric Le Goater } else { 4147c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 4148c8fd8373SCédric Le Goater } 4149c8fd8373SCédric Le Goater } 4150c8fd8373SCédric Le Goater 4151c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 4152fcf5ef2aSThomas Huth } 4153fcf5ef2aSThomas Huth 4154fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4155fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 4156fcf5ef2aSThomas Huth { 4157fcf5ef2aSThomas Huth TCGv_i32 t; 4158fcf5ef2aSThomas Huth TCGLabel *l; 4159fcf5ef2aSThomas Huth 4160fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 4161fcf5ef2aSThomas Huth return; 4162fcf5ef2aSThomas Huth } 4163fcf5ef2aSThomas Huth l = gen_new_label(); 4164fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 4165fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4166fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 4167fcf5ef2aSThomas Huth if (global) { 4168fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 4169fcf5ef2aSThomas Huth } else { 4170fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 4171fcf5ef2aSThomas Huth } 4172fcf5ef2aSThomas Huth gen_set_label(l); 4173fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4174fcf5ef2aSThomas Huth } 4175fcf5ef2aSThomas Huth #else 4176fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 4177fcf5ef2aSThomas Huth #endif 4178fcf5ef2aSThomas Huth 4179fcf5ef2aSThomas Huth /* isync */ 4180fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 4181fcf5ef2aSThomas Huth { 4182fcf5ef2aSThomas Huth /* 4183fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 4184fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 4185fcf5ef2aSThomas Huth */ 4186fcf5ef2aSThomas Huth if (!ctx->pr) { 4187fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 4188fcf5ef2aSThomas Huth } 41894771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4190fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4191fcf5ef2aSThomas Huth } 4192fcf5ef2aSThomas Huth 4193fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 4194fcf5ef2aSThomas Huth 419514776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 41962a4e6c1bSRichard Henderson { 41972a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 41982a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 41992a4e6c1bSRichard Henderson 42002a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 42012a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 42022a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 42032a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 42042a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 42052a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 42062a4e6c1bSRichard Henderson tcg_temp_free(t0); 42072a4e6c1bSRichard Henderson } 42082a4e6c1bSRichard Henderson 4209fcf5ef2aSThomas Huth #define LARX(name, memop) \ 4210fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4211fcf5ef2aSThomas Huth { \ 42122a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 4213fcf5ef2aSThomas Huth } 4214fcf5ef2aSThomas Huth 4215fcf5ef2aSThomas Huth /* lwarx */ 4216fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 4217fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 4218fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 4219fcf5ef2aSThomas Huth 422014776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 422120923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 422220923c1dSRichard Henderson { 422320923c1dSRichard Henderson TCGv t = tcg_temp_new(); 422420923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 422520923c1dSRichard Henderson TCGv u = tcg_temp_new(); 422620923c1dSRichard Henderson 422720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 422820923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 422920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 423020923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 423120923c1dSRichard Henderson 423220923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 423320923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 423420923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 423520923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 423620923c1dSRichard Henderson 423720923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 423820923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 423920923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 424020923c1dSRichard Henderson 424120923c1dSRichard Henderson tcg_temp_free(t); 424220923c1dSRichard Henderson tcg_temp_free(t2); 424320923c1dSRichard Henderson tcg_temp_free(u); 424420923c1dSRichard Henderson } 424520923c1dSRichard Henderson 424614776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 424720ba8504SRichard Henderson { 424820ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 424920ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 425020923c1dSRichard Henderson int rt = rD(ctx->opcode); 425120923c1dSRichard Henderson bool need_serial; 425220ba8504SRichard Henderson TCGv src, dst; 425320ba8504SRichard Henderson 425420ba8504SRichard Henderson gen_addr_register(ctx, EA); 425520923c1dSRichard Henderson dst = cpu_gpr[rt]; 425620923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 425720ba8504SRichard Henderson 425820923c1dSRichard Henderson need_serial = false; 425920ba8504SRichard Henderson memop |= MO_ALIGN; 426020ba8504SRichard Henderson switch (gpr_FC) { 426120ba8504SRichard Henderson case 0: /* Fetch and add */ 426220ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 426320ba8504SRichard Henderson break; 426420ba8504SRichard Henderson case 1: /* Fetch and xor */ 426520ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 426620ba8504SRichard Henderson break; 426720ba8504SRichard Henderson case 2: /* Fetch and or */ 426820ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 426920ba8504SRichard Henderson break; 427020ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 427120ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 427220ba8504SRichard Henderson break; 4273b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 4274b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 4275b8ce0f86SRichard Henderson break; 4276b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 4277b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 4278b8ce0f86SRichard Henderson break; 4279b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 4280b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 4281b8ce0f86SRichard Henderson break; 4282b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 4283b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 4284b8ce0f86SRichard Henderson break; 428520ba8504SRichard Henderson case 8: /* Swap */ 428620ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 428720ba8504SRichard Henderson break; 428820923c1dSRichard Henderson 428920923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 429020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 429120923c1dSRichard Henderson need_serial = true; 429220923c1dSRichard Henderson } else { 429320923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 429420923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 429520923c1dSRichard Henderson 429620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 429720923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 429820923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 429920923c1dSRichard Henderson } else { 430020923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 430120923c1dSRichard Henderson } 430220923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 430320923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 430420923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 430520923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 430620923c1dSRichard Henderson 430720923c1dSRichard Henderson tcg_temp_free(t0); 430820923c1dSRichard Henderson tcg_temp_free(t1); 430920923c1dSRichard Henderson } 431020ba8504SRichard Henderson break; 431120923c1dSRichard Henderson 431220923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 431320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 431420923c1dSRichard Henderson need_serial = true; 431520923c1dSRichard Henderson } else { 431620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 431720923c1dSRichard Henderson } 431820923c1dSRichard Henderson break; 431920923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 432020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 432120923c1dSRichard Henderson need_serial = true; 432220923c1dSRichard Henderson } else { 432320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 432420923c1dSRichard Henderson } 432520923c1dSRichard Henderson break; 432620923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 432720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 432820923c1dSRichard Henderson need_serial = true; 432920923c1dSRichard Henderson } else { 433020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 433120923c1dSRichard Henderson } 433220923c1dSRichard Henderson break; 433320923c1dSRichard Henderson 433420ba8504SRichard Henderson default: 433520ba8504SRichard Henderson /* invoke data storage error handler */ 433620ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 433720ba8504SRichard Henderson } 433820ba8504SRichard Henderson tcg_temp_free(EA); 433920923c1dSRichard Henderson 434020923c1dSRichard Henderson if (need_serial) { 434120923c1dSRichard Henderson /* Restart with exclusive lock. */ 434220923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 434320923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 434420923c1dSRichard Henderson } 4345a68a6146SBalamuruhan S } 4346a68a6146SBalamuruhan S 434720ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 434820ba8504SRichard Henderson { 434920ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 435020ba8504SRichard Henderson } 435120ba8504SRichard Henderson 435220ba8504SRichard Henderson #ifdef TARGET_PPC64 435320ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 435420ba8504SRichard Henderson { 435520ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 435620ba8504SRichard Henderson } 4357a68a6146SBalamuruhan S #endif 4358a68a6146SBalamuruhan S 435914776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 43609deb041cSRichard Henderson { 43619deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 43629deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 43639deb041cSRichard Henderson TCGv src, discard; 43649deb041cSRichard Henderson 43659deb041cSRichard Henderson gen_addr_register(ctx, EA); 43669deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 43679deb041cSRichard Henderson discard = tcg_temp_new(); 43689deb041cSRichard Henderson 43699deb041cSRichard Henderson memop |= MO_ALIGN; 43709deb041cSRichard Henderson switch (gpr_FC) { 43719deb041cSRichard Henderson case 0: /* add and Store */ 43729deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43739deb041cSRichard Henderson break; 43749deb041cSRichard Henderson case 1: /* xor and Store */ 43759deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43769deb041cSRichard Henderson break; 43779deb041cSRichard Henderson case 2: /* Or and Store */ 43789deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43799deb041cSRichard Henderson break; 43809deb041cSRichard Henderson case 3: /* 'and' and Store */ 43819deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43829deb041cSRichard Henderson break; 43839deb041cSRichard Henderson case 4: /* Store max unsigned */ 4384b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4385b8ce0f86SRichard Henderson break; 43869deb041cSRichard Henderson case 5: /* Store max signed */ 4387b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4388b8ce0f86SRichard Henderson break; 43899deb041cSRichard Henderson case 6: /* Store min unsigned */ 4390b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4391b8ce0f86SRichard Henderson break; 43929deb041cSRichard Henderson case 7: /* Store min signed */ 4393b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4394b8ce0f86SRichard Henderson break; 43959deb041cSRichard Henderson case 24: /* Store twin */ 43967fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 43977fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 43987fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 43997fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 44007fbc2b20SRichard Henderson } else { 44017fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 44027fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 44037fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 44047fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 44057fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 44067fbc2b20SRichard Henderson 44077fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 44087fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 44097fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 44107fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 44117fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 44127fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 44137fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 44147fbc2b20SRichard Henderson 44157fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 44167fbc2b20SRichard Henderson tcg_temp_free(s2); 44177fbc2b20SRichard Henderson tcg_temp_free(s); 44187fbc2b20SRichard Henderson tcg_temp_free(t2); 44197fbc2b20SRichard Henderson tcg_temp_free(t); 44207fbc2b20SRichard Henderson } 44219deb041cSRichard Henderson break; 44229deb041cSRichard Henderson default: 44239deb041cSRichard Henderson /* invoke data storage error handler */ 44249deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 44259deb041cSRichard Henderson } 44269deb041cSRichard Henderson tcg_temp_free(discard); 44279deb041cSRichard Henderson tcg_temp_free(EA); 4428a3401188SBalamuruhan S } 4429a3401188SBalamuruhan S 44309deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 44319deb041cSRichard Henderson { 44329deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 44339deb041cSRichard Henderson } 44349deb041cSRichard Henderson 44359deb041cSRichard Henderson #ifdef TARGET_PPC64 44369deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 44379deb041cSRichard Henderson { 44389deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 44399deb041cSRichard Henderson } 4440a3401188SBalamuruhan S #endif 4441a3401188SBalamuruhan S 444214776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4443fcf5ef2aSThomas Huth { 4444253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4445253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4446d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4447d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4448fcf5ef2aSThomas Huth 4449d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4450d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4451d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4452d8b86898SRichard Henderson tcg_temp_free(t0); 4453253ce7b2SNikunj A Dadhania 4454253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4455253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4456253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4457253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4458253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4459253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4460253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4461253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4462253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4463253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4464253ce7b2SNikunj A Dadhania 4465fcf5ef2aSThomas Huth gen_set_label(l1); 44664771df23SNikunj A Dadhania 4467efe843d8SDavid Gibson /* 4468efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4469efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4470efe843d8SDavid Gibson */ 44714771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4472253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4473253ce7b2SNikunj A Dadhania 4474253ce7b2SNikunj A Dadhania gen_set_label(l2); 4475fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4476fcf5ef2aSThomas Huth } 4477fcf5ef2aSThomas Huth 4478fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4479fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4480fcf5ef2aSThomas Huth { \ 4481d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4482fcf5ef2aSThomas Huth } 4483fcf5ef2aSThomas Huth 4484fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4485fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4486fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4487fcf5ef2aSThomas Huth 4488fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4489fcf5ef2aSThomas Huth /* ldarx */ 4490fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4491fcf5ef2aSThomas Huth /* stdcx. */ 4492fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4493fcf5ef2aSThomas Huth 4494fcf5ef2aSThomas Huth /* lqarx */ 4495fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4496fcf5ef2aSThomas Huth { 4497fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 449894bf2658SRichard Henderson TCGv EA, hi, lo; 4499fcf5ef2aSThomas Huth 4500fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4501fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4502fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4503fcf5ef2aSThomas Huth return; 4504fcf5ef2aSThomas Huth } 4505fcf5ef2aSThomas Huth 4506fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 450794bf2658SRichard Henderson EA = tcg_temp_new(); 4508fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 450994bf2658SRichard Henderson 451094bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 451194bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 451294bf2658SRichard Henderson hi = cpu_gpr[rd]; 451394bf2658SRichard Henderson 451494bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4515f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 451694bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 451794bf2658SRichard Henderson if (ctx->le_mode) { 451894bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 451994bf2658SRichard Henderson ctx->mem_idx)); 452094bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4521fcf5ef2aSThomas Huth } else { 452294bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 452394bf2658SRichard Henderson ctx->mem_idx)); 452494bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4525fcf5ef2aSThomas Huth } 452694bf2658SRichard Henderson tcg_temp_free_i32(oi); 452794bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4528f34ec0f6SRichard Henderson } else { 452994bf2658SRichard Henderson /* Restart with exclusive lock. */ 453094bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 453194bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 453294bf2658SRichard Henderson tcg_temp_free(EA); 453394bf2658SRichard Henderson return; 4534f34ec0f6SRichard Henderson } 453594bf2658SRichard Henderson } else if (ctx->le_mode) { 453694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4537fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4538fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 453994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 454094bf2658SRichard Henderson } else { 454194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 454294bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 454394bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 454494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 454594bf2658SRichard Henderson } 4546fcf5ef2aSThomas Huth tcg_temp_free(EA); 454794bf2658SRichard Henderson 454894bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 454994bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4550fcf5ef2aSThomas Huth } 4551fcf5ef2aSThomas Huth 4552fcf5ef2aSThomas Huth /* stqcx. */ 4553fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4554fcf5ef2aSThomas Huth { 45554a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 45564a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4557fcf5ef2aSThomas Huth 45584a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4559fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4560fcf5ef2aSThomas Huth return; 4561fcf5ef2aSThomas Huth } 45624a9b3c5dSRichard Henderson 4563fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 45644a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4565fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4566fcf5ef2aSThomas Huth 45674a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 45684a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 45694a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4570fcf5ef2aSThomas Huth 45714a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4572f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 45734a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 45744a9b3c5dSRichard Henderson if (ctx->le_mode) { 4575f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4576f34ec0f6SRichard Henderson EA, lo, hi, oi); 4577fcf5ef2aSThomas Huth } else { 4578f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4579f34ec0f6SRichard Henderson EA, lo, hi, oi); 4580fcf5ef2aSThomas Huth } 4581f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4582f34ec0f6SRichard Henderson } else { 45834a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 45844a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 45854a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4586f34ec0f6SRichard Henderson } 4587fcf5ef2aSThomas Huth tcg_temp_free(EA); 45884a9b3c5dSRichard Henderson } else { 45894a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 45904a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 45914a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 45924a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4593fcf5ef2aSThomas Huth 45944a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 45954a9b3c5dSRichard Henderson tcg_temp_free(EA); 45964a9b3c5dSRichard Henderson 45974a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 45984a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 45994a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 46004a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 46014a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 46024a9b3c5dSRichard Henderson 46034a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 46044a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 46054a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 46064a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 46074a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 46084a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 46094a9b3c5dSRichard Henderson 46104a9b3c5dSRichard Henderson /* Success */ 46114a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 46124a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 46134a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 46144a9b3c5dSRichard Henderson 46154a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46164a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 46174a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 46184a9b3c5dSRichard Henderson 46194a9b3c5dSRichard Henderson gen_set_label(lab_fail); 46204a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46214a9b3c5dSRichard Henderson 46224a9b3c5dSRichard Henderson gen_set_label(lab_over); 46234a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 46244a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 46254a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 46264a9b3c5dSRichard Henderson } 46274a9b3c5dSRichard Henderson } 4628fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4629fcf5ef2aSThomas Huth 4630fcf5ef2aSThomas Huth /* sync */ 4631fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4632fcf5ef2aSThomas Huth { 4633fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4634fcf5ef2aSThomas Huth 4635fcf5ef2aSThomas Huth /* 4636fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4637fcf5ef2aSThomas Huth * 4638fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4639fcf5ef2aSThomas Huth * 4640fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4641fcf5ef2aSThomas Huth * check MSR_PR as well. 4642fcf5ef2aSThomas Huth */ 4643fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4644fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4645fcf5ef2aSThomas Huth } 46464771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4647fcf5ef2aSThomas Huth } 4648fcf5ef2aSThomas Huth 4649fcf5ef2aSThomas Huth /* wait */ 4650fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4651fcf5ef2aSThomas Huth { 4652fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4653fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4654fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4655fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4656fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4657b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4658fcf5ef2aSThomas Huth } 4659fcf5ef2aSThomas Huth 4660fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4661fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4662fcf5ef2aSThomas Huth { 4663fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4664fcf5ef2aSThomas Huth GEN_PRIV; 4665fcf5ef2aSThomas Huth #else 4666fcf5ef2aSThomas Huth TCGv_i32 t; 4667fcf5ef2aSThomas Huth 4668fcf5ef2aSThomas Huth CHK_HV; 4669fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4670fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4671fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4672154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4673154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4674fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4675fcf5ef2aSThomas Huth } 4676fcf5ef2aSThomas Huth 4677fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4678fcf5ef2aSThomas Huth { 4679fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4680fcf5ef2aSThomas Huth GEN_PRIV; 4681fcf5ef2aSThomas Huth #else 4682fcf5ef2aSThomas Huth TCGv_i32 t; 4683fcf5ef2aSThomas Huth 4684fcf5ef2aSThomas Huth CHK_HV; 4685fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4686fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4687fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4688154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4689154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4690fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4691fcf5ef2aSThomas Huth } 4692fcf5ef2aSThomas Huth 4693cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4694cdee0e72SNikunj A Dadhania { 469521c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 469621c0d66aSBenjamin Herrenschmidt GEN_PRIV; 469721c0d66aSBenjamin Herrenschmidt #else 469821c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 469921c0d66aSBenjamin Herrenschmidt 470021c0d66aSBenjamin Herrenschmidt CHK_HV; 470121c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 470221c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 470321c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 470421c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 470521c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 470621c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4707cdee0e72SNikunj A Dadhania } 4708cdee0e72SNikunj A Dadhania 4709fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4710fcf5ef2aSThomas Huth { 4711fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4712fcf5ef2aSThomas Huth GEN_PRIV; 4713fcf5ef2aSThomas Huth #else 4714fcf5ef2aSThomas Huth TCGv_i32 t; 4715fcf5ef2aSThomas Huth 4716fcf5ef2aSThomas Huth CHK_HV; 4717fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4718fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4719fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4720154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4721154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4722fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4723fcf5ef2aSThomas Huth } 4724fcf5ef2aSThomas Huth 4725fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4726fcf5ef2aSThomas Huth { 4727fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4728fcf5ef2aSThomas Huth GEN_PRIV; 4729fcf5ef2aSThomas Huth #else 4730fcf5ef2aSThomas Huth TCGv_i32 t; 4731fcf5ef2aSThomas Huth 4732fcf5ef2aSThomas Huth CHK_HV; 4733fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4734fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4735fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4736154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4737154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4738fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4739fcf5ef2aSThomas Huth } 4740fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4741fcf5ef2aSThomas Huth 4742fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4743fcf5ef2aSThomas Huth { 4744fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4745efe843d8SDavid Gibson if (ctx->has_cfar) { 4746fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4747efe843d8SDavid Gibson } 4748fcf5ef2aSThomas Huth #endif 4749fcf5ef2aSThomas Huth } 4750fcf5ef2aSThomas Huth 4751fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4752fcf5ef2aSThomas Huth { 4753fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4754fcf5ef2aSThomas Huth return false; 4755fcf5ef2aSThomas Huth } 4756fcf5ef2aSThomas Huth 4757fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4758b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4759fcf5ef2aSThomas Huth #else 4760fcf5ef2aSThomas Huth return true; 4761fcf5ef2aSThomas Huth #endif 4762fcf5ef2aSThomas Huth } 4763fcf5ef2aSThomas Huth 47640e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 47650e3bf489SRoman Kapl { 47660e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 47670e3bf489SRoman Kapl if (unlikely(sse)) { 47680e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 47690e3bf489SRoman Kapl gen_debug_exception(ctx); 47700e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4771e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 47720e3bf489SRoman Kapl gen_exception(ctx, excp); 47730e3bf489SRoman Kapl } 47740e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 47750e3bf489SRoman Kapl } else { 47760e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 47770e3bf489SRoman Kapl } 47780e3bf489SRoman Kapl } 47790e3bf489SRoman Kapl 4780fcf5ef2aSThomas Huth /*** Branch ***/ 4781c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4782fcf5ef2aSThomas Huth { 4783fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4784fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4785fcf5ef2aSThomas Huth } 4786fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4787fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4788fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 478907ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4790fcf5ef2aSThomas Huth } else { 4791fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 47920e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4793fcf5ef2aSThomas Huth } 4794fcf5ef2aSThomas Huth } 4795fcf5ef2aSThomas Huth 4796fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4797fcf5ef2aSThomas Huth { 4798fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4799fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4800fcf5ef2aSThomas Huth } 4801fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4802fcf5ef2aSThomas Huth } 4803fcf5ef2aSThomas Huth 4804fcf5ef2aSThomas Huth /* b ba bl bla */ 4805fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4806fcf5ef2aSThomas Huth { 4807fcf5ef2aSThomas Huth target_ulong li, target; 4808fcf5ef2aSThomas Huth 4809fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 4810fcf5ef2aSThomas Huth /* sign extend LI */ 4811fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4812fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4813fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 48142c2bcb1bSRichard Henderson target = ctx->cia + li; 4815fcf5ef2aSThomas Huth } else { 4816fcf5ef2aSThomas Huth target = li; 4817fcf5ef2aSThomas Huth } 4818fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4819b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4820fcf5ef2aSThomas Huth } 48212c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4822fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 4823fcf5ef2aSThomas Huth } 4824fcf5ef2aSThomas Huth 4825fcf5ef2aSThomas Huth #define BCOND_IM 0 4826fcf5ef2aSThomas Huth #define BCOND_LR 1 4827fcf5ef2aSThomas Huth #define BCOND_CTR 2 4828fcf5ef2aSThomas Huth #define BCOND_TAR 3 4829fcf5ef2aSThomas Huth 4830c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4831fcf5ef2aSThomas Huth { 4832fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4833fcf5ef2aSThomas Huth TCGLabel *l1; 4834fcf5ef2aSThomas Huth TCGv target; 4835fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 48360e3bf489SRoman Kapl 4837fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4838fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4839efe843d8SDavid Gibson if (type == BCOND_CTR) { 4840fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4841efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4842fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4843efe843d8SDavid Gibson } else { 4844fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4845efe843d8SDavid Gibson } 4846fcf5ef2aSThomas Huth } else { 4847f764718dSRichard Henderson target = NULL; 4848fcf5ef2aSThomas Huth } 4849efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4850b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4851efe843d8SDavid Gibson } 4852fcf5ef2aSThomas Huth l1 = gen_new_label(); 4853fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4854fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4855fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4856fa200c95SGreg Kurz 4857fa200c95SGreg Kurz if (type == BCOND_CTR) { 4858fa200c95SGreg Kurz /* 4859fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4860fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4861fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 486215d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 486315d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 486415d68c5eSGreg Kurz * it basically useless and thus never used in real code. 486515d68c5eSGreg Kurz * 486615d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 486715d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 486815d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 486915d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 487015d68c5eSGreg Kurz * doing anything else harmful. 4871fa200c95SGreg Kurz */ 4872d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4873fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 48749acc95cdSGreg Kurz tcg_temp_free(temp); 48759acc95cdSGreg Kurz tcg_temp_free(target); 4876fcf5ef2aSThomas Huth return; 4877fcf5ef2aSThomas Huth } 4878fa200c95SGreg Kurz 4879fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4880fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4881fa200c95SGreg Kurz } else { 4882fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4883fa200c95SGreg Kurz } 4884fa200c95SGreg Kurz if (bo & 0x2) { 4885fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4886fa200c95SGreg Kurz } else { 4887fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4888fa200c95SGreg Kurz } 4889fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4890fa200c95SGreg Kurz } else { 4891fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4892fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4893fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4894fcf5ef2aSThomas Huth } else { 4895fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4896fcf5ef2aSThomas Huth } 4897fcf5ef2aSThomas Huth if (bo & 0x2) { 4898fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4899fcf5ef2aSThomas Huth } else { 4900fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4901fcf5ef2aSThomas Huth } 4902fa200c95SGreg Kurz } 4903fcf5ef2aSThomas Huth tcg_temp_free(temp); 4904fcf5ef2aSThomas Huth } 4905fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4906fcf5ef2aSThomas Huth /* Test CR */ 4907fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4908fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4909fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4910fcf5ef2aSThomas Huth 4911fcf5ef2aSThomas Huth if (bo & 0x8) { 4912fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4913fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4914fcf5ef2aSThomas Huth } else { 4915fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4916fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4917fcf5ef2aSThomas Huth } 4918fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4919fcf5ef2aSThomas Huth } 49202c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4921fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4922fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4923fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 49242c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4925fcf5ef2aSThomas Huth } else { 4926fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4927fcf5ef2aSThomas Huth } 4928fcf5ef2aSThomas Huth } else { 4929fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4930fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4931fcf5ef2aSThomas Huth } else { 4932fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4933fcf5ef2aSThomas Huth } 49340e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4935c4a2e3a9SRichard Henderson tcg_temp_free(target); 4936c4a2e3a9SRichard Henderson } 4937fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 49380e3bf489SRoman Kapl /* fallthrough case */ 4939fcf5ef2aSThomas Huth gen_set_label(l1); 4940b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4941fcf5ef2aSThomas Huth } 4942fcf5ef2aSThomas Huth } 4943fcf5ef2aSThomas Huth 4944fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4945fcf5ef2aSThomas Huth { 4946fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4947fcf5ef2aSThomas Huth } 4948fcf5ef2aSThomas Huth 4949fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4950fcf5ef2aSThomas Huth { 4951fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4952fcf5ef2aSThomas Huth } 4953fcf5ef2aSThomas Huth 4954fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4955fcf5ef2aSThomas Huth { 4956fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4957fcf5ef2aSThomas Huth } 4958fcf5ef2aSThomas Huth 4959fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4960fcf5ef2aSThomas Huth { 4961fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4962fcf5ef2aSThomas Huth } 4963fcf5ef2aSThomas Huth 4964fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4965fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4966fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4967fcf5ef2aSThomas Huth { \ 4968fcf5ef2aSThomas Huth uint8_t bitmask; \ 4969fcf5ef2aSThomas Huth int sh; \ 4970fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4971fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4972fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4973fcf5ef2aSThomas Huth if (sh > 0) \ 4974fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4975fcf5ef2aSThomas Huth else if (sh < 0) \ 4976fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4977fcf5ef2aSThomas Huth else \ 4978fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4979fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4980fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4981fcf5ef2aSThomas Huth if (sh > 0) \ 4982fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4983fcf5ef2aSThomas Huth else if (sh < 0) \ 4984fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4985fcf5ef2aSThomas Huth else \ 4986fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4987fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4988fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4989fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4990fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4991fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4992fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4993fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4994fcf5ef2aSThomas Huth } 4995fcf5ef2aSThomas Huth 4996fcf5ef2aSThomas Huth /* crand */ 4997fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4998fcf5ef2aSThomas Huth /* crandc */ 4999fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 5000fcf5ef2aSThomas Huth /* creqv */ 5001fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 5002fcf5ef2aSThomas Huth /* crnand */ 5003fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 5004fcf5ef2aSThomas Huth /* crnor */ 5005fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 5006fcf5ef2aSThomas Huth /* cror */ 5007fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 5008fcf5ef2aSThomas Huth /* crorc */ 5009fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 5010fcf5ef2aSThomas Huth /* crxor */ 5011fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 5012fcf5ef2aSThomas Huth 5013fcf5ef2aSThomas Huth /* mcrf */ 5014fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 5015fcf5ef2aSThomas Huth { 5016fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 5017fcf5ef2aSThomas Huth } 5018fcf5ef2aSThomas Huth 5019fcf5ef2aSThomas Huth /*** System linkage ***/ 5020fcf5ef2aSThomas Huth 5021fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 5022fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 5023fcf5ef2aSThomas Huth { 5024fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5025fcf5ef2aSThomas Huth GEN_PRIV; 5026fcf5ef2aSThomas Huth #else 5027efe843d8SDavid Gibson /* 5028efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 5029fcf5ef2aSThomas Huth * processors compliant with arch 2.x 5030fcf5ef2aSThomas Huth */ 5031d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 5032fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5033fcf5ef2aSThomas Huth return; 5034fcf5ef2aSThomas Huth } 5035fcf5ef2aSThomas Huth /* Restore CPU state */ 5036fcf5ef2aSThomas Huth CHK_SV; 5037a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5038a59d628fSMaria Klimushenkova gen_io_start(); 5039a59d628fSMaria Klimushenkova } 50402c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 5041fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 5042fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5043fcf5ef2aSThomas Huth #endif 5044fcf5ef2aSThomas Huth } 5045fcf5ef2aSThomas Huth 5046fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5047fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 5048fcf5ef2aSThomas Huth { 5049fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5050fcf5ef2aSThomas Huth GEN_PRIV; 5051fcf5ef2aSThomas Huth #else 5052fcf5ef2aSThomas Huth /* Restore CPU state */ 5053fcf5ef2aSThomas Huth CHK_SV; 5054a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5055a59d628fSMaria Klimushenkova gen_io_start(); 5056a59d628fSMaria Klimushenkova } 50572c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 5058fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 5059fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5060fcf5ef2aSThomas Huth #endif 5061fcf5ef2aSThomas Huth } 5062fcf5ef2aSThomas Huth 50633c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 50643c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 50653c89b8d6SNicholas Piggin { 50663c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 50673c89b8d6SNicholas Piggin GEN_PRIV; 50683c89b8d6SNicholas Piggin #else 50693c89b8d6SNicholas Piggin /* Restore CPU state */ 50703c89b8d6SNicholas Piggin CHK_SV; 50713c89b8d6SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 50723c89b8d6SNicholas Piggin gen_io_start(); 50733c89b8d6SNicholas Piggin } 50742c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 50753c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 50763c89b8d6SNicholas Piggin gen_sync_exception(ctx); 50773c89b8d6SNicholas Piggin #endif 50783c89b8d6SNicholas Piggin } 50793c89b8d6SNicholas Piggin #endif 50803c89b8d6SNicholas Piggin 5081fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 5082fcf5ef2aSThomas Huth { 5083fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5084fcf5ef2aSThomas Huth GEN_PRIV; 5085fcf5ef2aSThomas Huth #else 5086fcf5ef2aSThomas Huth /* Restore CPU state */ 5087fcf5ef2aSThomas Huth CHK_HV; 5088fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 5089fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5090fcf5ef2aSThomas Huth #endif 5091fcf5ef2aSThomas Huth } 5092fcf5ef2aSThomas Huth #endif 5093fcf5ef2aSThomas Huth 5094fcf5ef2aSThomas Huth /* sc */ 5095fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5096fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 5097fcf5ef2aSThomas Huth #else 5098fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 50993c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 5100fcf5ef2aSThomas Huth #endif 5101fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 5102fcf5ef2aSThomas Huth { 5103fcf5ef2aSThomas Huth uint32_t lev; 5104fcf5ef2aSThomas Huth 5105fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 5106fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 5107fcf5ef2aSThomas Huth } 5108fcf5ef2aSThomas Huth 51093c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 51103c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 51113c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 51123c89b8d6SNicholas Piggin { 5113f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 51143c89b8d6SNicholas Piggin 5115f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 5116f43520e5SRichard Henderson if (ctx->exception == POWERPC_EXCP_NONE) { 51172c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 51183c89b8d6SNicholas Piggin } 5119f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 51203c89b8d6SNicholas Piggin 5121f43520e5SRichard Henderson /* This need not be exact, just not POWERPC_EXCP_NONE */ 5122f43520e5SRichard Henderson ctx->exception = POWERPC_SYSCALL_VECTORED; 51233c89b8d6SNicholas Piggin } 51243c89b8d6SNicholas Piggin #endif 51253c89b8d6SNicholas Piggin #endif 51263c89b8d6SNicholas Piggin 5127fcf5ef2aSThomas Huth /*** Trap ***/ 5128fcf5ef2aSThomas Huth 5129fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 5130fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 5131fcf5ef2aSThomas Huth { 5132fcf5ef2aSThomas Huth /* Trap never */ 5133fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 5134fcf5ef2aSThomas Huth return true; 5135fcf5ef2aSThomas Huth } 5136fcf5ef2aSThomas Huth /* Trap always */ 5137fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 5138fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 5139fcf5ef2aSThomas Huth return true; 5140fcf5ef2aSThomas Huth } 5141fcf5ef2aSThomas Huth return false; 5142fcf5ef2aSThomas Huth } 5143fcf5ef2aSThomas Huth 5144fcf5ef2aSThomas Huth /* tw */ 5145fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 5146fcf5ef2aSThomas Huth { 5147fcf5ef2aSThomas Huth TCGv_i32 t0; 5148fcf5ef2aSThomas Huth 5149fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5150fcf5ef2aSThomas Huth return; 5151fcf5ef2aSThomas Huth } 5152fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5153fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5154fcf5ef2aSThomas Huth t0); 5155fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5156fcf5ef2aSThomas Huth } 5157fcf5ef2aSThomas Huth 5158fcf5ef2aSThomas Huth /* twi */ 5159fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 5160fcf5ef2aSThomas Huth { 5161fcf5ef2aSThomas Huth TCGv t0; 5162fcf5ef2aSThomas Huth TCGv_i32 t1; 5163fcf5ef2aSThomas Huth 5164fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5165fcf5ef2aSThomas Huth return; 5166fcf5ef2aSThomas Huth } 5167fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5168fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5169fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5170fcf5ef2aSThomas Huth tcg_temp_free(t0); 5171fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5172fcf5ef2aSThomas Huth } 5173fcf5ef2aSThomas Huth 5174fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5175fcf5ef2aSThomas Huth /* td */ 5176fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 5177fcf5ef2aSThomas Huth { 5178fcf5ef2aSThomas Huth TCGv_i32 t0; 5179fcf5ef2aSThomas Huth 5180fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5181fcf5ef2aSThomas Huth return; 5182fcf5ef2aSThomas Huth } 5183fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5184fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5185fcf5ef2aSThomas Huth t0); 5186fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5187fcf5ef2aSThomas Huth } 5188fcf5ef2aSThomas Huth 5189fcf5ef2aSThomas Huth /* tdi */ 5190fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 5191fcf5ef2aSThomas Huth { 5192fcf5ef2aSThomas Huth TCGv t0; 5193fcf5ef2aSThomas Huth TCGv_i32 t1; 5194fcf5ef2aSThomas Huth 5195fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5196fcf5ef2aSThomas Huth return; 5197fcf5ef2aSThomas Huth } 5198fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5199fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5200fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5201fcf5ef2aSThomas Huth tcg_temp_free(t0); 5202fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5203fcf5ef2aSThomas Huth } 5204fcf5ef2aSThomas Huth #endif 5205fcf5ef2aSThomas Huth 5206fcf5ef2aSThomas Huth /*** Processor control ***/ 5207fcf5ef2aSThomas Huth 5208fcf5ef2aSThomas Huth /* mcrxr */ 5209fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 5210fcf5ef2aSThomas Huth { 5211fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5212fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 5213fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5214fcf5ef2aSThomas Huth 5215fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 5216fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 5217fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 5218fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 5219fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 5220fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 5221fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 5222fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 5223fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5224fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5225fcf5ef2aSThomas Huth 5226fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 5227fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5228fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5229fcf5ef2aSThomas Huth } 5230fcf5ef2aSThomas Huth 5231b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 5232b63d0434SNikunj A Dadhania /* mcrxrx */ 5233b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 5234b63d0434SNikunj A Dadhania { 5235b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 5236b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 5237b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5238b63d0434SNikunj A Dadhania 5239b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 5240b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 5241b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 5242b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 5243b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 5244b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 5245b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 5246b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 5247b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 5248b63d0434SNikunj A Dadhania tcg_temp_free(t0); 5249b63d0434SNikunj A Dadhania tcg_temp_free(t1); 5250b63d0434SNikunj A Dadhania } 5251b63d0434SNikunj A Dadhania #endif 5252b63d0434SNikunj A Dadhania 5253fcf5ef2aSThomas Huth /* mfcr mfocrf */ 5254fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 5255fcf5ef2aSThomas Huth { 5256fcf5ef2aSThomas Huth uint32_t crm, crn; 5257fcf5ef2aSThomas Huth 5258fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 5259fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5260fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 5261fcf5ef2aSThomas Huth crn = ctz32(crm); 5262fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 5263fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 5264fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 5265fcf5ef2aSThomas Huth } 5266fcf5ef2aSThomas Huth } else { 5267fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5268fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 5269fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5270fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 5271fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5272fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 5273fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5274fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 5275fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5276fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 5277fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5278fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 5279fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5280fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 5281fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5282fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 5283fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5284fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5285fcf5ef2aSThomas Huth } 5286fcf5ef2aSThomas Huth } 5287fcf5ef2aSThomas Huth 5288fcf5ef2aSThomas Huth /* mfmsr */ 5289fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 5290fcf5ef2aSThomas Huth { 5291fcf5ef2aSThomas Huth CHK_SV; 5292fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 5293fcf5ef2aSThomas Huth } 5294fcf5ef2aSThomas Huth 5295fcf5ef2aSThomas Huth /* mfspr */ 5296fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 5297fcf5ef2aSThomas Huth { 5298fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 5299fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5300fcf5ef2aSThomas Huth 5301fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5302fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5303fcf5ef2aSThomas Huth #else 5304fcf5ef2aSThomas Huth if (ctx->pr) { 5305fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5306fcf5ef2aSThomas Huth } else if (ctx->hv) { 5307fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 5308fcf5ef2aSThomas Huth } else { 5309fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 5310fcf5ef2aSThomas Huth } 5311fcf5ef2aSThomas Huth #endif 5312fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 5313fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 5314fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 5315fcf5ef2aSThomas Huth } else { 5316fcf5ef2aSThomas Huth /* Privilege exception */ 5317efe843d8SDavid Gibson /* 5318efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 5319fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 5320fcf5ef2aSThomas Huth * allowing userland application to read the PVR 5321fcf5ef2aSThomas Huth */ 5322fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 532331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 532431085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 53252c2bcb1bSRichard Henderson ctx->cia); 5326fcf5ef2aSThomas Huth } 5327fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5328fcf5ef2aSThomas Huth } 5329fcf5ef2aSThomas Huth } else { 5330fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5331fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5332fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5333fcf5ef2aSThomas Huth /* This is a nop */ 5334fcf5ef2aSThomas Huth return; 5335fcf5ef2aSThomas Huth } 5336fcf5ef2aSThomas Huth /* Not defined */ 533731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 533831085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 53392c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5340fcf5ef2aSThomas Huth 5341efe843d8SDavid Gibson /* 5342efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5343efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5344fcf5ef2aSThomas Huth */ 5345fcf5ef2aSThomas Huth if (sprn & 0x10) { 5346fcf5ef2aSThomas Huth if (ctx->pr) { 5347fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5348fcf5ef2aSThomas Huth } 5349fcf5ef2aSThomas Huth } else { 5350fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5351fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5352fcf5ef2aSThomas Huth } 5353fcf5ef2aSThomas Huth } 5354fcf5ef2aSThomas Huth } 5355fcf5ef2aSThomas Huth } 5356fcf5ef2aSThomas Huth 5357fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5358fcf5ef2aSThomas Huth { 5359fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5360fcf5ef2aSThomas Huth } 5361fcf5ef2aSThomas Huth 5362fcf5ef2aSThomas Huth /* mftb */ 5363fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5364fcf5ef2aSThomas Huth { 5365fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5366fcf5ef2aSThomas Huth } 5367fcf5ef2aSThomas Huth 5368fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5369fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5370fcf5ef2aSThomas Huth { 5371fcf5ef2aSThomas Huth uint32_t crm, crn; 5372fcf5ef2aSThomas Huth 5373fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5374fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5375fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5376fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5377fcf5ef2aSThomas Huth crn = ctz32(crm); 5378fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5379fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5380fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5381fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5382fcf5ef2aSThomas Huth } 5383fcf5ef2aSThomas Huth } else { 5384fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5385fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5386fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5387fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5388fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5389fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5390fcf5ef2aSThomas Huth } 5391fcf5ef2aSThomas Huth } 5392fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5393fcf5ef2aSThomas Huth } 5394fcf5ef2aSThomas Huth } 5395fcf5ef2aSThomas Huth 5396fcf5ef2aSThomas Huth /* mtmsr */ 5397fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5398fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5399fcf5ef2aSThomas Huth { 5400fcf5ef2aSThomas Huth CHK_SV; 5401fcf5ef2aSThomas Huth 5402fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 54035ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54045ed19506SNicholas Piggin gen_io_start(); 54055ed19506SNicholas Piggin } 5406fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54075ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5408fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54095ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5410efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5411efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54125ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5413efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54145ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54155ed19506SNicholas Piggin 54165ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5417fcf5ef2aSThomas Huth tcg_temp_free(t0); 54185ed19506SNicholas Piggin tcg_temp_free(t1); 54195ed19506SNicholas Piggin 5420fcf5ef2aSThomas Huth } else { 5421efe843d8SDavid Gibson /* 5422efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5423efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5424efe843d8SDavid Gibson * ppc_store_msr 5425fcf5ef2aSThomas Huth */ 5426b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5427fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5428fcf5ef2aSThomas Huth } 54295ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54305ed19506SNicholas Piggin gen_stop_exception(ctx); 5431fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5432fcf5ef2aSThomas Huth } 5433fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5434fcf5ef2aSThomas Huth 5435fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5436fcf5ef2aSThomas Huth { 5437fcf5ef2aSThomas Huth CHK_SV; 5438fcf5ef2aSThomas Huth 5439fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 54405ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54415ed19506SNicholas Piggin gen_io_start(); 54425ed19506SNicholas Piggin } 5443fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54445ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5445fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54465ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5447efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5448efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54495ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5450efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54515ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54525ed19506SNicholas Piggin 54535ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5454fcf5ef2aSThomas Huth tcg_temp_free(t0); 54555ed19506SNicholas Piggin tcg_temp_free(t1); 54565ed19506SNicholas Piggin 5457fcf5ef2aSThomas Huth } else { 5458fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5459fcf5ef2aSThomas Huth 5460efe843d8SDavid Gibson /* 5461efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5462efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5463efe843d8SDavid Gibson * ppc_store_msr 5464fcf5ef2aSThomas Huth */ 5465b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5466fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5467fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5468fcf5ef2aSThomas Huth #else 5469fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5470fcf5ef2aSThomas Huth #endif 5471fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5472fcf5ef2aSThomas Huth tcg_temp_free(msr); 5473fcf5ef2aSThomas Huth } 54745ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54755ed19506SNicholas Piggin gen_stop_exception(ctx); 5476fcf5ef2aSThomas Huth #endif 5477fcf5ef2aSThomas Huth } 5478fcf5ef2aSThomas Huth 5479fcf5ef2aSThomas Huth /* mtspr */ 5480fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5481fcf5ef2aSThomas Huth { 5482fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5483fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5484fcf5ef2aSThomas Huth 5485fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5486fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5487fcf5ef2aSThomas Huth #else 5488fcf5ef2aSThomas Huth if (ctx->pr) { 5489fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5490fcf5ef2aSThomas Huth } else if (ctx->hv) { 5491fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5492fcf5ef2aSThomas Huth } else { 5493fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5494fcf5ef2aSThomas Huth } 5495fcf5ef2aSThomas Huth #endif 5496fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5497fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5498fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5499fcf5ef2aSThomas Huth } else { 5500fcf5ef2aSThomas Huth /* Privilege exception */ 550131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 550231085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 55032c2bcb1bSRichard Henderson ctx->cia); 5504fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5505fcf5ef2aSThomas Huth } 5506fcf5ef2aSThomas Huth } else { 5507fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5508fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5509fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5510fcf5ef2aSThomas Huth /* This is a nop */ 5511fcf5ef2aSThomas Huth return; 5512fcf5ef2aSThomas Huth } 5513fcf5ef2aSThomas Huth 5514fcf5ef2aSThomas Huth /* Not defined */ 551531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 551631085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 55172c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5518fcf5ef2aSThomas Huth 5519fcf5ef2aSThomas Huth 5520efe843d8SDavid Gibson /* 5521efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5522efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5523fcf5ef2aSThomas Huth */ 5524fcf5ef2aSThomas Huth if (sprn & 0x10) { 5525fcf5ef2aSThomas Huth if (ctx->pr) { 5526fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5527fcf5ef2aSThomas Huth } 5528fcf5ef2aSThomas Huth } else { 5529fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5530fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5531fcf5ef2aSThomas Huth } 5532fcf5ef2aSThomas Huth } 5533fcf5ef2aSThomas Huth } 5534fcf5ef2aSThomas Huth } 5535fcf5ef2aSThomas Huth 5536fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5537fcf5ef2aSThomas Huth /* setb */ 5538fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5539fcf5ef2aSThomas Huth { 5540fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5541fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5542fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5543fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5544fcf5ef2aSThomas Huth 5545fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5546fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5547fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5548fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5549fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5550fcf5ef2aSThomas Huth 5551fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5552fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5553fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5554fcf5ef2aSThomas Huth } 5555fcf5ef2aSThomas Huth #endif 5556fcf5ef2aSThomas Huth 5557fcf5ef2aSThomas Huth /*** Cache management ***/ 5558fcf5ef2aSThomas Huth 5559fcf5ef2aSThomas Huth /* dcbf */ 5560fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5561fcf5ef2aSThomas Huth { 5562fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5563fcf5ef2aSThomas Huth TCGv t0; 5564fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5565fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5566fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5567fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5568fcf5ef2aSThomas Huth tcg_temp_free(t0); 5569fcf5ef2aSThomas Huth } 5570fcf5ef2aSThomas Huth 557150728199SRoman Kapl /* dcbfep (external PID dcbf) */ 557250728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 557350728199SRoman Kapl { 557450728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 557550728199SRoman Kapl TCGv t0; 557650728199SRoman Kapl CHK_SV; 557750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 557850728199SRoman Kapl t0 = tcg_temp_new(); 557950728199SRoman Kapl gen_addr_reg_index(ctx, t0); 558050728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 558150728199SRoman Kapl tcg_temp_free(t0); 558250728199SRoman Kapl } 558350728199SRoman Kapl 5584fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5585fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5586fcf5ef2aSThomas Huth { 5587fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5588fcf5ef2aSThomas Huth GEN_PRIV; 5589fcf5ef2aSThomas Huth #else 5590fcf5ef2aSThomas Huth TCGv EA, val; 5591fcf5ef2aSThomas Huth 5592fcf5ef2aSThomas Huth CHK_SV; 5593fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5594fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5595fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5596fcf5ef2aSThomas Huth val = tcg_temp_new(); 5597fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5598fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5599fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5600fcf5ef2aSThomas Huth tcg_temp_free(val); 5601fcf5ef2aSThomas Huth tcg_temp_free(EA); 5602fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5603fcf5ef2aSThomas Huth } 5604fcf5ef2aSThomas Huth 5605fcf5ef2aSThomas Huth /* dcdst */ 5606fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5607fcf5ef2aSThomas Huth { 5608fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5609fcf5ef2aSThomas Huth TCGv t0; 5610fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5611fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5612fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5613fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5614fcf5ef2aSThomas Huth tcg_temp_free(t0); 5615fcf5ef2aSThomas Huth } 5616fcf5ef2aSThomas Huth 561750728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 561850728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 561950728199SRoman Kapl { 562050728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 562150728199SRoman Kapl TCGv t0; 562250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 562350728199SRoman Kapl t0 = tcg_temp_new(); 562450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 562550728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 562650728199SRoman Kapl tcg_temp_free(t0); 562750728199SRoman Kapl } 562850728199SRoman Kapl 5629fcf5ef2aSThomas Huth /* dcbt */ 5630fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5631fcf5ef2aSThomas Huth { 5632efe843d8SDavid Gibson /* 5633efe843d8SDavid Gibson * interpreted as no-op 5634efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5635efe843d8SDavid Gibson * does not generate any exception 5636fcf5ef2aSThomas Huth */ 5637fcf5ef2aSThomas Huth } 5638fcf5ef2aSThomas Huth 563950728199SRoman Kapl /* dcbtep */ 564050728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 564150728199SRoman Kapl { 5642efe843d8SDavid Gibson /* 5643efe843d8SDavid Gibson * interpreted as no-op 5644efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5645efe843d8SDavid Gibson * does not generate any exception 564650728199SRoman Kapl */ 564750728199SRoman Kapl } 564850728199SRoman Kapl 5649fcf5ef2aSThomas Huth /* dcbtst */ 5650fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5651fcf5ef2aSThomas Huth { 5652efe843d8SDavid Gibson /* 5653efe843d8SDavid Gibson * interpreted as no-op 5654efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5655efe843d8SDavid Gibson * does not generate any exception 5656fcf5ef2aSThomas Huth */ 5657fcf5ef2aSThomas Huth } 5658fcf5ef2aSThomas Huth 565950728199SRoman Kapl /* dcbtstep */ 566050728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 566150728199SRoman Kapl { 5662efe843d8SDavid Gibson /* 5663efe843d8SDavid Gibson * interpreted as no-op 5664efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5665efe843d8SDavid Gibson * does not generate any exception 566650728199SRoman Kapl */ 566750728199SRoman Kapl } 566850728199SRoman Kapl 5669fcf5ef2aSThomas Huth /* dcbtls */ 5670fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5671fcf5ef2aSThomas Huth { 5672fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5673fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5674fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5675fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5676fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5677fcf5ef2aSThomas Huth tcg_temp_free(t0); 5678fcf5ef2aSThomas Huth } 5679fcf5ef2aSThomas Huth 5680fcf5ef2aSThomas Huth /* dcbz */ 5681fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5682fcf5ef2aSThomas Huth { 5683fcf5ef2aSThomas Huth TCGv tcgv_addr; 5684fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5685fcf5ef2aSThomas Huth 5686fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5687fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5688fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5689fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5690fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5691fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5692fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5693fcf5ef2aSThomas Huth } 5694fcf5ef2aSThomas Huth 569550728199SRoman Kapl /* dcbzep */ 569650728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 569750728199SRoman Kapl { 569850728199SRoman Kapl TCGv tcgv_addr; 569950728199SRoman Kapl TCGv_i32 tcgv_op; 570050728199SRoman Kapl 570150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 570250728199SRoman Kapl tcgv_addr = tcg_temp_new(); 570350728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 570450728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 570550728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 570650728199SRoman Kapl tcg_temp_free(tcgv_addr); 570750728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 570850728199SRoman Kapl } 570950728199SRoman Kapl 5710fcf5ef2aSThomas Huth /* dst / dstt */ 5711fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5712fcf5ef2aSThomas Huth { 5713fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5714fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5715fcf5ef2aSThomas Huth } else { 5716fcf5ef2aSThomas Huth /* interpreted as no-op */ 5717fcf5ef2aSThomas Huth } 5718fcf5ef2aSThomas Huth } 5719fcf5ef2aSThomas Huth 5720fcf5ef2aSThomas Huth /* dstst /dststt */ 5721fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5722fcf5ef2aSThomas Huth { 5723fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5724fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5725fcf5ef2aSThomas Huth } else { 5726fcf5ef2aSThomas Huth /* interpreted as no-op */ 5727fcf5ef2aSThomas Huth } 5728fcf5ef2aSThomas Huth 5729fcf5ef2aSThomas Huth } 5730fcf5ef2aSThomas Huth 5731fcf5ef2aSThomas Huth /* dss / dssall */ 5732fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5733fcf5ef2aSThomas Huth { 5734fcf5ef2aSThomas Huth /* interpreted as no-op */ 5735fcf5ef2aSThomas Huth } 5736fcf5ef2aSThomas Huth 5737fcf5ef2aSThomas Huth /* icbi */ 5738fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5739fcf5ef2aSThomas Huth { 5740fcf5ef2aSThomas Huth TCGv t0; 5741fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5742fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5743fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5744fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5745fcf5ef2aSThomas Huth tcg_temp_free(t0); 5746fcf5ef2aSThomas Huth } 5747fcf5ef2aSThomas Huth 574850728199SRoman Kapl /* icbiep */ 574950728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 575050728199SRoman Kapl { 575150728199SRoman Kapl TCGv t0; 575250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 575350728199SRoman Kapl t0 = tcg_temp_new(); 575450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 575550728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 575650728199SRoman Kapl tcg_temp_free(t0); 575750728199SRoman Kapl } 575850728199SRoman Kapl 5759fcf5ef2aSThomas Huth /* Optional: */ 5760fcf5ef2aSThomas Huth /* dcba */ 5761fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5762fcf5ef2aSThomas Huth { 5763efe843d8SDavid Gibson /* 5764efe843d8SDavid Gibson * interpreted as no-op 5765efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5766fcf5ef2aSThomas Huth * but does not generate any exception 5767fcf5ef2aSThomas Huth */ 5768fcf5ef2aSThomas Huth } 5769fcf5ef2aSThomas Huth 5770fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5771fcf5ef2aSThomas Huth /* Supervisor only: */ 5772fcf5ef2aSThomas Huth 5773fcf5ef2aSThomas Huth /* mfsr */ 5774fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5775fcf5ef2aSThomas Huth { 5776fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5777fcf5ef2aSThomas Huth GEN_PRIV; 5778fcf5ef2aSThomas Huth #else 5779fcf5ef2aSThomas Huth TCGv t0; 5780fcf5ef2aSThomas Huth 5781fcf5ef2aSThomas Huth CHK_SV; 5782fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5783fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5784fcf5ef2aSThomas Huth tcg_temp_free(t0); 5785fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5786fcf5ef2aSThomas Huth } 5787fcf5ef2aSThomas Huth 5788fcf5ef2aSThomas Huth /* mfsrin */ 5789fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5790fcf5ef2aSThomas Huth { 5791fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5792fcf5ef2aSThomas Huth GEN_PRIV; 5793fcf5ef2aSThomas Huth #else 5794fcf5ef2aSThomas Huth TCGv t0; 5795fcf5ef2aSThomas Huth 5796fcf5ef2aSThomas Huth CHK_SV; 5797fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5798e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5799fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5800fcf5ef2aSThomas Huth tcg_temp_free(t0); 5801fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5802fcf5ef2aSThomas Huth } 5803fcf5ef2aSThomas Huth 5804fcf5ef2aSThomas Huth /* mtsr */ 5805fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5806fcf5ef2aSThomas Huth { 5807fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5808fcf5ef2aSThomas Huth GEN_PRIV; 5809fcf5ef2aSThomas Huth #else 5810fcf5ef2aSThomas Huth TCGv t0; 5811fcf5ef2aSThomas Huth 5812fcf5ef2aSThomas Huth CHK_SV; 5813fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5814fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5815fcf5ef2aSThomas Huth tcg_temp_free(t0); 5816fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5817fcf5ef2aSThomas Huth } 5818fcf5ef2aSThomas Huth 5819fcf5ef2aSThomas Huth /* mtsrin */ 5820fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5821fcf5ef2aSThomas Huth { 5822fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5823fcf5ef2aSThomas Huth GEN_PRIV; 5824fcf5ef2aSThomas Huth #else 5825fcf5ef2aSThomas Huth TCGv t0; 5826fcf5ef2aSThomas Huth CHK_SV; 5827fcf5ef2aSThomas Huth 5828fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5829e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5830fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5831fcf5ef2aSThomas Huth tcg_temp_free(t0); 5832fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5833fcf5ef2aSThomas Huth } 5834fcf5ef2aSThomas Huth 5835fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5836fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5837fcf5ef2aSThomas Huth 5838fcf5ef2aSThomas Huth /* mfsr */ 5839fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5840fcf5ef2aSThomas Huth { 5841fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5842fcf5ef2aSThomas Huth GEN_PRIV; 5843fcf5ef2aSThomas Huth #else 5844fcf5ef2aSThomas Huth TCGv t0; 5845fcf5ef2aSThomas Huth 5846fcf5ef2aSThomas Huth CHK_SV; 5847fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5848fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5849fcf5ef2aSThomas Huth tcg_temp_free(t0); 5850fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5851fcf5ef2aSThomas Huth } 5852fcf5ef2aSThomas Huth 5853fcf5ef2aSThomas Huth /* mfsrin */ 5854fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5855fcf5ef2aSThomas Huth { 5856fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5857fcf5ef2aSThomas Huth GEN_PRIV; 5858fcf5ef2aSThomas Huth #else 5859fcf5ef2aSThomas Huth TCGv t0; 5860fcf5ef2aSThomas Huth 5861fcf5ef2aSThomas Huth CHK_SV; 5862fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5863e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5864fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5865fcf5ef2aSThomas Huth tcg_temp_free(t0); 5866fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5867fcf5ef2aSThomas Huth } 5868fcf5ef2aSThomas Huth 5869fcf5ef2aSThomas Huth /* mtsr */ 5870fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5871fcf5ef2aSThomas Huth { 5872fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5873fcf5ef2aSThomas Huth GEN_PRIV; 5874fcf5ef2aSThomas Huth #else 5875fcf5ef2aSThomas Huth TCGv t0; 5876fcf5ef2aSThomas Huth 5877fcf5ef2aSThomas Huth CHK_SV; 5878fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5879fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5880fcf5ef2aSThomas Huth tcg_temp_free(t0); 5881fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5882fcf5ef2aSThomas Huth } 5883fcf5ef2aSThomas Huth 5884fcf5ef2aSThomas Huth /* mtsrin */ 5885fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5886fcf5ef2aSThomas Huth { 5887fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5888fcf5ef2aSThomas Huth GEN_PRIV; 5889fcf5ef2aSThomas Huth #else 5890fcf5ef2aSThomas Huth TCGv t0; 5891fcf5ef2aSThomas Huth 5892fcf5ef2aSThomas Huth CHK_SV; 5893fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5894e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5895fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5896fcf5ef2aSThomas Huth tcg_temp_free(t0); 5897fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5898fcf5ef2aSThomas Huth } 5899fcf5ef2aSThomas Huth 5900fcf5ef2aSThomas Huth /* slbmte */ 5901fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5902fcf5ef2aSThomas Huth { 5903fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5904fcf5ef2aSThomas Huth GEN_PRIV; 5905fcf5ef2aSThomas Huth #else 5906fcf5ef2aSThomas Huth CHK_SV; 5907fcf5ef2aSThomas Huth 5908fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5909fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5910fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5911fcf5ef2aSThomas Huth } 5912fcf5ef2aSThomas Huth 5913fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5914fcf5ef2aSThomas Huth { 5915fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5916fcf5ef2aSThomas Huth GEN_PRIV; 5917fcf5ef2aSThomas Huth #else 5918fcf5ef2aSThomas Huth CHK_SV; 5919fcf5ef2aSThomas Huth 5920fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5921fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5922fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5923fcf5ef2aSThomas Huth } 5924fcf5ef2aSThomas Huth 5925fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5926fcf5ef2aSThomas Huth { 5927fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5928fcf5ef2aSThomas Huth GEN_PRIV; 5929fcf5ef2aSThomas Huth #else 5930fcf5ef2aSThomas Huth CHK_SV; 5931fcf5ef2aSThomas Huth 5932fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5933fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5934fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5935fcf5ef2aSThomas Huth } 5936fcf5ef2aSThomas Huth 5937fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5938fcf5ef2aSThomas Huth { 5939fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5940fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5941fcf5ef2aSThomas Huth #else 5942fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5943fcf5ef2aSThomas Huth 5944fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5945fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5946fcf5ef2aSThomas Huth return; 5947fcf5ef2aSThomas Huth } 5948fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5949fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5950fcf5ef2aSThomas Huth l1 = gen_new_label(); 5951fcf5ef2aSThomas Huth l2 = gen_new_label(); 5952fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5953fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5954efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5955fcf5ef2aSThomas Huth tcg_gen_br(l2); 5956fcf5ef2aSThomas Huth gen_set_label(l1); 5957fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5958fcf5ef2aSThomas Huth gen_set_label(l2); 5959fcf5ef2aSThomas Huth #endif 5960fcf5ef2aSThomas Huth } 5961fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5962fcf5ef2aSThomas Huth 5963fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5964fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5965fcf5ef2aSThomas Huth 5966fcf5ef2aSThomas Huth /* tlbia */ 5967fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5968fcf5ef2aSThomas Huth { 5969fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5970fcf5ef2aSThomas Huth GEN_PRIV; 5971fcf5ef2aSThomas Huth #else 5972fcf5ef2aSThomas Huth CHK_HV; 5973fcf5ef2aSThomas Huth 5974fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5975fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5976fcf5ef2aSThomas Huth } 5977fcf5ef2aSThomas Huth 5978fcf5ef2aSThomas Huth /* tlbiel */ 5979fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5980fcf5ef2aSThomas Huth { 5981fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5982fcf5ef2aSThomas Huth GEN_PRIV; 5983fcf5ef2aSThomas Huth #else 5984fcf5ef2aSThomas Huth CHK_SV; 5985fcf5ef2aSThomas Huth 5986fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5987fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5988fcf5ef2aSThomas Huth } 5989fcf5ef2aSThomas Huth 5990fcf5ef2aSThomas Huth /* tlbie */ 5991fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5992fcf5ef2aSThomas Huth { 5993fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5994fcf5ef2aSThomas Huth GEN_PRIV; 5995fcf5ef2aSThomas Huth #else 5996fcf5ef2aSThomas Huth TCGv_i32 t1; 5997c6fd28fdSSuraj Jitindar Singh 5998c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 599991c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 6000c6fd28fdSSuraj Jitindar Singh } else { 6001c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 6002c6fd28fdSSuraj Jitindar Singh } 6003fcf5ef2aSThomas Huth 6004fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 6005fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6006fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 6007fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 6008fcf5ef2aSThomas Huth tcg_temp_free(t0); 6009fcf5ef2aSThomas Huth } else { 6010fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6011fcf5ef2aSThomas Huth } 6012fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 6013fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6014fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 6015fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6016fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6017fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6018fcf5ef2aSThomas Huth } 6019fcf5ef2aSThomas Huth 6020fcf5ef2aSThomas Huth /* tlbsync */ 6021fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 6022fcf5ef2aSThomas Huth { 6023fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6024fcf5ef2aSThomas Huth GEN_PRIV; 6025fcf5ef2aSThomas Huth #else 602691c60f12SCédric Le Goater 602791c60f12SCédric Le Goater if (ctx->gtse) { 602891c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 602991c60f12SCédric Le Goater } else { 603091c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 603191c60f12SCédric Le Goater } 6032fcf5ef2aSThomas Huth 6033fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 6034fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 6035fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 6036fcf5ef2aSThomas Huth } 6037fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6038fcf5ef2aSThomas Huth } 6039fcf5ef2aSThomas Huth 6040fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6041fcf5ef2aSThomas Huth /* slbia */ 6042fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 6043fcf5ef2aSThomas Huth { 6044fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6045fcf5ef2aSThomas Huth GEN_PRIV; 6046fcf5ef2aSThomas Huth #else 60470418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 60480418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 60490418bf78SNicholas Piggin 6050fcf5ef2aSThomas Huth CHK_SV; 6051fcf5ef2aSThomas Huth 60520418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 60533119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 6054fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6055fcf5ef2aSThomas Huth } 6056fcf5ef2aSThomas Huth 6057fcf5ef2aSThomas Huth /* slbie */ 6058fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 6059fcf5ef2aSThomas Huth { 6060fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6061fcf5ef2aSThomas Huth GEN_PRIV; 6062fcf5ef2aSThomas Huth #else 6063fcf5ef2aSThomas Huth CHK_SV; 6064fcf5ef2aSThomas Huth 6065fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6066fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6067fcf5ef2aSThomas Huth } 6068a63f1dfcSNikunj A Dadhania 6069a63f1dfcSNikunj A Dadhania /* slbieg */ 6070a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 6071a63f1dfcSNikunj A Dadhania { 6072a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 6073a63f1dfcSNikunj A Dadhania GEN_PRIV; 6074a63f1dfcSNikunj A Dadhania #else 6075a63f1dfcSNikunj A Dadhania CHK_SV; 6076a63f1dfcSNikunj A Dadhania 6077a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6078a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 6079a63f1dfcSNikunj A Dadhania } 6080a63f1dfcSNikunj A Dadhania 608162d897caSNikunj A Dadhania /* slbsync */ 608262d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 608362d897caSNikunj A Dadhania { 608462d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 608562d897caSNikunj A Dadhania GEN_PRIV; 608662d897caSNikunj A Dadhania #else 608762d897caSNikunj A Dadhania CHK_SV; 608862d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 608962d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 609062d897caSNikunj A Dadhania } 609162d897caSNikunj A Dadhania 6092fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6093fcf5ef2aSThomas Huth 6094fcf5ef2aSThomas Huth /*** External control ***/ 6095fcf5ef2aSThomas Huth /* Optional: */ 6096fcf5ef2aSThomas Huth 6097fcf5ef2aSThomas Huth /* eciwx */ 6098fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 6099fcf5ef2aSThomas Huth { 6100fcf5ef2aSThomas Huth TCGv t0; 6101fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6102fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6103fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6104fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6105c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6106c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6107fcf5ef2aSThomas Huth tcg_temp_free(t0); 6108fcf5ef2aSThomas Huth } 6109fcf5ef2aSThomas Huth 6110fcf5ef2aSThomas Huth /* ecowx */ 6111fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 6112fcf5ef2aSThomas Huth { 6113fcf5ef2aSThomas Huth TCGv t0; 6114fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6115fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6116fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6117fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6118c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6119c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6120fcf5ef2aSThomas Huth tcg_temp_free(t0); 6121fcf5ef2aSThomas Huth } 6122fcf5ef2aSThomas Huth 6123fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 6124fcf5ef2aSThomas Huth 6125fcf5ef2aSThomas Huth /* abs - abs. */ 6126fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 6127fcf5ef2aSThomas Huth { 6128fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6129fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6130fe21b785SRichard Henderson 6131fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6132efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6133fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6134fcf5ef2aSThomas Huth } 6135efe843d8SDavid Gibson } 6136fcf5ef2aSThomas Huth 6137fcf5ef2aSThomas Huth /* abso - abso. */ 6138fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 6139fcf5ef2aSThomas Huth { 6140fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6141fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6142fe21b785SRichard Henderson 6143fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 6144fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6145fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 6146efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6147fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6148fcf5ef2aSThomas Huth } 6149efe843d8SDavid Gibson } 6150fcf5ef2aSThomas Huth 6151fcf5ef2aSThomas Huth /* clcs */ 6152fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 6153fcf5ef2aSThomas Huth { 6154fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 6155fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6156fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6157fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 6158fcf5ef2aSThomas Huth } 6159fcf5ef2aSThomas Huth 6160fcf5ef2aSThomas Huth /* div - div. */ 6161fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 6162fcf5ef2aSThomas Huth { 6163fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6164fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6165efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6166fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6167fcf5ef2aSThomas Huth } 6168efe843d8SDavid Gibson } 6169fcf5ef2aSThomas Huth 6170fcf5ef2aSThomas Huth /* divo - divo. */ 6171fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 6172fcf5ef2aSThomas Huth { 6173fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6174fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6175efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6176fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6177fcf5ef2aSThomas Huth } 6178efe843d8SDavid Gibson } 6179fcf5ef2aSThomas Huth 6180fcf5ef2aSThomas Huth /* divs - divs. */ 6181fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 6182fcf5ef2aSThomas Huth { 6183fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6184fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6185efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6186fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6187fcf5ef2aSThomas Huth } 6188efe843d8SDavid Gibson } 6189fcf5ef2aSThomas Huth 6190fcf5ef2aSThomas Huth /* divso - divso. */ 6191fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 6192fcf5ef2aSThomas Huth { 6193fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 6194fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6195efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6196fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6197fcf5ef2aSThomas Huth } 6198efe843d8SDavid Gibson } 6199fcf5ef2aSThomas Huth 6200fcf5ef2aSThomas Huth /* doz - doz. */ 6201fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 6202fcf5ef2aSThomas Huth { 6203fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6204fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6205efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6206efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6207efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 6208efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 6209fcf5ef2aSThomas Huth tcg_gen_br(l2); 6210fcf5ef2aSThomas Huth gen_set_label(l1); 6211fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6212fcf5ef2aSThomas Huth gen_set_label(l2); 6213efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6214fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6215fcf5ef2aSThomas Huth } 6216efe843d8SDavid Gibson } 6217fcf5ef2aSThomas Huth 6218fcf5ef2aSThomas Huth /* dozo - dozo. */ 6219fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 6220fcf5ef2aSThomas Huth { 6221fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6222fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6223fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6224fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6225fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6226fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6227fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6228efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6229efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6230fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6231fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6232fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 6233fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6234fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 6235fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6236fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6237fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6238fcf5ef2aSThomas Huth tcg_gen_br(l2); 6239fcf5ef2aSThomas Huth gen_set_label(l1); 6240fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6241fcf5ef2aSThomas Huth gen_set_label(l2); 6242fcf5ef2aSThomas Huth tcg_temp_free(t0); 6243fcf5ef2aSThomas Huth tcg_temp_free(t1); 6244fcf5ef2aSThomas Huth tcg_temp_free(t2); 6245efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6246fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6247fcf5ef2aSThomas Huth } 6248efe843d8SDavid Gibson } 6249fcf5ef2aSThomas Huth 6250fcf5ef2aSThomas Huth /* dozi */ 6251fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 6252fcf5ef2aSThomas Huth { 6253fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 6254fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6255fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6256fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 6257fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 6258fcf5ef2aSThomas Huth tcg_gen_br(l2); 6259fcf5ef2aSThomas Huth gen_set_label(l1); 6260fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6261fcf5ef2aSThomas Huth gen_set_label(l2); 6262efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6263fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6264fcf5ef2aSThomas Huth } 6265efe843d8SDavid Gibson } 6266fcf5ef2aSThomas Huth 6267fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 6268fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 6269fcf5ef2aSThomas Huth { 6270fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6271fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 6272fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 6273fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 6274fcf5ef2aSThomas Huth 6275fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6276fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 6277fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6278fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 6279fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 6280fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 6281fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 6282efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6283fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 6284efe843d8SDavid Gibson } 6285fcf5ef2aSThomas Huth tcg_temp_free(t0); 6286fcf5ef2aSThomas Huth } 6287fcf5ef2aSThomas Huth 6288fcf5ef2aSThomas Huth /* maskg - maskg. */ 6289fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 6290fcf5ef2aSThomas Huth { 6291fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6292fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6293fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6294fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6295fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 6296fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 6297fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6298fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 6299fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 6300fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 6301fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 6302fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 6303fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 6304fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6305fcf5ef2aSThomas Huth gen_set_label(l1); 6306fcf5ef2aSThomas Huth tcg_temp_free(t0); 6307fcf5ef2aSThomas Huth tcg_temp_free(t1); 6308fcf5ef2aSThomas Huth tcg_temp_free(t2); 6309fcf5ef2aSThomas Huth tcg_temp_free(t3); 6310efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6311fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6312fcf5ef2aSThomas Huth } 6313efe843d8SDavid Gibson } 6314fcf5ef2aSThomas Huth 6315fcf5ef2aSThomas Huth /* maskir - maskir. */ 6316fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 6317fcf5ef2aSThomas Huth { 6318fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6319fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6320fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6321fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6322fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6323fcf5ef2aSThomas Huth tcg_temp_free(t0); 6324fcf5ef2aSThomas Huth tcg_temp_free(t1); 6325efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6326fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6327fcf5ef2aSThomas Huth } 6328efe843d8SDavid Gibson } 6329fcf5ef2aSThomas Huth 6330fcf5ef2aSThomas Huth /* mul - mul. */ 6331fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 6332fcf5ef2aSThomas Huth { 6333fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6334fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6335fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6336fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6337fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6338fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6339fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6340fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6341fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6342fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6343fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6344fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6345fcf5ef2aSThomas Huth tcg_temp_free(t2); 6346efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6347fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6348fcf5ef2aSThomas Huth } 6349efe843d8SDavid Gibson } 6350fcf5ef2aSThomas Huth 6351fcf5ef2aSThomas Huth /* mulo - mulo. */ 6352fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6353fcf5ef2aSThomas Huth { 6354fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6355fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6356fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6357fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6358fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6359fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6360fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6361fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6362fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6363fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6364fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6365fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6366fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6367fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6368fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6369fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6370fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6371fcf5ef2aSThomas Huth gen_set_label(l1); 6372fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6373fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6374fcf5ef2aSThomas Huth tcg_temp_free(t2); 6375efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6376fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6377fcf5ef2aSThomas Huth } 6378efe843d8SDavid Gibson } 6379fcf5ef2aSThomas Huth 6380fcf5ef2aSThomas Huth /* nabs - nabs. */ 6381fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6382fcf5ef2aSThomas Huth { 6383fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6384fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6385fe21b785SRichard Henderson 6386fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6387fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6388efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6389fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6390fcf5ef2aSThomas Huth } 6391efe843d8SDavid Gibson } 6392fcf5ef2aSThomas Huth 6393fcf5ef2aSThomas Huth /* nabso - nabso. */ 6394fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6395fcf5ef2aSThomas Huth { 6396fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6397fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6398fe21b785SRichard Henderson 6399fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6400fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6401fcf5ef2aSThomas Huth /* nabs never overflows */ 6402fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6403efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6404fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6405fcf5ef2aSThomas Huth } 6406efe843d8SDavid Gibson } 6407fcf5ef2aSThomas Huth 6408fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6409fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6410fcf5ef2aSThomas Huth { 6411fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6412fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6413fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6414fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6415fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6416fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6417efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6418efe843d8SDavid Gibson ~MASK(mb, me)); 6419fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6420fcf5ef2aSThomas Huth tcg_temp_free(t0); 6421efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6422fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6423fcf5ef2aSThomas Huth } 6424efe843d8SDavid Gibson } 6425fcf5ef2aSThomas Huth 6426fcf5ef2aSThomas Huth /* rrib - rrib. */ 6427fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6428fcf5ef2aSThomas Huth { 6429fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6430fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6431fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6432fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6433fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6434fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6435fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6436fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6437fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6438fcf5ef2aSThomas Huth tcg_temp_free(t0); 6439fcf5ef2aSThomas Huth tcg_temp_free(t1); 6440efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6441fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6442fcf5ef2aSThomas Huth } 6443efe843d8SDavid Gibson } 6444fcf5ef2aSThomas Huth 6445fcf5ef2aSThomas Huth /* sle - sle. */ 6446fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6447fcf5ef2aSThomas Huth { 6448fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6449fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6450fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6451fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6452fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6453fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6454fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6455fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6456fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6457fcf5ef2aSThomas Huth tcg_temp_free(t0); 6458fcf5ef2aSThomas Huth tcg_temp_free(t1); 6459efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6460fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6461fcf5ef2aSThomas Huth } 6462efe843d8SDavid Gibson } 6463fcf5ef2aSThomas Huth 6464fcf5ef2aSThomas Huth /* sleq - sleq. */ 6465fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6466fcf5ef2aSThomas Huth { 6467fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6468fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6469fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6470fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6471fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6472fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6473fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6474fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6475fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6476fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6477fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6478fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6479fcf5ef2aSThomas Huth tcg_temp_free(t0); 6480fcf5ef2aSThomas Huth tcg_temp_free(t1); 6481fcf5ef2aSThomas Huth tcg_temp_free(t2); 6482efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6483fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6484fcf5ef2aSThomas Huth } 6485efe843d8SDavid Gibson } 6486fcf5ef2aSThomas Huth 6487fcf5ef2aSThomas Huth /* sliq - sliq. */ 6488fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6489fcf5ef2aSThomas Huth { 6490fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6491fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6492fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6493fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6494fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6495fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6496fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6497fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6498fcf5ef2aSThomas Huth tcg_temp_free(t0); 6499fcf5ef2aSThomas Huth tcg_temp_free(t1); 6500efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6501fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6502fcf5ef2aSThomas Huth } 6503efe843d8SDavid Gibson } 6504fcf5ef2aSThomas Huth 6505fcf5ef2aSThomas Huth /* slliq - slliq. */ 6506fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6507fcf5ef2aSThomas Huth { 6508fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6509fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6510fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6511fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6512fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6513fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6514fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6515fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6516fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6517fcf5ef2aSThomas Huth tcg_temp_free(t0); 6518fcf5ef2aSThomas Huth tcg_temp_free(t1); 6519efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6520fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6521fcf5ef2aSThomas Huth } 6522efe843d8SDavid Gibson } 6523fcf5ef2aSThomas Huth 6524fcf5ef2aSThomas Huth /* sllq - sllq. */ 6525fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6526fcf5ef2aSThomas Huth { 6527fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6528fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6529fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6530fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6531fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6532fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6533fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6534fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6535fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6536fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6537fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6538fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6539fcf5ef2aSThomas Huth tcg_gen_br(l2); 6540fcf5ef2aSThomas Huth gen_set_label(l1); 6541fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6542fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6543fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6544fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6545fcf5ef2aSThomas Huth gen_set_label(l2); 6546fcf5ef2aSThomas Huth tcg_temp_free(t0); 6547fcf5ef2aSThomas Huth tcg_temp_free(t1); 6548fcf5ef2aSThomas Huth tcg_temp_free(t2); 6549efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6550fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6551fcf5ef2aSThomas Huth } 6552efe843d8SDavid Gibson } 6553fcf5ef2aSThomas Huth 6554fcf5ef2aSThomas Huth /* slq - slq. */ 6555fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6556fcf5ef2aSThomas Huth { 6557fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6558fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6559fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6560fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6561fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6562fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6563fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6564fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6565fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6566fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6567fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6568fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6569fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6570fcf5ef2aSThomas Huth gen_set_label(l1); 6571fcf5ef2aSThomas Huth tcg_temp_free(t0); 6572fcf5ef2aSThomas Huth tcg_temp_free(t1); 6573efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6574fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6575fcf5ef2aSThomas Huth } 6576efe843d8SDavid Gibson } 6577fcf5ef2aSThomas Huth 6578fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6579fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6580fcf5ef2aSThomas Huth { 6581fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6582fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6583fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6584fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6585fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6586fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6587fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6588fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6589fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6590fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6591fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6592fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6593fcf5ef2aSThomas Huth gen_set_label(l1); 6594fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6595fcf5ef2aSThomas Huth tcg_temp_free(t0); 6596fcf5ef2aSThomas Huth tcg_temp_free(t1); 6597efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6598fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6599fcf5ef2aSThomas Huth } 6600efe843d8SDavid Gibson } 6601fcf5ef2aSThomas Huth 6602fcf5ef2aSThomas Huth /* sraq - sraq. */ 6603fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6604fcf5ef2aSThomas Huth { 6605fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6606fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6607fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6608fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6609fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6610fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6611fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6612fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6613fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6614fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6615fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6616fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6617fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6618fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6619fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6620fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6621fcf5ef2aSThomas Huth gen_set_label(l1); 6622fcf5ef2aSThomas Huth tcg_temp_free(t0); 6623fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6624fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6625fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6626fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6627fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6628fcf5ef2aSThomas Huth gen_set_label(l2); 6629fcf5ef2aSThomas Huth tcg_temp_free(t1); 6630fcf5ef2aSThomas Huth tcg_temp_free(t2); 6631efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6632fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6633fcf5ef2aSThomas Huth } 6634efe843d8SDavid Gibson } 6635fcf5ef2aSThomas Huth 6636fcf5ef2aSThomas Huth /* sre - sre. */ 6637fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6638fcf5ef2aSThomas Huth { 6639fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6640fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6641fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6642fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6643fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6644fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6645fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6646fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6647fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6648fcf5ef2aSThomas Huth tcg_temp_free(t0); 6649fcf5ef2aSThomas Huth tcg_temp_free(t1); 6650efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6651fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6652fcf5ef2aSThomas Huth } 6653efe843d8SDavid Gibson } 6654fcf5ef2aSThomas Huth 6655fcf5ef2aSThomas Huth /* srea - srea. */ 6656fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6657fcf5ef2aSThomas Huth { 6658fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6659fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6660fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6661fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6662fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6663fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6664fcf5ef2aSThomas Huth tcg_temp_free(t0); 6665fcf5ef2aSThomas Huth tcg_temp_free(t1); 6666efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6667fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6668fcf5ef2aSThomas Huth } 6669efe843d8SDavid Gibson } 6670fcf5ef2aSThomas Huth 6671fcf5ef2aSThomas Huth /* sreq */ 6672fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6673fcf5ef2aSThomas Huth { 6674fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6675fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6676fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6677fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6678fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6679fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6680fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6681fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6682fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6683fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6684fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6685fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6686fcf5ef2aSThomas Huth tcg_temp_free(t0); 6687fcf5ef2aSThomas Huth tcg_temp_free(t1); 6688fcf5ef2aSThomas Huth tcg_temp_free(t2); 6689efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6690fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6691fcf5ef2aSThomas Huth } 6692efe843d8SDavid Gibson } 6693fcf5ef2aSThomas Huth 6694fcf5ef2aSThomas Huth /* sriq */ 6695fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6696fcf5ef2aSThomas Huth { 6697fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6698fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6699fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6700fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6701fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6702fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6703fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6704fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6705fcf5ef2aSThomas Huth tcg_temp_free(t0); 6706fcf5ef2aSThomas Huth tcg_temp_free(t1); 6707efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6708fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6709fcf5ef2aSThomas Huth } 6710efe843d8SDavid Gibson } 6711fcf5ef2aSThomas Huth 6712fcf5ef2aSThomas Huth /* srliq */ 6713fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6714fcf5ef2aSThomas Huth { 6715fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6716fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6717fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6718fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6719fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6720fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6721fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6722fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6723fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6724fcf5ef2aSThomas Huth tcg_temp_free(t0); 6725fcf5ef2aSThomas Huth tcg_temp_free(t1); 6726efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6727fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6728fcf5ef2aSThomas Huth } 6729efe843d8SDavid Gibson } 6730fcf5ef2aSThomas Huth 6731fcf5ef2aSThomas Huth /* srlq */ 6732fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6733fcf5ef2aSThomas Huth { 6734fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6735fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6736fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6737fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6738fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6739fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6740fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6741fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6742fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6743fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6744fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6745fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6746fcf5ef2aSThomas Huth tcg_gen_br(l2); 6747fcf5ef2aSThomas Huth gen_set_label(l1); 6748fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6749fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6750fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6751fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6752fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6753fcf5ef2aSThomas Huth gen_set_label(l2); 6754fcf5ef2aSThomas Huth tcg_temp_free(t0); 6755fcf5ef2aSThomas Huth tcg_temp_free(t1); 6756fcf5ef2aSThomas Huth tcg_temp_free(t2); 6757efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6758fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6759fcf5ef2aSThomas Huth } 6760efe843d8SDavid Gibson } 6761fcf5ef2aSThomas Huth 6762fcf5ef2aSThomas Huth /* srq */ 6763fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6764fcf5ef2aSThomas Huth { 6765fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6766fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6767fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6768fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6769fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6770fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6771fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6772fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6773fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6774fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6775fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6776fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6777fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6778fcf5ef2aSThomas Huth gen_set_label(l1); 6779fcf5ef2aSThomas Huth tcg_temp_free(t0); 6780fcf5ef2aSThomas Huth tcg_temp_free(t1); 6781efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6782fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6783fcf5ef2aSThomas Huth } 6784efe843d8SDavid Gibson } 6785fcf5ef2aSThomas Huth 6786fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6787fcf5ef2aSThomas Huth 6788fcf5ef2aSThomas Huth /* dsa */ 6789fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6790fcf5ef2aSThomas Huth { 6791fcf5ef2aSThomas Huth /* XXX: TODO */ 6792fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6793fcf5ef2aSThomas Huth } 6794fcf5ef2aSThomas Huth 6795fcf5ef2aSThomas Huth /* esa */ 6796fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6797fcf5ef2aSThomas Huth { 6798fcf5ef2aSThomas Huth /* XXX: TODO */ 6799fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6800fcf5ef2aSThomas Huth } 6801fcf5ef2aSThomas Huth 6802fcf5ef2aSThomas Huth /* mfrom */ 6803fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6804fcf5ef2aSThomas Huth { 6805fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6806fcf5ef2aSThomas Huth GEN_PRIV; 6807fcf5ef2aSThomas Huth #else 6808fcf5ef2aSThomas Huth CHK_SV; 6809fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6810fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6811fcf5ef2aSThomas Huth } 6812fcf5ef2aSThomas Huth 6813fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6814fcf5ef2aSThomas Huth 6815fcf5ef2aSThomas Huth /* tlbld */ 6816fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6817fcf5ef2aSThomas Huth { 6818fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6819fcf5ef2aSThomas Huth GEN_PRIV; 6820fcf5ef2aSThomas Huth #else 6821fcf5ef2aSThomas Huth CHK_SV; 6822fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6823fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6824fcf5ef2aSThomas Huth } 6825fcf5ef2aSThomas Huth 6826fcf5ef2aSThomas Huth /* tlbli */ 6827fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6828fcf5ef2aSThomas Huth { 6829fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6830fcf5ef2aSThomas Huth GEN_PRIV; 6831fcf5ef2aSThomas Huth #else 6832fcf5ef2aSThomas Huth CHK_SV; 6833fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6834fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6835fcf5ef2aSThomas Huth } 6836fcf5ef2aSThomas Huth 6837fcf5ef2aSThomas Huth /* 74xx TLB management */ 6838fcf5ef2aSThomas Huth 6839fcf5ef2aSThomas Huth /* tlbld */ 6840fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6841fcf5ef2aSThomas Huth { 6842fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6843fcf5ef2aSThomas Huth GEN_PRIV; 6844fcf5ef2aSThomas Huth #else 6845fcf5ef2aSThomas Huth CHK_SV; 6846fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6847fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6848fcf5ef2aSThomas Huth } 6849fcf5ef2aSThomas Huth 6850fcf5ef2aSThomas Huth /* tlbli */ 6851fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6852fcf5ef2aSThomas Huth { 6853fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6854fcf5ef2aSThomas Huth GEN_PRIV; 6855fcf5ef2aSThomas Huth #else 6856fcf5ef2aSThomas Huth CHK_SV; 6857fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6858fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6859fcf5ef2aSThomas Huth } 6860fcf5ef2aSThomas Huth 6861fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6862fcf5ef2aSThomas Huth 6863fcf5ef2aSThomas Huth /* clf */ 6864fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6865fcf5ef2aSThomas Huth { 6866fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6867fcf5ef2aSThomas Huth } 6868fcf5ef2aSThomas Huth 6869fcf5ef2aSThomas Huth /* cli */ 6870fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6871fcf5ef2aSThomas Huth { 6872fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6873fcf5ef2aSThomas Huth GEN_PRIV; 6874fcf5ef2aSThomas Huth #else 6875fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6876fcf5ef2aSThomas Huth CHK_SV; 6877fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6878fcf5ef2aSThomas Huth } 6879fcf5ef2aSThomas Huth 6880fcf5ef2aSThomas Huth /* dclst */ 6881fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6882fcf5ef2aSThomas Huth { 6883fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6884fcf5ef2aSThomas Huth } 6885fcf5ef2aSThomas Huth 6886fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6887fcf5ef2aSThomas Huth { 6888fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6889fcf5ef2aSThomas Huth GEN_PRIV; 6890fcf5ef2aSThomas Huth #else 6891fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6892fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6893fcf5ef2aSThomas Huth TCGv t0; 6894fcf5ef2aSThomas Huth 6895fcf5ef2aSThomas Huth CHK_SV; 6896fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6897fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6898e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6899fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6900fcf5ef2aSThomas Huth tcg_temp_free(t0); 6901efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6902fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6903efe843d8SDavid Gibson } 6904fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6905fcf5ef2aSThomas Huth } 6906fcf5ef2aSThomas Huth 6907fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6908fcf5ef2aSThomas Huth { 6909fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6910fcf5ef2aSThomas Huth GEN_PRIV; 6911fcf5ef2aSThomas Huth #else 6912fcf5ef2aSThomas Huth TCGv t0; 6913fcf5ef2aSThomas Huth 6914fcf5ef2aSThomas Huth CHK_SV; 6915fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6916fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6917fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6918fcf5ef2aSThomas Huth tcg_temp_free(t0); 6919fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6920fcf5ef2aSThomas Huth } 6921fcf5ef2aSThomas Huth 6922fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6923fcf5ef2aSThomas Huth { 6924fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6925fcf5ef2aSThomas Huth GEN_PRIV; 6926fcf5ef2aSThomas Huth #else 6927fcf5ef2aSThomas Huth CHK_SV; 6928fcf5ef2aSThomas Huth 6929fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 6930fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6931fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6932fcf5ef2aSThomas Huth } 6933fcf5ef2aSThomas Huth 6934fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6935fcf5ef2aSThomas Huth 6936fcf5ef2aSThomas Huth /* BookE specific instructions */ 6937fcf5ef2aSThomas Huth 6938fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6939fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6940fcf5ef2aSThomas Huth { 6941fcf5ef2aSThomas Huth /* XXX: TODO */ 6942fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6943fcf5ef2aSThomas Huth } 6944fcf5ef2aSThomas Huth 6945fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6946fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6947fcf5ef2aSThomas Huth { 6948fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6949fcf5ef2aSThomas Huth GEN_PRIV; 6950fcf5ef2aSThomas Huth #else 6951fcf5ef2aSThomas Huth TCGv t0; 6952fcf5ef2aSThomas Huth 6953fcf5ef2aSThomas Huth CHK_SV; 6954fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6955fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6956fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6957fcf5ef2aSThomas Huth tcg_temp_free(t0); 6958fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6959fcf5ef2aSThomas Huth } 6960fcf5ef2aSThomas Huth 6961fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6962fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6963fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6964fcf5ef2aSThomas Huth { 6965fcf5ef2aSThomas Huth TCGv t0, t1; 6966fcf5ef2aSThomas Huth 6967fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6968fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6969fcf5ef2aSThomas Huth 6970fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6971fcf5ef2aSThomas Huth case 0x05: 6972fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6973fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6974fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6975fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6976fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6977fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6978fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6979fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6980fcf5ef2aSThomas Huth break; 6981fcf5ef2aSThomas Huth case 0x04: 6982fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6983fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6984fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6985fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6986fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6987fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6988fcf5ef2aSThomas Huth break; 6989fcf5ef2aSThomas Huth case 0x01: 6990fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6991fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6992fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6993fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6994fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6995fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6996fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6997fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6998fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6999fcf5ef2aSThomas Huth break; 7000fcf5ef2aSThomas Huth case 0x00: 7001fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 7002fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 7003fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7004fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 7005fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 7006fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 7007fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 7008fcf5ef2aSThomas Huth break; 7009fcf5ef2aSThomas Huth case 0x0D: 7010fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 7011fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 7012fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 7013fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 7014fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7015fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 7016fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 7017fcf5ef2aSThomas Huth break; 7018fcf5ef2aSThomas Huth case 0x0C: 7019fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 7020fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 7021fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7022fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 7023fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 7024fcf5ef2aSThomas Huth break; 7025fcf5ef2aSThomas Huth } 7026fcf5ef2aSThomas Huth if (opc2 & 0x04) { 7027fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 7028fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 7029fcf5ef2aSThomas Huth if (opc2 & 0x02) { 7030fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 7031fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 7032fcf5ef2aSThomas Huth } else { 7033fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 7034fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 7035fcf5ef2aSThomas Huth } 7036fcf5ef2aSThomas Huth 7037fcf5ef2aSThomas Huth if (opc3 & 0x12) { 7038fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 7039fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7040fcf5ef2aSThomas Huth 7041fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7042fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 7043fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 7044fcf5ef2aSThomas Huth } 7045fcf5ef2aSThomas Huth if (opc3 & 0x01) { 7046fcf5ef2aSThomas Huth /* Signed */ 7047fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 7048fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 7049fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 7050fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 7051fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7052fcf5ef2aSThomas Huth /* Saturate */ 7053fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 7054fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 7055fcf5ef2aSThomas Huth } 7056fcf5ef2aSThomas Huth } else { 7057fcf5ef2aSThomas Huth /* Unsigned */ 7058fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 7059fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7060fcf5ef2aSThomas Huth /* Saturate */ 7061fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 7062fcf5ef2aSThomas Huth } 7063fcf5ef2aSThomas Huth } 7064fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7065fcf5ef2aSThomas Huth /* Check overflow */ 7066fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 7067fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 7068fcf5ef2aSThomas Huth } 7069fcf5ef2aSThomas Huth gen_set_label(l1); 7070fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 7071fcf5ef2aSThomas Huth } 7072fcf5ef2aSThomas Huth } else { 7073fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 7074fcf5ef2aSThomas Huth } 7075fcf5ef2aSThomas Huth tcg_temp_free(t0); 7076fcf5ef2aSThomas Huth tcg_temp_free(t1); 7077fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 7078fcf5ef2aSThomas Huth /* Update Rc0 */ 7079fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 7080fcf5ef2aSThomas Huth } 7081fcf5ef2aSThomas Huth } 7082fcf5ef2aSThomas Huth 7083fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7084fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 7085fcf5ef2aSThomas Huth { \ 7086fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 7087fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 7088fcf5ef2aSThomas Huth } 7089fcf5ef2aSThomas Huth 7090fcf5ef2aSThomas Huth /* macchw - macchw. */ 7091fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 7092fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 7093fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 7094fcf5ef2aSThomas Huth /* macchws - macchws. */ 7095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 7096fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 7097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 7098fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 7099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 7100fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 7101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 7102fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 7103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 7104fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 7105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 7106fcf5ef2aSThomas Huth /* machhw - machhw. */ 7107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 7108fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 7109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 7110fcf5ef2aSThomas Huth /* machhws - machhws. */ 7111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 7112fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 7113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 7114fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 7115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 7116fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 7117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 7118fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 7119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 7120fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 7121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 7122fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 7123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 7124fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 7125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 7126fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 7127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 7128fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 7129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 7130fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 7131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 7132fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 7133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 7134fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 7135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 7136fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 7137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 7138fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 7139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 7140fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 7141fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 7142fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 7143fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 7144fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 7145fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 7146fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 7147fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 7148fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 7149fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 7150fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 7151fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 7152fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 7153fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 7154fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 7155fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 7156fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 7157fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 7158fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 7159fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 7160fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 7161fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 7162fcf5ef2aSThomas Huth 7163fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 7164fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 7165fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 7166fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 7167fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 7168fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 7169fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7170fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 7171fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7172fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 7173fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7174fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 7175fcf5ef2aSThomas Huth 7176fcf5ef2aSThomas Huth /* mfdcr */ 7177fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 7178fcf5ef2aSThomas Huth { 7179fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7180fcf5ef2aSThomas Huth GEN_PRIV; 7181fcf5ef2aSThomas Huth #else 7182fcf5ef2aSThomas Huth TCGv dcrn; 7183fcf5ef2aSThomas Huth 7184fcf5ef2aSThomas Huth CHK_SV; 7185fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7186fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 7187fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7188fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7189fcf5ef2aSThomas Huth } 7190fcf5ef2aSThomas Huth 7191fcf5ef2aSThomas Huth /* mtdcr */ 7192fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 7193fcf5ef2aSThomas Huth { 7194fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7195fcf5ef2aSThomas Huth GEN_PRIV; 7196fcf5ef2aSThomas Huth #else 7197fcf5ef2aSThomas Huth TCGv dcrn; 7198fcf5ef2aSThomas Huth 7199fcf5ef2aSThomas Huth CHK_SV; 7200fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7201fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 7202fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7203fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7204fcf5ef2aSThomas Huth } 7205fcf5ef2aSThomas Huth 7206fcf5ef2aSThomas Huth /* mfdcrx */ 7207fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7208fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 7209fcf5ef2aSThomas Huth { 7210fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7211fcf5ef2aSThomas Huth GEN_PRIV; 7212fcf5ef2aSThomas Huth #else 7213fcf5ef2aSThomas Huth CHK_SV; 7214fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7215fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7216fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7217fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7218fcf5ef2aSThomas Huth } 7219fcf5ef2aSThomas Huth 7220fcf5ef2aSThomas Huth /* mtdcrx */ 7221fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7222fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 7223fcf5ef2aSThomas Huth { 7224fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7225fcf5ef2aSThomas Huth GEN_PRIV; 7226fcf5ef2aSThomas Huth #else 7227fcf5ef2aSThomas Huth CHK_SV; 7228fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7229fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7230fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7231fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7232fcf5ef2aSThomas Huth } 7233fcf5ef2aSThomas Huth 7234fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 7235fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 7236fcf5ef2aSThomas Huth { 7237fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7238fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7239fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7240fcf5ef2aSThomas Huth } 7241fcf5ef2aSThomas Huth 7242fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 7243fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 7244fcf5ef2aSThomas Huth { 7245fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7246fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7247fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7248fcf5ef2aSThomas Huth } 7249fcf5ef2aSThomas Huth 7250fcf5ef2aSThomas Huth /* dccci */ 7251fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 7252fcf5ef2aSThomas Huth { 7253fcf5ef2aSThomas Huth CHK_SV; 7254fcf5ef2aSThomas Huth /* interpreted as no-op */ 7255fcf5ef2aSThomas Huth } 7256fcf5ef2aSThomas Huth 7257fcf5ef2aSThomas Huth /* dcread */ 7258fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 7259fcf5ef2aSThomas Huth { 7260fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7261fcf5ef2aSThomas Huth GEN_PRIV; 7262fcf5ef2aSThomas Huth #else 7263fcf5ef2aSThomas Huth TCGv EA, val; 7264fcf5ef2aSThomas Huth 7265fcf5ef2aSThomas Huth CHK_SV; 7266fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 7267fcf5ef2aSThomas Huth EA = tcg_temp_new(); 7268fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 7269fcf5ef2aSThomas Huth val = tcg_temp_new(); 7270fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 7271fcf5ef2aSThomas Huth tcg_temp_free(val); 7272fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 7273fcf5ef2aSThomas Huth tcg_temp_free(EA); 7274fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7275fcf5ef2aSThomas Huth } 7276fcf5ef2aSThomas Huth 7277fcf5ef2aSThomas Huth /* icbt */ 7278fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 7279fcf5ef2aSThomas Huth { 7280efe843d8SDavid Gibson /* 7281efe843d8SDavid Gibson * interpreted as no-op 7282efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7283efe843d8SDavid Gibson * does not generate any exception 7284fcf5ef2aSThomas Huth */ 7285fcf5ef2aSThomas Huth } 7286fcf5ef2aSThomas Huth 7287fcf5ef2aSThomas Huth /* iccci */ 7288fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 7289fcf5ef2aSThomas Huth { 7290fcf5ef2aSThomas Huth CHK_SV; 7291fcf5ef2aSThomas Huth /* interpreted as no-op */ 7292fcf5ef2aSThomas Huth } 7293fcf5ef2aSThomas Huth 7294fcf5ef2aSThomas Huth /* icread */ 7295fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 7296fcf5ef2aSThomas Huth { 7297fcf5ef2aSThomas Huth CHK_SV; 7298fcf5ef2aSThomas Huth /* interpreted as no-op */ 7299fcf5ef2aSThomas Huth } 7300fcf5ef2aSThomas Huth 7301fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 7302fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 7303fcf5ef2aSThomas Huth { 7304fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7305fcf5ef2aSThomas Huth GEN_PRIV; 7306fcf5ef2aSThomas Huth #else 7307fcf5ef2aSThomas Huth CHK_SV; 7308fcf5ef2aSThomas Huth /* Restore CPU state */ 7309fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 7310fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7311fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7312fcf5ef2aSThomas Huth } 7313fcf5ef2aSThomas Huth 7314fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 7315fcf5ef2aSThomas Huth { 7316fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7317fcf5ef2aSThomas Huth GEN_PRIV; 7318fcf5ef2aSThomas Huth #else 7319fcf5ef2aSThomas Huth CHK_SV; 7320fcf5ef2aSThomas Huth /* Restore CPU state */ 7321fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 7322fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7323fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7324fcf5ef2aSThomas Huth } 7325fcf5ef2aSThomas Huth 7326fcf5ef2aSThomas Huth /* BookE specific */ 7327fcf5ef2aSThomas Huth 7328fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7329fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 7330fcf5ef2aSThomas Huth { 7331fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7332fcf5ef2aSThomas Huth GEN_PRIV; 7333fcf5ef2aSThomas Huth #else 7334fcf5ef2aSThomas Huth CHK_SV; 7335fcf5ef2aSThomas Huth /* Restore CPU state */ 7336fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 7337fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7338fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7339fcf5ef2aSThomas Huth } 7340fcf5ef2aSThomas Huth 7341fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7342fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 7343fcf5ef2aSThomas Huth { 7344fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7345fcf5ef2aSThomas Huth GEN_PRIV; 7346fcf5ef2aSThomas Huth #else 7347fcf5ef2aSThomas Huth CHK_SV; 7348fcf5ef2aSThomas Huth /* Restore CPU state */ 7349fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 7350fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7351fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7352fcf5ef2aSThomas Huth } 7353fcf5ef2aSThomas Huth 7354fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7355fcf5ef2aSThomas Huth 7356fcf5ef2aSThomas Huth /* tlbre */ 7357fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7358fcf5ef2aSThomas Huth { 7359fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7360fcf5ef2aSThomas Huth GEN_PRIV; 7361fcf5ef2aSThomas Huth #else 7362fcf5ef2aSThomas Huth CHK_SV; 7363fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7364fcf5ef2aSThomas Huth case 0: 7365fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7366fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7367fcf5ef2aSThomas Huth break; 7368fcf5ef2aSThomas Huth case 1: 7369fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7370fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7371fcf5ef2aSThomas Huth break; 7372fcf5ef2aSThomas Huth default: 7373fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7374fcf5ef2aSThomas Huth break; 7375fcf5ef2aSThomas Huth } 7376fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7377fcf5ef2aSThomas Huth } 7378fcf5ef2aSThomas Huth 7379fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7380fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7381fcf5ef2aSThomas Huth { 7382fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7383fcf5ef2aSThomas Huth GEN_PRIV; 7384fcf5ef2aSThomas Huth #else 7385fcf5ef2aSThomas Huth TCGv t0; 7386fcf5ef2aSThomas Huth 7387fcf5ef2aSThomas Huth CHK_SV; 7388fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7389fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7390fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7391fcf5ef2aSThomas Huth tcg_temp_free(t0); 7392fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7393fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7394fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7395fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7396fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7397fcf5ef2aSThomas Huth gen_set_label(l1); 7398fcf5ef2aSThomas Huth } 7399fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7400fcf5ef2aSThomas Huth } 7401fcf5ef2aSThomas Huth 7402fcf5ef2aSThomas Huth /* tlbwe */ 7403fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7404fcf5ef2aSThomas Huth { 7405fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7406fcf5ef2aSThomas Huth GEN_PRIV; 7407fcf5ef2aSThomas Huth #else 7408fcf5ef2aSThomas Huth CHK_SV; 7409fcf5ef2aSThomas Huth 7410fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7411fcf5ef2aSThomas Huth case 0: 7412fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7413fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7414fcf5ef2aSThomas Huth break; 7415fcf5ef2aSThomas Huth case 1: 7416fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7417fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7418fcf5ef2aSThomas Huth break; 7419fcf5ef2aSThomas Huth default: 7420fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7421fcf5ef2aSThomas Huth break; 7422fcf5ef2aSThomas Huth } 7423fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7424fcf5ef2aSThomas Huth } 7425fcf5ef2aSThomas Huth 7426fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7427fcf5ef2aSThomas Huth 7428fcf5ef2aSThomas Huth /* tlbre */ 7429fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7430fcf5ef2aSThomas Huth { 7431fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7432fcf5ef2aSThomas Huth GEN_PRIV; 7433fcf5ef2aSThomas Huth #else 7434fcf5ef2aSThomas Huth CHK_SV; 7435fcf5ef2aSThomas Huth 7436fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7437fcf5ef2aSThomas Huth case 0: 7438fcf5ef2aSThomas Huth case 1: 7439fcf5ef2aSThomas Huth case 2: 7440fcf5ef2aSThomas Huth { 7441fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7442fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7443fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7444fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7445fcf5ef2aSThomas Huth } 7446fcf5ef2aSThomas Huth break; 7447fcf5ef2aSThomas Huth default: 7448fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7449fcf5ef2aSThomas Huth break; 7450fcf5ef2aSThomas Huth } 7451fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7452fcf5ef2aSThomas Huth } 7453fcf5ef2aSThomas Huth 7454fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7455fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7456fcf5ef2aSThomas Huth { 7457fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7458fcf5ef2aSThomas Huth GEN_PRIV; 7459fcf5ef2aSThomas Huth #else 7460fcf5ef2aSThomas Huth TCGv t0; 7461fcf5ef2aSThomas Huth 7462fcf5ef2aSThomas Huth CHK_SV; 7463fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7464fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7465fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7466fcf5ef2aSThomas Huth tcg_temp_free(t0); 7467fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7468fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7469fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7470fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7471fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7472fcf5ef2aSThomas Huth gen_set_label(l1); 7473fcf5ef2aSThomas Huth } 7474fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7475fcf5ef2aSThomas Huth } 7476fcf5ef2aSThomas Huth 7477fcf5ef2aSThomas Huth /* tlbwe */ 7478fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7479fcf5ef2aSThomas Huth { 7480fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7481fcf5ef2aSThomas Huth GEN_PRIV; 7482fcf5ef2aSThomas Huth #else 7483fcf5ef2aSThomas Huth CHK_SV; 7484fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7485fcf5ef2aSThomas Huth case 0: 7486fcf5ef2aSThomas Huth case 1: 7487fcf5ef2aSThomas Huth case 2: 7488fcf5ef2aSThomas Huth { 7489fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7490fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7491fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7492fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7493fcf5ef2aSThomas Huth } 7494fcf5ef2aSThomas Huth break; 7495fcf5ef2aSThomas Huth default: 7496fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7497fcf5ef2aSThomas Huth break; 7498fcf5ef2aSThomas Huth } 7499fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7500fcf5ef2aSThomas Huth } 7501fcf5ef2aSThomas Huth 7502fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7503fcf5ef2aSThomas Huth 7504fcf5ef2aSThomas Huth /* tlbre */ 7505fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7506fcf5ef2aSThomas Huth { 7507fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7508fcf5ef2aSThomas Huth GEN_PRIV; 7509fcf5ef2aSThomas Huth #else 7510fcf5ef2aSThomas Huth CHK_SV; 7511fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7512fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7513fcf5ef2aSThomas Huth } 7514fcf5ef2aSThomas Huth 7515fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7516fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7517fcf5ef2aSThomas Huth { 7518fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7519fcf5ef2aSThomas Huth GEN_PRIV; 7520fcf5ef2aSThomas Huth #else 7521fcf5ef2aSThomas Huth TCGv t0; 7522fcf5ef2aSThomas Huth 7523fcf5ef2aSThomas Huth CHK_SV; 7524fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7525fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7526fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7527fcf5ef2aSThomas Huth } else { 7528fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7529fcf5ef2aSThomas Huth } 7530fcf5ef2aSThomas Huth 7531fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7532fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7533fcf5ef2aSThomas Huth tcg_temp_free(t0); 7534fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7535fcf5ef2aSThomas Huth } 7536fcf5ef2aSThomas Huth 7537fcf5ef2aSThomas Huth /* tlbwe */ 7538fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7539fcf5ef2aSThomas Huth { 7540fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7541fcf5ef2aSThomas Huth GEN_PRIV; 7542fcf5ef2aSThomas Huth #else 7543fcf5ef2aSThomas Huth CHK_SV; 7544fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7545fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7546fcf5ef2aSThomas Huth } 7547fcf5ef2aSThomas Huth 7548fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7549fcf5ef2aSThomas Huth { 7550fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7551fcf5ef2aSThomas Huth GEN_PRIV; 7552fcf5ef2aSThomas Huth #else 7553fcf5ef2aSThomas Huth TCGv t0; 7554fcf5ef2aSThomas Huth 7555fcf5ef2aSThomas Huth CHK_SV; 7556fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7557fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7558fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7559fcf5ef2aSThomas Huth tcg_temp_free(t0); 7560fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7561fcf5ef2aSThomas Huth } 7562fcf5ef2aSThomas Huth 7563fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7564fcf5ef2aSThomas Huth { 7565fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7566fcf5ef2aSThomas Huth GEN_PRIV; 7567fcf5ef2aSThomas Huth #else 7568fcf5ef2aSThomas Huth TCGv t0; 7569fcf5ef2aSThomas Huth 7570fcf5ef2aSThomas Huth CHK_SV; 7571fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7572fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7573fcf5ef2aSThomas Huth 7574fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7575fcf5ef2aSThomas Huth case 0: 7576fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7577fcf5ef2aSThomas Huth break; 7578fcf5ef2aSThomas Huth case 1: 7579fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7580fcf5ef2aSThomas Huth break; 7581fcf5ef2aSThomas Huth case 3: 7582fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7583fcf5ef2aSThomas Huth break; 7584fcf5ef2aSThomas Huth default: 7585fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7586fcf5ef2aSThomas Huth break; 7587fcf5ef2aSThomas Huth } 7588fcf5ef2aSThomas Huth 7589fcf5ef2aSThomas Huth tcg_temp_free(t0); 7590fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7591fcf5ef2aSThomas Huth } 7592fcf5ef2aSThomas Huth 7593fcf5ef2aSThomas Huth 7594fcf5ef2aSThomas Huth /* wrtee */ 7595fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7596fcf5ef2aSThomas Huth { 7597fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7598fcf5ef2aSThomas Huth GEN_PRIV; 7599fcf5ef2aSThomas Huth #else 7600fcf5ef2aSThomas Huth TCGv t0; 7601fcf5ef2aSThomas Huth 7602fcf5ef2aSThomas Huth CHK_SV; 7603fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7604fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7605fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7606fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7607fcf5ef2aSThomas Huth tcg_temp_free(t0); 7608efe843d8SDavid Gibson /* 7609efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7610efe843d8SDavid Gibson * just set msr_ee to 1 7611fcf5ef2aSThomas Huth */ 7612fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7613fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7614fcf5ef2aSThomas Huth } 7615fcf5ef2aSThomas Huth 7616fcf5ef2aSThomas Huth /* wrteei */ 7617fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7618fcf5ef2aSThomas Huth { 7619fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7620fcf5ef2aSThomas Huth GEN_PRIV; 7621fcf5ef2aSThomas Huth #else 7622fcf5ef2aSThomas Huth CHK_SV; 7623fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7624fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7625fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7626fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7627fcf5ef2aSThomas Huth } else { 7628fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7629fcf5ef2aSThomas Huth } 7630fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7631fcf5ef2aSThomas Huth } 7632fcf5ef2aSThomas Huth 7633fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7634fcf5ef2aSThomas Huth 7635fcf5ef2aSThomas Huth /* dlmzb */ 7636fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7637fcf5ef2aSThomas Huth { 7638fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7639fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7640fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7641fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7642fcf5ef2aSThomas Huth } 7643fcf5ef2aSThomas Huth 7644fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7645fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7646fcf5ef2aSThomas Huth { 7647fcf5ef2aSThomas Huth /* interpreted as no-op */ 7648fcf5ef2aSThomas Huth } 7649fcf5ef2aSThomas Huth 7650fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7651fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7652fcf5ef2aSThomas Huth { 765327a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 765427a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 765527a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 765627a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 765727a3ea7eSBALATON Zoltan } 765827a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7659fcf5ef2aSThomas Huth } 7660fcf5ef2aSThomas Huth 7661fcf5ef2aSThomas Huth /* icbt */ 7662fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7663fcf5ef2aSThomas Huth { 7664efe843d8SDavid Gibson /* 7665efe843d8SDavid Gibson * interpreted as no-op 7666efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7667efe843d8SDavid Gibson * does not generate any exception 7668fcf5ef2aSThomas Huth */ 7669fcf5ef2aSThomas Huth } 7670fcf5ef2aSThomas Huth 7671fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7672fcf5ef2aSThomas Huth 7673fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7674fcf5ef2aSThomas Huth { 7675fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7676fcf5ef2aSThomas Huth GEN_PRIV; 7677fcf5ef2aSThomas Huth #else 7678ebca5e6dSCédric Le Goater CHK_HV; 7679d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76807af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76817af1e7b0SCédric Le Goater } else { 7682fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76837af1e7b0SCédric Le Goater } 7684fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7685fcf5ef2aSThomas Huth } 7686fcf5ef2aSThomas Huth 7687fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7688fcf5ef2aSThomas Huth { 7689fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7690fcf5ef2aSThomas Huth GEN_PRIV; 7691fcf5ef2aSThomas Huth #else 7692ebca5e6dSCédric Le Goater CHK_HV; 7693d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76947af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76957af1e7b0SCédric Le Goater } else { 7696fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76977af1e7b0SCédric Le Goater } 7698fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7699fcf5ef2aSThomas Huth } 7700fcf5ef2aSThomas Huth 77015ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 77025ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 77035ba7ba1dSCédric Le Goater { 77045ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 77055ba7ba1dSCédric Le Goater GEN_PRIV; 77065ba7ba1dSCédric Le Goater #else 77075ba7ba1dSCédric Le Goater CHK_SV; 77085ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77095ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77105ba7ba1dSCédric Le Goater } 77115ba7ba1dSCédric Le Goater 77125ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 77135ba7ba1dSCédric Le Goater { 77145ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 77155ba7ba1dSCédric Le Goater GEN_PRIV; 77165ba7ba1dSCédric Le Goater #else 77175ba7ba1dSCédric Le Goater CHK_SV; 77185ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77195ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77205ba7ba1dSCédric Le Goater } 77215ba7ba1dSCédric Le Goater #endif 77225ba7ba1dSCédric Le Goater 77237af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 77247af1e7b0SCédric Le Goater { 77257af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 77267af1e7b0SCédric Le Goater GEN_PRIV; 77277af1e7b0SCédric Le Goater #else 77287af1e7b0SCédric Le Goater CHK_HV; 77297af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77307af1e7b0SCédric Le Goater /* interpreted as no-op */ 77317af1e7b0SCédric Le Goater } 7732fcf5ef2aSThomas Huth 7733fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7734fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7735fcf5ef2aSThomas Huth { 7736fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7737fcf5ef2aSThomas Huth 7738fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7739fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7740fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7741fcf5ef2aSThomas Huth } 7742fcf5ef2aSThomas Huth 7743fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7744fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7745fcf5ef2aSThomas Huth { 7746fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7747fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7748fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7749fcf5ef2aSThomas Huth 7750fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7751fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7752fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7753fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7754fcf5ef2aSThomas Huth } else { 7755fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7756fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7757fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7758fcf5ef2aSThomas Huth } 7759fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7760fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7761fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7762fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7763fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7764fcf5ef2aSThomas Huth } 7765fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7766fcf5ef2aSThomas Huth 7767fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7768fcf5ef2aSThomas Huth { 7769fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7770fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7771fcf5ef2aSThomas Huth return; 7772fcf5ef2aSThomas Huth } 7773fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7774fcf5ef2aSThomas Huth } 7775fcf5ef2aSThomas Huth 7776fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7777fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7778fcf5ef2aSThomas Huth { \ 7779fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7780fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7781fcf5ef2aSThomas Huth return; \ 7782fcf5ef2aSThomas Huth } \ 7783efe843d8SDavid Gibson /* \ 7784efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7785fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7786fcf5ef2aSThomas Huth * \ 7787fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7788fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7789fcf5ef2aSThomas Huth */ \ 7790fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7791fcf5ef2aSThomas Huth } 7792fcf5ef2aSThomas Huth 7793fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7794fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7795fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7796fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7797fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7798fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7799fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7800efe843d8SDavid Gibson 7801b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7802b8b4576eSSuraj Jitindar Singh { 7803efe843d8SDavid Gibson /* Do Nothing */ 7804b8b4576eSSuraj Jitindar Singh } 7805fcf5ef2aSThomas Huth 780680b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 780780b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 780880b8c1eeSNikunj A Dadhania { \ 7809efe843d8SDavid Gibson /* \ 7810efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7811efe843d8SDavid Gibson * implementation of the copy paste facility \ 781280b8c1eeSNikunj A Dadhania */ \ 781380b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 781480b8c1eeSNikunj A Dadhania } 781580b8c1eeSNikunj A Dadhania 781680b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 781780b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 781880b8c1eeSNikunj A Dadhania 7819fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7820fcf5ef2aSThomas Huth { 7821fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7822fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7823fcf5ef2aSThomas Huth return; 7824fcf5ef2aSThomas Huth } 7825efe843d8SDavid Gibson /* 7826efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7827efe843d8SDavid Gibson * simple: 7828fcf5ef2aSThomas Huth * 7829fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7830fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7831fcf5ef2aSThomas Huth */ 7832fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7833fcf5ef2aSThomas Huth } 7834fcf5ef2aSThomas Huth 7835fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7836fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7837fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7838fcf5ef2aSThomas Huth { \ 7839fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7840fcf5ef2aSThomas Huth } 7841fcf5ef2aSThomas Huth 7842fcf5ef2aSThomas Huth #else 7843fcf5ef2aSThomas Huth 7844fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7845fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7846fcf5ef2aSThomas Huth { \ 7847fcf5ef2aSThomas Huth CHK_SV; \ 7848fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7849fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7850fcf5ef2aSThomas Huth return; \ 7851fcf5ef2aSThomas Huth } \ 7852efe843d8SDavid Gibson /* \ 7853efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7854fcf5ef2aSThomas Huth * simple: \ 7855fcf5ef2aSThomas Huth * \ 7856fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7857fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7858fcf5ef2aSThomas Huth */ \ 7859fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7860fcf5ef2aSThomas Huth } 7861fcf5ef2aSThomas Huth 7862fcf5ef2aSThomas Huth #endif 7863fcf5ef2aSThomas Huth 7864fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7865fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7866fcf5ef2aSThomas Huth 78671a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 78681a404c91SMark Cave-Ayland { 7869e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 78701a404c91SMark Cave-Ayland } 78711a404c91SMark Cave-Ayland 78721a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 78731a404c91SMark Cave-Ayland { 7874e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 78751a404c91SMark Cave-Ayland } 78761a404c91SMark Cave-Ayland 7877c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7878c4a18dbfSMark Cave-Ayland { 787937da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7880c4a18dbfSMark Cave-Ayland } 7881c4a18dbfSMark Cave-Ayland 7882c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7883c4a18dbfSMark Cave-Ayland { 788437da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7885c4a18dbfSMark Cave-Ayland } 7886c4a18dbfSMark Cave-Ayland 7887139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7888fcf5ef2aSThomas Huth 7889139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7890fcf5ef2aSThomas Huth 7891139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7892fcf5ef2aSThomas Huth 7893139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7894fcf5ef2aSThomas Huth 7895139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7896fcf5ef2aSThomas Huth 78975cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 78985cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 78995cb091a4SNikunj A Dadhania { 79005cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 79015cb091a4SNikunj A Dadhania case 0: /* lfdp */ 79025cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 79035cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 79045cb091a4SNikunj A Dadhania } 79055cb091a4SNikunj A Dadhania break; 79065cb091a4SNikunj A Dadhania case 2: /* lxsd */ 79075cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79085cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 79095cb091a4SNikunj A Dadhania } 79105cb091a4SNikunj A Dadhania break; 79115cb091a4SNikunj A Dadhania case 3: /* lxssp */ 79125cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79135cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 79145cb091a4SNikunj A Dadhania } 79155cb091a4SNikunj A Dadhania break; 79165cb091a4SNikunj A Dadhania } 79175cb091a4SNikunj A Dadhania return gen_invalid(ctx); 79185cb091a4SNikunj A Dadhania } 79195cb091a4SNikunj A Dadhania 7920d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7921e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7922e3001664SNikunj A Dadhania { 7923e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7924e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7925e3001664SNikunj A Dadhania case 1: /* lxv */ 7926d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7927d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7928d59ba583SNikunj A Dadhania } 7929e3001664SNikunj A Dadhania break; 7930e3001664SNikunj A Dadhania case 5: /* stxv */ 7931d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7932d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7933d59ba583SNikunj A Dadhania } 7934e3001664SNikunj A Dadhania break; 7935e3001664SNikunj A Dadhania } 7936e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7937e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7938e3001664SNikunj A Dadhania case 0: /* stfdp */ 7939e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7940e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7941e3001664SNikunj A Dadhania } 7942e3001664SNikunj A Dadhania break; 7943e3001664SNikunj A Dadhania case 2: /* stxsd */ 7944e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7945e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7946e3001664SNikunj A Dadhania } 7947e3001664SNikunj A Dadhania break; 7948e3001664SNikunj A Dadhania case 3: /* stxssp */ 7949e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7950e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7951e3001664SNikunj A Dadhania } 7952e3001664SNikunj A Dadhania break; 7953e3001664SNikunj A Dadhania } 7954e3001664SNikunj A Dadhania } 7955e3001664SNikunj A Dadhania return gen_invalid(ctx); 7956e3001664SNikunj A Dadhania } 7957e3001664SNikunj A Dadhania 79589d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79599d69cfa2SLijun Pan /* brd */ 79609d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 79619d69cfa2SLijun Pan { 79629d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79639d69cfa2SLijun Pan } 79649d69cfa2SLijun Pan 79659d69cfa2SLijun Pan /* brw */ 79669d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 79679d69cfa2SLijun Pan { 79689d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79699d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 79709d69cfa2SLijun Pan 79719d69cfa2SLijun Pan } 79729d69cfa2SLijun Pan 79739d69cfa2SLijun Pan /* brh */ 79749d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 79759d69cfa2SLijun Pan { 79769d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 79779d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 79789d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 79799d69cfa2SLijun Pan 79809d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 79819d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 79829d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 79839d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 79849d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 79859d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 79869d69cfa2SLijun Pan 79879d69cfa2SLijun Pan tcg_temp_free_i64(t0); 79889d69cfa2SLijun Pan tcg_temp_free_i64(t1); 79899d69cfa2SLijun Pan tcg_temp_free_i64(t2); 79909d69cfa2SLijun Pan } 79919d69cfa2SLijun Pan #endif 79929d69cfa2SLijun Pan 7993fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 79949d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79959d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 79969d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 79979d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 79989d69cfa2SLijun Pan #endif 7999fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 8000fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 8001fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 8002fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 8003fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 8004fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8005fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 8006fcf5ef2aSThomas Huth #endif 8007fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 8008fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 8009fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 8010fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8011fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8012fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8013fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8014fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 8015fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 8016fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 8017fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 8018fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 8019fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8020fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8021fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 8022fcf5ef2aSThomas Huth #endif 8023fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 8024fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 8025fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8026fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8027fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8028fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 8029fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 803080b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 8031b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 803280b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 8033fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 8034fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 8035fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8036fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8037fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8038fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8039fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 8040fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 8041fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 8042fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8043fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 8044fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 8045fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 8046fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 8047fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 8048fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 8049fcf5ef2aSThomas Huth #endif 8050fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8051fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8052fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8053fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 8054fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 8055fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 8056fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 8057fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8058fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 8059fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 8060fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 8061fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 8062fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 8063fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 8064fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8065fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 8066fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8067fcf5ef2aSThomas Huth #endif 8068fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8069fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 8070fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 8071fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 8072fcf5ef2aSThomas Huth #endif 80735cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 80745cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8075d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 8076e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8077fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8078fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8079fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 8080fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 8081fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 8082fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 8083c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 8084fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 8085fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8086fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8087fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 8088a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 8089a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 8090fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8091fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8092fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 8093fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8094a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 8095a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 8096fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 8097fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 8098fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 8099fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 8100fcf5ef2aSThomas Huth #endif 8101fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 8102fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 8103c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 8104fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8105fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8106fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 8107fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 8108fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 8109fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 8110fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 8111fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8112fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 81133c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 81143c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81153c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81163c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81173c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 81183c89b8d6SNicholas Piggin #endif 8119cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8120fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8121fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8122fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8123fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8124fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 8125fcf5ef2aSThomas Huth #endif 81263c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81273c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 81283c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 8129fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 8130fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8131fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8132fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 8133fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 8134fcf5ef2aSThomas Huth #endif 8135fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 8136fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 8137fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 8138fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 8139fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 8140fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 8141fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8142fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 8143fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 8144b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 8145fcf5ef2aSThomas Huth #endif 8146fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 8147fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 8148fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 814950728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8150fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 8151fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 815250728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8153fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 815450728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8155fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 815650728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8157fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 8158fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 815950728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8160fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 816199d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 8162fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 8163fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 816450728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8165fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 8166fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 8167fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 8168fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 8169fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 8170fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8171fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 8172fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 8173fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8174fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 8175fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 8176fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8177fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 8178fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 8179fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 8180fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 8181fcf5ef2aSThomas Huth #endif 8182fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 8183efe843d8SDavid Gibson /* 8184efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 8185efe843d8SDavid Gibson * different ISA versions 8186efe843d8SDavid Gibson */ 8187fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 8188fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 8189c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 8190c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 8191fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 8192fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8193fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 8194fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 8195a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 819662d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8197fcf5ef2aSThomas Huth #endif 8198fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 8199fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 8200fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 8201fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 8202fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 8203fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 8204fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 8205fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 8206fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 8207fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 8208fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 8209fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8210fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 8211fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 8212fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 8213fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 8214fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 8215fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 8216fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 8217fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8218fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 8219fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 8220fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 8221fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 8222fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 8223fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 8224fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 8225fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 8226fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 8227fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 8228fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 8229fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 8230fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 8231fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 8232fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 8233fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 8234fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 8235fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 8236fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 8237fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 8238fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 8239fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 8240fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 8241fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 8242fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 8243fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 8244fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 8245fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 8246fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 8247fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8248fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8249fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 8250fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 8251fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8252fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8253fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 8254fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 8255fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 8256fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 8257fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 8258fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 8259fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 8260fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 8261fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 8262fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 8263fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 8264fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 8265fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 8266fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 8267fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 8268fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 8269fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 8270fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 8271fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 8272fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 8273fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 8274fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 8275fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 8276fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 8277fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 8278fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 8279fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8280fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 8281fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8282fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 8283fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8284fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 8285fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8286fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 8287fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8288fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 8289fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 8290fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 8291fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 82927af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 82937af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 8294fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8295fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8296fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8297fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8298fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 829927a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8300fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8301fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 83020c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 83030c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8304fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8305fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8306fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8307fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8308fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8309fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8310fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8311fcf5ef2aSThomas Huth PPC2_ISA300), 8312fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 83135ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 83145ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 83155ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 83165ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8317fcf5ef2aSThomas Huth #endif 8318fcf5ef2aSThomas Huth 8319fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8320fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8321fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8322fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8323fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8324fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8325fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8326fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8327fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8328fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8329fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8330fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8331fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8332fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8333fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 83344c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8335fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8336fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8337fcf5ef2aSThomas Huth 8338fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8339fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8340fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8341fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8342fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8343fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8344fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8345fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8346fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8347fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8348fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8349fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8350fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8351fcf5ef2aSThomas Huth 8352fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8353fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8354fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8355fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8356fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8357fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8358fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8359fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8360fcf5ef2aSThomas Huth 8361fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8362fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8363fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8364fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8365fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8366fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8367fcf5ef2aSThomas Huth 8368fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8369fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8370fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8371fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8372fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8373fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8374fcf5ef2aSThomas Huth #endif 8375fcf5ef2aSThomas Huth 8376fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8377fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8378fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8379fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8380fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8381fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8382fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8383fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8384fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8385fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8386fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8387fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8388fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8389fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8390fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8391fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8392fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8393fcf5ef2aSThomas Huth 8394fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8395fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8396fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8397fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8398fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8399fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8400fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8401fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8402fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8403fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8404fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8405fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8406fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8407fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8408fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8409fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8410fcf5ef2aSThomas Huth #endif 8411fcf5ef2aSThomas Huth 8412fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8413fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8414fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8415fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8416fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8417fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8418fcf5ef2aSThomas Huth PPC_64B) 8419fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8420fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8421fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8422fcf5ef2aSThomas Huth PPC_64B), \ 8423fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8424fcf5ef2aSThomas Huth PPC_64B), \ 8425fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8426fcf5ef2aSThomas Huth PPC_64B) 8427fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8428fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8429fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8430fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8431fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8432fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8433fcf5ef2aSThomas Huth #endif 8434fcf5ef2aSThomas Huth 8435fcf5ef2aSThomas Huth #undef GEN_LD 8436fcf5ef2aSThomas Huth #undef GEN_LDU 8437fcf5ef2aSThomas Huth #undef GEN_LDUX 8438fcf5ef2aSThomas Huth #undef GEN_LDX_E 8439fcf5ef2aSThomas Huth #undef GEN_LDS 8440fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 8441fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8442fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 8443fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 8444fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 8445fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8446fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8447fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8448fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 8449fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 8450fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 8451fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 8452fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 8453fcf5ef2aSThomas Huth 8454fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 8455fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 8456fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 8457fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 8458fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8459fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 8460fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 8461fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 8462fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 8463fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8464fcf5ef2aSThomas Huth 8465fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8466fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8467fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8468fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8469fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8470fcf5ef2aSThomas Huth #endif 8471fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8472fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8473fcf5ef2aSThomas Huth 847450728199SRoman Kapl /* External PID based load */ 847550728199SRoman Kapl #undef GEN_LDEPX 847650728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 847750728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 847850728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 847950728199SRoman Kapl 848050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 848150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 848250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 848350728199SRoman Kapl #if defined(TARGET_PPC64) 848450728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 848550728199SRoman Kapl #endif 848650728199SRoman Kapl 8487fcf5ef2aSThomas Huth #undef GEN_ST 8488fcf5ef2aSThomas Huth #undef GEN_STU 8489fcf5ef2aSThomas Huth #undef GEN_STUX 8490fcf5ef2aSThomas Huth #undef GEN_STX_E 8491fcf5ef2aSThomas Huth #undef GEN_STS 8492fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8493fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8494fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8495fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8496fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8497fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8498fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 84990123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8500fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8501fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8502fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8503fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8504fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8505fcf5ef2aSThomas Huth 8506fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8507fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8508fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8509fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8510fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8511fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8512fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8513fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8514fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8515fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8516fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8517fcf5ef2aSThomas Huth #endif 8518fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8519fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8520fcf5ef2aSThomas Huth 852150728199SRoman Kapl #undef GEN_STEPX 852250728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 852350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 852450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 852550728199SRoman Kapl 852650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 852750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 852850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 852950728199SRoman Kapl #if defined(TARGET_PPC64) 853050728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 853150728199SRoman Kapl #endif 853250728199SRoman Kapl 8533fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8534fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8535fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8536fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8537fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8538fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8539fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8540fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8541fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8542fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8543fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8544fcf5ef2aSThomas Huth 8545fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8546fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8547fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8583fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8584fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8585fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8586fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8587fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8588fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8589fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8590fcf5ef2aSThomas Huth 8591fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8592fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8593fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8594fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8595fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8596fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8597fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8598fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8599fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8600fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8601fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8602fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8603fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8604fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8605fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8606fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8607fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8608fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8609fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8610fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8611fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8612fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8613fcf5ef2aSThomas Huth 8614139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8615fcf5ef2aSThomas Huth 8616139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8617fcf5ef2aSThomas Huth 8618139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8619fcf5ef2aSThomas Huth 8620139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8621fcf5ef2aSThomas Huth 8622139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8623fcf5ef2aSThomas Huth }; 8624fcf5ef2aSThomas Huth 86257468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 86267468e2c8SBruno Larsen (billionai) /* Opcode types */ 86277468e2c8SBruno Larsen (billionai) enum { 86287468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 86297468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 86307468e2c8SBruno Larsen (billionai) }; 86317468e2c8SBruno Larsen (billionai) 86327468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 86337468e2c8SBruno Larsen (billionai) 86347468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 86357468e2c8SBruno Larsen (billionai) { 86367468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 86377468e2c8SBruno Larsen (billionai) } 86387468e2c8SBruno Larsen (billionai) 86397468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 86407468e2c8SBruno Larsen (billionai) { 86417468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 86427468e2c8SBruno Larsen (billionai) } 86437468e2c8SBruno Larsen (billionai) 86447468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 86457468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 86467468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 86477468e2c8SBruno Larsen (billionai) { 86487468e2c8SBruno Larsen (billionai) int i; 86497468e2c8SBruno Larsen (billionai) 86507468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 86517468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86527468e2c8SBruno Larsen (billionai) } 86537468e2c8SBruno Larsen (billionai) } 86547468e2c8SBruno Larsen (billionai) 86557468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 86567468e2c8SBruno Larsen (billionai) { 86577468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 86587468e2c8SBruno Larsen (billionai) 86597468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 86607468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 86617468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 86627468e2c8SBruno Larsen (billionai) 86637468e2c8SBruno Larsen (billionai) return 0; 86647468e2c8SBruno Larsen (billionai) } 86657468e2c8SBruno Larsen (billionai) 86667468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 86677468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86687468e2c8SBruno Larsen (billionai) { 86697468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 86707468e2c8SBruno Larsen (billionai) return -1; 86717468e2c8SBruno Larsen (billionai) } 86727468e2c8SBruno Larsen (billionai) table[idx] = handler; 86737468e2c8SBruno Larsen (billionai) 86747468e2c8SBruno Larsen (billionai) return 0; 86757468e2c8SBruno Larsen (billionai) } 86767468e2c8SBruno Larsen (billionai) 86777468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 86787468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 86797468e2c8SBruno Larsen (billionai) { 86807468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 86817468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 86827468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 86837468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 86847468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 86857468e2c8SBruno Larsen (billionai) ppc_opcodes[idx]->oname, handler->oname); 86867468e2c8SBruno Larsen (billionai) #endif 86877468e2c8SBruno Larsen (billionai) return -1; 86887468e2c8SBruno Larsen (billionai) } 86897468e2c8SBruno Larsen (billionai) 86907468e2c8SBruno Larsen (billionai) return 0; 86917468e2c8SBruno Larsen (billionai) } 86927468e2c8SBruno Larsen (billionai) 86937468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 86947468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86957468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86967468e2c8SBruno Larsen (billionai) { 86977468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 86987468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 86997468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 87007468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 87017468e2c8SBruno Larsen (billionai) return -1; 87027468e2c8SBruno Larsen (billionai) } 87037468e2c8SBruno Larsen (billionai) } else { 87047468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 87057468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 87067468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 87077468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 87087468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 87097468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 87107468e2c8SBruno Larsen (billionai) #endif 87117468e2c8SBruno Larsen (billionai) return -1; 87127468e2c8SBruno Larsen (billionai) } 87137468e2c8SBruno Larsen (billionai) } 87147468e2c8SBruno Larsen (billionai) if (handler != NULL && 87157468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 87167468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 87177468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 87187468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 87197468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 87207468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 87217468e2c8SBruno Larsen (billionai) #endif 87227468e2c8SBruno Larsen (billionai) return -1; 87237468e2c8SBruno Larsen (billionai) } 87247468e2c8SBruno Larsen (billionai) 87257468e2c8SBruno Larsen (billionai) return 0; 87267468e2c8SBruno Larsen (billionai) } 87277468e2c8SBruno Larsen (billionai) 87287468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 87297468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87307468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 87317468e2c8SBruno Larsen (billionai) { 87327468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 87337468e2c8SBruno Larsen (billionai) } 87347468e2c8SBruno Larsen (billionai) 87357468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 87367468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87377468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 87387468e2c8SBruno Larsen (billionai) { 87397468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 87407468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 87417468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 87427468e2c8SBruno Larsen (billionai) return -1; 87437468e2c8SBruno Larsen (billionai) } 87447468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 87457468e2c8SBruno Larsen (billionai) handler) < 0) { 87467468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 87477468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 87487468e2c8SBruno Larsen (billionai) return -1; 87497468e2c8SBruno Larsen (billionai) } 87507468e2c8SBruno Larsen (billionai) 87517468e2c8SBruno Larsen (billionai) return 0; 87527468e2c8SBruno Larsen (billionai) } 87537468e2c8SBruno Larsen (billionai) 87547468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 87557468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87567468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 87577468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 87587468e2c8SBruno Larsen (billionai) { 87597468e2c8SBruno Larsen (billionai) opc_handler_t **table; 87607468e2c8SBruno Larsen (billionai) 87617468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 87627468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 87637468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 87647468e2c8SBruno Larsen (billionai) return -1; 87657468e2c8SBruno Larsen (billionai) } 87667468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 87677468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 87687468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 87697468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 87707468e2c8SBruno Larsen (billionai) return -1; 87717468e2c8SBruno Larsen (billionai) } 87727468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 87737468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 87747468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 87757468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 87767468e2c8SBruno Larsen (billionai) return -1; 87777468e2c8SBruno Larsen (billionai) } 87787468e2c8SBruno Larsen (billionai) return 0; 87797468e2c8SBruno Larsen (billionai) } 87807468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 87817468e2c8SBruno Larsen (billionai) { 87827468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 87837468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 87847468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 87857468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 87867468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 87877468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 87887468e2c8SBruno Larsen (billionai) return -1; 87897468e2c8SBruno Larsen (billionai) } 87907468e2c8SBruno Larsen (billionai) } else { 87917468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 87927468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 87937468e2c8SBruno Larsen (billionai) return -1; 87947468e2c8SBruno Larsen (billionai) } 87957468e2c8SBruno Larsen (billionai) } 87967468e2c8SBruno Larsen (billionai) } else { 87977468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 87987468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 87997468e2c8SBruno Larsen (billionai) return -1; 88007468e2c8SBruno Larsen (billionai) } 88017468e2c8SBruno Larsen (billionai) } 88027468e2c8SBruno Larsen (billionai) } else { 88037468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 88047468e2c8SBruno Larsen (billionai) return -1; 88057468e2c8SBruno Larsen (billionai) } 88067468e2c8SBruno Larsen (billionai) } 88077468e2c8SBruno Larsen (billionai) 88087468e2c8SBruno Larsen (billionai) return 0; 88097468e2c8SBruno Larsen (billionai) } 88107468e2c8SBruno Larsen (billionai) 88117468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 88127468e2c8SBruno Larsen (billionai) { 88137468e2c8SBruno Larsen (billionai) int i, count, tmp; 88147468e2c8SBruno Larsen (billionai) 88157468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 88167468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 88177468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 88187468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88197468e2c8SBruno Larsen (billionai) } 88207468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 88217468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 88227468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 88237468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 88247468e2c8SBruno Larsen (billionai) if (tmp == 0) { 88257468e2c8SBruno Larsen (billionai) free(table[i]); 88267468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88277468e2c8SBruno Larsen (billionai) } else { 88287468e2c8SBruno Larsen (billionai) count++; 88297468e2c8SBruno Larsen (billionai) } 88307468e2c8SBruno Larsen (billionai) } else { 88317468e2c8SBruno Larsen (billionai) count++; 88327468e2c8SBruno Larsen (billionai) } 88337468e2c8SBruno Larsen (billionai) } 88347468e2c8SBruno Larsen (billionai) } 88357468e2c8SBruno Larsen (billionai) 88367468e2c8SBruno Larsen (billionai) return count; 88377468e2c8SBruno Larsen (billionai) } 88387468e2c8SBruno Larsen (billionai) 88397468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 88407468e2c8SBruno Larsen (billionai) { 88417468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 88427468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 88437468e2c8SBruno Larsen (billionai) } 88447468e2c8SBruno Larsen (billionai) } 88457468e2c8SBruno Larsen (billionai) 88467468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 88477468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 88487468e2c8SBruno Larsen (billionai) { 88497468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 88507468e2c8SBruno Larsen (billionai) opcode_t *opc; 88517468e2c8SBruno Larsen (billionai) 88527468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 88537468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 88547468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 88557468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 88567468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 88577468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 88587468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 88597468e2c8SBruno Larsen (billionai) opc->opc3); 88607468e2c8SBruno Larsen (billionai) return; 88617468e2c8SBruno Larsen (billionai) } 88627468e2c8SBruno Larsen (billionai) } 88637468e2c8SBruno Larsen (billionai) } 88647468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 88657468e2c8SBruno Larsen (billionai) fflush(stdout); 88667468e2c8SBruno Larsen (billionai) fflush(stderr); 88677468e2c8SBruno Larsen (billionai) } 88687468e2c8SBruno Larsen (billionai) 88697468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 88707468e2c8SBruno Larsen (billionai) { 88717468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 88727468e2c8SBruno Larsen (billionai) int i, j, k; 88737468e2c8SBruno Larsen (billionai) 88747468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 88757468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 88767468e2c8SBruno Larsen (billionai) continue; 88777468e2c8SBruno Larsen (billionai) } 88787468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 88797468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 88807468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 88817468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 88827468e2c8SBruno Larsen (billionai) continue; 88837468e2c8SBruno Larsen (billionai) } 88847468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 88857468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 88867468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 88877468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 88887468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 88897468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 88907468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88917468e2c8SBruno Larsen (billionai) } 88927468e2c8SBruno Larsen (billionai) } 88937468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 88947468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88957468e2c8SBruno Larsen (billionai) } 88967468e2c8SBruno Larsen (billionai) } 88977468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 88987468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88997468e2c8SBruno Larsen (billionai) } 89007468e2c8SBruno Larsen (billionai) } 89017468e2c8SBruno Larsen (billionai) } 89027468e2c8SBruno Larsen (billionai) 89037468e2c8SBruno Larsen (billionai) #if defined(PPC_DUMP_CPU) 89047468e2c8SBruno Larsen (billionai) static void dump_ppc_insns(CPUPPCState *env) 89057468e2c8SBruno Larsen (billionai) { 89067468e2c8SBruno Larsen (billionai) opc_handler_t **table, *handler; 89077468e2c8SBruno Larsen (billionai) const char *p, *q; 89087468e2c8SBruno Larsen (billionai) uint8_t opc1, opc2, opc3, opc4; 89097468e2c8SBruno Larsen (billionai) 89107468e2c8SBruno Larsen (billionai) printf("Instructions set:\n"); 89117468e2c8SBruno Larsen (billionai) /* opc1 is 6 bits long */ 89127468e2c8SBruno Larsen (billionai) for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 89137468e2c8SBruno Larsen (billionai) table = env->opcodes; 89147468e2c8SBruno Larsen (billionai) handler = table[opc1]; 89157468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89167468e2c8SBruno Larsen (billionai) /* opc2 is 5 bits long */ 89177468e2c8SBruno Larsen (billionai) for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 89187468e2c8SBruno Larsen (billionai) table = env->opcodes; 89197468e2c8SBruno Larsen (billionai) handler = env->opcodes[opc1]; 89207468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89217468e2c8SBruno Larsen (billionai) handler = table[opc2]; 89227468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89237468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89247468e2c8SBruno Larsen (billionai) /* opc3 is 5 bits long */ 89257468e2c8SBruno Larsen (billionai) for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 89267468e2c8SBruno Larsen (billionai) opc3++) { 89277468e2c8SBruno Larsen (billionai) handler = table[opc3]; 89287468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89297468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89307468e2c8SBruno Larsen (billionai) /* opc4 is 5 bits long */ 89317468e2c8SBruno Larsen (billionai) for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 89327468e2c8SBruno Larsen (billionai) opc4++) { 89337468e2c8SBruno Larsen (billionai) handler = table[opc4]; 89347468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89357468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x %02x -- " 89367468e2c8SBruno Larsen (billionai) "(%02d %04d %02d) : %s\n", 89377468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc4, 89387468e2c8SBruno Larsen (billionai) opc1, (opc3 << 5) | opc2, opc4, 89397468e2c8SBruno Larsen (billionai) handler->oname); 89407468e2c8SBruno Larsen (billionai) } 89417468e2c8SBruno Larsen (billionai) } 89427468e2c8SBruno Larsen (billionai) } else { 89437468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89447468e2c8SBruno Larsen (billionai) /* Special hack to properly dump SPE insns */ 89457468e2c8SBruno Larsen (billionai) p = strchr(handler->oname, '_'); 89467468e2c8SBruno Larsen (billionai) if (p == NULL) { 89477468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x (%02d %04d) : " 89487468e2c8SBruno Larsen (billionai) "%s\n", 89497468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc1, 89507468e2c8SBruno Larsen (billionai) (opc3 << 5) | opc2, 89517468e2c8SBruno Larsen (billionai) handler->oname); 89527468e2c8SBruno Larsen (billionai) } else { 89537468e2c8SBruno Larsen (billionai) q = "speundef"; 89547468e2c8SBruno Larsen (billionai) if ((p - handler->oname) != strlen(q) 89557468e2c8SBruno Larsen (billionai) || (memcmp(handler->oname, q, strlen(q)) 89567468e2c8SBruno Larsen (billionai) != 0)) { 89577468e2c8SBruno Larsen (billionai) /* First instruction */ 89587468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x" 89597468e2c8SBruno Larsen (billionai) "(%02d %04d) : %.*s\n", 89607468e2c8SBruno Larsen (billionai) opc1, opc2 << 1, opc3, opc1, 89617468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1), 89627468e2c8SBruno Larsen (billionai) (int)(p - handler->oname), 89637468e2c8SBruno Larsen (billionai) handler->oname); 89647468e2c8SBruno Larsen (billionai) } 89657468e2c8SBruno Larsen (billionai) if (strcmp(p + 1, q) != 0) { 89667468e2c8SBruno Larsen (billionai) /* Second instruction */ 89677468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x " 89687468e2c8SBruno Larsen (billionai) "(%02d %04d) : %s\n", opc1, 89697468e2c8SBruno Larsen (billionai) (opc2 << 1) | 1, opc3, opc1, 89707468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1) | 1, 89717468e2c8SBruno Larsen (billionai) p + 1); 89727468e2c8SBruno Larsen (billionai) } 89737468e2c8SBruno Larsen (billionai) } 89747468e2c8SBruno Larsen (billionai) } 89757468e2c8SBruno Larsen (billionai) } 89767468e2c8SBruno Larsen (billionai) } 89777468e2c8SBruno Larsen (billionai) } else { 89787468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89797468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 89807468e2c8SBruno Larsen (billionai) opc1, opc2, opc1, opc2, handler->oname); 89817468e2c8SBruno Larsen (billionai) } 89827468e2c8SBruno Larsen (billionai) } 89837468e2c8SBruno Larsen (billionai) } 89847468e2c8SBruno Larsen (billionai) } else { 89857468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89867468e2c8SBruno Larsen (billionai) printf("INSN: %02x -- -- (%02d ----) : %s\n", 89877468e2c8SBruno Larsen (billionai) opc1, opc1, handler->oname); 89887468e2c8SBruno Larsen (billionai) } 89897468e2c8SBruno Larsen (billionai) } 89907468e2c8SBruno Larsen (billionai) } 89917468e2c8SBruno Larsen (billionai) } 89927468e2c8SBruno Larsen (billionai) #endif 89937468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 89947468e2c8SBruno Larsen (billionai) { 89957468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 89967468e2c8SBruno Larsen (billionai) 89977468e2c8SBruno Larsen (billionai) /* 89987468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 89997468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 90007468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 90017468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 90027468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 90037468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 90047468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 90057468e2c8SBruno Larsen (billionai) */ 90067468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 90077468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 90087468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 90097468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 90107468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 90117468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 90127468e2c8SBruno Larsen (billionai) } 90137468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 90147468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 90157468e2c8SBruno Larsen (billionai) return 0; 90167468e2c8SBruno Larsen (billionai) } 90177468e2c8SBruno Larsen (billionai) 90187468e2c8SBruno Larsen (billionai) 901911cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 9020fcf5ef2aSThomas Huth { 9021fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9022fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 9023fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 9024fcf5ef2aSThomas Huth int op1, op2, op3; 9025fcf5ef2aSThomas Huth 9026fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 9027fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 9028fcf5ef2aSThomas Huth handler = t1[op1]; 9029fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9030fcf5ef2aSThomas Huth t2 = ind_table(handler); 9031fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 9032fcf5ef2aSThomas Huth handler = t2[op2]; 9033fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9034fcf5ef2aSThomas Huth t3 = ind_table(handler); 9035fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 9036fcf5ef2aSThomas Huth handler = t3[op3]; 9037efe843d8SDavid Gibson if (handler->count == 0) { 9038fcf5ef2aSThomas Huth continue; 9039efe843d8SDavid Gibson } 904011cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 9041fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9042fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 9043fcf5ef2aSThomas Huth handler->oname, 9044fcf5ef2aSThomas Huth handler->count, handler->count); 9045fcf5ef2aSThomas Huth } 9046fcf5ef2aSThomas Huth } else { 9047efe843d8SDavid Gibson if (handler->count == 0) { 9048fcf5ef2aSThomas Huth continue; 9049efe843d8SDavid Gibson } 905011cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 9051fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9052fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 9053fcf5ef2aSThomas Huth handler->count, handler->count); 9054fcf5ef2aSThomas Huth } 9055fcf5ef2aSThomas Huth } 9056fcf5ef2aSThomas Huth } else { 9057efe843d8SDavid Gibson if (handler->count == 0) { 9058fcf5ef2aSThomas Huth continue; 9059efe843d8SDavid Gibson } 906011cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 9061fcf5ef2aSThomas Huth " %" PRId64 "\n", 9062fcf5ef2aSThomas Huth op1, op1, handler->oname, 9063fcf5ef2aSThomas Huth handler->count, handler->count); 9064fcf5ef2aSThomas Huth } 9065fcf5ef2aSThomas Huth } 9066fcf5ef2aSThomas Huth #endif 9067fcf5ef2aSThomas Huth } 9068fcf5ef2aSThomas Huth 9069624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 9070624cb07fSRichard Henderson { 9071624cb07fSRichard Henderson opc_handler_t **table, *handler; 9072624cb07fSRichard Henderson uint32_t inval; 9073624cb07fSRichard Henderson 9074624cb07fSRichard Henderson ctx->opcode = insn; 9075624cb07fSRichard Henderson 9076624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 9077624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9078624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 9079624cb07fSRichard Henderson 9080624cb07fSRichard Henderson table = cpu->opcodes; 9081624cb07fSRichard Henderson handler = table[opc1(insn)]; 9082624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9083624cb07fSRichard Henderson table = ind_table(handler); 9084624cb07fSRichard Henderson handler = table[opc2(insn)]; 9085624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9086624cb07fSRichard Henderson table = ind_table(handler); 9087624cb07fSRichard Henderson handler = table[opc3(insn)]; 9088624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9089624cb07fSRichard Henderson table = ind_table(handler); 9090624cb07fSRichard Henderson handler = table[opc4(insn)]; 9091624cb07fSRichard Henderson } 9092624cb07fSRichard Henderson } 9093624cb07fSRichard Henderson } 9094624cb07fSRichard Henderson 9095624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 9096624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 9097624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 9098624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 9099624cb07fSRichard Henderson TARGET_FMT_lx "\n", 9100624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9101624cb07fSRichard Henderson insn, ctx->cia); 9102624cb07fSRichard Henderson return false; 9103624cb07fSRichard Henderson } 9104624cb07fSRichard Henderson 9105624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 9106624cb07fSRichard Henderson && Rc(insn))) { 9107624cb07fSRichard Henderson inval = handler->inval2; 9108624cb07fSRichard Henderson } else { 9109624cb07fSRichard Henderson inval = handler->inval1; 9110624cb07fSRichard Henderson } 9111624cb07fSRichard Henderson 9112624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 9113624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 9114624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 9115624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 9116624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9117624cb07fSRichard Henderson insn, ctx->cia); 9118624cb07fSRichard Henderson return false; 9119624cb07fSRichard Henderson } 9120624cb07fSRichard Henderson 9121624cb07fSRichard Henderson handler->handler(ctx); 9122624cb07fSRichard Henderson return true; 9123624cb07fSRichard Henderson } 9124624cb07fSRichard Henderson 9125b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 9126fcf5ef2aSThomas Huth { 9127b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 91289c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 91292df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 9130b0c2d521SEmilio G. Cota int bound; 9131fcf5ef2aSThomas Huth 9132b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 9133b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 91342df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 9135d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 91362df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 91372df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 9138b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 9139b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 9140b0c2d521SEmilio G. Cota ctx->access_type = -1; 9141d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 91422df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 9143b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 91440e3bf489SRoman Kapl ctx->flags = env->flags; 9145fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 91462df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 9147b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 9148fcf5ef2aSThomas Huth #endif 9149e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 9150e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 9151d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 9152fcf5ef2aSThomas Huth 91532df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 91542df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 91552df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 91562df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 91572df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 9158f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 91592df4fe7aSRichard Henderson 9160b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 91612df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 91622df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 9163efe843d8SDavid Gibson } 91642df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 9165b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 9166efe843d8SDavid Gibson } 9167b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9168b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 9169fcf5ef2aSThomas Huth } 9170b0c2d521SEmilio G. Cota 9171b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 9172b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 9173fcf5ef2aSThomas Huth } 9174fcf5ef2aSThomas Huth 9175b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 9176b0c2d521SEmilio G. Cota { 9177b0c2d521SEmilio G. Cota } 9178fcf5ef2aSThomas Huth 9179b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 9180b0c2d521SEmilio G. Cota { 9181b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 9182b0c2d521SEmilio G. Cota } 9183b0c2d521SEmilio G. Cota 9184b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 9185b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 9186b0c2d521SEmilio G. Cota { 9187b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9188b0c2d521SEmilio G. Cota 9189b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9190efe843d8SDavid Gibson /* 9191efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 9192efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 9193efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 9194efe843d8SDavid Gibson * setting tb->size below does the right thing. 9195efe843d8SDavid Gibson */ 9196b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9197b0c2d521SEmilio G. Cota return true; 9198fcf5ef2aSThomas Huth } 9199fcf5ef2aSThomas Huth 9200b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 9201b0c2d521SEmilio G. Cota { 9202b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 920328876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 9204b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 9205624cb07fSRichard Henderson uint32_t insn; 9206624cb07fSRichard Henderson bool ok; 9207b0c2d521SEmilio G. Cota 9208fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 9209fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 9210b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 9211b0c2d521SEmilio G. Cota 92122c2bcb1bSRichard Henderson ctx->cia = ctx->base.pc_next; 9213624cb07fSRichard Henderson insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); 9214b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9215fcf5ef2aSThomas Huth 9216624cb07fSRichard Henderson ok = decode_legacy(cpu, ctx, insn); 9217624cb07fSRichard Henderson if (!ok) { 9218624cb07fSRichard Henderson gen_invalid(ctx); 9219fcf5ef2aSThomas Huth } 9220624cb07fSRichard Henderson 9221fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9222fcf5ef2aSThomas Huth handler->count++; 9223fcf5ef2aSThomas Huth #endif 9224*3d8a5b69SRichard Henderson 9225fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 9226b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 9227b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 9228b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 9229b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 9230*3d8a5b69SRichard Henderson ctx->exception != POWERPC_EXCP_BRANCH && 9231*3d8a5b69SRichard Henderson ctx->base.is_jmp != DISAS_NORETURN)) { 9232e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 92330e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 9234fcf5ef2aSThomas Huth } 9235b0c2d521SEmilio G. Cota 9236fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 9237b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 9238b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 9239b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 9240fcf5ef2aSThomas Huth } 9241b0c2d521SEmilio G. Cota 9242*3d8a5b69SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT 9243*3d8a5b69SRichard Henderson && ctx->exception != POWERPC_EXCP_NONE) { 9244*3d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 9245*3d8a5b69SRichard Henderson } 9246fcf5ef2aSThomas Huth } 9247b0c2d521SEmilio G. Cota 9248b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 9249b0c2d521SEmilio G. Cota { 9250b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9251b0c2d521SEmilio G. Cota 9252*3d8a5b69SRichard Henderson if (ctx->base.is_jmp == DISAS_NORETURN) { 9253*3d8a5b69SRichard Henderson return; 9254*3d8a5b69SRichard Henderson } 9255*3d8a5b69SRichard Henderson 9256b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 9257b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 9258b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 9259b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9260b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9261fcf5ef2aSThomas Huth } 9262fcf5ef2aSThomas Huth /* Generate the return instruction */ 926307ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 9264fcf5ef2aSThomas Huth } 9265fcf5ef2aSThomas Huth } 9266b0c2d521SEmilio G. Cota 9267b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 9268b0c2d521SEmilio G. Cota { 9269b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 9270b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 9271b0c2d521SEmilio G. Cota } 9272b0c2d521SEmilio G. Cota 9273b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 9274b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 9275b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 9276b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 9277b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 9278b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 9279b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 9280b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 9281b0c2d521SEmilio G. Cota }; 9282b0c2d521SEmilio G. Cota 92838b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 9284b0c2d521SEmilio G. Cota { 9285b0c2d521SEmilio G. Cota DisasContext ctx; 9286b0c2d521SEmilio G. Cota 92878b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 9288fcf5ef2aSThomas Huth } 9289fcf5ef2aSThomas Huth 9290fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 9291fcf5ef2aSThomas Huth target_ulong *data) 9292fcf5ef2aSThomas Huth { 9293fcf5ef2aSThomas Huth env->nip = data[0]; 9294fcf5ef2aSThomas Huth } 9295