1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth 41fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 42fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 43fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 46efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 47efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 157fcf5ef2aSThomas Huth uint32_t opcode; 158fcf5ef2aSThomas Huth uint32_t exception; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 177fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 178fcf5ef2aSThomas Huth int singlestep_enabled; 1790e3bf489SRoman Kapl uint32_t flags; 180fcf5ef2aSThomas Huth uint64_t insns_flags; 181fcf5ef2aSThomas Huth uint64_t insns_flags2; 182fcf5ef2aSThomas Huth }; 183fcf5ef2aSThomas Huth 184fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 185fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 186fcf5ef2aSThomas Huth { 187fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 188fcf5ef2aSThomas Huth return ctx->le_mode; 189fcf5ef2aSThomas Huth #else 190fcf5ef2aSThomas Huth return !ctx->le_mode; 191fcf5ef2aSThomas Huth #endif 192fcf5ef2aSThomas Huth } 193fcf5ef2aSThomas Huth 194fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 195fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 196fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 197fcf5ef2aSThomas Huth #else 198fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 199fcf5ef2aSThomas Huth #endif 200fcf5ef2aSThomas Huth 201fcf5ef2aSThomas Huth struct opc_handler_t { 202fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 203fcf5ef2aSThomas Huth uint32_t inval1; 204fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 205fcf5ef2aSThomas Huth uint32_t inval2; 206fcf5ef2aSThomas Huth /* instruction type */ 207fcf5ef2aSThomas Huth uint64_t type; 208fcf5ef2aSThomas Huth /* extended instruction type */ 209fcf5ef2aSThomas Huth uint64_t type2; 210fcf5ef2aSThomas Huth /* handler */ 211fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 212fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 213fcf5ef2aSThomas Huth const char *oname; 214fcf5ef2aSThomas Huth #endif 215fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 216fcf5ef2aSThomas Huth uint64_t count; 217fcf5ef2aSThomas Huth #endif 218fcf5ef2aSThomas Huth }; 219fcf5ef2aSThomas Huth 2200e3bf489SRoman Kapl /* SPR load/store helpers */ 2210e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2220e3bf489SRoman Kapl { 2230e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2240e3bf489SRoman Kapl } 2250e3bf489SRoman Kapl 2260e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2270e3bf489SRoman Kapl { 2280e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2290e3bf489SRoman Kapl } 2300e3bf489SRoman Kapl 231fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 232fcf5ef2aSThomas Huth { 233fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 234fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 235fcf5ef2aSThomas Huth ctx->access_type = access_type; 236fcf5ef2aSThomas Huth } 237fcf5ef2aSThomas Huth } 238fcf5ef2aSThomas Huth 239fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 240fcf5ef2aSThomas Huth { 241fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 242fcf5ef2aSThomas Huth nip = (uint32_t)nip; 243fcf5ef2aSThomas Huth } 244fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 245fcf5ef2aSThomas Huth } 246fcf5ef2aSThomas Huth 247fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 248fcf5ef2aSThomas Huth { 249fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 250fcf5ef2aSThomas Huth 251efe843d8SDavid Gibson /* 252efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 253efe843d8SDavid Gibson * faulting instruction 254fcf5ef2aSThomas Huth */ 255fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 256b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 257fcf5ef2aSThomas Huth } 258fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 259fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 260fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 261fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 262fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 263fcf5ef2aSThomas Huth ctx->exception = (excp); 264fcf5ef2aSThomas Huth } 265fcf5ef2aSThomas Huth 266fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 267fcf5ef2aSThomas Huth { 268fcf5ef2aSThomas Huth TCGv_i32 t0; 269fcf5ef2aSThomas Huth 270efe843d8SDavid Gibson /* 271efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 272efe843d8SDavid Gibson * faulting instruction 273fcf5ef2aSThomas Huth */ 274fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 275b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 278fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 279fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 280fcf5ef2aSThomas Huth ctx->exception = (excp); 281fcf5ef2aSThomas Huth } 282fcf5ef2aSThomas Huth 283fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 284fcf5ef2aSThomas Huth target_ulong nip) 285fcf5ef2aSThomas Huth { 286fcf5ef2aSThomas Huth TCGv_i32 t0; 287fcf5ef2aSThomas Huth 288fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 289fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 290fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 291fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 292fcf5ef2aSThomas Huth ctx->exception = (excp); 293fcf5ef2aSThomas Huth } 294fcf5ef2aSThomas Huth 295e150ac89SRoman Kapl /* 296e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 297e150ac89SRoman Kapl * SPR registers for this exception. 298e150ac89SRoman Kapl * 299e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 300e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3010e3bf489SRoman Kapl */ 302e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3030e3bf489SRoman Kapl { 3040e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3050e3bf489SRoman Kapl target_ulong dbsr = 0; 306e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3070e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 308e150ac89SRoman Kapl } else { 309e150ac89SRoman Kapl /* Must have been branch */ 3100e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3110e3bf489SRoman Kapl } 3120e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3130e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3140e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3150e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3160e3bf489SRoman Kapl tcg_temp_free(t0); 3170e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3180e3bf489SRoman Kapl } else { 319e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3200e3bf489SRoman Kapl } 3210e3bf489SRoman Kapl } 3220e3bf489SRoman Kapl 323fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 324fcf5ef2aSThomas Huth { 325fcf5ef2aSThomas Huth TCGv_i32 t0; 326fcf5ef2aSThomas Huth 327efe843d8SDavid Gibson /* 328efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 329efe843d8SDavid Gibson * faulting instruction 330fcf5ef2aSThomas Huth */ 331fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 332fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 333b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 334fcf5ef2aSThomas Huth } 335fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 336fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 337fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 338fcf5ef2aSThomas Huth } 339fcf5ef2aSThomas Huth 340fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 341fcf5ef2aSThomas Huth { 342fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 343fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 344fcf5ef2aSThomas Huth } 345fcf5ef2aSThomas Huth 346fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 347fcf5ef2aSThomas Huth { 348fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 349fcf5ef2aSThomas Huth } 350fcf5ef2aSThomas Huth 351fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 352fcf5ef2aSThomas Huth { 353fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 354fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 355fcf5ef2aSThomas Huth } 356fcf5ef2aSThomas Huth 357fcf5ef2aSThomas Huth /* Stop translation */ 358fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 359fcf5ef2aSThomas Huth { 360b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 361fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 362fcf5ef2aSThomas Huth } 363fcf5ef2aSThomas Huth 364fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 365fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 366fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 367fcf5ef2aSThomas Huth { 368fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 369fcf5ef2aSThomas Huth } 370fcf5ef2aSThomas Huth #endif 371fcf5ef2aSThomas Huth 372*37f219c8SBruno Larsen (billionai) /*****************************************************************************/ 373*37f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 374*37f219c8SBruno Larsen (billionai) 375*37f219c8SBruno Larsen (billionai) static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 376*37f219c8SBruno Larsen (billionai) { 377*37f219c8SBruno Larsen (billionai) #if 0 378*37f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 379*37f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 380*37f219c8SBruno Larsen (billionai) #endif 381*37f219c8SBruno Larsen (billionai) } 382*37f219c8SBruno Larsen (billionai) #define SPR_NOACCESS (&spr_noaccess) 383*37f219c8SBruno Larsen (billionai) 384*37f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 385*37f219c8SBruno Larsen (billionai) 386*37f219c8SBruno Larsen (billionai) /* 387*37f219c8SBruno Larsen (billionai) * Generic callbacks: 388*37f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 389*37f219c8SBruno Larsen (billionai) */ 390*37f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 391*37f219c8SBruno Larsen (billionai) { 392*37f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 393*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 394*37f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 395*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 396*37f219c8SBruno Larsen (billionai) #endif 397*37f219c8SBruno Larsen (billionai) } 398*37f219c8SBruno Larsen (billionai) 399*37f219c8SBruno Larsen (billionai) static void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 400*37f219c8SBruno Larsen (billionai) { 401*37f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 402*37f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 403*37f219c8SBruno Larsen (billionai) } 404*37f219c8SBruno Larsen (billionai) 405*37f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 406*37f219c8SBruno Larsen (billionai) { 407*37f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 408*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 409*37f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 410*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 411*37f219c8SBruno Larsen (billionai) #endif 412*37f219c8SBruno Larsen (billionai) } 413*37f219c8SBruno Larsen (billionai) 414*37f219c8SBruno Larsen (billionai) static void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 415*37f219c8SBruno Larsen (billionai) { 416*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 417*37f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 418*37f219c8SBruno Larsen (billionai) } 419*37f219c8SBruno Larsen (billionai) 420*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 421*37f219c8SBruno Larsen (billionai) static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 422*37f219c8SBruno Larsen (billionai) { 423*37f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 424*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 425*37f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 426*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 427*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 428*37f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 429*37f219c8SBruno Larsen (billionai) #else 430*37f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 431*37f219c8SBruno Larsen (billionai) #endif 432*37f219c8SBruno Larsen (billionai) } 433*37f219c8SBruno Larsen (billionai) 434*37f219c8SBruno Larsen (billionai) static void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 435*37f219c8SBruno Larsen (billionai) { 436*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 437*37f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 438*37f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 439*37f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 440*37f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 441*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 442*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 443*37f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 444*37f219c8SBruno Larsen (billionai) } 445*37f219c8SBruno Larsen (billionai) 446*37f219c8SBruno Larsen (billionai) static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 447*37f219c8SBruno Larsen (billionai) { 448*37f219c8SBruno Larsen (billionai) } 449*37f219c8SBruno Larsen (billionai) 450*37f219c8SBruno Larsen (billionai) #endif 451*37f219c8SBruno Larsen (billionai) 452*37f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 453*37f219c8SBruno Larsen (billionai) /* XER */ 454*37f219c8SBruno Larsen (billionai) static void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 455*37f219c8SBruno Larsen (billionai) { 456*37f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 457*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 458*37f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 459*37f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 460*37f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 461*37f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 462*37f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 463*37f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 464*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 465*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 466*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 467*37f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 468*37f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 469*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 470*37f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 471*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 472*37f219c8SBruno Larsen (billionai) } 473*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 474*37f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 475*37f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 476*37f219c8SBruno Larsen (billionai) } 477*37f219c8SBruno Larsen (billionai) 478*37f219c8SBruno Larsen (billionai) static void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 479*37f219c8SBruno Larsen (billionai) { 480*37f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 481*37f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 482*37f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 483*37f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 484*37f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 485*37f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 486*37f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 487*37f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 488*37f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 489*37f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 490*37f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 491*37f219c8SBruno Larsen (billionai) } 492*37f219c8SBruno Larsen (billionai) 493*37f219c8SBruno Larsen (billionai) /* LR */ 494*37f219c8SBruno Larsen (billionai) static void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 495*37f219c8SBruno Larsen (billionai) { 496*37f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 497*37f219c8SBruno Larsen (billionai) } 498*37f219c8SBruno Larsen (billionai) 499*37f219c8SBruno Larsen (billionai) static void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 500*37f219c8SBruno Larsen (billionai) { 501*37f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 502*37f219c8SBruno Larsen (billionai) } 503*37f219c8SBruno Larsen (billionai) 504*37f219c8SBruno Larsen (billionai) /* CFAR */ 505*37f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 506*37f219c8SBruno Larsen (billionai) static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 507*37f219c8SBruno Larsen (billionai) { 508*37f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 509*37f219c8SBruno Larsen (billionai) } 510*37f219c8SBruno Larsen (billionai) 511*37f219c8SBruno Larsen (billionai) static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 512*37f219c8SBruno Larsen (billionai) { 513*37f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 514*37f219c8SBruno Larsen (billionai) } 515*37f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 516*37f219c8SBruno Larsen (billionai) 517*37f219c8SBruno Larsen (billionai) /* CTR */ 518*37f219c8SBruno Larsen (billionai) static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 519*37f219c8SBruno Larsen (billionai) { 520*37f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 521*37f219c8SBruno Larsen (billionai) } 522*37f219c8SBruno Larsen (billionai) 523*37f219c8SBruno Larsen (billionai) static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 524*37f219c8SBruno Larsen (billionai) { 525*37f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 526*37f219c8SBruno Larsen (billionai) } 527*37f219c8SBruno Larsen (billionai) 528*37f219c8SBruno Larsen (billionai) /* User read access to SPR */ 529*37f219c8SBruno Larsen (billionai) /* USPRx */ 530*37f219c8SBruno Larsen (billionai) /* UMMCRx */ 531*37f219c8SBruno Larsen (billionai) /* UPMCx */ 532*37f219c8SBruno Larsen (billionai) /* USIA */ 533*37f219c8SBruno Larsen (billionai) /* UDECR */ 534*37f219c8SBruno Larsen (billionai) static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 535*37f219c8SBruno Larsen (billionai) { 536*37f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 537*37f219c8SBruno Larsen (billionai) } 538*37f219c8SBruno Larsen (billionai) 539*37f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 540*37f219c8SBruno Larsen (billionai) static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 541*37f219c8SBruno Larsen (billionai) { 542*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 543*37f219c8SBruno Larsen (billionai) } 544*37f219c8SBruno Larsen (billionai) #endif 545*37f219c8SBruno Larsen (billionai) 546*37f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 547*37f219c8SBruno Larsen (billionai) /* DECR */ 548*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 549*37f219c8SBruno Larsen (billionai) static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 550*37f219c8SBruno Larsen (billionai) { 551*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 552*37f219c8SBruno Larsen (billionai) gen_io_start(); 553*37f219c8SBruno Larsen (billionai) } 554*37f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 555*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 556*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 557*37f219c8SBruno Larsen (billionai) } 558*37f219c8SBruno Larsen (billionai) } 559*37f219c8SBruno Larsen (billionai) 560*37f219c8SBruno Larsen (billionai) static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 561*37f219c8SBruno Larsen (billionai) { 562*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 563*37f219c8SBruno Larsen (billionai) gen_io_start(); 564*37f219c8SBruno Larsen (billionai) } 565*37f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 566*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 567*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 568*37f219c8SBruno Larsen (billionai) } 569*37f219c8SBruno Larsen (billionai) } 570*37f219c8SBruno Larsen (billionai) #endif 571*37f219c8SBruno Larsen (billionai) 572*37f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 573*37f219c8SBruno Larsen (billionai) /* Time base */ 574*37f219c8SBruno Larsen (billionai) static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 575*37f219c8SBruno Larsen (billionai) { 576*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 577*37f219c8SBruno Larsen (billionai) gen_io_start(); 578*37f219c8SBruno Larsen (billionai) } 579*37f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 580*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 581*37f219c8SBruno Larsen (billionai) gen_io_end(); 582*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 583*37f219c8SBruno Larsen (billionai) } 584*37f219c8SBruno Larsen (billionai) } 585*37f219c8SBruno Larsen (billionai) 586*37f219c8SBruno Larsen (billionai) static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 587*37f219c8SBruno Larsen (billionai) { 588*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 589*37f219c8SBruno Larsen (billionai) gen_io_start(); 590*37f219c8SBruno Larsen (billionai) } 591*37f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 592*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 593*37f219c8SBruno Larsen (billionai) gen_io_end(); 594*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 595*37f219c8SBruno Larsen (billionai) } 596*37f219c8SBruno Larsen (billionai) } 597*37f219c8SBruno Larsen (billionai) 598*37f219c8SBruno Larsen (billionai) ATTRIBUTE_UNUSED 599*37f219c8SBruno Larsen (billionai) static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 600*37f219c8SBruno Larsen (billionai) { 601*37f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 602*37f219c8SBruno Larsen (billionai) } 603*37f219c8SBruno Larsen (billionai) 604*37f219c8SBruno Larsen (billionai) ATTRIBUTE_UNUSED 605*37f219c8SBruno Larsen (billionai) static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 606*37f219c8SBruno Larsen (billionai) { 607*37f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 608*37f219c8SBruno Larsen (billionai) } 609*37f219c8SBruno Larsen (billionai) 610*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 611*37f219c8SBruno Larsen (billionai) static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 612*37f219c8SBruno Larsen (billionai) { 613*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 614*37f219c8SBruno Larsen (billionai) gen_io_start(); 615*37f219c8SBruno Larsen (billionai) } 616*37f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 617*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 618*37f219c8SBruno Larsen (billionai) gen_io_end(); 619*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 620*37f219c8SBruno Larsen (billionai) } 621*37f219c8SBruno Larsen (billionai) } 622*37f219c8SBruno Larsen (billionai) 623*37f219c8SBruno Larsen (billionai) static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 624*37f219c8SBruno Larsen (billionai) { 625*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 626*37f219c8SBruno Larsen (billionai) gen_io_start(); 627*37f219c8SBruno Larsen (billionai) } 628*37f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 629*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 630*37f219c8SBruno Larsen (billionai) gen_io_end(); 631*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 632*37f219c8SBruno Larsen (billionai) } 633*37f219c8SBruno Larsen (billionai) } 634*37f219c8SBruno Larsen (billionai) 635*37f219c8SBruno Larsen (billionai) ATTRIBUTE_UNUSED 636*37f219c8SBruno Larsen (billionai) static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 637*37f219c8SBruno Larsen (billionai) { 638*37f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 639*37f219c8SBruno Larsen (billionai) } 640*37f219c8SBruno Larsen (billionai) 641*37f219c8SBruno Larsen (billionai) ATTRIBUTE_UNUSED 642*37f219c8SBruno Larsen (billionai) static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 643*37f219c8SBruno Larsen (billionai) { 644*37f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 645*37f219c8SBruno Larsen (billionai) } 646*37f219c8SBruno Larsen (billionai) 647*37f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 648*37f219c8SBruno Larsen (billionai) ATTRIBUTE_UNUSED 649*37f219c8SBruno Larsen (billionai) static void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 650*37f219c8SBruno Larsen (billionai) { 651*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 652*37f219c8SBruno Larsen (billionai) gen_io_start(); 653*37f219c8SBruno Larsen (billionai) } 654*37f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 655*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 656*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 657*37f219c8SBruno Larsen (billionai) } 658*37f219c8SBruno Larsen (billionai) } 659*37f219c8SBruno Larsen (billionai) 660*37f219c8SBruno Larsen (billionai) static void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 661*37f219c8SBruno Larsen (billionai) { 662*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 663*37f219c8SBruno Larsen (billionai) gen_io_start(); 664*37f219c8SBruno Larsen (billionai) } 665*37f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 666*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 667*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 668*37f219c8SBruno Larsen (billionai) } 669*37f219c8SBruno Larsen (billionai) } 670*37f219c8SBruno Larsen (billionai) 671*37f219c8SBruno Larsen (billionai) /* HDECR */ 672*37f219c8SBruno Larsen (billionai) static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 673*37f219c8SBruno Larsen (billionai) { 674*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 675*37f219c8SBruno Larsen (billionai) gen_io_start(); 676*37f219c8SBruno Larsen (billionai) } 677*37f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 678*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 679*37f219c8SBruno Larsen (billionai) gen_io_end(); 680*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 681*37f219c8SBruno Larsen (billionai) } 682*37f219c8SBruno Larsen (billionai) } 683*37f219c8SBruno Larsen (billionai) 684*37f219c8SBruno Larsen (billionai) static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 685*37f219c8SBruno Larsen (billionai) { 686*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 687*37f219c8SBruno Larsen (billionai) gen_io_start(); 688*37f219c8SBruno Larsen (billionai) } 689*37f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 690*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 691*37f219c8SBruno Larsen (billionai) gen_io_end(); 692*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 693*37f219c8SBruno Larsen (billionai) } 694*37f219c8SBruno Larsen (billionai) } 695*37f219c8SBruno Larsen (billionai) 696*37f219c8SBruno Larsen (billionai) static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 697*37f219c8SBruno Larsen (billionai) { 698*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 699*37f219c8SBruno Larsen (billionai) gen_io_start(); 700*37f219c8SBruno Larsen (billionai) } 701*37f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 702*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 703*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 704*37f219c8SBruno Larsen (billionai) } 705*37f219c8SBruno Larsen (billionai) } 706*37f219c8SBruno Larsen (billionai) 707*37f219c8SBruno Larsen (billionai) static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 708*37f219c8SBruno Larsen (billionai) { 709*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 710*37f219c8SBruno Larsen (billionai) gen_io_start(); 711*37f219c8SBruno Larsen (billionai) } 712*37f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 713*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 714*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 715*37f219c8SBruno Larsen (billionai) } 716*37f219c8SBruno Larsen (billionai) } 717*37f219c8SBruno Larsen (billionai) 718*37f219c8SBruno Larsen (billionai) static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 719*37f219c8SBruno Larsen (billionai) { 720*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 721*37f219c8SBruno Larsen (billionai) gen_io_start(); 722*37f219c8SBruno Larsen (billionai) } 723*37f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 724*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 725*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 726*37f219c8SBruno Larsen (billionai) } 727*37f219c8SBruno Larsen (billionai) } 728*37f219c8SBruno Larsen (billionai) 729*37f219c8SBruno Larsen (billionai) #endif 730*37f219c8SBruno Larsen (billionai) #endif 731*37f219c8SBruno Larsen (billionai) 732*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 733*37f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 734*37f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 735*37f219c8SBruno Larsen (billionai) static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 736*37f219c8SBruno Larsen (billionai) { 737*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 738*37f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 739*37f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 740*37f219c8SBruno Larsen (billionai) } 741*37f219c8SBruno Larsen (billionai) 742*37f219c8SBruno Larsen (billionai) static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 743*37f219c8SBruno Larsen (billionai) { 744*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 745*37f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 746*37f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 747*37f219c8SBruno Larsen (billionai) } 748*37f219c8SBruno Larsen (billionai) 749*37f219c8SBruno Larsen (billionai) static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 750*37f219c8SBruno Larsen (billionai) { 751*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 752*37f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 753*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 754*37f219c8SBruno Larsen (billionai) } 755*37f219c8SBruno Larsen (billionai) 756*37f219c8SBruno Larsen (billionai) static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 757*37f219c8SBruno Larsen (billionai) { 758*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 759*37f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 760*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 761*37f219c8SBruno Larsen (billionai) } 762*37f219c8SBruno Larsen (billionai) 763*37f219c8SBruno Larsen (billionai) static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 764*37f219c8SBruno Larsen (billionai) { 765*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 766*37f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 767*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 768*37f219c8SBruno Larsen (billionai) } 769*37f219c8SBruno Larsen (billionai) 770*37f219c8SBruno Larsen (billionai) static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 771*37f219c8SBruno Larsen (billionai) { 772*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 773*37f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 774*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 775*37f219c8SBruno Larsen (billionai) } 776*37f219c8SBruno Larsen (billionai) 777*37f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 778*37f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 779*37f219c8SBruno Larsen (billionai) static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 780*37f219c8SBruno Larsen (billionai) { 781*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 782*37f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 783*37f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 784*37f219c8SBruno Larsen (billionai) } 785*37f219c8SBruno Larsen (billionai) 786*37f219c8SBruno Larsen (billionai) static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 787*37f219c8SBruno Larsen (billionai) { 788*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 789*37f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 790*37f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 791*37f219c8SBruno Larsen (billionai) } 792*37f219c8SBruno Larsen (billionai) 793*37f219c8SBruno Larsen (billionai) static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 794*37f219c8SBruno Larsen (billionai) { 795*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 796*37f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 797*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 798*37f219c8SBruno Larsen (billionai) } 799*37f219c8SBruno Larsen (billionai) 800*37f219c8SBruno Larsen (billionai) static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 801*37f219c8SBruno Larsen (billionai) { 802*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 803*37f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 804*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 805*37f219c8SBruno Larsen (billionai) } 806*37f219c8SBruno Larsen (billionai) 807*37f219c8SBruno Larsen (billionai) static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 808*37f219c8SBruno Larsen (billionai) { 809*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 810*37f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 811*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 812*37f219c8SBruno Larsen (billionai) } 813*37f219c8SBruno Larsen (billionai) 814*37f219c8SBruno Larsen (billionai) static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 815*37f219c8SBruno Larsen (billionai) { 816*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 817*37f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 818*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 819*37f219c8SBruno Larsen (billionai) } 820*37f219c8SBruno Larsen (billionai) 821*37f219c8SBruno Larsen (billionai) /* SDR1 */ 822*37f219c8SBruno Larsen (billionai) static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 823*37f219c8SBruno Larsen (billionai) { 824*37f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 825*37f219c8SBruno Larsen (billionai) } 826*37f219c8SBruno Larsen (billionai) 827*37f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 828*37f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 829*37f219c8SBruno Larsen (billionai) /* PIDR */ 830*37f219c8SBruno Larsen (billionai) static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 831*37f219c8SBruno Larsen (billionai) { 832*37f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 833*37f219c8SBruno Larsen (billionai) } 834*37f219c8SBruno Larsen (billionai) 835*37f219c8SBruno Larsen (billionai) static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 836*37f219c8SBruno Larsen (billionai) { 837*37f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 838*37f219c8SBruno Larsen (billionai) } 839*37f219c8SBruno Larsen (billionai) 840*37f219c8SBruno Larsen (billionai) static void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 841*37f219c8SBruno Larsen (billionai) { 842*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 843*37f219c8SBruno Larsen (billionai) } 844*37f219c8SBruno Larsen (billionai) 845*37f219c8SBruno Larsen (billionai) static void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 846*37f219c8SBruno Larsen (billionai) { 847*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 848*37f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 849*37f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 850*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 851*37f219c8SBruno Larsen (billionai) } 852*37f219c8SBruno Larsen (billionai) static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 853*37f219c8SBruno Larsen (billionai) { 854*37f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 855*37f219c8SBruno Larsen (billionai) } 856*37f219c8SBruno Larsen (billionai) 857*37f219c8SBruno Larsen (billionai) static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 858*37f219c8SBruno Larsen (billionai) { 859*37f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 860*37f219c8SBruno Larsen (billionai) } 861*37f219c8SBruno Larsen (billionai) 862*37f219c8SBruno Larsen (billionai) /* DPDES */ 863*37f219c8SBruno Larsen (billionai) static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 864*37f219c8SBruno Larsen (billionai) { 865*37f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 866*37f219c8SBruno Larsen (billionai) } 867*37f219c8SBruno Larsen (billionai) 868*37f219c8SBruno Larsen (billionai) static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 869*37f219c8SBruno Larsen (billionai) { 870*37f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 871*37f219c8SBruno Larsen (billionai) } 872*37f219c8SBruno Larsen (billionai) #endif 873*37f219c8SBruno Larsen (billionai) #endif 874*37f219c8SBruno Larsen (billionai) 875*37f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 876*37f219c8SBruno Larsen (billionai) /* RTC */ 877*37f219c8SBruno Larsen (billionai) static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 878*37f219c8SBruno Larsen (billionai) { 879*37f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 880*37f219c8SBruno Larsen (billionai) } 881*37f219c8SBruno Larsen (billionai) 882*37f219c8SBruno Larsen (billionai) static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 883*37f219c8SBruno Larsen (billionai) { 884*37f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 885*37f219c8SBruno Larsen (billionai) } 886*37f219c8SBruno Larsen (billionai) 887*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 888*37f219c8SBruno Larsen (billionai) static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 889*37f219c8SBruno Larsen (billionai) { 890*37f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 891*37f219c8SBruno Larsen (billionai) } 892*37f219c8SBruno Larsen (billionai) 893*37f219c8SBruno Larsen (billionai) static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 894*37f219c8SBruno Larsen (billionai) { 895*37f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 896*37f219c8SBruno Larsen (billionai) } 897*37f219c8SBruno Larsen (billionai) 898*37f219c8SBruno Larsen (billionai) static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 899*37f219c8SBruno Larsen (billionai) { 900*37f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 901*37f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 902*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 903*37f219c8SBruno Larsen (billionai) } 904*37f219c8SBruno Larsen (billionai) #endif 905*37f219c8SBruno Larsen (billionai) 906*37f219c8SBruno Larsen (billionai) /* Unified bats */ 907*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 908*37f219c8SBruno Larsen (billionai) static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 909*37f219c8SBruno Larsen (billionai) { 910*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 911*37f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 912*37f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 913*37f219c8SBruno Larsen (billionai) } 914*37f219c8SBruno Larsen (billionai) 915*37f219c8SBruno Larsen (billionai) static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 916*37f219c8SBruno Larsen (billionai) { 917*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 918*37f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 919*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 920*37f219c8SBruno Larsen (billionai) } 921*37f219c8SBruno Larsen (billionai) 922*37f219c8SBruno Larsen (billionai) static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 923*37f219c8SBruno Larsen (billionai) { 924*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 925*37f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 926*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 927*37f219c8SBruno Larsen (billionai) } 928*37f219c8SBruno Larsen (billionai) #endif 929*37f219c8SBruno Larsen (billionai) 930*37f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 931*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 932*37f219c8SBruno Larsen (billionai) static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 933*37f219c8SBruno Larsen (billionai) { 934*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 935*37f219c8SBruno Larsen (billionai) gen_io_start(); 936*37f219c8SBruno Larsen (billionai) } 937*37f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 938*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 939*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 940*37f219c8SBruno Larsen (billionai) } 941*37f219c8SBruno Larsen (billionai) } 942*37f219c8SBruno Larsen (billionai) 943*37f219c8SBruno Larsen (billionai) static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 944*37f219c8SBruno Larsen (billionai) { 945*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 946*37f219c8SBruno Larsen (billionai) gen_io_start(); 947*37f219c8SBruno Larsen (billionai) } 948*37f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 949*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 950*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 951*37f219c8SBruno Larsen (billionai) } 952*37f219c8SBruno Larsen (billionai) } 953*37f219c8SBruno Larsen (billionai) 954*37f219c8SBruno Larsen (billionai) static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 955*37f219c8SBruno Larsen (billionai) { 956*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 957*37f219c8SBruno Larsen (billionai) gen_io_start(); 958*37f219c8SBruno Larsen (billionai) } 959*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 960*37f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 961*37f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 962*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 963*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 964*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 965*37f219c8SBruno Larsen (billionai) } 966*37f219c8SBruno Larsen (billionai) } 967*37f219c8SBruno Larsen (billionai) 968*37f219c8SBruno Larsen (billionai) static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 969*37f219c8SBruno Larsen (billionai) { 970*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 971*37f219c8SBruno Larsen (billionai) gen_io_start(); 972*37f219c8SBruno Larsen (billionai) } 973*37f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 974*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 975*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 976*37f219c8SBruno Larsen (billionai) } 977*37f219c8SBruno Larsen (billionai) } 978*37f219c8SBruno Larsen (billionai) 979*37f219c8SBruno Larsen (billionai) static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 980*37f219c8SBruno Larsen (billionai) { 981*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 982*37f219c8SBruno Larsen (billionai) gen_io_start(); 983*37f219c8SBruno Larsen (billionai) } 984*37f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 985*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 986*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 987*37f219c8SBruno Larsen (billionai) } 988*37f219c8SBruno Larsen (billionai) } 989*37f219c8SBruno Larsen (billionai) 990*37f219c8SBruno Larsen (billionai) static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 991*37f219c8SBruno Larsen (billionai) { 992*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 993*37f219c8SBruno Larsen (billionai) gen_io_start(); 994*37f219c8SBruno Larsen (billionai) } 995*37f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 996*37f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 997*37f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 998*37f219c8SBruno Larsen (billionai) } 999*37f219c8SBruno Larsen (billionai) } 1000*37f219c8SBruno Larsen (billionai) #endif 1001*37f219c8SBruno Larsen (billionai) 1002*37f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 1003*37f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 1004*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1005*37f219c8SBruno Larsen (billionai) static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 1006*37f219c8SBruno Larsen (billionai) { 1007*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 1008*37f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 1009*37f219c8SBruno Larsen (billionai) } 1010*37f219c8SBruno Larsen (billionai) 1011*37f219c8SBruno Larsen (billionai) static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 1012*37f219c8SBruno Larsen (billionai) { 1013*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 1014*37f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 1015*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 1016*37f219c8SBruno Larsen (billionai) } 1017*37f219c8SBruno Larsen (billionai) 1018*37f219c8SBruno Larsen (billionai) static void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 1019*37f219c8SBruno Larsen (billionai) { 1020*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1021*37f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 1022*37f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 1023*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1024*37f219c8SBruno Larsen (billionai) } 1025*37f219c8SBruno Larsen (billionai) #endif 1026*37f219c8SBruno Larsen (billionai) 1027*37f219c8SBruno Larsen (billionai) /* SPE specific registers */ 1028*37f219c8SBruno Larsen (billionai) static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 1029*37f219c8SBruno Larsen (billionai) { 1030*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 1031*37f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 1032*37f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 1033*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 1034*37f219c8SBruno Larsen (billionai) } 1035*37f219c8SBruno Larsen (billionai) 1036*37f219c8SBruno Larsen (billionai) static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 1037*37f219c8SBruno Larsen (billionai) { 1038*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 1039*37f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 1040*37f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 1041*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 1042*37f219c8SBruno Larsen (billionai) } 1043*37f219c8SBruno Larsen (billionai) 1044*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1045*37f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 1046*37f219c8SBruno Larsen (billionai) static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 1047*37f219c8SBruno Larsen (billionai) { 1048*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1049*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 1050*37f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1051*37f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 1052*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 1053*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1054*37f219c8SBruno Larsen (billionai) } 1055*37f219c8SBruno Larsen (billionai) 1056*37f219c8SBruno Larsen (billionai) static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 1057*37f219c8SBruno Larsen (billionai) { 1058*37f219c8SBruno Larsen (billionai) int sprn_offs; 1059*37f219c8SBruno Larsen (billionai) 1060*37f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 1061*37f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 1062*37f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 1063*37f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 1064*37f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 1065*37f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 1066*37f219c8SBruno Larsen (billionai) } else { 1067*37f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 1068*37f219c8SBruno Larsen (billionai) sprn, sprn); 1069*37f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 1070*37f219c8SBruno Larsen (billionai) return; 1071*37f219c8SBruno Larsen (billionai) } 1072*37f219c8SBruno Larsen (billionai) 1073*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1074*37f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 1075*37f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 1076*37f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 1077*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 1078*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1079*37f219c8SBruno Larsen (billionai) } 1080*37f219c8SBruno Larsen (billionai) #endif 1081*37f219c8SBruno Larsen (billionai) 1082*37f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 1083*37f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1084*37f219c8SBruno Larsen (billionai) static void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 1085*37f219c8SBruno Larsen (billionai) { 1086*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1087*37f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 1088*37f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 1089*37f219c8SBruno Larsen (billionai) 1090*37f219c8SBruno Larsen (billionai) /* 1091*37f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 1092*37f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 1093*37f219c8SBruno Larsen (billionai) */ 1094*37f219c8SBruno Larsen (billionai) 1095*37f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 1096*37f219c8SBruno Larsen (billionai) if (ctx->pr) { 1097*37f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 1098*37f219c8SBruno Larsen (billionai) } else { 1099*37f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 1100*37f219c8SBruno Larsen (billionai) } 1101*37f219c8SBruno Larsen (billionai) 1102*37f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 1103*37f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1104*37f219c8SBruno Larsen (billionai) 1105*37f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 1106*37f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 1107*37f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 1108*37f219c8SBruno Larsen (billionai) 1109*37f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 1110*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 1111*37f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 1112*37f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 1113*37f219c8SBruno Larsen (billionai) 1114*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1115*37f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 1116*37f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 1117*37f219c8SBruno Larsen (billionai) } 1118*37f219c8SBruno Larsen (billionai) 1119*37f219c8SBruno Larsen (billionai) static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1120*37f219c8SBruno Larsen (billionai) { 1121*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1122*37f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 1123*37f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 1124*37f219c8SBruno Larsen (billionai) 1125*37f219c8SBruno Larsen (billionai) /* 1126*37f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 1127*37f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 1128*37f219c8SBruno Larsen (billionai) */ 1129*37f219c8SBruno Larsen (billionai) 1130*37f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 1131*37f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 1132*37f219c8SBruno Larsen (billionai) 1133*37f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 1134*37f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1135*37f219c8SBruno Larsen (billionai) 1136*37f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 1137*37f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 1138*37f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 1139*37f219c8SBruno Larsen (billionai) 1140*37f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 1141*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 1142*37f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 1143*37f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 1144*37f219c8SBruno Larsen (billionai) 1145*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1146*37f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 1147*37f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 1148*37f219c8SBruno Larsen (billionai) } 1149*37f219c8SBruno Larsen (billionai) 1150*37f219c8SBruno Larsen (billionai) static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1151*37f219c8SBruno Larsen (billionai) { 1152*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1153*37f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 1154*37f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 1155*37f219c8SBruno Larsen (billionai) 1156*37f219c8SBruno Larsen (billionai) /* 1157*37f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 1158*37f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 1159*37f219c8SBruno Larsen (billionai) */ 1160*37f219c8SBruno Larsen (billionai) 1161*37f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 1162*37f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 1163*37f219c8SBruno Larsen (billionai) 1164*37f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 1165*37f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1166*37f219c8SBruno Larsen (billionai) 1167*37f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 1168*37f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 1169*37f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 1170*37f219c8SBruno Larsen (billionai) 1171*37f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 1172*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 1173*37f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 1174*37f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 1175*37f219c8SBruno Larsen (billionai) 1176*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1177*37f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 1178*37f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 1179*37f219c8SBruno Larsen (billionai) } 1180*37f219c8SBruno Larsen (billionai) #endif 1181*37f219c8SBruno Larsen (billionai) #endif 1182*37f219c8SBruno Larsen (billionai) 1183*37f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1184*37f219c8SBruno Larsen (billionai) static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1185*37f219c8SBruno Larsen (billionai) { 1186*37f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 1187*37f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 1188*37f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 1189*37f219c8SBruno Larsen (billionai) } 1190*37f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 1191*37f219c8SBruno Larsen (billionai) 1192*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1193*37f219c8SBruno Larsen (billionai) static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1194*37f219c8SBruno Larsen (billionai) { 1195*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1196*37f219c8SBruno Larsen (billionai) 1197*37f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1198*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 1199*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1200*37f219c8SBruno Larsen (billionai) } 1201*37f219c8SBruno Larsen (billionai) 1202*37f219c8SBruno Larsen (billionai) static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1203*37f219c8SBruno Larsen (billionai) { 1204*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1205*37f219c8SBruno Larsen (billionai) 1206*37f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1207*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 1208*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1209*37f219c8SBruno Larsen (billionai) } 1210*37f219c8SBruno Larsen (billionai) 1211*37f219c8SBruno Larsen (billionai) static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1212*37f219c8SBruno Larsen (billionai) { 1213*37f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 1214*37f219c8SBruno Larsen (billionai) 1215*37f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1216*37f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1217*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 1218*37f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 1219*37f219c8SBruno Larsen (billionai) } 1220*37f219c8SBruno Larsen (billionai) 1221*37f219c8SBruno Larsen (billionai) static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1222*37f219c8SBruno Larsen (billionai) { 1223*37f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1224*37f219c8SBruno Larsen (billionai) } 1225*37f219c8SBruno Larsen (billionai) 1226*37f219c8SBruno Larsen (billionai) static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1227*37f219c8SBruno Larsen (billionai) { 1228*37f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 1229*37f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1230*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 1231*37f219c8SBruno Larsen (billionai) } 1232*37f219c8SBruno Larsen (billionai) static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1233*37f219c8SBruno Larsen (billionai) { 1234*37f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1235*37f219c8SBruno Larsen (billionai) } 1236*37f219c8SBruno Larsen (billionai) static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1237*37f219c8SBruno Larsen (billionai) { 1238*37f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1239*37f219c8SBruno Larsen (billionai) } 1240*37f219c8SBruno Larsen (billionai) 1241*37f219c8SBruno Larsen (billionai) #endif 1242*37f219c8SBruno Larsen (billionai) 1243*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1244*37f219c8SBruno Larsen (billionai) static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 1245*37f219c8SBruno Larsen (billionai) { 1246*37f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 1247*37f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 1248*37f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 1249*37f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 1250*37f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 1251*37f219c8SBruno Larsen (billionai) tcg_temp_free(val); 1252*37f219c8SBruno Larsen (billionai) } 1253*37f219c8SBruno Larsen (billionai) 1254*37f219c8SBruno Larsen (billionai) static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 1255*37f219c8SBruno Larsen (billionai) { 1256*37f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 1257*37f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 1258*37f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 1259*37f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 1260*37f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 1261*37f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 1262*37f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 1263*37f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 1264*37f219c8SBruno Larsen (billionai) } 1265*37f219c8SBruno Larsen (billionai) 1266*37f219c8SBruno Larsen (billionai) #endif 1267*37f219c8SBruno Larsen (billionai) 1268*37f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 1269*37f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 1270*37f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 1271*37f219c8SBruno Larsen (billionai) { 1272*37f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 1273*37f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 1274*37f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 1275*37f219c8SBruno Larsen (billionai) 1276*37f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 1277*37f219c8SBruno Larsen (billionai) 1278*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 1279*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 1280*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 1281*37f219c8SBruno Larsen (billionai) } 1282*37f219c8SBruno Larsen (billionai) 1283*37f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 1284*37f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 1285*37f219c8SBruno Larsen (billionai) { 1286*37f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 1287*37f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 1288*37f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 1289*37f219c8SBruno Larsen (billionai) 1290*37f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 1291*37f219c8SBruno Larsen (billionai) 1292*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 1293*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 1294*37f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 1295*37f219c8SBruno Larsen (billionai) } 1296*37f219c8SBruno Larsen (billionai) 1297*37f219c8SBruno Larsen (billionai) static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 1298*37f219c8SBruno Larsen (billionai) { 1299*37f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 1300*37f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 1301*37f219c8SBruno Larsen (billionai) 1302*37f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 1303*37f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 1304*37f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 1305*37f219c8SBruno Larsen (billionai) 1306*37f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 1307*37f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 1308*37f219c8SBruno Larsen (billionai) } 1309*37f219c8SBruno Larsen (billionai) 1310*37f219c8SBruno Larsen (billionai) static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 1311*37f219c8SBruno Larsen (billionai) { 1312*37f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 1313*37f219c8SBruno Larsen (billionai) 1314*37f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 1315*37f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 1316*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 1317*37f219c8SBruno Larsen (billionai) 1318*37f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 1319*37f219c8SBruno Larsen (billionai) } 1320*37f219c8SBruno Larsen (billionai) 1321*37f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1322*37f219c8SBruno Larsen (billionai) static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 1323*37f219c8SBruno Larsen (billionai) { 1324*37f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 1325*37f219c8SBruno Larsen (billionai) 1326*37f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 1327*37f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 1328*37f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 1329*37f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 1330*37f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 1331*37f219c8SBruno Larsen (billionai) } 1332*37f219c8SBruno Larsen (billionai) 1333*37f219c8SBruno Larsen (billionai) static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 1334*37f219c8SBruno Larsen (billionai) { 1335*37f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 1336*37f219c8SBruno Larsen (billionai) } 1337*37f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 1338*37f219c8SBruno Larsen (billionai) 1339*37f219c8SBruno Larsen (billionai) static void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 1340*37f219c8SBruno Larsen (billionai) { 1341*37f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1342*37f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 1343*37f219c8SBruno Larsen (billionai) } 1344*37f219c8SBruno Larsen (billionai) 1345*37f219c8SBruno Larsen (billionai) static void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 1346*37f219c8SBruno Larsen (billionai) { 1347*37f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 1348*37f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 1349*37f219c8SBruno Larsen (billionai) } 1350*37f219c8SBruno Larsen (billionai) 1351*37f219c8SBruno Larsen (billionai) static void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 1352*37f219c8SBruno Larsen (billionai) { 1353*37f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1354*37f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 1355*37f219c8SBruno Larsen (billionai) } 1356*37f219c8SBruno Larsen (billionai) 1357*37f219c8SBruno Larsen (billionai) static void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 1358*37f219c8SBruno Larsen (billionai) { 1359*37f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1360*37f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 1361*37f219c8SBruno Larsen (billionai) } 1362*37f219c8SBruno Larsen (billionai) 1363*37f219c8SBruno Larsen (billionai) static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 1364*37f219c8SBruno Larsen (billionai) { 1365*37f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1366*37f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 1367*37f219c8SBruno Larsen (billionai) } 1368*37f219c8SBruno Larsen (billionai) 1369*37f219c8SBruno Larsen (billionai) static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 1370*37f219c8SBruno Larsen (billionai) { 1371*37f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 1372*37f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 1373*37f219c8SBruno Larsen (billionai) } 1374*37f219c8SBruno Larsen (billionai) 1375*37f219c8SBruno Larsen (billionai) static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 1376*37f219c8SBruno Larsen (billionai) { 1377*37f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1378*37f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 1379*37f219c8SBruno Larsen (billionai) } 1380*37f219c8SBruno Larsen (billionai) 1381*37f219c8SBruno Larsen (billionai) static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 1382*37f219c8SBruno Larsen (billionai) { 1383*37f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1384*37f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 1385*37f219c8SBruno Larsen (billionai) } 1386*37f219c8SBruno Larsen (billionai) 1387*37f219c8SBruno Larsen (billionai) static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 1388*37f219c8SBruno Larsen (billionai) { 1389*37f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1390*37f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 1391*37f219c8SBruno Larsen (billionai) } 1392*37f219c8SBruno Larsen (billionai) 1393*37f219c8SBruno Larsen (billionai) static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 1394*37f219c8SBruno Larsen (billionai) { 1395*37f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 1396*37f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 1397*37f219c8SBruno Larsen (billionai) } 1398*37f219c8SBruno Larsen (billionai) #endif 1399*37f219c8SBruno Larsen (billionai) 1400fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1401fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1402fcf5ef2aSThomas Huth 1403fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1404fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1405fcf5ef2aSThomas Huth 1406fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1407fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1408fcf5ef2aSThomas Huth 1409fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1410fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1411fcf5ef2aSThomas Huth 1412fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1413fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1414fcf5ef2aSThomas Huth 1415fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1416fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1417fcf5ef2aSThomas Huth 1418fcf5ef2aSThomas Huth typedef struct opcode_t { 1419fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1420fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1421fcf5ef2aSThomas Huth unsigned char pad[4]; 1422fcf5ef2aSThomas Huth #endif 1423fcf5ef2aSThomas Huth opc_handler_t handler; 1424fcf5ef2aSThomas Huth const char *oname; 1425fcf5ef2aSThomas Huth } opcode_t; 1426fcf5ef2aSThomas Huth 1427fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1428fcf5ef2aSThomas Huth #define GEN_PRIV \ 1429fcf5ef2aSThomas Huth do { \ 1430fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1431fcf5ef2aSThomas Huth } while (0) 1432fcf5ef2aSThomas Huth 1433fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1434fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1435fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1436fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1437fcf5ef2aSThomas Huth #else 1438fcf5ef2aSThomas Huth #define CHK_HV \ 1439fcf5ef2aSThomas Huth do { \ 1440fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1441fcf5ef2aSThomas Huth GEN_PRIV; \ 1442fcf5ef2aSThomas Huth } \ 1443fcf5ef2aSThomas Huth } while (0) 1444fcf5ef2aSThomas Huth #define CHK_SV \ 1445fcf5ef2aSThomas Huth do { \ 1446fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1447fcf5ef2aSThomas Huth GEN_PRIV; \ 1448fcf5ef2aSThomas Huth } \ 1449fcf5ef2aSThomas Huth } while (0) 1450fcf5ef2aSThomas Huth #define CHK_HVRM \ 1451fcf5ef2aSThomas Huth do { \ 1452fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1453fcf5ef2aSThomas Huth GEN_PRIV; \ 1454fcf5ef2aSThomas Huth } \ 1455fcf5ef2aSThomas Huth } while (0) 1456fcf5ef2aSThomas Huth #endif 1457fcf5ef2aSThomas Huth 1458fcf5ef2aSThomas Huth #define CHK_NONE 1459fcf5ef2aSThomas Huth 1460fcf5ef2aSThomas Huth /*****************************************************************************/ 1461fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1462fcf5ef2aSThomas Huth 1463fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 1464fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1465fcf5ef2aSThomas Huth { \ 1466fcf5ef2aSThomas Huth .opc1 = op1, \ 1467fcf5ef2aSThomas Huth .opc2 = op2, \ 1468fcf5ef2aSThomas Huth .opc3 = op3, \ 1469fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1470fcf5ef2aSThomas Huth .handler = { \ 1471fcf5ef2aSThomas Huth .inval1 = invl, \ 1472fcf5ef2aSThomas Huth .type = _typ, \ 1473fcf5ef2aSThomas Huth .type2 = _typ2, \ 1474fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1475fcf5ef2aSThomas Huth .oname = stringify(name), \ 1476fcf5ef2aSThomas Huth }, \ 1477fcf5ef2aSThomas Huth .oname = stringify(name), \ 1478fcf5ef2aSThomas Huth } 1479fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1480fcf5ef2aSThomas Huth { \ 1481fcf5ef2aSThomas Huth .opc1 = op1, \ 1482fcf5ef2aSThomas Huth .opc2 = op2, \ 1483fcf5ef2aSThomas Huth .opc3 = op3, \ 1484fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1485fcf5ef2aSThomas Huth .handler = { \ 1486fcf5ef2aSThomas Huth .inval1 = invl1, \ 1487fcf5ef2aSThomas Huth .inval2 = invl2, \ 1488fcf5ef2aSThomas Huth .type = _typ, \ 1489fcf5ef2aSThomas Huth .type2 = _typ2, \ 1490fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1491fcf5ef2aSThomas Huth .oname = stringify(name), \ 1492fcf5ef2aSThomas Huth }, \ 1493fcf5ef2aSThomas Huth .oname = stringify(name), \ 1494fcf5ef2aSThomas Huth } 1495fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1496fcf5ef2aSThomas Huth { \ 1497fcf5ef2aSThomas Huth .opc1 = op1, \ 1498fcf5ef2aSThomas Huth .opc2 = op2, \ 1499fcf5ef2aSThomas Huth .opc3 = op3, \ 1500fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1501fcf5ef2aSThomas Huth .handler = { \ 1502fcf5ef2aSThomas Huth .inval1 = invl, \ 1503fcf5ef2aSThomas Huth .type = _typ, \ 1504fcf5ef2aSThomas Huth .type2 = _typ2, \ 1505fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1506fcf5ef2aSThomas Huth .oname = onam, \ 1507fcf5ef2aSThomas Huth }, \ 1508fcf5ef2aSThomas Huth .oname = onam, \ 1509fcf5ef2aSThomas Huth } 1510fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1511fcf5ef2aSThomas Huth { \ 1512fcf5ef2aSThomas Huth .opc1 = op1, \ 1513fcf5ef2aSThomas Huth .opc2 = op2, \ 1514fcf5ef2aSThomas Huth .opc3 = op3, \ 1515fcf5ef2aSThomas Huth .opc4 = op4, \ 1516fcf5ef2aSThomas Huth .handler = { \ 1517fcf5ef2aSThomas Huth .inval1 = invl, \ 1518fcf5ef2aSThomas Huth .type = _typ, \ 1519fcf5ef2aSThomas Huth .type2 = _typ2, \ 1520fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1521fcf5ef2aSThomas Huth .oname = stringify(name), \ 1522fcf5ef2aSThomas Huth }, \ 1523fcf5ef2aSThomas Huth .oname = stringify(name), \ 1524fcf5ef2aSThomas Huth } 1525fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1526fcf5ef2aSThomas Huth { \ 1527fcf5ef2aSThomas Huth .opc1 = op1, \ 1528fcf5ef2aSThomas Huth .opc2 = op2, \ 1529fcf5ef2aSThomas Huth .opc3 = op3, \ 1530fcf5ef2aSThomas Huth .opc4 = op4, \ 1531fcf5ef2aSThomas Huth .handler = { \ 1532fcf5ef2aSThomas Huth .inval1 = invl, \ 1533fcf5ef2aSThomas Huth .type = _typ, \ 1534fcf5ef2aSThomas Huth .type2 = _typ2, \ 1535fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1536fcf5ef2aSThomas Huth .oname = onam, \ 1537fcf5ef2aSThomas Huth }, \ 1538fcf5ef2aSThomas Huth .oname = onam, \ 1539fcf5ef2aSThomas Huth } 1540fcf5ef2aSThomas Huth #else 1541fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1542fcf5ef2aSThomas Huth { \ 1543fcf5ef2aSThomas Huth .opc1 = op1, \ 1544fcf5ef2aSThomas Huth .opc2 = op2, \ 1545fcf5ef2aSThomas Huth .opc3 = op3, \ 1546fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1547fcf5ef2aSThomas Huth .handler = { \ 1548fcf5ef2aSThomas Huth .inval1 = invl, \ 1549fcf5ef2aSThomas Huth .type = _typ, \ 1550fcf5ef2aSThomas Huth .type2 = _typ2, \ 1551fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1552fcf5ef2aSThomas Huth }, \ 1553fcf5ef2aSThomas Huth .oname = stringify(name), \ 1554fcf5ef2aSThomas Huth } 1555fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1556fcf5ef2aSThomas Huth { \ 1557fcf5ef2aSThomas Huth .opc1 = op1, \ 1558fcf5ef2aSThomas Huth .opc2 = op2, \ 1559fcf5ef2aSThomas Huth .opc3 = op3, \ 1560fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1561fcf5ef2aSThomas Huth .handler = { \ 1562fcf5ef2aSThomas Huth .inval1 = invl1, \ 1563fcf5ef2aSThomas Huth .inval2 = invl2, \ 1564fcf5ef2aSThomas Huth .type = _typ, \ 1565fcf5ef2aSThomas Huth .type2 = _typ2, \ 1566fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1567fcf5ef2aSThomas Huth }, \ 1568fcf5ef2aSThomas Huth .oname = stringify(name), \ 1569fcf5ef2aSThomas Huth } 1570fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1571fcf5ef2aSThomas Huth { \ 1572fcf5ef2aSThomas Huth .opc1 = op1, \ 1573fcf5ef2aSThomas Huth .opc2 = op2, \ 1574fcf5ef2aSThomas Huth .opc3 = op3, \ 1575fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1576fcf5ef2aSThomas Huth .handler = { \ 1577fcf5ef2aSThomas Huth .inval1 = invl, \ 1578fcf5ef2aSThomas Huth .type = _typ, \ 1579fcf5ef2aSThomas Huth .type2 = _typ2, \ 1580fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1581fcf5ef2aSThomas Huth }, \ 1582fcf5ef2aSThomas Huth .oname = onam, \ 1583fcf5ef2aSThomas Huth } 1584fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1585fcf5ef2aSThomas Huth { \ 1586fcf5ef2aSThomas Huth .opc1 = op1, \ 1587fcf5ef2aSThomas Huth .opc2 = op2, \ 1588fcf5ef2aSThomas Huth .opc3 = op3, \ 1589fcf5ef2aSThomas Huth .opc4 = op4, \ 1590fcf5ef2aSThomas Huth .handler = { \ 1591fcf5ef2aSThomas Huth .inval1 = invl, \ 1592fcf5ef2aSThomas Huth .type = _typ, \ 1593fcf5ef2aSThomas Huth .type2 = _typ2, \ 1594fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1595fcf5ef2aSThomas Huth }, \ 1596fcf5ef2aSThomas Huth .oname = stringify(name), \ 1597fcf5ef2aSThomas Huth } 1598fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1599fcf5ef2aSThomas Huth { \ 1600fcf5ef2aSThomas Huth .opc1 = op1, \ 1601fcf5ef2aSThomas Huth .opc2 = op2, \ 1602fcf5ef2aSThomas Huth .opc3 = op3, \ 1603fcf5ef2aSThomas Huth .opc4 = op4, \ 1604fcf5ef2aSThomas Huth .handler = { \ 1605fcf5ef2aSThomas Huth .inval1 = invl, \ 1606fcf5ef2aSThomas Huth .type = _typ, \ 1607fcf5ef2aSThomas Huth .type2 = _typ2, \ 1608fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1609fcf5ef2aSThomas Huth }, \ 1610fcf5ef2aSThomas Huth .oname = onam, \ 1611fcf5ef2aSThomas Huth } 1612fcf5ef2aSThomas Huth #endif 1613fcf5ef2aSThomas Huth 1614fcf5ef2aSThomas Huth /* Invalid instruction */ 1615fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1616fcf5ef2aSThomas Huth { 1617fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1618fcf5ef2aSThomas Huth } 1619fcf5ef2aSThomas Huth 1620fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1621fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1622fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1623fcf5ef2aSThomas Huth .type = PPC_NONE, 1624fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1625fcf5ef2aSThomas Huth .handler = gen_invalid, 1626fcf5ef2aSThomas Huth }; 1627fcf5ef2aSThomas Huth 1628fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1629fcf5ef2aSThomas Huth 1630fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1631fcf5ef2aSThomas Huth { 1632fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1633b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1634b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1635fcf5ef2aSThomas Huth 1636b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1637b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1638efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1639efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1640b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1641efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1642efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1643b62b3686Spbonzini@redhat.com 1644b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1645fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1646b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1647fcf5ef2aSThomas Huth 1648fcf5ef2aSThomas Huth tcg_temp_free(t0); 1649b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1650b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1651fcf5ef2aSThomas Huth } 1652fcf5ef2aSThomas Huth 1653fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1654fcf5ef2aSThomas Huth { 1655fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1656fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1657fcf5ef2aSThomas Huth tcg_temp_free(t0); 1658fcf5ef2aSThomas Huth } 1659fcf5ef2aSThomas Huth 1660fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1661fcf5ef2aSThomas Huth { 1662fcf5ef2aSThomas Huth TCGv t0, t1; 1663fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1664fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1665fcf5ef2aSThomas Huth if (s) { 1666fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1667fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1668fcf5ef2aSThomas Huth } else { 1669fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1670fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1671fcf5ef2aSThomas Huth } 1672fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1673fcf5ef2aSThomas Huth tcg_temp_free(t1); 1674fcf5ef2aSThomas Huth tcg_temp_free(t0); 1675fcf5ef2aSThomas Huth } 1676fcf5ef2aSThomas Huth 1677fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1678fcf5ef2aSThomas Huth { 1679fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1680fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1681fcf5ef2aSThomas Huth tcg_temp_free(t0); 1682fcf5ef2aSThomas Huth } 1683fcf5ef2aSThomas Huth 1684fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1685fcf5ef2aSThomas Huth { 1686fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1687fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1688fcf5ef2aSThomas Huth } else { 1689fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1690fcf5ef2aSThomas Huth } 1691fcf5ef2aSThomas Huth } 1692fcf5ef2aSThomas Huth 1693fcf5ef2aSThomas Huth /* cmp */ 1694fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1695fcf5ef2aSThomas Huth { 1696fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1697fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1698fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1699fcf5ef2aSThomas Huth } else { 1700fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1701fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1702fcf5ef2aSThomas Huth } 1703fcf5ef2aSThomas Huth } 1704fcf5ef2aSThomas Huth 1705fcf5ef2aSThomas Huth /* cmpi */ 1706fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1707fcf5ef2aSThomas Huth { 1708fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1709fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1710fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1711fcf5ef2aSThomas Huth } else { 1712fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1713fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1714fcf5ef2aSThomas Huth } 1715fcf5ef2aSThomas Huth } 1716fcf5ef2aSThomas Huth 1717fcf5ef2aSThomas Huth /* cmpl */ 1718fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1719fcf5ef2aSThomas Huth { 1720fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1721fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1722fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1723fcf5ef2aSThomas Huth } else { 1724fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1725fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1726fcf5ef2aSThomas Huth } 1727fcf5ef2aSThomas Huth } 1728fcf5ef2aSThomas Huth 1729fcf5ef2aSThomas Huth /* cmpli */ 1730fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1731fcf5ef2aSThomas Huth { 1732fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1733fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1734fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1735fcf5ef2aSThomas Huth } else { 1736fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1737fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1738fcf5ef2aSThomas Huth } 1739fcf5ef2aSThomas Huth } 1740fcf5ef2aSThomas Huth 1741fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1742fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1743fcf5ef2aSThomas Huth { 1744fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1745fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1746fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1747fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1748fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1749fcf5ef2aSThomas Huth 1750fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1751fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1752fcf5ef2aSThomas Huth 1753fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1754fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1755fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1756fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1757fcf5ef2aSThomas Huth 1758fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1759fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1760fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1761fcf5ef2aSThomas Huth 1762fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1763fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1764fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1765fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1766fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1767fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1768fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1769fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1770fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1771fcf5ef2aSThomas Huth } 1772efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1773fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1774fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1775fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1776fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1777fcf5ef2aSThomas Huth } 1778fcf5ef2aSThomas Huth 1779fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1780fcf5ef2aSThomas Huth /* cmpeqb */ 1781fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1782fcf5ef2aSThomas Huth { 1783fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1784fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1785fcf5ef2aSThomas Huth } 1786fcf5ef2aSThomas Huth #endif 1787fcf5ef2aSThomas Huth 1788fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1789fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1790fcf5ef2aSThomas Huth { 1791fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1792fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1793fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1794fcf5ef2aSThomas Huth TCGv zr; 1795fcf5ef2aSThomas Huth 1796fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1797fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1798fcf5ef2aSThomas Huth 1799fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1800fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1801fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1802fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1803fcf5ef2aSThomas Huth tcg_temp_free(zr); 1804fcf5ef2aSThomas Huth tcg_temp_free(t0); 1805fcf5ef2aSThomas Huth } 1806fcf5ef2aSThomas Huth 1807fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1808fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1809fcf5ef2aSThomas Huth { 1810fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1811fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1812fcf5ef2aSThomas Huth } 1813fcf5ef2aSThomas Huth 1814fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1815fcf5ef2aSThomas Huth 1816fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1817fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1818fcf5ef2aSThomas Huth { 1819fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1820fcf5ef2aSThomas Huth 1821fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1822fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1823fcf5ef2aSThomas Huth if (sub) { 1824fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1825fcf5ef2aSThomas Huth } else { 1826fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1827fcf5ef2aSThomas Huth } 1828fcf5ef2aSThomas Huth tcg_temp_free(t0); 1829fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1830dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1831dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1832dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1833fcf5ef2aSThomas Huth } 1834dc0ad844SNikunj A Dadhania } else { 1835dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1836dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1837dc0ad844SNikunj A Dadhania } 183838a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1839dc0ad844SNikunj A Dadhania } 1840fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1841fcf5ef2aSThomas Huth } 1842fcf5ef2aSThomas Huth 18436b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 18446b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 18454c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 18466b10d008SNikunj A Dadhania { 18476b10d008SNikunj A Dadhania TCGv t0; 18486b10d008SNikunj A Dadhania 18496b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 18506b10d008SNikunj A Dadhania return; 18516b10d008SNikunj A Dadhania } 18526b10d008SNikunj A Dadhania 18536b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 185433903d0aSNikunj A Dadhania if (sub) { 185533903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 185633903d0aSNikunj A Dadhania } else { 18576b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 185833903d0aSNikunj A Dadhania } 18596b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 18604c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 18616b10d008SNikunj A Dadhania tcg_temp_free(t0); 18626b10d008SNikunj A Dadhania } 18636b10d008SNikunj A Dadhania 1864fcf5ef2aSThomas Huth /* Common add function */ 1865fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 18664c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 18674c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1868fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1869fcf5ef2aSThomas Huth { 1870fcf5ef2aSThomas Huth TCGv t0 = ret; 1871fcf5ef2aSThomas Huth 1872fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1873fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1874fcf5ef2aSThomas Huth } 1875fcf5ef2aSThomas Huth 1876fcf5ef2aSThomas Huth if (compute_ca) { 1877fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1878efe843d8SDavid Gibson /* 1879efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1880efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1881efe843d8SDavid Gibson * produce the carry into bit 32. 1882efe843d8SDavid Gibson */ 1883fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1884fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1885fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1886fcf5ef2aSThomas Huth if (add_ca) { 18874c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1888fcf5ef2aSThomas Huth } 18894c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1890fcf5ef2aSThomas Huth tcg_temp_free(t1); 18914c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 18926b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 18934c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 18946b10d008SNikunj A Dadhania } 1895fcf5ef2aSThomas Huth } else { 1896fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1897fcf5ef2aSThomas Huth if (add_ca) { 18984c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 18994c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1900fcf5ef2aSThomas Huth } else { 19014c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1902fcf5ef2aSThomas Huth } 19034c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1904fcf5ef2aSThomas Huth tcg_temp_free(zero); 1905fcf5ef2aSThomas Huth } 1906fcf5ef2aSThomas Huth } else { 1907fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1908fcf5ef2aSThomas Huth if (add_ca) { 19094c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1910fcf5ef2aSThomas Huth } 1911fcf5ef2aSThomas Huth } 1912fcf5ef2aSThomas Huth 1913fcf5ef2aSThomas Huth if (compute_ov) { 1914fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1915fcf5ef2aSThomas Huth } 1916fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1917fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1918fcf5ef2aSThomas Huth } 1919fcf5ef2aSThomas Huth 192011f4e8f8SRichard Henderson if (t0 != ret) { 1921fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1922fcf5ef2aSThomas Huth tcg_temp_free(t0); 1923fcf5ef2aSThomas Huth } 1924fcf5ef2aSThomas Huth } 1925fcf5ef2aSThomas Huth /* Add functions with two operands */ 19264c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1927fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1928fcf5ef2aSThomas Huth { \ 1929fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1930fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 19314c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1932fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1933fcf5ef2aSThomas Huth } 1934fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 19354c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1936fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1937fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1938fcf5ef2aSThomas Huth { \ 1939fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1940fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1941fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 19424c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1943fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1944fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1945fcf5ef2aSThomas Huth } 1946fcf5ef2aSThomas Huth 1947fcf5ef2aSThomas Huth /* add add. addo addo. */ 19484c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 19494c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1950fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 19514c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 19524c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1953fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 19544c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 19554c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1956fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 19574c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 19584c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 19594c5920afSSuraj Jitindar Singh /* addex */ 19604c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1961fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 19624c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 19634c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1964fcf5ef2aSThomas Huth /* addi */ 1965fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 1966fcf5ef2aSThomas Huth { 1967fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1968fcf5ef2aSThomas Huth 1969fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1970fcf5ef2aSThomas Huth /* li case */ 1971fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 1972fcf5ef2aSThomas Huth } else { 1973fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1974fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 1975fcf5ef2aSThomas Huth } 1976fcf5ef2aSThomas Huth } 1977fcf5ef2aSThomas Huth /* addic addic.*/ 1978fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1979fcf5ef2aSThomas Huth { 1980fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1981fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 19824c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1983fcf5ef2aSThomas Huth tcg_temp_free(c); 1984fcf5ef2aSThomas Huth } 1985fcf5ef2aSThomas Huth 1986fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1987fcf5ef2aSThomas Huth { 1988fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1989fcf5ef2aSThomas Huth } 1990fcf5ef2aSThomas Huth 1991fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1992fcf5ef2aSThomas Huth { 1993fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1994fcf5ef2aSThomas Huth } 1995fcf5ef2aSThomas Huth 1996fcf5ef2aSThomas Huth /* addis */ 1997fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 1998fcf5ef2aSThomas Huth { 1999fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2000fcf5ef2aSThomas Huth 2001fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2002fcf5ef2aSThomas Huth /* lis case */ 2003fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 2004fcf5ef2aSThomas Huth } else { 2005fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 2006fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 2007fcf5ef2aSThomas Huth } 2008fcf5ef2aSThomas Huth } 2009fcf5ef2aSThomas Huth 2010fcf5ef2aSThomas Huth /* addpcis */ 2011fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 2012fcf5ef2aSThomas Huth { 2013fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 2014fcf5ef2aSThomas Huth 2015b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 2016fcf5ef2aSThomas Huth } 2017fcf5ef2aSThomas Huth 2018fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 2019fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2020fcf5ef2aSThomas Huth { 2021fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2022fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2023fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2024fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2025fcf5ef2aSThomas Huth 2026fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2027fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2028fcf5ef2aSThomas Huth if (sign) { 2029fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2030fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2031fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2032fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2033fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2034fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2035fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2036fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 2037fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2038fcf5ef2aSThomas Huth } else { 2039fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 2040fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2041fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2042fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 2043fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2044fcf5ef2aSThomas Huth } 2045fcf5ef2aSThomas Huth if (compute_ov) { 2046fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 2047c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2048c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 2049c44027ffSNikunj A Dadhania } 2050fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2051fcf5ef2aSThomas Huth } 2052fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2053fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2054fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2055fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2056fcf5ef2aSThomas Huth 2057efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2058fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2059fcf5ef2aSThomas Huth } 2060efe843d8SDavid Gibson } 2061fcf5ef2aSThomas Huth /* Div functions */ 2062fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 2063fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2064fcf5ef2aSThomas Huth { \ 2065fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2066fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2067fcf5ef2aSThomas Huth sign, compute_ov); \ 2068fcf5ef2aSThomas Huth } 2069fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 2070fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 2071fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 2072fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 2073fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 2074fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 2075fcf5ef2aSThomas Huth 2076fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 2077fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 2078fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 2079fcf5ef2aSThomas Huth { \ 2080fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 2081fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 2082fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 2083fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 2084fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 2085fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 2086fcf5ef2aSThomas Huth } \ 2087fcf5ef2aSThomas Huth } 2088fcf5ef2aSThomas Huth 2089fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 2090fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 2091fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 2092fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 2093fcf5ef2aSThomas Huth 2094fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2095fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 2096fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2097fcf5ef2aSThomas Huth { 2098fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2099fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2100fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2101fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2102fcf5ef2aSThomas Huth 2103fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2104fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2105fcf5ef2aSThomas Huth if (sign) { 2106fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2107fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2108fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2109fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2110fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2111fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2112fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2113fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 2114fcf5ef2aSThomas Huth } else { 2115fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 2116fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2117fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2118fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 2119fcf5ef2aSThomas Huth } 2120fcf5ef2aSThomas Huth if (compute_ov) { 2121fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 2122c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2123c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 2124c44027ffSNikunj A Dadhania } 2125fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2126fcf5ef2aSThomas Huth } 2127fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2128fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2129fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2130fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2131fcf5ef2aSThomas Huth 2132efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2133fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2134fcf5ef2aSThomas Huth } 2135efe843d8SDavid Gibson } 2136fcf5ef2aSThomas Huth 2137fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 2138fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2139fcf5ef2aSThomas Huth { \ 2140fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2141fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2142fcf5ef2aSThomas Huth sign, compute_ov); \ 2143fcf5ef2aSThomas Huth } 2144c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 2145fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 2146fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 2147c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 2148fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 2149fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 2150fcf5ef2aSThomas Huth 2151fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 2152fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 2153fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 2154fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 2155fcf5ef2aSThomas Huth #endif 2156fcf5ef2aSThomas Huth 2157fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 2158fcf5ef2aSThomas Huth TCGv arg2, int sign) 2159fcf5ef2aSThomas Huth { 2160fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2161fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2162fcf5ef2aSThomas Huth 2163fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2164fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2165fcf5ef2aSThomas Huth if (sign) { 2166fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2167fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2168fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2169fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2170fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2171fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2172fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2173fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2174fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2175fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 2176fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 2177fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2178fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2179fcf5ef2aSThomas Huth } else { 2180fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 2181fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 2182fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 2183fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 2184fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2185fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2186fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2187fcf5ef2aSThomas Huth } 2188fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2189fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2190fcf5ef2aSThomas Huth } 2191fcf5ef2aSThomas Huth 2192fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 2193fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2194fcf5ef2aSThomas Huth { \ 2195fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2196fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2197fcf5ef2aSThomas Huth sign); \ 2198fcf5ef2aSThomas Huth } 2199fcf5ef2aSThomas Huth 2200fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 2201fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 2202fcf5ef2aSThomas Huth 2203fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2204fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 2205fcf5ef2aSThomas Huth TCGv arg2, int sign) 2206fcf5ef2aSThomas Huth { 2207fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2208fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2209fcf5ef2aSThomas Huth 2210fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2211fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2212fcf5ef2aSThomas Huth if (sign) { 2213fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2214fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2215fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2216fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2217fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2218fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2219fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2220fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2221fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2222fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 2223fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2224fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2225fcf5ef2aSThomas Huth } else { 2226fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 2227fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2228fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2229fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2230fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2231fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2232fcf5ef2aSThomas Huth } 2233fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2234fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2235fcf5ef2aSThomas Huth } 2236fcf5ef2aSThomas Huth 2237fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2238fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2239fcf5ef2aSThomas Huth { \ 2240fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2241fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2242fcf5ef2aSThomas Huth sign); \ 2243fcf5ef2aSThomas Huth } 2244fcf5ef2aSThomas Huth 2245fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2246fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2247fcf5ef2aSThomas Huth #endif 2248fcf5ef2aSThomas Huth 2249fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2250fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2251fcf5ef2aSThomas Huth { 2252fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2253fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2254fcf5ef2aSThomas Huth 2255fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2256fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2257fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2258fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2259fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2260fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2261efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2262fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2263fcf5ef2aSThomas Huth } 2264efe843d8SDavid Gibson } 2265fcf5ef2aSThomas Huth 2266fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2267fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2268fcf5ef2aSThomas Huth { 2269fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2270fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2271fcf5ef2aSThomas Huth 2272fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2273fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2274fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2275fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2276fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2277fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2278efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2279fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2280fcf5ef2aSThomas Huth } 2281efe843d8SDavid Gibson } 2282fcf5ef2aSThomas Huth 2283fcf5ef2aSThomas Huth /* mullw mullw. */ 2284fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2285fcf5ef2aSThomas Huth { 2286fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2287fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2288fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2289fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2290fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2291fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2292fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2293fcf5ef2aSThomas Huth tcg_temp_free(t0); 2294fcf5ef2aSThomas Huth tcg_temp_free(t1); 2295fcf5ef2aSThomas Huth #else 2296fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2297fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2298fcf5ef2aSThomas Huth #endif 2299efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2300fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2301fcf5ef2aSThomas Huth } 2302efe843d8SDavid Gibson } 2303fcf5ef2aSThomas Huth 2304fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2305fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2306fcf5ef2aSThomas Huth { 2307fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2308fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2309fcf5ef2aSThomas Huth 2310fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2311fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2312fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2313fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2314fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2315fcf5ef2aSThomas Huth #else 2316fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2317fcf5ef2aSThomas Huth #endif 2318fcf5ef2aSThomas Huth 2319fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2320fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2321fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 232261aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 232361aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 232461aa9a69SNikunj A Dadhania } 2325fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2326fcf5ef2aSThomas Huth 2327fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2328fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2329efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2330fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2331fcf5ef2aSThomas Huth } 2332efe843d8SDavid Gibson } 2333fcf5ef2aSThomas Huth 2334fcf5ef2aSThomas Huth /* mulli */ 2335fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2336fcf5ef2aSThomas Huth { 2337fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2338fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2339fcf5ef2aSThomas Huth } 2340fcf5ef2aSThomas Huth 2341fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2342fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2343fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2344fcf5ef2aSThomas Huth { 2345fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2346fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2347fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2348fcf5ef2aSThomas Huth tcg_temp_free(lo); 2349fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2350fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2351fcf5ef2aSThomas Huth } 2352fcf5ef2aSThomas Huth } 2353fcf5ef2aSThomas Huth 2354fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2355fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2356fcf5ef2aSThomas Huth { 2357fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2358fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2359fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2360fcf5ef2aSThomas Huth tcg_temp_free(lo); 2361fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2362fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2363fcf5ef2aSThomas Huth } 2364fcf5ef2aSThomas Huth } 2365fcf5ef2aSThomas Huth 2366fcf5ef2aSThomas Huth /* mulld mulld. */ 2367fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2368fcf5ef2aSThomas Huth { 2369fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2370fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2371efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2372fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2373fcf5ef2aSThomas Huth } 2374efe843d8SDavid Gibson } 2375fcf5ef2aSThomas Huth 2376fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2377fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2378fcf5ef2aSThomas Huth { 2379fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2380fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2381fcf5ef2aSThomas Huth 2382fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2383fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2384fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2385fcf5ef2aSThomas Huth 2386fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2387fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 238861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 238961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 239061aa9a69SNikunj A Dadhania } 2391fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2392fcf5ef2aSThomas Huth 2393fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2394fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2395fcf5ef2aSThomas Huth 2396fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2397fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2398fcf5ef2aSThomas Huth } 2399fcf5ef2aSThomas Huth } 2400fcf5ef2aSThomas Huth #endif 2401fcf5ef2aSThomas Huth 2402fcf5ef2aSThomas Huth /* Common subf function */ 2403fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2404fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2405fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2406fcf5ef2aSThomas Huth { 2407fcf5ef2aSThomas Huth TCGv t0 = ret; 2408fcf5ef2aSThomas Huth 2409fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2410fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2411fcf5ef2aSThomas Huth } 2412fcf5ef2aSThomas Huth 2413fcf5ef2aSThomas Huth if (compute_ca) { 2414fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2415fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2416efe843d8SDavid Gibson /* 2417efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2418efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2419efe843d8SDavid Gibson * produce the carry into bit 32. 2420efe843d8SDavid Gibson */ 2421fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2422fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2423fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2424fcf5ef2aSThomas Huth if (add_ca) { 2425fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2426fcf5ef2aSThomas Huth } else { 2427fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2428fcf5ef2aSThomas Huth } 2429fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2430fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2431fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2432fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2433fcf5ef2aSThomas Huth tcg_temp_free(t1); 2434e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 243533903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 243633903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 243733903d0aSNikunj A Dadhania } 2438fcf5ef2aSThomas Huth } else if (add_ca) { 2439fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2440fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2441fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2442fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2443fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 24444c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2445fcf5ef2aSThomas Huth tcg_temp_free(zero); 2446fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2447fcf5ef2aSThomas Huth } else { 2448fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2449fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 24504c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2451fcf5ef2aSThomas Huth } 2452fcf5ef2aSThomas Huth } else if (add_ca) { 2453efe843d8SDavid Gibson /* 2454efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2455efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2456efe843d8SDavid Gibson */ 2457fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2458fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2459fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2460fcf5ef2aSThomas Huth } else { 2461fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2462fcf5ef2aSThomas Huth } 2463fcf5ef2aSThomas Huth 2464fcf5ef2aSThomas Huth if (compute_ov) { 2465fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2466fcf5ef2aSThomas Huth } 2467fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2468fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2469fcf5ef2aSThomas Huth } 2470fcf5ef2aSThomas Huth 247111f4e8f8SRichard Henderson if (t0 != ret) { 2472fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2473fcf5ef2aSThomas Huth tcg_temp_free(t0); 2474fcf5ef2aSThomas Huth } 2475fcf5ef2aSThomas Huth } 2476fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2477fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2478fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2479fcf5ef2aSThomas Huth { \ 2480fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2481fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2482fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2483fcf5ef2aSThomas Huth } 2484fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2485fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2486fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2487fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2488fcf5ef2aSThomas Huth { \ 2489fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2490fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2491fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2492fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2493fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2494fcf5ef2aSThomas Huth } 2495fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2496fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2497fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2498fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2499fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2500fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2501fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2502fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2503fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2504fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2505fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2506fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2507fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2508fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2509fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2510fcf5ef2aSThomas Huth 2511fcf5ef2aSThomas Huth /* subfic */ 2512fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2513fcf5ef2aSThomas Huth { 2514fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2515fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2516fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2517fcf5ef2aSThomas Huth tcg_temp_free(c); 2518fcf5ef2aSThomas Huth } 2519fcf5ef2aSThomas Huth 2520fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2521fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2522fcf5ef2aSThomas Huth { 2523fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2524fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2525fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2526fcf5ef2aSThomas Huth tcg_temp_free(zero); 2527fcf5ef2aSThomas Huth } 2528fcf5ef2aSThomas Huth 2529fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2530fcf5ef2aSThomas Huth { 25311480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 25321480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 25331480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 25341480d71cSNikunj A Dadhania } 2535fcf5ef2aSThomas Huth } 2536fcf5ef2aSThomas Huth 2537fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2538fcf5ef2aSThomas Huth { 2539fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2540fcf5ef2aSThomas Huth } 2541fcf5ef2aSThomas Huth 2542fcf5ef2aSThomas Huth /*** Integer logical ***/ 2543fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2544fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2545fcf5ef2aSThomas Huth { \ 2546fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2547fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2548fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2549fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2550fcf5ef2aSThomas Huth } 2551fcf5ef2aSThomas Huth 2552fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2553fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2554fcf5ef2aSThomas Huth { \ 2555fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2556fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2557fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2558fcf5ef2aSThomas Huth } 2559fcf5ef2aSThomas Huth 2560fcf5ef2aSThomas Huth /* and & and. */ 2561fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2562fcf5ef2aSThomas Huth /* andc & andc. */ 2563fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2564fcf5ef2aSThomas Huth 2565fcf5ef2aSThomas Huth /* andi. */ 2566fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2567fcf5ef2aSThomas Huth { 2568efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2569efe843d8SDavid Gibson UIMM(ctx->opcode)); 2570fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2571fcf5ef2aSThomas Huth } 2572fcf5ef2aSThomas Huth 2573fcf5ef2aSThomas Huth /* andis. */ 2574fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2575fcf5ef2aSThomas Huth { 2576efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2577efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2578fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2579fcf5ef2aSThomas Huth } 2580fcf5ef2aSThomas Huth 2581fcf5ef2aSThomas Huth /* cntlzw */ 2582fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2583fcf5ef2aSThomas Huth { 25849b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 25859b8514e5SRichard Henderson 25869b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 25879b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 25889b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 25899b8514e5SRichard Henderson tcg_temp_free_i32(t); 25909b8514e5SRichard Henderson 2591efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2592fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2593fcf5ef2aSThomas Huth } 2594efe843d8SDavid Gibson } 2595fcf5ef2aSThomas Huth 2596fcf5ef2aSThomas Huth /* cnttzw */ 2597fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2598fcf5ef2aSThomas Huth { 25999b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 26009b8514e5SRichard Henderson 26019b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 26029b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 26039b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 26049b8514e5SRichard Henderson tcg_temp_free_i32(t); 26059b8514e5SRichard Henderson 2606fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2607fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2608fcf5ef2aSThomas Huth } 2609fcf5ef2aSThomas Huth } 2610fcf5ef2aSThomas Huth 2611fcf5ef2aSThomas Huth /* eqv & eqv. */ 2612fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2613fcf5ef2aSThomas Huth /* extsb & extsb. */ 2614fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2615fcf5ef2aSThomas Huth /* extsh & extsh. */ 2616fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2617fcf5ef2aSThomas Huth /* nand & nand. */ 2618fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2619fcf5ef2aSThomas Huth /* nor & nor. */ 2620fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2621fcf5ef2aSThomas Huth 2622fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2623fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2624fcf5ef2aSThomas Huth { 2625fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2626fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2627fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2628fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2629fcf5ef2aSThomas Huth 2630fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2631b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2632fcf5ef2aSThomas Huth } 2633fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2634fcf5ef2aSThomas Huth 2635fcf5ef2aSThomas Huth /* or & or. */ 2636fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2637fcf5ef2aSThomas Huth { 2638fcf5ef2aSThomas Huth int rs, ra, rb; 2639fcf5ef2aSThomas Huth 2640fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2641fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2642fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2643fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2644fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2645efe843d8SDavid Gibson if (rs != rb) { 2646fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2647efe843d8SDavid Gibson } else { 2648fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2649efe843d8SDavid Gibson } 2650efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2651fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2652efe843d8SDavid Gibson } 2653fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2654fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2655fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2656fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2657fcf5ef2aSThomas Huth int prio = 0; 2658fcf5ef2aSThomas Huth 2659fcf5ef2aSThomas Huth switch (rs) { 2660fcf5ef2aSThomas Huth case 1: 2661fcf5ef2aSThomas Huth /* Set process priority to low */ 2662fcf5ef2aSThomas Huth prio = 2; 2663fcf5ef2aSThomas Huth break; 2664fcf5ef2aSThomas Huth case 6: 2665fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2666fcf5ef2aSThomas Huth prio = 3; 2667fcf5ef2aSThomas Huth break; 2668fcf5ef2aSThomas Huth case 2: 2669fcf5ef2aSThomas Huth /* Set process priority to normal */ 2670fcf5ef2aSThomas Huth prio = 4; 2671fcf5ef2aSThomas Huth break; 2672fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2673fcf5ef2aSThomas Huth case 31: 2674fcf5ef2aSThomas Huth if (!ctx->pr) { 2675fcf5ef2aSThomas Huth /* Set process priority to very low */ 2676fcf5ef2aSThomas Huth prio = 1; 2677fcf5ef2aSThomas Huth } 2678fcf5ef2aSThomas Huth break; 2679fcf5ef2aSThomas Huth case 5: 2680fcf5ef2aSThomas Huth if (!ctx->pr) { 2681fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2682fcf5ef2aSThomas Huth prio = 5; 2683fcf5ef2aSThomas Huth } 2684fcf5ef2aSThomas Huth break; 2685fcf5ef2aSThomas Huth case 3: 2686fcf5ef2aSThomas Huth if (!ctx->pr) { 2687fcf5ef2aSThomas Huth /* Set process priority to high */ 2688fcf5ef2aSThomas Huth prio = 6; 2689fcf5ef2aSThomas Huth } 2690fcf5ef2aSThomas Huth break; 2691fcf5ef2aSThomas Huth case 7: 2692fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2693fcf5ef2aSThomas Huth /* Set process priority to very high */ 2694fcf5ef2aSThomas Huth prio = 7; 2695fcf5ef2aSThomas Huth } 2696fcf5ef2aSThomas Huth break; 2697fcf5ef2aSThomas Huth #endif 2698fcf5ef2aSThomas Huth default: 2699fcf5ef2aSThomas Huth break; 2700fcf5ef2aSThomas Huth } 2701fcf5ef2aSThomas Huth if (prio) { 2702fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2703fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2704fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2705fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2706fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2707fcf5ef2aSThomas Huth tcg_temp_free(t0); 2708fcf5ef2aSThomas Huth } 2709fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2710efe843d8SDavid Gibson /* 2711efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2712efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2713efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2714efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2715fcf5ef2aSThomas Huth */ 2716fcf5ef2aSThomas Huth gen_pause(ctx); 2717fcf5ef2aSThomas Huth #endif 2718fcf5ef2aSThomas Huth #endif 2719fcf5ef2aSThomas Huth } 2720fcf5ef2aSThomas Huth } 2721fcf5ef2aSThomas Huth /* orc & orc. */ 2722fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2723fcf5ef2aSThomas Huth 2724fcf5ef2aSThomas Huth /* xor & xor. */ 2725fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2726fcf5ef2aSThomas Huth { 2727fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2728efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2729efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2730efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2731efe843d8SDavid Gibson } else { 2732fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2733efe843d8SDavid Gibson } 2734efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2735fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2736fcf5ef2aSThomas Huth } 2737efe843d8SDavid Gibson } 2738fcf5ef2aSThomas Huth 2739fcf5ef2aSThomas Huth /* ori */ 2740fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2741fcf5ef2aSThomas Huth { 2742fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2743fcf5ef2aSThomas Huth 2744fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2745fcf5ef2aSThomas Huth return; 2746fcf5ef2aSThomas Huth } 2747fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2748fcf5ef2aSThomas Huth } 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth /* oris */ 2751fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2752fcf5ef2aSThomas Huth { 2753fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2754fcf5ef2aSThomas Huth 2755fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2756fcf5ef2aSThomas Huth /* NOP */ 2757fcf5ef2aSThomas Huth return; 2758fcf5ef2aSThomas Huth } 2759efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2760efe843d8SDavid Gibson uimm << 16); 2761fcf5ef2aSThomas Huth } 2762fcf5ef2aSThomas Huth 2763fcf5ef2aSThomas Huth /* xori */ 2764fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2765fcf5ef2aSThomas Huth { 2766fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2767fcf5ef2aSThomas Huth 2768fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2769fcf5ef2aSThomas Huth /* NOP */ 2770fcf5ef2aSThomas Huth return; 2771fcf5ef2aSThomas Huth } 2772fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2773fcf5ef2aSThomas Huth } 2774fcf5ef2aSThomas Huth 2775fcf5ef2aSThomas Huth /* xoris */ 2776fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2777fcf5ef2aSThomas Huth { 2778fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2779fcf5ef2aSThomas Huth 2780fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2781fcf5ef2aSThomas Huth /* NOP */ 2782fcf5ef2aSThomas Huth return; 2783fcf5ef2aSThomas Huth } 2784efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2785efe843d8SDavid Gibson uimm << 16); 2786fcf5ef2aSThomas Huth } 2787fcf5ef2aSThomas Huth 2788fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2789fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2790fcf5ef2aSThomas Huth { 2791fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2792fcf5ef2aSThomas Huth } 2793fcf5ef2aSThomas Huth 2794fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2795fcf5ef2aSThomas Huth { 279679770002SRichard Henderson #if defined(TARGET_PPC64) 2797fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 279879770002SRichard Henderson #else 279979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 280079770002SRichard Henderson #endif 2801fcf5ef2aSThomas Huth } 2802fcf5ef2aSThomas Huth 2803fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2804fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2805fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2806fcf5ef2aSThomas Huth { 280779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2808fcf5ef2aSThomas Huth } 2809fcf5ef2aSThomas Huth #endif 2810fcf5ef2aSThomas Huth 2811fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2812fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2813fcf5ef2aSThomas Huth { 2814fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2815fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2816fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2817fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2818fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2819fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2820fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2821fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2822fcf5ef2aSThomas Huth tcg_temp_free(t0); 2823fcf5ef2aSThomas Huth } 2824fcf5ef2aSThomas Huth 2825fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2826fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2827fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2828fcf5ef2aSThomas Huth { 2829fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2830fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2831fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2832fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2833fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2834fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2835fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2836fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2837fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2838fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2839fcf5ef2aSThomas Huth tcg_temp_free(t0); 2840fcf5ef2aSThomas Huth } 2841fcf5ef2aSThomas Huth #endif 2842fcf5ef2aSThomas Huth 2843fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2844fcf5ef2aSThomas Huth /* bpermd */ 2845fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2846fcf5ef2aSThomas Huth { 2847fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2848fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth #endif 2851fcf5ef2aSThomas Huth 2852fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2853fcf5ef2aSThomas Huth /* extsw & extsw. */ 2854fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2855fcf5ef2aSThomas Huth 2856fcf5ef2aSThomas Huth /* cntlzd */ 2857fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2858fcf5ef2aSThomas Huth { 28599b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2860efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2861fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2862fcf5ef2aSThomas Huth } 2863efe843d8SDavid Gibson } 2864fcf5ef2aSThomas Huth 2865fcf5ef2aSThomas Huth /* cnttzd */ 2866fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2867fcf5ef2aSThomas Huth { 28689b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2869fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2870fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2871fcf5ef2aSThomas Huth } 2872fcf5ef2aSThomas Huth } 2873fcf5ef2aSThomas Huth 2874fcf5ef2aSThomas Huth /* darn */ 2875fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2876fcf5ef2aSThomas Huth { 2877fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2878fcf5ef2aSThomas Huth 28797e4357f6SRichard Henderson if (l > 2) { 28807e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 28817e4357f6SRichard Henderson } else { 28827e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28837e4357f6SRichard Henderson gen_io_start(); 28847e4357f6SRichard Henderson } 2885fcf5ef2aSThomas Huth if (l == 0) { 2886fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 28877e4357f6SRichard Henderson } else { 2888fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2889fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 28907e4357f6SRichard Henderson } 28917e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28927e4357f6SRichard Henderson gen_stop_exception(ctx); 28937e4357f6SRichard Henderson } 2894fcf5ef2aSThomas Huth } 2895fcf5ef2aSThomas Huth } 2896fcf5ef2aSThomas Huth #endif 2897fcf5ef2aSThomas Huth 2898fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2899fcf5ef2aSThomas Huth 2900fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2901fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2902fcf5ef2aSThomas Huth { 2903fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2904fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2905fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2906fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2907fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2908fcf5ef2aSThomas Huth 2909fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2910fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2911fcf5ef2aSThomas Huth } else { 2912fcf5ef2aSThomas Huth target_ulong mask; 2913c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2914fcf5ef2aSThomas Huth TCGv t1; 2915fcf5ef2aSThomas Huth 2916fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2917fcf5ef2aSThomas Huth mb += 32; 2918fcf5ef2aSThomas Huth me += 32; 2919fcf5ef2aSThomas Huth #endif 2920fcf5ef2aSThomas Huth mask = MASK(mb, me); 2921fcf5ef2aSThomas Huth 2922c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2923c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2924c4f6a4a3SDaniele Buono mask_in_32b = false; 2925c4f6a4a3SDaniele Buono } 2926c4f6a4a3SDaniele Buono #endif 2927fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2928c4f6a4a3SDaniele Buono if (mask_in_32b) { 2929fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2930fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2931fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2932fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2933fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2934fcf5ef2aSThomas Huth } else { 2935fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2936fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2937fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2938fcf5ef2aSThomas Huth #else 2939fcf5ef2aSThomas Huth g_assert_not_reached(); 2940fcf5ef2aSThomas Huth #endif 2941fcf5ef2aSThomas Huth } 2942fcf5ef2aSThomas Huth 2943fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2944fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2945fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2946fcf5ef2aSThomas Huth tcg_temp_free(t1); 2947fcf5ef2aSThomas Huth } 2948fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2949fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2950fcf5ef2aSThomas Huth } 2951fcf5ef2aSThomas Huth } 2952fcf5ef2aSThomas Huth 2953fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2954fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2955fcf5ef2aSThomas Huth { 2956fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2957fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 29587b4d326fSRichard Henderson int sh = SH(ctx->opcode); 29597b4d326fSRichard Henderson int mb = MB(ctx->opcode); 29607b4d326fSRichard Henderson int me = ME(ctx->opcode); 29617b4d326fSRichard Henderson int len = me - mb + 1; 29627b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2963fcf5ef2aSThomas Huth 29647b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 29657b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 29667b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 29677b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2968fcf5ef2aSThomas Huth } else { 2969fcf5ef2aSThomas Huth target_ulong mask; 2970c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2971fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2972fcf5ef2aSThomas Huth mb += 32; 2973fcf5ef2aSThomas Huth me += 32; 2974fcf5ef2aSThomas Huth #endif 2975fcf5ef2aSThomas Huth mask = MASK(mb, me); 2976c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2977c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2978c4f6a4a3SDaniele Buono mask_in_32b = false; 2979c4f6a4a3SDaniele Buono } 2980c4f6a4a3SDaniele Buono #endif 2981c4f6a4a3SDaniele Buono if (mask_in_32b) { 29827b4d326fSRichard Henderson if (sh == 0) { 29837b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 298494f040aaSVitaly Chikunov } else { 2985fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2986fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2987fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2988fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2989fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2990fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 299194f040aaSVitaly Chikunov } 2992fcf5ef2aSThomas Huth } else { 2993fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2994fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2995fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2996fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2997fcf5ef2aSThomas Huth #else 2998fcf5ef2aSThomas Huth g_assert_not_reached(); 2999fcf5ef2aSThomas Huth #endif 3000fcf5ef2aSThomas Huth } 3001fcf5ef2aSThomas Huth } 3002fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3003fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3004fcf5ef2aSThomas Huth } 3005fcf5ef2aSThomas Huth } 3006fcf5ef2aSThomas Huth 3007fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 3008fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 3009fcf5ef2aSThomas Huth { 3010fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3011fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3012fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3013fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 3014fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 3015fcf5ef2aSThomas Huth target_ulong mask; 3016c4f6a4a3SDaniele Buono bool mask_in_32b = true; 3017fcf5ef2aSThomas Huth 3018fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3019fcf5ef2aSThomas Huth mb += 32; 3020fcf5ef2aSThomas Huth me += 32; 3021fcf5ef2aSThomas Huth #endif 3022fcf5ef2aSThomas Huth mask = MASK(mb, me); 3023fcf5ef2aSThomas Huth 3024c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 3025c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 3026c4f6a4a3SDaniele Buono mask_in_32b = false; 3027c4f6a4a3SDaniele Buono } 3028c4f6a4a3SDaniele Buono #endif 3029c4f6a4a3SDaniele Buono if (mask_in_32b) { 3030fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3031fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3032fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 3033fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 3034fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 3035fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 3036fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 3037fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3038fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3039fcf5ef2aSThomas Huth } else { 3040fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3041fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 3042fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 3043fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 3044fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 3045fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 3046fcf5ef2aSThomas Huth #else 3047fcf5ef2aSThomas Huth g_assert_not_reached(); 3048fcf5ef2aSThomas Huth #endif 3049fcf5ef2aSThomas Huth } 3050fcf5ef2aSThomas Huth 3051fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 3052fcf5ef2aSThomas Huth 3053fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3054fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3055fcf5ef2aSThomas Huth } 3056fcf5ef2aSThomas Huth } 3057fcf5ef2aSThomas Huth 3058fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3059fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 3060fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3061fcf5ef2aSThomas Huth { \ 3062fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 3063fcf5ef2aSThomas Huth } \ 3064fcf5ef2aSThomas Huth \ 3065fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3066fcf5ef2aSThomas Huth { \ 3067fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 3068fcf5ef2aSThomas Huth } 3069fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 3070fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3071fcf5ef2aSThomas Huth { \ 3072fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 3073fcf5ef2aSThomas Huth } \ 3074fcf5ef2aSThomas Huth \ 3075fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3076fcf5ef2aSThomas Huth { \ 3077fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 3078fcf5ef2aSThomas Huth } \ 3079fcf5ef2aSThomas Huth \ 3080fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 3081fcf5ef2aSThomas Huth { \ 3082fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 3083fcf5ef2aSThomas Huth } \ 3084fcf5ef2aSThomas Huth \ 3085fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 3086fcf5ef2aSThomas Huth { \ 3087fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 3088fcf5ef2aSThomas Huth } 3089fcf5ef2aSThomas Huth 3090fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 3091fcf5ef2aSThomas Huth { 3092fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3093fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 30947b4d326fSRichard Henderson int len = me - mb + 1; 30957b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 3096fcf5ef2aSThomas Huth 30977b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 30987b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 30997b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 31007b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 3101fcf5ef2aSThomas Huth } else { 3102fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 3103fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3104fcf5ef2aSThomas Huth } 3105fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3106fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3107fcf5ef2aSThomas Huth } 3108fcf5ef2aSThomas Huth } 3109fcf5ef2aSThomas Huth 3110fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 3111fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 3112fcf5ef2aSThomas Huth { 3113fcf5ef2aSThomas Huth uint32_t sh, mb; 3114fcf5ef2aSThomas Huth 3115fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3116fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3117fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 3118fcf5ef2aSThomas Huth } 3119fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 3120fcf5ef2aSThomas Huth 3121fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 3122fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 3123fcf5ef2aSThomas Huth { 3124fcf5ef2aSThomas Huth uint32_t sh, me; 3125fcf5ef2aSThomas Huth 3126fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3127fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3128fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 3129fcf5ef2aSThomas Huth } 3130fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 3131fcf5ef2aSThomas Huth 3132fcf5ef2aSThomas Huth /* rldic - rldic. */ 3133fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 3134fcf5ef2aSThomas Huth { 3135fcf5ef2aSThomas Huth uint32_t sh, mb; 3136fcf5ef2aSThomas Huth 3137fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3138fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3139fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 3140fcf5ef2aSThomas Huth } 3141fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 3142fcf5ef2aSThomas Huth 3143fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 3144fcf5ef2aSThomas Huth { 3145fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3146fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3147fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3148fcf5ef2aSThomas Huth TCGv t0; 3149fcf5ef2aSThomas Huth 3150fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3151fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 3152fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 3153fcf5ef2aSThomas Huth tcg_temp_free(t0); 3154fcf5ef2aSThomas Huth 3155fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3156fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3157fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3158fcf5ef2aSThomas Huth } 3159fcf5ef2aSThomas Huth } 3160fcf5ef2aSThomas Huth 3161fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 3162fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 3163fcf5ef2aSThomas Huth { 3164fcf5ef2aSThomas Huth uint32_t mb; 3165fcf5ef2aSThomas Huth 3166fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3167fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 3168fcf5ef2aSThomas Huth } 3169fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 3170fcf5ef2aSThomas Huth 3171fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 3172fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 3173fcf5ef2aSThomas Huth { 3174fcf5ef2aSThomas Huth uint32_t me; 3175fcf5ef2aSThomas Huth 3176fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3177fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 3178fcf5ef2aSThomas Huth } 3179fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 3180fcf5ef2aSThomas Huth 3181fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 3182fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 3183fcf5ef2aSThomas Huth { 3184fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3185fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3186fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 3187fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 3188fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 3189fcf5ef2aSThomas Huth 3190fcf5ef2aSThomas Huth if (mb <= me) { 3191fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 3192fcf5ef2aSThomas Huth } else { 3193fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 3194fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3195fcf5ef2aSThomas Huth 3196fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 3197fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 3198fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 3199fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 3200fcf5ef2aSThomas Huth tcg_temp_free(t1); 3201fcf5ef2aSThomas Huth } 3202fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3203fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3204fcf5ef2aSThomas Huth } 3205fcf5ef2aSThomas Huth } 3206fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 3207fcf5ef2aSThomas Huth #endif 3208fcf5ef2aSThomas Huth 3209fcf5ef2aSThomas Huth /*** Integer shift ***/ 3210fcf5ef2aSThomas Huth 3211fcf5ef2aSThomas Huth /* slw & slw. */ 3212fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 3213fcf5ef2aSThomas Huth { 3214fcf5ef2aSThomas Huth TCGv t0, t1; 3215fcf5ef2aSThomas Huth 3216fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3217fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3218fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3219fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3220fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3221fcf5ef2aSThomas Huth #else 3222fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3223fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3224fcf5ef2aSThomas Huth #endif 3225fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3226fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3227fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3228fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3229fcf5ef2aSThomas Huth tcg_temp_free(t1); 3230fcf5ef2aSThomas Huth tcg_temp_free(t0); 3231fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 3232efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3233fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3234fcf5ef2aSThomas Huth } 3235efe843d8SDavid Gibson } 3236fcf5ef2aSThomas Huth 3237fcf5ef2aSThomas Huth /* sraw & sraw. */ 3238fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3239fcf5ef2aSThomas Huth { 3240fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3241fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3242efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3243fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3244fcf5ef2aSThomas Huth } 3245efe843d8SDavid Gibson } 3246fcf5ef2aSThomas Huth 3247fcf5ef2aSThomas Huth /* srawi & srawi. */ 3248fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3249fcf5ef2aSThomas Huth { 3250fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3251fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3252fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3253fcf5ef2aSThomas Huth if (sh == 0) { 3254fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3255fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3256af1c259fSSandipan Das if (is_isa300(ctx)) { 3257af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3258af1c259fSSandipan Das } 3259fcf5ef2aSThomas Huth } else { 3260fcf5ef2aSThomas Huth TCGv t0; 3261fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3262fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3263fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3264fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3265fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3266fcf5ef2aSThomas Huth tcg_temp_free(t0); 3267fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3268af1c259fSSandipan Das if (is_isa300(ctx)) { 3269af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3270af1c259fSSandipan Das } 3271fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3272fcf5ef2aSThomas Huth } 3273fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3274fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3275fcf5ef2aSThomas Huth } 3276fcf5ef2aSThomas Huth } 3277fcf5ef2aSThomas Huth 3278fcf5ef2aSThomas Huth /* srw & srw. */ 3279fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3280fcf5ef2aSThomas Huth { 3281fcf5ef2aSThomas Huth TCGv t0, t1; 3282fcf5ef2aSThomas Huth 3283fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3284fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3285fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3286fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3287fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3288fcf5ef2aSThomas Huth #else 3289fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3290fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3291fcf5ef2aSThomas Huth #endif 3292fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3293fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3294fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3295fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3296fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3297fcf5ef2aSThomas Huth tcg_temp_free(t1); 3298fcf5ef2aSThomas Huth tcg_temp_free(t0); 3299efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3300fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3301fcf5ef2aSThomas Huth } 3302efe843d8SDavid Gibson } 3303fcf5ef2aSThomas Huth 3304fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3305fcf5ef2aSThomas Huth /* sld & sld. */ 3306fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3307fcf5ef2aSThomas Huth { 3308fcf5ef2aSThomas Huth TCGv t0, t1; 3309fcf5ef2aSThomas Huth 3310fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3311fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3312fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3313fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3314fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3315fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3316fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3317fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3318fcf5ef2aSThomas Huth tcg_temp_free(t1); 3319fcf5ef2aSThomas Huth tcg_temp_free(t0); 3320efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3321fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3322fcf5ef2aSThomas Huth } 3323efe843d8SDavid Gibson } 3324fcf5ef2aSThomas Huth 3325fcf5ef2aSThomas Huth /* srad & srad. */ 3326fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3327fcf5ef2aSThomas Huth { 3328fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3329fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3330efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3331fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3332fcf5ef2aSThomas Huth } 3333efe843d8SDavid Gibson } 3334fcf5ef2aSThomas Huth /* sradi & sradi. */ 3335fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3336fcf5ef2aSThomas Huth { 3337fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3338fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3339fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3340fcf5ef2aSThomas Huth if (sh == 0) { 3341fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3342fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3343af1c259fSSandipan Das if (is_isa300(ctx)) { 3344af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3345af1c259fSSandipan Das } 3346fcf5ef2aSThomas Huth } else { 3347fcf5ef2aSThomas Huth TCGv t0; 3348fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3349fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3350fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3351fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3352fcf5ef2aSThomas Huth tcg_temp_free(t0); 3353fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3354af1c259fSSandipan Das if (is_isa300(ctx)) { 3355af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3356af1c259fSSandipan Das } 3357fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3358fcf5ef2aSThomas Huth } 3359fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3360fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3361fcf5ef2aSThomas Huth } 3362fcf5ef2aSThomas Huth } 3363fcf5ef2aSThomas Huth 3364fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3365fcf5ef2aSThomas Huth { 3366fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3367fcf5ef2aSThomas Huth } 3368fcf5ef2aSThomas Huth 3369fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3370fcf5ef2aSThomas Huth { 3371fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3372fcf5ef2aSThomas Huth } 3373fcf5ef2aSThomas Huth 3374fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3375fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3376fcf5ef2aSThomas Huth { 3377fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3378fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3379fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3380fcf5ef2aSThomas Huth 3381fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3382fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3383fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3384fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3385fcf5ef2aSThomas Huth } 3386fcf5ef2aSThomas Huth } 3387fcf5ef2aSThomas Huth 3388fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3389fcf5ef2aSThomas Huth { 3390fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3391fcf5ef2aSThomas Huth } 3392fcf5ef2aSThomas Huth 3393fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3394fcf5ef2aSThomas Huth { 3395fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3396fcf5ef2aSThomas Huth } 3397fcf5ef2aSThomas Huth 3398fcf5ef2aSThomas Huth /* srd & srd. */ 3399fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3400fcf5ef2aSThomas Huth { 3401fcf5ef2aSThomas Huth TCGv t0, t1; 3402fcf5ef2aSThomas Huth 3403fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3404fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3405fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3406fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3407fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3408fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3409fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3410fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3411fcf5ef2aSThomas Huth tcg_temp_free(t1); 3412fcf5ef2aSThomas Huth tcg_temp_free(t0); 3413efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3414fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3415fcf5ef2aSThomas Huth } 3416efe843d8SDavid Gibson } 3417fcf5ef2aSThomas Huth #endif 3418fcf5ef2aSThomas Huth 3419fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3420fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3421fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3422fcf5ef2aSThomas Huth target_long maskl) 3423fcf5ef2aSThomas Huth { 3424fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3425fcf5ef2aSThomas Huth 3426fcf5ef2aSThomas Huth simm &= ~maskl; 3427fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3428fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3429fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3430fcf5ef2aSThomas Huth } 3431fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3432fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3433fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3434fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3435fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3436fcf5ef2aSThomas Huth } 3437fcf5ef2aSThomas Huth } else { 3438fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3439fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3440fcf5ef2aSThomas Huth } else { 3441fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3442fcf5ef2aSThomas Huth } 3443fcf5ef2aSThomas Huth } 3444fcf5ef2aSThomas Huth } 3445fcf5ef2aSThomas Huth 3446fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3447fcf5ef2aSThomas Huth { 3448fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3449fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3450fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3451fcf5ef2aSThomas Huth } else { 3452fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3453fcf5ef2aSThomas Huth } 3454fcf5ef2aSThomas Huth } else { 3455fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3456fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3457fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3458fcf5ef2aSThomas Huth } 3459fcf5ef2aSThomas Huth } 3460fcf5ef2aSThomas Huth } 3461fcf5ef2aSThomas Huth 3462fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3463fcf5ef2aSThomas Huth { 3464fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3465fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3466fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3467fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3468fcf5ef2aSThomas Huth } else { 3469fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3470fcf5ef2aSThomas Huth } 3471fcf5ef2aSThomas Huth } 3472fcf5ef2aSThomas Huth 3473fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3474fcf5ef2aSThomas Huth target_long val) 3475fcf5ef2aSThomas Huth { 3476fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3477fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3478fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3479fcf5ef2aSThomas Huth } 3480fcf5ef2aSThomas Huth } 3481fcf5ef2aSThomas Huth 3482fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3483fcf5ef2aSThomas Huth { 3484fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3485fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3486fcf5ef2aSThomas Huth } 3487fcf5ef2aSThomas Huth 3488fcf5ef2aSThomas Huth /*** Integer load ***/ 3489fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3490fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3491fcf5ef2aSThomas Huth 3492fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3493fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3494fcf5ef2aSThomas Huth TCGv val, \ 3495fcf5ef2aSThomas Huth TCGv addr) \ 3496fcf5ef2aSThomas Huth { \ 3497fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3498fcf5ef2aSThomas Huth } 3499fcf5ef2aSThomas Huth 3500fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3501fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3502fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3503fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3504fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3505fcf5ef2aSThomas Huth 3506fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3507fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3508fcf5ef2aSThomas Huth 3509fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3510fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3511fcf5ef2aSThomas Huth TCGv_i64 val, \ 3512fcf5ef2aSThomas Huth TCGv addr) \ 3513fcf5ef2aSThomas Huth { \ 3514fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3515fcf5ef2aSThomas Huth } 3516fcf5ef2aSThomas Huth 3517fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3518fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3519fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3520fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3521fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3522fcf5ef2aSThomas Huth 3523fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3524fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3525fcf5ef2aSThomas Huth #endif 3526fcf5ef2aSThomas Huth 3527fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3528fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3529fcf5ef2aSThomas Huth TCGv val, \ 3530fcf5ef2aSThomas Huth TCGv addr) \ 3531fcf5ef2aSThomas Huth { \ 3532fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3533fcf5ef2aSThomas Huth } 3534fcf5ef2aSThomas Huth 3535fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3536fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3537fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3538fcf5ef2aSThomas Huth 3539fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3540fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3541fcf5ef2aSThomas Huth 3542fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3543fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3544fcf5ef2aSThomas Huth TCGv_i64 val, \ 3545fcf5ef2aSThomas Huth TCGv addr) \ 3546fcf5ef2aSThomas Huth { \ 3547fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3548fcf5ef2aSThomas Huth } 3549fcf5ef2aSThomas Huth 3550fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3551fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3552fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3553fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3554fcf5ef2aSThomas Huth 3555fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3556fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3557fcf5ef2aSThomas Huth #endif 3558fcf5ef2aSThomas Huth 3559fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 3560fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3561fcf5ef2aSThomas Huth { \ 3562fcf5ef2aSThomas Huth TCGv EA; \ 3563fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3564fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3565fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3566fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3567fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3568fcf5ef2aSThomas Huth } 3569fcf5ef2aSThomas Huth 3570fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 3571fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 3572fcf5ef2aSThomas Huth { \ 3573fcf5ef2aSThomas Huth TCGv EA; \ 3574fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3575fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3576fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3577fcf5ef2aSThomas Huth return; \ 3578fcf5ef2aSThomas Huth } \ 3579fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3580fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3581fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3582fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3583fcf5ef2aSThomas Huth else \ 3584fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3585fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3586fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3587fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3588fcf5ef2aSThomas Huth } 3589fcf5ef2aSThomas Huth 3590fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 3591fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3592fcf5ef2aSThomas Huth { \ 3593fcf5ef2aSThomas Huth TCGv EA; \ 3594fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3595fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3596fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3597fcf5ef2aSThomas Huth return; \ 3598fcf5ef2aSThomas Huth } \ 3599fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3600fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3601fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3602fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3603fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3604fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3605fcf5ef2aSThomas Huth } 3606fcf5ef2aSThomas Huth 3607fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3608fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3609fcf5ef2aSThomas Huth { \ 3610fcf5ef2aSThomas Huth TCGv EA; \ 3611fcf5ef2aSThomas Huth chk; \ 3612fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3613fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3614fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3615fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3616fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3617fcf5ef2aSThomas Huth } 3618fcf5ef2aSThomas Huth 3619fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3620fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3621fcf5ef2aSThomas Huth 3622fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3623fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3624fcf5ef2aSThomas Huth 3625fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 3626fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 3627fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 3628fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 3629fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 3630fcf5ef2aSThomas Huth 3631fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 3632fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 3633fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 3634fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 3635fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 3636fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 3637fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 3638fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 363950728199SRoman Kapl 364050728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 364150728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 364250728199SRoman Kapl { \ 364350728199SRoman Kapl TCGv EA; \ 364450728199SRoman Kapl CHK_SV; \ 364550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 364650728199SRoman Kapl EA = tcg_temp_new(); \ 364750728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 364850728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 364950728199SRoman Kapl tcg_temp_free(EA); \ 365050728199SRoman Kapl } 365150728199SRoman Kapl 365250728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 365350728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 365450728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 365550728199SRoman Kapl #if defined(TARGET_PPC64) 365650728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 365750728199SRoman Kapl #endif 365850728199SRoman Kapl 3659fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3660fcf5ef2aSThomas Huth /* lwaux */ 3661fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 3662fcf5ef2aSThomas Huth /* lwax */ 3663fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 3664fcf5ef2aSThomas Huth /* ldux */ 3665fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 3666fcf5ef2aSThomas Huth /* ldx */ 3667fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 3668fcf5ef2aSThomas Huth 3669fcf5ef2aSThomas Huth /* CI load/store variants */ 3670fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3671fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3672fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3673fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3674fcf5ef2aSThomas Huth 3675fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 3676fcf5ef2aSThomas Huth { 3677fcf5ef2aSThomas Huth TCGv EA; 3678fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3679fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 3680fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 3681fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3682fcf5ef2aSThomas Huth return; 3683fcf5ef2aSThomas Huth } 3684fcf5ef2aSThomas Huth } 3685fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3686fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3687fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3688fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 3689fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 3690fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3691fcf5ef2aSThomas Huth } else { 3692fcf5ef2aSThomas Huth /* ld - ldu */ 3693fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3694fcf5ef2aSThomas Huth } 3695efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3696fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3697efe843d8SDavid Gibson } 3698fcf5ef2aSThomas Huth tcg_temp_free(EA); 3699fcf5ef2aSThomas Huth } 3700fcf5ef2aSThomas Huth 3701fcf5ef2aSThomas Huth /* lq */ 3702fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3703fcf5ef2aSThomas Huth { 3704fcf5ef2aSThomas Huth int ra, rd; 370594bf2658SRichard Henderson TCGv EA, hi, lo; 3706fcf5ef2aSThomas Huth 3707fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3708fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3709fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3710fcf5ef2aSThomas Huth 3711fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3712fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3713fcf5ef2aSThomas Huth return; 3714fcf5ef2aSThomas Huth } 3715fcf5ef2aSThomas Huth 3716fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3717fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3718fcf5ef2aSThomas Huth return; 3719fcf5ef2aSThomas Huth } 3720fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3721fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3722fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3723fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3724fcf5ef2aSThomas Huth return; 3725fcf5ef2aSThomas Huth } 3726fcf5ef2aSThomas Huth 3727fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3728fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3729fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3730fcf5ef2aSThomas Huth 373194bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 373294bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 373394bf2658SRichard Henderson hi = cpu_gpr[rd]; 373494bf2658SRichard Henderson 373594bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3736f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 373794bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 373894bf2658SRichard Henderson if (ctx->le_mode) { 373994bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 374094bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3741fcf5ef2aSThomas Huth } else { 374294bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 374394bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 374494bf2658SRichard Henderson } 374594bf2658SRichard Henderson tcg_temp_free_i32(oi); 374694bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3747f34ec0f6SRichard Henderson } else { 374894bf2658SRichard Henderson /* Restart with exclusive lock. */ 374994bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 375094bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3751f34ec0f6SRichard Henderson } 375294bf2658SRichard Henderson } else if (ctx->le_mode) { 375394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3754fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 375594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 375694bf2658SRichard Henderson } else { 375794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 375894bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 375994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3760fcf5ef2aSThomas Huth } 3761fcf5ef2aSThomas Huth tcg_temp_free(EA); 3762fcf5ef2aSThomas Huth } 3763fcf5ef2aSThomas Huth #endif 3764fcf5ef2aSThomas Huth 3765fcf5ef2aSThomas Huth /*** Integer store ***/ 3766fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3767fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3768fcf5ef2aSThomas Huth { \ 3769fcf5ef2aSThomas Huth TCGv EA; \ 3770fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3771fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3772fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3773fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3774fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3775fcf5ef2aSThomas Huth } 3776fcf5ef2aSThomas Huth 3777fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3778fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3779fcf5ef2aSThomas Huth { \ 3780fcf5ef2aSThomas Huth TCGv EA; \ 3781fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3782fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3783fcf5ef2aSThomas Huth return; \ 3784fcf5ef2aSThomas Huth } \ 3785fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3786fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3787fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3788fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3789fcf5ef2aSThomas Huth else \ 3790fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3791fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3792fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3793fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3794fcf5ef2aSThomas Huth } 3795fcf5ef2aSThomas Huth 3796fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3797fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3798fcf5ef2aSThomas Huth { \ 3799fcf5ef2aSThomas Huth TCGv EA; \ 3800fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3801fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3802fcf5ef2aSThomas Huth return; \ 3803fcf5ef2aSThomas Huth } \ 3804fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3805fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3806fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3807fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3808fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3809fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3810fcf5ef2aSThomas Huth } 3811fcf5ef2aSThomas Huth 3812fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3813fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3814fcf5ef2aSThomas Huth { \ 3815fcf5ef2aSThomas Huth TCGv EA; \ 3816fcf5ef2aSThomas Huth chk; \ 3817fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3818fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3819fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3820fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3821fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3822fcf5ef2aSThomas Huth } 3823fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3824fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3825fcf5ef2aSThomas Huth 3826fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3827fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3828fcf5ef2aSThomas Huth 3829fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3830fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3831fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3832fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3833fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3834fcf5ef2aSThomas Huth 3835fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3836fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3837fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3838fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3839fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3840fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 384150728199SRoman Kapl 384250728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 384350728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 384450728199SRoman Kapl { \ 384550728199SRoman Kapl TCGv EA; \ 384650728199SRoman Kapl CHK_SV; \ 384750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 384850728199SRoman Kapl EA = tcg_temp_new(); \ 384950728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 385050728199SRoman Kapl tcg_gen_qemu_st_tl( \ 385150728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 385250728199SRoman Kapl tcg_temp_free(EA); \ 385350728199SRoman Kapl } 385450728199SRoman Kapl 385550728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 385650728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 385750728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 385850728199SRoman Kapl #if defined(TARGET_PPC64) 385950728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 386050728199SRoman Kapl #endif 386150728199SRoman Kapl 3862fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3863fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3864fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3865fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3866fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3867fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3868fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3869fcf5ef2aSThomas Huth 3870fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3871fcf5ef2aSThomas Huth { 3872fcf5ef2aSThomas Huth int rs; 3873fcf5ef2aSThomas Huth TCGv EA; 3874fcf5ef2aSThomas Huth 3875fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3876fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3877fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3878fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3879f89ced5fSRichard Henderson TCGv hi, lo; 3880fcf5ef2aSThomas Huth 3881fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3882fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3883fcf5ef2aSThomas Huth } 3884fcf5ef2aSThomas Huth 3885fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3886fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3887fcf5ef2aSThomas Huth return; 3888fcf5ef2aSThomas Huth } 3889fcf5ef2aSThomas Huth 3890fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3891fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3892fcf5ef2aSThomas Huth return; 3893fcf5ef2aSThomas Huth } 3894fcf5ef2aSThomas Huth 3895fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3896fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3897fcf5ef2aSThomas Huth return; 3898fcf5ef2aSThomas Huth } 3899fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3900fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3901fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3902fcf5ef2aSThomas Huth 3903f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3904f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3905f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3906f89ced5fSRichard Henderson 3907f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3908f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3909f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3910f89ced5fSRichard Henderson if (ctx->le_mode) { 3911f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3912f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3913fcf5ef2aSThomas Huth } else { 3914f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3915f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3916f89ced5fSRichard Henderson } 3917f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3918f34ec0f6SRichard Henderson } else { 3919f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3920f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3921f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3922f34ec0f6SRichard Henderson } 3923f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3924f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3925fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3926f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3927f89ced5fSRichard Henderson } else { 3928f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3929f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3930f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3931fcf5ef2aSThomas Huth } 3932fcf5ef2aSThomas Huth tcg_temp_free(EA); 3933fcf5ef2aSThomas Huth } else { 3934fcf5ef2aSThomas Huth /* std / stdu */ 3935fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3936fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3937fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3938fcf5ef2aSThomas Huth return; 3939fcf5ef2aSThomas Huth } 3940fcf5ef2aSThomas Huth } 3941fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3942fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3943fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3944fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3945efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3946fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3947efe843d8SDavid Gibson } 3948fcf5ef2aSThomas Huth tcg_temp_free(EA); 3949fcf5ef2aSThomas Huth } 3950fcf5ef2aSThomas Huth } 3951fcf5ef2aSThomas Huth #endif 3952fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3953fcf5ef2aSThomas Huth 3954fcf5ef2aSThomas Huth /* lhbrx */ 3955fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3956fcf5ef2aSThomas Huth 3957fcf5ef2aSThomas Huth /* lwbrx */ 3958fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3959fcf5ef2aSThomas Huth 3960fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3961fcf5ef2aSThomas Huth /* ldbrx */ 3962fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3963fcf5ef2aSThomas Huth /* stdbrx */ 3964fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3965fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3966fcf5ef2aSThomas Huth 3967fcf5ef2aSThomas Huth /* sthbrx */ 3968fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3969fcf5ef2aSThomas Huth /* stwbrx */ 3970fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3971fcf5ef2aSThomas Huth 3972fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3973fcf5ef2aSThomas Huth 3974fcf5ef2aSThomas Huth /* lmw */ 3975fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3976fcf5ef2aSThomas Huth { 3977fcf5ef2aSThomas Huth TCGv t0; 3978fcf5ef2aSThomas Huth TCGv_i32 t1; 3979fcf5ef2aSThomas Huth 3980fcf5ef2aSThomas Huth if (ctx->le_mode) { 3981fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3982fcf5ef2aSThomas Huth return; 3983fcf5ef2aSThomas Huth } 3984fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3985fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3986fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3987fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3988fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3989fcf5ef2aSThomas Huth tcg_temp_free(t0); 3990fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3991fcf5ef2aSThomas Huth } 3992fcf5ef2aSThomas Huth 3993fcf5ef2aSThomas Huth /* stmw */ 3994fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3995fcf5ef2aSThomas Huth { 3996fcf5ef2aSThomas Huth TCGv t0; 3997fcf5ef2aSThomas Huth TCGv_i32 t1; 3998fcf5ef2aSThomas Huth 3999fcf5ef2aSThomas Huth if (ctx->le_mode) { 4000fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4001fcf5ef2aSThomas Huth return; 4002fcf5ef2aSThomas Huth } 4003fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4004fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4005fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 4006fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 4007fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 4008fcf5ef2aSThomas Huth tcg_temp_free(t0); 4009fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4010fcf5ef2aSThomas Huth } 4011fcf5ef2aSThomas Huth 4012fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 4013fcf5ef2aSThomas Huth 4014fcf5ef2aSThomas Huth /* lswi */ 4015efe843d8SDavid Gibson /* 4016efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 4017efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 4018efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 4019efe843d8SDavid Gibson * spec... 4020fcf5ef2aSThomas Huth */ 4021fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 4022fcf5ef2aSThomas Huth { 4023fcf5ef2aSThomas Huth TCGv t0; 4024fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4025fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4026fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 4027fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 4028fcf5ef2aSThomas Huth int nr; 4029fcf5ef2aSThomas Huth 4030fcf5ef2aSThomas Huth if (ctx->le_mode) { 4031fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4032fcf5ef2aSThomas Huth return; 4033fcf5ef2aSThomas Huth } 4034efe843d8SDavid Gibson if (nb == 0) { 4035fcf5ef2aSThomas Huth nb = 32; 4036efe843d8SDavid Gibson } 4037f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 4038fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 4039fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 4040fcf5ef2aSThomas Huth return; 4041fcf5ef2aSThomas Huth } 4042fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4043fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4044fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4045fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4046fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 4047fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 4048fcf5ef2aSThomas Huth tcg_temp_free(t0); 4049fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4050fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4051fcf5ef2aSThomas Huth } 4052fcf5ef2aSThomas Huth 4053fcf5ef2aSThomas Huth /* lswx */ 4054fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 4055fcf5ef2aSThomas Huth { 4056fcf5ef2aSThomas Huth TCGv t0; 4057fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 4058fcf5ef2aSThomas Huth 4059fcf5ef2aSThomas Huth if (ctx->le_mode) { 4060fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4061fcf5ef2aSThomas Huth return; 4062fcf5ef2aSThomas Huth } 4063fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4064fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4065fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4066fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 4067fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 4068fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 4069fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 4070fcf5ef2aSThomas Huth tcg_temp_free(t0); 4071fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4072fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4073fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4074fcf5ef2aSThomas Huth } 4075fcf5ef2aSThomas Huth 4076fcf5ef2aSThomas Huth /* stswi */ 4077fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 4078fcf5ef2aSThomas Huth { 4079fcf5ef2aSThomas Huth TCGv t0; 4080fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4081fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4082fcf5ef2aSThomas Huth 4083fcf5ef2aSThomas Huth if (ctx->le_mode) { 4084fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4085fcf5ef2aSThomas Huth return; 4086fcf5ef2aSThomas Huth } 4087fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4088fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4089fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4090efe843d8SDavid Gibson if (nb == 0) { 4091fcf5ef2aSThomas Huth nb = 32; 4092efe843d8SDavid Gibson } 4093fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4094fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4095fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4096fcf5ef2aSThomas Huth tcg_temp_free(t0); 4097fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4098fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4099fcf5ef2aSThomas Huth } 4100fcf5ef2aSThomas Huth 4101fcf5ef2aSThomas Huth /* stswx */ 4102fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 4103fcf5ef2aSThomas Huth { 4104fcf5ef2aSThomas Huth TCGv t0; 4105fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4106fcf5ef2aSThomas Huth 4107fcf5ef2aSThomas Huth if (ctx->le_mode) { 4108fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4109fcf5ef2aSThomas Huth return; 4110fcf5ef2aSThomas Huth } 4111fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4112fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4113fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4114fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4115fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 4116fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 4117fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4118fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4119fcf5ef2aSThomas Huth tcg_temp_free(t0); 4120fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4121fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4122fcf5ef2aSThomas Huth } 4123fcf5ef2aSThomas Huth 4124fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 4125fcf5ef2aSThomas Huth /* eieio */ 4126fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 4127fcf5ef2aSThomas Huth { 4128c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 4129c8fd8373SCédric Le Goater 4130c8fd8373SCédric Le Goater /* 4131c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 4132c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 4133c8fd8373SCédric Le Goater */ 4134c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 4135c8fd8373SCédric Le Goater /* 4136c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 4137c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 4138c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 4139c8fd8373SCédric Le Goater * complain to the user. 4140c8fd8373SCédric Le Goater */ 4141c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 4142c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 4143c8fd8373SCédric Le Goater TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 4144c8fd8373SCédric Le Goater } else { 4145c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 4146c8fd8373SCédric Le Goater } 4147c8fd8373SCédric Le Goater } 4148c8fd8373SCédric Le Goater 4149c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 4150fcf5ef2aSThomas Huth } 4151fcf5ef2aSThomas Huth 4152fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4153fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 4154fcf5ef2aSThomas Huth { 4155fcf5ef2aSThomas Huth TCGv_i32 t; 4156fcf5ef2aSThomas Huth TCGLabel *l; 4157fcf5ef2aSThomas Huth 4158fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 4159fcf5ef2aSThomas Huth return; 4160fcf5ef2aSThomas Huth } 4161fcf5ef2aSThomas Huth l = gen_new_label(); 4162fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 4163fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4164fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 4165fcf5ef2aSThomas Huth if (global) { 4166fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 4167fcf5ef2aSThomas Huth } else { 4168fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 4169fcf5ef2aSThomas Huth } 4170fcf5ef2aSThomas Huth gen_set_label(l); 4171fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4172fcf5ef2aSThomas Huth } 4173fcf5ef2aSThomas Huth #else 4174fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 4175fcf5ef2aSThomas Huth #endif 4176fcf5ef2aSThomas Huth 4177fcf5ef2aSThomas Huth /* isync */ 4178fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 4179fcf5ef2aSThomas Huth { 4180fcf5ef2aSThomas Huth /* 4181fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 4182fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 4183fcf5ef2aSThomas Huth */ 4184fcf5ef2aSThomas Huth if (!ctx->pr) { 4185fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 4186fcf5ef2aSThomas Huth } 41874771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4188fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4189fcf5ef2aSThomas Huth } 4190fcf5ef2aSThomas Huth 4191fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 4192fcf5ef2aSThomas Huth 419314776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 41942a4e6c1bSRichard Henderson { 41952a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 41962a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 41972a4e6c1bSRichard Henderson 41982a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 41992a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 42002a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 42012a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 42022a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 42032a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 42042a4e6c1bSRichard Henderson tcg_temp_free(t0); 42052a4e6c1bSRichard Henderson } 42062a4e6c1bSRichard Henderson 4207fcf5ef2aSThomas Huth #define LARX(name, memop) \ 4208fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4209fcf5ef2aSThomas Huth { \ 42102a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 4211fcf5ef2aSThomas Huth } 4212fcf5ef2aSThomas Huth 4213fcf5ef2aSThomas Huth /* lwarx */ 4214fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 4215fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 4216fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 4217fcf5ef2aSThomas Huth 421814776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 421920923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 422020923c1dSRichard Henderson { 422120923c1dSRichard Henderson TCGv t = tcg_temp_new(); 422220923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 422320923c1dSRichard Henderson TCGv u = tcg_temp_new(); 422420923c1dSRichard Henderson 422520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 422620923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 422720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 422820923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 422920923c1dSRichard Henderson 423020923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 423120923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 423220923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 423320923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 423420923c1dSRichard Henderson 423520923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 423620923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 423720923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 423820923c1dSRichard Henderson 423920923c1dSRichard Henderson tcg_temp_free(t); 424020923c1dSRichard Henderson tcg_temp_free(t2); 424120923c1dSRichard Henderson tcg_temp_free(u); 424220923c1dSRichard Henderson } 424320923c1dSRichard Henderson 424414776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 424520ba8504SRichard Henderson { 424620ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 424720ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 424820923c1dSRichard Henderson int rt = rD(ctx->opcode); 424920923c1dSRichard Henderson bool need_serial; 425020ba8504SRichard Henderson TCGv src, dst; 425120ba8504SRichard Henderson 425220ba8504SRichard Henderson gen_addr_register(ctx, EA); 425320923c1dSRichard Henderson dst = cpu_gpr[rt]; 425420923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 425520ba8504SRichard Henderson 425620923c1dSRichard Henderson need_serial = false; 425720ba8504SRichard Henderson memop |= MO_ALIGN; 425820ba8504SRichard Henderson switch (gpr_FC) { 425920ba8504SRichard Henderson case 0: /* Fetch and add */ 426020ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 426120ba8504SRichard Henderson break; 426220ba8504SRichard Henderson case 1: /* Fetch and xor */ 426320ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 426420ba8504SRichard Henderson break; 426520ba8504SRichard Henderson case 2: /* Fetch and or */ 426620ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 426720ba8504SRichard Henderson break; 426820ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 426920ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 427020ba8504SRichard Henderson break; 4271b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 4272b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 4273b8ce0f86SRichard Henderson break; 4274b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 4275b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 4276b8ce0f86SRichard Henderson break; 4277b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 4278b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 4279b8ce0f86SRichard Henderson break; 4280b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 4281b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 4282b8ce0f86SRichard Henderson break; 428320ba8504SRichard Henderson case 8: /* Swap */ 428420ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 428520ba8504SRichard Henderson break; 428620923c1dSRichard Henderson 428720923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 428820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 428920923c1dSRichard Henderson need_serial = true; 429020923c1dSRichard Henderson } else { 429120923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 429220923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 429320923c1dSRichard Henderson 429420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 429520923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 429620923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 429720923c1dSRichard Henderson } else { 429820923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 429920923c1dSRichard Henderson } 430020923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 430120923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 430220923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 430320923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 430420923c1dSRichard Henderson 430520923c1dSRichard Henderson tcg_temp_free(t0); 430620923c1dSRichard Henderson tcg_temp_free(t1); 430720923c1dSRichard Henderson } 430820ba8504SRichard Henderson break; 430920923c1dSRichard Henderson 431020923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 431120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 431220923c1dSRichard Henderson need_serial = true; 431320923c1dSRichard Henderson } else { 431420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 431520923c1dSRichard Henderson } 431620923c1dSRichard Henderson break; 431720923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 431820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 431920923c1dSRichard Henderson need_serial = true; 432020923c1dSRichard Henderson } else { 432120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 432220923c1dSRichard Henderson } 432320923c1dSRichard Henderson break; 432420923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 432520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 432620923c1dSRichard Henderson need_serial = true; 432720923c1dSRichard Henderson } else { 432820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 432920923c1dSRichard Henderson } 433020923c1dSRichard Henderson break; 433120923c1dSRichard Henderson 433220ba8504SRichard Henderson default: 433320ba8504SRichard Henderson /* invoke data storage error handler */ 433420ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 433520ba8504SRichard Henderson } 433620ba8504SRichard Henderson tcg_temp_free(EA); 433720923c1dSRichard Henderson 433820923c1dSRichard Henderson if (need_serial) { 433920923c1dSRichard Henderson /* Restart with exclusive lock. */ 434020923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 434120923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 434220923c1dSRichard Henderson } 4343a68a6146SBalamuruhan S } 4344a68a6146SBalamuruhan S 434520ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 434620ba8504SRichard Henderson { 434720ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 434820ba8504SRichard Henderson } 434920ba8504SRichard Henderson 435020ba8504SRichard Henderson #ifdef TARGET_PPC64 435120ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 435220ba8504SRichard Henderson { 435320ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 435420ba8504SRichard Henderson } 4355a68a6146SBalamuruhan S #endif 4356a68a6146SBalamuruhan S 435714776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 43589deb041cSRichard Henderson { 43599deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 43609deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 43619deb041cSRichard Henderson TCGv src, discard; 43629deb041cSRichard Henderson 43639deb041cSRichard Henderson gen_addr_register(ctx, EA); 43649deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 43659deb041cSRichard Henderson discard = tcg_temp_new(); 43669deb041cSRichard Henderson 43679deb041cSRichard Henderson memop |= MO_ALIGN; 43689deb041cSRichard Henderson switch (gpr_FC) { 43699deb041cSRichard Henderson case 0: /* add and Store */ 43709deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43719deb041cSRichard Henderson break; 43729deb041cSRichard Henderson case 1: /* xor and Store */ 43739deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43749deb041cSRichard Henderson break; 43759deb041cSRichard Henderson case 2: /* Or and Store */ 43769deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43779deb041cSRichard Henderson break; 43789deb041cSRichard Henderson case 3: /* 'and' and Store */ 43799deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43809deb041cSRichard Henderson break; 43819deb041cSRichard Henderson case 4: /* Store max unsigned */ 4382b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4383b8ce0f86SRichard Henderson break; 43849deb041cSRichard Henderson case 5: /* Store max signed */ 4385b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4386b8ce0f86SRichard Henderson break; 43879deb041cSRichard Henderson case 6: /* Store min unsigned */ 4388b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4389b8ce0f86SRichard Henderson break; 43909deb041cSRichard Henderson case 7: /* Store min signed */ 4391b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4392b8ce0f86SRichard Henderson break; 43939deb041cSRichard Henderson case 24: /* Store twin */ 43947fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 43957fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 43967fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 43977fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 43987fbc2b20SRichard Henderson } else { 43997fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 44007fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 44017fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 44027fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 44037fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 44047fbc2b20SRichard Henderson 44057fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 44067fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 44077fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 44087fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 44097fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 44107fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 44117fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 44127fbc2b20SRichard Henderson 44137fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 44147fbc2b20SRichard Henderson tcg_temp_free(s2); 44157fbc2b20SRichard Henderson tcg_temp_free(s); 44167fbc2b20SRichard Henderson tcg_temp_free(t2); 44177fbc2b20SRichard Henderson tcg_temp_free(t); 44187fbc2b20SRichard Henderson } 44199deb041cSRichard Henderson break; 44209deb041cSRichard Henderson default: 44219deb041cSRichard Henderson /* invoke data storage error handler */ 44229deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 44239deb041cSRichard Henderson } 44249deb041cSRichard Henderson tcg_temp_free(discard); 44259deb041cSRichard Henderson tcg_temp_free(EA); 4426a3401188SBalamuruhan S } 4427a3401188SBalamuruhan S 44289deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 44299deb041cSRichard Henderson { 44309deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 44319deb041cSRichard Henderson } 44329deb041cSRichard Henderson 44339deb041cSRichard Henderson #ifdef TARGET_PPC64 44349deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 44359deb041cSRichard Henderson { 44369deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 44379deb041cSRichard Henderson } 4438a3401188SBalamuruhan S #endif 4439a3401188SBalamuruhan S 444014776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4441fcf5ef2aSThomas Huth { 4442253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4443253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4444d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4445d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4446fcf5ef2aSThomas Huth 4447d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4448d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4449d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4450d8b86898SRichard Henderson tcg_temp_free(t0); 4451253ce7b2SNikunj A Dadhania 4452253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4453253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4454253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4455253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4456253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4457253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4458253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4459253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4460253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4461253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4462253ce7b2SNikunj A Dadhania 4463fcf5ef2aSThomas Huth gen_set_label(l1); 44644771df23SNikunj A Dadhania 4465efe843d8SDavid Gibson /* 4466efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4467efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4468efe843d8SDavid Gibson */ 44694771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4470253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4471253ce7b2SNikunj A Dadhania 4472253ce7b2SNikunj A Dadhania gen_set_label(l2); 4473fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4474fcf5ef2aSThomas Huth } 4475fcf5ef2aSThomas Huth 4476fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4477fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4478fcf5ef2aSThomas Huth { \ 4479d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4480fcf5ef2aSThomas Huth } 4481fcf5ef2aSThomas Huth 4482fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4483fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4484fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4485fcf5ef2aSThomas Huth 4486fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4487fcf5ef2aSThomas Huth /* ldarx */ 4488fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4489fcf5ef2aSThomas Huth /* stdcx. */ 4490fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4491fcf5ef2aSThomas Huth 4492fcf5ef2aSThomas Huth /* lqarx */ 4493fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4494fcf5ef2aSThomas Huth { 4495fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 449694bf2658SRichard Henderson TCGv EA, hi, lo; 4497fcf5ef2aSThomas Huth 4498fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4499fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4500fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4501fcf5ef2aSThomas Huth return; 4502fcf5ef2aSThomas Huth } 4503fcf5ef2aSThomas Huth 4504fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 450594bf2658SRichard Henderson EA = tcg_temp_new(); 4506fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 450794bf2658SRichard Henderson 450894bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 450994bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 451094bf2658SRichard Henderson hi = cpu_gpr[rd]; 451194bf2658SRichard Henderson 451294bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4513f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 451494bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 451594bf2658SRichard Henderson if (ctx->le_mode) { 451694bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 451794bf2658SRichard Henderson ctx->mem_idx)); 451894bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4519fcf5ef2aSThomas Huth } else { 452094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 452194bf2658SRichard Henderson ctx->mem_idx)); 452294bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4523fcf5ef2aSThomas Huth } 452494bf2658SRichard Henderson tcg_temp_free_i32(oi); 452594bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4526f34ec0f6SRichard Henderson } else { 452794bf2658SRichard Henderson /* Restart with exclusive lock. */ 452894bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 452994bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 453094bf2658SRichard Henderson tcg_temp_free(EA); 453194bf2658SRichard Henderson return; 4532f34ec0f6SRichard Henderson } 453394bf2658SRichard Henderson } else if (ctx->le_mode) { 453494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4535fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4536fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 453794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 453894bf2658SRichard Henderson } else { 453994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 454094bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 454194bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 454294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 454394bf2658SRichard Henderson } 4544fcf5ef2aSThomas Huth tcg_temp_free(EA); 454594bf2658SRichard Henderson 454694bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 454794bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4548fcf5ef2aSThomas Huth } 4549fcf5ef2aSThomas Huth 4550fcf5ef2aSThomas Huth /* stqcx. */ 4551fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4552fcf5ef2aSThomas Huth { 45534a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 45544a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4555fcf5ef2aSThomas Huth 45564a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4557fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4558fcf5ef2aSThomas Huth return; 4559fcf5ef2aSThomas Huth } 45604a9b3c5dSRichard Henderson 4561fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 45624a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4563fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4564fcf5ef2aSThomas Huth 45654a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 45664a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 45674a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4568fcf5ef2aSThomas Huth 45694a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4570f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 45714a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 45724a9b3c5dSRichard Henderson if (ctx->le_mode) { 4573f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4574f34ec0f6SRichard Henderson EA, lo, hi, oi); 4575fcf5ef2aSThomas Huth } else { 4576f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4577f34ec0f6SRichard Henderson EA, lo, hi, oi); 4578fcf5ef2aSThomas Huth } 4579f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4580f34ec0f6SRichard Henderson } else { 45814a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 45824a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 45834a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4584f34ec0f6SRichard Henderson } 4585fcf5ef2aSThomas Huth tcg_temp_free(EA); 45864a9b3c5dSRichard Henderson } else { 45874a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 45884a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 45894a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 45904a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4591fcf5ef2aSThomas Huth 45924a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 45934a9b3c5dSRichard Henderson tcg_temp_free(EA); 45944a9b3c5dSRichard Henderson 45954a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 45964a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 45974a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 45984a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 45994a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 46004a9b3c5dSRichard Henderson 46014a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 46024a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 46034a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 46044a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 46054a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 46064a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 46074a9b3c5dSRichard Henderson 46084a9b3c5dSRichard Henderson /* Success */ 46094a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 46104a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 46114a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 46124a9b3c5dSRichard Henderson 46134a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46144a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 46154a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 46164a9b3c5dSRichard Henderson 46174a9b3c5dSRichard Henderson gen_set_label(lab_fail); 46184a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46194a9b3c5dSRichard Henderson 46204a9b3c5dSRichard Henderson gen_set_label(lab_over); 46214a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 46224a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 46234a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 46244a9b3c5dSRichard Henderson } 46254a9b3c5dSRichard Henderson } 4626fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4627fcf5ef2aSThomas Huth 4628fcf5ef2aSThomas Huth /* sync */ 4629fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4630fcf5ef2aSThomas Huth { 4631fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4632fcf5ef2aSThomas Huth 4633fcf5ef2aSThomas Huth /* 4634fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4635fcf5ef2aSThomas Huth * 4636fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4637fcf5ef2aSThomas Huth * 4638fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4639fcf5ef2aSThomas Huth * check MSR_PR as well. 4640fcf5ef2aSThomas Huth */ 4641fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4642fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4643fcf5ef2aSThomas Huth } 46444771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4645fcf5ef2aSThomas Huth } 4646fcf5ef2aSThomas Huth 4647fcf5ef2aSThomas Huth /* wait */ 4648fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4649fcf5ef2aSThomas Huth { 4650fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4651fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4652fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4653fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4654fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4655b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4656fcf5ef2aSThomas Huth } 4657fcf5ef2aSThomas Huth 4658fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4659fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4660fcf5ef2aSThomas Huth { 4661fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4662fcf5ef2aSThomas Huth GEN_PRIV; 4663fcf5ef2aSThomas Huth #else 4664fcf5ef2aSThomas Huth TCGv_i32 t; 4665fcf5ef2aSThomas Huth 4666fcf5ef2aSThomas Huth CHK_HV; 4667fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4668fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4669fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4670154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4671154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4672fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4673fcf5ef2aSThomas Huth } 4674fcf5ef2aSThomas Huth 4675fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4676fcf5ef2aSThomas Huth { 4677fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4678fcf5ef2aSThomas Huth GEN_PRIV; 4679fcf5ef2aSThomas Huth #else 4680fcf5ef2aSThomas Huth TCGv_i32 t; 4681fcf5ef2aSThomas Huth 4682fcf5ef2aSThomas Huth CHK_HV; 4683fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4684fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4685fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4686154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4687154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4688fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4689fcf5ef2aSThomas Huth } 4690fcf5ef2aSThomas Huth 4691cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4692cdee0e72SNikunj A Dadhania { 469321c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 469421c0d66aSBenjamin Herrenschmidt GEN_PRIV; 469521c0d66aSBenjamin Herrenschmidt #else 469621c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 469721c0d66aSBenjamin Herrenschmidt 469821c0d66aSBenjamin Herrenschmidt CHK_HV; 469921c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 470021c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 470121c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 470221c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 470321c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 470421c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4705cdee0e72SNikunj A Dadhania } 4706cdee0e72SNikunj A Dadhania 4707fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4708fcf5ef2aSThomas Huth { 4709fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4710fcf5ef2aSThomas Huth GEN_PRIV; 4711fcf5ef2aSThomas Huth #else 4712fcf5ef2aSThomas Huth TCGv_i32 t; 4713fcf5ef2aSThomas Huth 4714fcf5ef2aSThomas Huth CHK_HV; 4715fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4716fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4717fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4718154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4719154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4720fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4721fcf5ef2aSThomas Huth } 4722fcf5ef2aSThomas Huth 4723fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4724fcf5ef2aSThomas Huth { 4725fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4726fcf5ef2aSThomas Huth GEN_PRIV; 4727fcf5ef2aSThomas Huth #else 4728fcf5ef2aSThomas Huth TCGv_i32 t; 4729fcf5ef2aSThomas Huth 4730fcf5ef2aSThomas Huth CHK_HV; 4731fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4732fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4733fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4734154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4735154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4736fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4737fcf5ef2aSThomas Huth } 4738fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4739fcf5ef2aSThomas Huth 4740fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4741fcf5ef2aSThomas Huth { 4742fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4743efe843d8SDavid Gibson if (ctx->has_cfar) { 4744fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4745efe843d8SDavid Gibson } 4746fcf5ef2aSThomas Huth #endif 4747fcf5ef2aSThomas Huth } 4748fcf5ef2aSThomas Huth 4749fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4750fcf5ef2aSThomas Huth { 4751fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4752fcf5ef2aSThomas Huth return false; 4753fcf5ef2aSThomas Huth } 4754fcf5ef2aSThomas Huth 4755fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4756b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4757fcf5ef2aSThomas Huth #else 4758fcf5ef2aSThomas Huth return true; 4759fcf5ef2aSThomas Huth #endif 4760fcf5ef2aSThomas Huth } 4761fcf5ef2aSThomas Huth 47620e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 47630e3bf489SRoman Kapl { 47640e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 47650e3bf489SRoman Kapl if (unlikely(sse)) { 47660e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 47670e3bf489SRoman Kapl gen_debug_exception(ctx); 47680e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4769e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 47700e3bf489SRoman Kapl gen_exception(ctx, excp); 47710e3bf489SRoman Kapl } 47720e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 47730e3bf489SRoman Kapl } else { 47740e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 47750e3bf489SRoman Kapl } 47760e3bf489SRoman Kapl } 47770e3bf489SRoman Kapl 4778fcf5ef2aSThomas Huth /*** Branch ***/ 4779c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4780fcf5ef2aSThomas Huth { 4781fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4782fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4783fcf5ef2aSThomas Huth } 4784fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4785fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4786fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 478707ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4788fcf5ef2aSThomas Huth } else { 4789fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 47900e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4791fcf5ef2aSThomas Huth } 4792fcf5ef2aSThomas Huth } 4793fcf5ef2aSThomas Huth 4794fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4795fcf5ef2aSThomas Huth { 4796fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4797fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4798fcf5ef2aSThomas Huth } 4799fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4800fcf5ef2aSThomas Huth } 4801fcf5ef2aSThomas Huth 4802fcf5ef2aSThomas Huth /* b ba bl bla */ 4803fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4804fcf5ef2aSThomas Huth { 4805fcf5ef2aSThomas Huth target_ulong li, target; 4806fcf5ef2aSThomas Huth 4807fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 4808fcf5ef2aSThomas Huth /* sign extend LI */ 4809fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4810fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4811fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 4812b6bac4bcSEmilio G. Cota target = ctx->base.pc_next + li - 4; 4813fcf5ef2aSThomas Huth } else { 4814fcf5ef2aSThomas Huth target = li; 4815fcf5ef2aSThomas Huth } 4816fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4817b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4818fcf5ef2aSThomas Huth } 4819b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 4820fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 4821fcf5ef2aSThomas Huth } 4822fcf5ef2aSThomas Huth 4823fcf5ef2aSThomas Huth #define BCOND_IM 0 4824fcf5ef2aSThomas Huth #define BCOND_LR 1 4825fcf5ef2aSThomas Huth #define BCOND_CTR 2 4826fcf5ef2aSThomas Huth #define BCOND_TAR 3 4827fcf5ef2aSThomas Huth 4828c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4829fcf5ef2aSThomas Huth { 4830fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4831fcf5ef2aSThomas Huth TCGLabel *l1; 4832fcf5ef2aSThomas Huth TCGv target; 4833fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 48340e3bf489SRoman Kapl 4835fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4836fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4837efe843d8SDavid Gibson if (type == BCOND_CTR) { 4838fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4839efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4840fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4841efe843d8SDavid Gibson } else { 4842fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4843efe843d8SDavid Gibson } 4844fcf5ef2aSThomas Huth } else { 4845f764718dSRichard Henderson target = NULL; 4846fcf5ef2aSThomas Huth } 4847efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4848b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4849efe843d8SDavid Gibson } 4850fcf5ef2aSThomas Huth l1 = gen_new_label(); 4851fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4852fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4853fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4854fa200c95SGreg Kurz 4855fa200c95SGreg Kurz if (type == BCOND_CTR) { 4856fa200c95SGreg Kurz /* 4857fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4858fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4859fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 486015d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 486115d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 486215d68c5eSGreg Kurz * it basically useless and thus never used in real code. 486315d68c5eSGreg Kurz * 486415d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 486515d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 486615d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 486715d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 486815d68c5eSGreg Kurz * doing anything else harmful. 4869fa200c95SGreg Kurz */ 4870d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4871fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 48729acc95cdSGreg Kurz tcg_temp_free(temp); 48739acc95cdSGreg Kurz tcg_temp_free(target); 4874fcf5ef2aSThomas Huth return; 4875fcf5ef2aSThomas Huth } 4876fa200c95SGreg Kurz 4877fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4878fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4879fa200c95SGreg Kurz } else { 4880fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4881fa200c95SGreg Kurz } 4882fa200c95SGreg Kurz if (bo & 0x2) { 4883fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4884fa200c95SGreg Kurz } else { 4885fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4886fa200c95SGreg Kurz } 4887fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4888fa200c95SGreg Kurz } else { 4889fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4890fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4891fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4892fcf5ef2aSThomas Huth } else { 4893fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4894fcf5ef2aSThomas Huth } 4895fcf5ef2aSThomas Huth if (bo & 0x2) { 4896fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4897fcf5ef2aSThomas Huth } else { 4898fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4899fcf5ef2aSThomas Huth } 4900fa200c95SGreg Kurz } 4901fcf5ef2aSThomas Huth tcg_temp_free(temp); 4902fcf5ef2aSThomas Huth } 4903fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4904fcf5ef2aSThomas Huth /* Test CR */ 4905fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4906fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4907fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4908fcf5ef2aSThomas Huth 4909fcf5ef2aSThomas Huth if (bo & 0x8) { 4910fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4911fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4912fcf5ef2aSThomas Huth } else { 4913fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4914fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4915fcf5ef2aSThomas Huth } 4916fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4917fcf5ef2aSThomas Huth } 4918b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 4919fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4920fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4921fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 4922b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 4923fcf5ef2aSThomas Huth } else { 4924fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4925fcf5ef2aSThomas Huth } 4926fcf5ef2aSThomas Huth } else { 4927fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4928fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4929fcf5ef2aSThomas Huth } else { 4930fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4931fcf5ef2aSThomas Huth } 49320e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4933c4a2e3a9SRichard Henderson tcg_temp_free(target); 4934c4a2e3a9SRichard Henderson } 4935fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 49360e3bf489SRoman Kapl /* fallthrough case */ 4937fcf5ef2aSThomas Huth gen_set_label(l1); 4938b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4939fcf5ef2aSThomas Huth } 4940fcf5ef2aSThomas Huth } 4941fcf5ef2aSThomas Huth 4942fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4943fcf5ef2aSThomas Huth { 4944fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4945fcf5ef2aSThomas Huth } 4946fcf5ef2aSThomas Huth 4947fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4948fcf5ef2aSThomas Huth { 4949fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4950fcf5ef2aSThomas Huth } 4951fcf5ef2aSThomas Huth 4952fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4953fcf5ef2aSThomas Huth { 4954fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4955fcf5ef2aSThomas Huth } 4956fcf5ef2aSThomas Huth 4957fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4958fcf5ef2aSThomas Huth { 4959fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4960fcf5ef2aSThomas Huth } 4961fcf5ef2aSThomas Huth 4962fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4963fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4964fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4965fcf5ef2aSThomas Huth { \ 4966fcf5ef2aSThomas Huth uint8_t bitmask; \ 4967fcf5ef2aSThomas Huth int sh; \ 4968fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4969fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4970fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4971fcf5ef2aSThomas Huth if (sh > 0) \ 4972fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4973fcf5ef2aSThomas Huth else if (sh < 0) \ 4974fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4975fcf5ef2aSThomas Huth else \ 4976fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4977fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4978fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4979fcf5ef2aSThomas Huth if (sh > 0) \ 4980fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4981fcf5ef2aSThomas Huth else if (sh < 0) \ 4982fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4983fcf5ef2aSThomas Huth else \ 4984fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4985fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4986fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4987fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4988fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4989fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4990fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4991fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4992fcf5ef2aSThomas Huth } 4993fcf5ef2aSThomas Huth 4994fcf5ef2aSThomas Huth /* crand */ 4995fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4996fcf5ef2aSThomas Huth /* crandc */ 4997fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4998fcf5ef2aSThomas Huth /* creqv */ 4999fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 5000fcf5ef2aSThomas Huth /* crnand */ 5001fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 5002fcf5ef2aSThomas Huth /* crnor */ 5003fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 5004fcf5ef2aSThomas Huth /* cror */ 5005fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 5006fcf5ef2aSThomas Huth /* crorc */ 5007fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 5008fcf5ef2aSThomas Huth /* crxor */ 5009fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 5010fcf5ef2aSThomas Huth 5011fcf5ef2aSThomas Huth /* mcrf */ 5012fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 5013fcf5ef2aSThomas Huth { 5014fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 5015fcf5ef2aSThomas Huth } 5016fcf5ef2aSThomas Huth 5017fcf5ef2aSThomas Huth /*** System linkage ***/ 5018fcf5ef2aSThomas Huth 5019fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 5020fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 5021fcf5ef2aSThomas Huth { 5022fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5023fcf5ef2aSThomas Huth GEN_PRIV; 5024fcf5ef2aSThomas Huth #else 5025efe843d8SDavid Gibson /* 5026efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 5027fcf5ef2aSThomas Huth * processors compliant with arch 2.x 5028fcf5ef2aSThomas Huth */ 5029d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 5030fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5031fcf5ef2aSThomas Huth return; 5032fcf5ef2aSThomas Huth } 5033fcf5ef2aSThomas Huth /* Restore CPU state */ 5034fcf5ef2aSThomas Huth CHK_SV; 5035a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5036a59d628fSMaria Klimushenkova gen_io_start(); 5037a59d628fSMaria Klimushenkova } 5038b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 5039fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 5040fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5041fcf5ef2aSThomas Huth #endif 5042fcf5ef2aSThomas Huth } 5043fcf5ef2aSThomas Huth 5044fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5045fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 5046fcf5ef2aSThomas Huth { 5047fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5048fcf5ef2aSThomas Huth GEN_PRIV; 5049fcf5ef2aSThomas Huth #else 5050fcf5ef2aSThomas Huth /* Restore CPU state */ 5051fcf5ef2aSThomas Huth CHK_SV; 5052a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5053a59d628fSMaria Klimushenkova gen_io_start(); 5054a59d628fSMaria Klimushenkova } 5055b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 5056fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 5057fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5058fcf5ef2aSThomas Huth #endif 5059fcf5ef2aSThomas Huth } 5060fcf5ef2aSThomas Huth 50613c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 50623c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 50633c89b8d6SNicholas Piggin { 50643c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 50653c89b8d6SNicholas Piggin GEN_PRIV; 50663c89b8d6SNicholas Piggin #else 50673c89b8d6SNicholas Piggin /* Restore CPU state */ 50683c89b8d6SNicholas Piggin CHK_SV; 50693c89b8d6SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 50703c89b8d6SNicholas Piggin gen_io_start(); 50713c89b8d6SNicholas Piggin } 50723c89b8d6SNicholas Piggin gen_update_cfar(ctx, ctx->base.pc_next - 4); 50733c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 50743c89b8d6SNicholas Piggin gen_sync_exception(ctx); 50753c89b8d6SNicholas Piggin #endif 50763c89b8d6SNicholas Piggin } 50773c89b8d6SNicholas Piggin #endif 50783c89b8d6SNicholas Piggin 5079fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 5080fcf5ef2aSThomas Huth { 5081fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5082fcf5ef2aSThomas Huth GEN_PRIV; 5083fcf5ef2aSThomas Huth #else 5084fcf5ef2aSThomas Huth /* Restore CPU state */ 5085fcf5ef2aSThomas Huth CHK_HV; 5086fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 5087fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5088fcf5ef2aSThomas Huth #endif 5089fcf5ef2aSThomas Huth } 5090fcf5ef2aSThomas Huth #endif 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth /* sc */ 5093fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5094fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 5095fcf5ef2aSThomas Huth #else 5096fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 50973c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 5098fcf5ef2aSThomas Huth #endif 5099fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 5100fcf5ef2aSThomas Huth { 5101fcf5ef2aSThomas Huth uint32_t lev; 5102fcf5ef2aSThomas Huth 5103fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 5104fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 5105fcf5ef2aSThomas Huth } 5106fcf5ef2aSThomas Huth 51073c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 51083c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 51093c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 51103c89b8d6SNicholas Piggin { 5111f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 51123c89b8d6SNicholas Piggin 5113f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 5114f43520e5SRichard Henderson if (ctx->exception == POWERPC_EXCP_NONE) { 5115f43520e5SRichard Henderson gen_update_nip(ctx, ctx->base.pc_next - 4); 51163c89b8d6SNicholas Piggin } 5117f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 51183c89b8d6SNicholas Piggin 5119f43520e5SRichard Henderson /* This need not be exact, just not POWERPC_EXCP_NONE */ 5120f43520e5SRichard Henderson ctx->exception = POWERPC_SYSCALL_VECTORED; 51213c89b8d6SNicholas Piggin } 51223c89b8d6SNicholas Piggin #endif 51233c89b8d6SNicholas Piggin #endif 51243c89b8d6SNicholas Piggin 5125fcf5ef2aSThomas Huth /*** Trap ***/ 5126fcf5ef2aSThomas Huth 5127fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 5128fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 5129fcf5ef2aSThomas Huth { 5130fcf5ef2aSThomas Huth /* Trap never */ 5131fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 5132fcf5ef2aSThomas Huth return true; 5133fcf5ef2aSThomas Huth } 5134fcf5ef2aSThomas Huth /* Trap always */ 5135fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 5136fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 5137fcf5ef2aSThomas Huth return true; 5138fcf5ef2aSThomas Huth } 5139fcf5ef2aSThomas Huth return false; 5140fcf5ef2aSThomas Huth } 5141fcf5ef2aSThomas Huth 5142fcf5ef2aSThomas Huth /* tw */ 5143fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 5144fcf5ef2aSThomas Huth { 5145fcf5ef2aSThomas Huth TCGv_i32 t0; 5146fcf5ef2aSThomas Huth 5147fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5148fcf5ef2aSThomas Huth return; 5149fcf5ef2aSThomas Huth } 5150fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5151fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5152fcf5ef2aSThomas Huth t0); 5153fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5154fcf5ef2aSThomas Huth } 5155fcf5ef2aSThomas Huth 5156fcf5ef2aSThomas Huth /* twi */ 5157fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 5158fcf5ef2aSThomas Huth { 5159fcf5ef2aSThomas Huth TCGv t0; 5160fcf5ef2aSThomas Huth TCGv_i32 t1; 5161fcf5ef2aSThomas Huth 5162fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5163fcf5ef2aSThomas Huth return; 5164fcf5ef2aSThomas Huth } 5165fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5166fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5167fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5168fcf5ef2aSThomas Huth tcg_temp_free(t0); 5169fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5170fcf5ef2aSThomas Huth } 5171fcf5ef2aSThomas Huth 5172fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5173fcf5ef2aSThomas Huth /* td */ 5174fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 5175fcf5ef2aSThomas Huth { 5176fcf5ef2aSThomas Huth TCGv_i32 t0; 5177fcf5ef2aSThomas Huth 5178fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5179fcf5ef2aSThomas Huth return; 5180fcf5ef2aSThomas Huth } 5181fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5182fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5183fcf5ef2aSThomas Huth t0); 5184fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5185fcf5ef2aSThomas Huth } 5186fcf5ef2aSThomas Huth 5187fcf5ef2aSThomas Huth /* tdi */ 5188fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 5189fcf5ef2aSThomas Huth { 5190fcf5ef2aSThomas Huth TCGv t0; 5191fcf5ef2aSThomas Huth TCGv_i32 t1; 5192fcf5ef2aSThomas Huth 5193fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5194fcf5ef2aSThomas Huth return; 5195fcf5ef2aSThomas Huth } 5196fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5197fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5198fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5199fcf5ef2aSThomas Huth tcg_temp_free(t0); 5200fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5201fcf5ef2aSThomas Huth } 5202fcf5ef2aSThomas Huth #endif 5203fcf5ef2aSThomas Huth 5204fcf5ef2aSThomas Huth /*** Processor control ***/ 5205fcf5ef2aSThomas Huth 5206fcf5ef2aSThomas Huth /* mcrxr */ 5207fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 5208fcf5ef2aSThomas Huth { 5209fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5210fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 5211fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5212fcf5ef2aSThomas Huth 5213fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 5214fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 5215fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 5216fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 5217fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 5218fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 5219fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 5220fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 5221fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5222fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5223fcf5ef2aSThomas Huth 5224fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 5225fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5226fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5227fcf5ef2aSThomas Huth } 5228fcf5ef2aSThomas Huth 5229b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 5230b63d0434SNikunj A Dadhania /* mcrxrx */ 5231b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 5232b63d0434SNikunj A Dadhania { 5233b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 5234b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 5235b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5236b63d0434SNikunj A Dadhania 5237b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 5238b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 5239b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 5240b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 5241b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 5242b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 5243b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 5244b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 5245b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 5246b63d0434SNikunj A Dadhania tcg_temp_free(t0); 5247b63d0434SNikunj A Dadhania tcg_temp_free(t1); 5248b63d0434SNikunj A Dadhania } 5249b63d0434SNikunj A Dadhania #endif 5250b63d0434SNikunj A Dadhania 5251fcf5ef2aSThomas Huth /* mfcr mfocrf */ 5252fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 5253fcf5ef2aSThomas Huth { 5254fcf5ef2aSThomas Huth uint32_t crm, crn; 5255fcf5ef2aSThomas Huth 5256fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 5257fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5258fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 5259fcf5ef2aSThomas Huth crn = ctz32(crm); 5260fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 5261fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 5262fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 5263fcf5ef2aSThomas Huth } 5264fcf5ef2aSThomas Huth } else { 5265fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5266fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 5267fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5268fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 5269fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5270fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 5271fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5272fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 5273fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5274fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 5275fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5276fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 5277fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5278fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 5279fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5280fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 5281fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5282fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5283fcf5ef2aSThomas Huth } 5284fcf5ef2aSThomas Huth } 5285fcf5ef2aSThomas Huth 5286fcf5ef2aSThomas Huth /* mfmsr */ 5287fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 5288fcf5ef2aSThomas Huth { 5289fcf5ef2aSThomas Huth CHK_SV; 5290fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 5291fcf5ef2aSThomas Huth } 5292fcf5ef2aSThomas Huth 5293fcf5ef2aSThomas Huth /* mfspr */ 5294fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 5295fcf5ef2aSThomas Huth { 5296fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 5297fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5298fcf5ef2aSThomas Huth 5299fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5300fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5301fcf5ef2aSThomas Huth #else 5302fcf5ef2aSThomas Huth if (ctx->pr) { 5303fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5304fcf5ef2aSThomas Huth } else if (ctx->hv) { 5305fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 5306fcf5ef2aSThomas Huth } else { 5307fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 5308fcf5ef2aSThomas Huth } 5309fcf5ef2aSThomas Huth #endif 5310fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 5311fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 5312fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 5313fcf5ef2aSThomas Huth } else { 5314fcf5ef2aSThomas Huth /* Privilege exception */ 5315efe843d8SDavid Gibson /* 5316efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 5317fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 5318fcf5ef2aSThomas Huth * allowing userland application to read the PVR 5319fcf5ef2aSThomas Huth */ 5320fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 532131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 532231085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 5323b6bac4bcSEmilio G. Cota ctx->base.pc_next - 4); 5324fcf5ef2aSThomas Huth } 5325fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5326fcf5ef2aSThomas Huth } 5327fcf5ef2aSThomas Huth } else { 5328fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5329fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5330fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5331fcf5ef2aSThomas Huth /* This is a nop */ 5332fcf5ef2aSThomas Huth return; 5333fcf5ef2aSThomas Huth } 5334fcf5ef2aSThomas Huth /* Not defined */ 533531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 533631085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 5337b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 5338fcf5ef2aSThomas Huth 5339efe843d8SDavid Gibson /* 5340efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5341efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5342fcf5ef2aSThomas Huth */ 5343fcf5ef2aSThomas Huth if (sprn & 0x10) { 5344fcf5ef2aSThomas Huth if (ctx->pr) { 5345fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5346fcf5ef2aSThomas Huth } 5347fcf5ef2aSThomas Huth } else { 5348fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5349fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5350fcf5ef2aSThomas Huth } 5351fcf5ef2aSThomas Huth } 5352fcf5ef2aSThomas Huth } 5353fcf5ef2aSThomas Huth } 5354fcf5ef2aSThomas Huth 5355fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5356fcf5ef2aSThomas Huth { 5357fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5358fcf5ef2aSThomas Huth } 5359fcf5ef2aSThomas Huth 5360fcf5ef2aSThomas Huth /* mftb */ 5361fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5362fcf5ef2aSThomas Huth { 5363fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5364fcf5ef2aSThomas Huth } 5365fcf5ef2aSThomas Huth 5366fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5367fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5368fcf5ef2aSThomas Huth { 5369fcf5ef2aSThomas Huth uint32_t crm, crn; 5370fcf5ef2aSThomas Huth 5371fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5372fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5373fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5374fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5375fcf5ef2aSThomas Huth crn = ctz32(crm); 5376fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5377fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5378fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5379fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5380fcf5ef2aSThomas Huth } 5381fcf5ef2aSThomas Huth } else { 5382fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5383fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5384fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5385fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5386fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5387fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5388fcf5ef2aSThomas Huth } 5389fcf5ef2aSThomas Huth } 5390fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5391fcf5ef2aSThomas Huth } 5392fcf5ef2aSThomas Huth } 5393fcf5ef2aSThomas Huth 5394fcf5ef2aSThomas Huth /* mtmsr */ 5395fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5396fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5397fcf5ef2aSThomas Huth { 5398fcf5ef2aSThomas Huth CHK_SV; 5399fcf5ef2aSThomas Huth 5400fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 54015ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54025ed19506SNicholas Piggin gen_io_start(); 54035ed19506SNicholas Piggin } 5404fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54055ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5406fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54075ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5408efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5409efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54105ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5411efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54125ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54135ed19506SNicholas Piggin 54145ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5415fcf5ef2aSThomas Huth tcg_temp_free(t0); 54165ed19506SNicholas Piggin tcg_temp_free(t1); 54175ed19506SNicholas Piggin 5418fcf5ef2aSThomas Huth } else { 5419efe843d8SDavid Gibson /* 5420efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5421efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5422efe843d8SDavid Gibson * ppc_store_msr 5423fcf5ef2aSThomas Huth */ 5424b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5425fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5426fcf5ef2aSThomas Huth } 54275ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54285ed19506SNicholas Piggin gen_stop_exception(ctx); 5429fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5430fcf5ef2aSThomas Huth } 5431fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5434fcf5ef2aSThomas Huth { 5435fcf5ef2aSThomas Huth CHK_SV; 5436fcf5ef2aSThomas Huth 5437fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 54385ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54395ed19506SNicholas Piggin gen_io_start(); 54405ed19506SNicholas Piggin } 5441fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54425ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5443fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54445ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5445efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5446efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54475ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5448efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54495ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54505ed19506SNicholas Piggin 54515ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5452fcf5ef2aSThomas Huth tcg_temp_free(t0); 54535ed19506SNicholas Piggin tcg_temp_free(t1); 54545ed19506SNicholas Piggin 5455fcf5ef2aSThomas Huth } else { 5456fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5457fcf5ef2aSThomas Huth 5458efe843d8SDavid Gibson /* 5459efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5460efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5461efe843d8SDavid Gibson * ppc_store_msr 5462fcf5ef2aSThomas Huth */ 5463b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5464fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5465fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5466fcf5ef2aSThomas Huth #else 5467fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5468fcf5ef2aSThomas Huth #endif 5469fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5470fcf5ef2aSThomas Huth tcg_temp_free(msr); 5471fcf5ef2aSThomas Huth } 54725ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54735ed19506SNicholas Piggin gen_stop_exception(ctx); 5474fcf5ef2aSThomas Huth #endif 5475fcf5ef2aSThomas Huth } 5476fcf5ef2aSThomas Huth 5477fcf5ef2aSThomas Huth /* mtspr */ 5478fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5479fcf5ef2aSThomas Huth { 5480fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5481fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5482fcf5ef2aSThomas Huth 5483fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5484fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5485fcf5ef2aSThomas Huth #else 5486fcf5ef2aSThomas Huth if (ctx->pr) { 5487fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5488fcf5ef2aSThomas Huth } else if (ctx->hv) { 5489fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5490fcf5ef2aSThomas Huth } else { 5491fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5492fcf5ef2aSThomas Huth } 5493fcf5ef2aSThomas Huth #endif 5494fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5495fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5496fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5497fcf5ef2aSThomas Huth } else { 5498fcf5ef2aSThomas Huth /* Privilege exception */ 549931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 550031085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 550131085338SThomas Huth ctx->base.pc_next - 4); 5502fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5503fcf5ef2aSThomas Huth } 5504fcf5ef2aSThomas Huth } else { 5505fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5506fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5507fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5508fcf5ef2aSThomas Huth /* This is a nop */ 5509fcf5ef2aSThomas Huth return; 5510fcf5ef2aSThomas Huth } 5511fcf5ef2aSThomas Huth 5512fcf5ef2aSThomas Huth /* Not defined */ 551331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 551431085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 5515b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 5516fcf5ef2aSThomas Huth 5517fcf5ef2aSThomas Huth 5518efe843d8SDavid Gibson /* 5519efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5520efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5521fcf5ef2aSThomas Huth */ 5522fcf5ef2aSThomas Huth if (sprn & 0x10) { 5523fcf5ef2aSThomas Huth if (ctx->pr) { 5524fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5525fcf5ef2aSThomas Huth } 5526fcf5ef2aSThomas Huth } else { 5527fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5528fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5529fcf5ef2aSThomas Huth } 5530fcf5ef2aSThomas Huth } 5531fcf5ef2aSThomas Huth } 5532fcf5ef2aSThomas Huth } 5533fcf5ef2aSThomas Huth 5534fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5535fcf5ef2aSThomas Huth /* setb */ 5536fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5537fcf5ef2aSThomas Huth { 5538fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5539fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5540fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5541fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5542fcf5ef2aSThomas Huth 5543fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5544fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5545fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5546fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5547fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5548fcf5ef2aSThomas Huth 5549fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5550fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5551fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5552fcf5ef2aSThomas Huth } 5553fcf5ef2aSThomas Huth #endif 5554fcf5ef2aSThomas Huth 5555fcf5ef2aSThomas Huth /*** Cache management ***/ 5556fcf5ef2aSThomas Huth 5557fcf5ef2aSThomas Huth /* dcbf */ 5558fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5559fcf5ef2aSThomas Huth { 5560fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5561fcf5ef2aSThomas Huth TCGv t0; 5562fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5563fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5564fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5565fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5566fcf5ef2aSThomas Huth tcg_temp_free(t0); 5567fcf5ef2aSThomas Huth } 5568fcf5ef2aSThomas Huth 556950728199SRoman Kapl /* dcbfep (external PID dcbf) */ 557050728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 557150728199SRoman Kapl { 557250728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 557350728199SRoman Kapl TCGv t0; 557450728199SRoman Kapl CHK_SV; 557550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 557650728199SRoman Kapl t0 = tcg_temp_new(); 557750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 557850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 557950728199SRoman Kapl tcg_temp_free(t0); 558050728199SRoman Kapl } 558150728199SRoman Kapl 5582fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5583fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5584fcf5ef2aSThomas Huth { 5585fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5586fcf5ef2aSThomas Huth GEN_PRIV; 5587fcf5ef2aSThomas Huth #else 5588fcf5ef2aSThomas Huth TCGv EA, val; 5589fcf5ef2aSThomas Huth 5590fcf5ef2aSThomas Huth CHK_SV; 5591fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5592fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5593fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5594fcf5ef2aSThomas Huth val = tcg_temp_new(); 5595fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5596fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5597fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5598fcf5ef2aSThomas Huth tcg_temp_free(val); 5599fcf5ef2aSThomas Huth tcg_temp_free(EA); 5600fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5601fcf5ef2aSThomas Huth } 5602fcf5ef2aSThomas Huth 5603fcf5ef2aSThomas Huth /* dcdst */ 5604fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5605fcf5ef2aSThomas Huth { 5606fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5607fcf5ef2aSThomas Huth TCGv t0; 5608fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5609fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5610fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5611fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5612fcf5ef2aSThomas Huth tcg_temp_free(t0); 5613fcf5ef2aSThomas Huth } 5614fcf5ef2aSThomas Huth 561550728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 561650728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 561750728199SRoman Kapl { 561850728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 561950728199SRoman Kapl TCGv t0; 562050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 562150728199SRoman Kapl t0 = tcg_temp_new(); 562250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 562350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 562450728199SRoman Kapl tcg_temp_free(t0); 562550728199SRoman Kapl } 562650728199SRoman Kapl 5627fcf5ef2aSThomas Huth /* dcbt */ 5628fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5629fcf5ef2aSThomas Huth { 5630efe843d8SDavid Gibson /* 5631efe843d8SDavid Gibson * interpreted as no-op 5632efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5633efe843d8SDavid Gibson * does not generate any exception 5634fcf5ef2aSThomas Huth */ 5635fcf5ef2aSThomas Huth } 5636fcf5ef2aSThomas Huth 563750728199SRoman Kapl /* dcbtep */ 563850728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 563950728199SRoman Kapl { 5640efe843d8SDavid Gibson /* 5641efe843d8SDavid Gibson * interpreted as no-op 5642efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5643efe843d8SDavid Gibson * does not generate any exception 564450728199SRoman Kapl */ 564550728199SRoman Kapl } 564650728199SRoman Kapl 5647fcf5ef2aSThomas Huth /* dcbtst */ 5648fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5649fcf5ef2aSThomas Huth { 5650efe843d8SDavid Gibson /* 5651efe843d8SDavid Gibson * interpreted as no-op 5652efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5653efe843d8SDavid Gibson * does not generate any exception 5654fcf5ef2aSThomas Huth */ 5655fcf5ef2aSThomas Huth } 5656fcf5ef2aSThomas Huth 565750728199SRoman Kapl /* dcbtstep */ 565850728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 565950728199SRoman Kapl { 5660efe843d8SDavid Gibson /* 5661efe843d8SDavid Gibson * interpreted as no-op 5662efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5663efe843d8SDavid Gibson * does not generate any exception 566450728199SRoman Kapl */ 566550728199SRoman Kapl } 566650728199SRoman Kapl 5667fcf5ef2aSThomas Huth /* dcbtls */ 5668fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5669fcf5ef2aSThomas Huth { 5670fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5671fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5672fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5673fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5674fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5675fcf5ef2aSThomas Huth tcg_temp_free(t0); 5676fcf5ef2aSThomas Huth } 5677fcf5ef2aSThomas Huth 5678fcf5ef2aSThomas Huth /* dcbz */ 5679fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5680fcf5ef2aSThomas Huth { 5681fcf5ef2aSThomas Huth TCGv tcgv_addr; 5682fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5683fcf5ef2aSThomas Huth 5684fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5685fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5686fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5687fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5688fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5689fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5690fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5691fcf5ef2aSThomas Huth } 5692fcf5ef2aSThomas Huth 569350728199SRoman Kapl /* dcbzep */ 569450728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 569550728199SRoman Kapl { 569650728199SRoman Kapl TCGv tcgv_addr; 569750728199SRoman Kapl TCGv_i32 tcgv_op; 569850728199SRoman Kapl 569950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 570050728199SRoman Kapl tcgv_addr = tcg_temp_new(); 570150728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 570250728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 570350728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 570450728199SRoman Kapl tcg_temp_free(tcgv_addr); 570550728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 570650728199SRoman Kapl } 570750728199SRoman Kapl 5708fcf5ef2aSThomas Huth /* dst / dstt */ 5709fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5710fcf5ef2aSThomas Huth { 5711fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5712fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5713fcf5ef2aSThomas Huth } else { 5714fcf5ef2aSThomas Huth /* interpreted as no-op */ 5715fcf5ef2aSThomas Huth } 5716fcf5ef2aSThomas Huth } 5717fcf5ef2aSThomas Huth 5718fcf5ef2aSThomas Huth /* dstst /dststt */ 5719fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5720fcf5ef2aSThomas Huth { 5721fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5722fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5723fcf5ef2aSThomas Huth } else { 5724fcf5ef2aSThomas Huth /* interpreted as no-op */ 5725fcf5ef2aSThomas Huth } 5726fcf5ef2aSThomas Huth 5727fcf5ef2aSThomas Huth } 5728fcf5ef2aSThomas Huth 5729fcf5ef2aSThomas Huth /* dss / dssall */ 5730fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5731fcf5ef2aSThomas Huth { 5732fcf5ef2aSThomas Huth /* interpreted as no-op */ 5733fcf5ef2aSThomas Huth } 5734fcf5ef2aSThomas Huth 5735fcf5ef2aSThomas Huth /* icbi */ 5736fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5737fcf5ef2aSThomas Huth { 5738fcf5ef2aSThomas Huth TCGv t0; 5739fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5740fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5741fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5742fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5743fcf5ef2aSThomas Huth tcg_temp_free(t0); 5744fcf5ef2aSThomas Huth } 5745fcf5ef2aSThomas Huth 574650728199SRoman Kapl /* icbiep */ 574750728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 574850728199SRoman Kapl { 574950728199SRoman Kapl TCGv t0; 575050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 575150728199SRoman Kapl t0 = tcg_temp_new(); 575250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 575350728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 575450728199SRoman Kapl tcg_temp_free(t0); 575550728199SRoman Kapl } 575650728199SRoman Kapl 5757fcf5ef2aSThomas Huth /* Optional: */ 5758fcf5ef2aSThomas Huth /* dcba */ 5759fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5760fcf5ef2aSThomas Huth { 5761efe843d8SDavid Gibson /* 5762efe843d8SDavid Gibson * interpreted as no-op 5763efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5764fcf5ef2aSThomas Huth * but does not generate any exception 5765fcf5ef2aSThomas Huth */ 5766fcf5ef2aSThomas Huth } 5767fcf5ef2aSThomas Huth 5768fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5769fcf5ef2aSThomas Huth /* Supervisor only: */ 5770fcf5ef2aSThomas Huth 5771fcf5ef2aSThomas Huth /* mfsr */ 5772fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5773fcf5ef2aSThomas Huth { 5774fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5775fcf5ef2aSThomas Huth GEN_PRIV; 5776fcf5ef2aSThomas Huth #else 5777fcf5ef2aSThomas Huth TCGv t0; 5778fcf5ef2aSThomas Huth 5779fcf5ef2aSThomas Huth CHK_SV; 5780fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5781fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5782fcf5ef2aSThomas Huth tcg_temp_free(t0); 5783fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5784fcf5ef2aSThomas Huth } 5785fcf5ef2aSThomas Huth 5786fcf5ef2aSThomas Huth /* mfsrin */ 5787fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5788fcf5ef2aSThomas Huth { 5789fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5790fcf5ef2aSThomas Huth GEN_PRIV; 5791fcf5ef2aSThomas Huth #else 5792fcf5ef2aSThomas Huth TCGv t0; 5793fcf5ef2aSThomas Huth 5794fcf5ef2aSThomas Huth CHK_SV; 5795fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5796e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5797fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5798fcf5ef2aSThomas Huth tcg_temp_free(t0); 5799fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5800fcf5ef2aSThomas Huth } 5801fcf5ef2aSThomas Huth 5802fcf5ef2aSThomas Huth /* mtsr */ 5803fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5804fcf5ef2aSThomas Huth { 5805fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5806fcf5ef2aSThomas Huth GEN_PRIV; 5807fcf5ef2aSThomas Huth #else 5808fcf5ef2aSThomas Huth TCGv t0; 5809fcf5ef2aSThomas Huth 5810fcf5ef2aSThomas Huth CHK_SV; 5811fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5812fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5813fcf5ef2aSThomas Huth tcg_temp_free(t0); 5814fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5815fcf5ef2aSThomas Huth } 5816fcf5ef2aSThomas Huth 5817fcf5ef2aSThomas Huth /* mtsrin */ 5818fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5819fcf5ef2aSThomas Huth { 5820fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5821fcf5ef2aSThomas Huth GEN_PRIV; 5822fcf5ef2aSThomas Huth #else 5823fcf5ef2aSThomas Huth TCGv t0; 5824fcf5ef2aSThomas Huth CHK_SV; 5825fcf5ef2aSThomas Huth 5826fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5827e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5828fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5829fcf5ef2aSThomas Huth tcg_temp_free(t0); 5830fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5831fcf5ef2aSThomas Huth } 5832fcf5ef2aSThomas Huth 5833fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5834fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5835fcf5ef2aSThomas Huth 5836fcf5ef2aSThomas Huth /* mfsr */ 5837fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5838fcf5ef2aSThomas Huth { 5839fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5840fcf5ef2aSThomas Huth GEN_PRIV; 5841fcf5ef2aSThomas Huth #else 5842fcf5ef2aSThomas Huth TCGv t0; 5843fcf5ef2aSThomas Huth 5844fcf5ef2aSThomas Huth CHK_SV; 5845fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5846fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5847fcf5ef2aSThomas Huth tcg_temp_free(t0); 5848fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5849fcf5ef2aSThomas Huth } 5850fcf5ef2aSThomas Huth 5851fcf5ef2aSThomas Huth /* mfsrin */ 5852fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5853fcf5ef2aSThomas Huth { 5854fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5855fcf5ef2aSThomas Huth GEN_PRIV; 5856fcf5ef2aSThomas Huth #else 5857fcf5ef2aSThomas Huth TCGv t0; 5858fcf5ef2aSThomas Huth 5859fcf5ef2aSThomas Huth CHK_SV; 5860fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5861e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5862fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5863fcf5ef2aSThomas Huth tcg_temp_free(t0); 5864fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5865fcf5ef2aSThomas Huth } 5866fcf5ef2aSThomas Huth 5867fcf5ef2aSThomas Huth /* mtsr */ 5868fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5869fcf5ef2aSThomas Huth { 5870fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5871fcf5ef2aSThomas Huth GEN_PRIV; 5872fcf5ef2aSThomas Huth #else 5873fcf5ef2aSThomas Huth TCGv t0; 5874fcf5ef2aSThomas Huth 5875fcf5ef2aSThomas Huth CHK_SV; 5876fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5877fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5878fcf5ef2aSThomas Huth tcg_temp_free(t0); 5879fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5880fcf5ef2aSThomas Huth } 5881fcf5ef2aSThomas Huth 5882fcf5ef2aSThomas Huth /* mtsrin */ 5883fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5884fcf5ef2aSThomas Huth { 5885fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5886fcf5ef2aSThomas Huth GEN_PRIV; 5887fcf5ef2aSThomas Huth #else 5888fcf5ef2aSThomas Huth TCGv t0; 5889fcf5ef2aSThomas Huth 5890fcf5ef2aSThomas Huth CHK_SV; 5891fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5892e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5893fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5894fcf5ef2aSThomas Huth tcg_temp_free(t0); 5895fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5896fcf5ef2aSThomas Huth } 5897fcf5ef2aSThomas Huth 5898fcf5ef2aSThomas Huth /* slbmte */ 5899fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5900fcf5ef2aSThomas Huth { 5901fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5902fcf5ef2aSThomas Huth GEN_PRIV; 5903fcf5ef2aSThomas Huth #else 5904fcf5ef2aSThomas Huth CHK_SV; 5905fcf5ef2aSThomas Huth 5906fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5907fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5908fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5909fcf5ef2aSThomas Huth } 5910fcf5ef2aSThomas Huth 5911fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5912fcf5ef2aSThomas Huth { 5913fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5914fcf5ef2aSThomas Huth GEN_PRIV; 5915fcf5ef2aSThomas Huth #else 5916fcf5ef2aSThomas Huth CHK_SV; 5917fcf5ef2aSThomas Huth 5918fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5919fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5920fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5921fcf5ef2aSThomas Huth } 5922fcf5ef2aSThomas Huth 5923fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5924fcf5ef2aSThomas Huth { 5925fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5926fcf5ef2aSThomas Huth GEN_PRIV; 5927fcf5ef2aSThomas Huth #else 5928fcf5ef2aSThomas Huth CHK_SV; 5929fcf5ef2aSThomas Huth 5930fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5931fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5932fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5933fcf5ef2aSThomas Huth } 5934fcf5ef2aSThomas Huth 5935fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5936fcf5ef2aSThomas Huth { 5937fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5938fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5939fcf5ef2aSThomas Huth #else 5940fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5941fcf5ef2aSThomas Huth 5942fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5943fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5944fcf5ef2aSThomas Huth return; 5945fcf5ef2aSThomas Huth } 5946fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5947fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5948fcf5ef2aSThomas Huth l1 = gen_new_label(); 5949fcf5ef2aSThomas Huth l2 = gen_new_label(); 5950fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5951fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5952efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5953fcf5ef2aSThomas Huth tcg_gen_br(l2); 5954fcf5ef2aSThomas Huth gen_set_label(l1); 5955fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5956fcf5ef2aSThomas Huth gen_set_label(l2); 5957fcf5ef2aSThomas Huth #endif 5958fcf5ef2aSThomas Huth } 5959fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5960fcf5ef2aSThomas Huth 5961fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5962fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5963fcf5ef2aSThomas Huth 5964fcf5ef2aSThomas Huth /* tlbia */ 5965fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5966fcf5ef2aSThomas Huth { 5967fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5968fcf5ef2aSThomas Huth GEN_PRIV; 5969fcf5ef2aSThomas Huth #else 5970fcf5ef2aSThomas Huth CHK_HV; 5971fcf5ef2aSThomas Huth 5972fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5973fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5974fcf5ef2aSThomas Huth } 5975fcf5ef2aSThomas Huth 5976fcf5ef2aSThomas Huth /* tlbiel */ 5977fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5978fcf5ef2aSThomas Huth { 5979fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5980fcf5ef2aSThomas Huth GEN_PRIV; 5981fcf5ef2aSThomas Huth #else 5982fcf5ef2aSThomas Huth CHK_SV; 5983fcf5ef2aSThomas Huth 5984fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5985fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5986fcf5ef2aSThomas Huth } 5987fcf5ef2aSThomas Huth 5988fcf5ef2aSThomas Huth /* tlbie */ 5989fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5990fcf5ef2aSThomas Huth { 5991fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5992fcf5ef2aSThomas Huth GEN_PRIV; 5993fcf5ef2aSThomas Huth #else 5994fcf5ef2aSThomas Huth TCGv_i32 t1; 5995c6fd28fdSSuraj Jitindar Singh 5996c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 599791c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5998c6fd28fdSSuraj Jitindar Singh } else { 5999c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 6000c6fd28fdSSuraj Jitindar Singh } 6001fcf5ef2aSThomas Huth 6002fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 6003fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6004fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 6005fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 6006fcf5ef2aSThomas Huth tcg_temp_free(t0); 6007fcf5ef2aSThomas Huth } else { 6008fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6009fcf5ef2aSThomas Huth } 6010fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 6011fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6012fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 6013fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6014fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6015fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6016fcf5ef2aSThomas Huth } 6017fcf5ef2aSThomas Huth 6018fcf5ef2aSThomas Huth /* tlbsync */ 6019fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 6020fcf5ef2aSThomas Huth { 6021fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6022fcf5ef2aSThomas Huth GEN_PRIV; 6023fcf5ef2aSThomas Huth #else 602491c60f12SCédric Le Goater 602591c60f12SCédric Le Goater if (ctx->gtse) { 602691c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 602791c60f12SCédric Le Goater } else { 602891c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 602991c60f12SCédric Le Goater } 6030fcf5ef2aSThomas Huth 6031fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 6032fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 6033fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 6034fcf5ef2aSThomas Huth } 6035fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6036fcf5ef2aSThomas Huth } 6037fcf5ef2aSThomas Huth 6038fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6039fcf5ef2aSThomas Huth /* slbia */ 6040fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 6041fcf5ef2aSThomas Huth { 6042fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6043fcf5ef2aSThomas Huth GEN_PRIV; 6044fcf5ef2aSThomas Huth #else 60450418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 60460418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 60470418bf78SNicholas Piggin 6048fcf5ef2aSThomas Huth CHK_SV; 6049fcf5ef2aSThomas Huth 60500418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 60513119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 6052fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6053fcf5ef2aSThomas Huth } 6054fcf5ef2aSThomas Huth 6055fcf5ef2aSThomas Huth /* slbie */ 6056fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 6057fcf5ef2aSThomas Huth { 6058fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6059fcf5ef2aSThomas Huth GEN_PRIV; 6060fcf5ef2aSThomas Huth #else 6061fcf5ef2aSThomas Huth CHK_SV; 6062fcf5ef2aSThomas Huth 6063fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6064fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6065fcf5ef2aSThomas Huth } 6066a63f1dfcSNikunj A Dadhania 6067a63f1dfcSNikunj A Dadhania /* slbieg */ 6068a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 6069a63f1dfcSNikunj A Dadhania { 6070a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 6071a63f1dfcSNikunj A Dadhania GEN_PRIV; 6072a63f1dfcSNikunj A Dadhania #else 6073a63f1dfcSNikunj A Dadhania CHK_SV; 6074a63f1dfcSNikunj A Dadhania 6075a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6076a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 6077a63f1dfcSNikunj A Dadhania } 6078a63f1dfcSNikunj A Dadhania 607962d897caSNikunj A Dadhania /* slbsync */ 608062d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 608162d897caSNikunj A Dadhania { 608262d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 608362d897caSNikunj A Dadhania GEN_PRIV; 608462d897caSNikunj A Dadhania #else 608562d897caSNikunj A Dadhania CHK_SV; 608662d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 608762d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 608862d897caSNikunj A Dadhania } 608962d897caSNikunj A Dadhania 6090fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6091fcf5ef2aSThomas Huth 6092fcf5ef2aSThomas Huth /*** External control ***/ 6093fcf5ef2aSThomas Huth /* Optional: */ 6094fcf5ef2aSThomas Huth 6095fcf5ef2aSThomas Huth /* eciwx */ 6096fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 6097fcf5ef2aSThomas Huth { 6098fcf5ef2aSThomas Huth TCGv t0; 6099fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6100fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6101fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6102fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6103c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6104c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6105fcf5ef2aSThomas Huth tcg_temp_free(t0); 6106fcf5ef2aSThomas Huth } 6107fcf5ef2aSThomas Huth 6108fcf5ef2aSThomas Huth /* ecowx */ 6109fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 6110fcf5ef2aSThomas Huth { 6111fcf5ef2aSThomas Huth TCGv t0; 6112fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6113fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6114fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6115fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6116c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6117c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6118fcf5ef2aSThomas Huth tcg_temp_free(t0); 6119fcf5ef2aSThomas Huth } 6120fcf5ef2aSThomas Huth 6121fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 6122fcf5ef2aSThomas Huth 6123fcf5ef2aSThomas Huth /* abs - abs. */ 6124fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 6125fcf5ef2aSThomas Huth { 6126fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6127fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6128fe21b785SRichard Henderson 6129fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6130efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6131fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6132fcf5ef2aSThomas Huth } 6133efe843d8SDavid Gibson } 6134fcf5ef2aSThomas Huth 6135fcf5ef2aSThomas Huth /* abso - abso. */ 6136fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 6137fcf5ef2aSThomas Huth { 6138fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6139fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6140fe21b785SRichard Henderson 6141fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 6142fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6143fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 6144efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6145fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6146fcf5ef2aSThomas Huth } 6147efe843d8SDavid Gibson } 6148fcf5ef2aSThomas Huth 6149fcf5ef2aSThomas Huth /* clcs */ 6150fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 6151fcf5ef2aSThomas Huth { 6152fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 6153fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6154fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6155fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 6156fcf5ef2aSThomas Huth } 6157fcf5ef2aSThomas Huth 6158fcf5ef2aSThomas Huth /* div - div. */ 6159fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 6160fcf5ef2aSThomas Huth { 6161fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6162fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6163efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6164fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6165fcf5ef2aSThomas Huth } 6166efe843d8SDavid Gibson } 6167fcf5ef2aSThomas Huth 6168fcf5ef2aSThomas Huth /* divo - divo. */ 6169fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 6170fcf5ef2aSThomas Huth { 6171fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6172fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6173efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6174fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6175fcf5ef2aSThomas Huth } 6176efe843d8SDavid Gibson } 6177fcf5ef2aSThomas Huth 6178fcf5ef2aSThomas Huth /* divs - divs. */ 6179fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 6180fcf5ef2aSThomas Huth { 6181fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6182fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6183efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6184fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6185fcf5ef2aSThomas Huth } 6186efe843d8SDavid Gibson } 6187fcf5ef2aSThomas Huth 6188fcf5ef2aSThomas Huth /* divso - divso. */ 6189fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 6190fcf5ef2aSThomas Huth { 6191fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 6192fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6193efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6194fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6195fcf5ef2aSThomas Huth } 6196efe843d8SDavid Gibson } 6197fcf5ef2aSThomas Huth 6198fcf5ef2aSThomas Huth /* doz - doz. */ 6199fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 6200fcf5ef2aSThomas Huth { 6201fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6202fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6203efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6204efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6205efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 6206efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 6207fcf5ef2aSThomas Huth tcg_gen_br(l2); 6208fcf5ef2aSThomas Huth gen_set_label(l1); 6209fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6210fcf5ef2aSThomas Huth gen_set_label(l2); 6211efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6212fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6213fcf5ef2aSThomas Huth } 6214efe843d8SDavid Gibson } 6215fcf5ef2aSThomas Huth 6216fcf5ef2aSThomas Huth /* dozo - dozo. */ 6217fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 6218fcf5ef2aSThomas Huth { 6219fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6220fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6221fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6222fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6223fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6224fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6225fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6226efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6227efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6228fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6229fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6230fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 6231fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6232fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 6233fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6234fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6235fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6236fcf5ef2aSThomas Huth tcg_gen_br(l2); 6237fcf5ef2aSThomas Huth gen_set_label(l1); 6238fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6239fcf5ef2aSThomas Huth gen_set_label(l2); 6240fcf5ef2aSThomas Huth tcg_temp_free(t0); 6241fcf5ef2aSThomas Huth tcg_temp_free(t1); 6242fcf5ef2aSThomas Huth tcg_temp_free(t2); 6243efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6244fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6245fcf5ef2aSThomas Huth } 6246efe843d8SDavid Gibson } 6247fcf5ef2aSThomas Huth 6248fcf5ef2aSThomas Huth /* dozi */ 6249fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 6250fcf5ef2aSThomas Huth { 6251fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 6252fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6253fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6254fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 6255fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 6256fcf5ef2aSThomas Huth tcg_gen_br(l2); 6257fcf5ef2aSThomas Huth gen_set_label(l1); 6258fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6259fcf5ef2aSThomas Huth gen_set_label(l2); 6260efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6261fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6262fcf5ef2aSThomas Huth } 6263efe843d8SDavid Gibson } 6264fcf5ef2aSThomas Huth 6265fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 6266fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 6267fcf5ef2aSThomas Huth { 6268fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6269fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 6270fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 6271fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 6272fcf5ef2aSThomas Huth 6273fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6274fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 6275fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6276fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 6277fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 6278fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 6279fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 6280efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6281fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 6282efe843d8SDavid Gibson } 6283fcf5ef2aSThomas Huth tcg_temp_free(t0); 6284fcf5ef2aSThomas Huth } 6285fcf5ef2aSThomas Huth 6286fcf5ef2aSThomas Huth /* maskg - maskg. */ 6287fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 6288fcf5ef2aSThomas Huth { 6289fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6290fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6291fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6292fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6293fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 6294fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 6295fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6296fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 6297fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 6298fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 6299fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 6300fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 6301fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 6302fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6303fcf5ef2aSThomas Huth gen_set_label(l1); 6304fcf5ef2aSThomas Huth tcg_temp_free(t0); 6305fcf5ef2aSThomas Huth tcg_temp_free(t1); 6306fcf5ef2aSThomas Huth tcg_temp_free(t2); 6307fcf5ef2aSThomas Huth tcg_temp_free(t3); 6308efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6309fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6310fcf5ef2aSThomas Huth } 6311efe843d8SDavid Gibson } 6312fcf5ef2aSThomas Huth 6313fcf5ef2aSThomas Huth /* maskir - maskir. */ 6314fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 6315fcf5ef2aSThomas Huth { 6316fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6317fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6318fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6319fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6320fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6321fcf5ef2aSThomas Huth tcg_temp_free(t0); 6322fcf5ef2aSThomas Huth tcg_temp_free(t1); 6323efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6324fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6325fcf5ef2aSThomas Huth } 6326efe843d8SDavid Gibson } 6327fcf5ef2aSThomas Huth 6328fcf5ef2aSThomas Huth /* mul - mul. */ 6329fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 6330fcf5ef2aSThomas Huth { 6331fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6332fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6333fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6334fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6335fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6336fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6337fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6338fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6339fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6340fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6341fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6342fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6343fcf5ef2aSThomas Huth tcg_temp_free(t2); 6344efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6345fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6346fcf5ef2aSThomas Huth } 6347efe843d8SDavid Gibson } 6348fcf5ef2aSThomas Huth 6349fcf5ef2aSThomas Huth /* mulo - mulo. */ 6350fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6351fcf5ef2aSThomas Huth { 6352fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6353fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6354fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6355fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6356fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6357fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6358fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6359fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6360fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6361fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6362fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6363fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6364fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6365fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6366fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6367fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6368fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6369fcf5ef2aSThomas Huth gen_set_label(l1); 6370fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6371fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6372fcf5ef2aSThomas Huth tcg_temp_free(t2); 6373efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6374fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6375fcf5ef2aSThomas Huth } 6376efe843d8SDavid Gibson } 6377fcf5ef2aSThomas Huth 6378fcf5ef2aSThomas Huth /* nabs - nabs. */ 6379fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6380fcf5ef2aSThomas Huth { 6381fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6382fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6383fe21b785SRichard Henderson 6384fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6385fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6386efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6387fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6388fcf5ef2aSThomas Huth } 6389efe843d8SDavid Gibson } 6390fcf5ef2aSThomas Huth 6391fcf5ef2aSThomas Huth /* nabso - nabso. */ 6392fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6393fcf5ef2aSThomas Huth { 6394fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6395fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6396fe21b785SRichard Henderson 6397fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6398fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6399fcf5ef2aSThomas Huth /* nabs never overflows */ 6400fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6401efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6402fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6403fcf5ef2aSThomas Huth } 6404efe843d8SDavid Gibson } 6405fcf5ef2aSThomas Huth 6406fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6407fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6408fcf5ef2aSThomas Huth { 6409fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6410fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6411fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6412fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6413fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6414fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6415efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6416efe843d8SDavid Gibson ~MASK(mb, me)); 6417fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6418fcf5ef2aSThomas Huth tcg_temp_free(t0); 6419efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6420fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6421fcf5ef2aSThomas Huth } 6422efe843d8SDavid Gibson } 6423fcf5ef2aSThomas Huth 6424fcf5ef2aSThomas Huth /* rrib - rrib. */ 6425fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6426fcf5ef2aSThomas Huth { 6427fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6428fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6429fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6430fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6431fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6432fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6433fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6434fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6435fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6436fcf5ef2aSThomas Huth tcg_temp_free(t0); 6437fcf5ef2aSThomas Huth tcg_temp_free(t1); 6438efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6439fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6440fcf5ef2aSThomas Huth } 6441efe843d8SDavid Gibson } 6442fcf5ef2aSThomas Huth 6443fcf5ef2aSThomas Huth /* sle - sle. */ 6444fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6445fcf5ef2aSThomas Huth { 6446fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6447fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6448fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6449fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6450fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6451fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6452fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6453fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6454fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6455fcf5ef2aSThomas Huth tcg_temp_free(t0); 6456fcf5ef2aSThomas Huth tcg_temp_free(t1); 6457efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6458fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6459fcf5ef2aSThomas Huth } 6460efe843d8SDavid Gibson } 6461fcf5ef2aSThomas Huth 6462fcf5ef2aSThomas Huth /* sleq - sleq. */ 6463fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6464fcf5ef2aSThomas Huth { 6465fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6466fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6467fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6468fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6469fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6470fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6471fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6472fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6473fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6474fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6475fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6476fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6477fcf5ef2aSThomas Huth tcg_temp_free(t0); 6478fcf5ef2aSThomas Huth tcg_temp_free(t1); 6479fcf5ef2aSThomas Huth tcg_temp_free(t2); 6480efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6481fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6482fcf5ef2aSThomas Huth } 6483efe843d8SDavid Gibson } 6484fcf5ef2aSThomas Huth 6485fcf5ef2aSThomas Huth /* sliq - sliq. */ 6486fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6487fcf5ef2aSThomas Huth { 6488fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6489fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6490fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6491fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6492fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6493fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6494fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6495fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6496fcf5ef2aSThomas Huth tcg_temp_free(t0); 6497fcf5ef2aSThomas Huth tcg_temp_free(t1); 6498efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6499fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6500fcf5ef2aSThomas Huth } 6501efe843d8SDavid Gibson } 6502fcf5ef2aSThomas Huth 6503fcf5ef2aSThomas Huth /* slliq - slliq. */ 6504fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6505fcf5ef2aSThomas Huth { 6506fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6507fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6508fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6509fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6510fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6511fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6512fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6513fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6514fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6515fcf5ef2aSThomas Huth tcg_temp_free(t0); 6516fcf5ef2aSThomas Huth tcg_temp_free(t1); 6517efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6518fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6519fcf5ef2aSThomas Huth } 6520efe843d8SDavid Gibson } 6521fcf5ef2aSThomas Huth 6522fcf5ef2aSThomas Huth /* sllq - sllq. */ 6523fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6524fcf5ef2aSThomas Huth { 6525fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6526fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6527fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6528fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6529fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6530fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6531fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6532fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6533fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6534fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6535fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6536fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6537fcf5ef2aSThomas Huth tcg_gen_br(l2); 6538fcf5ef2aSThomas Huth gen_set_label(l1); 6539fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6540fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6541fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6542fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6543fcf5ef2aSThomas Huth gen_set_label(l2); 6544fcf5ef2aSThomas Huth tcg_temp_free(t0); 6545fcf5ef2aSThomas Huth tcg_temp_free(t1); 6546fcf5ef2aSThomas Huth tcg_temp_free(t2); 6547efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6548fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6549fcf5ef2aSThomas Huth } 6550efe843d8SDavid Gibson } 6551fcf5ef2aSThomas Huth 6552fcf5ef2aSThomas Huth /* slq - slq. */ 6553fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6554fcf5ef2aSThomas Huth { 6555fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6556fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6557fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6558fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6559fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6560fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6561fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6562fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6563fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6564fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6565fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6566fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6567fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6568fcf5ef2aSThomas Huth gen_set_label(l1); 6569fcf5ef2aSThomas Huth tcg_temp_free(t0); 6570fcf5ef2aSThomas Huth tcg_temp_free(t1); 6571efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6572fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6573fcf5ef2aSThomas Huth } 6574efe843d8SDavid Gibson } 6575fcf5ef2aSThomas Huth 6576fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6577fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6578fcf5ef2aSThomas Huth { 6579fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6580fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6581fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6582fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6583fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6584fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6585fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6586fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6587fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6588fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6589fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6590fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6591fcf5ef2aSThomas Huth gen_set_label(l1); 6592fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6593fcf5ef2aSThomas Huth tcg_temp_free(t0); 6594fcf5ef2aSThomas Huth tcg_temp_free(t1); 6595efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6596fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6597fcf5ef2aSThomas Huth } 6598efe843d8SDavid Gibson } 6599fcf5ef2aSThomas Huth 6600fcf5ef2aSThomas Huth /* sraq - sraq. */ 6601fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6602fcf5ef2aSThomas Huth { 6603fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6604fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6605fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6606fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6607fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6608fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6609fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6610fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6611fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6612fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6613fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6614fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6615fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6616fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6617fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6618fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6619fcf5ef2aSThomas Huth gen_set_label(l1); 6620fcf5ef2aSThomas Huth tcg_temp_free(t0); 6621fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6622fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6623fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6624fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6625fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6626fcf5ef2aSThomas Huth gen_set_label(l2); 6627fcf5ef2aSThomas Huth tcg_temp_free(t1); 6628fcf5ef2aSThomas Huth tcg_temp_free(t2); 6629efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6630fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6631fcf5ef2aSThomas Huth } 6632efe843d8SDavid Gibson } 6633fcf5ef2aSThomas Huth 6634fcf5ef2aSThomas Huth /* sre - sre. */ 6635fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6636fcf5ef2aSThomas Huth { 6637fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6638fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6639fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6640fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6641fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6642fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6643fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6644fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6645fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6646fcf5ef2aSThomas Huth tcg_temp_free(t0); 6647fcf5ef2aSThomas Huth tcg_temp_free(t1); 6648efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6649fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6650fcf5ef2aSThomas Huth } 6651efe843d8SDavid Gibson } 6652fcf5ef2aSThomas Huth 6653fcf5ef2aSThomas Huth /* srea - srea. */ 6654fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6655fcf5ef2aSThomas Huth { 6656fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6657fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6658fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6659fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6660fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6661fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6662fcf5ef2aSThomas Huth tcg_temp_free(t0); 6663fcf5ef2aSThomas Huth tcg_temp_free(t1); 6664efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6665fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6666fcf5ef2aSThomas Huth } 6667efe843d8SDavid Gibson } 6668fcf5ef2aSThomas Huth 6669fcf5ef2aSThomas Huth /* sreq */ 6670fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6671fcf5ef2aSThomas Huth { 6672fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6673fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6674fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6675fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6676fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6677fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6678fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6679fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6680fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6681fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6682fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6683fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6684fcf5ef2aSThomas Huth tcg_temp_free(t0); 6685fcf5ef2aSThomas Huth tcg_temp_free(t1); 6686fcf5ef2aSThomas Huth tcg_temp_free(t2); 6687efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6688fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6689fcf5ef2aSThomas Huth } 6690efe843d8SDavid Gibson } 6691fcf5ef2aSThomas Huth 6692fcf5ef2aSThomas Huth /* sriq */ 6693fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6694fcf5ef2aSThomas Huth { 6695fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6696fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6697fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6698fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6699fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6700fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6701fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6702fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6703fcf5ef2aSThomas Huth tcg_temp_free(t0); 6704fcf5ef2aSThomas Huth tcg_temp_free(t1); 6705efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6706fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6707fcf5ef2aSThomas Huth } 6708efe843d8SDavid Gibson } 6709fcf5ef2aSThomas Huth 6710fcf5ef2aSThomas Huth /* srliq */ 6711fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6712fcf5ef2aSThomas Huth { 6713fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6714fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6715fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6716fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6717fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6718fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6719fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6720fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6721fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6722fcf5ef2aSThomas Huth tcg_temp_free(t0); 6723fcf5ef2aSThomas Huth tcg_temp_free(t1); 6724efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6725fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6726fcf5ef2aSThomas Huth } 6727efe843d8SDavid Gibson } 6728fcf5ef2aSThomas Huth 6729fcf5ef2aSThomas Huth /* srlq */ 6730fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6731fcf5ef2aSThomas Huth { 6732fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6733fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6734fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6735fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6736fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6737fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6738fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6739fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6740fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6741fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6742fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6743fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6744fcf5ef2aSThomas Huth tcg_gen_br(l2); 6745fcf5ef2aSThomas Huth gen_set_label(l1); 6746fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6747fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6748fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6749fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6750fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6751fcf5ef2aSThomas Huth gen_set_label(l2); 6752fcf5ef2aSThomas Huth tcg_temp_free(t0); 6753fcf5ef2aSThomas Huth tcg_temp_free(t1); 6754fcf5ef2aSThomas Huth tcg_temp_free(t2); 6755efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6756fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6757fcf5ef2aSThomas Huth } 6758efe843d8SDavid Gibson } 6759fcf5ef2aSThomas Huth 6760fcf5ef2aSThomas Huth /* srq */ 6761fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6762fcf5ef2aSThomas Huth { 6763fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6764fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6765fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6766fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6767fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6768fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6769fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6770fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6771fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6772fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6773fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6774fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6775fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6776fcf5ef2aSThomas Huth gen_set_label(l1); 6777fcf5ef2aSThomas Huth tcg_temp_free(t0); 6778fcf5ef2aSThomas Huth tcg_temp_free(t1); 6779efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6780fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6781fcf5ef2aSThomas Huth } 6782efe843d8SDavid Gibson } 6783fcf5ef2aSThomas Huth 6784fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6785fcf5ef2aSThomas Huth 6786fcf5ef2aSThomas Huth /* dsa */ 6787fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6788fcf5ef2aSThomas Huth { 6789fcf5ef2aSThomas Huth /* XXX: TODO */ 6790fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6791fcf5ef2aSThomas Huth } 6792fcf5ef2aSThomas Huth 6793fcf5ef2aSThomas Huth /* esa */ 6794fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6795fcf5ef2aSThomas Huth { 6796fcf5ef2aSThomas Huth /* XXX: TODO */ 6797fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6798fcf5ef2aSThomas Huth } 6799fcf5ef2aSThomas Huth 6800fcf5ef2aSThomas Huth /* mfrom */ 6801fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6802fcf5ef2aSThomas Huth { 6803fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6804fcf5ef2aSThomas Huth GEN_PRIV; 6805fcf5ef2aSThomas Huth #else 6806fcf5ef2aSThomas Huth CHK_SV; 6807fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6808fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6809fcf5ef2aSThomas Huth } 6810fcf5ef2aSThomas Huth 6811fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6812fcf5ef2aSThomas Huth 6813fcf5ef2aSThomas Huth /* tlbld */ 6814fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6815fcf5ef2aSThomas Huth { 6816fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6817fcf5ef2aSThomas Huth GEN_PRIV; 6818fcf5ef2aSThomas Huth #else 6819fcf5ef2aSThomas Huth CHK_SV; 6820fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6821fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6822fcf5ef2aSThomas Huth } 6823fcf5ef2aSThomas Huth 6824fcf5ef2aSThomas Huth /* tlbli */ 6825fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6826fcf5ef2aSThomas Huth { 6827fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6828fcf5ef2aSThomas Huth GEN_PRIV; 6829fcf5ef2aSThomas Huth #else 6830fcf5ef2aSThomas Huth CHK_SV; 6831fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6832fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6833fcf5ef2aSThomas Huth } 6834fcf5ef2aSThomas Huth 6835fcf5ef2aSThomas Huth /* 74xx TLB management */ 6836fcf5ef2aSThomas Huth 6837fcf5ef2aSThomas Huth /* tlbld */ 6838fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6839fcf5ef2aSThomas Huth { 6840fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6841fcf5ef2aSThomas Huth GEN_PRIV; 6842fcf5ef2aSThomas Huth #else 6843fcf5ef2aSThomas Huth CHK_SV; 6844fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6845fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6846fcf5ef2aSThomas Huth } 6847fcf5ef2aSThomas Huth 6848fcf5ef2aSThomas Huth /* tlbli */ 6849fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6850fcf5ef2aSThomas Huth { 6851fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6852fcf5ef2aSThomas Huth GEN_PRIV; 6853fcf5ef2aSThomas Huth #else 6854fcf5ef2aSThomas Huth CHK_SV; 6855fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6856fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6857fcf5ef2aSThomas Huth } 6858fcf5ef2aSThomas Huth 6859fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6860fcf5ef2aSThomas Huth 6861fcf5ef2aSThomas Huth /* clf */ 6862fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6863fcf5ef2aSThomas Huth { 6864fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6865fcf5ef2aSThomas Huth } 6866fcf5ef2aSThomas Huth 6867fcf5ef2aSThomas Huth /* cli */ 6868fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6869fcf5ef2aSThomas Huth { 6870fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6871fcf5ef2aSThomas Huth GEN_PRIV; 6872fcf5ef2aSThomas Huth #else 6873fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6874fcf5ef2aSThomas Huth CHK_SV; 6875fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6876fcf5ef2aSThomas Huth } 6877fcf5ef2aSThomas Huth 6878fcf5ef2aSThomas Huth /* dclst */ 6879fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6880fcf5ef2aSThomas Huth { 6881fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6882fcf5ef2aSThomas Huth } 6883fcf5ef2aSThomas Huth 6884fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6885fcf5ef2aSThomas Huth { 6886fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6887fcf5ef2aSThomas Huth GEN_PRIV; 6888fcf5ef2aSThomas Huth #else 6889fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6890fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6891fcf5ef2aSThomas Huth TCGv t0; 6892fcf5ef2aSThomas Huth 6893fcf5ef2aSThomas Huth CHK_SV; 6894fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6895fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6896e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6897fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6898fcf5ef2aSThomas Huth tcg_temp_free(t0); 6899efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6900fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6901efe843d8SDavid Gibson } 6902fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6903fcf5ef2aSThomas Huth } 6904fcf5ef2aSThomas Huth 6905fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6906fcf5ef2aSThomas Huth { 6907fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6908fcf5ef2aSThomas Huth GEN_PRIV; 6909fcf5ef2aSThomas Huth #else 6910fcf5ef2aSThomas Huth TCGv t0; 6911fcf5ef2aSThomas Huth 6912fcf5ef2aSThomas Huth CHK_SV; 6913fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6914fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6915fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6916fcf5ef2aSThomas Huth tcg_temp_free(t0); 6917fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6918fcf5ef2aSThomas Huth } 6919fcf5ef2aSThomas Huth 6920fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6921fcf5ef2aSThomas Huth { 6922fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6923fcf5ef2aSThomas Huth GEN_PRIV; 6924fcf5ef2aSThomas Huth #else 6925fcf5ef2aSThomas Huth CHK_SV; 6926fcf5ef2aSThomas Huth 6927fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 6928fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6929fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6930fcf5ef2aSThomas Huth } 6931fcf5ef2aSThomas Huth 6932fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6933fcf5ef2aSThomas Huth 6934fcf5ef2aSThomas Huth /* BookE specific instructions */ 6935fcf5ef2aSThomas Huth 6936fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6937fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6938fcf5ef2aSThomas Huth { 6939fcf5ef2aSThomas Huth /* XXX: TODO */ 6940fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6941fcf5ef2aSThomas Huth } 6942fcf5ef2aSThomas Huth 6943fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6944fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6945fcf5ef2aSThomas Huth { 6946fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6947fcf5ef2aSThomas Huth GEN_PRIV; 6948fcf5ef2aSThomas Huth #else 6949fcf5ef2aSThomas Huth TCGv t0; 6950fcf5ef2aSThomas Huth 6951fcf5ef2aSThomas Huth CHK_SV; 6952fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6953fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6954fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6955fcf5ef2aSThomas Huth tcg_temp_free(t0); 6956fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6957fcf5ef2aSThomas Huth } 6958fcf5ef2aSThomas Huth 6959fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6960fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6961fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6962fcf5ef2aSThomas Huth { 6963fcf5ef2aSThomas Huth TCGv t0, t1; 6964fcf5ef2aSThomas Huth 6965fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6966fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6967fcf5ef2aSThomas Huth 6968fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6969fcf5ef2aSThomas Huth case 0x05: 6970fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6971fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6972fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6973fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6974fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6975fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6976fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6977fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6978fcf5ef2aSThomas Huth break; 6979fcf5ef2aSThomas Huth case 0x04: 6980fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6981fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6982fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6983fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6984fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6985fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6986fcf5ef2aSThomas Huth break; 6987fcf5ef2aSThomas Huth case 0x01: 6988fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6989fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6990fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6991fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6992fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6993fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6994fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6995fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6996fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6997fcf5ef2aSThomas Huth break; 6998fcf5ef2aSThomas Huth case 0x00: 6999fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 7000fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 7001fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7002fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 7003fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 7004fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 7005fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 7006fcf5ef2aSThomas Huth break; 7007fcf5ef2aSThomas Huth case 0x0D: 7008fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 7009fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 7010fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 7011fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 7012fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7013fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 7014fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 7015fcf5ef2aSThomas Huth break; 7016fcf5ef2aSThomas Huth case 0x0C: 7017fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 7018fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 7019fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7020fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 7021fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 7022fcf5ef2aSThomas Huth break; 7023fcf5ef2aSThomas Huth } 7024fcf5ef2aSThomas Huth if (opc2 & 0x04) { 7025fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 7026fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 7027fcf5ef2aSThomas Huth if (opc2 & 0x02) { 7028fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 7029fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 7030fcf5ef2aSThomas Huth } else { 7031fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 7032fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 7033fcf5ef2aSThomas Huth } 7034fcf5ef2aSThomas Huth 7035fcf5ef2aSThomas Huth if (opc3 & 0x12) { 7036fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 7037fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7038fcf5ef2aSThomas Huth 7039fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7040fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 7041fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 7042fcf5ef2aSThomas Huth } 7043fcf5ef2aSThomas Huth if (opc3 & 0x01) { 7044fcf5ef2aSThomas Huth /* Signed */ 7045fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 7046fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 7047fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 7048fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 7049fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7050fcf5ef2aSThomas Huth /* Saturate */ 7051fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 7052fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 7053fcf5ef2aSThomas Huth } 7054fcf5ef2aSThomas Huth } else { 7055fcf5ef2aSThomas Huth /* Unsigned */ 7056fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 7057fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7058fcf5ef2aSThomas Huth /* Saturate */ 7059fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 7060fcf5ef2aSThomas Huth } 7061fcf5ef2aSThomas Huth } 7062fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7063fcf5ef2aSThomas Huth /* Check overflow */ 7064fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 7065fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 7066fcf5ef2aSThomas Huth } 7067fcf5ef2aSThomas Huth gen_set_label(l1); 7068fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 7069fcf5ef2aSThomas Huth } 7070fcf5ef2aSThomas Huth } else { 7071fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 7072fcf5ef2aSThomas Huth } 7073fcf5ef2aSThomas Huth tcg_temp_free(t0); 7074fcf5ef2aSThomas Huth tcg_temp_free(t1); 7075fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 7076fcf5ef2aSThomas Huth /* Update Rc0 */ 7077fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 7078fcf5ef2aSThomas Huth } 7079fcf5ef2aSThomas Huth } 7080fcf5ef2aSThomas Huth 7081fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7082fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 7083fcf5ef2aSThomas Huth { \ 7084fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 7085fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 7086fcf5ef2aSThomas Huth } 7087fcf5ef2aSThomas Huth 7088fcf5ef2aSThomas Huth /* macchw - macchw. */ 7089fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 7090fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 7091fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 7092fcf5ef2aSThomas Huth /* macchws - macchws. */ 7093fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 7094fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 7095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 7096fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 7097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 7098fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 7099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 7100fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 7101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 7102fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 7103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 7104fcf5ef2aSThomas Huth /* machhw - machhw. */ 7105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 7106fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 7107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 7108fcf5ef2aSThomas Huth /* machhws - machhws. */ 7109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 7110fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 7111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 7112fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 7113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 7114fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 7115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 7116fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 7117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 7118fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 7119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 7120fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 7121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 7122fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 7123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 7124fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 7125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 7126fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 7127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 7128fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 7129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 7130fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 7131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 7132fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 7133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 7134fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 7135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 7136fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 7137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 7138fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 7139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 7140fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 7141fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 7142fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 7143fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 7144fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 7145fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 7146fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 7147fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 7148fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 7149fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 7150fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 7151fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 7152fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 7153fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 7154fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 7155fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 7156fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 7157fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 7158fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 7159fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 7160fcf5ef2aSThomas Huth 7161fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 7162fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 7163fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 7164fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 7165fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 7166fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 7167fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7168fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 7169fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7170fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 7171fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7172fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 7173fcf5ef2aSThomas Huth 7174fcf5ef2aSThomas Huth /* mfdcr */ 7175fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 7176fcf5ef2aSThomas Huth { 7177fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7178fcf5ef2aSThomas Huth GEN_PRIV; 7179fcf5ef2aSThomas Huth #else 7180fcf5ef2aSThomas Huth TCGv dcrn; 7181fcf5ef2aSThomas Huth 7182fcf5ef2aSThomas Huth CHK_SV; 7183fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7184fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 7185fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7186fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7187fcf5ef2aSThomas Huth } 7188fcf5ef2aSThomas Huth 7189fcf5ef2aSThomas Huth /* mtdcr */ 7190fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 7191fcf5ef2aSThomas Huth { 7192fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7193fcf5ef2aSThomas Huth GEN_PRIV; 7194fcf5ef2aSThomas Huth #else 7195fcf5ef2aSThomas Huth TCGv dcrn; 7196fcf5ef2aSThomas Huth 7197fcf5ef2aSThomas Huth CHK_SV; 7198fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7199fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 7200fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7201fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7202fcf5ef2aSThomas Huth } 7203fcf5ef2aSThomas Huth 7204fcf5ef2aSThomas Huth /* mfdcrx */ 7205fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7206fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 7207fcf5ef2aSThomas Huth { 7208fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7209fcf5ef2aSThomas Huth GEN_PRIV; 7210fcf5ef2aSThomas Huth #else 7211fcf5ef2aSThomas Huth CHK_SV; 7212fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7213fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7214fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7215fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7216fcf5ef2aSThomas Huth } 7217fcf5ef2aSThomas Huth 7218fcf5ef2aSThomas Huth /* mtdcrx */ 7219fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7220fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 7221fcf5ef2aSThomas Huth { 7222fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7223fcf5ef2aSThomas Huth GEN_PRIV; 7224fcf5ef2aSThomas Huth #else 7225fcf5ef2aSThomas Huth CHK_SV; 7226fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7227fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7228fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7229fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7230fcf5ef2aSThomas Huth } 7231fcf5ef2aSThomas Huth 7232fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 7233fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 7234fcf5ef2aSThomas Huth { 7235fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7236fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7237fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7238fcf5ef2aSThomas Huth } 7239fcf5ef2aSThomas Huth 7240fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 7241fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 7242fcf5ef2aSThomas Huth { 7243fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7244fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7245fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7246fcf5ef2aSThomas Huth } 7247fcf5ef2aSThomas Huth 7248fcf5ef2aSThomas Huth /* dccci */ 7249fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 7250fcf5ef2aSThomas Huth { 7251fcf5ef2aSThomas Huth CHK_SV; 7252fcf5ef2aSThomas Huth /* interpreted as no-op */ 7253fcf5ef2aSThomas Huth } 7254fcf5ef2aSThomas Huth 7255fcf5ef2aSThomas Huth /* dcread */ 7256fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 7257fcf5ef2aSThomas Huth { 7258fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7259fcf5ef2aSThomas Huth GEN_PRIV; 7260fcf5ef2aSThomas Huth #else 7261fcf5ef2aSThomas Huth TCGv EA, val; 7262fcf5ef2aSThomas Huth 7263fcf5ef2aSThomas Huth CHK_SV; 7264fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 7265fcf5ef2aSThomas Huth EA = tcg_temp_new(); 7266fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 7267fcf5ef2aSThomas Huth val = tcg_temp_new(); 7268fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 7269fcf5ef2aSThomas Huth tcg_temp_free(val); 7270fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 7271fcf5ef2aSThomas Huth tcg_temp_free(EA); 7272fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7273fcf5ef2aSThomas Huth } 7274fcf5ef2aSThomas Huth 7275fcf5ef2aSThomas Huth /* icbt */ 7276fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 7277fcf5ef2aSThomas Huth { 7278efe843d8SDavid Gibson /* 7279efe843d8SDavid Gibson * interpreted as no-op 7280efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7281efe843d8SDavid Gibson * does not generate any exception 7282fcf5ef2aSThomas Huth */ 7283fcf5ef2aSThomas Huth } 7284fcf5ef2aSThomas Huth 7285fcf5ef2aSThomas Huth /* iccci */ 7286fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 7287fcf5ef2aSThomas Huth { 7288fcf5ef2aSThomas Huth CHK_SV; 7289fcf5ef2aSThomas Huth /* interpreted as no-op */ 7290fcf5ef2aSThomas Huth } 7291fcf5ef2aSThomas Huth 7292fcf5ef2aSThomas Huth /* icread */ 7293fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 7294fcf5ef2aSThomas Huth { 7295fcf5ef2aSThomas Huth CHK_SV; 7296fcf5ef2aSThomas Huth /* interpreted as no-op */ 7297fcf5ef2aSThomas Huth } 7298fcf5ef2aSThomas Huth 7299fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 7300fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 7301fcf5ef2aSThomas Huth { 7302fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7303fcf5ef2aSThomas Huth GEN_PRIV; 7304fcf5ef2aSThomas Huth #else 7305fcf5ef2aSThomas Huth CHK_SV; 7306fcf5ef2aSThomas Huth /* Restore CPU state */ 7307fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 7308fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7309fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7310fcf5ef2aSThomas Huth } 7311fcf5ef2aSThomas Huth 7312fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 7313fcf5ef2aSThomas Huth { 7314fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7315fcf5ef2aSThomas Huth GEN_PRIV; 7316fcf5ef2aSThomas Huth #else 7317fcf5ef2aSThomas Huth CHK_SV; 7318fcf5ef2aSThomas Huth /* Restore CPU state */ 7319fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 7320fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7321fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7322fcf5ef2aSThomas Huth } 7323fcf5ef2aSThomas Huth 7324fcf5ef2aSThomas Huth /* BookE specific */ 7325fcf5ef2aSThomas Huth 7326fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7327fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 7328fcf5ef2aSThomas Huth { 7329fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7330fcf5ef2aSThomas Huth GEN_PRIV; 7331fcf5ef2aSThomas Huth #else 7332fcf5ef2aSThomas Huth CHK_SV; 7333fcf5ef2aSThomas Huth /* Restore CPU state */ 7334fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 7335fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7336fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7337fcf5ef2aSThomas Huth } 7338fcf5ef2aSThomas Huth 7339fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7340fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 7341fcf5ef2aSThomas Huth { 7342fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7343fcf5ef2aSThomas Huth GEN_PRIV; 7344fcf5ef2aSThomas Huth #else 7345fcf5ef2aSThomas Huth CHK_SV; 7346fcf5ef2aSThomas Huth /* Restore CPU state */ 7347fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 7348fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7349fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7350fcf5ef2aSThomas Huth } 7351fcf5ef2aSThomas Huth 7352fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7353fcf5ef2aSThomas Huth 7354fcf5ef2aSThomas Huth /* tlbre */ 7355fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7356fcf5ef2aSThomas Huth { 7357fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7358fcf5ef2aSThomas Huth GEN_PRIV; 7359fcf5ef2aSThomas Huth #else 7360fcf5ef2aSThomas Huth CHK_SV; 7361fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7362fcf5ef2aSThomas Huth case 0: 7363fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7364fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7365fcf5ef2aSThomas Huth break; 7366fcf5ef2aSThomas Huth case 1: 7367fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7368fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7369fcf5ef2aSThomas Huth break; 7370fcf5ef2aSThomas Huth default: 7371fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7372fcf5ef2aSThomas Huth break; 7373fcf5ef2aSThomas Huth } 7374fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7375fcf5ef2aSThomas Huth } 7376fcf5ef2aSThomas Huth 7377fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7378fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7379fcf5ef2aSThomas Huth { 7380fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7381fcf5ef2aSThomas Huth GEN_PRIV; 7382fcf5ef2aSThomas Huth #else 7383fcf5ef2aSThomas Huth TCGv t0; 7384fcf5ef2aSThomas Huth 7385fcf5ef2aSThomas Huth CHK_SV; 7386fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7387fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7388fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7389fcf5ef2aSThomas Huth tcg_temp_free(t0); 7390fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7391fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7392fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7393fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7394fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7395fcf5ef2aSThomas Huth gen_set_label(l1); 7396fcf5ef2aSThomas Huth } 7397fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7398fcf5ef2aSThomas Huth } 7399fcf5ef2aSThomas Huth 7400fcf5ef2aSThomas Huth /* tlbwe */ 7401fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7402fcf5ef2aSThomas Huth { 7403fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7404fcf5ef2aSThomas Huth GEN_PRIV; 7405fcf5ef2aSThomas Huth #else 7406fcf5ef2aSThomas Huth CHK_SV; 7407fcf5ef2aSThomas Huth 7408fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7409fcf5ef2aSThomas Huth case 0: 7410fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7411fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7412fcf5ef2aSThomas Huth break; 7413fcf5ef2aSThomas Huth case 1: 7414fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7415fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7416fcf5ef2aSThomas Huth break; 7417fcf5ef2aSThomas Huth default: 7418fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7419fcf5ef2aSThomas Huth break; 7420fcf5ef2aSThomas Huth } 7421fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7422fcf5ef2aSThomas Huth } 7423fcf5ef2aSThomas Huth 7424fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7425fcf5ef2aSThomas Huth 7426fcf5ef2aSThomas Huth /* tlbre */ 7427fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7428fcf5ef2aSThomas Huth { 7429fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7430fcf5ef2aSThomas Huth GEN_PRIV; 7431fcf5ef2aSThomas Huth #else 7432fcf5ef2aSThomas Huth CHK_SV; 7433fcf5ef2aSThomas Huth 7434fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7435fcf5ef2aSThomas Huth case 0: 7436fcf5ef2aSThomas Huth case 1: 7437fcf5ef2aSThomas Huth case 2: 7438fcf5ef2aSThomas Huth { 7439fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7440fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7441fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7442fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7443fcf5ef2aSThomas Huth } 7444fcf5ef2aSThomas Huth break; 7445fcf5ef2aSThomas Huth default: 7446fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7447fcf5ef2aSThomas Huth break; 7448fcf5ef2aSThomas Huth } 7449fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7450fcf5ef2aSThomas Huth } 7451fcf5ef2aSThomas Huth 7452fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7453fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7454fcf5ef2aSThomas Huth { 7455fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7456fcf5ef2aSThomas Huth GEN_PRIV; 7457fcf5ef2aSThomas Huth #else 7458fcf5ef2aSThomas Huth TCGv t0; 7459fcf5ef2aSThomas Huth 7460fcf5ef2aSThomas Huth CHK_SV; 7461fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7462fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7463fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7464fcf5ef2aSThomas Huth tcg_temp_free(t0); 7465fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7466fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7467fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7468fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7469fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7470fcf5ef2aSThomas Huth gen_set_label(l1); 7471fcf5ef2aSThomas Huth } 7472fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7473fcf5ef2aSThomas Huth } 7474fcf5ef2aSThomas Huth 7475fcf5ef2aSThomas Huth /* tlbwe */ 7476fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7477fcf5ef2aSThomas Huth { 7478fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7479fcf5ef2aSThomas Huth GEN_PRIV; 7480fcf5ef2aSThomas Huth #else 7481fcf5ef2aSThomas Huth CHK_SV; 7482fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7483fcf5ef2aSThomas Huth case 0: 7484fcf5ef2aSThomas Huth case 1: 7485fcf5ef2aSThomas Huth case 2: 7486fcf5ef2aSThomas Huth { 7487fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7488fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7489fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7490fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7491fcf5ef2aSThomas Huth } 7492fcf5ef2aSThomas Huth break; 7493fcf5ef2aSThomas Huth default: 7494fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7495fcf5ef2aSThomas Huth break; 7496fcf5ef2aSThomas Huth } 7497fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7498fcf5ef2aSThomas Huth } 7499fcf5ef2aSThomas Huth 7500fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7501fcf5ef2aSThomas Huth 7502fcf5ef2aSThomas Huth /* tlbre */ 7503fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7504fcf5ef2aSThomas Huth { 7505fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7506fcf5ef2aSThomas Huth GEN_PRIV; 7507fcf5ef2aSThomas Huth #else 7508fcf5ef2aSThomas Huth CHK_SV; 7509fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7510fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7511fcf5ef2aSThomas Huth } 7512fcf5ef2aSThomas Huth 7513fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7514fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7515fcf5ef2aSThomas Huth { 7516fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7517fcf5ef2aSThomas Huth GEN_PRIV; 7518fcf5ef2aSThomas Huth #else 7519fcf5ef2aSThomas Huth TCGv t0; 7520fcf5ef2aSThomas Huth 7521fcf5ef2aSThomas Huth CHK_SV; 7522fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7523fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7524fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7525fcf5ef2aSThomas Huth } else { 7526fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7527fcf5ef2aSThomas Huth } 7528fcf5ef2aSThomas Huth 7529fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7530fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7531fcf5ef2aSThomas Huth tcg_temp_free(t0); 7532fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7533fcf5ef2aSThomas Huth } 7534fcf5ef2aSThomas Huth 7535fcf5ef2aSThomas Huth /* tlbwe */ 7536fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7537fcf5ef2aSThomas Huth { 7538fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7539fcf5ef2aSThomas Huth GEN_PRIV; 7540fcf5ef2aSThomas Huth #else 7541fcf5ef2aSThomas Huth CHK_SV; 7542fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7543fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7544fcf5ef2aSThomas Huth } 7545fcf5ef2aSThomas Huth 7546fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7547fcf5ef2aSThomas Huth { 7548fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7549fcf5ef2aSThomas Huth GEN_PRIV; 7550fcf5ef2aSThomas Huth #else 7551fcf5ef2aSThomas Huth TCGv t0; 7552fcf5ef2aSThomas Huth 7553fcf5ef2aSThomas Huth CHK_SV; 7554fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7555fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7556fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7557fcf5ef2aSThomas Huth tcg_temp_free(t0); 7558fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7559fcf5ef2aSThomas Huth } 7560fcf5ef2aSThomas Huth 7561fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7562fcf5ef2aSThomas Huth { 7563fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7564fcf5ef2aSThomas Huth GEN_PRIV; 7565fcf5ef2aSThomas Huth #else 7566fcf5ef2aSThomas Huth TCGv t0; 7567fcf5ef2aSThomas Huth 7568fcf5ef2aSThomas Huth CHK_SV; 7569fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7570fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7571fcf5ef2aSThomas Huth 7572fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7573fcf5ef2aSThomas Huth case 0: 7574fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7575fcf5ef2aSThomas Huth break; 7576fcf5ef2aSThomas Huth case 1: 7577fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7578fcf5ef2aSThomas Huth break; 7579fcf5ef2aSThomas Huth case 3: 7580fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7581fcf5ef2aSThomas Huth break; 7582fcf5ef2aSThomas Huth default: 7583fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7584fcf5ef2aSThomas Huth break; 7585fcf5ef2aSThomas Huth } 7586fcf5ef2aSThomas Huth 7587fcf5ef2aSThomas Huth tcg_temp_free(t0); 7588fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7589fcf5ef2aSThomas Huth } 7590fcf5ef2aSThomas Huth 7591fcf5ef2aSThomas Huth 7592fcf5ef2aSThomas Huth /* wrtee */ 7593fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7594fcf5ef2aSThomas Huth { 7595fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7596fcf5ef2aSThomas Huth GEN_PRIV; 7597fcf5ef2aSThomas Huth #else 7598fcf5ef2aSThomas Huth TCGv t0; 7599fcf5ef2aSThomas Huth 7600fcf5ef2aSThomas Huth CHK_SV; 7601fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7602fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7603fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7604fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7605fcf5ef2aSThomas Huth tcg_temp_free(t0); 7606efe843d8SDavid Gibson /* 7607efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7608efe843d8SDavid Gibson * just set msr_ee to 1 7609fcf5ef2aSThomas Huth */ 7610fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7611fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7612fcf5ef2aSThomas Huth } 7613fcf5ef2aSThomas Huth 7614fcf5ef2aSThomas Huth /* wrteei */ 7615fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7616fcf5ef2aSThomas Huth { 7617fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7618fcf5ef2aSThomas Huth GEN_PRIV; 7619fcf5ef2aSThomas Huth #else 7620fcf5ef2aSThomas Huth CHK_SV; 7621fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7622fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7623fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7624fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7625fcf5ef2aSThomas Huth } else { 7626fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7627fcf5ef2aSThomas Huth } 7628fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7629fcf5ef2aSThomas Huth } 7630fcf5ef2aSThomas Huth 7631fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7632fcf5ef2aSThomas Huth 7633fcf5ef2aSThomas Huth /* dlmzb */ 7634fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7635fcf5ef2aSThomas Huth { 7636fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7637fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7638fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7639fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7640fcf5ef2aSThomas Huth } 7641fcf5ef2aSThomas Huth 7642fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7643fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7644fcf5ef2aSThomas Huth { 7645fcf5ef2aSThomas Huth /* interpreted as no-op */ 7646fcf5ef2aSThomas Huth } 7647fcf5ef2aSThomas Huth 7648fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7649fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7650fcf5ef2aSThomas Huth { 765127a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 765227a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 765327a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 765427a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 765527a3ea7eSBALATON Zoltan } 765627a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7657fcf5ef2aSThomas Huth } 7658fcf5ef2aSThomas Huth 7659fcf5ef2aSThomas Huth /* icbt */ 7660fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7661fcf5ef2aSThomas Huth { 7662efe843d8SDavid Gibson /* 7663efe843d8SDavid Gibson * interpreted as no-op 7664efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7665efe843d8SDavid Gibson * does not generate any exception 7666fcf5ef2aSThomas Huth */ 7667fcf5ef2aSThomas Huth } 7668fcf5ef2aSThomas Huth 7669fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7670fcf5ef2aSThomas Huth 7671fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7672fcf5ef2aSThomas Huth { 7673fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7674fcf5ef2aSThomas Huth GEN_PRIV; 7675fcf5ef2aSThomas Huth #else 7676ebca5e6dSCédric Le Goater CHK_HV; 7677d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76787af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76797af1e7b0SCédric Le Goater } else { 7680fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76817af1e7b0SCédric Le Goater } 7682fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7683fcf5ef2aSThomas Huth } 7684fcf5ef2aSThomas Huth 7685fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7686fcf5ef2aSThomas Huth { 7687fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7688fcf5ef2aSThomas Huth GEN_PRIV; 7689fcf5ef2aSThomas Huth #else 7690ebca5e6dSCédric Le Goater CHK_HV; 7691d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76927af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76937af1e7b0SCédric Le Goater } else { 7694fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76957af1e7b0SCédric Le Goater } 7696fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7697fcf5ef2aSThomas Huth } 7698fcf5ef2aSThomas Huth 76995ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 77005ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 77015ba7ba1dSCédric Le Goater { 77025ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 77035ba7ba1dSCédric Le Goater GEN_PRIV; 77045ba7ba1dSCédric Le Goater #else 77055ba7ba1dSCédric Le Goater CHK_SV; 77065ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77075ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77085ba7ba1dSCédric Le Goater } 77095ba7ba1dSCédric Le Goater 77105ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 77115ba7ba1dSCédric Le Goater { 77125ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 77135ba7ba1dSCédric Le Goater GEN_PRIV; 77145ba7ba1dSCédric Le Goater #else 77155ba7ba1dSCédric Le Goater CHK_SV; 77165ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77175ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77185ba7ba1dSCédric Le Goater } 77195ba7ba1dSCédric Le Goater #endif 77205ba7ba1dSCédric Le Goater 77217af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 77227af1e7b0SCédric Le Goater { 77237af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 77247af1e7b0SCédric Le Goater GEN_PRIV; 77257af1e7b0SCédric Le Goater #else 77267af1e7b0SCédric Le Goater CHK_HV; 77277af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77287af1e7b0SCédric Le Goater /* interpreted as no-op */ 77297af1e7b0SCédric Le Goater } 7730fcf5ef2aSThomas Huth 7731fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7732fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7733fcf5ef2aSThomas Huth { 7734fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7735fcf5ef2aSThomas Huth 7736fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7737fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7738fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7739fcf5ef2aSThomas Huth } 7740fcf5ef2aSThomas Huth 7741fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7742fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7743fcf5ef2aSThomas Huth { 7744fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7745fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7746fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7747fcf5ef2aSThomas Huth 7748fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7749fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7750fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7751fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7752fcf5ef2aSThomas Huth } else { 7753fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7754fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7755fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7756fcf5ef2aSThomas Huth } 7757fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7758fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7759fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7760fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7761fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7762fcf5ef2aSThomas Huth } 7763fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7764fcf5ef2aSThomas Huth 7765fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7766fcf5ef2aSThomas Huth { 7767fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7768fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7769fcf5ef2aSThomas Huth return; 7770fcf5ef2aSThomas Huth } 7771fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7772fcf5ef2aSThomas Huth } 7773fcf5ef2aSThomas Huth 7774fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7775fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7776fcf5ef2aSThomas Huth { \ 7777fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7778fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7779fcf5ef2aSThomas Huth return; \ 7780fcf5ef2aSThomas Huth } \ 7781efe843d8SDavid Gibson /* \ 7782efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7783fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7784fcf5ef2aSThomas Huth * \ 7785fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7786fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7787fcf5ef2aSThomas Huth */ \ 7788fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7789fcf5ef2aSThomas Huth } 7790fcf5ef2aSThomas Huth 7791fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7792fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7793fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7794fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7795fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7796fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7797fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7798efe843d8SDavid Gibson 7799b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7800b8b4576eSSuraj Jitindar Singh { 7801efe843d8SDavid Gibson /* Do Nothing */ 7802b8b4576eSSuraj Jitindar Singh } 7803fcf5ef2aSThomas Huth 780480b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 780580b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 780680b8c1eeSNikunj A Dadhania { \ 7807efe843d8SDavid Gibson /* \ 7808efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7809efe843d8SDavid Gibson * implementation of the copy paste facility \ 781080b8c1eeSNikunj A Dadhania */ \ 781180b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 781280b8c1eeSNikunj A Dadhania } 781380b8c1eeSNikunj A Dadhania 781480b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 781580b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 781680b8c1eeSNikunj A Dadhania 7817fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7818fcf5ef2aSThomas Huth { 7819fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7820fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7821fcf5ef2aSThomas Huth return; 7822fcf5ef2aSThomas Huth } 7823efe843d8SDavid Gibson /* 7824efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7825efe843d8SDavid Gibson * simple: 7826fcf5ef2aSThomas Huth * 7827fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7828fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7829fcf5ef2aSThomas Huth */ 7830fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7831fcf5ef2aSThomas Huth } 7832fcf5ef2aSThomas Huth 7833fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7834fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7835fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7836fcf5ef2aSThomas Huth { \ 7837fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7838fcf5ef2aSThomas Huth } 7839fcf5ef2aSThomas Huth 7840fcf5ef2aSThomas Huth #else 7841fcf5ef2aSThomas Huth 7842fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7843fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7844fcf5ef2aSThomas Huth { \ 7845fcf5ef2aSThomas Huth CHK_SV; \ 7846fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7847fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7848fcf5ef2aSThomas Huth return; \ 7849fcf5ef2aSThomas Huth } \ 7850efe843d8SDavid Gibson /* \ 7851efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7852fcf5ef2aSThomas Huth * simple: \ 7853fcf5ef2aSThomas Huth * \ 7854fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7855fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7856fcf5ef2aSThomas Huth */ \ 7857fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7858fcf5ef2aSThomas Huth } 7859fcf5ef2aSThomas Huth 7860fcf5ef2aSThomas Huth #endif 7861fcf5ef2aSThomas Huth 7862fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7863fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7864fcf5ef2aSThomas Huth 78651a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 78661a404c91SMark Cave-Ayland { 7867e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 78681a404c91SMark Cave-Ayland } 78691a404c91SMark Cave-Ayland 78701a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 78711a404c91SMark Cave-Ayland { 7872e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 78731a404c91SMark Cave-Ayland } 78741a404c91SMark Cave-Ayland 7875c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7876c4a18dbfSMark Cave-Ayland { 787737da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7878c4a18dbfSMark Cave-Ayland } 7879c4a18dbfSMark Cave-Ayland 7880c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7881c4a18dbfSMark Cave-Ayland { 788237da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7883c4a18dbfSMark Cave-Ayland } 7884c4a18dbfSMark Cave-Ayland 7885139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7886fcf5ef2aSThomas Huth 7887139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7888fcf5ef2aSThomas Huth 7889139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7890fcf5ef2aSThomas Huth 7891139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7892fcf5ef2aSThomas Huth 7893139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7894fcf5ef2aSThomas Huth 78955cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 78965cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 78975cb091a4SNikunj A Dadhania { 78985cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 78995cb091a4SNikunj A Dadhania case 0: /* lfdp */ 79005cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 79015cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 79025cb091a4SNikunj A Dadhania } 79035cb091a4SNikunj A Dadhania break; 79045cb091a4SNikunj A Dadhania case 2: /* lxsd */ 79055cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79065cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 79075cb091a4SNikunj A Dadhania } 79085cb091a4SNikunj A Dadhania break; 79095cb091a4SNikunj A Dadhania case 3: /* lxssp */ 79105cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79115cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 79125cb091a4SNikunj A Dadhania } 79135cb091a4SNikunj A Dadhania break; 79145cb091a4SNikunj A Dadhania } 79155cb091a4SNikunj A Dadhania return gen_invalid(ctx); 79165cb091a4SNikunj A Dadhania } 79175cb091a4SNikunj A Dadhania 7918d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7919e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7920e3001664SNikunj A Dadhania { 7921e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7922e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7923e3001664SNikunj A Dadhania case 1: /* lxv */ 7924d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7925d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7926d59ba583SNikunj A Dadhania } 7927e3001664SNikunj A Dadhania break; 7928e3001664SNikunj A Dadhania case 5: /* stxv */ 7929d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7930d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7931d59ba583SNikunj A Dadhania } 7932e3001664SNikunj A Dadhania break; 7933e3001664SNikunj A Dadhania } 7934e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7935e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7936e3001664SNikunj A Dadhania case 0: /* stfdp */ 7937e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7938e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7939e3001664SNikunj A Dadhania } 7940e3001664SNikunj A Dadhania break; 7941e3001664SNikunj A Dadhania case 2: /* stxsd */ 7942e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7943e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7944e3001664SNikunj A Dadhania } 7945e3001664SNikunj A Dadhania break; 7946e3001664SNikunj A Dadhania case 3: /* stxssp */ 7947e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7948e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7949e3001664SNikunj A Dadhania } 7950e3001664SNikunj A Dadhania break; 7951e3001664SNikunj A Dadhania } 7952e3001664SNikunj A Dadhania } 7953e3001664SNikunj A Dadhania return gen_invalid(ctx); 7954e3001664SNikunj A Dadhania } 7955e3001664SNikunj A Dadhania 79569d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79579d69cfa2SLijun Pan /* brd */ 79589d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 79599d69cfa2SLijun Pan { 79609d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79619d69cfa2SLijun Pan } 79629d69cfa2SLijun Pan 79639d69cfa2SLijun Pan /* brw */ 79649d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 79659d69cfa2SLijun Pan { 79669d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79679d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 79689d69cfa2SLijun Pan 79699d69cfa2SLijun Pan } 79709d69cfa2SLijun Pan 79719d69cfa2SLijun Pan /* brh */ 79729d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 79739d69cfa2SLijun Pan { 79749d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 79759d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 79769d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 79779d69cfa2SLijun Pan 79789d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 79799d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 79809d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 79819d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 79829d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 79839d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 79849d69cfa2SLijun Pan 79859d69cfa2SLijun Pan tcg_temp_free_i64(t0); 79869d69cfa2SLijun Pan tcg_temp_free_i64(t1); 79879d69cfa2SLijun Pan tcg_temp_free_i64(t2); 79889d69cfa2SLijun Pan } 79899d69cfa2SLijun Pan #endif 79909d69cfa2SLijun Pan 7991fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 79929d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79939d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 79949d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 79959d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 79969d69cfa2SLijun Pan #endif 7997fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7998fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7999fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 8000fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 8001fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 8002fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8003fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 8004fcf5ef2aSThomas Huth #endif 8005fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 8006fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 8007fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 8008fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8009fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8010fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8011fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8012fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 8013fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 8014fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 8015fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 8016fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 8017fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8018fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8019fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 8020fcf5ef2aSThomas Huth #endif 8021fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 8022fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 8023fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8024fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8025fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8026fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 8027fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 802880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 8029b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 803080b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 8031fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 8032fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 8033fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8034fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8035fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8036fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8037fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 8038fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 8039fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 8040fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8041fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 8042fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 8043fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 8044fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 8045fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 8046fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 8047fcf5ef2aSThomas Huth #endif 8048fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8049fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8050fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8051fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 8052fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 8053fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 8054fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 8055fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8056fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 8057fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 8058fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 8059fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 8060fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 8061fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 8062fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8063fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 8064fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8065fcf5ef2aSThomas Huth #endif 8066fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8067fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 8068fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 8069fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 8070fcf5ef2aSThomas Huth #endif 80715cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 80725cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8073d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 8074e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8075fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8076fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8077fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 8078fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 8079fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 8080fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 8081c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 8082fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 8083fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8084fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8085fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 8086a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 8087a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 8088fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8089fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8090fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 8091fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8092a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 8093a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 8094fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 8095fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 8096fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 8097fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 8098fcf5ef2aSThomas Huth #endif 8099fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 8100fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 8101c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 8102fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8103fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8104fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 8105fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 8106fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 8107fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 8108fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 8109fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8110fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 81113c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 81123c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81133c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81143c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81153c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 81163c89b8d6SNicholas Piggin #endif 8117cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8118fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8119fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8120fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8121fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8122fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 8123fcf5ef2aSThomas Huth #endif 81243c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81253c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 81263c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 8127fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 8128fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8129fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8130fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 8131fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 8132fcf5ef2aSThomas Huth #endif 8133fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 8134fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 8135fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 8136fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 8137fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 8138fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 8139fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8140fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 8141fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 8142b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 8143fcf5ef2aSThomas Huth #endif 8144fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 8145fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 8146fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 814750728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8148fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 8149fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 815050728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8151fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 815250728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8153fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 815450728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8155fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 8156fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 815750728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8158fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 815999d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 8160fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 8161fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 816250728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8163fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 8164fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 8165fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 8166fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 8167fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 8168fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8169fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 8170fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 8171fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8172fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 8173fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 8174fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8175fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 8176fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 8177fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 8178fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 8179fcf5ef2aSThomas Huth #endif 8180fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 8181efe843d8SDavid Gibson /* 8182efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 8183efe843d8SDavid Gibson * different ISA versions 8184efe843d8SDavid Gibson */ 8185fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 8186fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 8187c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 8188c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 8189fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 8190fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8191fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 8192fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 8193a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 819462d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8195fcf5ef2aSThomas Huth #endif 8196fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 8197fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 8198fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 8199fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 8200fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 8201fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 8202fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 8203fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 8204fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 8205fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 8206fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 8207fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8208fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 8209fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 8210fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 8211fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 8212fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 8213fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 8214fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 8215fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8216fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 8217fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 8218fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 8219fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 8220fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 8221fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 8222fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 8223fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 8224fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 8225fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 8226fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 8227fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 8228fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 8229fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 8230fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 8231fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 8232fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 8233fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 8234fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 8235fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 8236fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 8237fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 8238fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 8239fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 8240fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 8241fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 8242fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 8243fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 8244fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 8245fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8246fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8247fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 8248fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 8249fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8250fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8251fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 8252fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 8253fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 8254fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 8255fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 8256fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 8257fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 8258fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 8259fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 8260fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 8261fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 8262fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 8263fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 8264fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 8265fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 8266fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 8267fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 8268fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 8269fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 8270fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 8271fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 8272fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 8273fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 8274fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 8275fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 8276fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 8277fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8278fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 8279fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8280fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 8281fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8282fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 8283fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8284fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 8285fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8286fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 8287fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 8288fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 8289fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 82907af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 82917af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 8292fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8293fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8294fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8295fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8296fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 829727a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8298fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8299fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 83000c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 83010c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8302fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8303fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8304fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8305fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8306fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8307fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8308fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8309fcf5ef2aSThomas Huth PPC2_ISA300), 8310fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 83115ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 83125ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 83135ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 83145ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8315fcf5ef2aSThomas Huth #endif 8316fcf5ef2aSThomas Huth 8317fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8318fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8319fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8320fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8321fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8322fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8323fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8324fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8325fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8326fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8327fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8328fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8329fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8330fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8331fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 83324c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8333fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8334fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8335fcf5ef2aSThomas Huth 8336fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8337fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8338fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8339fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8340fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8341fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8342fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8343fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8344fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8345fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8346fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8347fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8348fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8349fcf5ef2aSThomas Huth 8350fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8351fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8352fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8353fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8354fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8355fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8356fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8357fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8358fcf5ef2aSThomas Huth 8359fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8360fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8361fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8362fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8363fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8364fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8365fcf5ef2aSThomas Huth 8366fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8367fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8368fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8369fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8370fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8371fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8372fcf5ef2aSThomas Huth #endif 8373fcf5ef2aSThomas Huth 8374fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8375fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8376fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8377fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8378fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8379fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8380fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8381fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8382fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8383fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8384fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8385fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8386fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8387fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8388fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8389fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8390fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8391fcf5ef2aSThomas Huth 8392fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8393fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8394fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8395fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8396fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8397fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8398fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8399fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8400fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8401fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8402fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8403fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8404fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8405fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8406fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8407fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8408fcf5ef2aSThomas Huth #endif 8409fcf5ef2aSThomas Huth 8410fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8411fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8412fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8413fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8414fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8415fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8416fcf5ef2aSThomas Huth PPC_64B) 8417fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8418fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8419fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8420fcf5ef2aSThomas Huth PPC_64B), \ 8421fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8422fcf5ef2aSThomas Huth PPC_64B), \ 8423fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8424fcf5ef2aSThomas Huth PPC_64B) 8425fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8426fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8427fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8428fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8429fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8430fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8431fcf5ef2aSThomas Huth #endif 8432fcf5ef2aSThomas Huth 8433fcf5ef2aSThomas Huth #undef GEN_LD 8434fcf5ef2aSThomas Huth #undef GEN_LDU 8435fcf5ef2aSThomas Huth #undef GEN_LDUX 8436fcf5ef2aSThomas Huth #undef GEN_LDX_E 8437fcf5ef2aSThomas Huth #undef GEN_LDS 8438fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 8439fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8440fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 8441fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 8442fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 8443fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8444fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8445fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8446fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 8447fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 8448fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 8449fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 8450fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 8451fcf5ef2aSThomas Huth 8452fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 8453fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 8454fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 8455fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 8456fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8457fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 8458fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 8459fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 8460fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 8461fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8462fcf5ef2aSThomas Huth 8463fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8464fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8465fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8466fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8467fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8468fcf5ef2aSThomas Huth #endif 8469fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8470fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8471fcf5ef2aSThomas Huth 847250728199SRoman Kapl /* External PID based load */ 847350728199SRoman Kapl #undef GEN_LDEPX 847450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 847550728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 847650728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 847750728199SRoman Kapl 847850728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 847950728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 848050728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 848150728199SRoman Kapl #if defined(TARGET_PPC64) 848250728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 848350728199SRoman Kapl #endif 848450728199SRoman Kapl 8485fcf5ef2aSThomas Huth #undef GEN_ST 8486fcf5ef2aSThomas Huth #undef GEN_STU 8487fcf5ef2aSThomas Huth #undef GEN_STUX 8488fcf5ef2aSThomas Huth #undef GEN_STX_E 8489fcf5ef2aSThomas Huth #undef GEN_STS 8490fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8491fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8492fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8493fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8494fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8495fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8496fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 84970123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8498fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8499fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8500fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8501fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8502fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8503fcf5ef2aSThomas Huth 8504fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8505fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8506fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8507fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8508fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8509fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8510fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8511fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8512fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8513fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8514fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8515fcf5ef2aSThomas Huth #endif 8516fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8517fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8518fcf5ef2aSThomas Huth 851950728199SRoman Kapl #undef GEN_STEPX 852050728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 852150728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 852250728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 852350728199SRoman Kapl 852450728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 852550728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 852650728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 852750728199SRoman Kapl #if defined(TARGET_PPC64) 852850728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 852950728199SRoman Kapl #endif 853050728199SRoman Kapl 8531fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8532fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8533fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8534fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8535fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8536fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8537fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8538fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8539fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8540fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8541fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8542fcf5ef2aSThomas Huth 8543fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8544fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8545fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8546fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8547fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8583fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8584fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8585fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8586fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8587fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8588fcf5ef2aSThomas Huth 8589fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8590fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8591fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8592fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8593fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8594fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8595fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8596fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8597fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8598fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8599fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8600fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8601fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8602fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8603fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8604fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8605fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8606fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8607fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8608fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8609fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8610fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8611fcf5ef2aSThomas Huth 8612139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8613fcf5ef2aSThomas Huth 8614139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8615fcf5ef2aSThomas Huth 8616139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8617fcf5ef2aSThomas Huth 8618139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8619fcf5ef2aSThomas Huth 8620139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8621fcf5ef2aSThomas Huth }; 8622fcf5ef2aSThomas Huth 8623fcf5ef2aSThomas Huth #include "helper_regs.h" 8624139c1837SPaolo Bonzini #include "translate_init.c.inc" 8625fcf5ef2aSThomas Huth 8626fcf5ef2aSThomas Huth /*****************************************************************************/ 8627fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 862890c84c56SMarkus Armbruster void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 8629fcf5ef2aSThomas Huth { 8630fcf5ef2aSThomas Huth #define RGPL 4 8631fcf5ef2aSThomas Huth #define RFPL 4 8632fcf5ef2aSThomas Huth 8633fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 8634fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 8635fcf5ef2aSThomas Huth int i; 8636fcf5ef2aSThomas Huth 863790c84c56SMarkus Armbruster qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8638fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8639fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 8640fcf5ef2aSThomas Huth cs->cpu_index); 864190c84c56SMarkus Armbruster qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 864226c55599SRichard Henderson "%08x iidx %d didx %d\n", 8643d764184dSRichard Henderson env->msr, env->spr[SPR_HID0], env->hflags, 8644d764184dSRichard Henderson cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8645fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 864690c84c56SMarkus Armbruster qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8647fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 8648a8dafa52SSuraj Jitindar Singh " DECR " TARGET_FMT_lu 8649fcf5ef2aSThomas Huth #endif 8650fcf5ef2aSThomas Huth "\n", 8651fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8652fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 8653fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 8654fcf5ef2aSThomas Huth #endif 8655fcf5ef2aSThomas Huth ); 8656fcf5ef2aSThomas Huth #endif 8657fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 8658efe843d8SDavid Gibson if ((i & (RGPL - 1)) == 0) { 865990c84c56SMarkus Armbruster qemu_fprintf(f, "GPR%02d", i); 8660efe843d8SDavid Gibson } 866190c84c56SMarkus Armbruster qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8662efe843d8SDavid Gibson if ((i & (RGPL - 1)) == (RGPL - 1)) { 866390c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 8664fcf5ef2aSThomas Huth } 8665efe843d8SDavid Gibson } 866690c84c56SMarkus Armbruster qemu_fprintf(f, "CR "); 8667fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 866890c84c56SMarkus Armbruster qemu_fprintf(f, "%01x", env->crf[i]); 866990c84c56SMarkus Armbruster qemu_fprintf(f, " ["); 8670fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 8671fcf5ef2aSThomas Huth char a = '-'; 8672efe843d8SDavid Gibson if (env->crf[i] & 0x08) { 8673fcf5ef2aSThomas Huth a = 'L'; 8674efe843d8SDavid Gibson } else if (env->crf[i] & 0x04) { 8675fcf5ef2aSThomas Huth a = 'G'; 8676efe843d8SDavid Gibson } else if (env->crf[i] & 0x02) { 8677fcf5ef2aSThomas Huth a = 'E'; 8678efe843d8SDavid Gibson } 867990c84c56SMarkus Armbruster qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8680fcf5ef2aSThomas Huth } 868190c84c56SMarkus Armbruster qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8682fcf5ef2aSThomas Huth env->reserve_addr); 8683685f1ce2SRichard Henderson 8684685f1ce2SRichard Henderson if (flags & CPU_DUMP_FPU) { 8685fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 8686685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == 0) { 868790c84c56SMarkus Armbruster qemu_fprintf(f, "FPR%02d", i); 8688685f1ce2SRichard Henderson } 868990c84c56SMarkus Armbruster qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8690685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == (RFPL - 1)) { 869190c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 8692fcf5ef2aSThomas Huth } 8693685f1ce2SRichard Henderson } 869490c84c56SMarkus Armbruster qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8695685f1ce2SRichard Henderson } 8696685f1ce2SRichard Henderson 8697fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 869890c84c56SMarkus Armbruster qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8699fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8700fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8701fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8702fcf5ef2aSThomas Huth 870390c84c56SMarkus Armbruster qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8704fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8705fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8706fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8707fcf5ef2aSThomas Huth 870890c84c56SMarkus Armbruster qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8709fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8710fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8711fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8712fcf5ef2aSThomas Huth 8713fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8714fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 8715a790e82bSBenjamin Herrenschmidt env->excp_model == POWERPC_EXCP_POWER8 || 8716526cdce7SNicholas Piggin env->excp_model == POWERPC_EXCP_POWER9 || 8717526cdce7SNicholas Piggin env->excp_model == POWERPC_EXCP_POWER10) { 871890c84c56SMarkus Armbruster qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8719fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8720fcf5ef2aSThomas Huth } 8721fcf5ef2aSThomas Huth #endif 8722fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 872390c84c56SMarkus Armbruster qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8724fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8725fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8726fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8727fcf5ef2aSThomas Huth 872890c84c56SMarkus Armbruster qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8729fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8730fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8731fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8732fcf5ef2aSThomas Huth 873390c84c56SMarkus Armbruster qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8734fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8735fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8736fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8737fcf5ef2aSThomas Huth 873890c84c56SMarkus Armbruster qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8739fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 8740fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8741fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 8742fcf5ef2aSThomas Huth 8743fcf5ef2aSThomas Huth /* FSL-specific */ 874490c84c56SMarkus Armbruster qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8745fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8746fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8747fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8748fcf5ef2aSThomas Huth 8749fcf5ef2aSThomas Huth /* 8750fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 8751fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 8752fcf5ef2aSThomas Huth */ 8753fcf5ef2aSThomas Huth } 8754fcf5ef2aSThomas Huth 8755fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8756fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 875790c84c56SMarkus Armbruster qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8758fcf5ef2aSThomas Huth } 8759fcf5ef2aSThomas Huth #endif 8760fcf5ef2aSThomas Huth 8761efe843d8SDavid Gibson if (env->spr_cb[SPR_LPCR].name) { 876290c84c56SMarkus Armbruster qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8763efe843d8SDavid Gibson } 8764d801a61eSSuraj Jitindar Singh 87650941d728SDavid Gibson switch (env->mmu_model) { 8766fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 8767fcf5ef2aSThomas Huth case POWERPC_MMU_601: 8768fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 8769fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 8770fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 87710941d728SDavid Gibson case POWERPC_MMU_64B: 87720941d728SDavid Gibson case POWERPC_MMU_2_03: 87730941d728SDavid Gibson case POWERPC_MMU_2_06: 87740941d728SDavid Gibson case POWERPC_MMU_2_07: 87750941d728SDavid Gibson case POWERPC_MMU_3_00: 8776fcf5ef2aSThomas Huth #endif 87774f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 877890c84c56SMarkus Armbruster qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 87794f4f28ffSSuraj Jitindar Singh } 87804a7518e0SCédric Le Goater if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 878190c84c56SMarkus Armbruster qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 87824a7518e0SCédric Le Goater } 878390c84c56SMarkus Armbruster qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8784fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8785fcf5ef2aSThomas Huth break; 8786fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 878790c84c56SMarkus Armbruster qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8788fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8789fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8790fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8791fcf5ef2aSThomas Huth 879290c84c56SMarkus Armbruster qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8793fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8794fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8795fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8796fcf5ef2aSThomas Huth 879790c84c56SMarkus Armbruster qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8798fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 8799fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8800fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 8801fcf5ef2aSThomas Huth break; 8802fcf5ef2aSThomas Huth default: 8803fcf5ef2aSThomas Huth break; 8804fcf5ef2aSThomas Huth } 8805fcf5ef2aSThomas Huth #endif 8806fcf5ef2aSThomas Huth 8807fcf5ef2aSThomas Huth #undef RGPL 8808fcf5ef2aSThomas Huth #undef RFPL 8809fcf5ef2aSThomas Huth } 8810fcf5ef2aSThomas Huth 88117468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 88127468e2c8SBruno Larsen (billionai) /* Opcode types */ 88137468e2c8SBruno Larsen (billionai) enum { 88147468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 88157468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 88167468e2c8SBruno Larsen (billionai) }; 88177468e2c8SBruno Larsen (billionai) 88187468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 88197468e2c8SBruno Larsen (billionai) 88207468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 88217468e2c8SBruno Larsen (billionai) { 88227468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 88237468e2c8SBruno Larsen (billionai) } 88247468e2c8SBruno Larsen (billionai) 88257468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 88267468e2c8SBruno Larsen (billionai) { 88277468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 88287468e2c8SBruno Larsen (billionai) } 88297468e2c8SBruno Larsen (billionai) 88307468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 88317468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 88327468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 88337468e2c8SBruno Larsen (billionai) { 88347468e2c8SBruno Larsen (billionai) int i; 88357468e2c8SBruno Larsen (billionai) 88367468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 88377468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88387468e2c8SBruno Larsen (billionai) } 88397468e2c8SBruno Larsen (billionai) } 88407468e2c8SBruno Larsen (billionai) 88417468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 88427468e2c8SBruno Larsen (billionai) { 88437468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 88447468e2c8SBruno Larsen (billionai) 88457468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 88467468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 88477468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 88487468e2c8SBruno Larsen (billionai) 88497468e2c8SBruno Larsen (billionai) return 0; 88507468e2c8SBruno Larsen (billionai) } 88517468e2c8SBruno Larsen (billionai) 88527468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 88537468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 88547468e2c8SBruno Larsen (billionai) { 88557468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 88567468e2c8SBruno Larsen (billionai) return -1; 88577468e2c8SBruno Larsen (billionai) } 88587468e2c8SBruno Larsen (billionai) table[idx] = handler; 88597468e2c8SBruno Larsen (billionai) 88607468e2c8SBruno Larsen (billionai) return 0; 88617468e2c8SBruno Larsen (billionai) } 88627468e2c8SBruno Larsen (billionai) 88637468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 88647468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 88657468e2c8SBruno Larsen (billionai) { 88667468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 88677468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 88687468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 88697468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 88707468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 88717468e2c8SBruno Larsen (billionai) ppc_opcodes[idx]->oname, handler->oname); 88727468e2c8SBruno Larsen (billionai) #endif 88737468e2c8SBruno Larsen (billionai) return -1; 88747468e2c8SBruno Larsen (billionai) } 88757468e2c8SBruno Larsen (billionai) 88767468e2c8SBruno Larsen (billionai) return 0; 88777468e2c8SBruno Larsen (billionai) } 88787468e2c8SBruno Larsen (billionai) 88797468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 88807468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 88817468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 88827468e2c8SBruno Larsen (billionai) { 88837468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 88847468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 88857468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 88867468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 88877468e2c8SBruno Larsen (billionai) return -1; 88887468e2c8SBruno Larsen (billionai) } 88897468e2c8SBruno Larsen (billionai) } else { 88907468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 88917468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 88927468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 88937468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 88947468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 88957468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 88967468e2c8SBruno Larsen (billionai) #endif 88977468e2c8SBruno Larsen (billionai) return -1; 88987468e2c8SBruno Larsen (billionai) } 88997468e2c8SBruno Larsen (billionai) } 89007468e2c8SBruno Larsen (billionai) if (handler != NULL && 89017468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 89027468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 89037468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 89047468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 89057468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 89067468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 89077468e2c8SBruno Larsen (billionai) #endif 89087468e2c8SBruno Larsen (billionai) return -1; 89097468e2c8SBruno Larsen (billionai) } 89107468e2c8SBruno Larsen (billionai) 89117468e2c8SBruno Larsen (billionai) return 0; 89127468e2c8SBruno Larsen (billionai) } 89137468e2c8SBruno Larsen (billionai) 89147468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 89157468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 89167468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 89177468e2c8SBruno Larsen (billionai) { 89187468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 89197468e2c8SBruno Larsen (billionai) } 89207468e2c8SBruno Larsen (billionai) 89217468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 89227468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 89237468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 89247468e2c8SBruno Larsen (billionai) { 89257468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 89267468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 89277468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 89287468e2c8SBruno Larsen (billionai) return -1; 89297468e2c8SBruno Larsen (billionai) } 89307468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 89317468e2c8SBruno Larsen (billionai) handler) < 0) { 89327468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 89337468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 89347468e2c8SBruno Larsen (billionai) return -1; 89357468e2c8SBruno Larsen (billionai) } 89367468e2c8SBruno Larsen (billionai) 89377468e2c8SBruno Larsen (billionai) return 0; 89387468e2c8SBruno Larsen (billionai) } 89397468e2c8SBruno Larsen (billionai) 89407468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 89417468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 89427468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 89437468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 89447468e2c8SBruno Larsen (billionai) { 89457468e2c8SBruno Larsen (billionai) opc_handler_t **table; 89467468e2c8SBruno Larsen (billionai) 89477468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 89487468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 89497468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 89507468e2c8SBruno Larsen (billionai) return -1; 89517468e2c8SBruno Larsen (billionai) } 89527468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 89537468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 89547468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 89557468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 89567468e2c8SBruno Larsen (billionai) return -1; 89577468e2c8SBruno Larsen (billionai) } 89587468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 89597468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 89607468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 89617468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 89627468e2c8SBruno Larsen (billionai) return -1; 89637468e2c8SBruno Larsen (billionai) } 89647468e2c8SBruno Larsen (billionai) return 0; 89657468e2c8SBruno Larsen (billionai) } 89667468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 89677468e2c8SBruno Larsen (billionai) { 89687468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 89697468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 89707468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 89717468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 89727468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 89737468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 89747468e2c8SBruno Larsen (billionai) return -1; 89757468e2c8SBruno Larsen (billionai) } 89767468e2c8SBruno Larsen (billionai) } else { 89777468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 89787468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 89797468e2c8SBruno Larsen (billionai) return -1; 89807468e2c8SBruno Larsen (billionai) } 89817468e2c8SBruno Larsen (billionai) } 89827468e2c8SBruno Larsen (billionai) } else { 89837468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 89847468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 89857468e2c8SBruno Larsen (billionai) return -1; 89867468e2c8SBruno Larsen (billionai) } 89877468e2c8SBruno Larsen (billionai) } 89887468e2c8SBruno Larsen (billionai) } else { 89897468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 89907468e2c8SBruno Larsen (billionai) return -1; 89917468e2c8SBruno Larsen (billionai) } 89927468e2c8SBruno Larsen (billionai) } 89937468e2c8SBruno Larsen (billionai) 89947468e2c8SBruno Larsen (billionai) return 0; 89957468e2c8SBruno Larsen (billionai) } 89967468e2c8SBruno Larsen (billionai) 89977468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 89987468e2c8SBruno Larsen (billionai) { 89997468e2c8SBruno Larsen (billionai) int i, count, tmp; 90007468e2c8SBruno Larsen (billionai) 90017468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 90027468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 90037468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 90047468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 90057468e2c8SBruno Larsen (billionai) } 90067468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 90077468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 90087468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 90097468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 90107468e2c8SBruno Larsen (billionai) if (tmp == 0) { 90117468e2c8SBruno Larsen (billionai) free(table[i]); 90127468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 90137468e2c8SBruno Larsen (billionai) } else { 90147468e2c8SBruno Larsen (billionai) count++; 90157468e2c8SBruno Larsen (billionai) } 90167468e2c8SBruno Larsen (billionai) } else { 90177468e2c8SBruno Larsen (billionai) count++; 90187468e2c8SBruno Larsen (billionai) } 90197468e2c8SBruno Larsen (billionai) } 90207468e2c8SBruno Larsen (billionai) } 90217468e2c8SBruno Larsen (billionai) 90227468e2c8SBruno Larsen (billionai) return count; 90237468e2c8SBruno Larsen (billionai) } 90247468e2c8SBruno Larsen (billionai) 90257468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 90267468e2c8SBruno Larsen (billionai) { 90277468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 90287468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 90297468e2c8SBruno Larsen (billionai) } 90307468e2c8SBruno Larsen (billionai) } 90317468e2c8SBruno Larsen (billionai) 90327468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 90337468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 90347468e2c8SBruno Larsen (billionai) { 90357468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 90367468e2c8SBruno Larsen (billionai) opcode_t *opc; 90377468e2c8SBruno Larsen (billionai) 90387468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 90397468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 90407468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 90417468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 90427468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 90437468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 90447468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 90457468e2c8SBruno Larsen (billionai) opc->opc3); 90467468e2c8SBruno Larsen (billionai) return; 90477468e2c8SBruno Larsen (billionai) } 90487468e2c8SBruno Larsen (billionai) } 90497468e2c8SBruno Larsen (billionai) } 90507468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 90517468e2c8SBruno Larsen (billionai) fflush(stdout); 90527468e2c8SBruno Larsen (billionai) fflush(stderr); 90537468e2c8SBruno Larsen (billionai) } 90547468e2c8SBruno Larsen (billionai) 90557468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 90567468e2c8SBruno Larsen (billionai) { 90577468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 90587468e2c8SBruno Larsen (billionai) int i, j, k; 90597468e2c8SBruno Larsen (billionai) 90607468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 90617468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 90627468e2c8SBruno Larsen (billionai) continue; 90637468e2c8SBruno Larsen (billionai) } 90647468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 90657468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 90667468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 90677468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 90687468e2c8SBruno Larsen (billionai) continue; 90697468e2c8SBruno Larsen (billionai) } 90707468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 90717468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 90727468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 90737468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 90747468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 90757468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 90767468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 90777468e2c8SBruno Larsen (billionai) } 90787468e2c8SBruno Larsen (billionai) } 90797468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 90807468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 90817468e2c8SBruno Larsen (billionai) } 90827468e2c8SBruno Larsen (billionai) } 90837468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 90847468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 90857468e2c8SBruno Larsen (billionai) } 90867468e2c8SBruno Larsen (billionai) } 90877468e2c8SBruno Larsen (billionai) } 90887468e2c8SBruno Larsen (billionai) 90897468e2c8SBruno Larsen (billionai) #if defined(PPC_DUMP_CPU) 90907468e2c8SBruno Larsen (billionai) static void dump_ppc_insns(CPUPPCState *env) 90917468e2c8SBruno Larsen (billionai) { 90927468e2c8SBruno Larsen (billionai) opc_handler_t **table, *handler; 90937468e2c8SBruno Larsen (billionai) const char *p, *q; 90947468e2c8SBruno Larsen (billionai) uint8_t opc1, opc2, opc3, opc4; 90957468e2c8SBruno Larsen (billionai) 90967468e2c8SBruno Larsen (billionai) printf("Instructions set:\n"); 90977468e2c8SBruno Larsen (billionai) /* opc1 is 6 bits long */ 90987468e2c8SBruno Larsen (billionai) for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 90997468e2c8SBruno Larsen (billionai) table = env->opcodes; 91007468e2c8SBruno Larsen (billionai) handler = table[opc1]; 91017468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 91027468e2c8SBruno Larsen (billionai) /* opc2 is 5 bits long */ 91037468e2c8SBruno Larsen (billionai) for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 91047468e2c8SBruno Larsen (billionai) table = env->opcodes; 91057468e2c8SBruno Larsen (billionai) handler = env->opcodes[opc1]; 91067468e2c8SBruno Larsen (billionai) table = ind_table(handler); 91077468e2c8SBruno Larsen (billionai) handler = table[opc2]; 91087468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 91097468e2c8SBruno Larsen (billionai) table = ind_table(handler); 91107468e2c8SBruno Larsen (billionai) /* opc3 is 5 bits long */ 91117468e2c8SBruno Larsen (billionai) for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 91127468e2c8SBruno Larsen (billionai) opc3++) { 91137468e2c8SBruno Larsen (billionai) handler = table[opc3]; 91147468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 91157468e2c8SBruno Larsen (billionai) table = ind_table(handler); 91167468e2c8SBruno Larsen (billionai) /* opc4 is 5 bits long */ 91177468e2c8SBruno Larsen (billionai) for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 91187468e2c8SBruno Larsen (billionai) opc4++) { 91197468e2c8SBruno Larsen (billionai) handler = table[opc4]; 91207468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 91217468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x %02x -- " 91227468e2c8SBruno Larsen (billionai) "(%02d %04d %02d) : %s\n", 91237468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc4, 91247468e2c8SBruno Larsen (billionai) opc1, (opc3 << 5) | opc2, opc4, 91257468e2c8SBruno Larsen (billionai) handler->oname); 91267468e2c8SBruno Larsen (billionai) } 91277468e2c8SBruno Larsen (billionai) } 91287468e2c8SBruno Larsen (billionai) } else { 91297468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 91307468e2c8SBruno Larsen (billionai) /* Special hack to properly dump SPE insns */ 91317468e2c8SBruno Larsen (billionai) p = strchr(handler->oname, '_'); 91327468e2c8SBruno Larsen (billionai) if (p == NULL) { 91337468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x (%02d %04d) : " 91347468e2c8SBruno Larsen (billionai) "%s\n", 91357468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc1, 91367468e2c8SBruno Larsen (billionai) (opc3 << 5) | opc2, 91377468e2c8SBruno Larsen (billionai) handler->oname); 91387468e2c8SBruno Larsen (billionai) } else { 91397468e2c8SBruno Larsen (billionai) q = "speundef"; 91407468e2c8SBruno Larsen (billionai) if ((p - handler->oname) != strlen(q) 91417468e2c8SBruno Larsen (billionai) || (memcmp(handler->oname, q, strlen(q)) 91427468e2c8SBruno Larsen (billionai) != 0)) { 91437468e2c8SBruno Larsen (billionai) /* First instruction */ 91447468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x" 91457468e2c8SBruno Larsen (billionai) "(%02d %04d) : %.*s\n", 91467468e2c8SBruno Larsen (billionai) opc1, opc2 << 1, opc3, opc1, 91477468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1), 91487468e2c8SBruno Larsen (billionai) (int)(p - handler->oname), 91497468e2c8SBruno Larsen (billionai) handler->oname); 91507468e2c8SBruno Larsen (billionai) } 91517468e2c8SBruno Larsen (billionai) if (strcmp(p + 1, q) != 0) { 91527468e2c8SBruno Larsen (billionai) /* Second instruction */ 91537468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x " 91547468e2c8SBruno Larsen (billionai) "(%02d %04d) : %s\n", opc1, 91557468e2c8SBruno Larsen (billionai) (opc2 << 1) | 1, opc3, opc1, 91567468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1) | 1, 91577468e2c8SBruno Larsen (billionai) p + 1); 91587468e2c8SBruno Larsen (billionai) } 91597468e2c8SBruno Larsen (billionai) } 91607468e2c8SBruno Larsen (billionai) } 91617468e2c8SBruno Larsen (billionai) } 91627468e2c8SBruno Larsen (billionai) } 91637468e2c8SBruno Larsen (billionai) } else { 91647468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 91657468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 91667468e2c8SBruno Larsen (billionai) opc1, opc2, opc1, opc2, handler->oname); 91677468e2c8SBruno Larsen (billionai) } 91687468e2c8SBruno Larsen (billionai) } 91697468e2c8SBruno Larsen (billionai) } 91707468e2c8SBruno Larsen (billionai) } else { 91717468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 91727468e2c8SBruno Larsen (billionai) printf("INSN: %02x -- -- (%02d ----) : %s\n", 91737468e2c8SBruno Larsen (billionai) opc1, opc1, handler->oname); 91747468e2c8SBruno Larsen (billionai) } 91757468e2c8SBruno Larsen (billionai) } 91767468e2c8SBruno Larsen (billionai) } 91777468e2c8SBruno Larsen (billionai) } 91787468e2c8SBruno Larsen (billionai) #endif 91797468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 91807468e2c8SBruno Larsen (billionai) { 91817468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 91827468e2c8SBruno Larsen (billionai) 91837468e2c8SBruno Larsen (billionai) /* 91847468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 91857468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 91867468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 91877468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 91887468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 91897468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 91907468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 91917468e2c8SBruno Larsen (billionai) */ 91927468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 91937468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 91947468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 91957468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 91967468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 91977468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 91987468e2c8SBruno Larsen (billionai) } 91997468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 92007468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 92017468e2c8SBruno Larsen (billionai) return 0; 92027468e2c8SBruno Larsen (billionai) } 92037468e2c8SBruno Larsen (billionai) 92047468e2c8SBruno Larsen (billionai) 920511cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 9206fcf5ef2aSThomas Huth { 9207fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9208fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 9209fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 9210fcf5ef2aSThomas Huth int op1, op2, op3; 9211fcf5ef2aSThomas Huth 9212fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 9213fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 9214fcf5ef2aSThomas Huth handler = t1[op1]; 9215fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9216fcf5ef2aSThomas Huth t2 = ind_table(handler); 9217fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 9218fcf5ef2aSThomas Huth handler = t2[op2]; 9219fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9220fcf5ef2aSThomas Huth t3 = ind_table(handler); 9221fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 9222fcf5ef2aSThomas Huth handler = t3[op3]; 9223efe843d8SDavid Gibson if (handler->count == 0) { 9224fcf5ef2aSThomas Huth continue; 9225efe843d8SDavid Gibson } 922611cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 9227fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9228fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 9229fcf5ef2aSThomas Huth handler->oname, 9230fcf5ef2aSThomas Huth handler->count, handler->count); 9231fcf5ef2aSThomas Huth } 9232fcf5ef2aSThomas Huth } else { 9233efe843d8SDavid Gibson if (handler->count == 0) { 9234fcf5ef2aSThomas Huth continue; 9235efe843d8SDavid Gibson } 923611cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 9237fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9238fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 9239fcf5ef2aSThomas Huth handler->count, handler->count); 9240fcf5ef2aSThomas Huth } 9241fcf5ef2aSThomas Huth } 9242fcf5ef2aSThomas Huth } else { 9243efe843d8SDavid Gibson if (handler->count == 0) { 9244fcf5ef2aSThomas Huth continue; 9245efe843d8SDavid Gibson } 924611cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 9247fcf5ef2aSThomas Huth " %" PRId64 "\n", 9248fcf5ef2aSThomas Huth op1, op1, handler->oname, 9249fcf5ef2aSThomas Huth handler->count, handler->count); 9250fcf5ef2aSThomas Huth } 9251fcf5ef2aSThomas Huth } 9252fcf5ef2aSThomas Huth #endif 9253fcf5ef2aSThomas Huth } 9254fcf5ef2aSThomas Huth 9255b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 9256fcf5ef2aSThomas Huth { 9257b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 92589c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 92592df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 9260b0c2d521SEmilio G. Cota int bound; 9261fcf5ef2aSThomas Huth 9262b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 9263b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 92642df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 9265d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 92662df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 92672df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 9268b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 9269b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 9270b0c2d521SEmilio G. Cota ctx->access_type = -1; 9271d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 92722df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 9273b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 92740e3bf489SRoman Kapl ctx->flags = env->flags; 9275fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 92762df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 9277b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 9278fcf5ef2aSThomas Huth #endif 9279e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 9280e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 9281d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 9282fcf5ef2aSThomas Huth 92832df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 92842df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 92852df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 92862df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 92872df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 9288f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 92892df4fe7aSRichard Henderson 9290b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 92912df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 92922df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 9293efe843d8SDavid Gibson } 92942df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 9295b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 9296efe843d8SDavid Gibson } 9297b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9298b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 9299fcf5ef2aSThomas Huth } 9300b0c2d521SEmilio G. Cota 9301b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 9302b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 9303fcf5ef2aSThomas Huth } 9304fcf5ef2aSThomas Huth 9305b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 9306b0c2d521SEmilio G. Cota { 9307b0c2d521SEmilio G. Cota } 9308fcf5ef2aSThomas Huth 9309b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 9310b0c2d521SEmilio G. Cota { 9311b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 9312b0c2d521SEmilio G. Cota } 9313b0c2d521SEmilio G. Cota 9314b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 9315b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 9316b0c2d521SEmilio G. Cota { 9317b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9318b0c2d521SEmilio G. Cota 9319b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 93202a8ceefcSEmilio G. Cota dcbase->is_jmp = DISAS_NORETURN; 9321efe843d8SDavid Gibson /* 9322efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 9323efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 9324efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 9325efe843d8SDavid Gibson * setting tb->size below does the right thing. 9326efe843d8SDavid Gibson */ 9327b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9328b0c2d521SEmilio G. Cota return true; 9329fcf5ef2aSThomas Huth } 9330fcf5ef2aSThomas Huth 9331b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 9332b0c2d521SEmilio G. Cota { 9333b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 933428876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 9335b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 9336b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 9337b0c2d521SEmilio G. Cota 9338fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 9339fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 9340b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 9341b0c2d521SEmilio G. Cota 934223f42b60SEmilio G. Cota ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, 934323f42b60SEmilio G. Cota need_byteswap(ctx)); 934423f42b60SEmilio G. Cota 9345fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 9346b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 9347b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 9348b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 9349b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 935028876bf2SAlex Bennée table = cpu->opcodes; 9351b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 9352fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9353fcf5ef2aSThomas Huth table = ind_table(handler); 9354b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 9355fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9356fcf5ef2aSThomas Huth table = ind_table(handler); 9357b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 9358fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9359fcf5ef2aSThomas Huth table = ind_table(handler); 9360b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 9361fcf5ef2aSThomas Huth } 9362fcf5ef2aSThomas Huth } 9363fcf5ef2aSThomas Huth } 9364fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 9365fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 9366fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 9367fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 9368fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 9369b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 9370b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 9371b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 9372fcf5ef2aSThomas Huth } else { 9373fcf5ef2aSThomas Huth uint32_t inval; 9374fcf5ef2aSThomas Huth 9375b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 9376b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 9377fcf5ef2aSThomas Huth inval = handler->inval2; 9378fcf5ef2aSThomas Huth } else { 9379fcf5ef2aSThomas Huth inval = handler->inval1; 9380fcf5ef2aSThomas Huth } 9381fcf5ef2aSThomas Huth 9382b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 9383fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 9384fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 9385b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 9386b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 9387b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 9388b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4); 9389b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 9390b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 9391b0c2d521SEmilio G. Cota return; 9392fcf5ef2aSThomas Huth } 9393fcf5ef2aSThomas Huth } 9394b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 9395fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9396fcf5ef2aSThomas Huth handler->count++; 9397fcf5ef2aSThomas Huth #endif 9398fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 9399b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 9400b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 9401b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 9402b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 9403b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 9404e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 94050e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 9406fcf5ef2aSThomas Huth } 9407b0c2d521SEmilio G. Cota 9408fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 9409b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 9410b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 9411b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 9412fcf5ef2aSThomas Huth } 9413b0c2d521SEmilio G. Cota 9414b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 9415b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 9416fcf5ef2aSThomas Huth } 9417b0c2d521SEmilio G. Cota 9418b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 9419b0c2d521SEmilio G. Cota { 9420b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9421b0c2d521SEmilio G. Cota 9422b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 9423b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 9424b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 9425b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9426b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9427fcf5ef2aSThomas Huth } 9428fcf5ef2aSThomas Huth /* Generate the return instruction */ 942907ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 9430fcf5ef2aSThomas Huth } 9431fcf5ef2aSThomas Huth } 9432b0c2d521SEmilio G. Cota 9433b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 9434b0c2d521SEmilio G. Cota { 9435b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 9436b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 9437b0c2d521SEmilio G. Cota } 9438b0c2d521SEmilio G. Cota 9439b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 9440b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 9441b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 9442b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 9443b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 9444b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 9445b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 9446b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 9447b0c2d521SEmilio G. Cota }; 9448b0c2d521SEmilio G. Cota 94498b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 9450b0c2d521SEmilio G. Cota { 9451b0c2d521SEmilio G. Cota DisasContext ctx; 9452b0c2d521SEmilio G. Cota 94538b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 9454fcf5ef2aSThomas Huth } 9455fcf5ef2aSThomas Huth 9456fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 9457fcf5ef2aSThomas Huth target_ulong *data) 9458fcf5ef2aSThomas Huth { 9459fcf5ef2aSThomas Huth env->nip = data[0]; 9460fcf5ef2aSThomas Huth } 9461