1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39eeaaefe9SLeandro Lupori #include "power8-pmu.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44d53106c9SRichard Henderson #define HELPER_H "helper.h" 45d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 46d53106c9SRichard Henderson #undef HELPER_H 47d53106c9SRichard Henderson 48fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 49fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 50fcf5ef2aSThomas Huth 51fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 52efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 53fcf5ef2aSThomas Huth 54fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 56fcf5ef2aSThomas Huth #else 57fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 58fcf5ef2aSThomas Huth #endif 59fcf5ef2aSThomas Huth /*****************************************************************************/ 60fcf5ef2aSThomas Huth /* Code translation helpers */ 61fcf5ef2aSThomas Huth 62fcf5ef2aSThomas Huth /* global register indexes */ 63fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 64fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 65fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 66fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 67fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 68fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 69fcf5ef2aSThomas Huth static TCGv cpu_nip; 70fcf5ef2aSThomas Huth static TCGv cpu_msr; 71fcf5ef2aSThomas Huth static TCGv cpu_ctr; 72fcf5ef2aSThomas Huth static TCGv cpu_lr; 73fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 74fcf5ef2aSThomas Huth static TCGv cpu_cfar; 75fcf5ef2aSThomas Huth #endif 76dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 77fcf5ef2aSThomas Huth static TCGv cpu_reserve; 78392d328aSNicholas Piggin static TCGv cpu_reserve_length; 79253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 80894448aeSRichard Henderson static TCGv cpu_reserve_val2; 81fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 82fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 83fcf5ef2aSThomas Huth 84fcf5ef2aSThomas Huth void ppc_translate_init(void) 85fcf5ef2aSThomas Huth { 86fcf5ef2aSThomas Huth int i; 87fcf5ef2aSThomas Huth char *p; 88fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 89fcf5ef2aSThomas Huth 90fcf5ef2aSThomas Huth p = cpu_reg_names; 91fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 92fcf5ef2aSThomas Huth 93fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 94fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 95fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 96fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 97fcf5ef2aSThomas Huth p += 5; 98fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 99fcf5ef2aSThomas Huth } 100fcf5ef2aSThomas Huth 101fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 103fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 107fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 108fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 109fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 110fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 111fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 112fcf5ef2aSThomas Huth } 113fcf5ef2aSThomas Huth 114fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 115fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 118fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 119fcf5ef2aSThomas Huth 120fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 121fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 122fcf5ef2aSThomas Huth 123fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 124fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 127fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 128fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 129fcf5ef2aSThomas Huth #endif 130fcf5ef2aSThomas Huth 131fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 133fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 135fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 137fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 138fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 139dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 141dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 142dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 143fcf5ef2aSThomas Huth 144fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 145fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 146fcf5ef2aSThomas Huth "reserve_addr"); 147392d328aSNicholas Piggin cpu_reserve_length = tcg_global_mem_new(cpu_env, 148392d328aSNicholas Piggin offsetof(CPUPPCState, 149392d328aSNicholas Piggin reserve_length), 150392d328aSNicholas Piggin "reserve_length"); 151253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 152253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 153253ce7b2SNikunj A Dadhania "reserve_val"); 154894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 155894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 156894448aeSRichard Henderson "reserve_val2"); 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 159fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 160fcf5ef2aSThomas Huth 161fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 162efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 163efe843d8SDavid Gibson "access_type"); 164fcf5ef2aSThomas Huth } 165fcf5ef2aSThomas Huth 166fcf5ef2aSThomas Huth /* internal defines */ 167fcf5ef2aSThomas Huth struct DisasContext { 168b6bac4bcSEmilio G. Cota DisasContextBase base; 1692c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 170fcf5ef2aSThomas Huth uint32_t opcode; 171fcf5ef2aSThomas Huth /* Routine used to access memory */ 172fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 173fcf5ef2aSThomas Huth bool lazy_tlb_flush; 174fcf5ef2aSThomas Huth bool need_access_type; 175fcf5ef2aSThomas Huth int mem_idx; 176fcf5ef2aSThomas Huth int access_type; 177fcf5ef2aSThomas Huth /* Translation flags */ 17814776ab5STony Nguyen MemOp default_tcg_memop_mask; 179fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 180fcf5ef2aSThomas Huth bool sf_mode; 181fcf5ef2aSThomas Huth bool has_cfar; 182fcf5ef2aSThomas Huth #endif 183fcf5ef2aSThomas Huth bool fpu_enabled; 184fcf5ef2aSThomas Huth bool altivec_enabled; 185fcf5ef2aSThomas Huth bool vsx_enabled; 186fcf5ef2aSThomas Huth bool spe_enabled; 187fcf5ef2aSThomas Huth bool tm_enabled; 188c6fd28fdSSuraj Jitindar Singh bool gtse; 1891db3632aSMatheus Ferst bool hr; 190f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 191f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1928b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1938b3d1c49SLeandro Lupori bool pmc_other; 19446d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 195fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 196fcf5ef2aSThomas Huth int singlestep_enabled; 1970e3bf489SRoman Kapl uint32_t flags; 198fcf5ef2aSThomas Huth uint64_t insns_flags; 199fcf5ef2aSThomas Huth uint64_t insns_flags2; 200fcf5ef2aSThomas Huth }; 201fcf5ef2aSThomas Huth 202a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 203a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 204a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 205a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 206a9b5b3d0SRichard Henderson 207fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 208fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 209fcf5ef2aSThomas Huth { 210ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 211fcf5ef2aSThomas Huth return ctx->le_mode; 212fcf5ef2aSThomas Huth #else 213fcf5ef2aSThomas Huth return !ctx->le_mode; 214fcf5ef2aSThomas Huth #endif 215fcf5ef2aSThomas Huth } 216fcf5ef2aSThomas Huth 217fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 218fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 219fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 220fcf5ef2aSThomas Huth #else 221fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 222fcf5ef2aSThomas Huth #endif 223fcf5ef2aSThomas Huth 224fcf5ef2aSThomas Huth struct opc_handler_t { 225fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 226fcf5ef2aSThomas Huth uint32_t inval1; 227fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 228fcf5ef2aSThomas Huth uint32_t inval2; 229fcf5ef2aSThomas Huth /* instruction type */ 230fcf5ef2aSThomas Huth uint64_t type; 231fcf5ef2aSThomas Huth /* extended instruction type */ 232fcf5ef2aSThomas Huth uint64_t type2; 233fcf5ef2aSThomas Huth /* handler */ 234fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 235fcf5ef2aSThomas Huth }; 236fcf5ef2aSThomas Huth 237b769d4c8SNicholas Piggin static inline bool gen_serialize(DisasContext *ctx) 238b769d4c8SNicholas Piggin { 239b769d4c8SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 240b769d4c8SNicholas Piggin /* Restart with exclusive lock. */ 241b769d4c8SNicholas Piggin gen_helper_exit_atomic(cpu_env); 242b769d4c8SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 243b769d4c8SNicholas Piggin return false; 244b769d4c8SNicholas Piggin } 245b769d4c8SNicholas Piggin return true; 246b769d4c8SNicholas Piggin } 247b769d4c8SNicholas Piggin 248b769d4c8SNicholas Piggin #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 249*3401ea3cSNicholas Piggin static inline bool gen_serialize_core_lpar(DisasContext *ctx) 250b769d4c8SNicholas Piggin { 251*3401ea3cSNicholas Piggin if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 252b769d4c8SNicholas Piggin return gen_serialize(ctx); 253b769d4c8SNicholas Piggin } 254b769d4c8SNicholas Piggin 255b769d4c8SNicholas Piggin return true; 256b769d4c8SNicholas Piggin } 257b769d4c8SNicholas Piggin #endif 258b769d4c8SNicholas Piggin 2590e3bf489SRoman Kapl /* SPR load/store helpers */ 2600e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2610e3bf489SRoman Kapl { 2620e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2630e3bf489SRoman Kapl } 2640e3bf489SRoman Kapl 2650e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2660e3bf489SRoman Kapl { 2670e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2680e3bf489SRoman Kapl } 2690e3bf489SRoman Kapl 270fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 271fcf5ef2aSThomas Huth { 272fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 273fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 274fcf5ef2aSThomas Huth ctx->access_type = access_type; 275fcf5ef2aSThomas Huth } 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth 278fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 279fcf5ef2aSThomas Huth { 280fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 281fcf5ef2aSThomas Huth nip = (uint32_t)nip; 282fcf5ef2aSThomas Huth } 283fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 284fcf5ef2aSThomas Huth } 285fcf5ef2aSThomas Huth 286fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 287fcf5ef2aSThomas Huth { 288fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 289fcf5ef2aSThomas Huth 290efe843d8SDavid Gibson /* 291efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 292efe843d8SDavid Gibson * faulting instruction 293fcf5ef2aSThomas Huth */ 2942c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2957058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 2967058ff52SRichard Henderson t1 = tcg_constant_i32(error); 297fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 2983d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 299fcf5ef2aSThomas Huth } 300fcf5ef2aSThomas Huth 301fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 302fcf5ef2aSThomas Huth { 303fcf5ef2aSThomas Huth TCGv_i32 t0; 304fcf5ef2aSThomas Huth 305efe843d8SDavid Gibson /* 306efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 307efe843d8SDavid Gibson * faulting instruction 308fcf5ef2aSThomas Huth */ 3092c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 3107058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 311fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3123d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 313fcf5ef2aSThomas Huth } 314fcf5ef2aSThomas Huth 315fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 316fcf5ef2aSThomas Huth target_ulong nip) 317fcf5ef2aSThomas Huth { 318fcf5ef2aSThomas Huth TCGv_i32 t0; 319fcf5ef2aSThomas Huth 320fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 3217058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 322fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3233d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 324fcf5ef2aSThomas Huth } 325fcf5ef2aSThomas Huth 3262fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3272fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3282fdedcbcSMatheus Ferst { 329283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 3302fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3312fdedcbcSMatheus Ferst } 3322fdedcbcSMatheus Ferst #endif 3332fdedcbcSMatheus Ferst 334e150ac89SRoman Kapl /* 335e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 336e150ac89SRoman Kapl * SPR registers for this exception. 337e150ac89SRoman Kapl * 338e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 339e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3400e3bf489SRoman Kapl */ 341e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3420e3bf489SRoman Kapl { 3430e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3440e3bf489SRoman Kapl target_ulong dbsr = 0; 345e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3460e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 347e150ac89SRoman Kapl } else { 348e150ac89SRoman Kapl /* Must have been branch */ 3490e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3500e3bf489SRoman Kapl } 3510e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3520e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3530e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3540e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3550e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3560e3bf489SRoman Kapl } else { 357e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3580e3bf489SRoman Kapl } 3590e3bf489SRoman Kapl } 3600e3bf489SRoman Kapl 361fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 362fcf5ef2aSThomas Huth { 3639498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3643d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 365fcf5ef2aSThomas Huth } 366fcf5ef2aSThomas Huth 367fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 368fcf5ef2aSThomas Huth { 369fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 370fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 371fcf5ef2aSThomas Huth } 372fcf5ef2aSThomas Huth 373fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 374fcf5ef2aSThomas Huth { 375fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 376fcf5ef2aSThomas Huth } 377fcf5ef2aSThomas Huth 378fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 379fcf5ef2aSThomas Huth { 380fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 381fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 382fcf5ef2aSThomas Huth } 383fcf5ef2aSThomas Huth 38437f219c8SBruno Larsen (billionai) /*****************************************************************************/ 38537f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 38637f219c8SBruno Larsen (billionai) 387a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 38837f219c8SBruno Larsen (billionai) { 38937f219c8SBruno Larsen (billionai) #if 0 39037f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 39137f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 39237f219c8SBruno Larsen (billionai) #endif 39337f219c8SBruno Larsen (billionai) } 39437f219c8SBruno Larsen (billionai) 39537f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 39637f219c8SBruno Larsen (billionai) 39737f219c8SBruno Larsen (billionai) /* 39837f219c8SBruno Larsen (billionai) * Generic callbacks: 39937f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 40037f219c8SBruno Larsen (billionai) */ 40137f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 40237f219c8SBruno Larsen (billionai) { 40337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4047058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 40537f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 40637f219c8SBruno Larsen (billionai) #endif 40737f219c8SBruno Larsen (billionai) } 40837f219c8SBruno Larsen (billionai) 409a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 41037f219c8SBruno Larsen (billionai) { 41137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 41237f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 41337f219c8SBruno Larsen (billionai) } 41437f219c8SBruno Larsen (billionai) 41537f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 41637f219c8SBruno Larsen (billionai) { 41737f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4187058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 41937f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 42037f219c8SBruno Larsen (billionai) #endif 42137f219c8SBruno Larsen (billionai) } 42237f219c8SBruno Larsen (billionai) 423a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 42437f219c8SBruno Larsen (billionai) { 42537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 42637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42737f219c8SBruno Larsen (billionai) } 42837f219c8SBruno Larsen (billionai) 429a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43037f219c8SBruno Larsen (billionai) { 43137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43537f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43637f219c8SBruno Larsen (billionai) #else 43737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43837f219c8SBruno Larsen (billionai) #endif 43937f219c8SBruno Larsen (billionai) } 44037f219c8SBruno Larsen (billionai) 441c5d98a7bSNicholas Piggin static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 442fbda88f7SNicholas Piggin { 443488aad11SNicholas Piggin /* This does not implement >1 thread */ 444488aad11SNicholas Piggin TCGv t0 = tcg_temp_new(); 445488aad11SNicholas Piggin TCGv t1 = tcg_temp_new(); 446488aad11SNicholas Piggin tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 447488aad11SNicholas Piggin tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 448488aad11SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 449488aad11SNicholas Piggin gen_store_spr(sprn, t1); 450c5d98a7bSNicholas Piggin } 451c5d98a7bSNicholas Piggin 452c5d98a7bSNicholas Piggin void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 453c5d98a7bSNicholas Piggin { 454*3401ea3cSNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 455*3401ea3cSNicholas Piggin /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 456c5d98a7bSNicholas Piggin spr_write_CTRL_ST(ctx, sprn, gprn); 457c5d98a7bSNicholas Piggin goto out; 458c5d98a7bSNicholas Piggin } 459c5d98a7bSNicholas Piggin 460c5d98a7bSNicholas Piggin if (!gen_serialize(ctx)) { 461c5d98a7bSNicholas Piggin return; 462c5d98a7bSNicholas Piggin } 463c5d98a7bSNicholas Piggin 464c5d98a7bSNicholas Piggin gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 465c5d98a7bSNicholas Piggin cpu_gpr[gprn]); 466c5d98a7bSNicholas Piggin out: 467488aad11SNicholas Piggin spr_store_dump_spr(sprn); 468fbda88f7SNicholas Piggin 469fbda88f7SNicholas Piggin /* 470fbda88f7SNicholas Piggin * SPR_CTRL writes must force a new translation block, 471fbda88f7SNicholas Piggin * allowing the PMU to calculate the run latch events with 472fbda88f7SNicholas Piggin * more accuracy. 473fbda88f7SNicholas Piggin */ 474fbda88f7SNicholas Piggin ctx->base.is_jmp = DISAS_EXIT_UPDATE; 475fbda88f7SNicholas Piggin } 476fbda88f7SNicholas Piggin 477fbda88f7SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 478a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 47937f219c8SBruno Larsen (billionai) { 48037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 48137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 48237f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 48337f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 48437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 48537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 48637f219c8SBruno Larsen (billionai) } 48737f219c8SBruno Larsen (billionai) 488a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 48937f219c8SBruno Larsen (billionai) { 49037f219c8SBruno Larsen (billionai) } 49137f219c8SBruno Larsen (billionai) 49237f219c8SBruno Larsen (billionai) #endif 49337f219c8SBruno Larsen (billionai) 49437f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 49537f219c8SBruno Larsen (billionai) /* XER */ 496a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 49737f219c8SBruno Larsen (billionai) { 49837f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 49937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 50037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 50137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 50237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 50337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 50437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 50537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 50637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 50737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 50837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 50937f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 51037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 51137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 51237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 51337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 51437f219c8SBruno Larsen (billionai) } 51537f219c8SBruno Larsen (billionai) } 51637f219c8SBruno Larsen (billionai) 517a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 51837f219c8SBruno Larsen (billionai) { 51937f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 52037f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 52137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 52237f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 52337f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 52437f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 52537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 52637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 52737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 52837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 52937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 53037f219c8SBruno Larsen (billionai) } 53137f219c8SBruno Larsen (billionai) 53237f219c8SBruno Larsen (billionai) /* LR */ 533a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 53437f219c8SBruno Larsen (billionai) { 53537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 53637f219c8SBruno Larsen (billionai) } 53737f219c8SBruno Larsen (billionai) 538a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 53937f219c8SBruno Larsen (billionai) { 54037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 54137f219c8SBruno Larsen (billionai) } 54237f219c8SBruno Larsen (billionai) 54337f219c8SBruno Larsen (billionai) /* CFAR */ 54437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 545a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 54637f219c8SBruno Larsen (billionai) { 54737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 54837f219c8SBruno Larsen (billionai) } 54937f219c8SBruno Larsen (billionai) 550a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 55137f219c8SBruno Larsen (billionai) { 55237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 55337f219c8SBruno Larsen (billionai) } 55437f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 55537f219c8SBruno Larsen (billionai) 55637f219c8SBruno Larsen (billionai) /* CTR */ 557a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 55837f219c8SBruno Larsen (billionai) { 55937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 56037f219c8SBruno Larsen (billionai) } 56137f219c8SBruno Larsen (billionai) 562a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 56337f219c8SBruno Larsen (billionai) { 56437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 56537f219c8SBruno Larsen (billionai) } 56637f219c8SBruno Larsen (billionai) 56737f219c8SBruno Larsen (billionai) /* User read access to SPR */ 56837f219c8SBruno Larsen (billionai) /* USPRx */ 56937f219c8SBruno Larsen (billionai) /* UMMCRx */ 57037f219c8SBruno Larsen (billionai) /* UPMCx */ 57137f219c8SBruno Larsen (billionai) /* USIA */ 57237f219c8SBruno Larsen (billionai) /* UDECR */ 573a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 57437f219c8SBruno Larsen (billionai) { 57537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 57637f219c8SBruno Larsen (billionai) } 57737f219c8SBruno Larsen (billionai) 57837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 579a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 58037f219c8SBruno Larsen (billionai) { 58137f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 58237f219c8SBruno Larsen (billionai) } 58337f219c8SBruno Larsen (billionai) #endif 58437f219c8SBruno Larsen (billionai) 58537f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 58637f219c8SBruno Larsen (billionai) /* DECR */ 58737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 588a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 58937f219c8SBruno Larsen (billionai) { 590283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 59137f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 59237f219c8SBruno Larsen (billionai) } 59337f219c8SBruno Larsen (billionai) 594a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 59537f219c8SBruno Larsen (billionai) { 596283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 59737f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 59837f219c8SBruno Larsen (billionai) } 59937f219c8SBruno Larsen (billionai) #endif 60037f219c8SBruno Larsen (billionai) 60137f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 60237f219c8SBruno Larsen (billionai) /* Time base */ 603a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 60437f219c8SBruno Larsen (billionai) { 605283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 60637f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 60737f219c8SBruno Larsen (billionai) } 60837f219c8SBruno Larsen (billionai) 609a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 61037f219c8SBruno Larsen (billionai) { 611283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 61237f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 61337f219c8SBruno Larsen (billionai) } 61437f219c8SBruno Larsen (billionai) 615a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 61637f219c8SBruno Larsen (billionai) { 61737f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 61837f219c8SBruno Larsen (billionai) } 61937f219c8SBruno Larsen (billionai) 620a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 62137f219c8SBruno Larsen (billionai) { 62237f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 62337f219c8SBruno Larsen (billionai) } 62437f219c8SBruno Larsen (billionai) 62537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 626a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 62737f219c8SBruno Larsen (billionai) { 628283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 62937f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 63037f219c8SBruno Larsen (billionai) } 63137f219c8SBruno Larsen (billionai) 632a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 63337f219c8SBruno Larsen (billionai) { 634283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 63537f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 63637f219c8SBruno Larsen (billionai) } 63737f219c8SBruno Larsen (billionai) 638a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 63937f219c8SBruno Larsen (billionai) { 64037f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 64137f219c8SBruno Larsen (billionai) } 64237f219c8SBruno Larsen (billionai) 643a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 64437f219c8SBruno Larsen (billionai) { 64537f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 64637f219c8SBruno Larsen (billionai) } 64737f219c8SBruno Larsen (billionai) 64837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 649a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 65037f219c8SBruno Larsen (billionai) { 651283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65237f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 65337f219c8SBruno Larsen (billionai) } 65437f219c8SBruno Larsen (billionai) 655a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 65637f219c8SBruno Larsen (billionai) { 657283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65837f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 65937f219c8SBruno Larsen (billionai) } 66037f219c8SBruno Larsen (billionai) 66137f219c8SBruno Larsen (billionai) /* HDECR */ 662a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 66337f219c8SBruno Larsen (billionai) { 664283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 66537f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 66637f219c8SBruno Larsen (billionai) } 66737f219c8SBruno Larsen (billionai) 668a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 66937f219c8SBruno Larsen (billionai) { 670283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67137f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 67237f219c8SBruno Larsen (billionai) } 67337f219c8SBruno Larsen (billionai) 674a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 67537f219c8SBruno Larsen (billionai) { 676283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67737f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 67837f219c8SBruno Larsen (billionai) } 67937f219c8SBruno Larsen (billionai) 680a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 68137f219c8SBruno Larsen (billionai) { 682283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 68337f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 68437f219c8SBruno Larsen (billionai) } 68537f219c8SBruno Larsen (billionai) 686a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 68737f219c8SBruno Larsen (billionai) { 688283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 68937f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 69037f219c8SBruno Larsen (billionai) } 69137f219c8SBruno Larsen (billionai) 69237f219c8SBruno Larsen (billionai) #endif 69337f219c8SBruno Larsen (billionai) #endif 69437f219c8SBruno Larsen (billionai) 69537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 69637f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 69737f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 698a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 69937f219c8SBruno Larsen (billionai) { 70037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70237f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 70337f219c8SBruno Larsen (billionai) } 70437f219c8SBruno Larsen (billionai) 705a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 70637f219c8SBruno Larsen (billionai) { 70737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70937f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 71037f219c8SBruno Larsen (billionai) } 71137f219c8SBruno Larsen (billionai) 712a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 71337f219c8SBruno Larsen (billionai) { 7147058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 71537f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 71637f219c8SBruno Larsen (billionai) } 71737f219c8SBruno Larsen (billionai) 718a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 71937f219c8SBruno Larsen (billionai) { 7207058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 72137f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 72237f219c8SBruno Larsen (billionai) } 72337f219c8SBruno Larsen (billionai) 724a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 72537f219c8SBruno Larsen (billionai) { 7267058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 72737f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 72837f219c8SBruno Larsen (billionai) } 72937f219c8SBruno Larsen (billionai) 730a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 73137f219c8SBruno Larsen (billionai) { 7327058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 73337f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 73437f219c8SBruno Larsen (billionai) } 73537f219c8SBruno Larsen (billionai) 73637f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 73737f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 738a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 73937f219c8SBruno Larsen (billionai) { 74037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74237f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 74337f219c8SBruno Larsen (billionai) } 74437f219c8SBruno Larsen (billionai) 745a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 74637f219c8SBruno Larsen (billionai) { 74737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74937f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 75037f219c8SBruno Larsen (billionai) } 75137f219c8SBruno Larsen (billionai) 752a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 75337f219c8SBruno Larsen (billionai) { 7547058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 75537f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 75637f219c8SBruno Larsen (billionai) } 75737f219c8SBruno Larsen (billionai) 758a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 75937f219c8SBruno Larsen (billionai) { 7607058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 76137f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 76237f219c8SBruno Larsen (billionai) } 76337f219c8SBruno Larsen (billionai) 764a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 76537f219c8SBruno Larsen (billionai) { 7667058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 76737f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 76837f219c8SBruno Larsen (billionai) } 76937f219c8SBruno Larsen (billionai) 770a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 77137f219c8SBruno Larsen (billionai) { 7727058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 77337f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 77437f219c8SBruno Larsen (billionai) } 77537f219c8SBruno Larsen (billionai) 77637f219c8SBruno Larsen (billionai) /* SDR1 */ 777a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 77837f219c8SBruno Larsen (billionai) { 77937f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 78037f219c8SBruno Larsen (billionai) } 78137f219c8SBruno Larsen (billionai) 78237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 78337f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 78437f219c8SBruno Larsen (billionai) /* PIDR */ 785a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 78637f219c8SBruno Larsen (billionai) { 78737f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) 795a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 79637f219c8SBruno Larsen (billionai) { 79737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 79837f219c8SBruno Larsen (billionai) } 79937f219c8SBruno Larsen (billionai) 800a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 80137f219c8SBruno Larsen (billionai) { 80237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 80337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 80437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 80537f219c8SBruno Larsen (billionai) } 806a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 80737f219c8SBruno Larsen (billionai) { 80837f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 80937f219c8SBruno Larsen (billionai) } 81037f219c8SBruno Larsen (billionai) 811a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 81237f219c8SBruno Larsen (billionai) { 81337f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 81437f219c8SBruno Larsen (billionai) } 81537f219c8SBruno Larsen (billionai) 81637f219c8SBruno Larsen (billionai) /* DPDES */ 817a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 81837f219c8SBruno Larsen (billionai) { 819*3401ea3cSNicholas Piggin if (!gen_serialize_core_lpar(ctx)) { 820d24e80b2SNicholas Piggin return; 821d24e80b2SNicholas Piggin } 822d24e80b2SNicholas Piggin 82337f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 82437f219c8SBruno Larsen (billionai) } 82537f219c8SBruno Larsen (billionai) 826a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 82737f219c8SBruno Larsen (billionai) { 828*3401ea3cSNicholas Piggin if (!gen_serialize_core_lpar(ctx)) { 829d24e80b2SNicholas Piggin return; 830d24e80b2SNicholas Piggin } 831d24e80b2SNicholas Piggin 83237f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 83337f219c8SBruno Larsen (billionai) } 83437f219c8SBruno Larsen (billionai) #endif 83537f219c8SBruno Larsen (billionai) #endif 83637f219c8SBruno Larsen (billionai) 83737f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 83837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 839a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 84037f219c8SBruno Larsen (billionai) { 841283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 84237f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 84337f219c8SBruno Larsen (billionai) } 84437f219c8SBruno Larsen (billionai) 845a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 84637f219c8SBruno Larsen (billionai) { 847283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 84837f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 84937f219c8SBruno Larsen (billionai) } 85037f219c8SBruno Larsen (billionai) 851a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 85237f219c8SBruno Larsen (billionai) { 853283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 85437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 85537f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 85637f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 857d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 85837f219c8SBruno Larsen (billionai) } 85937f219c8SBruno Larsen (billionai) 860a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 86137f219c8SBruno Larsen (billionai) { 862283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 86337f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 86437f219c8SBruno Larsen (billionai) } 86537f219c8SBruno Larsen (billionai) 866cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 867cbd8f17dSCédric Le Goater { 868283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 869cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 870cbd8f17dSCédric Le Goater } 871cbd8f17dSCédric Le Goater 872cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 873cbd8f17dSCédric Le Goater { 874283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 875cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 876cbd8f17dSCédric Le Goater } 877cbd8f17dSCédric Le Goater 878dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 879dd69d140SCédric Le Goater { 880dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 881dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 88247822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 883dd69d140SCédric Le Goater } 884dd69d140SCédric Le Goater 885a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 88637f219c8SBruno Larsen (billionai) { 887283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 88837f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 88937f219c8SBruno Larsen (billionai) } 89037f219c8SBruno Larsen (billionai) 891a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 89237f219c8SBruno Larsen (billionai) { 893283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 89437f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 89537f219c8SBruno Larsen (billionai) } 89637f219c8SBruno Larsen (billionai) #endif 89737f219c8SBruno Larsen (billionai) 898328c95fcSCédric Le Goater /* PIR */ 89937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 900a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 90137f219c8SBruno Larsen (billionai) { 90237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 90337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 90437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 90537f219c8SBruno Larsen (billionai) } 90637f219c8SBruno Larsen (billionai) #endif 90737f219c8SBruno Larsen (billionai) 90837f219c8SBruno Larsen (billionai) /* SPE specific registers */ 909a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 91037f219c8SBruno Larsen (billionai) { 91137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91237f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 91337f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 91437f219c8SBruno Larsen (billionai) } 91537f219c8SBruno Larsen (billionai) 916a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 91737f219c8SBruno Larsen (billionai) { 91837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 91937f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 92037f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92137f219c8SBruno Larsen (billionai) } 92237f219c8SBruno Larsen (billionai) 92337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 92437f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 925a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 92637f219c8SBruno Larsen (billionai) { 92737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 92937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 93037f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 93137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 93237f219c8SBruno Larsen (billionai) } 93337f219c8SBruno Larsen (billionai) 934a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 93537f219c8SBruno Larsen (billionai) { 93637f219c8SBruno Larsen (billionai) int sprn_offs; 93737f219c8SBruno Larsen (billionai) 93837f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 93937f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 94037f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 94137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 94237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 94337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 94437f219c8SBruno Larsen (billionai) } else { 9458e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9468e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9478e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 94837f219c8SBruno Larsen (billionai) return; 94937f219c8SBruno Larsen (billionai) } 95037f219c8SBruno Larsen (billionai) 95137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 95337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 95537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95637f219c8SBruno Larsen (billionai) } 95737f219c8SBruno Larsen (billionai) #endif 95837f219c8SBruno Larsen (billionai) 95937f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 96037f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 961a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 96237f219c8SBruno Larsen (billionai) { 96337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) 96737f219c8SBruno Larsen (billionai) /* 96837f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 96937f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97037f219c8SBruno Larsen (billionai) */ 97137f219c8SBruno Larsen (billionai) 97237f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97337f219c8SBruno Larsen (billionai) if (ctx->pr) { 97437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 97537f219c8SBruno Larsen (billionai) } else { 97637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97737f219c8SBruno Larsen (billionai) } 97837f219c8SBruno Larsen (billionai) 97937f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 98037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 98137f219c8SBruno Larsen (billionai) 98237f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98337f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 98437f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98537f219c8SBruno Larsen (billionai) 98637f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 98837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 98937f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 99037f219c8SBruno Larsen (billionai) } 99137f219c8SBruno Larsen (billionai) 992a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 99337f219c8SBruno Larsen (billionai) { 99437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 99537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 99637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 99737f219c8SBruno Larsen (billionai) 99837f219c8SBruno Larsen (billionai) /* 99937f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100137f219c8SBruno Larsen (billionai) */ 100237f219c8SBruno Larsen (billionai) 100337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 100537f219c8SBruno Larsen (billionai) 100637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 100737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 100837f219c8SBruno Larsen (billionai) 100937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 101137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101237f219c8SBruno Larsen (billionai) 101337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 101537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 101637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 101737f219c8SBruno Larsen (billionai) } 101837f219c8SBruno Larsen (billionai) 1019a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 102037f219c8SBruno Larsen (billionai) { 102137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 102237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 102337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 102437f219c8SBruno Larsen (billionai) 102537f219c8SBruno Larsen (billionai) /* 102637f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 102737f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 102837f219c8SBruno Larsen (billionai) */ 102937f219c8SBruno Larsen (billionai) 103037f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 103137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 103237f219c8SBruno Larsen (billionai) 103337f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 103437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 103537f219c8SBruno Larsen (billionai) 103637f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 103737f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 103837f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 103937f219c8SBruno Larsen (billionai) 104037f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 104137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 104237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 104337f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 104437f219c8SBruno Larsen (billionai) } 104537f219c8SBruno Larsen (billionai) #endif 104637f219c8SBruno Larsen (billionai) #endif 104737f219c8SBruno Larsen (billionai) 104837f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1049a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 105037f219c8SBruno Larsen (billionai) { 105137f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 105237f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 105337f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 105437f219c8SBruno Larsen (billionai) } 105537f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 105637f219c8SBruno Larsen (billionai) 105737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1058a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 105937f219c8SBruno Larsen (billionai) { 106037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106137f219c8SBruno Larsen (billionai) 106237f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 106337f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 106437f219c8SBruno Larsen (billionai) } 106537f219c8SBruno Larsen (billionai) 1066a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 106737f219c8SBruno Larsen (billionai) { 106837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106937f219c8SBruno Larsen (billionai) 107037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 107137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107237f219c8SBruno Larsen (billionai) } 107337f219c8SBruno Larsen (billionai) 1074a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 107537f219c8SBruno Larsen (billionai) { 107637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107737f219c8SBruno Larsen (billionai) 107837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 107937f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 108037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108137f219c8SBruno Larsen (billionai) } 108237f219c8SBruno Larsen (billionai) 1083a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 108437f219c8SBruno Larsen (billionai) { 108537f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 108637f219c8SBruno Larsen (billionai) } 108737f219c8SBruno Larsen (billionai) 1088a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 108937f219c8SBruno Larsen (billionai) { 10907058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 109137f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 109237f219c8SBruno Larsen (billionai) } 10937058ff52SRichard Henderson 1094a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 109537f219c8SBruno Larsen (billionai) { 109637f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 109737f219c8SBruno Larsen (billionai) } 10987058ff52SRichard Henderson 1099a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 110037f219c8SBruno Larsen (billionai) { 110137f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 110237f219c8SBruno Larsen (billionai) } 110337f219c8SBruno Larsen (billionai) 110437f219c8SBruno Larsen (billionai) #endif 110537f219c8SBruno Larsen (billionai) 110637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1107a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 110837f219c8SBruno Larsen (billionai) { 110937f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 111037f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 111137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 111237f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 111337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 111437f219c8SBruno Larsen (billionai) } 111537f219c8SBruno Larsen (billionai) 1116a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 111737f219c8SBruno Larsen (billionai) { 111837f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 111937f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 112037f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 112137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 112237f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 112337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 112437f219c8SBruno Larsen (billionai) } 112537f219c8SBruno Larsen (billionai) 112637f219c8SBruno Larsen (billionai) #endif 112737f219c8SBruno Larsen (billionai) 112837f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 112937f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 113037f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 113137f219c8SBruno Larsen (billionai) { 11327058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11337058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11347058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 113537f219c8SBruno Larsen (billionai) 113637f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 113737f219c8SBruno Larsen (billionai) } 113837f219c8SBruno Larsen (billionai) 113937f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 114037f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 114137f219c8SBruno Larsen (billionai) { 11427058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11437058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11447058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 114537f219c8SBruno Larsen (billionai) 114637f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 114737f219c8SBruno Larsen (billionai) } 114837f219c8SBruno Larsen (billionai) 1149a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 115037f219c8SBruno Larsen (billionai) { 115137f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 115237f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 115337f219c8SBruno Larsen (billionai) 115437f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 115537f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 115637f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 115737f219c8SBruno Larsen (billionai) } 115837f219c8SBruno Larsen (billionai) 1159a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 116037f219c8SBruno Larsen (billionai) { 116137f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 116237f219c8SBruno Larsen (billionai) 116337f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 116437f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 116537f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 116637f219c8SBruno Larsen (billionai) } 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1169a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 117037f219c8SBruno Larsen (billionai) { 117137f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 117237f219c8SBruno Larsen (billionai) 117337f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 117437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 117537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 117637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 117737f219c8SBruno Larsen (billionai) } 117837f219c8SBruno Larsen (billionai) 1179b25f2ffaSNicholas Piggin void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1180b25f2ffaSNicholas Piggin { 1181b25f2ffaSNicholas Piggin gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1182b25f2ffaSNicholas Piggin } 1183b25f2ffaSNicholas Piggin 1184b25f2ffaSNicholas Piggin void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1185b25f2ffaSNicholas Piggin { 1186b25f2ffaSNicholas Piggin gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1187b25f2ffaSNicholas Piggin } 1188b25f2ffaSNicholas Piggin 1189a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 119037f219c8SBruno Larsen (billionai) { 1191c32654afSNicholas Piggin translator_io_start(&ctx->base); 119237f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 119337f219c8SBruno Larsen (billionai) } 119437f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 119537f219c8SBruno Larsen (billionai) 1196a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 119737f219c8SBruno Larsen (billionai) { 119837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 119937f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 120037f219c8SBruno Larsen (billionai) } 120137f219c8SBruno Larsen (billionai) 1202a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 120337f219c8SBruno Larsen (billionai) { 120437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 120537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 120637f219c8SBruno Larsen (billionai) } 120737f219c8SBruno Larsen (billionai) 1208a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 120937f219c8SBruno Larsen (billionai) { 121037f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121137f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 121237f219c8SBruno Larsen (billionai) } 121337f219c8SBruno Larsen (billionai) 1214a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 121537f219c8SBruno Larsen (billionai) { 121637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 121837f219c8SBruno Larsen (billionai) } 121937f219c8SBruno Larsen (billionai) 1220a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 122137f219c8SBruno Larsen (billionai) { 122237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122337f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 122437f219c8SBruno Larsen (billionai) } 122537f219c8SBruno Larsen (billionai) 1226a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 122737f219c8SBruno Larsen (billionai) { 122837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 122937f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 123037f219c8SBruno Larsen (billionai) } 123137f219c8SBruno Larsen (billionai) 1232a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 123337f219c8SBruno Larsen (billionai) { 123437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123537f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123637f219c8SBruno Larsen (billionai) } 123737f219c8SBruno Larsen (billionai) 1238a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 123937f219c8SBruno Larsen (billionai) { 124037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124137f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124237f219c8SBruno Larsen (billionai) } 124337f219c8SBruno Larsen (billionai) 1244a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 124537f219c8SBruno Larsen (billionai) { 124637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 124737f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124837f219c8SBruno Larsen (billionai) } 124937f219c8SBruno Larsen (billionai) 1250a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 125137f219c8SBruno Larsen (billionai) { 125237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 125337f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125437f219c8SBruno Larsen (billionai) } 1255395b5d5bSNicholas Miehlbradt 1256395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1257395b5d5bSNicholas Miehlbradt { 1258395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1259395b5d5bSNicholas Miehlbradt 1260395b5d5bSNicholas Miehlbradt /* 1261395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1262395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1263395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1264395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1265395b5d5bSNicholas Miehlbradt * 1266395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1267395b5d5bSNicholas Miehlbradt */ 1268395b5d5bSNicholas Miehlbradt 1269395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1270395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1271395b5d5bSNicholas Miehlbradt } 127237f219c8SBruno Larsen (billionai) #endif 127337f219c8SBruno Larsen (billionai) 1274fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1275fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1276fcf5ef2aSThomas Huth 1277fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1278fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1279fcf5ef2aSThomas Huth 1280fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1281fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1282fcf5ef2aSThomas Huth 1283fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1284fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1285fcf5ef2aSThomas Huth 1286fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1287fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1288fcf5ef2aSThomas Huth 1289fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1290fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1291fcf5ef2aSThomas Huth 1292fcf5ef2aSThomas Huth typedef struct opcode_t { 1293fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1294fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1295fcf5ef2aSThomas Huth unsigned char pad[4]; 1296fcf5ef2aSThomas Huth #endif 1297fcf5ef2aSThomas Huth opc_handler_t handler; 1298fcf5ef2aSThomas Huth const char *oname; 1299fcf5ef2aSThomas Huth } opcode_t; 1300fcf5ef2aSThomas Huth 13019f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 13029f0cf041SMatheus Ferst { 13039f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 13049f0cf041SMatheus Ferst } 13059f0cf041SMatheus Ferst 1306fcf5ef2aSThomas Huth /* Helpers for priv. check */ 13079f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1308fcf5ef2aSThomas Huth do { \ 13099f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1310fcf5ef2aSThomas Huth } while (0) 1311fcf5ef2aSThomas Huth 1312fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 13139f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 13149f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 13159f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1316fcf5ef2aSThomas Huth #else 13179f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1318fcf5ef2aSThomas Huth do { \ 1319fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 13209f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1321fcf5ef2aSThomas Huth } \ 1322fcf5ef2aSThomas Huth } while (0) 13239f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1324fcf5ef2aSThomas Huth do { \ 1325fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13269f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1327fcf5ef2aSThomas Huth } \ 1328fcf5ef2aSThomas Huth } while (0) 13299f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1330fcf5ef2aSThomas Huth do { \ 1331fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13329f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1333fcf5ef2aSThomas Huth } \ 1334fcf5ef2aSThomas Huth } while (0) 1335fcf5ef2aSThomas Huth #endif 1336fcf5ef2aSThomas Huth 13379f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1338fcf5ef2aSThomas Huth 1339fcf5ef2aSThomas Huth /*****************************************************************************/ 1340fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1341fcf5ef2aSThomas Huth 1342fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1343fcf5ef2aSThomas Huth { \ 1344fcf5ef2aSThomas Huth .opc1 = op1, \ 1345fcf5ef2aSThomas Huth .opc2 = op2, \ 1346fcf5ef2aSThomas Huth .opc3 = op3, \ 1347fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1348fcf5ef2aSThomas Huth .handler = { \ 1349fcf5ef2aSThomas Huth .inval1 = invl, \ 1350fcf5ef2aSThomas Huth .type = _typ, \ 1351fcf5ef2aSThomas Huth .type2 = _typ2, \ 1352fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1353fcf5ef2aSThomas Huth }, \ 1354fcf5ef2aSThomas Huth .oname = stringify(name), \ 1355fcf5ef2aSThomas Huth } 1356fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1357fcf5ef2aSThomas Huth { \ 1358fcf5ef2aSThomas Huth .opc1 = op1, \ 1359fcf5ef2aSThomas Huth .opc2 = op2, \ 1360fcf5ef2aSThomas Huth .opc3 = op3, \ 1361fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1362fcf5ef2aSThomas Huth .handler = { \ 1363fcf5ef2aSThomas Huth .inval1 = invl1, \ 1364fcf5ef2aSThomas Huth .inval2 = invl2, \ 1365fcf5ef2aSThomas Huth .type = _typ, \ 1366fcf5ef2aSThomas Huth .type2 = _typ2, \ 1367fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1368fcf5ef2aSThomas Huth }, \ 1369fcf5ef2aSThomas Huth .oname = stringify(name), \ 1370fcf5ef2aSThomas Huth } 1371fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1372fcf5ef2aSThomas Huth { \ 1373fcf5ef2aSThomas Huth .opc1 = op1, \ 1374fcf5ef2aSThomas Huth .opc2 = op2, \ 1375fcf5ef2aSThomas Huth .opc3 = op3, \ 1376fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1377fcf5ef2aSThomas Huth .handler = { \ 1378fcf5ef2aSThomas Huth .inval1 = invl, \ 1379fcf5ef2aSThomas Huth .type = _typ, \ 1380fcf5ef2aSThomas Huth .type2 = _typ2, \ 1381fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1382fcf5ef2aSThomas Huth }, \ 1383fcf5ef2aSThomas Huth .oname = onam, \ 1384fcf5ef2aSThomas Huth } 1385fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1386fcf5ef2aSThomas Huth { \ 1387fcf5ef2aSThomas Huth .opc1 = op1, \ 1388fcf5ef2aSThomas Huth .opc2 = op2, \ 1389fcf5ef2aSThomas Huth .opc3 = op3, \ 1390fcf5ef2aSThomas Huth .opc4 = op4, \ 1391fcf5ef2aSThomas Huth .handler = { \ 1392fcf5ef2aSThomas Huth .inval1 = invl, \ 1393fcf5ef2aSThomas Huth .type = _typ, \ 1394fcf5ef2aSThomas Huth .type2 = _typ2, \ 1395fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1396fcf5ef2aSThomas Huth }, \ 1397fcf5ef2aSThomas Huth .oname = stringify(name), \ 1398fcf5ef2aSThomas Huth } 1399fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1400fcf5ef2aSThomas Huth { \ 1401fcf5ef2aSThomas Huth .opc1 = op1, \ 1402fcf5ef2aSThomas Huth .opc2 = op2, \ 1403fcf5ef2aSThomas Huth .opc3 = op3, \ 1404fcf5ef2aSThomas Huth .opc4 = op4, \ 1405fcf5ef2aSThomas Huth .handler = { \ 1406fcf5ef2aSThomas Huth .inval1 = invl, \ 1407fcf5ef2aSThomas Huth .type = _typ, \ 1408fcf5ef2aSThomas Huth .type2 = _typ2, \ 1409fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1410fcf5ef2aSThomas Huth }, \ 1411fcf5ef2aSThomas Huth .oname = onam, \ 1412fcf5ef2aSThomas Huth } 1413fcf5ef2aSThomas Huth 1414fcf5ef2aSThomas Huth /* Invalid instruction */ 1415fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1416fcf5ef2aSThomas Huth { 1417fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1418fcf5ef2aSThomas Huth } 1419fcf5ef2aSThomas Huth 1420fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1421fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1422fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1423fcf5ef2aSThomas Huth .type = PPC_NONE, 1424fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1425fcf5ef2aSThomas Huth .handler = gen_invalid, 1426fcf5ef2aSThomas Huth }; 1427fcf5ef2aSThomas Huth 1428fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1429fcf5ef2aSThomas Huth 1430fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1431fcf5ef2aSThomas Huth { 1432fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1433b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1434b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1435fcf5ef2aSThomas Huth 1436b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1437b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1438efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1439efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1440b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1441efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1442efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1443b62b3686Spbonzini@redhat.com 1444b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1445fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1446b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1447fcf5ef2aSThomas Huth } 1448fcf5ef2aSThomas Huth 1449fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1450fcf5ef2aSThomas Huth { 14517058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1452fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1453fcf5ef2aSThomas Huth } 1454fcf5ef2aSThomas Huth 1455fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1456fcf5ef2aSThomas Huth { 1457fcf5ef2aSThomas Huth TCGv t0, t1; 1458fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1459fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1460fcf5ef2aSThomas Huth if (s) { 1461fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1462fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1463fcf5ef2aSThomas Huth } else { 1464fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1465fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1466fcf5ef2aSThomas Huth } 1467fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1468fcf5ef2aSThomas Huth } 1469fcf5ef2aSThomas Huth 1470fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1471fcf5ef2aSThomas Huth { 14727058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1473fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1474fcf5ef2aSThomas Huth } 1475fcf5ef2aSThomas Huth 1476fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1477fcf5ef2aSThomas Huth { 1478fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1479fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1480fcf5ef2aSThomas Huth } else { 1481fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1482fcf5ef2aSThomas Huth } 1483fcf5ef2aSThomas Huth } 1484fcf5ef2aSThomas Huth 1485fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1486fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1487fcf5ef2aSThomas Huth { 1488fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1489fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1490fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1491fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1492fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1493fcf5ef2aSThomas Huth 1494fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1495fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1496fcf5ef2aSThomas Huth 1497fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1498fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1499fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1500fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1501fcf5ef2aSThomas Huth 1502fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1503fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1504fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1505fcf5ef2aSThomas Huth 1506fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1507fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1508fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1509fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1510fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1511fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1512fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1513fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1514fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1515fcf5ef2aSThomas Huth } 1516efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1517fcf5ef2aSThomas Huth } 1518fcf5ef2aSThomas Huth 1519fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1520fcf5ef2aSThomas Huth /* cmpeqb */ 1521fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1522fcf5ef2aSThomas Huth { 1523fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1524fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1525fcf5ef2aSThomas Huth } 1526fcf5ef2aSThomas Huth #endif 1527fcf5ef2aSThomas Huth 1528fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1529fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1530fcf5ef2aSThomas Huth { 1531fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1532fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1533fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1534fcf5ef2aSThomas Huth TCGv zr; 1535fcf5ef2aSThomas Huth 1536fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1537fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1538fcf5ef2aSThomas Huth 15397058ff52SRichard Henderson zr = tcg_constant_tl(0); 1540fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1541fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1542fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1543fcf5ef2aSThomas Huth } 1544fcf5ef2aSThomas Huth 1545fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1546fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1547fcf5ef2aSThomas Huth { 1548fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1549fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1550fcf5ef2aSThomas Huth } 1551fcf5ef2aSThomas Huth 1552fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1553fcf5ef2aSThomas Huth 1554fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1555fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1556fcf5ef2aSThomas Huth { 1557fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1558fcf5ef2aSThomas Huth 1559fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1560fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1561fcf5ef2aSThomas Huth if (sub) { 1562fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1563fcf5ef2aSThomas Huth } else { 1564fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1565fcf5ef2aSThomas Huth } 1566fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1567dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1568dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1569dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1570fcf5ef2aSThomas Huth } 1571dc0ad844SNikunj A Dadhania } else { 1572dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1573dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1574dc0ad844SNikunj A Dadhania } 157538a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1576dc0ad844SNikunj A Dadhania } 1577fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1578fcf5ef2aSThomas Huth } 1579fcf5ef2aSThomas Huth 15806b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15816b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15824c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15836b10d008SNikunj A Dadhania { 15846b10d008SNikunj A Dadhania TCGv t0; 15856b10d008SNikunj A Dadhania 15866b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 15876b10d008SNikunj A Dadhania return; 15886b10d008SNikunj A Dadhania } 15896b10d008SNikunj A Dadhania 15906b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 159133903d0aSNikunj A Dadhania if (sub) { 159233903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 159333903d0aSNikunj A Dadhania } else { 15946b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 159533903d0aSNikunj A Dadhania } 15966b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 15974c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 15986b10d008SNikunj A Dadhania } 15996b10d008SNikunj A Dadhania 1600fcf5ef2aSThomas Huth /* Common add function */ 1601fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16024c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16034c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1604fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1605fcf5ef2aSThomas Huth { 1606fcf5ef2aSThomas Huth TCGv t0 = ret; 1607fcf5ef2aSThomas Huth 1608fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1609fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1610fcf5ef2aSThomas Huth } 1611fcf5ef2aSThomas Huth 1612fcf5ef2aSThomas Huth if (compute_ca) { 1613fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1614efe843d8SDavid Gibson /* 1615efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1616efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1617efe843d8SDavid Gibson * produce the carry into bit 32. 1618efe843d8SDavid Gibson */ 1619fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1620fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1621fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1622fcf5ef2aSThomas Huth if (add_ca) { 16234c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1624fcf5ef2aSThomas Huth } 16254c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 16264c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16276b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16284c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16296b10d008SNikunj A Dadhania } 1630fcf5ef2aSThomas Huth } else { 16317058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 1632fcf5ef2aSThomas Huth if (add_ca) { 16334c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16344c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1635fcf5ef2aSThomas Huth } else { 16364c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1637fcf5ef2aSThomas Huth } 16384c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1639fcf5ef2aSThomas Huth } 1640fcf5ef2aSThomas Huth } else { 1641fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1642fcf5ef2aSThomas Huth if (add_ca) { 16434c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1644fcf5ef2aSThomas Huth } 1645fcf5ef2aSThomas Huth } 1646fcf5ef2aSThomas Huth 1647fcf5ef2aSThomas Huth if (compute_ov) { 1648fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1649fcf5ef2aSThomas Huth } 1650fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1651fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1652fcf5ef2aSThomas Huth } 1653fcf5ef2aSThomas Huth 165411f4e8f8SRichard Henderson if (t0 != ret) { 1655fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1656fcf5ef2aSThomas Huth } 1657fcf5ef2aSThomas Huth } 1658fcf5ef2aSThomas Huth /* Add functions with two operands */ 16594c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1660fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1661fcf5ef2aSThomas Huth { \ 1662fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1663fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16644c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1665fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16684c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1669fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1670fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1671fcf5ef2aSThomas Huth { \ 16727058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 1673fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1674fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16754c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1676fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1677fcf5ef2aSThomas Huth } 1678fcf5ef2aSThomas Huth 1679fcf5ef2aSThomas Huth /* add add. addo addo. */ 16804c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16814c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1682fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16834c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16844c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1685fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 16864c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 16874c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1688fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 16894c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 16904c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 16914c5920afSSuraj Jitindar Singh /* addex */ 16924c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1693fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 16944c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 16954c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1696fcf5ef2aSThomas Huth /* addic addic.*/ 1697fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1698fcf5ef2aSThomas Huth { 16997058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1700fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17014c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1702fcf5ef2aSThomas Huth } 1703fcf5ef2aSThomas Huth 1704fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1705fcf5ef2aSThomas Huth { 1706fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1707fcf5ef2aSThomas Huth } 1708fcf5ef2aSThomas Huth 1709fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1710fcf5ef2aSThomas Huth { 1711fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1712fcf5ef2aSThomas Huth } 1713fcf5ef2aSThomas Huth 1714fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1715fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1716fcf5ef2aSThomas Huth { 1717fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1718fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1719fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1720fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1721fcf5ef2aSThomas Huth 1722fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1723fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1724fcf5ef2aSThomas Huth if (sign) { 1725fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1726fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1727fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1728fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1729fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1730fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1731fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1732fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1733fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1734fcf5ef2aSThomas Huth } else { 1735fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1736fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1737fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1738fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1739fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1740fcf5ef2aSThomas Huth } 1741fcf5ef2aSThomas Huth if (compute_ov) { 1742fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1743c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1744c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1745c44027ffSNikunj A Dadhania } 1746fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1747fcf5ef2aSThomas Huth } 1748fcf5ef2aSThomas Huth 1749efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1750fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1751fcf5ef2aSThomas Huth } 1752efe843d8SDavid Gibson } 1753fcf5ef2aSThomas Huth /* Div functions */ 1754fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1755fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1756fcf5ef2aSThomas Huth { \ 1757fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1758fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1759fcf5ef2aSThomas Huth sign, compute_ov); \ 1760fcf5ef2aSThomas Huth } 1761fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1762fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1763fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1764fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1765fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1766fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1767fcf5ef2aSThomas Huth 1768fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1769fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1770fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1771fcf5ef2aSThomas Huth { \ 17727058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1773fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1774fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1775fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1776fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1777fcf5ef2aSThomas Huth } \ 1778fcf5ef2aSThomas Huth } 1779fcf5ef2aSThomas Huth 1780fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1781fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1782fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1783fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1784fcf5ef2aSThomas Huth 1785fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1786fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1787fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1788fcf5ef2aSThomas Huth { 1789fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1790fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1791fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1792fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1793fcf5ef2aSThomas Huth 1794fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1795fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1796fcf5ef2aSThomas Huth if (sign) { 1797fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1798fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1799fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1800fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1801fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1802fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1803fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1804fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1805fcf5ef2aSThomas Huth } else { 1806fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1807fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1808fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1809fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1810fcf5ef2aSThomas Huth } 1811fcf5ef2aSThomas Huth if (compute_ov) { 1812fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1813c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1814c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1815c44027ffSNikunj A Dadhania } 1816fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1817fcf5ef2aSThomas Huth } 1818fcf5ef2aSThomas Huth 1819efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1820fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1821fcf5ef2aSThomas Huth } 1822efe843d8SDavid Gibson } 1823fcf5ef2aSThomas Huth 1824fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1825fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1826fcf5ef2aSThomas Huth { \ 1827fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1828fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1829fcf5ef2aSThomas Huth sign, compute_ov); \ 1830fcf5ef2aSThomas Huth } 1831c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1832fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1833fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1834c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1835fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1836fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1837fcf5ef2aSThomas Huth 1838fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1839fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1840fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1841fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1842fcf5ef2aSThomas Huth #endif 1843fcf5ef2aSThomas Huth 1844fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1845fcf5ef2aSThomas Huth TCGv arg2, int sign) 1846fcf5ef2aSThomas Huth { 1847fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1848fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1849fcf5ef2aSThomas Huth 1850fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1851fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1852fcf5ef2aSThomas Huth if (sign) { 1853fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1854fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1855fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1856fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1857fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1858fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1859fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1860fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1861fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1862fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1863fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1864fcf5ef2aSThomas Huth } else { 18657058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(1); 18667058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(0); 1867fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1868a253231fSRichard Henderson tcg_gen_remu_i32(t0, t0, t1); 1869a253231fSRichard Henderson tcg_gen_extu_i32_tl(ret, t0); 1870fcf5ef2aSThomas Huth } 1871fcf5ef2aSThomas Huth } 1872fcf5ef2aSThomas Huth 1873fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1874fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1875fcf5ef2aSThomas Huth { \ 1876fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1877fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1878fcf5ef2aSThomas Huth sign); \ 1879fcf5ef2aSThomas Huth } 1880fcf5ef2aSThomas Huth 1881fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1882fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1883fcf5ef2aSThomas Huth 1884fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1885fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1886fcf5ef2aSThomas Huth TCGv arg2, int sign) 1887fcf5ef2aSThomas Huth { 1888fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1889fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1890fcf5ef2aSThomas Huth 1891fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1892fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1893fcf5ef2aSThomas Huth if (sign) { 1894fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1895fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1896fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1897fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1898fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1899fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1900fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1901fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1902fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1903fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1904fcf5ef2aSThomas Huth } else { 19057058ff52SRichard Henderson TCGv_i64 t2 = tcg_constant_i64(1); 19067058ff52SRichard Henderson TCGv_i64 t3 = tcg_constant_i64(0); 1907fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1908fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1909fcf5ef2aSThomas Huth } 1910fcf5ef2aSThomas Huth } 1911fcf5ef2aSThomas Huth 1912fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1913fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1914fcf5ef2aSThomas Huth { \ 1915fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1916fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1917fcf5ef2aSThomas Huth sign); \ 1918fcf5ef2aSThomas Huth } 1919fcf5ef2aSThomas Huth 1920fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1921fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1922fcf5ef2aSThomas Huth #endif 1923fcf5ef2aSThomas Huth 1924fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1925fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1926fcf5ef2aSThomas Huth { 1927fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1928fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1929fcf5ef2aSThomas Huth 1930fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1931fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1932fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1933fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1934efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1935fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1936fcf5ef2aSThomas Huth } 1937efe843d8SDavid Gibson } 1938fcf5ef2aSThomas Huth 1939fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1940fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1941fcf5ef2aSThomas Huth { 1942fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1943fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1944fcf5ef2aSThomas Huth 1945fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1946fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1947fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1948fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1949efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1950fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1951fcf5ef2aSThomas Huth } 1952efe843d8SDavid Gibson } 1953fcf5ef2aSThomas Huth 1954fcf5ef2aSThomas Huth /* mullw mullw. */ 1955fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1956fcf5ef2aSThomas Huth { 1957fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1958fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1959fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1960fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1961fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1962fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1963fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1964fcf5ef2aSThomas Huth #else 1965fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1966fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1967fcf5ef2aSThomas Huth #endif 1968efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1969fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1970fcf5ef2aSThomas Huth } 1971efe843d8SDavid Gibson } 1972fcf5ef2aSThomas Huth 1973fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1974fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1975fcf5ef2aSThomas Huth { 1976fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1977fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1978fcf5ef2aSThomas Huth 1979fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1980fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1981fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1982fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1983fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1984fcf5ef2aSThomas Huth #else 1985fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1986fcf5ef2aSThomas Huth #endif 1987fcf5ef2aSThomas Huth 1988fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1989fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1990fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 199161aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 199261aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 199361aa9a69SNikunj A Dadhania } 1994fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1995fcf5ef2aSThomas Huth 1996efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1997fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1998fcf5ef2aSThomas Huth } 1999efe843d8SDavid Gibson } 2000fcf5ef2aSThomas Huth 2001fcf5ef2aSThomas Huth /* mulli */ 2002fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2003fcf5ef2aSThomas Huth { 2004fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2005fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2006fcf5ef2aSThomas Huth } 2007fcf5ef2aSThomas Huth 2008fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2009fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2010fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2011fcf5ef2aSThomas Huth { 2012fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2013fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2014fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2015fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2016fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2017fcf5ef2aSThomas Huth } 2018fcf5ef2aSThomas Huth } 2019fcf5ef2aSThomas Huth 2020fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2021fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2022fcf5ef2aSThomas Huth { 2023fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2024fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2025fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2026fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2027fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2028fcf5ef2aSThomas Huth } 2029fcf5ef2aSThomas Huth } 2030fcf5ef2aSThomas Huth 2031fcf5ef2aSThomas Huth /* mulld mulld. */ 2032fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2033fcf5ef2aSThomas Huth { 2034fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2035fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2036efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2037fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2038fcf5ef2aSThomas Huth } 2039efe843d8SDavid Gibson } 2040fcf5ef2aSThomas Huth 2041fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2042fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2043fcf5ef2aSThomas Huth { 2044fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2045fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2046fcf5ef2aSThomas Huth 2047fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2048fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2049fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2050fcf5ef2aSThomas Huth 2051fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2052fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 205361aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 205461aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 205561aa9a69SNikunj A Dadhania } 2056fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2057fcf5ef2aSThomas Huth 2058fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2059fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2060fcf5ef2aSThomas Huth } 2061fcf5ef2aSThomas Huth } 2062fcf5ef2aSThomas Huth #endif 2063fcf5ef2aSThomas Huth 2064fcf5ef2aSThomas Huth /* Common subf function */ 2065fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2066fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2067fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2068fcf5ef2aSThomas Huth { 2069fcf5ef2aSThomas Huth TCGv t0 = ret; 2070fcf5ef2aSThomas Huth 2071fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2072fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2073fcf5ef2aSThomas Huth } 2074fcf5ef2aSThomas Huth 2075fcf5ef2aSThomas Huth if (compute_ca) { 2076fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2077fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2078efe843d8SDavid Gibson /* 2079efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2080efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2081efe843d8SDavid Gibson * produce the carry into bit 32. 2082efe843d8SDavid Gibson */ 2083fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2084fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2085fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2086fcf5ef2aSThomas Huth if (add_ca) { 2087fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2088fcf5ef2aSThomas Huth } else { 2089fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2090fcf5ef2aSThomas Huth } 2091fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2092fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2093fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2094e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 209533903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 209633903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 209733903d0aSNikunj A Dadhania } 2098fcf5ef2aSThomas Huth } else if (add_ca) { 2099fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2100fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 21017058ff52SRichard Henderson zero = tcg_constant_tl(0); 2102fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2103fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21044c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2105fcf5ef2aSThomas Huth } else { 2106fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2107fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21084c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2109fcf5ef2aSThomas Huth } 2110fcf5ef2aSThomas Huth } else if (add_ca) { 2111efe843d8SDavid Gibson /* 2112efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2113efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2114efe843d8SDavid Gibson */ 2115fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2116fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2117fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2118fcf5ef2aSThomas Huth } else { 2119fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2120fcf5ef2aSThomas Huth } 2121fcf5ef2aSThomas Huth 2122fcf5ef2aSThomas Huth if (compute_ov) { 2123fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2124fcf5ef2aSThomas Huth } 2125fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2126fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2127fcf5ef2aSThomas Huth } 2128fcf5ef2aSThomas Huth 212911f4e8f8SRichard Henderson if (t0 != ret) { 2130fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2131fcf5ef2aSThomas Huth } 2132fcf5ef2aSThomas Huth } 2133fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2134fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2135fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2136fcf5ef2aSThomas Huth { \ 2137fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2138fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2139fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2140fcf5ef2aSThomas Huth } 2141fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2142fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2143fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2144fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2145fcf5ef2aSThomas Huth { \ 21467058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 2147fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2148fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2149fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2150fcf5ef2aSThomas Huth } 2151fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2152fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2153fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2154fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2155fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2156fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2157fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2158fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2159fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2160fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2161fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2162fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2163fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2164fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2165fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2166fcf5ef2aSThomas Huth 2167fcf5ef2aSThomas Huth /* subfic */ 2168fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2169fcf5ef2aSThomas Huth { 21707058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2171fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2172fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2173fcf5ef2aSThomas Huth } 2174fcf5ef2aSThomas Huth 2175fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2176fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2177fcf5ef2aSThomas Huth { 21787058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 2179fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2180fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2181fcf5ef2aSThomas Huth } 2182fcf5ef2aSThomas Huth 2183fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2184fcf5ef2aSThomas Huth { 21851480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 21861480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 21871480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 21881480d71cSNikunj A Dadhania } 2189fcf5ef2aSThomas Huth } 2190fcf5ef2aSThomas Huth 2191fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2192fcf5ef2aSThomas Huth { 2193fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2194fcf5ef2aSThomas Huth } 2195fcf5ef2aSThomas Huth 2196fcf5ef2aSThomas Huth /*** Integer logical ***/ 2197fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2198fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2199fcf5ef2aSThomas Huth { \ 2200fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2201fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2202fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2203fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2204fcf5ef2aSThomas Huth } 2205fcf5ef2aSThomas Huth 2206fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2207fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2208fcf5ef2aSThomas Huth { \ 2209fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2210fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2211fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2212fcf5ef2aSThomas Huth } 2213fcf5ef2aSThomas Huth 2214fcf5ef2aSThomas Huth /* and & and. */ 2215fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2216fcf5ef2aSThomas Huth /* andc & andc. */ 2217fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2218fcf5ef2aSThomas Huth 2219fcf5ef2aSThomas Huth /* andi. */ 2220fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2221fcf5ef2aSThomas Huth { 2222efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2223efe843d8SDavid Gibson UIMM(ctx->opcode)); 2224fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2225fcf5ef2aSThomas Huth } 2226fcf5ef2aSThomas Huth 2227fcf5ef2aSThomas Huth /* andis. */ 2228fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2229fcf5ef2aSThomas Huth { 2230efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2231efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2232fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2233fcf5ef2aSThomas Huth } 2234fcf5ef2aSThomas Huth 2235fcf5ef2aSThomas Huth /* cntlzw */ 2236fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2237fcf5ef2aSThomas Huth { 22389b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22399b8514e5SRichard Henderson 22409b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22419b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22429b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22439b8514e5SRichard Henderson 2244efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2245fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2246fcf5ef2aSThomas Huth } 2247efe843d8SDavid Gibson } 2248fcf5ef2aSThomas Huth 2249fcf5ef2aSThomas Huth /* cnttzw */ 2250fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2251fcf5ef2aSThomas Huth { 22529b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22539b8514e5SRichard Henderson 22549b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22559b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22569b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22579b8514e5SRichard Henderson 2258fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2259fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2260fcf5ef2aSThomas Huth } 2261fcf5ef2aSThomas Huth } 2262fcf5ef2aSThomas Huth 2263fcf5ef2aSThomas Huth /* eqv & eqv. */ 2264fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2265fcf5ef2aSThomas Huth /* extsb & extsb. */ 2266fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2267fcf5ef2aSThomas Huth /* extsh & extsh. */ 2268fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2269fcf5ef2aSThomas Huth /* nand & nand. */ 2270fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2271fcf5ef2aSThomas Huth /* nor & nor. */ 2272fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2273fcf5ef2aSThomas Huth 2274fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2275fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2276fcf5ef2aSThomas Huth { 22777058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(0); 2278fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2279fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2280fcf5ef2aSThomas Huth 2281fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2282b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2283fcf5ef2aSThomas Huth } 2284fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2285fcf5ef2aSThomas Huth 2286fcf5ef2aSThomas Huth /* or & or. */ 2287fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2288fcf5ef2aSThomas Huth { 2289fcf5ef2aSThomas Huth int rs, ra, rb; 2290fcf5ef2aSThomas Huth 2291fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2292fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2293fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2294fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2295fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2296efe843d8SDavid Gibson if (rs != rb) { 2297fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2298efe843d8SDavid Gibson } else { 2299fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2300efe843d8SDavid Gibson } 2301efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2302fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2303efe843d8SDavid Gibson } 2304fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2305fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2306fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2307fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2308fcf5ef2aSThomas Huth int prio = 0; 2309fcf5ef2aSThomas Huth 2310fcf5ef2aSThomas Huth switch (rs) { 2311fcf5ef2aSThomas Huth case 1: 2312fcf5ef2aSThomas Huth /* Set process priority to low */ 2313fcf5ef2aSThomas Huth prio = 2; 2314fcf5ef2aSThomas Huth break; 2315fcf5ef2aSThomas Huth case 6: 2316fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2317fcf5ef2aSThomas Huth prio = 3; 2318fcf5ef2aSThomas Huth break; 2319fcf5ef2aSThomas Huth case 2: 2320fcf5ef2aSThomas Huth /* Set process priority to normal */ 2321fcf5ef2aSThomas Huth prio = 4; 2322fcf5ef2aSThomas Huth break; 2323fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2324fcf5ef2aSThomas Huth case 31: 2325fcf5ef2aSThomas Huth if (!ctx->pr) { 2326fcf5ef2aSThomas Huth /* Set process priority to very low */ 2327fcf5ef2aSThomas Huth prio = 1; 2328fcf5ef2aSThomas Huth } 2329fcf5ef2aSThomas Huth break; 2330fcf5ef2aSThomas Huth case 5: 2331fcf5ef2aSThomas Huth if (!ctx->pr) { 2332fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2333fcf5ef2aSThomas Huth prio = 5; 2334fcf5ef2aSThomas Huth } 2335fcf5ef2aSThomas Huth break; 2336fcf5ef2aSThomas Huth case 3: 2337fcf5ef2aSThomas Huth if (!ctx->pr) { 2338fcf5ef2aSThomas Huth /* Set process priority to high */ 2339fcf5ef2aSThomas Huth prio = 6; 2340fcf5ef2aSThomas Huth } 2341fcf5ef2aSThomas Huth break; 2342fcf5ef2aSThomas Huth case 7: 2343fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2344fcf5ef2aSThomas Huth /* Set process priority to very high */ 2345fcf5ef2aSThomas Huth prio = 7; 2346fcf5ef2aSThomas Huth } 2347fcf5ef2aSThomas Huth break; 2348fcf5ef2aSThomas Huth #endif 2349fcf5ef2aSThomas Huth default: 2350fcf5ef2aSThomas Huth break; 2351fcf5ef2aSThomas Huth } 2352fcf5ef2aSThomas Huth if (prio) { 2353fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2354fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2355fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2356fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2357fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2358fcf5ef2aSThomas Huth } 2359fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2360efe843d8SDavid Gibson /* 2361efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2362efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2363efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2364efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2365fcf5ef2aSThomas Huth */ 2366fcf5ef2aSThomas Huth gen_pause(ctx); 2367fcf5ef2aSThomas Huth #endif 2368fcf5ef2aSThomas Huth #endif 2369fcf5ef2aSThomas Huth } 2370fcf5ef2aSThomas Huth } 2371fcf5ef2aSThomas Huth /* orc & orc. */ 2372fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2373fcf5ef2aSThomas Huth 2374fcf5ef2aSThomas Huth /* xor & xor. */ 2375fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2376fcf5ef2aSThomas Huth { 2377fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2378efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2379efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2380efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2381efe843d8SDavid Gibson } else { 2382fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2383efe843d8SDavid Gibson } 2384efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2385fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2386fcf5ef2aSThomas Huth } 2387efe843d8SDavid Gibson } 2388fcf5ef2aSThomas Huth 2389fcf5ef2aSThomas Huth /* ori */ 2390fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2391fcf5ef2aSThomas Huth { 2392fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2393fcf5ef2aSThomas Huth 2394fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2395fcf5ef2aSThomas Huth return; 2396fcf5ef2aSThomas Huth } 2397fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2398fcf5ef2aSThomas Huth } 2399fcf5ef2aSThomas Huth 2400fcf5ef2aSThomas Huth /* oris */ 2401fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2402fcf5ef2aSThomas Huth { 2403fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2404fcf5ef2aSThomas Huth 2405fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2406fcf5ef2aSThomas Huth /* NOP */ 2407fcf5ef2aSThomas Huth return; 2408fcf5ef2aSThomas Huth } 2409efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2410efe843d8SDavid Gibson uimm << 16); 2411fcf5ef2aSThomas Huth } 2412fcf5ef2aSThomas Huth 2413fcf5ef2aSThomas Huth /* xori */ 2414fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2415fcf5ef2aSThomas Huth { 2416fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2417fcf5ef2aSThomas Huth 2418fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2419fcf5ef2aSThomas Huth /* NOP */ 2420fcf5ef2aSThomas Huth return; 2421fcf5ef2aSThomas Huth } 2422fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2423fcf5ef2aSThomas Huth } 2424fcf5ef2aSThomas Huth 2425fcf5ef2aSThomas Huth /* xoris */ 2426fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2427fcf5ef2aSThomas Huth { 2428fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2429fcf5ef2aSThomas Huth 2430fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2431fcf5ef2aSThomas Huth /* NOP */ 2432fcf5ef2aSThomas Huth return; 2433fcf5ef2aSThomas Huth } 2434efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2435efe843d8SDavid Gibson uimm << 16); 2436fcf5ef2aSThomas Huth } 2437fcf5ef2aSThomas Huth 2438fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2439fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2440fcf5ef2aSThomas Huth { 2441fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2442fcf5ef2aSThomas Huth } 2443fcf5ef2aSThomas Huth 2444fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2445fcf5ef2aSThomas Huth { 244679770002SRichard Henderson #if defined(TARGET_PPC64) 2447fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 244879770002SRichard Henderson #else 244979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 245079770002SRichard Henderson #endif 2451fcf5ef2aSThomas Huth } 2452fcf5ef2aSThomas Huth 2453fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2454fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2455fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2456fcf5ef2aSThomas Huth { 245779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2458fcf5ef2aSThomas Huth } 2459fcf5ef2aSThomas Huth #endif 2460fcf5ef2aSThomas Huth 2461fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2462fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2463fcf5ef2aSThomas Huth { 2464fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2465fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2466fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2467fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2468fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2469fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2470fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2471fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2472fcf5ef2aSThomas Huth } 2473fcf5ef2aSThomas Huth 2474fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2475fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2476fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2477fcf5ef2aSThomas Huth { 2478fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2479fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2480fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2481fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2482fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2483fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2484fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2485fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2486fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2487fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2488fcf5ef2aSThomas Huth } 2489fcf5ef2aSThomas Huth #endif 2490fcf5ef2aSThomas Huth 2491fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2492fcf5ef2aSThomas Huth /* bpermd */ 2493fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2494fcf5ef2aSThomas Huth { 2495fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2496fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2497fcf5ef2aSThomas Huth } 2498fcf5ef2aSThomas Huth #endif 2499fcf5ef2aSThomas Huth 2500fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2501fcf5ef2aSThomas Huth /* extsw & extsw. */ 2502fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2503fcf5ef2aSThomas Huth 2504fcf5ef2aSThomas Huth /* cntlzd */ 2505fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2506fcf5ef2aSThomas Huth { 25079b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2508efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2509fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2510fcf5ef2aSThomas Huth } 2511efe843d8SDavid Gibson } 2512fcf5ef2aSThomas Huth 2513fcf5ef2aSThomas Huth /* cnttzd */ 2514fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2515fcf5ef2aSThomas Huth { 25169b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2517fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2518fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2519fcf5ef2aSThomas Huth } 2520fcf5ef2aSThomas Huth } 2521fcf5ef2aSThomas Huth 2522fcf5ef2aSThomas Huth /* darn */ 2523fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2524fcf5ef2aSThomas Huth { 2525fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2526fcf5ef2aSThomas Huth 25277e4357f6SRichard Henderson if (l > 2) { 25287e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25297e4357f6SRichard Henderson } else { 2530283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 2531fcf5ef2aSThomas Huth if (l == 0) { 2532fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25337e4357f6SRichard Henderson } else { 2534fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2535fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25367e4357f6SRichard Henderson } 2537fcf5ef2aSThomas Huth } 2538fcf5ef2aSThomas Huth } 2539fcf5ef2aSThomas Huth #endif 2540fcf5ef2aSThomas Huth 2541fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2542fcf5ef2aSThomas Huth 2543fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2544fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2545fcf5ef2aSThomas Huth { 2546fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2547fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2548fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2549fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2550fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2551fcf5ef2aSThomas Huth 2552fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2553fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2554fcf5ef2aSThomas Huth } else { 2555fcf5ef2aSThomas Huth target_ulong mask; 2556c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2557fcf5ef2aSThomas Huth TCGv t1; 2558fcf5ef2aSThomas Huth 2559fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2560fcf5ef2aSThomas Huth mb += 32; 2561fcf5ef2aSThomas Huth me += 32; 2562fcf5ef2aSThomas Huth #endif 2563fcf5ef2aSThomas Huth mask = MASK(mb, me); 2564fcf5ef2aSThomas Huth 2565c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2566c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2567c4f6a4a3SDaniele Buono mask_in_32b = false; 2568c4f6a4a3SDaniele Buono } 2569c4f6a4a3SDaniele Buono #endif 2570fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2571c4f6a4a3SDaniele Buono if (mask_in_32b) { 2572fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2573fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2574fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2575fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2576fcf5ef2aSThomas Huth } else { 2577fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2578fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2579fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2580fcf5ef2aSThomas Huth #else 2581fcf5ef2aSThomas Huth g_assert_not_reached(); 2582fcf5ef2aSThomas Huth #endif 2583fcf5ef2aSThomas Huth } 2584fcf5ef2aSThomas Huth 2585fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2586fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2587fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2588fcf5ef2aSThomas Huth } 2589fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2590fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2591fcf5ef2aSThomas Huth } 2592fcf5ef2aSThomas Huth } 2593fcf5ef2aSThomas Huth 2594fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2595fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2596fcf5ef2aSThomas Huth { 2597fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2598fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 25997b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26007b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26017b4d326fSRichard Henderson int me = ME(ctx->opcode); 26027b4d326fSRichard Henderson int len = me - mb + 1; 26037b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2604fcf5ef2aSThomas Huth 26057b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26067b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26077b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26087b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2609fcf5ef2aSThomas Huth } else { 2610fcf5ef2aSThomas Huth target_ulong mask; 2611c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2612fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2613fcf5ef2aSThomas Huth mb += 32; 2614fcf5ef2aSThomas Huth me += 32; 2615fcf5ef2aSThomas Huth #endif 2616fcf5ef2aSThomas Huth mask = MASK(mb, me); 2617c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2618c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2619c4f6a4a3SDaniele Buono mask_in_32b = false; 2620c4f6a4a3SDaniele Buono } 2621c4f6a4a3SDaniele Buono #endif 2622c4f6a4a3SDaniele Buono if (mask_in_32b) { 26237b4d326fSRichard Henderson if (sh == 0) { 26247b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 262594f040aaSVitaly Chikunov } else { 2626fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2627fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2628fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2629fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2630fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 263194f040aaSVitaly Chikunov } 2632fcf5ef2aSThomas Huth } else { 2633fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2634fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2635fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2636fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2637fcf5ef2aSThomas Huth #else 2638fcf5ef2aSThomas Huth g_assert_not_reached(); 2639fcf5ef2aSThomas Huth #endif 2640fcf5ef2aSThomas Huth } 2641fcf5ef2aSThomas Huth } 2642fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2643fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2644fcf5ef2aSThomas Huth } 2645fcf5ef2aSThomas Huth } 2646fcf5ef2aSThomas Huth 2647fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2648fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2649fcf5ef2aSThomas Huth { 2650fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2651fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2652fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2653fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2654fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2655fcf5ef2aSThomas Huth target_ulong mask; 2656c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2657fcf5ef2aSThomas Huth 2658fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2659fcf5ef2aSThomas Huth mb += 32; 2660fcf5ef2aSThomas Huth me += 32; 2661fcf5ef2aSThomas Huth #endif 2662fcf5ef2aSThomas Huth mask = MASK(mb, me); 2663fcf5ef2aSThomas Huth 2664c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2665c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2666c4f6a4a3SDaniele Buono mask_in_32b = false; 2667c4f6a4a3SDaniele Buono } 2668c4f6a4a3SDaniele Buono #endif 2669c4f6a4a3SDaniele Buono if (mask_in_32b) { 2670fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2671fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2672fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2673fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2674fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2675fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2676fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2677fcf5ef2aSThomas Huth } else { 2678fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2679fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2680fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2681fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2682fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2683fcf5ef2aSThomas Huth #else 2684fcf5ef2aSThomas Huth g_assert_not_reached(); 2685fcf5ef2aSThomas Huth #endif 2686fcf5ef2aSThomas Huth } 2687fcf5ef2aSThomas Huth 2688fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2689fcf5ef2aSThomas Huth 2690fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2691fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2692fcf5ef2aSThomas Huth } 2693fcf5ef2aSThomas Huth } 2694fcf5ef2aSThomas Huth 2695fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2696fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2697fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2698fcf5ef2aSThomas Huth { \ 2699fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2700fcf5ef2aSThomas Huth } \ 2701fcf5ef2aSThomas Huth \ 2702fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2703fcf5ef2aSThomas Huth { \ 2704fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2705fcf5ef2aSThomas Huth } 2706fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2707fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2708fcf5ef2aSThomas Huth { \ 2709fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2710fcf5ef2aSThomas Huth } \ 2711fcf5ef2aSThomas Huth \ 2712fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2713fcf5ef2aSThomas Huth { \ 2714fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2715fcf5ef2aSThomas Huth } \ 2716fcf5ef2aSThomas Huth \ 2717fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2718fcf5ef2aSThomas Huth { \ 2719fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2720fcf5ef2aSThomas Huth } \ 2721fcf5ef2aSThomas Huth \ 2722fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2723fcf5ef2aSThomas Huth { \ 2724fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2725fcf5ef2aSThomas Huth } 2726fcf5ef2aSThomas Huth 2727fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2728fcf5ef2aSThomas Huth { 2729fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2730fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27317b4d326fSRichard Henderson int len = me - mb + 1; 27327b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2733fcf5ef2aSThomas Huth 27347b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27357b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27367b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27377b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2738fcf5ef2aSThomas Huth } else { 2739fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2740fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2741fcf5ef2aSThomas Huth } 2742fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2743fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2744fcf5ef2aSThomas Huth } 2745fcf5ef2aSThomas Huth } 2746fcf5ef2aSThomas Huth 2747fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2748fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2749fcf5ef2aSThomas Huth { 2750fcf5ef2aSThomas Huth uint32_t sh, mb; 2751fcf5ef2aSThomas Huth 2752fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2753fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2754fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2755fcf5ef2aSThomas Huth } 2756fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2757fcf5ef2aSThomas Huth 2758fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2759fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2760fcf5ef2aSThomas Huth { 2761fcf5ef2aSThomas Huth uint32_t sh, me; 2762fcf5ef2aSThomas Huth 2763fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2764fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2765fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2766fcf5ef2aSThomas Huth } 2767fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2768fcf5ef2aSThomas Huth 2769fcf5ef2aSThomas Huth /* rldic - rldic. */ 2770fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2771fcf5ef2aSThomas Huth { 2772fcf5ef2aSThomas Huth uint32_t sh, mb; 2773fcf5ef2aSThomas Huth 2774fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2775fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2776fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2777fcf5ef2aSThomas Huth } 2778fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2779fcf5ef2aSThomas Huth 2780fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2781fcf5ef2aSThomas Huth { 2782fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2783fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2784fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2785fcf5ef2aSThomas Huth TCGv t0; 2786fcf5ef2aSThomas Huth 2787fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2788fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2789fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2790fcf5ef2aSThomas Huth 2791fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2792fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2793fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2794fcf5ef2aSThomas Huth } 2795fcf5ef2aSThomas Huth } 2796fcf5ef2aSThomas Huth 2797fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2798fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2799fcf5ef2aSThomas Huth { 2800fcf5ef2aSThomas Huth uint32_t mb; 2801fcf5ef2aSThomas Huth 2802fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2803fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2804fcf5ef2aSThomas Huth } 2805fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2806fcf5ef2aSThomas Huth 2807fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2808fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2809fcf5ef2aSThomas Huth { 2810fcf5ef2aSThomas Huth uint32_t me; 2811fcf5ef2aSThomas Huth 2812fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2813fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2814fcf5ef2aSThomas Huth } 2815fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2816fcf5ef2aSThomas Huth 2817fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2818fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2819fcf5ef2aSThomas Huth { 2820fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2821fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2822fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2823fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2824fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2825fcf5ef2aSThomas Huth 2826fcf5ef2aSThomas Huth if (mb <= me) { 2827fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2828fcf5ef2aSThomas Huth } else { 2829fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2830fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2831fcf5ef2aSThomas Huth 2832fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2833fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2834fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2835fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2836fcf5ef2aSThomas Huth } 2837fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2838fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2839fcf5ef2aSThomas Huth } 2840fcf5ef2aSThomas Huth } 2841fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2842fcf5ef2aSThomas Huth #endif 2843fcf5ef2aSThomas Huth 2844fcf5ef2aSThomas Huth /*** Integer shift ***/ 2845fcf5ef2aSThomas Huth 2846fcf5ef2aSThomas Huth /* slw & slw. */ 2847fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2848fcf5ef2aSThomas Huth { 2849fcf5ef2aSThomas Huth TCGv t0, t1; 2850fcf5ef2aSThomas Huth 2851fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2852fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2853fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2854fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2855fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2856fcf5ef2aSThomas Huth #else 2857fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2858fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2859fcf5ef2aSThomas Huth #endif 2860fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2861fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2862fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2863fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2864fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2865efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2866fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2867fcf5ef2aSThomas Huth } 2868efe843d8SDavid Gibson } 2869fcf5ef2aSThomas Huth 2870fcf5ef2aSThomas Huth /* sraw & sraw. */ 2871fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2872fcf5ef2aSThomas Huth { 2873fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2874fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2875efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2876fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2877fcf5ef2aSThomas Huth } 2878efe843d8SDavid Gibson } 2879fcf5ef2aSThomas Huth 2880fcf5ef2aSThomas Huth /* srawi & srawi. */ 2881fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2882fcf5ef2aSThomas Huth { 2883fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2884fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2885fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2886fcf5ef2aSThomas Huth if (sh == 0) { 2887fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2888fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2889af1c259fSSandipan Das if (is_isa300(ctx)) { 2890af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2891af1c259fSSandipan Das } 2892fcf5ef2aSThomas Huth } else { 2893fcf5ef2aSThomas Huth TCGv t0; 2894fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2895fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2896fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2897fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2898fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2899fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2900af1c259fSSandipan Das if (is_isa300(ctx)) { 2901af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2902af1c259fSSandipan Das } 2903fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2904fcf5ef2aSThomas Huth } 2905fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2906fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2907fcf5ef2aSThomas Huth } 2908fcf5ef2aSThomas Huth } 2909fcf5ef2aSThomas Huth 2910fcf5ef2aSThomas Huth /* srw & srw. */ 2911fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2912fcf5ef2aSThomas Huth { 2913fcf5ef2aSThomas Huth TCGv t0, t1; 2914fcf5ef2aSThomas Huth 2915fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2916fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2917fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2918fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2919fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2920fcf5ef2aSThomas Huth #else 2921fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2922fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2923fcf5ef2aSThomas Huth #endif 2924fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2925fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2926fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2927fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2928fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2929efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2930fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2931fcf5ef2aSThomas Huth } 2932efe843d8SDavid Gibson } 2933fcf5ef2aSThomas Huth 2934fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2935fcf5ef2aSThomas Huth /* sld & sld. */ 2936fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2937fcf5ef2aSThomas Huth { 2938fcf5ef2aSThomas Huth TCGv t0, t1; 2939fcf5ef2aSThomas Huth 2940fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2941fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2942fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2943fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2944fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2945fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2946fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2947fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2948efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2949fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2950fcf5ef2aSThomas Huth } 2951efe843d8SDavid Gibson } 2952fcf5ef2aSThomas Huth 2953fcf5ef2aSThomas Huth /* srad & srad. */ 2954fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2955fcf5ef2aSThomas Huth { 2956fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2957fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2958efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2959fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2960fcf5ef2aSThomas Huth } 2961efe843d8SDavid Gibson } 2962fcf5ef2aSThomas Huth /* sradi & sradi. */ 2963fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2964fcf5ef2aSThomas Huth { 2965fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2966fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2967fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2968fcf5ef2aSThomas Huth if (sh == 0) { 2969fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2970fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2971af1c259fSSandipan Das if (is_isa300(ctx)) { 2972af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2973af1c259fSSandipan Das } 2974fcf5ef2aSThomas Huth } else { 2975fcf5ef2aSThomas Huth TCGv t0; 2976fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2977fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2978fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2979fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2980fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2981af1c259fSSandipan Das if (is_isa300(ctx)) { 2982af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2983af1c259fSSandipan Das } 2984fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2985fcf5ef2aSThomas Huth } 2986fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2987fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2988fcf5ef2aSThomas Huth } 2989fcf5ef2aSThomas Huth } 2990fcf5ef2aSThomas Huth 2991fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2992fcf5ef2aSThomas Huth { 2993fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2994fcf5ef2aSThomas Huth } 2995fcf5ef2aSThomas Huth 2996fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2997fcf5ef2aSThomas Huth { 2998fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2999fcf5ef2aSThomas Huth } 3000fcf5ef2aSThomas Huth 3001fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3002fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3003fcf5ef2aSThomas Huth { 3004fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3005fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3006fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3007fcf5ef2aSThomas Huth 3008fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3009fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3010fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3011fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3012fcf5ef2aSThomas Huth } 3013fcf5ef2aSThomas Huth } 3014fcf5ef2aSThomas Huth 3015fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3016fcf5ef2aSThomas Huth { 3017fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3018fcf5ef2aSThomas Huth } 3019fcf5ef2aSThomas Huth 3020fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3021fcf5ef2aSThomas Huth { 3022fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3023fcf5ef2aSThomas Huth } 3024fcf5ef2aSThomas Huth 3025fcf5ef2aSThomas Huth /* srd & srd. */ 3026fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3027fcf5ef2aSThomas Huth { 3028fcf5ef2aSThomas Huth TCGv t0, t1; 3029fcf5ef2aSThomas Huth 3030fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3031fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3032fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3033fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3034fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3035fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3036fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3037fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3038efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3039fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3040fcf5ef2aSThomas Huth } 3041efe843d8SDavid Gibson } 3042fcf5ef2aSThomas Huth #endif 3043fcf5ef2aSThomas Huth 3044fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3045fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3046fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3047fcf5ef2aSThomas Huth target_long maskl) 3048fcf5ef2aSThomas Huth { 3049fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3050fcf5ef2aSThomas Huth 3051fcf5ef2aSThomas Huth simm &= ~maskl; 3052fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3053fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3054fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3055fcf5ef2aSThomas Huth } 3056fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3057fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3058fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3059fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3060fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3061fcf5ef2aSThomas Huth } 3062fcf5ef2aSThomas Huth } else { 3063fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3064fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3065fcf5ef2aSThomas Huth } else { 3066fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3067fcf5ef2aSThomas Huth } 3068fcf5ef2aSThomas Huth } 3069fcf5ef2aSThomas Huth } 3070fcf5ef2aSThomas Huth 3071fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3072fcf5ef2aSThomas Huth { 3073fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3074fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3075fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3076fcf5ef2aSThomas Huth } else { 3077fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3078fcf5ef2aSThomas Huth } 3079fcf5ef2aSThomas Huth } else { 3080fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3081fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3082fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth } 3085fcf5ef2aSThomas Huth } 3086fcf5ef2aSThomas Huth 3087fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3088fcf5ef2aSThomas Huth { 3089fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3090fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3091fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3092fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3093fcf5ef2aSThomas Huth } else { 3094fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3095fcf5ef2aSThomas Huth } 3096fcf5ef2aSThomas Huth } 3097fcf5ef2aSThomas Huth 3098fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3099fcf5ef2aSThomas Huth target_long val) 3100fcf5ef2aSThomas Huth { 3101fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3102fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3103fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3104fcf5ef2aSThomas Huth } 3105fcf5ef2aSThomas Huth } 3106fcf5ef2aSThomas Huth 3107fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3108fcf5ef2aSThomas Huth { 3109fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3110fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3111fcf5ef2aSThomas Huth } 3112fcf5ef2aSThomas Huth 3113eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3114eb63efd9SFernando Eckhardt Valle { 3115eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3116eb63efd9SFernando Eckhardt Valle if (ra) { 3117eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3118eb63efd9SFernando Eckhardt Valle } else { 3119eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3120eb63efd9SFernando Eckhardt Valle } 3121eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3122eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3123eb63efd9SFernando Eckhardt Valle } 3124eb63efd9SFernando Eckhardt Valle return ea; 3125eb63efd9SFernando Eckhardt Valle } 3126eb63efd9SFernando Eckhardt Valle 3127fcf5ef2aSThomas Huth /*** Integer load ***/ 3128fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3129fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3130fcf5ef2aSThomas Huth 3131fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3132fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3133fcf5ef2aSThomas Huth TCGv val, \ 3134fcf5ef2aSThomas Huth TCGv addr) \ 3135fcf5ef2aSThomas Huth { \ 3136fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3137fcf5ef2aSThomas Huth } 3138fcf5ef2aSThomas Huth 3139fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3140fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3141fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3142fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3143fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3144fcf5ef2aSThomas Huth 3145fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3146fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3147fcf5ef2aSThomas Huth 3148fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3149fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3150fcf5ef2aSThomas Huth TCGv_i64 val, \ 3151fcf5ef2aSThomas Huth TCGv addr) \ 3152fcf5ef2aSThomas Huth { \ 3153fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3154fcf5ef2aSThomas Huth } 3155fcf5ef2aSThomas Huth 3156fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3157fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3158fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3159fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3160fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3161fcf5ef2aSThomas Huth 3162fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3163fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3164fcf5ef2aSThomas Huth #endif 3165fcf5ef2aSThomas Huth 3166fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3167fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3168fcf5ef2aSThomas Huth TCGv val, \ 3169fcf5ef2aSThomas Huth TCGv addr) \ 3170fcf5ef2aSThomas Huth { \ 3171fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3172fcf5ef2aSThomas Huth } 3173fcf5ef2aSThomas Huth 3174e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3175fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3176e8f4c8d6SRichard Henderson #endif 3177fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3178fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3179fcf5ef2aSThomas Huth 3180fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3181fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3182fcf5ef2aSThomas Huth 3183fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3184fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3185fcf5ef2aSThomas Huth TCGv_i64 val, \ 3186fcf5ef2aSThomas Huth TCGv addr) \ 3187fcf5ef2aSThomas Huth { \ 3188fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3189fcf5ef2aSThomas Huth } 3190fcf5ef2aSThomas Huth 3191fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3192fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3193fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3194fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3195fcf5ef2aSThomas Huth 3196fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3197fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3198fcf5ef2aSThomas Huth #endif 3199fcf5ef2aSThomas Huth 3200fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3201fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3202fcf5ef2aSThomas Huth { \ 3203fcf5ef2aSThomas Huth TCGv EA; \ 32049f0cf041SMatheus Ferst chk(ctx); \ 3205fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3206fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3207fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3208fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3209fcf5ef2aSThomas Huth } 3210fcf5ef2aSThomas Huth 3211fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3212fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3213fcf5ef2aSThomas Huth 3214fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3215fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3216fcf5ef2aSThomas Huth 321750728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 321850728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 321950728199SRoman Kapl { \ 322050728199SRoman Kapl TCGv EA; \ 32219f0cf041SMatheus Ferst CHK_SV(ctx); \ 322250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 322350728199SRoman Kapl EA = tcg_temp_new(); \ 322450728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 322550728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 322650728199SRoman Kapl } 322750728199SRoman Kapl 322850728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 322950728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 323050728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 323150728199SRoman Kapl #if defined(TARGET_PPC64) 3232fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 323350728199SRoman Kapl #endif 323450728199SRoman Kapl 3235fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3236fcf5ef2aSThomas Huth /* CI load/store variants */ 3237fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3238fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3239fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3240fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3241fcf5ef2aSThomas Huth #endif 3242fcf5ef2aSThomas Huth 3243fcf5ef2aSThomas Huth /*** Integer store ***/ 3244fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3245fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3246fcf5ef2aSThomas Huth { \ 3247fcf5ef2aSThomas Huth TCGv EA; \ 32489f0cf041SMatheus Ferst chk(ctx); \ 3249fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3250fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3251fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3252fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3253fcf5ef2aSThomas Huth } 3254fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3255fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3256fcf5ef2aSThomas Huth 3257fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3258fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3259fcf5ef2aSThomas Huth 326050728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 326150728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 326250728199SRoman Kapl { \ 326350728199SRoman Kapl TCGv EA; \ 32649f0cf041SMatheus Ferst CHK_SV(ctx); \ 326550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 326650728199SRoman Kapl EA = tcg_temp_new(); \ 326750728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 326850728199SRoman Kapl tcg_gen_qemu_st_tl( \ 326950728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 327050728199SRoman Kapl } 327150728199SRoman Kapl 327250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 327350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 327450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 327550728199SRoman Kapl #if defined(TARGET_PPC64) 3276fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 327750728199SRoman Kapl #endif 327850728199SRoman Kapl 3279fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3280fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3281fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3282fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3283fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3284fcf5ef2aSThomas Huth #endif 3285fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3286fcf5ef2aSThomas Huth 3287fcf5ef2aSThomas Huth /* lhbrx */ 3288fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3289fcf5ef2aSThomas Huth 3290fcf5ef2aSThomas Huth /* lwbrx */ 3291fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3292fcf5ef2aSThomas Huth 3293fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3294fcf5ef2aSThomas Huth /* ldbrx */ 3295fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3296fcf5ef2aSThomas Huth /* stdbrx */ 3297fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3298fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3299fcf5ef2aSThomas Huth 3300fcf5ef2aSThomas Huth /* sthbrx */ 3301fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3302fcf5ef2aSThomas Huth /* stwbrx */ 3303fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3304fcf5ef2aSThomas Huth 3305fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3306fcf5ef2aSThomas Huth 3307fcf5ef2aSThomas Huth /* lmw */ 3308fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3309fcf5ef2aSThomas Huth { 3310fcf5ef2aSThomas Huth TCGv t0; 3311fcf5ef2aSThomas Huth TCGv_i32 t1; 3312fcf5ef2aSThomas Huth 3313fcf5ef2aSThomas Huth if (ctx->le_mode) { 3314fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3315fcf5ef2aSThomas Huth return; 3316fcf5ef2aSThomas Huth } 3317fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3318fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33197058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 3320fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3321fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3322fcf5ef2aSThomas Huth } 3323fcf5ef2aSThomas Huth 3324fcf5ef2aSThomas Huth /* stmw */ 3325fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3326fcf5ef2aSThomas Huth { 3327fcf5ef2aSThomas Huth TCGv t0; 3328fcf5ef2aSThomas Huth TCGv_i32 t1; 3329fcf5ef2aSThomas Huth 3330fcf5ef2aSThomas Huth if (ctx->le_mode) { 3331fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3332fcf5ef2aSThomas Huth return; 3333fcf5ef2aSThomas Huth } 3334fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3335fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33367058ff52SRichard Henderson t1 = tcg_constant_i32(rS(ctx->opcode)); 3337fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3338fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3339fcf5ef2aSThomas Huth } 3340fcf5ef2aSThomas Huth 3341fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3342fcf5ef2aSThomas Huth 3343fcf5ef2aSThomas Huth /* lswi */ 3344efe843d8SDavid Gibson /* 3345efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3346efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3347efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3348efe843d8SDavid Gibson * spec... 3349fcf5ef2aSThomas Huth */ 3350fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3351fcf5ef2aSThomas Huth { 3352fcf5ef2aSThomas Huth TCGv t0; 3353fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3354fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3355fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3356fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3357fcf5ef2aSThomas Huth int nr; 3358fcf5ef2aSThomas Huth 3359fcf5ef2aSThomas Huth if (ctx->le_mode) { 3360fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3361fcf5ef2aSThomas Huth return; 3362fcf5ef2aSThomas Huth } 3363efe843d8SDavid Gibson if (nb == 0) { 3364fcf5ef2aSThomas Huth nb = 32; 3365efe843d8SDavid Gibson } 3366f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3367fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3368fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3369fcf5ef2aSThomas Huth return; 3370fcf5ef2aSThomas Huth } 3371fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3372fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3373fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 33747058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 33757058ff52SRichard Henderson t2 = tcg_constant_i32(start); 3376fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3377fcf5ef2aSThomas Huth } 3378fcf5ef2aSThomas Huth 3379fcf5ef2aSThomas Huth /* lswx */ 3380fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3381fcf5ef2aSThomas Huth { 3382fcf5ef2aSThomas Huth TCGv t0; 3383fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3384fcf5ef2aSThomas Huth 3385fcf5ef2aSThomas Huth if (ctx->le_mode) { 3386fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3387fcf5ef2aSThomas Huth return; 3388fcf5ef2aSThomas Huth } 3389fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3390fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3391fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 33927058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 33937058ff52SRichard Henderson t2 = tcg_constant_i32(rA(ctx->opcode)); 33947058ff52SRichard Henderson t3 = tcg_constant_i32(rB(ctx->opcode)); 3395fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3396fcf5ef2aSThomas Huth } 3397fcf5ef2aSThomas Huth 3398fcf5ef2aSThomas Huth /* stswi */ 3399fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3400fcf5ef2aSThomas Huth { 3401fcf5ef2aSThomas Huth TCGv t0; 3402fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3403fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3404fcf5ef2aSThomas Huth 3405fcf5ef2aSThomas Huth if (ctx->le_mode) { 3406fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3407fcf5ef2aSThomas Huth return; 3408fcf5ef2aSThomas Huth } 3409fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3410fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3411fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3412efe843d8SDavid Gibson if (nb == 0) { 3413fcf5ef2aSThomas Huth nb = 32; 3414efe843d8SDavid Gibson } 34157058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 34167058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3417fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3418fcf5ef2aSThomas Huth } 3419fcf5ef2aSThomas Huth 3420fcf5ef2aSThomas Huth /* stswx */ 3421fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3422fcf5ef2aSThomas Huth { 3423fcf5ef2aSThomas Huth TCGv t0; 3424fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3425fcf5ef2aSThomas Huth 3426fcf5ef2aSThomas Huth if (ctx->le_mode) { 3427fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3428fcf5ef2aSThomas Huth return; 3429fcf5ef2aSThomas Huth } 3430fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3431fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3432fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3433fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3434fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3435fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 34367058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3437fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3438fcf5ef2aSThomas Huth } 3439fcf5ef2aSThomas Huth 3440fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3441fcf5ef2aSThomas Huth /* eieio */ 3442fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3443fcf5ef2aSThomas Huth { 3444fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3445fcb830afSNicholas Piggin 3446fcb830afSNicholas Piggin /* 3447fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3448fcb830afSNicholas Piggin * operations in the set: 3449fcb830afSNicholas Piggin * - loads from CI memory. 3450fcb830afSNicholas Piggin * - stores to CI memory. 3451fcb830afSNicholas Piggin * - stores to WT memory. 3452fcb830afSNicholas Piggin * 3453fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3454fcb830afSNicholas Piggin * - stores to cacheble memory. 3455fcb830afSNicholas Piggin * 3456fcb830afSNicholas Piggin * It also serializes instructions: 3457fcb830afSNicholas Piggin * - dcbt and dcbst. 3458fcb830afSNicholas Piggin * 3459fcb830afSNicholas Piggin * It separately serializes: 3460fcb830afSNicholas Piggin * - tlbie and tlbsync. 3461fcb830afSNicholas Piggin * 3462fcb830afSNicholas Piggin * And separately serializes: 3463fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3464fcb830afSNicholas Piggin * 3465fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3466fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3467fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3468fcb830afSNicholas Piggin * serialization. 3469fcb830afSNicholas Piggin */ 3470c8fd8373SCédric Le Goater 3471c8fd8373SCédric Le Goater /* 3472c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3473c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3474c8fd8373SCédric Le Goater */ 3475c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3476c8fd8373SCédric Le Goater /* 3477c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3478c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3479c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3480c8fd8373SCédric Le Goater * complain to the user. 3481c8fd8373SCédric Le Goater */ 3482c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3483c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 34842c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3485c8fd8373SCédric Le Goater } else { 3486c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3487c8fd8373SCédric Le Goater } 3488c8fd8373SCédric Le Goater } 3489c8fd8373SCédric Le Goater 3490c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3491fcf5ef2aSThomas Huth } 3492fcf5ef2aSThomas Huth 3493fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3494fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3495fcf5ef2aSThomas Huth { 3496fcf5ef2aSThomas Huth TCGv_i32 t; 3497fcf5ef2aSThomas Huth TCGLabel *l; 3498fcf5ef2aSThomas Huth 3499fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3500fcf5ef2aSThomas Huth return; 3501fcf5ef2aSThomas Huth } 3502fcf5ef2aSThomas Huth l = gen_new_label(); 3503fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3504fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3505fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3506fcf5ef2aSThomas Huth if (global) { 3507fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3508fcf5ef2aSThomas Huth } else { 3509fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3510fcf5ef2aSThomas Huth } 3511fcf5ef2aSThomas Huth gen_set_label(l); 3512fcf5ef2aSThomas Huth } 3513fcf5ef2aSThomas Huth #else 3514fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3515fcf5ef2aSThomas Huth #endif 3516fcf5ef2aSThomas Huth 3517fcf5ef2aSThomas Huth /* isync */ 3518fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3519fcf5ef2aSThomas Huth { 3520fcf5ef2aSThomas Huth /* 3521fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3522fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3523fcf5ef2aSThomas Huth */ 3524fcf5ef2aSThomas Huth if (!ctx->pr) { 3525fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3526fcf5ef2aSThomas Huth } 35274771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3528d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3529fcf5ef2aSThomas Huth } 3530fcf5ef2aSThomas Huth 3531fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3532fcf5ef2aSThomas Huth 353314776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 35342a4e6c1bSRichard Henderson { 35352a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 35362a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 35372a4e6c1bSRichard Henderson 35382a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 35392a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 35402a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 35412a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 3542392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 35432a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 35442a4e6c1bSRichard Henderson } 35452a4e6c1bSRichard Henderson 3546fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3547fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3548fcf5ef2aSThomas Huth { \ 35492a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3550fcf5ef2aSThomas Huth } 3551fcf5ef2aSThomas Huth 3552fcf5ef2aSThomas Huth /* lwarx */ 3553fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3554fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3555fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3556fcf5ef2aSThomas Huth 355714776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 355820923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 355920923c1dSRichard Henderson { 356020923c1dSRichard Henderson TCGv t = tcg_temp_new(); 356120923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 356220923c1dSRichard Henderson TCGv u = tcg_temp_new(); 356320923c1dSRichard Henderson 356420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 356520923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 356620923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 356720923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 356820923c1dSRichard Henderson 356920923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 357020923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 357120923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 357220923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 357320923c1dSRichard Henderson 357420923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 357520923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 357620923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 357720923c1dSRichard Henderson } 357820923c1dSRichard Henderson 357914776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 358020ba8504SRichard Henderson { 358120ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 358220ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 358320923c1dSRichard Henderson int rt = rD(ctx->opcode); 358420923c1dSRichard Henderson bool need_serial; 358520ba8504SRichard Henderson TCGv src, dst; 358620ba8504SRichard Henderson 358720ba8504SRichard Henderson gen_addr_register(ctx, EA); 358820923c1dSRichard Henderson dst = cpu_gpr[rt]; 358920923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 359020ba8504SRichard Henderson 359120923c1dSRichard Henderson need_serial = false; 359220ba8504SRichard Henderson memop |= MO_ALIGN; 359320ba8504SRichard Henderson switch (gpr_FC) { 359420ba8504SRichard Henderson case 0: /* Fetch and add */ 359520ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 359620ba8504SRichard Henderson break; 359720ba8504SRichard Henderson case 1: /* Fetch and xor */ 359820ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 359920ba8504SRichard Henderson break; 360020ba8504SRichard Henderson case 2: /* Fetch and or */ 360120ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 360220ba8504SRichard Henderson break; 360320ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 360420ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 360520ba8504SRichard Henderson break; 3606b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3607b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3608b8ce0f86SRichard Henderson break; 3609b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3610b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3611b8ce0f86SRichard Henderson break; 3612b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3613b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3614b8ce0f86SRichard Henderson break; 3615b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3616b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3617b8ce0f86SRichard Henderson break; 361820ba8504SRichard Henderson case 8: /* Swap */ 361920ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 362020ba8504SRichard Henderson break; 362120923c1dSRichard Henderson 362220923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 362320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 362420923c1dSRichard Henderson need_serial = true; 362520923c1dSRichard Henderson } else { 362620923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 362720923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 362820923c1dSRichard Henderson 362920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 363020923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 363120923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 363220923c1dSRichard Henderson } else { 363320923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 363420923c1dSRichard Henderson } 363520923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 363620923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 363720923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 363820923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 363920923c1dSRichard Henderson } 364020ba8504SRichard Henderson break; 364120923c1dSRichard Henderson 364220923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 364320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 364420923c1dSRichard Henderson need_serial = true; 364520923c1dSRichard Henderson } else { 364620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 364720923c1dSRichard Henderson } 364820923c1dSRichard Henderson break; 364920923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 365020923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 365120923c1dSRichard Henderson need_serial = true; 365220923c1dSRichard Henderson } else { 365320923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 365420923c1dSRichard Henderson } 365520923c1dSRichard Henderson break; 365620923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 365720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 365820923c1dSRichard Henderson need_serial = true; 365920923c1dSRichard Henderson } else { 366020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 366120923c1dSRichard Henderson } 366220923c1dSRichard Henderson break; 366320923c1dSRichard Henderson 366420ba8504SRichard Henderson default: 366520ba8504SRichard Henderson /* invoke data storage error handler */ 366620ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 366720ba8504SRichard Henderson } 366820923c1dSRichard Henderson 366920923c1dSRichard Henderson if (need_serial) { 367020923c1dSRichard Henderson /* Restart with exclusive lock. */ 367120923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 367220923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 367320923c1dSRichard Henderson } 3674a68a6146SBalamuruhan S } 3675a68a6146SBalamuruhan S 367620ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 367720ba8504SRichard Henderson { 367820ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 367920ba8504SRichard Henderson } 368020ba8504SRichard Henderson 368120ba8504SRichard Henderson #ifdef TARGET_PPC64 368220ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 368320ba8504SRichard Henderson { 3684fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 368520ba8504SRichard Henderson } 3686a68a6146SBalamuruhan S #endif 3687a68a6146SBalamuruhan S 368814776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 36899deb041cSRichard Henderson { 36909deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 36919deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 36929deb041cSRichard Henderson TCGv src, discard; 36939deb041cSRichard Henderson 36949deb041cSRichard Henderson gen_addr_register(ctx, EA); 36959deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 36969deb041cSRichard Henderson discard = tcg_temp_new(); 36979deb041cSRichard Henderson 36989deb041cSRichard Henderson memop |= MO_ALIGN; 36999deb041cSRichard Henderson switch (gpr_FC) { 37009deb041cSRichard Henderson case 0: /* add and Store */ 37019deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37029deb041cSRichard Henderson break; 37039deb041cSRichard Henderson case 1: /* xor and Store */ 37049deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37059deb041cSRichard Henderson break; 37069deb041cSRichard Henderson case 2: /* Or and Store */ 37079deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37089deb041cSRichard Henderson break; 37099deb041cSRichard Henderson case 3: /* 'and' and Store */ 37109deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37119deb041cSRichard Henderson break; 37129deb041cSRichard Henderson case 4: /* Store max unsigned */ 3713b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3714b8ce0f86SRichard Henderson break; 37159deb041cSRichard Henderson case 5: /* Store max signed */ 3716b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3717b8ce0f86SRichard Henderson break; 37189deb041cSRichard Henderson case 6: /* Store min unsigned */ 3719b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3720b8ce0f86SRichard Henderson break; 37219deb041cSRichard Henderson case 7: /* Store min signed */ 3722b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3723b8ce0f86SRichard Henderson break; 37249deb041cSRichard Henderson case 24: /* Store twin */ 37257fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 37267fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 37277fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 37287fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 37297fbc2b20SRichard Henderson } else { 37307fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 37317fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 37327fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 37337fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 37347fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 37357fbc2b20SRichard Henderson 37367fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 37377fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 37387fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 37397fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 37407fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 37417fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 37427fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 37437fbc2b20SRichard Henderson } 37449deb041cSRichard Henderson break; 37459deb041cSRichard Henderson default: 37469deb041cSRichard Henderson /* invoke data storage error handler */ 37479deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 37489deb041cSRichard Henderson } 3749a3401188SBalamuruhan S } 3750a3401188SBalamuruhan S 37519deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 37529deb041cSRichard Henderson { 37539deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 37549deb041cSRichard Henderson } 37559deb041cSRichard Henderson 37569deb041cSRichard Henderson #ifdef TARGET_PPC64 37579deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 37589deb041cSRichard Henderson { 3759fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 37609deb041cSRichard Henderson } 3761a3401188SBalamuruhan S #endif 3762a3401188SBalamuruhan S 376314776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3764fcf5ef2aSThomas Huth { 376521ee07e7SNicholas Piggin TCGLabel *lfail; 376621ee07e7SNicholas Piggin TCGv EA; 376721ee07e7SNicholas Piggin TCGv cr0; 376821ee07e7SNicholas Piggin TCGv t0; 376921ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3770fcf5ef2aSThomas Huth 377121ee07e7SNicholas Piggin lfail = gen_new_label(); 377221ee07e7SNicholas Piggin EA = tcg_temp_new(); 377321ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3774253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 377521ee07e7SNicholas Piggin 377621ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 377721ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 377821ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 377921ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 378021ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 378121ee07e7SNicholas Piggin 3782253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 378321ee07e7SNicholas Piggin cpu_gpr[rs], ctx->mem_idx, 3784253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3785253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3786253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 378721ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3788253ce7b2SNikunj A Dadhania 378921ee07e7SNicholas Piggin gen_set_label(lfail); 379021ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3791fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3792fcf5ef2aSThomas Huth } 3793fcf5ef2aSThomas Huth 3794fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3795fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3796fcf5ef2aSThomas Huth { \ 3797d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3798fcf5ef2aSThomas Huth } 3799fcf5ef2aSThomas Huth 3800fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3801fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3802fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3803fcf5ef2aSThomas Huth 3804fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3805fcf5ef2aSThomas Huth /* ldarx */ 3806fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3807fcf5ef2aSThomas Huth /* stdcx. */ 3808fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3809fcf5ef2aSThomas Huth 3810fcf5ef2aSThomas Huth /* lqarx */ 3811fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3812fcf5ef2aSThomas Huth { 3813fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 381494bf2658SRichard Henderson TCGv EA, hi, lo; 381557b38ffdSRichard Henderson TCGv_i128 t16; 3816fcf5ef2aSThomas Huth 3817fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3818fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3819fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3820fcf5ef2aSThomas Huth return; 3821fcf5ef2aSThomas Huth } 3822fcf5ef2aSThomas Huth 3823fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 382494bf2658SRichard Henderson EA = tcg_temp_new(); 3825fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 382694bf2658SRichard Henderson 382794bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 382894bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 382994bf2658SRichard Henderson hi = cpu_gpr[rd]; 383094bf2658SRichard Henderson 383157b38ffdSRichard Henderson t16 = tcg_temp_new_i128(); 383257b38ffdSRichard Henderson tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 383357b38ffdSRichard Henderson tcg_gen_extr_i128_i64(lo, hi, t16); 383494bf2658SRichard Henderson 3835e025e8f5SNicholas Piggin tcg_gen_mov_tl(cpu_reserve, EA); 3836392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, 16); 383794bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 383894bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3839fcf5ef2aSThomas Huth } 3840fcf5ef2aSThomas Huth 3841fcf5ef2aSThomas Huth /* stqcx. */ 3842fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3843fcf5ef2aSThomas Huth { 384421ee07e7SNicholas Piggin TCGLabel *lfail; 3845894448aeSRichard Henderson TCGv EA, t0, t1; 384621ee07e7SNicholas Piggin TCGv cr0; 3847894448aeSRichard Henderson TCGv_i128 cmp, val; 384821ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3849fcf5ef2aSThomas Huth 38504a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3851fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3852fcf5ef2aSThomas Huth return; 3853fcf5ef2aSThomas Huth } 38544a9b3c5dSRichard Henderson 385521ee07e7SNicholas Piggin lfail = gen_new_label(); 38564a9b3c5dSRichard Henderson EA = tcg_temp_new(); 385721ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3858fcf5ef2aSThomas Huth 385921ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 386021ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 386121ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 386221ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 386321ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 38644a9b3c5dSRichard Henderson 3865894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 3866894448aeSRichard Henderson val = tcg_temp_new_i128(); 38674a9b3c5dSRichard Henderson 3868894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 38694a9b3c5dSRichard Henderson 3870894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3871894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 38724a9b3c5dSRichard Henderson 3873894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3874894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 3875894448aeSRichard Henderson 3876894448aeSRichard Henderson t0 = tcg_temp_new(); 3877894448aeSRichard Henderson t1 = tcg_temp_new(); 3878894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 3879894448aeSRichard Henderson 3880894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3881894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3882894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 3883894448aeSRichard Henderson 3884894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3885894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 388621ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3887894448aeSRichard Henderson 388821ee07e7SNicholas Piggin gen_set_label(lfail); 388921ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 38904a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 38914a9b3c5dSRichard Henderson } 3892fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3893fcf5ef2aSThomas Huth 3894fcf5ef2aSThomas Huth /* sync */ 3895fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3896fcf5ef2aSThomas Huth { 389703abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 3898fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3899fcf5ef2aSThomas Huth 390003abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 390103abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 390203abfd90SNicholas Piggin } 390303abfd90SNicholas Piggin 3904fcf5ef2aSThomas Huth /* 3905fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3906fcf5ef2aSThomas Huth * 3907fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3908fcf5ef2aSThomas Huth * 3909fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3910fcf5ef2aSThomas Huth * check MSR_PR as well. 3911fcf5ef2aSThomas Huth */ 3912fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3913fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3914fcf5ef2aSThomas Huth } 391503abfd90SNicholas Piggin 391603abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 3917fcf5ef2aSThomas Huth } 3918fcf5ef2aSThomas Huth 3919fcf5ef2aSThomas Huth /* wait */ 3920fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3921fcf5ef2aSThomas Huth { 39220c9717ffSNicholas Piggin uint32_t wc; 39230c9717ffSNicholas Piggin 39240c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 39250c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 39260c9717ffSNicholas Piggin 39270c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 39280c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 39290c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39300c9717ffSNicholas Piggin } else { 39310c9717ffSNicholas Piggin wc = 0; 39320c9717ffSNicholas Piggin } 39330c9717ffSNicholas Piggin 39340c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 39350c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 39360c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39370c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 39380c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 39390c9717ffSNicholas Piggin 39400c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 39410c9717ffSNicholas Piggin if (wc == 3) { 39420c9717ffSNicholas Piggin gen_invalid(ctx); 39430c9717ffSNicholas Piggin return; 39440c9717ffSNicholas Piggin } 39450c9717ffSNicholas Piggin 39460c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 39470c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 39480c9717ffSNicholas Piggin gen_invalid(ctx); 39490c9717ffSNicholas Piggin return; 39500c9717ffSNicholas Piggin } 39510c9717ffSNicholas Piggin 39520c9717ffSNicholas Piggin } else { /* ISA300 */ 39530c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 39540c9717ffSNicholas Piggin if (wc > 0) { 39550c9717ffSNicholas Piggin gen_invalid(ctx); 39560c9717ffSNicholas Piggin return; 39570c9717ffSNicholas Piggin } 39580c9717ffSNicholas Piggin } 39590c9717ffSNicholas Piggin 39600c9717ffSNicholas Piggin } else { 39610c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 39620c9717ffSNicholas Piggin gen_invalid(ctx); 39630c9717ffSNicholas Piggin return; 39640c9717ffSNicholas Piggin } 39650c9717ffSNicholas Piggin 39660c9717ffSNicholas Piggin /* 39670c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 39680c9717ffSNicholas Piggin * to occur. 39690c9717ffSNicholas Piggin */ 39700c9717ffSNicholas Piggin if (wc == 0) { 39717058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(1); 3972fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3973fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3974fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3975b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3976fcf5ef2aSThomas Huth } 3977fcf5ef2aSThomas Huth 39780c9717ffSNicholas Piggin /* 39790c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 39800c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 39810c9717ffSNicholas Piggin * 39820c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 39830c9717ffSNicholas Piggin * no-ops. 39840c9717ffSNicholas Piggin * 39850c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 39860c9717ffSNicholas Piggin * 39870c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 39880c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 39890c9717ffSNicholas Piggin * 39900c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 39910c9717ffSNicholas Piggin * 39920c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 39930c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 39940c9717ffSNicholas Piggin * can be implemented as a no-op. 39950c9717ffSNicholas Piggin * 39960c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 39970c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 39980c9717ffSNicholas Piggin * no-op. 39990c9717ffSNicholas Piggin * 40000c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 40010c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 40020c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 40030c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 40040c9717ffSNicholas Piggin * (if suboptimal). 40050c9717ffSNicholas Piggin */ 40060c9717ffSNicholas Piggin } 40070c9717ffSNicholas Piggin 4008fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4009fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4010fcf5ef2aSThomas Huth { 4011fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40129f0cf041SMatheus Ferst GEN_PRIV(ctx); 4013fcf5ef2aSThomas Huth #else 4014fcf5ef2aSThomas Huth TCGv_i32 t; 4015fcf5ef2aSThomas Huth 40169f0cf041SMatheus Ferst CHK_HV(ctx); 4017c32654afSNicholas Piggin translator_io_start(&ctx->base); 40187058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_DOZE); 4019fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4020154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4021154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4022fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4023fcf5ef2aSThomas Huth } 4024fcf5ef2aSThomas Huth 4025fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4026fcf5ef2aSThomas Huth { 4027fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40289f0cf041SMatheus Ferst GEN_PRIV(ctx); 4029fcf5ef2aSThomas Huth #else 4030fcf5ef2aSThomas Huth TCGv_i32 t; 4031fcf5ef2aSThomas Huth 40329f0cf041SMatheus Ferst CHK_HV(ctx); 4033c32654afSNicholas Piggin translator_io_start(&ctx->base); 40347058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_NAP); 4035fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4036154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4037154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4038fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4039fcf5ef2aSThomas Huth } 4040fcf5ef2aSThomas Huth 4041cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4042cdee0e72SNikunj A Dadhania { 404321c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 40449f0cf041SMatheus Ferst GEN_PRIV(ctx); 404521c0d66aSBenjamin Herrenschmidt #else 404621c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 404721c0d66aSBenjamin Herrenschmidt 40489f0cf041SMatheus Ferst CHK_HV(ctx); 4049c32654afSNicholas Piggin translator_io_start(&ctx->base); 40507058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_STOP); 405121c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 405221c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 405321c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 405421c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4055cdee0e72SNikunj A Dadhania } 4056cdee0e72SNikunj A Dadhania 4057fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4058fcf5ef2aSThomas Huth { 4059fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40609f0cf041SMatheus Ferst GEN_PRIV(ctx); 4061fcf5ef2aSThomas Huth #else 4062fcf5ef2aSThomas Huth TCGv_i32 t; 4063fcf5ef2aSThomas Huth 40649f0cf041SMatheus Ferst CHK_HV(ctx); 4065c32654afSNicholas Piggin translator_io_start(&ctx->base); 40667058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_SLEEP); 4067fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4068154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4069154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4070fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4071fcf5ef2aSThomas Huth } 4072fcf5ef2aSThomas Huth 4073fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4074fcf5ef2aSThomas Huth { 4075fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40769f0cf041SMatheus Ferst GEN_PRIV(ctx); 4077fcf5ef2aSThomas Huth #else 4078fcf5ef2aSThomas Huth TCGv_i32 t; 4079fcf5ef2aSThomas Huth 40809f0cf041SMatheus Ferst CHK_HV(ctx); 4081c32654afSNicholas Piggin translator_io_start(&ctx->base); 40827058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_RVWINKLE); 4083fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4084154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4085154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4086fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4087fcf5ef2aSThomas Huth } 4088fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4089fcf5ef2aSThomas Huth 4090fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4091fcf5ef2aSThomas Huth { 4092fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4093efe843d8SDavid Gibson if (ctx->has_cfar) { 4094fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4095efe843d8SDavid Gibson } 4096fcf5ef2aSThomas Huth #endif 4097fcf5ef2aSThomas Huth } 4098fcf5ef2aSThomas Huth 409946d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 410046d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 410146d396bdSDaniel Henrique Barboza { 410246d396bdSDaniel Henrique Barboza /* 410346d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 410446d396bdSDaniel Henrique Barboza * instructions. 410546d396bdSDaniel Henrique Barboza */ 410646d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 410746d396bdSDaniel Henrique Barboza return; 410846d396bdSDaniel Henrique Barboza } 410946d396bdSDaniel Henrique Barboza 411046d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4111eeaaefe9SLeandro Lupori TCGLabel *l; 4112eeaaefe9SLeandro Lupori TCGv t0; 4113eeaaefe9SLeandro Lupori 411446d396bdSDaniel Henrique Barboza /* 411546d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 411646d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 411746d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 411846d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 411946d396bdSDaniel Henrique Barboza */ 4120283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 412146d396bdSDaniel Henrique Barboza 4122eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4123eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4124eeaaefe9SLeandro Lupori l = gen_new_label(); 4125eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4126eeaaefe9SLeandro Lupori 4127eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4128eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4129eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4130eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4131eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4132eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4133eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4134eeaaefe9SLeandro Lupori } 4135eeaaefe9SLeandro Lupori 4136eeaaefe9SLeandro Lupori gen_set_label(l); 4137eeaaefe9SLeandro Lupori } else { 413846d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4139eeaaefe9SLeandro Lupori } 414046d396bdSDaniel Henrique Barboza #else 414146d396bdSDaniel Henrique Barboza /* 414246d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 414346d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 414446d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 414546d396bdSDaniel Henrique Barboza */ 414646d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 414746d396bdSDaniel Henrique Barboza 414846d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 414946d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 415046d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 415146d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 415246d396bdSDaniel Henrique Barboza } 415346d396bdSDaniel Henrique Barboza #else 415446d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 415546d396bdSDaniel Henrique Barboza { 415646d396bdSDaniel Henrique Barboza return; 415746d396bdSDaniel Henrique Barboza } 415846d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 415946d396bdSDaniel Henrique Barboza 4160fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4161fcf5ef2aSThomas Huth { 41626e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4163fcf5ef2aSThomas Huth } 4164fcf5ef2aSThomas Huth 41650e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 41660e3bf489SRoman Kapl { 41679498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 41680e3bf489SRoman Kapl gen_debug_exception(ctx); 41690e3bf489SRoman Kapl } else { 417046d396bdSDaniel Henrique Barboza /* 417146d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 417246d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 417346d396bdSDaniel Henrique Barboza */ 417446d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 417546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 417646d396bdSDaniel Henrique Barboza } 417746d396bdSDaniel Henrique Barboza 41780e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 41790e3bf489SRoman Kapl } 41800e3bf489SRoman Kapl } 41810e3bf489SRoman Kapl 4182fcf5ef2aSThomas Huth /*** Branch ***/ 4183c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4184fcf5ef2aSThomas Huth { 4185fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4186fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4187fcf5ef2aSThomas Huth } 4188fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 418946d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4190fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4191fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 419207ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4193fcf5ef2aSThomas Huth } else { 4194fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 41950e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4196fcf5ef2aSThomas Huth } 4197fcf5ef2aSThomas Huth } 4198fcf5ef2aSThomas Huth 4199fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4200fcf5ef2aSThomas Huth { 4201fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4202fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4203fcf5ef2aSThomas Huth } 4204fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4205fcf5ef2aSThomas Huth } 4206fcf5ef2aSThomas Huth 4207fcf5ef2aSThomas Huth /* b ba bl bla */ 4208fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4209fcf5ef2aSThomas Huth { 4210fcf5ef2aSThomas Huth target_ulong li, target; 4211fcf5ef2aSThomas Huth 4212fcf5ef2aSThomas Huth /* sign extend LI */ 4213fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4214fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4215fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42162c2bcb1bSRichard Henderson target = ctx->cia + li; 4217fcf5ef2aSThomas Huth } else { 4218fcf5ef2aSThomas Huth target = li; 4219fcf5ef2aSThomas Huth } 4220fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4221b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4222fcf5ef2aSThomas Huth } 42232c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4224fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 42256086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4226fcf5ef2aSThomas Huth } 4227fcf5ef2aSThomas Huth 4228fcf5ef2aSThomas Huth #define BCOND_IM 0 4229fcf5ef2aSThomas Huth #define BCOND_LR 1 4230fcf5ef2aSThomas Huth #define BCOND_CTR 2 4231fcf5ef2aSThomas Huth #define BCOND_TAR 3 4232fcf5ef2aSThomas Huth 4233c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4234fcf5ef2aSThomas Huth { 4235fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4236fcf5ef2aSThomas Huth TCGLabel *l1; 4237fcf5ef2aSThomas Huth TCGv target; 42380e3bf489SRoman Kapl 4239fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 42409723281fSRichard Henderson target = tcg_temp_new(); 4241efe843d8SDavid Gibson if (type == BCOND_CTR) { 4242fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4243efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4244fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4245efe843d8SDavid Gibson } else { 4246fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4247efe843d8SDavid Gibson } 4248fcf5ef2aSThomas Huth } else { 4249f764718dSRichard Henderson target = NULL; 4250fcf5ef2aSThomas Huth } 4251efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4252b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4253efe843d8SDavid Gibson } 4254fcf5ef2aSThomas Huth l1 = gen_new_label(); 4255fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4256fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4257fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4258fa200c95SGreg Kurz 4259fa200c95SGreg Kurz if (type == BCOND_CTR) { 4260fa200c95SGreg Kurz /* 4261fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4262fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4263fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 426415d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 426515d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 426615d68c5eSGreg Kurz * it basically useless and thus never used in real code. 426715d68c5eSGreg Kurz * 426815d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 426915d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 427015d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 427115d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 427215d68c5eSGreg Kurz * doing anything else harmful. 4273fa200c95SGreg Kurz */ 4274d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4275fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4276fcf5ef2aSThomas Huth return; 4277fcf5ef2aSThomas Huth } 4278fa200c95SGreg Kurz 4279fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4280fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4281fa200c95SGreg Kurz } else { 4282fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4283fa200c95SGreg Kurz } 4284fa200c95SGreg Kurz if (bo & 0x2) { 4285fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4286fa200c95SGreg Kurz } else { 4287fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4288fa200c95SGreg Kurz } 4289fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4290fa200c95SGreg Kurz } else { 4291fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4292fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4293fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4294fcf5ef2aSThomas Huth } else { 4295fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4296fcf5ef2aSThomas Huth } 4297fcf5ef2aSThomas Huth if (bo & 0x2) { 4298fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4299fcf5ef2aSThomas Huth } else { 4300fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4301fcf5ef2aSThomas Huth } 4302fa200c95SGreg Kurz } 4303fcf5ef2aSThomas Huth } 4304fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4305fcf5ef2aSThomas Huth /* Test CR */ 4306fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4307fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4308fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4309fcf5ef2aSThomas Huth 4310fcf5ef2aSThomas Huth if (bo & 0x8) { 4311fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4312fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4313fcf5ef2aSThomas Huth } else { 4314fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4315fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4316fcf5ef2aSThomas Huth } 4317fcf5ef2aSThomas Huth } 43182c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4319fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4320fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4321fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43222c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4323fcf5ef2aSThomas Huth } else { 4324fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4325fcf5ef2aSThomas Huth } 4326fcf5ef2aSThomas Huth } else { 4327fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4328fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4329fcf5ef2aSThomas Huth } else { 4330fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4331fcf5ef2aSThomas Huth } 43320e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4333c4a2e3a9SRichard Henderson } 4334fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 43350e3bf489SRoman Kapl /* fallthrough case */ 4336fcf5ef2aSThomas Huth gen_set_label(l1); 4337b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4338fcf5ef2aSThomas Huth } 43396086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4340fcf5ef2aSThomas Huth } 4341fcf5ef2aSThomas Huth 4342fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4343fcf5ef2aSThomas Huth { 4344fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4345fcf5ef2aSThomas Huth } 4346fcf5ef2aSThomas Huth 4347fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4348fcf5ef2aSThomas Huth { 4349fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4350fcf5ef2aSThomas Huth } 4351fcf5ef2aSThomas Huth 4352fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4353fcf5ef2aSThomas Huth { 4354fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4355fcf5ef2aSThomas Huth } 4356fcf5ef2aSThomas Huth 4357fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4358fcf5ef2aSThomas Huth { 4359fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4360fcf5ef2aSThomas Huth } 4361fcf5ef2aSThomas Huth 4362fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4363fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4364fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4365fcf5ef2aSThomas Huth { \ 4366fcf5ef2aSThomas Huth uint8_t bitmask; \ 4367fcf5ef2aSThomas Huth int sh; \ 4368fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4369fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4370fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4371fcf5ef2aSThomas Huth if (sh > 0) \ 4372fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4373fcf5ef2aSThomas Huth else if (sh < 0) \ 4374fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4375fcf5ef2aSThomas Huth else \ 4376fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4377fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4378fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4379fcf5ef2aSThomas Huth if (sh > 0) \ 4380fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4381fcf5ef2aSThomas Huth else if (sh < 0) \ 4382fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4383fcf5ef2aSThomas Huth else \ 4384fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4385fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4386fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4387fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4388fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4389fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4390fcf5ef2aSThomas Huth } 4391fcf5ef2aSThomas Huth 4392fcf5ef2aSThomas Huth /* crand */ 4393fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4394fcf5ef2aSThomas Huth /* crandc */ 4395fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4396fcf5ef2aSThomas Huth /* creqv */ 4397fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4398fcf5ef2aSThomas Huth /* crnand */ 4399fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4400fcf5ef2aSThomas Huth /* crnor */ 4401fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4402fcf5ef2aSThomas Huth /* cror */ 4403fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4404fcf5ef2aSThomas Huth /* crorc */ 4405fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4406fcf5ef2aSThomas Huth /* crxor */ 4407fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4408fcf5ef2aSThomas Huth 4409fcf5ef2aSThomas Huth /* mcrf */ 4410fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4411fcf5ef2aSThomas Huth { 4412fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4413fcf5ef2aSThomas Huth } 4414fcf5ef2aSThomas Huth 4415fcf5ef2aSThomas Huth /*** System linkage ***/ 4416fcf5ef2aSThomas Huth 4417fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4418fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4419fcf5ef2aSThomas Huth { 4420fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44219f0cf041SMatheus Ferst GEN_PRIV(ctx); 4422fcf5ef2aSThomas Huth #else 4423efe843d8SDavid Gibson /* 4424efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4425fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4426fcf5ef2aSThomas Huth */ 4427d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4428fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4429fcf5ef2aSThomas Huth return; 4430fcf5ef2aSThomas Huth } 4431fcf5ef2aSThomas Huth /* Restore CPU state */ 44329f0cf041SMatheus Ferst CHK_SV(ctx); 4433283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44342c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4435fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 443659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4437fcf5ef2aSThomas Huth #endif 4438fcf5ef2aSThomas Huth } 4439fcf5ef2aSThomas Huth 4440fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4441fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4442fcf5ef2aSThomas Huth { 4443fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44449f0cf041SMatheus Ferst GEN_PRIV(ctx); 4445fcf5ef2aSThomas Huth #else 4446fcf5ef2aSThomas Huth /* Restore CPU state */ 44479f0cf041SMatheus Ferst CHK_SV(ctx); 4448283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44492c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4450fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 445159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4452fcf5ef2aSThomas Huth #endif 4453fcf5ef2aSThomas Huth } 4454fcf5ef2aSThomas Huth 44553c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44563c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 44573c89b8d6SNicholas Piggin { 44583c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 44599f0cf041SMatheus Ferst GEN_PRIV(ctx); 44603c89b8d6SNicholas Piggin #else 44613c89b8d6SNicholas Piggin /* Restore CPU state */ 44629f0cf041SMatheus Ferst CHK_SV(ctx); 4463283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44642c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 44653c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 446659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 44673c89b8d6SNicholas Piggin #endif 44683c89b8d6SNicholas Piggin } 44693c89b8d6SNicholas Piggin #endif 44703c89b8d6SNicholas Piggin 4471fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4472fcf5ef2aSThomas Huth { 4473fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44749f0cf041SMatheus Ferst GEN_PRIV(ctx); 4475fcf5ef2aSThomas Huth #else 4476fcf5ef2aSThomas Huth /* Restore CPU state */ 44779f0cf041SMatheus Ferst CHK_HV(ctx); 4478c32654afSNicholas Piggin translator_io_start(&ctx->base); 4479fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 448059bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4481fcf5ef2aSThomas Huth #endif 4482fcf5ef2aSThomas Huth } 4483fcf5ef2aSThomas Huth #endif 4484fcf5ef2aSThomas Huth 4485fcf5ef2aSThomas Huth /* sc */ 4486fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4487fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4488fcf5ef2aSThomas Huth #else 4489fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4490fcf5ef2aSThomas Huth #endif 4491fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4492fcf5ef2aSThomas Huth { 4493fcf5ef2aSThomas Huth uint32_t lev; 4494fcf5ef2aSThomas Huth 4495984eda58SNicholas Piggin /* 4496984eda58SNicholas Piggin * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4497984eda58SNicholas Piggin * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4498984eda58SNicholas Piggin * for Ultravisor which TCG does not support, so just ignore the top 6. 4499984eda58SNicholas Piggin */ 4500984eda58SNicholas Piggin lev = (ctx->opcode >> 5) & 0x1; 4501fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4502fcf5ef2aSThomas Huth } 4503fcf5ef2aSThomas Huth 45043c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 45053c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45063c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 45073c89b8d6SNicholas Piggin { 4508f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 45093c89b8d6SNicholas Piggin 4510f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 45112c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4512f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 45133c89b8d6SNicholas Piggin 45147a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 45153c89b8d6SNicholas Piggin } 45163c89b8d6SNicholas Piggin #endif 45173c89b8d6SNicholas Piggin #endif 45183c89b8d6SNicholas Piggin 4519fcf5ef2aSThomas Huth /*** Trap ***/ 4520fcf5ef2aSThomas Huth 4521fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4522fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4523fcf5ef2aSThomas Huth { 4524fcf5ef2aSThomas Huth /* Trap never */ 4525fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4526fcf5ef2aSThomas Huth return true; 4527fcf5ef2aSThomas Huth } 4528fcf5ef2aSThomas Huth /* Trap always */ 4529fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4530fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4531fcf5ef2aSThomas Huth return true; 4532fcf5ef2aSThomas Huth } 4533fcf5ef2aSThomas Huth return false; 4534fcf5ef2aSThomas Huth } 4535fcf5ef2aSThomas Huth 4536fcf5ef2aSThomas Huth /* tw */ 4537fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4538fcf5ef2aSThomas Huth { 4539fcf5ef2aSThomas Huth TCGv_i32 t0; 4540fcf5ef2aSThomas Huth 4541fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4542fcf5ef2aSThomas Huth return; 4543fcf5ef2aSThomas Huth } 45447058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4545fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4546fcf5ef2aSThomas Huth t0); 4547fcf5ef2aSThomas Huth } 4548fcf5ef2aSThomas Huth 4549fcf5ef2aSThomas Huth /* twi */ 4550fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4551fcf5ef2aSThomas Huth { 4552fcf5ef2aSThomas Huth TCGv t0; 4553fcf5ef2aSThomas Huth TCGv_i32 t1; 4554fcf5ef2aSThomas Huth 4555fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4556fcf5ef2aSThomas Huth return; 4557fcf5ef2aSThomas Huth } 45587058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45597058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4560fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4561fcf5ef2aSThomas Huth } 4562fcf5ef2aSThomas Huth 4563fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4564fcf5ef2aSThomas Huth /* td */ 4565fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4566fcf5ef2aSThomas Huth { 4567fcf5ef2aSThomas Huth TCGv_i32 t0; 4568fcf5ef2aSThomas Huth 4569fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4570fcf5ef2aSThomas Huth return; 4571fcf5ef2aSThomas Huth } 45727058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4573fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4574fcf5ef2aSThomas Huth t0); 4575fcf5ef2aSThomas Huth } 4576fcf5ef2aSThomas Huth 4577fcf5ef2aSThomas Huth /* tdi */ 4578fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4579fcf5ef2aSThomas Huth { 4580fcf5ef2aSThomas Huth TCGv t0; 4581fcf5ef2aSThomas Huth TCGv_i32 t1; 4582fcf5ef2aSThomas Huth 4583fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4584fcf5ef2aSThomas Huth return; 4585fcf5ef2aSThomas Huth } 45867058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45877058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4588fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4589fcf5ef2aSThomas Huth } 4590fcf5ef2aSThomas Huth #endif 4591fcf5ef2aSThomas Huth 4592fcf5ef2aSThomas Huth /*** Processor control ***/ 4593fcf5ef2aSThomas Huth 4594fcf5ef2aSThomas Huth /* mcrxr */ 4595fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4596fcf5ef2aSThomas Huth { 4597fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4598fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4599fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4600fcf5ef2aSThomas Huth 4601fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4602fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4603fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4604fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4605fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4606fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4607fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4608fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4609fcf5ef2aSThomas Huth 4610fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4611fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4612fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4613fcf5ef2aSThomas Huth } 4614fcf5ef2aSThomas Huth 4615b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4616b63d0434SNikunj A Dadhania /* mcrxrx */ 4617b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4618b63d0434SNikunj A Dadhania { 4619b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4620b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4621b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4622b63d0434SNikunj A Dadhania 4623b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4624b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4625b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4626b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4627b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4628b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4629b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4630b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4631b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4632b63d0434SNikunj A Dadhania } 4633b63d0434SNikunj A Dadhania #endif 4634b63d0434SNikunj A Dadhania 4635fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4636fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4637fcf5ef2aSThomas Huth { 4638fcf5ef2aSThomas Huth uint32_t crm, crn; 4639fcf5ef2aSThomas Huth 4640fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4641fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4642fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4643fcf5ef2aSThomas Huth crn = ctz32(crm); 4644fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4645fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4646fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4647fcf5ef2aSThomas Huth } 4648fcf5ef2aSThomas Huth } else { 4649fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4650fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4651fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4652fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4653fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4654fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4655fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4656fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4657fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4658fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4659fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4660fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4661fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4662fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4663fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4664fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4665fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4666fcf5ef2aSThomas Huth } 4667fcf5ef2aSThomas Huth } 4668fcf5ef2aSThomas Huth 4669fcf5ef2aSThomas Huth /* mfmsr */ 4670fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4671fcf5ef2aSThomas Huth { 46729f0cf041SMatheus Ferst CHK_SV(ctx); 4673fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4674fcf5ef2aSThomas Huth } 4675fcf5ef2aSThomas Huth 4676fcf5ef2aSThomas Huth /* mfspr */ 4677fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4678fcf5ef2aSThomas Huth { 4679fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4680fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4681fcf5ef2aSThomas Huth 4682fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4683fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4684fcf5ef2aSThomas Huth #else 4685fcf5ef2aSThomas Huth if (ctx->pr) { 4686fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4687fcf5ef2aSThomas Huth } else if (ctx->hv) { 4688fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4689fcf5ef2aSThomas Huth } else { 4690fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4691fcf5ef2aSThomas Huth } 4692fcf5ef2aSThomas Huth #endif 4693fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4694fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4695fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4696fcf5ef2aSThomas Huth } else { 4697fcf5ef2aSThomas Huth /* Privilege exception */ 4698efe843d8SDavid Gibson /* 4699efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4700fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4701fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4702fcf5ef2aSThomas Huth */ 4703fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 470431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 470531085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 47062c2bcb1bSRichard Henderson ctx->cia); 4707fcf5ef2aSThomas Huth } 4708fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4709fcf5ef2aSThomas Huth } 4710fcf5ef2aSThomas Huth } else { 4711fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4712fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4713fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4714fcf5ef2aSThomas Huth /* This is a nop */ 4715fcf5ef2aSThomas Huth return; 4716fcf5ef2aSThomas Huth } 4717fcf5ef2aSThomas Huth /* Not defined */ 471831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 471931085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 47202c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4721fcf5ef2aSThomas Huth 4722efe843d8SDavid Gibson /* 4723efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4724efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4725fcf5ef2aSThomas Huth */ 4726fcf5ef2aSThomas Huth if (sprn & 0x10) { 4727fcf5ef2aSThomas Huth if (ctx->pr) { 47281315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4729fcf5ef2aSThomas Huth } 4730fcf5ef2aSThomas Huth } else { 4731fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 47321315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4733fcf5ef2aSThomas Huth } 4734fcf5ef2aSThomas Huth } 4735fcf5ef2aSThomas Huth } 4736fcf5ef2aSThomas Huth } 4737fcf5ef2aSThomas Huth 4738fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4739fcf5ef2aSThomas Huth { 4740fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4741fcf5ef2aSThomas Huth } 4742fcf5ef2aSThomas Huth 4743fcf5ef2aSThomas Huth /* mftb */ 4744fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4745fcf5ef2aSThomas Huth { 4746fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4747fcf5ef2aSThomas Huth } 4748fcf5ef2aSThomas Huth 4749fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4750fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4751fcf5ef2aSThomas Huth { 4752fcf5ef2aSThomas Huth uint32_t crm, crn; 4753fcf5ef2aSThomas Huth 4754fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4755fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4756fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4757fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4758fcf5ef2aSThomas Huth crn = ctz32(crm); 4759fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4760fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4761fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4762fcf5ef2aSThomas Huth } 4763fcf5ef2aSThomas Huth } else { 4764fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4765fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4766fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4767fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4768fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4769fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4770fcf5ef2aSThomas Huth } 4771fcf5ef2aSThomas Huth } 4772fcf5ef2aSThomas Huth } 4773fcf5ef2aSThomas Huth } 4774fcf5ef2aSThomas Huth 4775fcf5ef2aSThomas Huth /* mtmsr */ 4776fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4777fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4778fcf5ef2aSThomas Huth { 4779caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4780caf590ddSNicholas Piggin gen_invalid(ctx); 4781caf590ddSNicholas Piggin return; 4782caf590ddSNicholas Piggin } 4783caf590ddSNicholas Piggin 47849f0cf041SMatheus Ferst CHK_SV(ctx); 4785fcf5ef2aSThomas Huth 4786fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 47876fa5726bSMatheus Ferst TCGv t0, t1; 47886fa5726bSMatheus Ferst target_ulong mask; 47896fa5726bSMatheus Ferst 47906fa5726bSMatheus Ferst t0 = tcg_temp_new(); 47916fa5726bSMatheus Ferst t1 = tcg_temp_new(); 47926fa5726bSMatheus Ferst 4793283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 47946fa5726bSMatheus Ferst 4795fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 47965ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 47976fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4798fcf5ef2aSThomas Huth } else { 47996fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 48006fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 48016fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4802efe843d8SDavid Gibson /* 4803efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4804efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4805efe843d8SDavid Gibson * ppc_store_msr 4806fcf5ef2aSThomas Huth */ 4807b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4808fcf5ef2aSThomas Huth } 48096fa5726bSMatheus Ferst 48106fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48116fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48126fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48136fa5726bSMatheus Ferst 48146fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48156fa5726bSMatheus Ferst 48165ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4817d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4818fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4819fcf5ef2aSThomas Huth } 4820fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4821fcf5ef2aSThomas Huth 4822fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4823fcf5ef2aSThomas Huth { 48249f0cf041SMatheus Ferst CHK_SV(ctx); 4825fcf5ef2aSThomas Huth 4826fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48276fa5726bSMatheus Ferst TCGv t0, t1; 48286fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 48296fa5726bSMatheus Ferst 48306fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48316fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48326fa5726bSMatheus Ferst 4833283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 4834fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48355ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48366fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4837fcf5ef2aSThomas Huth } else { 48386fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 48396fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4840fcf5ef2aSThomas Huth 4841efe843d8SDavid Gibson /* 4842efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4843efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4844efe843d8SDavid Gibson * ppc_store_msr 4845fcf5ef2aSThomas Huth */ 4846b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4847fcf5ef2aSThomas Huth } 48486fa5726bSMatheus Ferst 48496fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48506fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48516fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48526fa5726bSMatheus Ferst 48536fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48546fa5726bSMatheus Ferst 48555ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4856d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4857fcf5ef2aSThomas Huth #endif 4858fcf5ef2aSThomas Huth } 4859fcf5ef2aSThomas Huth 4860fcf5ef2aSThomas Huth /* mtspr */ 4861fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4862fcf5ef2aSThomas Huth { 4863fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4864fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4865fcf5ef2aSThomas Huth 4866fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4867fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4868fcf5ef2aSThomas Huth #else 4869fcf5ef2aSThomas Huth if (ctx->pr) { 4870fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4871fcf5ef2aSThomas Huth } else if (ctx->hv) { 4872fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4873fcf5ef2aSThomas Huth } else { 4874fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4875fcf5ef2aSThomas Huth } 4876fcf5ef2aSThomas Huth #endif 4877fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4878fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4879fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4880fcf5ef2aSThomas Huth } else { 4881fcf5ef2aSThomas Huth /* Privilege exception */ 488231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 488331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48842c2bcb1bSRichard Henderson ctx->cia); 4885fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4886fcf5ef2aSThomas Huth } 4887fcf5ef2aSThomas Huth } else { 4888fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4889fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4890fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4891fcf5ef2aSThomas Huth /* This is a nop */ 4892fcf5ef2aSThomas Huth return; 4893fcf5ef2aSThomas Huth } 4894fcf5ef2aSThomas Huth 4895fcf5ef2aSThomas Huth /* Not defined */ 489631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 489731085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 48982c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4899fcf5ef2aSThomas Huth 4900fcf5ef2aSThomas Huth 4901efe843d8SDavid Gibson /* 4902efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4903efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4904fcf5ef2aSThomas Huth */ 4905fcf5ef2aSThomas Huth if (sprn & 0x10) { 4906fcf5ef2aSThomas Huth if (ctx->pr) { 49071315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4908fcf5ef2aSThomas Huth } 4909fcf5ef2aSThomas Huth } else { 4910fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 49111315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4912fcf5ef2aSThomas Huth } 4913fcf5ef2aSThomas Huth } 4914fcf5ef2aSThomas Huth } 4915fcf5ef2aSThomas Huth } 4916fcf5ef2aSThomas Huth 4917fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4918fcf5ef2aSThomas Huth /* setb */ 4919fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4920fcf5ef2aSThomas Huth { 4921fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 49226f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 49236f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 4924fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4925fcf5ef2aSThomas Huth 4926fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4927fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4928fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4929fcf5ef2aSThomas Huth } 4930fcf5ef2aSThomas Huth #endif 4931fcf5ef2aSThomas Huth 4932fcf5ef2aSThomas Huth /*** Cache management ***/ 4933fcf5ef2aSThomas Huth 4934fcf5ef2aSThomas Huth /* dcbf */ 4935fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4936fcf5ef2aSThomas Huth { 4937fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4938fcf5ef2aSThomas Huth TCGv t0; 4939fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4940fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4941fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4942fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4943fcf5ef2aSThomas Huth } 4944fcf5ef2aSThomas Huth 494550728199SRoman Kapl /* dcbfep (external PID dcbf) */ 494650728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 494750728199SRoman Kapl { 494850728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 494950728199SRoman Kapl TCGv t0; 49509f0cf041SMatheus Ferst CHK_SV(ctx); 495150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 495250728199SRoman Kapl t0 = tcg_temp_new(); 495350728199SRoman Kapl gen_addr_reg_index(ctx, t0); 495450728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 495550728199SRoman Kapl } 495650728199SRoman Kapl 4957fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4958fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4959fcf5ef2aSThomas Huth { 4960fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 49619f0cf041SMatheus Ferst GEN_PRIV(ctx); 4962fcf5ef2aSThomas Huth #else 4963fcf5ef2aSThomas Huth TCGv EA, val; 4964fcf5ef2aSThomas Huth 49659f0cf041SMatheus Ferst CHK_SV(ctx); 4966fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4967fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4968fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4969fcf5ef2aSThomas Huth val = tcg_temp_new(); 4970fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4971fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4972fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4973fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4974fcf5ef2aSThomas Huth } 4975fcf5ef2aSThomas Huth 4976fcf5ef2aSThomas Huth /* dcdst */ 4977fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4978fcf5ef2aSThomas Huth { 4979fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4980fcf5ef2aSThomas Huth TCGv t0; 4981fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4982fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4983fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4984fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4985fcf5ef2aSThomas Huth } 4986fcf5ef2aSThomas Huth 498750728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 498850728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 498950728199SRoman Kapl { 499050728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 499150728199SRoman Kapl TCGv t0; 499250728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 499350728199SRoman Kapl t0 = tcg_temp_new(); 499450728199SRoman Kapl gen_addr_reg_index(ctx, t0); 499550728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 499650728199SRoman Kapl } 499750728199SRoman Kapl 4998fcf5ef2aSThomas Huth /* dcbt */ 4999fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5000fcf5ef2aSThomas Huth { 5001efe843d8SDavid Gibson /* 5002efe843d8SDavid Gibson * interpreted as no-op 5003efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5004efe843d8SDavid Gibson * does not generate any exception 5005fcf5ef2aSThomas Huth */ 5006fcf5ef2aSThomas Huth } 5007fcf5ef2aSThomas Huth 500850728199SRoman Kapl /* dcbtep */ 500950728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 501050728199SRoman Kapl { 5011efe843d8SDavid Gibson /* 5012efe843d8SDavid Gibson * interpreted as no-op 5013efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5014efe843d8SDavid Gibson * does not generate any exception 501550728199SRoman Kapl */ 501650728199SRoman Kapl } 501750728199SRoman Kapl 5018fcf5ef2aSThomas Huth /* dcbtst */ 5019fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5020fcf5ef2aSThomas Huth { 5021efe843d8SDavid Gibson /* 5022efe843d8SDavid Gibson * interpreted as no-op 5023efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5024efe843d8SDavid Gibson * does not generate any exception 5025fcf5ef2aSThomas Huth */ 5026fcf5ef2aSThomas Huth } 5027fcf5ef2aSThomas Huth 502850728199SRoman Kapl /* dcbtstep */ 502950728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 503050728199SRoman Kapl { 5031efe843d8SDavid Gibson /* 5032efe843d8SDavid Gibson * interpreted as no-op 5033efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5034efe843d8SDavid Gibson * does not generate any exception 503550728199SRoman Kapl */ 503650728199SRoman Kapl } 503750728199SRoman Kapl 5038fcf5ef2aSThomas Huth /* dcbtls */ 5039fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5040fcf5ef2aSThomas Huth { 5041fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5042fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5043fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5044fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5045fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5046fcf5ef2aSThomas Huth } 5047fcf5ef2aSThomas Huth 5048e64645baSBernhard Beschow /* dcblc */ 5049e64645baSBernhard Beschow static void gen_dcblc(DisasContext *ctx) 5050e64645baSBernhard Beschow { 5051e64645baSBernhard Beschow /* 5052e64645baSBernhard Beschow * interpreted as no-op 5053e64645baSBernhard Beschow */ 5054e64645baSBernhard Beschow } 5055e64645baSBernhard Beschow 5056fcf5ef2aSThomas Huth /* dcbz */ 5057fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5058fcf5ef2aSThomas Huth { 5059fcf5ef2aSThomas Huth TCGv tcgv_addr; 5060fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5061fcf5ef2aSThomas Huth 5062fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5063fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 50647058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5065fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5066fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5067fcf5ef2aSThomas Huth } 5068fcf5ef2aSThomas Huth 506950728199SRoman Kapl /* dcbzep */ 507050728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 507150728199SRoman Kapl { 507250728199SRoman Kapl TCGv tcgv_addr; 507350728199SRoman Kapl TCGv_i32 tcgv_op; 507450728199SRoman Kapl 507550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 507650728199SRoman Kapl tcgv_addr = tcg_temp_new(); 50777058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 507850728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 507950728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 508050728199SRoman Kapl } 508150728199SRoman Kapl 5082fcf5ef2aSThomas Huth /* dst / dstt */ 5083fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5084fcf5ef2aSThomas Huth { 5085fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5086fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5087fcf5ef2aSThomas Huth } else { 5088fcf5ef2aSThomas Huth /* interpreted as no-op */ 5089fcf5ef2aSThomas Huth } 5090fcf5ef2aSThomas Huth } 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth /* dstst /dststt */ 5093fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5094fcf5ef2aSThomas Huth { 5095fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5096fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5097fcf5ef2aSThomas Huth } else { 5098fcf5ef2aSThomas Huth /* interpreted as no-op */ 5099fcf5ef2aSThomas Huth } 5100fcf5ef2aSThomas Huth 5101fcf5ef2aSThomas Huth } 5102fcf5ef2aSThomas Huth 5103fcf5ef2aSThomas Huth /* dss / dssall */ 5104fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5105fcf5ef2aSThomas Huth { 5106fcf5ef2aSThomas Huth /* interpreted as no-op */ 5107fcf5ef2aSThomas Huth } 5108fcf5ef2aSThomas Huth 5109fcf5ef2aSThomas Huth /* icbi */ 5110fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5111fcf5ef2aSThomas Huth { 5112fcf5ef2aSThomas Huth TCGv t0; 5113fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5114fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5115fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5116fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5117fcf5ef2aSThomas Huth } 5118fcf5ef2aSThomas Huth 511950728199SRoman Kapl /* icbiep */ 512050728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 512150728199SRoman Kapl { 512250728199SRoman Kapl TCGv t0; 512350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 512450728199SRoman Kapl t0 = tcg_temp_new(); 512550728199SRoman Kapl gen_addr_reg_index(ctx, t0); 512650728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 512750728199SRoman Kapl } 512850728199SRoman Kapl 5129fcf5ef2aSThomas Huth /* Optional: */ 5130fcf5ef2aSThomas Huth /* dcba */ 5131fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5132fcf5ef2aSThomas Huth { 5133efe843d8SDavid Gibson /* 5134efe843d8SDavid Gibson * interpreted as no-op 5135efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5136fcf5ef2aSThomas Huth * but does not generate any exception 5137fcf5ef2aSThomas Huth */ 5138fcf5ef2aSThomas Huth } 5139fcf5ef2aSThomas Huth 5140fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5141fcf5ef2aSThomas Huth /* Supervisor only: */ 5142fcf5ef2aSThomas Huth 5143fcf5ef2aSThomas Huth /* mfsr */ 5144fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5145fcf5ef2aSThomas Huth { 5146fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51479f0cf041SMatheus Ferst GEN_PRIV(ctx); 5148fcf5ef2aSThomas Huth #else 5149fcf5ef2aSThomas Huth TCGv t0; 5150fcf5ef2aSThomas Huth 51519f0cf041SMatheus Ferst CHK_SV(ctx); 51527058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5153fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5154fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5155fcf5ef2aSThomas Huth } 5156fcf5ef2aSThomas Huth 5157fcf5ef2aSThomas Huth /* mfsrin */ 5158fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5159fcf5ef2aSThomas Huth { 5160fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51619f0cf041SMatheus Ferst GEN_PRIV(ctx); 5162fcf5ef2aSThomas Huth #else 5163fcf5ef2aSThomas Huth TCGv t0; 5164fcf5ef2aSThomas Huth 51659f0cf041SMatheus Ferst CHK_SV(ctx); 5166fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5167e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5168fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5169fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5170fcf5ef2aSThomas Huth } 5171fcf5ef2aSThomas Huth 5172fcf5ef2aSThomas Huth /* mtsr */ 5173fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5174fcf5ef2aSThomas Huth { 5175fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51769f0cf041SMatheus Ferst GEN_PRIV(ctx); 5177fcf5ef2aSThomas Huth #else 5178fcf5ef2aSThomas Huth TCGv t0; 5179fcf5ef2aSThomas Huth 51809f0cf041SMatheus Ferst CHK_SV(ctx); 51817058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5182fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5183fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5184fcf5ef2aSThomas Huth } 5185fcf5ef2aSThomas Huth 5186fcf5ef2aSThomas Huth /* mtsrin */ 5187fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5188fcf5ef2aSThomas Huth { 5189fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51909f0cf041SMatheus Ferst GEN_PRIV(ctx); 5191fcf5ef2aSThomas Huth #else 5192fcf5ef2aSThomas Huth TCGv t0; 51939f0cf041SMatheus Ferst CHK_SV(ctx); 5194fcf5ef2aSThomas Huth 5195fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5196e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5197fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5198fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5199fcf5ef2aSThomas Huth } 5200fcf5ef2aSThomas Huth 5201fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5202fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5203fcf5ef2aSThomas Huth 5204fcf5ef2aSThomas Huth /* mfsr */ 5205fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5206fcf5ef2aSThomas Huth { 5207fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52089f0cf041SMatheus Ferst GEN_PRIV(ctx); 5209fcf5ef2aSThomas Huth #else 5210fcf5ef2aSThomas Huth TCGv t0; 5211fcf5ef2aSThomas Huth 52129f0cf041SMatheus Ferst CHK_SV(ctx); 52137058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5214fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5215fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5216fcf5ef2aSThomas Huth } 5217fcf5ef2aSThomas Huth 5218fcf5ef2aSThomas Huth /* mfsrin */ 5219fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5220fcf5ef2aSThomas Huth { 5221fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52229f0cf041SMatheus Ferst GEN_PRIV(ctx); 5223fcf5ef2aSThomas Huth #else 5224fcf5ef2aSThomas Huth TCGv t0; 5225fcf5ef2aSThomas Huth 52269f0cf041SMatheus Ferst CHK_SV(ctx); 5227fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5228e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5229fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5230fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5231fcf5ef2aSThomas Huth } 5232fcf5ef2aSThomas Huth 5233fcf5ef2aSThomas Huth /* mtsr */ 5234fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5235fcf5ef2aSThomas Huth { 5236fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52379f0cf041SMatheus Ferst GEN_PRIV(ctx); 5238fcf5ef2aSThomas Huth #else 5239fcf5ef2aSThomas Huth TCGv t0; 5240fcf5ef2aSThomas Huth 52419f0cf041SMatheus Ferst CHK_SV(ctx); 52427058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5243fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5244fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5245fcf5ef2aSThomas Huth } 5246fcf5ef2aSThomas Huth 5247fcf5ef2aSThomas Huth /* mtsrin */ 5248fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5249fcf5ef2aSThomas Huth { 5250fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52519f0cf041SMatheus Ferst GEN_PRIV(ctx); 5252fcf5ef2aSThomas Huth #else 5253fcf5ef2aSThomas Huth TCGv t0; 5254fcf5ef2aSThomas Huth 52559f0cf041SMatheus Ferst CHK_SV(ctx); 5256fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5257e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5258fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5259fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5260fcf5ef2aSThomas Huth } 5261fcf5ef2aSThomas Huth 5262fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5263fcf5ef2aSThomas Huth 5264fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5265fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5266fcf5ef2aSThomas Huth 5267fcf5ef2aSThomas Huth /* tlbia */ 5268fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5269fcf5ef2aSThomas Huth { 5270fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52719f0cf041SMatheus Ferst GEN_PRIV(ctx); 5272fcf5ef2aSThomas Huth #else 52739f0cf041SMatheus Ferst CHK_HV(ctx); 5274fcf5ef2aSThomas Huth 5275fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5276fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5277fcf5ef2aSThomas Huth } 5278fcf5ef2aSThomas Huth 5279fcf5ef2aSThomas Huth /* tlbsync */ 5280fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5281fcf5ef2aSThomas Huth { 5282fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52839f0cf041SMatheus Ferst GEN_PRIV(ctx); 5284fcf5ef2aSThomas Huth #else 528591c60f12SCédric Le Goater 528691c60f12SCédric Le Goater if (ctx->gtse) { 52879f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 528891c60f12SCédric Le Goater } else { 52899f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 529091c60f12SCédric Le Goater } 5291fcf5ef2aSThomas Huth 5292fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5293fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5294fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5295fcf5ef2aSThomas Huth } 5296fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5297fcf5ef2aSThomas Huth } 5298fcf5ef2aSThomas Huth 5299fcf5ef2aSThomas Huth /*** External control ***/ 5300fcf5ef2aSThomas Huth /* Optional: */ 5301fcf5ef2aSThomas Huth 5302fcf5ef2aSThomas Huth /* eciwx */ 5303fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5304fcf5ef2aSThomas Huth { 5305fcf5ef2aSThomas Huth TCGv t0; 5306fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5307fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5308fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5309fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5310c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5311c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5312fcf5ef2aSThomas Huth } 5313fcf5ef2aSThomas Huth 5314fcf5ef2aSThomas Huth /* ecowx */ 5315fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5316fcf5ef2aSThomas Huth { 5317fcf5ef2aSThomas Huth TCGv t0; 5318fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5319fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5320fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5321fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5322c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5323c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5324fcf5ef2aSThomas Huth } 5325fcf5ef2aSThomas Huth 5326fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5327fcf5ef2aSThomas Huth 5328fcf5ef2aSThomas Huth /* tlbld */ 5329fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5330fcf5ef2aSThomas Huth { 5331fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53329f0cf041SMatheus Ferst GEN_PRIV(ctx); 5333fcf5ef2aSThomas Huth #else 53349f0cf041SMatheus Ferst CHK_SV(ctx); 5335fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5336fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5337fcf5ef2aSThomas Huth } 5338fcf5ef2aSThomas Huth 5339fcf5ef2aSThomas Huth /* tlbli */ 5340fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5341fcf5ef2aSThomas Huth { 5342fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53439f0cf041SMatheus Ferst GEN_PRIV(ctx); 5344fcf5ef2aSThomas Huth #else 53459f0cf041SMatheus Ferst CHK_SV(ctx); 5346fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5347fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5348fcf5ef2aSThomas Huth } 5349fcf5ef2aSThomas Huth 5350fcf5ef2aSThomas Huth /* BookE specific instructions */ 5351fcf5ef2aSThomas Huth 5352fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5353fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5354fcf5ef2aSThomas Huth { 5355fcf5ef2aSThomas Huth /* XXX: TODO */ 5356fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5357fcf5ef2aSThomas Huth } 5358fcf5ef2aSThomas Huth 5359fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5360fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5361fcf5ef2aSThomas Huth { 5362fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53639f0cf041SMatheus Ferst GEN_PRIV(ctx); 5364fcf5ef2aSThomas Huth #else 5365fcf5ef2aSThomas Huth TCGv t0; 5366fcf5ef2aSThomas Huth 53679f0cf041SMatheus Ferst CHK_SV(ctx); 5368fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5369fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5370fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5371fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5372fcf5ef2aSThomas Huth } 5373fcf5ef2aSThomas Huth 5374fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5375fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5376fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5377fcf5ef2aSThomas Huth { 5378fcf5ef2aSThomas Huth TCGv t0, t1; 5379fcf5ef2aSThomas Huth 53809723281fSRichard Henderson t0 = tcg_temp_new(); 53819723281fSRichard Henderson t1 = tcg_temp_new(); 5382fcf5ef2aSThomas Huth 5383fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5384fcf5ef2aSThomas Huth case 0x05: 5385fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5386fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5387fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5388fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5389fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5390fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5391fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5392fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5393fcf5ef2aSThomas Huth break; 5394fcf5ef2aSThomas Huth case 0x04: 5395fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5396fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5397fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5398fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5399fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5400fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5401fcf5ef2aSThomas Huth break; 5402fcf5ef2aSThomas Huth case 0x01: 5403fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5404fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5405fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5406fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5407fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5408fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5409fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5410fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5411fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5412fcf5ef2aSThomas Huth break; 5413fcf5ef2aSThomas Huth case 0x00: 5414fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5415fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5416fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5417fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5418fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5419fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5420fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5421fcf5ef2aSThomas Huth break; 5422fcf5ef2aSThomas Huth case 0x0D: 5423fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5424fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5425fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5426fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5427fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5428fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5429fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5430fcf5ef2aSThomas Huth break; 5431fcf5ef2aSThomas Huth case 0x0C: 5432fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5433fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5434fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5435fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5436fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5437fcf5ef2aSThomas Huth break; 5438fcf5ef2aSThomas Huth } 5439fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5440fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5441fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5442fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5443fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5444fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5445fcf5ef2aSThomas Huth } else { 5446fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5447fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5448fcf5ef2aSThomas Huth } 5449fcf5ef2aSThomas Huth 5450fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5451fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5452fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5453fcf5ef2aSThomas Huth 5454fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5455fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5456fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5457fcf5ef2aSThomas Huth } 5458fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5459fcf5ef2aSThomas Huth /* Signed */ 5460fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5461fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5462fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5463fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5464fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5465fcf5ef2aSThomas Huth /* Saturate */ 5466fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5467fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5468fcf5ef2aSThomas Huth } 5469fcf5ef2aSThomas Huth } else { 5470fcf5ef2aSThomas Huth /* Unsigned */ 5471fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5472fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5473fcf5ef2aSThomas Huth /* Saturate */ 5474fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5475fcf5ef2aSThomas Huth } 5476fcf5ef2aSThomas Huth } 5477fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5478fcf5ef2aSThomas Huth /* Check overflow */ 5479fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5480fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5481fcf5ef2aSThomas Huth } 5482fcf5ef2aSThomas Huth gen_set_label(l1); 5483fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5484fcf5ef2aSThomas Huth } 5485fcf5ef2aSThomas Huth } else { 5486fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5487fcf5ef2aSThomas Huth } 5488fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5489fcf5ef2aSThomas Huth /* Update Rc0 */ 5490fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5491fcf5ef2aSThomas Huth } 5492fcf5ef2aSThomas Huth } 5493fcf5ef2aSThomas Huth 5494fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5495fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5496fcf5ef2aSThomas Huth { \ 5497fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5498fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5499fcf5ef2aSThomas Huth } 5500fcf5ef2aSThomas Huth 5501fcf5ef2aSThomas Huth /* macchw - macchw. */ 5502fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5503fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5504fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5505fcf5ef2aSThomas Huth /* macchws - macchws. */ 5506fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5507fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5508fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5509fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5510fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5511fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5512fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5513fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5514fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5515fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5516fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5517fcf5ef2aSThomas Huth /* machhw - machhw. */ 5518fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5519fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5520fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5521fcf5ef2aSThomas Huth /* machhws - machhws. */ 5522fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5523fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5524fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5525fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5526fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5527fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5528fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5529fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5530fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5531fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5532fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5533fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5534fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5535fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5536fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5537fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5538fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5539fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5540fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5541fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5542fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5543fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5544fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5545fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5546fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5547fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5549fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5551fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5553fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5555fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5557fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5559fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5561fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5563fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5565fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5567fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5569fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5571fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5573fcf5ef2aSThomas Huth 5574fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5576fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5578fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5580fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5582fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5583fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5584fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5585fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5586fcf5ef2aSThomas Huth 5587fcf5ef2aSThomas Huth /* mfdcr */ 5588fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5589fcf5ef2aSThomas Huth { 5590fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55919f0cf041SMatheus Ferst GEN_PRIV(ctx); 5592fcf5ef2aSThomas Huth #else 5593fcf5ef2aSThomas Huth TCGv dcrn; 5594fcf5ef2aSThomas Huth 55959f0cf041SMatheus Ferst CHK_SV(ctx); 55967058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5597fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5598fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5599fcf5ef2aSThomas Huth } 5600fcf5ef2aSThomas Huth 5601fcf5ef2aSThomas Huth /* mtdcr */ 5602fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5603fcf5ef2aSThomas Huth { 5604fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56059f0cf041SMatheus Ferst GEN_PRIV(ctx); 5606fcf5ef2aSThomas Huth #else 5607fcf5ef2aSThomas Huth TCGv dcrn; 5608fcf5ef2aSThomas Huth 56099f0cf041SMatheus Ferst CHK_SV(ctx); 56107058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5611fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5612fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5613fcf5ef2aSThomas Huth } 5614fcf5ef2aSThomas Huth 5615fcf5ef2aSThomas Huth /* mfdcrx */ 5616fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5617fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5618fcf5ef2aSThomas Huth { 5619fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56209f0cf041SMatheus Ferst GEN_PRIV(ctx); 5621fcf5ef2aSThomas Huth #else 56229f0cf041SMatheus Ferst CHK_SV(ctx); 5623fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5624fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5625fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5626fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5627fcf5ef2aSThomas Huth } 5628fcf5ef2aSThomas Huth 5629fcf5ef2aSThomas Huth /* mtdcrx */ 5630fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5631fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5632fcf5ef2aSThomas Huth { 5633fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56349f0cf041SMatheus Ferst GEN_PRIV(ctx); 5635fcf5ef2aSThomas Huth #else 56369f0cf041SMatheus Ferst CHK_SV(ctx); 5637fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5638fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5639fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5640fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5641fcf5ef2aSThomas Huth } 5642fcf5ef2aSThomas Huth 5643fcf5ef2aSThomas Huth /* dccci */ 5644fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5645fcf5ef2aSThomas Huth { 56469f0cf041SMatheus Ferst CHK_SV(ctx); 5647fcf5ef2aSThomas Huth /* interpreted as no-op */ 5648fcf5ef2aSThomas Huth } 5649fcf5ef2aSThomas Huth 5650fcf5ef2aSThomas Huth /* dcread */ 5651fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5652fcf5ef2aSThomas Huth { 5653fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56549f0cf041SMatheus Ferst GEN_PRIV(ctx); 5655fcf5ef2aSThomas Huth #else 5656fcf5ef2aSThomas Huth TCGv EA, val; 5657fcf5ef2aSThomas Huth 56589f0cf041SMatheus Ferst CHK_SV(ctx); 5659fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5660fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5661fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5662fcf5ef2aSThomas Huth val = tcg_temp_new(); 5663fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5664fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5665fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5666fcf5ef2aSThomas Huth } 5667fcf5ef2aSThomas Huth 5668fcf5ef2aSThomas Huth /* icbt */ 5669fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5670fcf5ef2aSThomas Huth { 5671efe843d8SDavid Gibson /* 5672efe843d8SDavid Gibson * interpreted as no-op 5673efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5674efe843d8SDavid Gibson * does not generate any exception 5675fcf5ef2aSThomas Huth */ 5676fcf5ef2aSThomas Huth } 5677fcf5ef2aSThomas Huth 5678fcf5ef2aSThomas Huth /* iccci */ 5679fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5680fcf5ef2aSThomas Huth { 56819f0cf041SMatheus Ferst CHK_SV(ctx); 5682fcf5ef2aSThomas Huth /* interpreted as no-op */ 5683fcf5ef2aSThomas Huth } 5684fcf5ef2aSThomas Huth 5685fcf5ef2aSThomas Huth /* icread */ 5686fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5687fcf5ef2aSThomas Huth { 56889f0cf041SMatheus Ferst CHK_SV(ctx); 5689fcf5ef2aSThomas Huth /* interpreted as no-op */ 5690fcf5ef2aSThomas Huth } 5691fcf5ef2aSThomas Huth 5692fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5693fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5694fcf5ef2aSThomas Huth { 5695fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56969f0cf041SMatheus Ferst GEN_PRIV(ctx); 5697fcf5ef2aSThomas Huth #else 56989f0cf041SMatheus Ferst CHK_SV(ctx); 5699fcf5ef2aSThomas Huth /* Restore CPU state */ 5700fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 570159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5702fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5703fcf5ef2aSThomas Huth } 5704fcf5ef2aSThomas Huth 5705fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5706fcf5ef2aSThomas Huth { 5707fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57089f0cf041SMatheus Ferst GEN_PRIV(ctx); 5709fcf5ef2aSThomas Huth #else 57109f0cf041SMatheus Ferst CHK_SV(ctx); 5711fcf5ef2aSThomas Huth /* Restore CPU state */ 5712fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 571359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5714fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5715fcf5ef2aSThomas Huth } 5716fcf5ef2aSThomas Huth 5717fcf5ef2aSThomas Huth /* BookE specific */ 5718fcf5ef2aSThomas Huth 5719fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5720fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5721fcf5ef2aSThomas Huth { 5722fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57239f0cf041SMatheus Ferst GEN_PRIV(ctx); 5724fcf5ef2aSThomas Huth #else 57259f0cf041SMatheus Ferst CHK_SV(ctx); 5726fcf5ef2aSThomas Huth /* Restore CPU state */ 5727fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 572859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5729fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5730fcf5ef2aSThomas Huth } 5731fcf5ef2aSThomas Huth 5732fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5733fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5734fcf5ef2aSThomas Huth { 5735fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57369f0cf041SMatheus Ferst GEN_PRIV(ctx); 5737fcf5ef2aSThomas Huth #else 57389f0cf041SMatheus Ferst CHK_SV(ctx); 5739fcf5ef2aSThomas Huth /* Restore CPU state */ 5740fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 574159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5742fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5743fcf5ef2aSThomas Huth } 5744fcf5ef2aSThomas Huth 5745fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5746fcf5ef2aSThomas Huth 5747fcf5ef2aSThomas Huth /* tlbre */ 5748fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5749fcf5ef2aSThomas Huth { 5750fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57519f0cf041SMatheus Ferst GEN_PRIV(ctx); 5752fcf5ef2aSThomas Huth #else 57539f0cf041SMatheus Ferst CHK_SV(ctx); 5754fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5755fcf5ef2aSThomas Huth case 0: 5756fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5757fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5758fcf5ef2aSThomas Huth break; 5759fcf5ef2aSThomas Huth case 1: 5760fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5761fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5762fcf5ef2aSThomas Huth break; 5763fcf5ef2aSThomas Huth default: 5764fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5765fcf5ef2aSThomas Huth break; 5766fcf5ef2aSThomas Huth } 5767fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5768fcf5ef2aSThomas Huth } 5769fcf5ef2aSThomas Huth 5770fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5771fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5772fcf5ef2aSThomas Huth { 5773fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57749f0cf041SMatheus Ferst GEN_PRIV(ctx); 5775fcf5ef2aSThomas Huth #else 5776fcf5ef2aSThomas Huth TCGv t0; 5777fcf5ef2aSThomas Huth 57789f0cf041SMatheus Ferst CHK_SV(ctx); 5779fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5780fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5781fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5782fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5783fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5784fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5785fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5786fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5787fcf5ef2aSThomas Huth gen_set_label(l1); 5788fcf5ef2aSThomas Huth } 5789fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5790fcf5ef2aSThomas Huth } 5791fcf5ef2aSThomas Huth 5792fcf5ef2aSThomas Huth /* tlbwe */ 5793fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5794fcf5ef2aSThomas Huth { 5795fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57969f0cf041SMatheus Ferst GEN_PRIV(ctx); 5797fcf5ef2aSThomas Huth #else 57989f0cf041SMatheus Ferst CHK_SV(ctx); 5799fcf5ef2aSThomas Huth 5800fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5801fcf5ef2aSThomas Huth case 0: 5802fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5803fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5804fcf5ef2aSThomas Huth break; 5805fcf5ef2aSThomas Huth case 1: 5806fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5807fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5808fcf5ef2aSThomas Huth break; 5809fcf5ef2aSThomas Huth default: 5810fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5811fcf5ef2aSThomas Huth break; 5812fcf5ef2aSThomas Huth } 5813fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5814fcf5ef2aSThomas Huth } 5815fcf5ef2aSThomas Huth 5816fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5817fcf5ef2aSThomas Huth 5818fcf5ef2aSThomas Huth /* tlbre */ 5819fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5820fcf5ef2aSThomas Huth { 5821fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58229f0cf041SMatheus Ferst GEN_PRIV(ctx); 5823fcf5ef2aSThomas Huth #else 58249f0cf041SMatheus Ferst CHK_SV(ctx); 5825fcf5ef2aSThomas Huth 5826fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5827fcf5ef2aSThomas Huth case 0: 5828fcf5ef2aSThomas Huth case 1: 5829fcf5ef2aSThomas Huth case 2: 5830fcf5ef2aSThomas Huth { 58317058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5832fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5833fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5834fcf5ef2aSThomas Huth } 5835fcf5ef2aSThomas Huth break; 5836fcf5ef2aSThomas Huth default: 5837fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5838fcf5ef2aSThomas Huth break; 5839fcf5ef2aSThomas Huth } 5840fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5841fcf5ef2aSThomas Huth } 5842fcf5ef2aSThomas Huth 5843fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5844fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5845fcf5ef2aSThomas Huth { 5846fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58479f0cf041SMatheus Ferst GEN_PRIV(ctx); 5848fcf5ef2aSThomas Huth #else 5849fcf5ef2aSThomas Huth TCGv t0; 5850fcf5ef2aSThomas Huth 58519f0cf041SMatheus Ferst CHK_SV(ctx); 5852fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5853fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5854fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5855fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5856fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5857fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5858fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5859fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5860fcf5ef2aSThomas Huth gen_set_label(l1); 5861fcf5ef2aSThomas Huth } 5862fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5863fcf5ef2aSThomas Huth } 5864fcf5ef2aSThomas Huth 5865fcf5ef2aSThomas Huth /* tlbwe */ 5866fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5867fcf5ef2aSThomas Huth { 5868fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58699f0cf041SMatheus Ferst GEN_PRIV(ctx); 5870fcf5ef2aSThomas Huth #else 58719f0cf041SMatheus Ferst CHK_SV(ctx); 5872fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5873fcf5ef2aSThomas Huth case 0: 5874fcf5ef2aSThomas Huth case 1: 5875fcf5ef2aSThomas Huth case 2: 5876fcf5ef2aSThomas Huth { 58777058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5878fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5879fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5880fcf5ef2aSThomas Huth } 5881fcf5ef2aSThomas Huth break; 5882fcf5ef2aSThomas Huth default: 5883fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5884fcf5ef2aSThomas Huth break; 5885fcf5ef2aSThomas Huth } 5886fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5887fcf5ef2aSThomas Huth } 5888fcf5ef2aSThomas Huth 5889fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5890fcf5ef2aSThomas Huth 5891fcf5ef2aSThomas Huth /* tlbre */ 5892fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5893fcf5ef2aSThomas Huth { 5894fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58959f0cf041SMatheus Ferst GEN_PRIV(ctx); 5896fcf5ef2aSThomas Huth #else 58979f0cf041SMatheus Ferst CHK_SV(ctx); 5898fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5899fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5900fcf5ef2aSThomas Huth } 5901fcf5ef2aSThomas Huth 5902fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5903fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5904fcf5ef2aSThomas Huth { 5905fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59069f0cf041SMatheus Ferst GEN_PRIV(ctx); 5907fcf5ef2aSThomas Huth #else 5908fcf5ef2aSThomas Huth TCGv t0; 5909fcf5ef2aSThomas Huth 59109f0cf041SMatheus Ferst CHK_SV(ctx); 5911fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5912fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 59139d15d8e1SRichard Henderson tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5914fcf5ef2aSThomas Huth } else { 59159d15d8e1SRichard Henderson t0 = cpu_gpr[rB(ctx->opcode)]; 5916fcf5ef2aSThomas Huth } 5917fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5918fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5919fcf5ef2aSThomas Huth } 5920fcf5ef2aSThomas Huth 5921fcf5ef2aSThomas Huth /* tlbwe */ 5922fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5923fcf5ef2aSThomas Huth { 5924fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59259f0cf041SMatheus Ferst GEN_PRIV(ctx); 5926fcf5ef2aSThomas Huth #else 59279f0cf041SMatheus Ferst CHK_SV(ctx); 5928fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5929fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5930fcf5ef2aSThomas Huth } 5931fcf5ef2aSThomas Huth 5932fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5933fcf5ef2aSThomas Huth { 5934fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59359f0cf041SMatheus Ferst GEN_PRIV(ctx); 5936fcf5ef2aSThomas Huth #else 5937fcf5ef2aSThomas Huth TCGv t0; 5938fcf5ef2aSThomas Huth 59399f0cf041SMatheus Ferst CHK_SV(ctx); 5940fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5941fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5942fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5943fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5944fcf5ef2aSThomas Huth } 5945fcf5ef2aSThomas Huth 5946fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5947fcf5ef2aSThomas Huth { 5948fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59499f0cf041SMatheus Ferst GEN_PRIV(ctx); 5950fcf5ef2aSThomas Huth #else 5951fcf5ef2aSThomas Huth TCGv t0; 5952fcf5ef2aSThomas Huth 59539f0cf041SMatheus Ferst CHK_SV(ctx); 5954fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5955fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5956fcf5ef2aSThomas Huth 5957fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 5958fcf5ef2aSThomas Huth case 0: 5959fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 5960fcf5ef2aSThomas Huth break; 5961fcf5ef2aSThomas Huth case 1: 5962fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 5963fcf5ef2aSThomas Huth break; 5964fcf5ef2aSThomas Huth case 3: 5965fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 5966fcf5ef2aSThomas Huth break; 5967fcf5ef2aSThomas Huth default: 5968fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5969fcf5ef2aSThomas Huth break; 5970fcf5ef2aSThomas Huth } 5971fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5972fcf5ef2aSThomas Huth } 5973fcf5ef2aSThomas Huth 5974fcf5ef2aSThomas Huth /* wrtee */ 5975fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 5976fcf5ef2aSThomas Huth { 5977fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59789f0cf041SMatheus Ferst GEN_PRIV(ctx); 5979fcf5ef2aSThomas Huth #else 5980fcf5ef2aSThomas Huth TCGv t0; 5981fcf5ef2aSThomas Huth 59829f0cf041SMatheus Ferst CHK_SV(ctx); 5983fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5984fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 5985fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 5986fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 59872fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 5988efe843d8SDavid Gibson /* 5989efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 5990efe843d8SDavid Gibson * just set msr_ee to 1 5991fcf5ef2aSThomas Huth */ 5992d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 5993fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5994fcf5ef2aSThomas Huth } 5995fcf5ef2aSThomas Huth 5996fcf5ef2aSThomas Huth /* wrteei */ 5997fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 5998fcf5ef2aSThomas Huth { 5999fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60009f0cf041SMatheus Ferst GEN_PRIV(ctx); 6001fcf5ef2aSThomas Huth #else 60029f0cf041SMatheus Ferst CHK_SV(ctx); 6003fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6004fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 60052fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6006fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6007d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6008fcf5ef2aSThomas Huth } else { 6009fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6010fcf5ef2aSThomas Huth } 6011fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6012fcf5ef2aSThomas Huth } 6013fcf5ef2aSThomas Huth 6014fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6015fcf5ef2aSThomas Huth 6016fcf5ef2aSThomas Huth /* dlmzb */ 6017fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6018fcf5ef2aSThomas Huth { 60197058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6020fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6021fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6022fcf5ef2aSThomas Huth } 6023fcf5ef2aSThomas Huth 6024fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6025fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6026fcf5ef2aSThomas Huth { 6027fcf5ef2aSThomas Huth /* interpreted as no-op */ 6028fcf5ef2aSThomas Huth } 6029fcf5ef2aSThomas Huth 6030fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6031fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6032fcf5ef2aSThomas Huth { 603327a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 603427a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 603527a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 603627a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 603727a3ea7eSBALATON Zoltan } 603827a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6039fcf5ef2aSThomas Huth } 6040fcf5ef2aSThomas Huth 6041fcf5ef2aSThomas Huth /* icbt */ 6042fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6043fcf5ef2aSThomas Huth { 6044efe843d8SDavid Gibson /* 6045efe843d8SDavid Gibson * interpreted as no-op 6046efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6047efe843d8SDavid Gibson * does not generate any exception 6048fcf5ef2aSThomas Huth */ 6049fcf5ef2aSThomas Huth } 6050fcf5ef2aSThomas Huth 6051fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6052fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6053fcf5ef2aSThomas Huth { 6054fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6055fcf5ef2aSThomas Huth 6056fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6057fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6058fcf5ef2aSThomas Huth } 6059fcf5ef2aSThomas Huth 6060fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6061fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6062fcf5ef2aSThomas Huth { 6063fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6064fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6065fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6066fcf5ef2aSThomas Huth 6067fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6068fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6069fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6070fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6071fcf5ef2aSThomas Huth } else { 6072fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6073fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6074fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6075fcf5ef2aSThomas Huth } 6076fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6077fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6078fcf5ef2aSThomas Huth } 6079fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6080fcf5ef2aSThomas Huth 6081fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6082fcf5ef2aSThomas Huth { 6083fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6084fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6085fcf5ef2aSThomas Huth return; 6086fcf5ef2aSThomas Huth } 6087fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6088fcf5ef2aSThomas Huth } 6089fcf5ef2aSThomas Huth 6090fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6091fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6092fcf5ef2aSThomas Huth { \ 6093fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6094fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6095fcf5ef2aSThomas Huth return; \ 6096fcf5ef2aSThomas Huth } \ 6097efe843d8SDavid Gibson /* \ 6098efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6099fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6100fcf5ef2aSThomas Huth * \ 6101fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6102fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6103fcf5ef2aSThomas Huth */ \ 6104fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6105fcf5ef2aSThomas Huth } 6106fcf5ef2aSThomas Huth 6107fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6108fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6109fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6110fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6111fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6112fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6113fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6114efe843d8SDavid Gibson 6115b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6116b8b4576eSSuraj Jitindar Singh { 6117efe843d8SDavid Gibson /* Do Nothing */ 6118b8b4576eSSuraj Jitindar Singh } 6119fcf5ef2aSThomas Huth 612080b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 612180b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 612280b8c1eeSNikunj A Dadhania { \ 6123efe843d8SDavid Gibson /* \ 6124efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6125efe843d8SDavid Gibson * implementation of the copy paste facility \ 612680b8c1eeSNikunj A Dadhania */ \ 612780b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 612880b8c1eeSNikunj A Dadhania } 612980b8c1eeSNikunj A Dadhania 613080b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 613180b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 613280b8c1eeSNikunj A Dadhania 6133fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6134fcf5ef2aSThomas Huth { 6135fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6136fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6137fcf5ef2aSThomas Huth return; 6138fcf5ef2aSThomas Huth } 6139efe843d8SDavid Gibson /* 6140efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6141efe843d8SDavid Gibson * simple: 6142fcf5ef2aSThomas Huth * 6143fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6144fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6145fcf5ef2aSThomas Huth */ 6146fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6147fcf5ef2aSThomas Huth } 6148fcf5ef2aSThomas Huth 6149fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6150fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6151fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6152fcf5ef2aSThomas Huth { \ 61539f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6154fcf5ef2aSThomas Huth } 6155fcf5ef2aSThomas Huth 6156fcf5ef2aSThomas Huth #else 6157fcf5ef2aSThomas Huth 6158fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6159fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6160fcf5ef2aSThomas Huth { \ 61619f0cf041SMatheus Ferst CHK_SV(ctx); \ 6162fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6163fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6164fcf5ef2aSThomas Huth return; \ 6165fcf5ef2aSThomas Huth } \ 6166efe843d8SDavid Gibson /* \ 6167efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6168fcf5ef2aSThomas Huth * simple: \ 6169fcf5ef2aSThomas Huth * \ 6170fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6171fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6172fcf5ef2aSThomas Huth */ \ 6173fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6174fcf5ef2aSThomas Huth } 6175fcf5ef2aSThomas Huth 6176fcf5ef2aSThomas Huth #endif 6177fcf5ef2aSThomas Huth 6178fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6179fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6180fcf5ef2aSThomas Huth 61811a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 61821a404c91SMark Cave-Ayland { 6183e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 61841a404c91SMark Cave-Ayland } 61851a404c91SMark Cave-Ayland 61861a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 61871a404c91SMark Cave-Ayland { 6188e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 61894b65b6e7SVíctor Colombo /* 61904b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 61914b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 61924b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 61934b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 61944b65b6e7SVíctor Colombo * to be 0. 61954b65b6e7SVíctor Colombo */ 61964b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 61971a404c91SMark Cave-Ayland } 61981a404c91SMark Cave-Ayland 6199c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6200c4a18dbfSMark Cave-Ayland { 620137da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6202c4a18dbfSMark Cave-Ayland } 6203c4a18dbfSMark Cave-Ayland 6204c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6205c4a18dbfSMark Cave-Ayland { 620637da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6207c4a18dbfSMark Cave-Ayland } 6208c4a18dbfSMark Cave-Ayland 6209c9826ae9SRichard Henderson /* 6210f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6211f2aabda8SRichard Henderson */ 6212d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6213d39b2cc7SLuis Pires { 6214d39b2cc7SLuis Pires return x * 2; 6215d39b2cc7SLuis Pires } 6216d39b2cc7SLuis Pires 6217f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6218f2aabda8SRichard Henderson { 6219f2aabda8SRichard Henderson return x * 4; 6220f2aabda8SRichard Henderson } 6221f2aabda8SRichard Henderson 6222e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6223e10271e1SMatheus Ferst { 6224e10271e1SMatheus Ferst return x * 16; 6225e10271e1SMatheus Ferst } 6226e10271e1SMatheus Ferst 6227670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6228670f1da3SVíctor Colombo { 6229670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6230670f1da3SVíctor Colombo } 6231670f1da3SVíctor Colombo 6232f2aabda8SRichard Henderson /* 6233c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6234c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6235c9826ae9SRichard Henderson * proper variable. 6236c9826ae9SRichard Henderson */ 6237c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6238c9826ae9SRichard Henderson do { \ 6239c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6240c9826ae9SRichard Henderson return false; \ 6241c9826ae9SRichard Henderson } \ 6242c9826ae9SRichard Henderson } while (0) 6243c9826ae9SRichard Henderson 6244c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6245c9826ae9SRichard Henderson do { \ 6246c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6247c9826ae9SRichard Henderson return false; \ 6248c9826ae9SRichard Henderson } \ 6249c9826ae9SRichard Henderson } while (0) 6250c9826ae9SRichard Henderson 6251c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6252c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6253c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6254c9826ae9SRichard Henderson #else 6255c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6256c9826ae9SRichard Henderson #endif 6257c9826ae9SRichard Henderson 6258e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6259e2205a46SBruno Larsen do { \ 6260e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6261e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6262e2205a46SBruno Larsen return true; \ 6263e2205a46SBruno Larsen } \ 6264e2205a46SBruno Larsen } while (0) 6265e2205a46SBruno Larsen 62668226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 62678226cb2dSBruno Larsen (billionai) do { \ 62688226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 62698226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 62708226cb2dSBruno Larsen (billionai) return true; \ 62718226cb2dSBruno Larsen (billionai) } \ 62728226cb2dSBruno Larsen (billionai) } while (0) 62738226cb2dSBruno Larsen (billionai) 627486057426SFernando Valle #define REQUIRE_FPU(ctx) \ 627586057426SFernando Valle do { \ 627686057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 627786057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 627886057426SFernando Valle return true; \ 627986057426SFernando Valle } \ 628086057426SFernando Valle } while (0) 628186057426SFernando Valle 6282fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6283fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6284fc34e81aSMatheus Ferst do { \ 6285fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6286fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6287fc34e81aSMatheus Ferst return true; \ 6288fc34e81aSMatheus Ferst } \ 6289fc34e81aSMatheus Ferst } while (0) 6290fc34e81aSMatheus Ferst 6291fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6292fc34e81aSMatheus Ferst do { \ 6293e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6294fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6295fc34e81aSMatheus Ferst return true; \ 6296fc34e81aSMatheus Ferst } \ 6297fc34e81aSMatheus Ferst } while (0) 6298fc34e81aSMatheus Ferst #else 6299fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6300fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6301fc34e81aSMatheus Ferst #endif 6302fc34e81aSMatheus Ferst 6303f2aabda8SRichard Henderson /* 6304f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6305f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6306f2aabda8SRichard Henderson */ 6307f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6308f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6309f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 631019f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 631119f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 631219f0862dSLuis Pires { \ 631319f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 631419f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 631519f0862dSLuis Pires } 631619f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 631719f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 631819f0862dSLuis Pires { \ 631919f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 632019f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 632119f0862dSLuis Pires } 6322f2aabda8SRichard Henderson 6323f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6324f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6325f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 632619f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 632719f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 632819f0862dSLuis Pires { \ 632919f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 633019f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 633119f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 633219f0862dSLuis Pires } 6333f2aabda8SRichard Henderson 6334f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6335f2aabda8SRichard Henderson 6336f2aabda8SRichard Henderson 633799082815SRichard Henderson #include "decode-insn32.c.inc" 633899082815SRichard Henderson #include "decode-insn64.c.inc" 6339565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6340565cb109SGustavo Romero 6341725b2d4dSFernando Eckhardt Valle /* 6342725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6343725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6344725b2d4dSFernando Eckhardt Valle */ 6345725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6346725b2d4dSFernando Eckhardt Valle { 6347725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6348725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6349725b2d4dSFernando Eckhardt Valle d->si = a->si; 6350725b2d4dSFernando Eckhardt Valle if (a->r) { 6351725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6352725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6353725b2d4dSFernando Eckhardt Valle return false; 6354725b2d4dSFernando Eckhardt Valle } 6355725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6356725b2d4dSFernando Eckhardt Valle } 6357725b2d4dSFernando Eckhardt Valle return true; 6358725b2d4dSFernando Eckhardt Valle } 6359725b2d4dSFernando Eckhardt Valle 636099082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 636199082815SRichard Henderson 6362139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6363fcf5ef2aSThomas Huth 6364139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6365fcf5ef2aSThomas Huth 6366139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6367fcf5ef2aSThomas Huth 6368139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6369fcf5ef2aSThomas Huth 6370139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6371fcf5ef2aSThomas Huth 63721f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 63731f26c751SDaniel Henrique Barboza 637498f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 637598f43417SMatheus Ferst 6376016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6377016b6e1dSLeandro Lupori 637820e2d04eSLeandro Lupori /* Handles lfdp */ 63795cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 63805cb091a4SNikunj A Dadhania { 638120e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 63825cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 63835cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 63845cb091a4SNikunj A Dadhania } 63855cb091a4SNikunj A Dadhania } 63865cb091a4SNikunj A Dadhania return gen_invalid(ctx); 63875cb091a4SNikunj A Dadhania } 63885cb091a4SNikunj A Dadhania 638920e2d04eSLeandro Lupori /* Handles stfdp */ 6390e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6391e3001664SNikunj A Dadhania { 639220e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 639320e2d04eSLeandro Lupori /* stfdp */ 6394e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6395e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6396e3001664SNikunj A Dadhania } 6397e3001664SNikunj A Dadhania } 6398e3001664SNikunj A Dadhania return gen_invalid(ctx); 6399e3001664SNikunj A Dadhania } 6400e3001664SNikunj A Dadhania 64019d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64029d69cfa2SLijun Pan /* brd */ 64039d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 64049d69cfa2SLijun Pan { 64059d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64069d69cfa2SLijun Pan } 64079d69cfa2SLijun Pan 64089d69cfa2SLijun Pan /* brw */ 64099d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 64109d69cfa2SLijun Pan { 64119d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64129d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 64139d69cfa2SLijun Pan 64149d69cfa2SLijun Pan } 64159d69cfa2SLijun Pan 64169d69cfa2SLijun Pan /* brh */ 64179d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 64189d69cfa2SLijun Pan { 6419491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 64209d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 64219d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 64229d69cfa2SLijun Pan 64239d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6424491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6425491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 64269d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 64279d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 64289d69cfa2SLijun Pan } 64299d69cfa2SLijun Pan #endif 64309d69cfa2SLijun Pan 6431fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 64329d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64339d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 64349d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 64359d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 64369d69cfa2SLijun Pan #endif 6437fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6438fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6439fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6440fcf5ef2aSThomas Huth #endif 6441fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6442fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6443fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6444fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6445fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6446fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6447fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6448fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6449fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6450fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6451fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6452fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6453fcf5ef2aSThomas Huth #endif 6454fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6455fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6456fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6457fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6458fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6459fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6460fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 646180b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6462b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 646380b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6464fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6465fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6466fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6467fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6468fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6469fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6470fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6471fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6472fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6473fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6474fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6475fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6476fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6477fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6478fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6479fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6480fcf5ef2aSThomas Huth #endif 6481fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6482fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6483fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6484fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6485fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6486fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6487fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6488fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6489fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6490fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6491fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6492fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6493fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6494fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6495fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6496fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6497fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6498fcf5ef2aSThomas Huth #endif 64995cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 65005cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 650172b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6502e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6503fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6504fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6505fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6506fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6507fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6508fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6509c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6510fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6511fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6512fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6513fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6514a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6515a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6516fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6517fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6518fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6519fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6520a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6521a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6522fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6523fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6524fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6525fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6526fcf5ef2aSThomas Huth #endif 6527fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 65280c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 65290c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 65300c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6531fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6532fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6533fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6534fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6535fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6536fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6537fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6538fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6539fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 65403c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 65413c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65423c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65433c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65443c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 65453c89b8d6SNicholas Piggin #endif 6546cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6547fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6548fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6549fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6550fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6551fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6552fcf5ef2aSThomas Huth #endif 65533c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65543c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 65553c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6556fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6557fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6558fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6559fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6560fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6561fcf5ef2aSThomas Huth #endif 6562fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6563fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6564fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6565fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6566fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6567fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6568fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6569fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6570fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6571b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6572fcf5ef2aSThomas Huth #endif 6573fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6574fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6575fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 657650728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6577fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6578fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 657950728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6580fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 658150728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6582fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 658350728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6584fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6585e64645baSBernhard Beschow GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6586fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 658750728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6588fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 658999d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6590fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6591fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 659250728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6593fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6594fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6595fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6596fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6597fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6598fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6599fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6600fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6601fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6602fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6603fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6604fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6605fcf5ef2aSThomas Huth #endif 6606fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6607efe843d8SDavid Gibson /* 6608efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6609efe843d8SDavid Gibson * different ISA versions 6610efe843d8SDavid Gibson */ 6611fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6612fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6613fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6614fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6615fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6616fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6617fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6618fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6619fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6620fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6621fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6622fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6623fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6624fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6625fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6626fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6627fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6628fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6629fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6630fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6631fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6632fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6633fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6634fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6635fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6636fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6637fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6638fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6639fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6640fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6641fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6642fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6643fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6644fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6645fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6646fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6647fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6648fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6649fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6650fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6651fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 665227a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6653fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6654fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 66550c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 66560c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6657fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6658fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6659fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6660fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6661fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6662fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6663fcf5ef2aSThomas Huth PPC2_ISA300), 6664fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6665fcf5ef2aSThomas Huth #endif 6666fcf5ef2aSThomas Huth 6667fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6668fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6669fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6670fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6671fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6672fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6673fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6674fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6675fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6676fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6677fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6678fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6679fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6680fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6681fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 66824c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6683fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6684fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6685fcf5ef2aSThomas Huth 6686fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6687fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6688fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6689fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6690fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6691fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6692fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6693fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6694fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6695fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6696fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6697fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6698fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6699fcf5ef2aSThomas Huth 6700fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6701fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6702fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6703fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6704fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6705fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6706fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6707fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6708fcf5ef2aSThomas Huth 6709fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6710fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6711fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6712fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6713fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6714fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6715fcf5ef2aSThomas Huth 6716fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6717fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6718fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6719fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6720fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6721fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6722fcf5ef2aSThomas Huth #endif 6723fcf5ef2aSThomas Huth 6724fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6725fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6726fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6727fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6728fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6729fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6730fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6731fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6732fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6733fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6734fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6735fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6736fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6737fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6738fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6739fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6740fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6741fcf5ef2aSThomas Huth 6742fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6743fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6744fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6745fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6746fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6747fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6748fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6749fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6750fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6751fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6752fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6753fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6754fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6755fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6756fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6757fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6758fcf5ef2aSThomas Huth #endif 6759fcf5ef2aSThomas Huth 6760fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6761fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6762fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6763fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6764fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6765fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6766fcf5ef2aSThomas Huth PPC_64B) 6767fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6768fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6769fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6770fcf5ef2aSThomas Huth PPC_64B), \ 6771fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6772fcf5ef2aSThomas Huth PPC_64B), \ 6773fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6774fcf5ef2aSThomas Huth PPC_64B) 6775fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6776fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6777fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6778fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6779fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6780fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6781fcf5ef2aSThomas Huth #endif 6782fcf5ef2aSThomas Huth 6783fcf5ef2aSThomas Huth #undef GEN_LDX_E 6784fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6785fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6786fcf5ef2aSThomas Huth 6787fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6788fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6789fcf5ef2aSThomas Huth 6790fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6791fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6792fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6793fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6794fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6795fcf5ef2aSThomas Huth #endif 6796fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6797fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6798fcf5ef2aSThomas Huth 679950728199SRoman Kapl /* External PID based load */ 680050728199SRoman Kapl #undef GEN_LDEPX 680150728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 680250728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 680350728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 680450728199SRoman Kapl 680550728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 680650728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 680750728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 680850728199SRoman Kapl #if defined(TARGET_PPC64) 6809fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 681050728199SRoman Kapl #endif 681150728199SRoman Kapl 6812fcf5ef2aSThomas Huth #undef GEN_STX_E 6813fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 68140123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6815fcf5ef2aSThomas Huth 6816fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6817fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6818fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6819fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6820fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6821fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6822fcf5ef2aSThomas Huth #endif 6823fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6824fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6825fcf5ef2aSThomas Huth 682650728199SRoman Kapl #undef GEN_STEPX 682750728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 682850728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 682950728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 683050728199SRoman Kapl 683150728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 683250728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 683350728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 683450728199SRoman Kapl #if defined(TARGET_PPC64) 6835fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 683650728199SRoman Kapl #endif 683750728199SRoman Kapl 6838fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6839fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6840fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6841fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6842fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6843fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6844fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6845fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6846fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6847fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6848fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6849fcf5ef2aSThomas Huth 6850fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6851fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6852fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6853fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6854fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6855fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6856fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6857fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6858fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6859fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6860fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6861fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6862fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6863fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6864fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6865fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6866fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6867fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6868fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6869fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6870fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6871fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6872fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6873fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6874fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6875fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6876fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6877fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6878fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6879fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6880fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6881fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6882fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6883fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6884fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6885fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6886fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6887fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6888fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6889fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6890fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6891fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6892fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6893fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6894fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6895fcf5ef2aSThomas Huth 6896fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6897fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6898fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6899fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6900fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6901fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6902fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6903fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6904fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6905fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6906fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6907fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6908fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6909fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6910fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6911fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6912fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6913fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6914fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6915fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6916fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6917fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6918fcf5ef2aSThomas Huth 6919139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 6920fcf5ef2aSThomas Huth 6921139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 6922fcf5ef2aSThomas Huth 6923139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 6924fcf5ef2aSThomas Huth 6925139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 6926fcf5ef2aSThomas Huth }; 6927fcf5ef2aSThomas Huth 69287468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 69297468e2c8SBruno Larsen (billionai) /* Opcode types */ 69307468e2c8SBruno Larsen (billionai) enum { 69317468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 69327468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 69337468e2c8SBruno Larsen (billionai) }; 69347468e2c8SBruno Larsen (billionai) 69357468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 69367468e2c8SBruno Larsen (billionai) 69377468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 69387468e2c8SBruno Larsen (billionai) { 69397468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 69407468e2c8SBruno Larsen (billionai) } 69417468e2c8SBruno Larsen (billionai) 69427468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 69437468e2c8SBruno Larsen (billionai) { 69447468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 69457468e2c8SBruno Larsen (billionai) } 69467468e2c8SBruno Larsen (billionai) 69477468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 69487468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 69497468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 69507468e2c8SBruno Larsen (billionai) { 69517468e2c8SBruno Larsen (billionai) int i; 69527468e2c8SBruno Larsen (billionai) 69537468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 69547468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 69557468e2c8SBruno Larsen (billionai) } 69567468e2c8SBruno Larsen (billionai) } 69577468e2c8SBruno Larsen (billionai) 69587468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 69597468e2c8SBruno Larsen (billionai) { 69607468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 69617468e2c8SBruno Larsen (billionai) 69627468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 69637468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 69647468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 69657468e2c8SBruno Larsen (billionai) 69667468e2c8SBruno Larsen (billionai) return 0; 69677468e2c8SBruno Larsen (billionai) } 69687468e2c8SBruno Larsen (billionai) 69697468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 69707468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69717468e2c8SBruno Larsen (billionai) { 69727468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 69737468e2c8SBruno Larsen (billionai) return -1; 69747468e2c8SBruno Larsen (billionai) } 69757468e2c8SBruno Larsen (billionai) table[idx] = handler; 69767468e2c8SBruno Larsen (billionai) 69777468e2c8SBruno Larsen (billionai) return 0; 69787468e2c8SBruno Larsen (billionai) } 69797468e2c8SBruno Larsen (billionai) 69807468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 69817468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 69827468e2c8SBruno Larsen (billionai) { 69837468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 69847468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 69857468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 69867468e2c8SBruno Larsen (billionai) return -1; 69877468e2c8SBruno Larsen (billionai) } 69887468e2c8SBruno Larsen (billionai) 69897468e2c8SBruno Larsen (billionai) return 0; 69907468e2c8SBruno Larsen (billionai) } 69917468e2c8SBruno Larsen (billionai) 69927468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 69937468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 69947468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69957468e2c8SBruno Larsen (billionai) { 69967468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 69977468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 69987468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 69997468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 70007468e2c8SBruno Larsen (billionai) return -1; 70017468e2c8SBruno Larsen (billionai) } 70027468e2c8SBruno Larsen (billionai) } else { 70037468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 70047468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 70057468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 70067468e2c8SBruno Larsen (billionai) return -1; 70077468e2c8SBruno Larsen (billionai) } 70087468e2c8SBruno Larsen (billionai) } 70097468e2c8SBruno Larsen (billionai) if (handler != NULL && 70107468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 70117468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 70127468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 70137468e2c8SBruno Larsen (billionai) return -1; 70147468e2c8SBruno Larsen (billionai) } 70157468e2c8SBruno Larsen (billionai) 70167468e2c8SBruno Larsen (billionai) return 0; 70177468e2c8SBruno Larsen (billionai) } 70187468e2c8SBruno Larsen (billionai) 70197468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 70207468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70217468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70227468e2c8SBruno Larsen (billionai) { 70237468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 70247468e2c8SBruno Larsen (billionai) } 70257468e2c8SBruno Larsen (billionai) 70267468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 70277468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70287468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 70297468e2c8SBruno Larsen (billionai) { 70307468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70317468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70327468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70337468e2c8SBruno Larsen (billionai) return -1; 70347468e2c8SBruno Larsen (billionai) } 70357468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 70367468e2c8SBruno Larsen (billionai) handler) < 0) { 70377468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70387468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70397468e2c8SBruno Larsen (billionai) return -1; 70407468e2c8SBruno Larsen (billionai) } 70417468e2c8SBruno Larsen (billionai) 70427468e2c8SBruno Larsen (billionai) return 0; 70437468e2c8SBruno Larsen (billionai) } 70447468e2c8SBruno Larsen (billionai) 70457468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 70467468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70477468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 70487468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70497468e2c8SBruno Larsen (billionai) { 70507468e2c8SBruno Larsen (billionai) opc_handler_t **table; 70517468e2c8SBruno Larsen (billionai) 70527468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70537468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70547468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70557468e2c8SBruno Larsen (billionai) return -1; 70567468e2c8SBruno Larsen (billionai) } 70577468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 70587468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 70597468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 70607468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70617468e2c8SBruno Larsen (billionai) return -1; 70627468e2c8SBruno Larsen (billionai) } 70637468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 70647468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 70657468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70667468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 70677468e2c8SBruno Larsen (billionai) return -1; 70687468e2c8SBruno Larsen (billionai) } 70697468e2c8SBruno Larsen (billionai) return 0; 70707468e2c8SBruno Larsen (billionai) } 70717468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 70727468e2c8SBruno Larsen (billionai) { 70737468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 70747468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 70757468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 70767468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70777468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 70787468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 70797468e2c8SBruno Larsen (billionai) return -1; 70807468e2c8SBruno Larsen (billionai) } 70817468e2c8SBruno Larsen (billionai) } else { 70827468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 70837468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 70847468e2c8SBruno Larsen (billionai) return -1; 70857468e2c8SBruno Larsen (billionai) } 70867468e2c8SBruno Larsen (billionai) } 70877468e2c8SBruno Larsen (billionai) } else { 70887468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 70897468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 70907468e2c8SBruno Larsen (billionai) return -1; 70917468e2c8SBruno Larsen (billionai) } 70927468e2c8SBruno Larsen (billionai) } 70937468e2c8SBruno Larsen (billionai) } else { 70947468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 70957468e2c8SBruno Larsen (billionai) return -1; 70967468e2c8SBruno Larsen (billionai) } 70977468e2c8SBruno Larsen (billionai) } 70987468e2c8SBruno Larsen (billionai) 70997468e2c8SBruno Larsen (billionai) return 0; 71007468e2c8SBruno Larsen (billionai) } 71017468e2c8SBruno Larsen (billionai) 71027468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 71037468e2c8SBruno Larsen (billionai) { 71047468e2c8SBruno Larsen (billionai) int i, count, tmp; 71057468e2c8SBruno Larsen (billionai) 71067468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 71077468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 71087468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 71097468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71107468e2c8SBruno Larsen (billionai) } 71117468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 71127468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 71137468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 71147468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 71157468e2c8SBruno Larsen (billionai) if (tmp == 0) { 71167468e2c8SBruno Larsen (billionai) free(table[i]); 71177468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71187468e2c8SBruno Larsen (billionai) } else { 71197468e2c8SBruno Larsen (billionai) count++; 71207468e2c8SBruno Larsen (billionai) } 71217468e2c8SBruno Larsen (billionai) } else { 71227468e2c8SBruno Larsen (billionai) count++; 71237468e2c8SBruno Larsen (billionai) } 71247468e2c8SBruno Larsen (billionai) } 71257468e2c8SBruno Larsen (billionai) } 71267468e2c8SBruno Larsen (billionai) 71277468e2c8SBruno Larsen (billionai) return count; 71287468e2c8SBruno Larsen (billionai) } 71297468e2c8SBruno Larsen (billionai) 71307468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 71317468e2c8SBruno Larsen (billionai) { 71327468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 71337468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 71347468e2c8SBruno Larsen (billionai) } 71357468e2c8SBruno Larsen (billionai) } 71367468e2c8SBruno Larsen (billionai) 71377468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71387468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 71397468e2c8SBruno Larsen (billionai) { 71407468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 71417468e2c8SBruno Larsen (billionai) opcode_t *opc; 71427468e2c8SBruno Larsen (billionai) 71437468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 71447468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 71457468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 71467468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 71477468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 71487468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 71497468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 71507468e2c8SBruno Larsen (billionai) opc->opc3); 71517468e2c8SBruno Larsen (billionai) return; 71527468e2c8SBruno Larsen (billionai) } 71537468e2c8SBruno Larsen (billionai) } 71547468e2c8SBruno Larsen (billionai) } 71557468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 71567468e2c8SBruno Larsen (billionai) fflush(stdout); 71577468e2c8SBruno Larsen (billionai) fflush(stderr); 71587468e2c8SBruno Larsen (billionai) } 71597468e2c8SBruno Larsen (billionai) 71607468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 71617468e2c8SBruno Larsen (billionai) { 71627468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 71637468e2c8SBruno Larsen (billionai) int i, j, k; 71647468e2c8SBruno Larsen (billionai) 71657468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 71667468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 71677468e2c8SBruno Larsen (billionai) continue; 71687468e2c8SBruno Larsen (billionai) } 71697468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 71707468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 71717468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 71727468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 71737468e2c8SBruno Larsen (billionai) continue; 71747468e2c8SBruno Larsen (billionai) } 71757468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 71767468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 71777468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 71787468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 71797468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 71807468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 71817468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71827468e2c8SBruno Larsen (billionai) } 71837468e2c8SBruno Larsen (billionai) } 71847468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 71857468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71867468e2c8SBruno Larsen (billionai) } 71877468e2c8SBruno Larsen (billionai) } 71887468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 71897468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 71907468e2c8SBruno Larsen (billionai) } 71917468e2c8SBruno Larsen (billionai) } 71927468e2c8SBruno Larsen (billionai) } 71937468e2c8SBruno Larsen (billionai) 71947468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 71957468e2c8SBruno Larsen (billionai) { 71967468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 71977468e2c8SBruno Larsen (billionai) 71987468e2c8SBruno Larsen (billionai) /* 71997468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 72007468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 72017468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 72027468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 72037468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 72047468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 72057468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 72067468e2c8SBruno Larsen (billionai) */ 72077468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 72087468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 72097468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 72107468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 72117468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 72127468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 72137468e2c8SBruno Larsen (billionai) } 72147468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 72157468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 72167468e2c8SBruno Larsen (billionai) return 0; 72177468e2c8SBruno Larsen (billionai) } 72187468e2c8SBruno Larsen (billionai) 7219624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7220624cb07fSRichard Henderson { 7221624cb07fSRichard Henderson opc_handler_t **table, *handler; 7222624cb07fSRichard Henderson uint32_t inval; 7223624cb07fSRichard Henderson 7224624cb07fSRichard Henderson ctx->opcode = insn; 7225624cb07fSRichard Henderson 7226624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7227624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7228624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7229624cb07fSRichard Henderson 7230624cb07fSRichard Henderson table = cpu->opcodes; 7231624cb07fSRichard Henderson handler = table[opc1(insn)]; 7232624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7233624cb07fSRichard Henderson table = ind_table(handler); 7234624cb07fSRichard Henderson handler = table[opc2(insn)]; 7235624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7236624cb07fSRichard Henderson table = ind_table(handler); 7237624cb07fSRichard Henderson handler = table[opc3(insn)]; 7238624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7239624cb07fSRichard Henderson table = ind_table(handler); 7240624cb07fSRichard Henderson handler = table[opc4(insn)]; 7241624cb07fSRichard Henderson } 7242624cb07fSRichard Henderson } 7243624cb07fSRichard Henderson } 7244624cb07fSRichard Henderson 7245624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7246624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7247624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7248624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7249624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7250624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7251624cb07fSRichard Henderson insn, ctx->cia); 7252624cb07fSRichard Henderson return false; 7253624cb07fSRichard Henderson } 7254624cb07fSRichard Henderson 7255624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7256624cb07fSRichard Henderson && Rc(insn))) { 7257624cb07fSRichard Henderson inval = handler->inval2; 7258624cb07fSRichard Henderson } else { 7259624cb07fSRichard Henderson inval = handler->inval1; 7260624cb07fSRichard Henderson } 7261624cb07fSRichard Henderson 7262624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7263624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7264624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7265624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7266624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7267624cb07fSRichard Henderson insn, ctx->cia); 7268624cb07fSRichard Henderson return false; 7269624cb07fSRichard Henderson } 7270624cb07fSRichard Henderson 7271624cb07fSRichard Henderson handler->handler(ctx); 7272624cb07fSRichard Henderson return true; 7273624cb07fSRichard Henderson } 7274624cb07fSRichard Henderson 7275b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7276fcf5ef2aSThomas Huth { 7277b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 72789c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 72792df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7280fcf5ef2aSThomas Huth 7281b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 72822df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7283d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 72842df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 72852df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7286b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7287b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7288b0c2d521SEmilio G. Cota ctx->access_type = -1; 7289d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 72902df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7291b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 72920e3bf489SRoman Kapl ctx->flags = env->flags; 7293fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72942df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7295b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7296fcf5ef2aSThomas Huth #endif 7297e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7298d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7299fcf5ef2aSThomas Huth 73002df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 73012df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 73022df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 73032df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 73042df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7305f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 73061db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7307f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7308f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 73098b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 73108b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 731146d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 73122df4fe7aSRichard Henderson 7313b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 73142df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 73152df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 73169498d103SRichard Henderson ctx->base.max_insns = 1; 7317efe843d8SDavid Gibson } 73182df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7319b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7320efe843d8SDavid Gibson } 732113b45575SRichard Henderson } 7322fcf5ef2aSThomas Huth 7323b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7324b0c2d521SEmilio G. Cota { 7325b0c2d521SEmilio G. Cota } 7326fcf5ef2aSThomas Huth 7327b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7328b0c2d521SEmilio G. Cota { 7329b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7330b0c2d521SEmilio G. Cota } 7331b0c2d521SEmilio G. Cota 733299082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 733399082815SRichard Henderson { 733499082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 733599082815SRichard Henderson return opc1(insn) == 1; 733699082815SRichard Henderson } 733799082815SRichard Henderson 7338b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7339b0c2d521SEmilio G. Cota { 7340b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 734128876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7342b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 734399082815SRichard Henderson target_ulong pc; 7344624cb07fSRichard Henderson uint32_t insn; 7345624cb07fSRichard Henderson bool ok; 7346b0c2d521SEmilio G. Cota 7347fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7348fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7349b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7350b0c2d521SEmilio G. Cota 735199082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 73524e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 735399082815SRichard Henderson ctx->base.pc_next = pc += 4; 7354fcf5ef2aSThomas Huth 735599082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 735699082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 735799082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 735899082815SRichard Henderson } else if ((pc & 63) == 0) { 735999082815SRichard Henderson /* 736099082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 736199082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 736299082815SRichard Henderson * 64-byte address boundary (system alignment error). 736399082815SRichard Henderson */ 736499082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 736599082815SRichard Henderson ok = true; 736699082815SRichard Henderson } else { 73674e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 73684e116893SIlya Leoshkevich need_byteswap(ctx)); 736999082815SRichard Henderson ctx->base.pc_next = pc += 4; 737099082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 737199082815SRichard Henderson } 7372624cb07fSRichard Henderson if (!ok) { 7373624cb07fSRichard Henderson gen_invalid(ctx); 7374fcf5ef2aSThomas Huth } 7375624cb07fSRichard Henderson 737664a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 737799082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 737864a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 737964a0f644SRichard Henderson } 7380fcf5ef2aSThomas Huth } 7381b0c2d521SEmilio G. Cota 7382b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7383b0c2d521SEmilio G. Cota { 7384b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7385a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7386a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7387b0c2d521SEmilio G. Cota 7388a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7389a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 73903d8a5b69SRichard Henderson return; 73913d8a5b69SRichard Henderson } 73923d8a5b69SRichard Henderson 7393a9b5b3d0SRichard Henderson /* Honor single stepping. */ 73949498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 73959498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7396a9b5b3d0SRichard Henderson switch (is_jmp) { 7397a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7398a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7399a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7400a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7401a9b5b3d0SRichard Henderson break; 7402a9b5b3d0SRichard Henderson case DISAS_EXIT: 7403a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7404a9b5b3d0SRichard Henderson break; 7405a9b5b3d0SRichard Henderson default: 7406a9b5b3d0SRichard Henderson g_assert_not_reached(); 7407fcf5ef2aSThomas Huth } 740813b45575SRichard Henderson 7409a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7410a9b5b3d0SRichard Henderson return; 7411a9b5b3d0SRichard Henderson } 7412a9b5b3d0SRichard Henderson 7413a9b5b3d0SRichard Henderson switch (is_jmp) { 7414a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7415a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 741646d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7417a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7418a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7419a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7420a9b5b3d0SRichard Henderson break; 7421a9b5b3d0SRichard Henderson } 7422a9b5b3d0SRichard Henderson /* fall through */ 7423a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7424a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7425a9b5b3d0SRichard Henderson /* fall through */ 7426a9b5b3d0SRichard Henderson case DISAS_CHAIN: 742746d396bdSDaniel Henrique Barboza /* 742846d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 742946d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 743046d396bdSDaniel Henrique Barboza */ 743146d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 743246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 743346d396bdSDaniel Henrique Barboza } 743446d396bdSDaniel Henrique Barboza 7435a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7436a9b5b3d0SRichard Henderson break; 7437a9b5b3d0SRichard Henderson 7438a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7439a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7440a9b5b3d0SRichard Henderson /* fall through */ 7441a9b5b3d0SRichard Henderson case DISAS_EXIT: 744246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 744307ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7444a9b5b3d0SRichard Henderson break; 7445a9b5b3d0SRichard Henderson 7446a9b5b3d0SRichard Henderson default: 7447a9b5b3d0SRichard Henderson g_assert_not_reached(); 7448fcf5ef2aSThomas Huth } 7449fcf5ef2aSThomas Huth } 7450b0c2d521SEmilio G. Cota 74518eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 74528eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7453b0c2d521SEmilio G. Cota { 74548eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 74558eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7456b0c2d521SEmilio G. Cota } 7457b0c2d521SEmilio G. Cota 7458b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7459b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7460b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7461b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7462b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7463b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7464b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7465b0c2d521SEmilio G. Cota }; 7466b0c2d521SEmilio G. Cota 7467597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7468306c8721SRichard Henderson target_ulong pc, void *host_pc) 7469b0c2d521SEmilio G. Cota { 7470b0c2d521SEmilio G. Cota DisasContext ctx; 7471b0c2d521SEmilio G. Cota 7472306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7473fcf5ef2aSThomas Huth } 7474