1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3899e964efSFabiano Rosas #include "spr_common.h" 39fcf5ef2aSThomas Huth 403e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 413e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 44fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 47efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 1572c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 158fcf5ef2aSThomas Huth uint32_t opcode; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 1771db3632aSMatheus Ferst bool hr; 178f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 179f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 18046d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 189a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 190a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 191a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 192a9b5b3d0SRichard Henderson 193fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 194fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 195fcf5ef2aSThomas Huth { 196ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 197fcf5ef2aSThomas Huth return ctx->le_mode; 198fcf5ef2aSThomas Huth #else 199fcf5ef2aSThomas Huth return !ctx->le_mode; 200fcf5ef2aSThomas Huth #endif 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 204fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 206fcf5ef2aSThomas Huth #else 207fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 208fcf5ef2aSThomas Huth #endif 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth struct opc_handler_t { 211fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 212fcf5ef2aSThomas Huth uint32_t inval1; 213fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 214fcf5ef2aSThomas Huth uint32_t inval2; 215fcf5ef2aSThomas Huth /* instruction type */ 216fcf5ef2aSThomas Huth uint64_t type; 217fcf5ef2aSThomas Huth /* extended instruction type */ 218fcf5ef2aSThomas Huth uint64_t type2; 219fcf5ef2aSThomas Huth /* handler */ 220fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 221fcf5ef2aSThomas Huth }; 222fcf5ef2aSThomas Huth 2230e3bf489SRoman Kapl /* SPR load/store helpers */ 2240e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2250e3bf489SRoman Kapl { 2260e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2270e3bf489SRoman Kapl } 2280e3bf489SRoman Kapl 2290e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2300e3bf489SRoman Kapl { 2310e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2320e3bf489SRoman Kapl } 2330e3bf489SRoman Kapl 234fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 235fcf5ef2aSThomas Huth { 236fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 237fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 238fcf5ef2aSThomas Huth ctx->access_type = access_type; 239fcf5ef2aSThomas Huth } 240fcf5ef2aSThomas Huth } 241fcf5ef2aSThomas Huth 242fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 243fcf5ef2aSThomas Huth { 244fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 245fcf5ef2aSThomas Huth nip = (uint32_t)nip; 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 248fcf5ef2aSThomas Huth } 249fcf5ef2aSThomas Huth 250fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 251fcf5ef2aSThomas Huth { 252fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 253fcf5ef2aSThomas Huth 254efe843d8SDavid Gibson /* 255efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 256efe843d8SDavid Gibson * faulting instruction 257fcf5ef2aSThomas Huth */ 2582c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 259fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 260fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 261fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 262fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 263fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2643d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 265fcf5ef2aSThomas Huth } 266fcf5ef2aSThomas Huth 267fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 268fcf5ef2aSThomas Huth { 269fcf5ef2aSThomas Huth TCGv_i32 t0; 270fcf5ef2aSThomas Huth 271efe843d8SDavid Gibson /* 272efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 273efe843d8SDavid Gibson * faulting instruction 274fcf5ef2aSThomas Huth */ 2752c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 276fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 277fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 278fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2793d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth 282fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 283fcf5ef2aSThomas Huth target_ulong nip) 284fcf5ef2aSThomas Huth { 285fcf5ef2aSThomas Huth TCGv_i32 t0; 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 288fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 289fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 290fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2913d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 292fcf5ef2aSThomas Huth } 293fcf5ef2aSThomas Huth 294f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 295f5b6daacSRichard Henderson { 296f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 297f5b6daacSRichard Henderson gen_io_start(); 298f5b6daacSRichard Henderson /* 299f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 300f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 301f5b6daacSRichard Henderson * decide if we need to return to the main loop. 302f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 303f5b6daacSRichard Henderson */ 304f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 305f5b6daacSRichard Henderson } 306f5b6daacSRichard Henderson } 307f5b6daacSRichard Henderson 308e150ac89SRoman Kapl /* 309e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 310e150ac89SRoman Kapl * SPR registers for this exception. 311e150ac89SRoman Kapl * 312e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 313e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3140e3bf489SRoman Kapl */ 315e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3160e3bf489SRoman Kapl { 3170e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3180e3bf489SRoman Kapl target_ulong dbsr = 0; 319e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3200e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 321e150ac89SRoman Kapl } else { 322e150ac89SRoman Kapl /* Must have been branch */ 3230e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3240e3bf489SRoman Kapl } 3250e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3260e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3270e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3280e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3290e3bf489SRoman Kapl tcg_temp_free(t0); 3300e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3310e3bf489SRoman Kapl } else { 332e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3330e3bf489SRoman Kapl } 3340e3bf489SRoman Kapl } 3350e3bf489SRoman Kapl 336fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 337fcf5ef2aSThomas Huth { 3389498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3393d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 340fcf5ef2aSThomas Huth } 341fcf5ef2aSThomas Huth 342fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 343fcf5ef2aSThomas Huth { 344fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 345fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 346fcf5ef2aSThomas Huth } 347fcf5ef2aSThomas Huth 348fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 353fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 354fcf5ef2aSThomas Huth { 355fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 356fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 357fcf5ef2aSThomas Huth } 358fcf5ef2aSThomas Huth 35937f219c8SBruno Larsen (billionai) /*****************************************************************************/ 36037f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 36137f219c8SBruno Larsen (billionai) 362a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36337f219c8SBruno Larsen (billionai) { 36437f219c8SBruno Larsen (billionai) #if 0 36537f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36637f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36737f219c8SBruno Larsen (billionai) #endif 36837f219c8SBruno Larsen (billionai) } 36937f219c8SBruno Larsen (billionai) 37037f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 37137f219c8SBruno Larsen (billionai) 37237f219c8SBruno Larsen (billionai) /* 37337f219c8SBruno Larsen (billionai) * Generic callbacks: 37437f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37537f219c8SBruno Larsen (billionai) */ 37637f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37737f219c8SBruno Larsen (billionai) { 37837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 38037f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 38137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38237f219c8SBruno Larsen (billionai) #endif 38337f219c8SBruno Larsen (billionai) } 38437f219c8SBruno Larsen (billionai) 385a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38637f219c8SBruno Larsen (billionai) { 38737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38937f219c8SBruno Larsen (billionai) } 39037f219c8SBruno Larsen (billionai) 39137f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39237f219c8SBruno Larsen (billionai) { 39337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39537f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39737f219c8SBruno Larsen (billionai) #endif 39837f219c8SBruno Larsen (billionai) } 39937f219c8SBruno Larsen (billionai) 400a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 40137f219c8SBruno Larsen (billionai) { 40237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40437f219c8SBruno Larsen (billionai) } 40537f219c8SBruno Larsen (billionai) 4067aeac354SDaniel Henrique Barboza void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 4077aeac354SDaniel Henrique Barboza { 4087aeac354SDaniel Henrique Barboza spr_write_generic(ctx, sprn, gprn); 4097aeac354SDaniel Henrique Barboza 4107aeac354SDaniel Henrique Barboza /* 4117aeac354SDaniel Henrique Barboza * SPR_CTRL writes must force a new translation block, 4127aeac354SDaniel Henrique Barboza * allowing the PMU to calculate the run latch events with 4137aeac354SDaniel Henrique Barboza * more accuracy. 4147aeac354SDaniel Henrique Barboza */ 4157aeac354SDaniel Henrique Barboza ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4167aeac354SDaniel Henrique Barboza } 4177aeac354SDaniel Henrique Barboza 41837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 419a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 42037f219c8SBruno Larsen (billionai) { 42137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 42237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 42437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42737f219c8SBruno Larsen (billionai) #else 42837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 42937f219c8SBruno Larsen (billionai) #endif 43037f219c8SBruno Larsen (billionai) } 43137f219c8SBruno Larsen (billionai) 432a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 43337f219c8SBruno Larsen (billionai) { 43437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 43637f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 43737f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 43837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 43937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 44137f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 44237f219c8SBruno Larsen (billionai) } 44337f219c8SBruno Larsen (billionai) 444a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 44537f219c8SBruno Larsen (billionai) { 44637f219c8SBruno Larsen (billionai) } 44737f219c8SBruno Larsen (billionai) 44837f219c8SBruno Larsen (billionai) #endif 44937f219c8SBruno Larsen (billionai) 45037f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 45137f219c8SBruno Larsen (billionai) /* XER */ 452a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 45337f219c8SBruno Larsen (billionai) { 45437f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 45537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 45637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 45737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 45837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 45937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 46037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 46137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 46237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 46337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 46437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46537f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 46637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 46737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 46937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47037f219c8SBruno Larsen (billionai) } 47137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 47237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 47337f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 47437f219c8SBruno Larsen (billionai) } 47537f219c8SBruno Larsen (billionai) 476a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 47737f219c8SBruno Larsen (billionai) { 47837f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 47937f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 48037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 48137f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 48237f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 48337f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 48437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 48537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 48637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 48737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 48837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 48937f219c8SBruno Larsen (billionai) } 49037f219c8SBruno Larsen (billionai) 49137f219c8SBruno Larsen (billionai) /* LR */ 492a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 49337f219c8SBruno Larsen (billionai) { 49437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 49537f219c8SBruno Larsen (billionai) } 49637f219c8SBruno Larsen (billionai) 497a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 49837f219c8SBruno Larsen (billionai) { 49937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 50037f219c8SBruno Larsen (billionai) } 50137f219c8SBruno Larsen (billionai) 50237f219c8SBruno Larsen (billionai) /* CFAR */ 50337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 504a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 50537f219c8SBruno Larsen (billionai) { 50637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 50737f219c8SBruno Larsen (billionai) } 50837f219c8SBruno Larsen (billionai) 509a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 51037f219c8SBruno Larsen (billionai) { 51137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 51237f219c8SBruno Larsen (billionai) } 51337f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 51437f219c8SBruno Larsen (billionai) 51537f219c8SBruno Larsen (billionai) /* CTR */ 516a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 51737f219c8SBruno Larsen (billionai) { 51837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 51937f219c8SBruno Larsen (billionai) } 52037f219c8SBruno Larsen (billionai) 521a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 52237f219c8SBruno Larsen (billionai) { 52337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 52437f219c8SBruno Larsen (billionai) } 52537f219c8SBruno Larsen (billionai) 52637f219c8SBruno Larsen (billionai) /* User read access to SPR */ 52737f219c8SBruno Larsen (billionai) /* USPRx */ 52837f219c8SBruno Larsen (billionai) /* UMMCRx */ 52937f219c8SBruno Larsen (billionai) /* UPMCx */ 53037f219c8SBruno Larsen (billionai) /* USIA */ 53137f219c8SBruno Larsen (billionai) /* UDECR */ 532a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 53337f219c8SBruno Larsen (billionai) { 53437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 53537f219c8SBruno Larsen (billionai) } 53637f219c8SBruno Larsen (billionai) 53737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 538a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 53937f219c8SBruno Larsen (billionai) { 54037f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 54137f219c8SBruno Larsen (billionai) } 54237f219c8SBruno Larsen (billionai) #endif 54337f219c8SBruno Larsen (billionai) 54437f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 54537f219c8SBruno Larsen (billionai) /* DECR */ 54637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 547a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 54837f219c8SBruno Larsen (billionai) { 549f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55037f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 55137f219c8SBruno Larsen (billionai) } 55237f219c8SBruno Larsen (billionai) 553a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 55437f219c8SBruno Larsen (billionai) { 555f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55637f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 55737f219c8SBruno Larsen (billionai) } 55837f219c8SBruno Larsen (billionai) #endif 55937f219c8SBruno Larsen (billionai) 56037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 56137f219c8SBruno Larsen (billionai) /* Time base */ 562a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 56337f219c8SBruno Larsen (billionai) { 564f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56537f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 56637f219c8SBruno Larsen (billionai) } 56737f219c8SBruno Larsen (billionai) 568a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 56937f219c8SBruno Larsen (billionai) { 570f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57137f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 57237f219c8SBruno Larsen (billionai) } 57337f219c8SBruno Larsen (billionai) 574a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 57537f219c8SBruno Larsen (billionai) { 57637f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 57737f219c8SBruno Larsen (billionai) } 57837f219c8SBruno Larsen (billionai) 579a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 58037f219c8SBruno Larsen (billionai) { 58137f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 58237f219c8SBruno Larsen (billionai) } 58337f219c8SBruno Larsen (billionai) 58437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 585a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 58637f219c8SBruno Larsen (billionai) { 587f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58837f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 58937f219c8SBruno Larsen (billionai) } 59037f219c8SBruno Larsen (billionai) 591a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 59237f219c8SBruno Larsen (billionai) { 593f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59437f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 59537f219c8SBruno Larsen (billionai) } 59637f219c8SBruno Larsen (billionai) 597a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 59837f219c8SBruno Larsen (billionai) { 59937f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 60037f219c8SBruno Larsen (billionai) } 60137f219c8SBruno Larsen (billionai) 602a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 60337f219c8SBruno Larsen (billionai) { 60437f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 60537f219c8SBruno Larsen (billionai) } 60637f219c8SBruno Larsen (billionai) 60737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 608a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 60937f219c8SBruno Larsen (billionai) { 610f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61137f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 61237f219c8SBruno Larsen (billionai) } 61337f219c8SBruno Larsen (billionai) 614a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 61537f219c8SBruno Larsen (billionai) { 616f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61737f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 61837f219c8SBruno Larsen (billionai) } 61937f219c8SBruno Larsen (billionai) 62037f219c8SBruno Larsen (billionai) /* HDECR */ 621a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 62237f219c8SBruno Larsen (billionai) { 623f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62437f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 62537f219c8SBruno Larsen (billionai) } 62637f219c8SBruno Larsen (billionai) 627a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 62837f219c8SBruno Larsen (billionai) { 629f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63037f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 63137f219c8SBruno Larsen (billionai) } 63237f219c8SBruno Larsen (billionai) 633a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 63437f219c8SBruno Larsen (billionai) { 635f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63637f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 63737f219c8SBruno Larsen (billionai) } 63837f219c8SBruno Larsen (billionai) 639a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 64037f219c8SBruno Larsen (billionai) { 641f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64237f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 64337f219c8SBruno Larsen (billionai) } 64437f219c8SBruno Larsen (billionai) 645a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 64637f219c8SBruno Larsen (billionai) { 647f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64837f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 64937f219c8SBruno Larsen (billionai) } 65037f219c8SBruno Larsen (billionai) 65137f219c8SBruno Larsen (billionai) #endif 65237f219c8SBruno Larsen (billionai) #endif 65337f219c8SBruno Larsen (billionai) 65437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 65537f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 65637f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 657a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 66237f219c8SBruno Larsen (billionai) } 66337f219c8SBruno Larsen (billionai) 664a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 66537f219c8SBruno Larsen (billionai) { 66637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66837f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 66937f219c8SBruno Larsen (billionai) } 67037f219c8SBruno Larsen (billionai) 671a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 67237f219c8SBruno Larsen (billionai) { 67337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 67437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 67537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67637f219c8SBruno Larsen (billionai) } 67737f219c8SBruno Larsen (billionai) 678a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 67937f219c8SBruno Larsen (billionai) { 68037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 68137f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 68237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 685a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 68637f219c8SBruno Larsen (billionai) { 68737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 68837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69037f219c8SBruno Larsen (billionai) } 69137f219c8SBruno Larsen (billionai) 692a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 69337f219c8SBruno Larsen (billionai) { 69437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 69537f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 69637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69737f219c8SBruno Larsen (billionai) } 69837f219c8SBruno Larsen (billionai) 69937f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 70037f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 701a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 70237f219c8SBruno Larsen (billionai) { 70337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70537f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) 708a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 70937f219c8SBruno Larsen (billionai) { 71037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 71137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 71237f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) 715a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 71637f219c8SBruno Larsen (billionai) { 71737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 71837f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) 722a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 72337f219c8SBruno Larsen (billionai) { 72437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 72537f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 729a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 73037f219c8SBruno Larsen (billionai) { 73137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 73237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73437f219c8SBruno Larsen (billionai) } 73537f219c8SBruno Larsen (billionai) 736a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 73737f219c8SBruno Larsen (billionai) { 73837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 73937f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 74037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74137f219c8SBruno Larsen (billionai) } 74237f219c8SBruno Larsen (billionai) 74337f219c8SBruno Larsen (billionai) /* SDR1 */ 744a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 74737f219c8SBruno Larsen (billionai) } 74837f219c8SBruno Larsen (billionai) 74937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 75037f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 75137f219c8SBruno Larsen (billionai) /* PIDR */ 752a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 75337f219c8SBruno Larsen (billionai) { 75437f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 75537f219c8SBruno Larsen (billionai) } 75637f219c8SBruno Larsen (billionai) 757a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 75837f219c8SBruno Larsen (billionai) { 75937f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 76037f219c8SBruno Larsen (billionai) } 76137f219c8SBruno Larsen (billionai) 762a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 76337f219c8SBruno Larsen (billionai) { 76437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 76537f219c8SBruno Larsen (billionai) } 76637f219c8SBruno Larsen (billionai) 767a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 76837f219c8SBruno Larsen (billionai) { 76937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 77037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 77137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 77237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 77337f219c8SBruno Larsen (billionai) } 774a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 77537f219c8SBruno Larsen (billionai) { 77637f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 77737f219c8SBruno Larsen (billionai) } 77837f219c8SBruno Larsen (billionai) 779a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 78037f219c8SBruno Larsen (billionai) { 78137f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 78237f219c8SBruno Larsen (billionai) } 78337f219c8SBruno Larsen (billionai) 78437f219c8SBruno Larsen (billionai) /* DPDES */ 785a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 78637f219c8SBruno Larsen (billionai) { 78737f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) #endif 79537f219c8SBruno Larsen (billionai) #endif 79637f219c8SBruno Larsen (billionai) 79737f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 79837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 799a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 80037f219c8SBruno Larsen (billionai) { 801f5b6daacSRichard Henderson gen_icount_io_start(ctx); 80237f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 80337f219c8SBruno Larsen (billionai) } 80437f219c8SBruno Larsen (billionai) 805a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 80637f219c8SBruno Larsen (billionai) { 807f5b6daacSRichard Henderson gen_icount_io_start(ctx); 80837f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 80937f219c8SBruno Larsen (billionai) } 81037f219c8SBruno Larsen (billionai) 811a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 81237f219c8SBruno Larsen (billionai) { 813f5b6daacSRichard Henderson gen_icount_io_start(ctx); 81437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 81537f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 81637f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 817d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 81837f219c8SBruno Larsen (billionai) } 81937f219c8SBruno Larsen (billionai) 820a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 82137f219c8SBruno Larsen (billionai) { 822f5b6daacSRichard Henderson gen_icount_io_start(ctx); 82337f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 82437f219c8SBruno Larsen (billionai) } 82537f219c8SBruno Larsen (billionai) 826cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 827cbd8f17dSCédric Le Goater { 828cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 829cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 830cbd8f17dSCédric Le Goater } 831cbd8f17dSCédric Le Goater 832cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 833cbd8f17dSCédric Le Goater { 834cbd8f17dSCédric Le Goater gen_icount_io_start(ctx); 835cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 836cbd8f17dSCédric Le Goater } 837cbd8f17dSCédric Le Goater 838dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 839dd69d140SCédric Le Goater { 840dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 841dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 84247822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 843dd69d140SCédric Le Goater tcg_temp_free(t0); 844dd69d140SCédric Le Goater } 845dd69d140SCédric Le Goater 846a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 84737f219c8SBruno Larsen (billionai) { 848f5b6daacSRichard Henderson gen_icount_io_start(ctx); 84937f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 85037f219c8SBruno Larsen (billionai) } 85137f219c8SBruno Larsen (billionai) 852a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 85337f219c8SBruno Larsen (billionai) { 854f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85537f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 85637f219c8SBruno Larsen (billionai) } 85737f219c8SBruno Larsen (billionai) #endif 85837f219c8SBruno Larsen (billionai) 859328c95fcSCédric Le Goater /* PIR */ 86037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 861a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 86237f219c8SBruno Larsen (billionai) { 86337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 86437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 86537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 86637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 86737f219c8SBruno Larsen (billionai) } 86837f219c8SBruno Larsen (billionai) #endif 86937f219c8SBruno Larsen (billionai) 87037f219c8SBruno Larsen (billionai) /* SPE specific registers */ 871a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 87237f219c8SBruno Larsen (billionai) { 87337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 87437f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 87537f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 87637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 87737f219c8SBruno Larsen (billionai) } 87837f219c8SBruno Larsen (billionai) 879a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 88037f219c8SBruno Larsen (billionai) { 88137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 88237f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 88337f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 88437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 88537f219c8SBruno Larsen (billionai) } 88637f219c8SBruno Larsen (billionai) 88737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 88837f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 889a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 89037f219c8SBruno Larsen (billionai) { 89137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 89237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 89337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 89437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 89537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 89637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 89737f219c8SBruno Larsen (billionai) } 89837f219c8SBruno Larsen (billionai) 899a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 90037f219c8SBruno Larsen (billionai) { 90137f219c8SBruno Larsen (billionai) int sprn_offs; 90237f219c8SBruno Larsen (billionai) 90337f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 90437f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 90537f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 90637f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 90737f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 90837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 90937f219c8SBruno Larsen (billionai) } else { 9108e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9118e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9128e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 91337f219c8SBruno Larsen (billionai) return; 91437f219c8SBruno Larsen (billionai) } 91537f219c8SBruno Larsen (billionai) 91637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 91737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 91837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 91937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 92037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 92137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 92237f219c8SBruno Larsen (billionai) } 92337f219c8SBruno Larsen (billionai) #endif 92437f219c8SBruno Larsen (billionai) 92537f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 92637f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 927a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 92837f219c8SBruno Larsen (billionai) { 92937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 93037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 93137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 93237f219c8SBruno Larsen (billionai) 93337f219c8SBruno Larsen (billionai) /* 93437f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 93537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 93637f219c8SBruno Larsen (billionai) */ 93737f219c8SBruno Larsen (billionai) 93837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 93937f219c8SBruno Larsen (billionai) if (ctx->pr) { 94037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 94137f219c8SBruno Larsen (billionai) } else { 94237f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 94337f219c8SBruno Larsen (billionai) } 94437f219c8SBruno Larsen (billionai) 94537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 94637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 94737f219c8SBruno Larsen (billionai) 94837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 94937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 95037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 95137f219c8SBruno Larsen (billionai) 95237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 95337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 95437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 95537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 95637f219c8SBruno Larsen (billionai) 95737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 95837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 95937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 96037f219c8SBruno Larsen (billionai) } 96137f219c8SBruno Larsen (billionai) 962a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 96337f219c8SBruno Larsen (billionai) { 96437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 96737f219c8SBruno Larsen (billionai) 96837f219c8SBruno Larsen (billionai) /* 96937f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 97037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 97137f219c8SBruno Larsen (billionai) */ 97237f219c8SBruno Larsen (billionai) 97337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 97437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 97537f219c8SBruno Larsen (billionai) 97637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 97737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 97837f219c8SBruno Larsen (billionai) 97937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 98037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 98137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 98237f219c8SBruno Larsen (billionai) 98337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 98437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 98537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 98637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 98737f219c8SBruno Larsen (billionai) 98837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 98937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 99037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 99137f219c8SBruno Larsen (billionai) } 99237f219c8SBruno Larsen (billionai) 993a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 99437f219c8SBruno Larsen (billionai) { 99537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 99637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 99737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 99837f219c8SBruno Larsen (billionai) 99937f219c8SBruno Larsen (billionai) /* 100037f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 100137f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 100237f219c8SBruno Larsen (billionai) */ 100337f219c8SBruno Larsen (billionai) 100437f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 100537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 100637f219c8SBruno Larsen (billionai) 100737f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 100837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 100937f219c8SBruno Larsen (billionai) 101037f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 101137f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 101237f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101337f219c8SBruno Larsen (billionai) 101437f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 101637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 101737f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 101837f219c8SBruno Larsen (billionai) 101937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102037f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 102137f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 102237f219c8SBruno Larsen (billionai) } 102337f219c8SBruno Larsen (billionai) #endif 102437f219c8SBruno Larsen (billionai) #endif 102537f219c8SBruno Larsen (billionai) 102637f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1027a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 102837f219c8SBruno Larsen (billionai) { 102937f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 103037f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 103137f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 103237f219c8SBruno Larsen (billionai) } 103337f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 103437f219c8SBruno Larsen (billionai) 103537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1036a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 103737f219c8SBruno Larsen (billionai) { 103837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103937f219c8SBruno Larsen (billionai) 104037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 104137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 104237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 104337f219c8SBruno Larsen (billionai) } 104437f219c8SBruno Larsen (billionai) 1045a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 104637f219c8SBruno Larsen (billionai) { 104737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 104837f219c8SBruno Larsen (billionai) 104937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 105037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 105137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105237f219c8SBruno Larsen (billionai) } 105337f219c8SBruno Larsen (billionai) 1054a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 105537f219c8SBruno Larsen (billionai) { 105637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 105737f219c8SBruno Larsen (billionai) 105837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 105937f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 106037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 106137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 106237f219c8SBruno Larsen (billionai) } 106337f219c8SBruno Larsen (billionai) 1064a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 106537f219c8SBruno Larsen (billionai) { 106637f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 106737f219c8SBruno Larsen (billionai) } 106837f219c8SBruno Larsen (billionai) 1069a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 107037f219c8SBruno Larsen (billionai) { 107137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 107237f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 107337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 107437f219c8SBruno Larsen (billionai) } 1075a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 107637f219c8SBruno Larsen (billionai) { 107737f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 107837f219c8SBruno Larsen (billionai) } 1079a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 108037f219c8SBruno Larsen (billionai) { 108137f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 108237f219c8SBruno Larsen (billionai) } 108337f219c8SBruno Larsen (billionai) 108437f219c8SBruno Larsen (billionai) #endif 108537f219c8SBruno Larsen (billionai) 108637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1087a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 108837f219c8SBruno Larsen (billionai) { 108937f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 109037f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 109137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 109237f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 109337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 109437f219c8SBruno Larsen (billionai) tcg_temp_free(val); 109537f219c8SBruno Larsen (billionai) } 109637f219c8SBruno Larsen (billionai) 1097a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 109837f219c8SBruno Larsen (billionai) { 109937f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 110037f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 110137f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 110237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 110337f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 110437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 110537f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 110637f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 110737f219c8SBruno Larsen (billionai) } 110837f219c8SBruno Larsen (billionai) 110937f219c8SBruno Larsen (billionai) #endif 111037f219c8SBruno Larsen (billionai) 111137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 111237f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 111337f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 111437f219c8SBruno Larsen (billionai) { 111537f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 111637f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 111737f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 111837f219c8SBruno Larsen (billionai) 111937f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 112037f219c8SBruno Larsen (billionai) 112137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 112237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 112337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 112437f219c8SBruno Larsen (billionai) } 112537f219c8SBruno Larsen (billionai) 112637f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 112737f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 112837f219c8SBruno Larsen (billionai) { 112937f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 113037f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 113137f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 113237f219c8SBruno Larsen (billionai) 113337f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 113437f219c8SBruno Larsen (billionai) 113537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 113637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 113737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 113837f219c8SBruno Larsen (billionai) } 113937f219c8SBruno Larsen (billionai) 1140a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 114137f219c8SBruno Larsen (billionai) { 114237f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 114337f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 114437f219c8SBruno Larsen (billionai) 114537f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 114637f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 114737f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 114837f219c8SBruno Larsen (billionai) 114937f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 115037f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 115137f219c8SBruno Larsen (billionai) } 115237f219c8SBruno Larsen (billionai) 1153a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 115437f219c8SBruno Larsen (billionai) { 115537f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 115637f219c8SBruno Larsen (billionai) 115737f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 115837f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 115937f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 116037f219c8SBruno Larsen (billionai) 116137f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 116237f219c8SBruno Larsen (billionai) } 116337f219c8SBruno Larsen (billionai) 116437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1165a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 116637f219c8SBruno Larsen (billionai) { 116737f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 116837f219c8SBruno Larsen (billionai) 116937f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 117037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 117137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 117237f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 117337f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 117437f219c8SBruno Larsen (billionai) } 117537f219c8SBruno Larsen (billionai) 1176a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 117737f219c8SBruno Larsen (billionai) { 117837f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 117937f219c8SBruno Larsen (billionai) } 118037f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 118137f219c8SBruno Larsen (billionai) 1182a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 118337f219c8SBruno Larsen (billionai) { 118437f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 118537f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 118637f219c8SBruno Larsen (billionai) } 118737f219c8SBruno Larsen (billionai) 1188a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 118937f219c8SBruno Larsen (billionai) { 119037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 119137f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 119237f219c8SBruno Larsen (billionai) } 119337f219c8SBruno Larsen (billionai) 1194a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 119537f219c8SBruno Larsen (billionai) { 119637f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 119737f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 119837f219c8SBruno Larsen (billionai) } 119937f219c8SBruno Larsen (billionai) 1200a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 120137f219c8SBruno Larsen (billionai) { 120237f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 120337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 120437f219c8SBruno Larsen (billionai) } 120537f219c8SBruno Larsen (billionai) 1206a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 120737f219c8SBruno Larsen (billionai) { 120837f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 120937f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 121037f219c8SBruno Larsen (billionai) } 121137f219c8SBruno Larsen (billionai) 1212a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 121337f219c8SBruno Larsen (billionai) { 121437f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 121537f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 121637f219c8SBruno Larsen (billionai) } 121737f219c8SBruno Larsen (billionai) 1218a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 121937f219c8SBruno Larsen (billionai) { 122037f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 122137f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122237f219c8SBruno Larsen (billionai) } 122337f219c8SBruno Larsen (billionai) 1224a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 122537f219c8SBruno Larsen (billionai) { 122637f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 122737f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 122837f219c8SBruno Larsen (billionai) } 122937f219c8SBruno Larsen (billionai) 1230a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 123137f219c8SBruno Larsen (billionai) { 123237f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123337f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 123437f219c8SBruno Larsen (billionai) } 123537f219c8SBruno Larsen (billionai) 1236a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 123737f219c8SBruno Larsen (billionai) { 123837f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 123937f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 124037f219c8SBruno Larsen (billionai) } 124137f219c8SBruno Larsen (billionai) #endif 124237f219c8SBruno Larsen (billionai) 1243fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1244fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1245fcf5ef2aSThomas Huth 1246fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1247fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1248fcf5ef2aSThomas Huth 1249fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1250fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1251fcf5ef2aSThomas Huth 1252fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1253fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1254fcf5ef2aSThomas Huth 1255fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1256fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1257fcf5ef2aSThomas Huth 1258fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1259fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1260fcf5ef2aSThomas Huth 1261fcf5ef2aSThomas Huth typedef struct opcode_t { 1262fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1263fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1264fcf5ef2aSThomas Huth unsigned char pad[4]; 1265fcf5ef2aSThomas Huth #endif 1266fcf5ef2aSThomas Huth opc_handler_t handler; 1267fcf5ef2aSThomas Huth const char *oname; 1268fcf5ef2aSThomas Huth } opcode_t; 1269fcf5ef2aSThomas Huth 12709f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 12719f0cf041SMatheus Ferst { 12729f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 12739f0cf041SMatheus Ferst } 12749f0cf041SMatheus Ferst 1275fcf5ef2aSThomas Huth /* Helpers for priv. check */ 12769f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1277fcf5ef2aSThomas Huth do { \ 12789f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1279fcf5ef2aSThomas Huth } while (0) 1280fcf5ef2aSThomas Huth 1281fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 12829f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 12839f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 12849f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1285fcf5ef2aSThomas Huth #else 12869f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1287fcf5ef2aSThomas Huth do { \ 1288fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 12899f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1290fcf5ef2aSThomas Huth } \ 1291fcf5ef2aSThomas Huth } while (0) 12929f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1293fcf5ef2aSThomas Huth do { \ 1294fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 12959f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1296fcf5ef2aSThomas Huth } \ 1297fcf5ef2aSThomas Huth } while (0) 12989f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1299fcf5ef2aSThomas Huth do { \ 1300fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13019f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1302fcf5ef2aSThomas Huth } \ 1303fcf5ef2aSThomas Huth } while (0) 1304fcf5ef2aSThomas Huth #endif 1305fcf5ef2aSThomas Huth 13069f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1307fcf5ef2aSThomas Huth 1308fcf5ef2aSThomas Huth /*****************************************************************************/ 1309fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1310fcf5ef2aSThomas Huth 1311fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1312fcf5ef2aSThomas Huth { \ 1313fcf5ef2aSThomas Huth .opc1 = op1, \ 1314fcf5ef2aSThomas Huth .opc2 = op2, \ 1315fcf5ef2aSThomas Huth .opc3 = op3, \ 1316fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1317fcf5ef2aSThomas Huth .handler = { \ 1318fcf5ef2aSThomas Huth .inval1 = invl, \ 1319fcf5ef2aSThomas Huth .type = _typ, \ 1320fcf5ef2aSThomas Huth .type2 = _typ2, \ 1321fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1322fcf5ef2aSThomas Huth }, \ 1323fcf5ef2aSThomas Huth .oname = stringify(name), \ 1324fcf5ef2aSThomas Huth } 1325fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1326fcf5ef2aSThomas Huth { \ 1327fcf5ef2aSThomas Huth .opc1 = op1, \ 1328fcf5ef2aSThomas Huth .opc2 = op2, \ 1329fcf5ef2aSThomas Huth .opc3 = op3, \ 1330fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1331fcf5ef2aSThomas Huth .handler = { \ 1332fcf5ef2aSThomas Huth .inval1 = invl1, \ 1333fcf5ef2aSThomas Huth .inval2 = invl2, \ 1334fcf5ef2aSThomas Huth .type = _typ, \ 1335fcf5ef2aSThomas Huth .type2 = _typ2, \ 1336fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1337fcf5ef2aSThomas Huth }, \ 1338fcf5ef2aSThomas Huth .oname = stringify(name), \ 1339fcf5ef2aSThomas Huth } 1340fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1341fcf5ef2aSThomas Huth { \ 1342fcf5ef2aSThomas Huth .opc1 = op1, \ 1343fcf5ef2aSThomas Huth .opc2 = op2, \ 1344fcf5ef2aSThomas Huth .opc3 = op3, \ 1345fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1346fcf5ef2aSThomas Huth .handler = { \ 1347fcf5ef2aSThomas Huth .inval1 = invl, \ 1348fcf5ef2aSThomas Huth .type = _typ, \ 1349fcf5ef2aSThomas Huth .type2 = _typ2, \ 1350fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1351fcf5ef2aSThomas Huth }, \ 1352fcf5ef2aSThomas Huth .oname = onam, \ 1353fcf5ef2aSThomas Huth } 1354fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1355fcf5ef2aSThomas Huth { \ 1356fcf5ef2aSThomas Huth .opc1 = op1, \ 1357fcf5ef2aSThomas Huth .opc2 = op2, \ 1358fcf5ef2aSThomas Huth .opc3 = op3, \ 1359fcf5ef2aSThomas Huth .opc4 = op4, \ 1360fcf5ef2aSThomas Huth .handler = { \ 1361fcf5ef2aSThomas Huth .inval1 = invl, \ 1362fcf5ef2aSThomas Huth .type = _typ, \ 1363fcf5ef2aSThomas Huth .type2 = _typ2, \ 1364fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1365fcf5ef2aSThomas Huth }, \ 1366fcf5ef2aSThomas Huth .oname = stringify(name), \ 1367fcf5ef2aSThomas Huth } 1368fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1369fcf5ef2aSThomas Huth { \ 1370fcf5ef2aSThomas Huth .opc1 = op1, \ 1371fcf5ef2aSThomas Huth .opc2 = op2, \ 1372fcf5ef2aSThomas Huth .opc3 = op3, \ 1373fcf5ef2aSThomas Huth .opc4 = op4, \ 1374fcf5ef2aSThomas Huth .handler = { \ 1375fcf5ef2aSThomas Huth .inval1 = invl, \ 1376fcf5ef2aSThomas Huth .type = _typ, \ 1377fcf5ef2aSThomas Huth .type2 = _typ2, \ 1378fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1379fcf5ef2aSThomas Huth }, \ 1380fcf5ef2aSThomas Huth .oname = onam, \ 1381fcf5ef2aSThomas Huth } 1382fcf5ef2aSThomas Huth 1383fcf5ef2aSThomas Huth /* Invalid instruction */ 1384fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1385fcf5ef2aSThomas Huth { 1386fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1387fcf5ef2aSThomas Huth } 1388fcf5ef2aSThomas Huth 1389fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1390fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1391fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1392fcf5ef2aSThomas Huth .type = PPC_NONE, 1393fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1394fcf5ef2aSThomas Huth .handler = gen_invalid, 1395fcf5ef2aSThomas Huth }; 1396fcf5ef2aSThomas Huth 1397fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1398fcf5ef2aSThomas Huth 1399fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1400fcf5ef2aSThomas Huth { 1401fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1402b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1403b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1404fcf5ef2aSThomas Huth 1405b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1406b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1407efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1408efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1409b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1410efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1411efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1412b62b3686Spbonzini@redhat.com 1413b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1414fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1415b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1416fcf5ef2aSThomas Huth 1417fcf5ef2aSThomas Huth tcg_temp_free(t0); 1418b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1419b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1420fcf5ef2aSThomas Huth } 1421fcf5ef2aSThomas Huth 1422fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1423fcf5ef2aSThomas Huth { 1424fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1425fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1426fcf5ef2aSThomas Huth tcg_temp_free(t0); 1427fcf5ef2aSThomas Huth } 1428fcf5ef2aSThomas Huth 1429fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1430fcf5ef2aSThomas Huth { 1431fcf5ef2aSThomas Huth TCGv t0, t1; 1432fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1433fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1434fcf5ef2aSThomas Huth if (s) { 1435fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1436fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1437fcf5ef2aSThomas Huth } else { 1438fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1439fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1440fcf5ef2aSThomas Huth } 1441fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1442fcf5ef2aSThomas Huth tcg_temp_free(t1); 1443fcf5ef2aSThomas Huth tcg_temp_free(t0); 1444fcf5ef2aSThomas Huth } 1445fcf5ef2aSThomas Huth 1446fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1447fcf5ef2aSThomas Huth { 1448fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1449fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1450fcf5ef2aSThomas Huth tcg_temp_free(t0); 1451fcf5ef2aSThomas Huth } 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1454fcf5ef2aSThomas Huth { 1455fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1456fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1457fcf5ef2aSThomas Huth } else { 1458fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1459fcf5ef2aSThomas Huth } 1460fcf5ef2aSThomas Huth } 1461fcf5ef2aSThomas Huth 1462fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1463fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1464fcf5ef2aSThomas Huth { 1465fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1466fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1467fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1468fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1469fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1470fcf5ef2aSThomas Huth 1471fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1472fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1473fcf5ef2aSThomas Huth 1474fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1475fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1476fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1477fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1478fcf5ef2aSThomas Huth 1479fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1480fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1481fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1482fcf5ef2aSThomas Huth 1483fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1484fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1485fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1486fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1487fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1488fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1489fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1490fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1491fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1492fcf5ef2aSThomas Huth } 1493efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1494fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1495fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1496fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1497fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1498fcf5ef2aSThomas Huth } 1499fcf5ef2aSThomas Huth 1500fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1501fcf5ef2aSThomas Huth /* cmpeqb */ 1502fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1503fcf5ef2aSThomas Huth { 1504fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1505fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1506fcf5ef2aSThomas Huth } 1507fcf5ef2aSThomas Huth #endif 1508fcf5ef2aSThomas Huth 1509fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1510fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1511fcf5ef2aSThomas Huth { 1512fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1513fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1514fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1515fcf5ef2aSThomas Huth TCGv zr; 1516fcf5ef2aSThomas Huth 1517fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1518fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1519fcf5ef2aSThomas Huth 1520fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1521fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1522fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1523fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1524fcf5ef2aSThomas Huth tcg_temp_free(zr); 1525fcf5ef2aSThomas Huth tcg_temp_free(t0); 1526fcf5ef2aSThomas Huth } 1527fcf5ef2aSThomas Huth 1528fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1529fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1530fcf5ef2aSThomas Huth { 1531fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1532fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1533fcf5ef2aSThomas Huth } 1534fcf5ef2aSThomas Huth 1535fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1536fcf5ef2aSThomas Huth 1537fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1538fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1539fcf5ef2aSThomas Huth { 1540fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1541fcf5ef2aSThomas Huth 1542fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1543fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1544fcf5ef2aSThomas Huth if (sub) { 1545fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1546fcf5ef2aSThomas Huth } else { 1547fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1548fcf5ef2aSThomas Huth } 1549fcf5ef2aSThomas Huth tcg_temp_free(t0); 1550fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1551dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1552dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1553dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1554fcf5ef2aSThomas Huth } 1555dc0ad844SNikunj A Dadhania } else { 1556dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1557dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1558dc0ad844SNikunj A Dadhania } 155938a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1560dc0ad844SNikunj A Dadhania } 1561fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1562fcf5ef2aSThomas Huth } 1563fcf5ef2aSThomas Huth 15646b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 15656b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 15664c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 15676b10d008SNikunj A Dadhania { 15686b10d008SNikunj A Dadhania TCGv t0; 15696b10d008SNikunj A Dadhania 15706b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 15716b10d008SNikunj A Dadhania return; 15726b10d008SNikunj A Dadhania } 15736b10d008SNikunj A Dadhania 15746b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 157533903d0aSNikunj A Dadhania if (sub) { 157633903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 157733903d0aSNikunj A Dadhania } else { 15786b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 157933903d0aSNikunj A Dadhania } 15806b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 15814c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 15826b10d008SNikunj A Dadhania tcg_temp_free(t0); 15836b10d008SNikunj A Dadhania } 15846b10d008SNikunj A Dadhania 1585fcf5ef2aSThomas Huth /* Common add function */ 1586fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 15874c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 15884c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1589fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1590fcf5ef2aSThomas Huth { 1591fcf5ef2aSThomas Huth TCGv t0 = ret; 1592fcf5ef2aSThomas Huth 1593fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1594fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1595fcf5ef2aSThomas Huth } 1596fcf5ef2aSThomas Huth 1597fcf5ef2aSThomas Huth if (compute_ca) { 1598fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1599efe843d8SDavid Gibson /* 1600efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1601efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1602efe843d8SDavid Gibson * produce the carry into bit 32. 1603efe843d8SDavid Gibson */ 1604fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1605fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1606fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1607fcf5ef2aSThomas Huth if (add_ca) { 16084c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1609fcf5ef2aSThomas Huth } 16104c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1611fcf5ef2aSThomas Huth tcg_temp_free(t1); 16124c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16136b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16144c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16156b10d008SNikunj A Dadhania } 1616fcf5ef2aSThomas Huth } else { 1617fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1618fcf5ef2aSThomas Huth if (add_ca) { 16194c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16204c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1621fcf5ef2aSThomas Huth } else { 16224c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1623fcf5ef2aSThomas Huth } 16244c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1625fcf5ef2aSThomas Huth tcg_temp_free(zero); 1626fcf5ef2aSThomas Huth } 1627fcf5ef2aSThomas Huth } else { 1628fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1629fcf5ef2aSThomas Huth if (add_ca) { 16304c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1631fcf5ef2aSThomas Huth } 1632fcf5ef2aSThomas Huth } 1633fcf5ef2aSThomas Huth 1634fcf5ef2aSThomas Huth if (compute_ov) { 1635fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1636fcf5ef2aSThomas Huth } 1637fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1638fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1639fcf5ef2aSThomas Huth } 1640fcf5ef2aSThomas Huth 164111f4e8f8SRichard Henderson if (t0 != ret) { 1642fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1643fcf5ef2aSThomas Huth tcg_temp_free(t0); 1644fcf5ef2aSThomas Huth } 1645fcf5ef2aSThomas Huth } 1646fcf5ef2aSThomas Huth /* Add functions with two operands */ 16474c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1648fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1649fcf5ef2aSThomas Huth { \ 1650fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1651fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16524c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1653fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1654fcf5ef2aSThomas Huth } 1655fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16564c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1657fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1658fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1659fcf5ef2aSThomas Huth { \ 1660fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1661fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1662fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 16634c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1664fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1665fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth 1668fcf5ef2aSThomas Huth /* add add. addo addo. */ 16694c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 16704c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1671fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 16724c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 16734c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1674fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 16754c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 16764c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1677fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 16784c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 16794c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 16804c5920afSSuraj Jitindar Singh /* addex */ 16814c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1682fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 16834c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 16844c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1685fcf5ef2aSThomas Huth /* addic addic.*/ 1686fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1687fcf5ef2aSThomas Huth { 1688fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1689fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 16904c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1691fcf5ef2aSThomas Huth tcg_temp_free(c); 1692fcf5ef2aSThomas Huth } 1693fcf5ef2aSThomas Huth 1694fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1695fcf5ef2aSThomas Huth { 1696fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1697fcf5ef2aSThomas Huth } 1698fcf5ef2aSThomas Huth 1699fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1700fcf5ef2aSThomas Huth { 1701fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1702fcf5ef2aSThomas Huth } 1703fcf5ef2aSThomas Huth 1704fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1705fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1706fcf5ef2aSThomas Huth { 1707fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1708fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1709fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1710fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1711fcf5ef2aSThomas Huth 1712fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1713fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1714fcf5ef2aSThomas Huth if (sign) { 1715fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1716fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1717fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1718fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1719fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1720fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1721fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1722fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1723fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1724fcf5ef2aSThomas Huth } else { 1725fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1726fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1727fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1728fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1729fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1730fcf5ef2aSThomas Huth } 1731fcf5ef2aSThomas Huth if (compute_ov) { 1732fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1733c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1734c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1735c44027ffSNikunj A Dadhania } 1736fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1737fcf5ef2aSThomas Huth } 1738fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1739fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1740fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1741fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1742fcf5ef2aSThomas Huth 1743efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1744fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1745fcf5ef2aSThomas Huth } 1746efe843d8SDavid Gibson } 1747fcf5ef2aSThomas Huth /* Div functions */ 1748fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1749fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1750fcf5ef2aSThomas Huth { \ 1751fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1752fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1753fcf5ef2aSThomas Huth sign, compute_ov); \ 1754fcf5ef2aSThomas Huth } 1755fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1756fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1757fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1758fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1759fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1760fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1761fcf5ef2aSThomas Huth 1762fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1763fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1764fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1765fcf5ef2aSThomas Huth { \ 1766fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1767fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1768fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1769fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1770fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1771fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1772fcf5ef2aSThomas Huth } \ 1773fcf5ef2aSThomas Huth } 1774fcf5ef2aSThomas Huth 1775fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1776fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1777fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1778fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1779fcf5ef2aSThomas Huth 1780fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1781fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1782fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1783fcf5ef2aSThomas Huth { 1784fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1785fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1786fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1787fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1788fcf5ef2aSThomas Huth 1789fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1790fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1791fcf5ef2aSThomas Huth if (sign) { 1792fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1793fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1794fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1795fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1796fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1797fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1798fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1799fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1800fcf5ef2aSThomas Huth } else { 1801fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1802fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1803fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1804fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1805fcf5ef2aSThomas Huth } 1806fcf5ef2aSThomas Huth if (compute_ov) { 1807fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1808c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1809c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1810c44027ffSNikunj A Dadhania } 1811fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1812fcf5ef2aSThomas Huth } 1813fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1814fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1815fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1816fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1817fcf5ef2aSThomas Huth 1818efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1819fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1820fcf5ef2aSThomas Huth } 1821efe843d8SDavid Gibson } 1822fcf5ef2aSThomas Huth 1823fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1824fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1825fcf5ef2aSThomas Huth { \ 1826fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1827fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1828fcf5ef2aSThomas Huth sign, compute_ov); \ 1829fcf5ef2aSThomas Huth } 1830c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1831fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1832fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1833c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1834fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1835fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1836fcf5ef2aSThomas Huth 1837fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1838fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1839fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1840fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1841fcf5ef2aSThomas Huth #endif 1842fcf5ef2aSThomas Huth 1843fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1844fcf5ef2aSThomas Huth TCGv arg2, int sign) 1845fcf5ef2aSThomas Huth { 1846fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1847fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1848fcf5ef2aSThomas Huth 1849fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1850fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1851fcf5ef2aSThomas Huth if (sign) { 1852fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1853fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1854fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1855fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1856fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1857fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1858fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1859fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1860fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1861fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1862fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1863fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1864fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1865fcf5ef2aSThomas Huth } else { 1866fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1867fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1868fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1869fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1870fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1871fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1872fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1873fcf5ef2aSThomas Huth } 1874fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1875fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1876fcf5ef2aSThomas Huth } 1877fcf5ef2aSThomas Huth 1878fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1879fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1880fcf5ef2aSThomas Huth { \ 1881fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1882fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1883fcf5ef2aSThomas Huth sign); \ 1884fcf5ef2aSThomas Huth } 1885fcf5ef2aSThomas Huth 1886fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1887fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1888fcf5ef2aSThomas Huth 1889fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1890fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1891fcf5ef2aSThomas Huth TCGv arg2, int sign) 1892fcf5ef2aSThomas Huth { 1893fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1894fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1895fcf5ef2aSThomas Huth 1896fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1897fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1898fcf5ef2aSThomas Huth if (sign) { 1899fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1900fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1901fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1902fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1903fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1904fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1905fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1906fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1907fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1908fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1909fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1910fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1911fcf5ef2aSThomas Huth } else { 1912fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1913fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1914fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1915fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1916fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1917fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1918fcf5ef2aSThomas Huth } 1919fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1920fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1921fcf5ef2aSThomas Huth } 1922fcf5ef2aSThomas Huth 1923fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1924fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1925fcf5ef2aSThomas Huth { \ 1926fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1927fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1928fcf5ef2aSThomas Huth sign); \ 1929fcf5ef2aSThomas Huth } 1930fcf5ef2aSThomas Huth 1931fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1932fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1933fcf5ef2aSThomas Huth #endif 1934fcf5ef2aSThomas Huth 1935fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1936fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1937fcf5ef2aSThomas Huth { 1938fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1939fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1940fcf5ef2aSThomas Huth 1941fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1942fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1943fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1944fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1945fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1946fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1947efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1948fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1949fcf5ef2aSThomas Huth } 1950efe843d8SDavid Gibson } 1951fcf5ef2aSThomas Huth 1952fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1953fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1954fcf5ef2aSThomas Huth { 1955fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1956fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1957fcf5ef2aSThomas Huth 1958fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1959fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1960fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1961fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1962fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1963fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1964efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1965fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1966fcf5ef2aSThomas Huth } 1967efe843d8SDavid Gibson } 1968fcf5ef2aSThomas Huth 1969fcf5ef2aSThomas Huth /* mullw mullw. */ 1970fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1971fcf5ef2aSThomas Huth { 1972fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1973fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1974fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1975fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1976fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1977fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1978fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1979fcf5ef2aSThomas Huth tcg_temp_free(t0); 1980fcf5ef2aSThomas Huth tcg_temp_free(t1); 1981fcf5ef2aSThomas Huth #else 1982fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1983fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1984fcf5ef2aSThomas Huth #endif 1985efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1986fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1987fcf5ef2aSThomas Huth } 1988efe843d8SDavid Gibson } 1989fcf5ef2aSThomas Huth 1990fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1991fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1992fcf5ef2aSThomas Huth { 1993fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1994fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1995fcf5ef2aSThomas Huth 1996fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1997fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1998fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1999fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2000fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2001fcf5ef2aSThomas Huth #else 2002fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2003fcf5ef2aSThomas Huth #endif 2004fcf5ef2aSThomas Huth 2005fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2006fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2007fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 200861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 200961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 201061aa9a69SNikunj A Dadhania } 2011fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2012fcf5ef2aSThomas Huth 2013fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2014fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2015efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2016fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2017fcf5ef2aSThomas Huth } 2018efe843d8SDavid Gibson } 2019fcf5ef2aSThomas Huth 2020fcf5ef2aSThomas Huth /* mulli */ 2021fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2022fcf5ef2aSThomas Huth { 2023fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2024fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2025fcf5ef2aSThomas Huth } 2026fcf5ef2aSThomas Huth 2027fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2028fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2029fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2030fcf5ef2aSThomas Huth { 2031fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2032fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2033fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2034fcf5ef2aSThomas Huth tcg_temp_free(lo); 2035fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2036fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2037fcf5ef2aSThomas Huth } 2038fcf5ef2aSThomas Huth } 2039fcf5ef2aSThomas Huth 2040fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2041fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2042fcf5ef2aSThomas Huth { 2043fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2044fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2045fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2046fcf5ef2aSThomas Huth tcg_temp_free(lo); 2047fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2048fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2049fcf5ef2aSThomas Huth } 2050fcf5ef2aSThomas Huth } 2051fcf5ef2aSThomas Huth 2052fcf5ef2aSThomas Huth /* mulld mulld. */ 2053fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2054fcf5ef2aSThomas Huth { 2055fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2056fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2057efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2058fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2059fcf5ef2aSThomas Huth } 2060efe843d8SDavid Gibson } 2061fcf5ef2aSThomas Huth 2062fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2063fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2064fcf5ef2aSThomas Huth { 2065fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2066fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2067fcf5ef2aSThomas Huth 2068fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2069fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2070fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2071fcf5ef2aSThomas Huth 2072fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2073fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 207461aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 207561aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 207661aa9a69SNikunj A Dadhania } 2077fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2078fcf5ef2aSThomas Huth 2079fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2080fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2081fcf5ef2aSThomas Huth 2082fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2083fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2084fcf5ef2aSThomas Huth } 2085fcf5ef2aSThomas Huth } 2086fcf5ef2aSThomas Huth #endif 2087fcf5ef2aSThomas Huth 2088fcf5ef2aSThomas Huth /* Common subf function */ 2089fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2090fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2091fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2092fcf5ef2aSThomas Huth { 2093fcf5ef2aSThomas Huth TCGv t0 = ret; 2094fcf5ef2aSThomas Huth 2095fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2096fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2097fcf5ef2aSThomas Huth } 2098fcf5ef2aSThomas Huth 2099fcf5ef2aSThomas Huth if (compute_ca) { 2100fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2101fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2102efe843d8SDavid Gibson /* 2103efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2104efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2105efe843d8SDavid Gibson * produce the carry into bit 32. 2106efe843d8SDavid Gibson */ 2107fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2108fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2109fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2110fcf5ef2aSThomas Huth if (add_ca) { 2111fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2112fcf5ef2aSThomas Huth } else { 2113fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2114fcf5ef2aSThomas Huth } 2115fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2116fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2117fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2118fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2119fcf5ef2aSThomas Huth tcg_temp_free(t1); 2120e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 212133903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 212233903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 212333903d0aSNikunj A Dadhania } 2124fcf5ef2aSThomas Huth } else if (add_ca) { 2125fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2126fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2127fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2128fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2129fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21304c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2131fcf5ef2aSThomas Huth tcg_temp_free(zero); 2132fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2133fcf5ef2aSThomas Huth } else { 2134fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2135fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21364c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2137fcf5ef2aSThomas Huth } 2138fcf5ef2aSThomas Huth } else if (add_ca) { 2139efe843d8SDavid Gibson /* 2140efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2141efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2142efe843d8SDavid Gibson */ 2143fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2144fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2145fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2146fcf5ef2aSThomas Huth } else { 2147fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2148fcf5ef2aSThomas Huth } 2149fcf5ef2aSThomas Huth 2150fcf5ef2aSThomas Huth if (compute_ov) { 2151fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2152fcf5ef2aSThomas Huth } 2153fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2154fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2155fcf5ef2aSThomas Huth } 2156fcf5ef2aSThomas Huth 215711f4e8f8SRichard Henderson if (t0 != ret) { 2158fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2159fcf5ef2aSThomas Huth tcg_temp_free(t0); 2160fcf5ef2aSThomas Huth } 2161fcf5ef2aSThomas Huth } 2162fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2163fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2164fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2165fcf5ef2aSThomas Huth { \ 2166fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2167fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2168fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2169fcf5ef2aSThomas Huth } 2170fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2171fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2172fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2173fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2174fcf5ef2aSThomas Huth { \ 2175fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2176fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2177fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2178fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2179fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2180fcf5ef2aSThomas Huth } 2181fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2182fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2183fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2184fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2185fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2186fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2187fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2188fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2189fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2190fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2191fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2192fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2193fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2194fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2195fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2196fcf5ef2aSThomas Huth 2197fcf5ef2aSThomas Huth /* subfic */ 2198fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2199fcf5ef2aSThomas Huth { 2200fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2201fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2202fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2203fcf5ef2aSThomas Huth tcg_temp_free(c); 2204fcf5ef2aSThomas Huth } 2205fcf5ef2aSThomas Huth 2206fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2207fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2208fcf5ef2aSThomas Huth { 2209fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2210fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2211fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2212fcf5ef2aSThomas Huth tcg_temp_free(zero); 2213fcf5ef2aSThomas Huth } 2214fcf5ef2aSThomas Huth 2215fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2216fcf5ef2aSThomas Huth { 22171480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22181480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22191480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22201480d71cSNikunj A Dadhania } 2221fcf5ef2aSThomas Huth } 2222fcf5ef2aSThomas Huth 2223fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2224fcf5ef2aSThomas Huth { 2225fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2226fcf5ef2aSThomas Huth } 2227fcf5ef2aSThomas Huth 2228fcf5ef2aSThomas Huth /*** Integer logical ***/ 2229fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2230fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2231fcf5ef2aSThomas Huth { \ 2232fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2233fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2234fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2235fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2236fcf5ef2aSThomas Huth } 2237fcf5ef2aSThomas Huth 2238fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2239fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2240fcf5ef2aSThomas Huth { \ 2241fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2242fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2243fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2244fcf5ef2aSThomas Huth } 2245fcf5ef2aSThomas Huth 2246fcf5ef2aSThomas Huth /* and & and. */ 2247fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2248fcf5ef2aSThomas Huth /* andc & andc. */ 2249fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2250fcf5ef2aSThomas Huth 2251fcf5ef2aSThomas Huth /* andi. */ 2252fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2253fcf5ef2aSThomas Huth { 2254efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2255efe843d8SDavid Gibson UIMM(ctx->opcode)); 2256fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2257fcf5ef2aSThomas Huth } 2258fcf5ef2aSThomas Huth 2259fcf5ef2aSThomas Huth /* andis. */ 2260fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2261fcf5ef2aSThomas Huth { 2262efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2263efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2264fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2265fcf5ef2aSThomas Huth } 2266fcf5ef2aSThomas Huth 2267fcf5ef2aSThomas Huth /* cntlzw */ 2268fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2269fcf5ef2aSThomas Huth { 22709b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22719b8514e5SRichard Henderson 22729b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22739b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22749b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22759b8514e5SRichard Henderson tcg_temp_free_i32(t); 22769b8514e5SRichard Henderson 2277efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2278fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2279fcf5ef2aSThomas Huth } 2280efe843d8SDavid Gibson } 2281fcf5ef2aSThomas Huth 2282fcf5ef2aSThomas Huth /* cnttzw */ 2283fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2284fcf5ef2aSThomas Huth { 22859b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22869b8514e5SRichard Henderson 22879b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22889b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22899b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22909b8514e5SRichard Henderson tcg_temp_free_i32(t); 22919b8514e5SRichard Henderson 2292fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2293fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2294fcf5ef2aSThomas Huth } 2295fcf5ef2aSThomas Huth } 2296fcf5ef2aSThomas Huth 2297fcf5ef2aSThomas Huth /* eqv & eqv. */ 2298fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2299fcf5ef2aSThomas Huth /* extsb & extsb. */ 2300fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2301fcf5ef2aSThomas Huth /* extsh & extsh. */ 2302fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2303fcf5ef2aSThomas Huth /* nand & nand. */ 2304fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2305fcf5ef2aSThomas Huth /* nor & nor. */ 2306fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2307fcf5ef2aSThomas Huth 2308fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2309fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2310fcf5ef2aSThomas Huth { 2311fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2312fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2313fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2314fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2315fcf5ef2aSThomas Huth 2316fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2317b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2318fcf5ef2aSThomas Huth } 2319fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2320fcf5ef2aSThomas Huth 2321fcf5ef2aSThomas Huth /* or & or. */ 2322fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2323fcf5ef2aSThomas Huth { 2324fcf5ef2aSThomas Huth int rs, ra, rb; 2325fcf5ef2aSThomas Huth 2326fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2327fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2328fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2329fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2330fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2331efe843d8SDavid Gibson if (rs != rb) { 2332fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2333efe843d8SDavid Gibson } else { 2334fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2335efe843d8SDavid Gibson } 2336efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2337fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2338efe843d8SDavid Gibson } 2339fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2340fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2341fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2342fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2343fcf5ef2aSThomas Huth int prio = 0; 2344fcf5ef2aSThomas Huth 2345fcf5ef2aSThomas Huth switch (rs) { 2346fcf5ef2aSThomas Huth case 1: 2347fcf5ef2aSThomas Huth /* Set process priority to low */ 2348fcf5ef2aSThomas Huth prio = 2; 2349fcf5ef2aSThomas Huth break; 2350fcf5ef2aSThomas Huth case 6: 2351fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2352fcf5ef2aSThomas Huth prio = 3; 2353fcf5ef2aSThomas Huth break; 2354fcf5ef2aSThomas Huth case 2: 2355fcf5ef2aSThomas Huth /* Set process priority to normal */ 2356fcf5ef2aSThomas Huth prio = 4; 2357fcf5ef2aSThomas Huth break; 2358fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2359fcf5ef2aSThomas Huth case 31: 2360fcf5ef2aSThomas Huth if (!ctx->pr) { 2361fcf5ef2aSThomas Huth /* Set process priority to very low */ 2362fcf5ef2aSThomas Huth prio = 1; 2363fcf5ef2aSThomas Huth } 2364fcf5ef2aSThomas Huth break; 2365fcf5ef2aSThomas Huth case 5: 2366fcf5ef2aSThomas Huth if (!ctx->pr) { 2367fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2368fcf5ef2aSThomas Huth prio = 5; 2369fcf5ef2aSThomas Huth } 2370fcf5ef2aSThomas Huth break; 2371fcf5ef2aSThomas Huth case 3: 2372fcf5ef2aSThomas Huth if (!ctx->pr) { 2373fcf5ef2aSThomas Huth /* Set process priority to high */ 2374fcf5ef2aSThomas Huth prio = 6; 2375fcf5ef2aSThomas Huth } 2376fcf5ef2aSThomas Huth break; 2377fcf5ef2aSThomas Huth case 7: 2378fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2379fcf5ef2aSThomas Huth /* Set process priority to very high */ 2380fcf5ef2aSThomas Huth prio = 7; 2381fcf5ef2aSThomas Huth } 2382fcf5ef2aSThomas Huth break; 2383fcf5ef2aSThomas Huth #endif 2384fcf5ef2aSThomas Huth default: 2385fcf5ef2aSThomas Huth break; 2386fcf5ef2aSThomas Huth } 2387fcf5ef2aSThomas Huth if (prio) { 2388fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2389fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2390fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2391fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2392fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2393fcf5ef2aSThomas Huth tcg_temp_free(t0); 2394fcf5ef2aSThomas Huth } 2395fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2396efe843d8SDavid Gibson /* 2397efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2398efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2399efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2400efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2401fcf5ef2aSThomas Huth */ 2402fcf5ef2aSThomas Huth gen_pause(ctx); 2403fcf5ef2aSThomas Huth #endif 2404fcf5ef2aSThomas Huth #endif 2405fcf5ef2aSThomas Huth } 2406fcf5ef2aSThomas Huth } 2407fcf5ef2aSThomas Huth /* orc & orc. */ 2408fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2409fcf5ef2aSThomas Huth 2410fcf5ef2aSThomas Huth /* xor & xor. */ 2411fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2412fcf5ef2aSThomas Huth { 2413fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2414efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2415efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2416efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2417efe843d8SDavid Gibson } else { 2418fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2419efe843d8SDavid Gibson } 2420efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2421fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2422fcf5ef2aSThomas Huth } 2423efe843d8SDavid Gibson } 2424fcf5ef2aSThomas Huth 2425fcf5ef2aSThomas Huth /* ori */ 2426fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2427fcf5ef2aSThomas Huth { 2428fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2429fcf5ef2aSThomas Huth 2430fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2431fcf5ef2aSThomas Huth return; 2432fcf5ef2aSThomas Huth } 2433fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2434fcf5ef2aSThomas Huth } 2435fcf5ef2aSThomas Huth 2436fcf5ef2aSThomas Huth /* oris */ 2437fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2438fcf5ef2aSThomas Huth { 2439fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2440fcf5ef2aSThomas Huth 2441fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2442fcf5ef2aSThomas Huth /* NOP */ 2443fcf5ef2aSThomas Huth return; 2444fcf5ef2aSThomas Huth } 2445efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2446efe843d8SDavid Gibson uimm << 16); 2447fcf5ef2aSThomas Huth } 2448fcf5ef2aSThomas Huth 2449fcf5ef2aSThomas Huth /* xori */ 2450fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2451fcf5ef2aSThomas Huth { 2452fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2453fcf5ef2aSThomas Huth 2454fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2455fcf5ef2aSThomas Huth /* NOP */ 2456fcf5ef2aSThomas Huth return; 2457fcf5ef2aSThomas Huth } 2458fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2459fcf5ef2aSThomas Huth } 2460fcf5ef2aSThomas Huth 2461fcf5ef2aSThomas Huth /* xoris */ 2462fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2463fcf5ef2aSThomas Huth { 2464fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2465fcf5ef2aSThomas Huth 2466fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2467fcf5ef2aSThomas Huth /* NOP */ 2468fcf5ef2aSThomas Huth return; 2469fcf5ef2aSThomas Huth } 2470efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2471efe843d8SDavid Gibson uimm << 16); 2472fcf5ef2aSThomas Huth } 2473fcf5ef2aSThomas Huth 2474fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2475fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2476fcf5ef2aSThomas Huth { 2477fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2478fcf5ef2aSThomas Huth } 2479fcf5ef2aSThomas Huth 2480fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2481fcf5ef2aSThomas Huth { 248279770002SRichard Henderson #if defined(TARGET_PPC64) 2483fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 248479770002SRichard Henderson #else 248579770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 248679770002SRichard Henderson #endif 2487fcf5ef2aSThomas Huth } 2488fcf5ef2aSThomas Huth 2489fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2490fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2491fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2492fcf5ef2aSThomas Huth { 249379770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2494fcf5ef2aSThomas Huth } 2495fcf5ef2aSThomas Huth #endif 2496fcf5ef2aSThomas Huth 2497fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2498fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2499fcf5ef2aSThomas Huth { 2500fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2501fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2502fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2503fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2504fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2505fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2506fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2507fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2508fcf5ef2aSThomas Huth tcg_temp_free(t0); 2509fcf5ef2aSThomas Huth } 2510fcf5ef2aSThomas Huth 2511fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2512fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2513fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2514fcf5ef2aSThomas Huth { 2515fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2516fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2517fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2518fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2519fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2520fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2521fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2522fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2523fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2524fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2525fcf5ef2aSThomas Huth tcg_temp_free(t0); 2526fcf5ef2aSThomas Huth } 2527fcf5ef2aSThomas Huth #endif 2528fcf5ef2aSThomas Huth 2529fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2530fcf5ef2aSThomas Huth /* bpermd */ 2531fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2532fcf5ef2aSThomas Huth { 2533fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2534fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2535fcf5ef2aSThomas Huth } 2536fcf5ef2aSThomas Huth #endif 2537fcf5ef2aSThomas Huth 2538fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2539fcf5ef2aSThomas Huth /* extsw & extsw. */ 2540fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2541fcf5ef2aSThomas Huth 2542fcf5ef2aSThomas Huth /* cntlzd */ 2543fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2544fcf5ef2aSThomas Huth { 25459b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2546efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2547fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2548fcf5ef2aSThomas Huth } 2549efe843d8SDavid Gibson } 2550fcf5ef2aSThomas Huth 2551fcf5ef2aSThomas Huth /* cnttzd */ 2552fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2553fcf5ef2aSThomas Huth { 25549b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2555fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2556fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2557fcf5ef2aSThomas Huth } 2558fcf5ef2aSThomas Huth } 2559fcf5ef2aSThomas Huth 2560fcf5ef2aSThomas Huth /* darn */ 2561fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2562fcf5ef2aSThomas Huth { 2563fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2564fcf5ef2aSThomas Huth 25657e4357f6SRichard Henderson if (l > 2) { 25667e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25677e4357f6SRichard Henderson } else { 2568f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2569fcf5ef2aSThomas Huth if (l == 0) { 2570fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25717e4357f6SRichard Henderson } else { 2572fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2573fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25747e4357f6SRichard Henderson } 2575fcf5ef2aSThomas Huth } 2576fcf5ef2aSThomas Huth } 2577fcf5ef2aSThomas Huth #endif 2578fcf5ef2aSThomas Huth 2579fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2580fcf5ef2aSThomas Huth 2581fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2582fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2583fcf5ef2aSThomas Huth { 2584fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2585fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2586fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2587fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2588fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2589fcf5ef2aSThomas Huth 2590fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2591fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2592fcf5ef2aSThomas Huth } else { 2593fcf5ef2aSThomas Huth target_ulong mask; 2594c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2595fcf5ef2aSThomas Huth TCGv t1; 2596fcf5ef2aSThomas Huth 2597fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2598fcf5ef2aSThomas Huth mb += 32; 2599fcf5ef2aSThomas Huth me += 32; 2600fcf5ef2aSThomas Huth #endif 2601fcf5ef2aSThomas Huth mask = MASK(mb, me); 2602fcf5ef2aSThomas Huth 2603c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2604c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2605c4f6a4a3SDaniele Buono mask_in_32b = false; 2606c4f6a4a3SDaniele Buono } 2607c4f6a4a3SDaniele Buono #endif 2608fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2609c4f6a4a3SDaniele Buono if (mask_in_32b) { 2610fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2611fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2612fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2613fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2614fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2615fcf5ef2aSThomas Huth } else { 2616fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2617fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2618fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2619fcf5ef2aSThomas Huth #else 2620fcf5ef2aSThomas Huth g_assert_not_reached(); 2621fcf5ef2aSThomas Huth #endif 2622fcf5ef2aSThomas Huth } 2623fcf5ef2aSThomas Huth 2624fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2625fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2626fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2627fcf5ef2aSThomas Huth tcg_temp_free(t1); 2628fcf5ef2aSThomas Huth } 2629fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2630fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2631fcf5ef2aSThomas Huth } 2632fcf5ef2aSThomas Huth } 2633fcf5ef2aSThomas Huth 2634fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2635fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2636fcf5ef2aSThomas Huth { 2637fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2638fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26397b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26407b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26417b4d326fSRichard Henderson int me = ME(ctx->opcode); 26427b4d326fSRichard Henderson int len = me - mb + 1; 26437b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2644fcf5ef2aSThomas Huth 26457b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26467b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26477b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26487b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2649fcf5ef2aSThomas Huth } else { 2650fcf5ef2aSThomas Huth target_ulong mask; 2651c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2652fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2653fcf5ef2aSThomas Huth mb += 32; 2654fcf5ef2aSThomas Huth me += 32; 2655fcf5ef2aSThomas Huth #endif 2656fcf5ef2aSThomas Huth mask = MASK(mb, me); 2657c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2658c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2659c4f6a4a3SDaniele Buono mask_in_32b = false; 2660c4f6a4a3SDaniele Buono } 2661c4f6a4a3SDaniele Buono #endif 2662c4f6a4a3SDaniele Buono if (mask_in_32b) { 26637b4d326fSRichard Henderson if (sh == 0) { 26647b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 266594f040aaSVitaly Chikunov } else { 2666fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2667fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2668fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2669fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2670fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2671fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 267294f040aaSVitaly Chikunov } 2673fcf5ef2aSThomas Huth } else { 2674fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2675fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2676fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2677fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2678fcf5ef2aSThomas Huth #else 2679fcf5ef2aSThomas Huth g_assert_not_reached(); 2680fcf5ef2aSThomas Huth #endif 2681fcf5ef2aSThomas Huth } 2682fcf5ef2aSThomas Huth } 2683fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2684fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2685fcf5ef2aSThomas Huth } 2686fcf5ef2aSThomas Huth } 2687fcf5ef2aSThomas Huth 2688fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2689fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2690fcf5ef2aSThomas Huth { 2691fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2692fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2693fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2694fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2695fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2696fcf5ef2aSThomas Huth target_ulong mask; 2697c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2698fcf5ef2aSThomas Huth 2699fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2700fcf5ef2aSThomas Huth mb += 32; 2701fcf5ef2aSThomas Huth me += 32; 2702fcf5ef2aSThomas Huth #endif 2703fcf5ef2aSThomas Huth mask = MASK(mb, me); 2704fcf5ef2aSThomas Huth 2705c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2706c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2707c4f6a4a3SDaniele Buono mask_in_32b = false; 2708c4f6a4a3SDaniele Buono } 2709c4f6a4a3SDaniele Buono #endif 2710c4f6a4a3SDaniele Buono if (mask_in_32b) { 2711fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2712fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2713fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2714fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2715fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2716fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2717fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2718fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2719fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2720fcf5ef2aSThomas Huth } else { 2721fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2722fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2723fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2724fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2725fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2726fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2727fcf5ef2aSThomas Huth #else 2728fcf5ef2aSThomas Huth g_assert_not_reached(); 2729fcf5ef2aSThomas Huth #endif 2730fcf5ef2aSThomas Huth } 2731fcf5ef2aSThomas Huth 2732fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2733fcf5ef2aSThomas Huth 2734fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2735fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2736fcf5ef2aSThomas Huth } 2737fcf5ef2aSThomas Huth } 2738fcf5ef2aSThomas Huth 2739fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2740fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2741fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2742fcf5ef2aSThomas Huth { \ 2743fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2744fcf5ef2aSThomas Huth } \ 2745fcf5ef2aSThomas Huth \ 2746fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2747fcf5ef2aSThomas Huth { \ 2748fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2749fcf5ef2aSThomas Huth } 2750fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2751fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2752fcf5ef2aSThomas Huth { \ 2753fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2754fcf5ef2aSThomas Huth } \ 2755fcf5ef2aSThomas Huth \ 2756fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2757fcf5ef2aSThomas Huth { \ 2758fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2759fcf5ef2aSThomas Huth } \ 2760fcf5ef2aSThomas Huth \ 2761fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2762fcf5ef2aSThomas Huth { \ 2763fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2764fcf5ef2aSThomas Huth } \ 2765fcf5ef2aSThomas Huth \ 2766fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2767fcf5ef2aSThomas Huth { \ 2768fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2769fcf5ef2aSThomas Huth } 2770fcf5ef2aSThomas Huth 2771fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2772fcf5ef2aSThomas Huth { 2773fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2774fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27757b4d326fSRichard Henderson int len = me - mb + 1; 27767b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2777fcf5ef2aSThomas Huth 27787b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27797b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27807b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27817b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2782fcf5ef2aSThomas Huth } else { 2783fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2784fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2785fcf5ef2aSThomas Huth } 2786fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2787fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2788fcf5ef2aSThomas Huth } 2789fcf5ef2aSThomas Huth } 2790fcf5ef2aSThomas Huth 2791fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2792fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2793fcf5ef2aSThomas Huth { 2794fcf5ef2aSThomas Huth uint32_t sh, mb; 2795fcf5ef2aSThomas Huth 2796fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2797fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2798fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2799fcf5ef2aSThomas Huth } 2800fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2801fcf5ef2aSThomas Huth 2802fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2803fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2804fcf5ef2aSThomas Huth { 2805fcf5ef2aSThomas Huth uint32_t sh, me; 2806fcf5ef2aSThomas Huth 2807fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2808fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2809fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2810fcf5ef2aSThomas Huth } 2811fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2812fcf5ef2aSThomas Huth 2813fcf5ef2aSThomas Huth /* rldic - rldic. */ 2814fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2815fcf5ef2aSThomas Huth { 2816fcf5ef2aSThomas Huth uint32_t sh, mb; 2817fcf5ef2aSThomas Huth 2818fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2819fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2820fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2821fcf5ef2aSThomas Huth } 2822fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2823fcf5ef2aSThomas Huth 2824fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2825fcf5ef2aSThomas Huth { 2826fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2827fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2828fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2829fcf5ef2aSThomas Huth TCGv t0; 2830fcf5ef2aSThomas Huth 2831fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2832fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2833fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2834fcf5ef2aSThomas Huth tcg_temp_free(t0); 2835fcf5ef2aSThomas Huth 2836fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2837fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2838fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2839fcf5ef2aSThomas Huth } 2840fcf5ef2aSThomas Huth } 2841fcf5ef2aSThomas Huth 2842fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2843fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2844fcf5ef2aSThomas Huth { 2845fcf5ef2aSThomas Huth uint32_t mb; 2846fcf5ef2aSThomas Huth 2847fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2848fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2851fcf5ef2aSThomas Huth 2852fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2853fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2854fcf5ef2aSThomas Huth { 2855fcf5ef2aSThomas Huth uint32_t me; 2856fcf5ef2aSThomas Huth 2857fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2858fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2859fcf5ef2aSThomas Huth } 2860fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2861fcf5ef2aSThomas Huth 2862fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2863fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2864fcf5ef2aSThomas Huth { 2865fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2866fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2867fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2868fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2869fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2870fcf5ef2aSThomas Huth 2871fcf5ef2aSThomas Huth if (mb <= me) { 2872fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2873fcf5ef2aSThomas Huth } else { 2874fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2875fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2876fcf5ef2aSThomas Huth 2877fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2878fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2879fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2880fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2881fcf5ef2aSThomas Huth tcg_temp_free(t1); 2882fcf5ef2aSThomas Huth } 2883fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2884fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2885fcf5ef2aSThomas Huth } 2886fcf5ef2aSThomas Huth } 2887fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2888fcf5ef2aSThomas Huth #endif 2889fcf5ef2aSThomas Huth 2890fcf5ef2aSThomas Huth /*** Integer shift ***/ 2891fcf5ef2aSThomas Huth 2892fcf5ef2aSThomas Huth /* slw & slw. */ 2893fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2894fcf5ef2aSThomas Huth { 2895fcf5ef2aSThomas Huth TCGv t0, t1; 2896fcf5ef2aSThomas Huth 2897fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2898fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2899fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2900fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2901fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2902fcf5ef2aSThomas Huth #else 2903fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2904fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2905fcf5ef2aSThomas Huth #endif 2906fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2907fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2908fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2909fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2910fcf5ef2aSThomas Huth tcg_temp_free(t1); 2911fcf5ef2aSThomas Huth tcg_temp_free(t0); 2912fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2913efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2914fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2915fcf5ef2aSThomas Huth } 2916efe843d8SDavid Gibson } 2917fcf5ef2aSThomas Huth 2918fcf5ef2aSThomas Huth /* sraw & sraw. */ 2919fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2920fcf5ef2aSThomas Huth { 2921fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2922fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2923efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2924fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2925fcf5ef2aSThomas Huth } 2926efe843d8SDavid Gibson } 2927fcf5ef2aSThomas Huth 2928fcf5ef2aSThomas Huth /* srawi & srawi. */ 2929fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2930fcf5ef2aSThomas Huth { 2931fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2932fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2933fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2934fcf5ef2aSThomas Huth if (sh == 0) { 2935fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2936fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2937af1c259fSSandipan Das if (is_isa300(ctx)) { 2938af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2939af1c259fSSandipan Das } 2940fcf5ef2aSThomas Huth } else { 2941fcf5ef2aSThomas Huth TCGv t0; 2942fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2943fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2944fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2945fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2946fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2947fcf5ef2aSThomas Huth tcg_temp_free(t0); 2948fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2949af1c259fSSandipan Das if (is_isa300(ctx)) { 2950af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2951af1c259fSSandipan Das } 2952fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2953fcf5ef2aSThomas Huth } 2954fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2955fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2956fcf5ef2aSThomas Huth } 2957fcf5ef2aSThomas Huth } 2958fcf5ef2aSThomas Huth 2959fcf5ef2aSThomas Huth /* srw & srw. */ 2960fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2961fcf5ef2aSThomas Huth { 2962fcf5ef2aSThomas Huth TCGv t0, t1; 2963fcf5ef2aSThomas Huth 2964fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2965fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2966fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2967fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2968fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2969fcf5ef2aSThomas Huth #else 2970fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2971fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2972fcf5ef2aSThomas Huth #endif 2973fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2974fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2975fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2976fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2977fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2978fcf5ef2aSThomas Huth tcg_temp_free(t1); 2979fcf5ef2aSThomas Huth tcg_temp_free(t0); 2980efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2981fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2982fcf5ef2aSThomas Huth } 2983efe843d8SDavid Gibson } 2984fcf5ef2aSThomas Huth 2985fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2986fcf5ef2aSThomas Huth /* sld & sld. */ 2987fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2988fcf5ef2aSThomas Huth { 2989fcf5ef2aSThomas Huth TCGv t0, t1; 2990fcf5ef2aSThomas Huth 2991fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2992fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2993fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2994fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2995fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2996fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2997fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2998fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2999fcf5ef2aSThomas Huth tcg_temp_free(t1); 3000fcf5ef2aSThomas Huth tcg_temp_free(t0); 3001efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3002fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3003fcf5ef2aSThomas Huth } 3004efe843d8SDavid Gibson } 3005fcf5ef2aSThomas Huth 3006fcf5ef2aSThomas Huth /* srad & srad. */ 3007fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3008fcf5ef2aSThomas Huth { 3009fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3010fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3011efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3012fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3013fcf5ef2aSThomas Huth } 3014efe843d8SDavid Gibson } 3015fcf5ef2aSThomas Huth /* sradi & sradi. */ 3016fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3017fcf5ef2aSThomas Huth { 3018fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3019fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3020fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3021fcf5ef2aSThomas Huth if (sh == 0) { 3022fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3023fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3024af1c259fSSandipan Das if (is_isa300(ctx)) { 3025af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3026af1c259fSSandipan Das } 3027fcf5ef2aSThomas Huth } else { 3028fcf5ef2aSThomas Huth TCGv t0; 3029fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3030fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3031fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3032fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3033fcf5ef2aSThomas Huth tcg_temp_free(t0); 3034fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3035af1c259fSSandipan Das if (is_isa300(ctx)) { 3036af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3037af1c259fSSandipan Das } 3038fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3039fcf5ef2aSThomas Huth } 3040fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3041fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3042fcf5ef2aSThomas Huth } 3043fcf5ef2aSThomas Huth } 3044fcf5ef2aSThomas Huth 3045fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3046fcf5ef2aSThomas Huth { 3047fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3048fcf5ef2aSThomas Huth } 3049fcf5ef2aSThomas Huth 3050fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3051fcf5ef2aSThomas Huth { 3052fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3053fcf5ef2aSThomas Huth } 3054fcf5ef2aSThomas Huth 3055fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3056fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3057fcf5ef2aSThomas Huth { 3058fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3059fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3060fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3061fcf5ef2aSThomas Huth 3062fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3063fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3064fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3065fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3066fcf5ef2aSThomas Huth } 3067fcf5ef2aSThomas Huth } 3068fcf5ef2aSThomas Huth 3069fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3070fcf5ef2aSThomas Huth { 3071fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3072fcf5ef2aSThomas Huth } 3073fcf5ef2aSThomas Huth 3074fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3075fcf5ef2aSThomas Huth { 3076fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3077fcf5ef2aSThomas Huth } 3078fcf5ef2aSThomas Huth 3079fcf5ef2aSThomas Huth /* srd & srd. */ 3080fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3081fcf5ef2aSThomas Huth { 3082fcf5ef2aSThomas Huth TCGv t0, t1; 3083fcf5ef2aSThomas Huth 3084fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3085fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3086fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3087fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3088fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3089fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3090fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3091fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3092fcf5ef2aSThomas Huth tcg_temp_free(t1); 3093fcf5ef2aSThomas Huth tcg_temp_free(t0); 3094efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3095fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3096fcf5ef2aSThomas Huth } 3097efe843d8SDavid Gibson } 3098fcf5ef2aSThomas Huth #endif 3099fcf5ef2aSThomas Huth 3100fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3101fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3102fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3103fcf5ef2aSThomas Huth target_long maskl) 3104fcf5ef2aSThomas Huth { 3105fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3106fcf5ef2aSThomas Huth 3107fcf5ef2aSThomas Huth simm &= ~maskl; 3108fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3109fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3110fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3111fcf5ef2aSThomas Huth } 3112fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3113fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3114fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3115fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3116fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3117fcf5ef2aSThomas Huth } 3118fcf5ef2aSThomas Huth } else { 3119fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3120fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3121fcf5ef2aSThomas Huth } else { 3122fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3123fcf5ef2aSThomas Huth } 3124fcf5ef2aSThomas Huth } 3125fcf5ef2aSThomas Huth } 3126fcf5ef2aSThomas Huth 3127fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3128fcf5ef2aSThomas Huth { 3129fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3130fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3131fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3132fcf5ef2aSThomas Huth } else { 3133fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3134fcf5ef2aSThomas Huth } 3135fcf5ef2aSThomas Huth } else { 3136fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3137fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3138fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3139fcf5ef2aSThomas Huth } 3140fcf5ef2aSThomas Huth } 3141fcf5ef2aSThomas Huth } 3142fcf5ef2aSThomas Huth 3143fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3144fcf5ef2aSThomas Huth { 3145fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3146fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3147fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3148fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3149fcf5ef2aSThomas Huth } else { 3150fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3151fcf5ef2aSThomas Huth } 3152fcf5ef2aSThomas Huth } 3153fcf5ef2aSThomas Huth 3154fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3155fcf5ef2aSThomas Huth target_long val) 3156fcf5ef2aSThomas Huth { 3157fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3158fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3159fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3160fcf5ef2aSThomas Huth } 3161fcf5ef2aSThomas Huth } 3162fcf5ef2aSThomas Huth 3163fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3164fcf5ef2aSThomas Huth { 3165fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3166fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3167fcf5ef2aSThomas Huth } 3168fcf5ef2aSThomas Huth 3169eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3170eb63efd9SFernando Eckhardt Valle { 3171eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3172eb63efd9SFernando Eckhardt Valle if (ra) { 3173eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3174eb63efd9SFernando Eckhardt Valle } else { 3175eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3176eb63efd9SFernando Eckhardt Valle } 3177eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3178eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3179eb63efd9SFernando Eckhardt Valle } 3180eb63efd9SFernando Eckhardt Valle return ea; 3181eb63efd9SFernando Eckhardt Valle } 3182eb63efd9SFernando Eckhardt Valle 3183fcf5ef2aSThomas Huth /*** Integer load ***/ 3184fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3185fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3186fcf5ef2aSThomas Huth 3187fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3188fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3189fcf5ef2aSThomas Huth TCGv val, \ 3190fcf5ef2aSThomas Huth TCGv addr) \ 3191fcf5ef2aSThomas Huth { \ 3192fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3193fcf5ef2aSThomas Huth } 3194fcf5ef2aSThomas Huth 3195fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3196fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3197fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3198fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3199fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3200fcf5ef2aSThomas Huth 3201fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3202fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3203fcf5ef2aSThomas Huth 3204fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3205fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3206fcf5ef2aSThomas Huth TCGv_i64 val, \ 3207fcf5ef2aSThomas Huth TCGv addr) \ 3208fcf5ef2aSThomas Huth { \ 3209fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3210fcf5ef2aSThomas Huth } 3211fcf5ef2aSThomas Huth 3212fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3213fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3214fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3215fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3216fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3217fcf5ef2aSThomas Huth 3218fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3219fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3220fcf5ef2aSThomas Huth #endif 3221fcf5ef2aSThomas Huth 3222fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3223fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3224fcf5ef2aSThomas Huth TCGv val, \ 3225fcf5ef2aSThomas Huth TCGv addr) \ 3226fcf5ef2aSThomas Huth { \ 3227fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3228fcf5ef2aSThomas Huth } 3229fcf5ef2aSThomas Huth 3230e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3231fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3232e8f4c8d6SRichard Henderson #endif 3233fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3234fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3235fcf5ef2aSThomas Huth 3236fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3237fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3238fcf5ef2aSThomas Huth 3239fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3240fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3241fcf5ef2aSThomas Huth TCGv_i64 val, \ 3242fcf5ef2aSThomas Huth TCGv addr) \ 3243fcf5ef2aSThomas Huth { \ 3244fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3245fcf5ef2aSThomas Huth } 3246fcf5ef2aSThomas Huth 3247fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3248fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3249fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3250fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3251fcf5ef2aSThomas Huth 3252fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3253fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3254fcf5ef2aSThomas Huth #endif 3255fcf5ef2aSThomas Huth 3256fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3257fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3258fcf5ef2aSThomas Huth { \ 3259fcf5ef2aSThomas Huth TCGv EA; \ 32609f0cf041SMatheus Ferst chk(ctx); \ 3261fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3262fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3263fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3264fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3265fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3266fcf5ef2aSThomas Huth } 3267fcf5ef2aSThomas Huth 3268fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3269fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3270fcf5ef2aSThomas Huth 3271fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3272fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3273fcf5ef2aSThomas Huth 327450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 327550728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 327650728199SRoman Kapl { \ 327750728199SRoman Kapl TCGv EA; \ 32789f0cf041SMatheus Ferst CHK_SV(ctx); \ 327950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 328050728199SRoman Kapl EA = tcg_temp_new(); \ 328150728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 328250728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 328350728199SRoman Kapl tcg_temp_free(EA); \ 328450728199SRoman Kapl } 328550728199SRoman Kapl 328650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 328750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 328850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 328950728199SRoman Kapl #if defined(TARGET_PPC64) 3290fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 329150728199SRoman Kapl #endif 329250728199SRoman Kapl 3293fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3294fcf5ef2aSThomas Huth /* CI load/store variants */ 3295fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3296fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3297fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3298fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3299fcf5ef2aSThomas Huth #endif 3300fcf5ef2aSThomas Huth 3301fcf5ef2aSThomas Huth /*** Integer store ***/ 3302fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3303fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3304fcf5ef2aSThomas Huth { \ 3305fcf5ef2aSThomas Huth TCGv EA; \ 33069f0cf041SMatheus Ferst chk(ctx); \ 3307fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3308fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3309fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3310fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3311fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3312fcf5ef2aSThomas Huth } 3313fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3314fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3315fcf5ef2aSThomas Huth 3316fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3317fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3318fcf5ef2aSThomas Huth 331950728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 332050728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 332150728199SRoman Kapl { \ 332250728199SRoman Kapl TCGv EA; \ 33239f0cf041SMatheus Ferst CHK_SV(ctx); \ 332450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 332550728199SRoman Kapl EA = tcg_temp_new(); \ 332650728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 332750728199SRoman Kapl tcg_gen_qemu_st_tl( \ 332850728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 332950728199SRoman Kapl tcg_temp_free(EA); \ 333050728199SRoman Kapl } 333150728199SRoman Kapl 333250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 333350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 333450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 333550728199SRoman Kapl #if defined(TARGET_PPC64) 3336fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 333750728199SRoman Kapl #endif 333850728199SRoman Kapl 3339fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3340fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3341fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3342fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3343fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3344fcf5ef2aSThomas Huth #endif 3345fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3346fcf5ef2aSThomas Huth 3347fcf5ef2aSThomas Huth /* lhbrx */ 3348fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3349fcf5ef2aSThomas Huth 3350fcf5ef2aSThomas Huth /* lwbrx */ 3351fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3352fcf5ef2aSThomas Huth 3353fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3354fcf5ef2aSThomas Huth /* ldbrx */ 3355fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3356fcf5ef2aSThomas Huth /* stdbrx */ 3357fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3358fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3359fcf5ef2aSThomas Huth 3360fcf5ef2aSThomas Huth /* sthbrx */ 3361fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3362fcf5ef2aSThomas Huth /* stwbrx */ 3363fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3364fcf5ef2aSThomas Huth 3365fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3366fcf5ef2aSThomas Huth 3367fcf5ef2aSThomas Huth /* lmw */ 3368fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3369fcf5ef2aSThomas Huth { 3370fcf5ef2aSThomas Huth TCGv t0; 3371fcf5ef2aSThomas Huth TCGv_i32 t1; 3372fcf5ef2aSThomas Huth 3373fcf5ef2aSThomas Huth if (ctx->le_mode) { 3374fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3375fcf5ef2aSThomas Huth return; 3376fcf5ef2aSThomas Huth } 3377fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3378fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3379fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3380fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3381fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3382fcf5ef2aSThomas Huth tcg_temp_free(t0); 3383fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3384fcf5ef2aSThomas Huth } 3385fcf5ef2aSThomas Huth 3386fcf5ef2aSThomas Huth /* stmw */ 3387fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3388fcf5ef2aSThomas Huth { 3389fcf5ef2aSThomas Huth TCGv t0; 3390fcf5ef2aSThomas Huth TCGv_i32 t1; 3391fcf5ef2aSThomas Huth 3392fcf5ef2aSThomas Huth if (ctx->le_mode) { 3393fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3394fcf5ef2aSThomas Huth return; 3395fcf5ef2aSThomas Huth } 3396fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3397fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3398fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3399fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3400fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3401fcf5ef2aSThomas Huth tcg_temp_free(t0); 3402fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3403fcf5ef2aSThomas Huth } 3404fcf5ef2aSThomas Huth 3405fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3406fcf5ef2aSThomas Huth 3407fcf5ef2aSThomas Huth /* lswi */ 3408efe843d8SDavid Gibson /* 3409efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3410efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3411efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3412efe843d8SDavid Gibson * spec... 3413fcf5ef2aSThomas Huth */ 3414fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3415fcf5ef2aSThomas Huth { 3416fcf5ef2aSThomas Huth TCGv t0; 3417fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3418fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3419fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3420fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3421fcf5ef2aSThomas Huth int nr; 3422fcf5ef2aSThomas Huth 3423fcf5ef2aSThomas Huth if (ctx->le_mode) { 3424fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3425fcf5ef2aSThomas Huth return; 3426fcf5ef2aSThomas Huth } 3427efe843d8SDavid Gibson if (nb == 0) { 3428fcf5ef2aSThomas Huth nb = 32; 3429efe843d8SDavid Gibson } 3430f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3431fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3432fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3433fcf5ef2aSThomas Huth return; 3434fcf5ef2aSThomas Huth } 3435fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3436fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3437fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3438fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3439fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3440fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3441fcf5ef2aSThomas Huth tcg_temp_free(t0); 3442fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3443fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3444fcf5ef2aSThomas Huth } 3445fcf5ef2aSThomas Huth 3446fcf5ef2aSThomas Huth /* lswx */ 3447fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3448fcf5ef2aSThomas Huth { 3449fcf5ef2aSThomas Huth TCGv t0; 3450fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3451fcf5ef2aSThomas Huth 3452fcf5ef2aSThomas Huth if (ctx->le_mode) { 3453fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3454fcf5ef2aSThomas Huth return; 3455fcf5ef2aSThomas Huth } 3456fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3457fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3458fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3459fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3460fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3461fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3462fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3463fcf5ef2aSThomas Huth tcg_temp_free(t0); 3464fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3465fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3466fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3467fcf5ef2aSThomas Huth } 3468fcf5ef2aSThomas Huth 3469fcf5ef2aSThomas Huth /* stswi */ 3470fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3471fcf5ef2aSThomas Huth { 3472fcf5ef2aSThomas Huth TCGv t0; 3473fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3474fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3475fcf5ef2aSThomas Huth 3476fcf5ef2aSThomas Huth if (ctx->le_mode) { 3477fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3478fcf5ef2aSThomas Huth return; 3479fcf5ef2aSThomas Huth } 3480fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3481fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3482fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3483efe843d8SDavid Gibson if (nb == 0) { 3484fcf5ef2aSThomas Huth nb = 32; 3485efe843d8SDavid Gibson } 3486fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3487fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3488fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3489fcf5ef2aSThomas Huth tcg_temp_free(t0); 3490fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3491fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3492fcf5ef2aSThomas Huth } 3493fcf5ef2aSThomas Huth 3494fcf5ef2aSThomas Huth /* stswx */ 3495fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3496fcf5ef2aSThomas Huth { 3497fcf5ef2aSThomas Huth TCGv t0; 3498fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3499fcf5ef2aSThomas Huth 3500fcf5ef2aSThomas Huth if (ctx->le_mode) { 3501fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3502fcf5ef2aSThomas Huth return; 3503fcf5ef2aSThomas Huth } 3504fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3505fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3506fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3507fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3508fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3509fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3510fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3511fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3512fcf5ef2aSThomas Huth tcg_temp_free(t0); 3513fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3514fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3515fcf5ef2aSThomas Huth } 3516fcf5ef2aSThomas Huth 3517fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3518fcf5ef2aSThomas Huth /* eieio */ 3519fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3520fcf5ef2aSThomas Huth { 3521fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3522fcb830afSNicholas Piggin 3523fcb830afSNicholas Piggin /* 3524fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3525fcb830afSNicholas Piggin * operations in the set: 3526fcb830afSNicholas Piggin * - loads from CI memory. 3527fcb830afSNicholas Piggin * - stores to CI memory. 3528fcb830afSNicholas Piggin * - stores to WT memory. 3529fcb830afSNicholas Piggin * 3530fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3531fcb830afSNicholas Piggin * - stores to cacheble memory. 3532fcb830afSNicholas Piggin * 3533fcb830afSNicholas Piggin * It also serializes instructions: 3534fcb830afSNicholas Piggin * - dcbt and dcbst. 3535fcb830afSNicholas Piggin * 3536fcb830afSNicholas Piggin * It separately serializes: 3537fcb830afSNicholas Piggin * - tlbie and tlbsync. 3538fcb830afSNicholas Piggin * 3539fcb830afSNicholas Piggin * And separately serializes: 3540fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3541fcb830afSNicholas Piggin * 3542fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3543fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3544fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3545fcb830afSNicholas Piggin * serialization. 3546fcb830afSNicholas Piggin */ 3547c8fd8373SCédric Le Goater 3548c8fd8373SCédric Le Goater /* 3549c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3550c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3551c8fd8373SCédric Le Goater */ 3552c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3553c8fd8373SCédric Le Goater /* 3554c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3555c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3556c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3557c8fd8373SCédric Le Goater * complain to the user. 3558c8fd8373SCédric Le Goater */ 3559c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3560c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 35612c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3562c8fd8373SCédric Le Goater } else { 3563c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3564c8fd8373SCédric Le Goater } 3565c8fd8373SCédric Le Goater } 3566c8fd8373SCédric Le Goater 3567c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3568fcf5ef2aSThomas Huth } 3569fcf5ef2aSThomas Huth 3570fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3571fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3572fcf5ef2aSThomas Huth { 3573fcf5ef2aSThomas Huth TCGv_i32 t; 3574fcf5ef2aSThomas Huth TCGLabel *l; 3575fcf5ef2aSThomas Huth 3576fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3577fcf5ef2aSThomas Huth return; 3578fcf5ef2aSThomas Huth } 3579fcf5ef2aSThomas Huth l = gen_new_label(); 3580fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3581fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3582fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3583fcf5ef2aSThomas Huth if (global) { 3584fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3585fcf5ef2aSThomas Huth } else { 3586fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3587fcf5ef2aSThomas Huth } 3588fcf5ef2aSThomas Huth gen_set_label(l); 3589fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3590fcf5ef2aSThomas Huth } 3591fcf5ef2aSThomas Huth #else 3592fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3593fcf5ef2aSThomas Huth #endif 3594fcf5ef2aSThomas Huth 3595fcf5ef2aSThomas Huth /* isync */ 3596fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3597fcf5ef2aSThomas Huth { 3598fcf5ef2aSThomas Huth /* 3599fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3600fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3601fcf5ef2aSThomas Huth */ 3602fcf5ef2aSThomas Huth if (!ctx->pr) { 3603fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3604fcf5ef2aSThomas Huth } 36054771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3606d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3607fcf5ef2aSThomas Huth } 3608fcf5ef2aSThomas Huth 3609fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3610fcf5ef2aSThomas Huth 361114776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 36122a4e6c1bSRichard Henderson { 36132a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 36142a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 36152a4e6c1bSRichard Henderson 36162a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 36172a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 36182a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 36192a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 36202a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 36212a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 36222a4e6c1bSRichard Henderson tcg_temp_free(t0); 36232a4e6c1bSRichard Henderson } 36242a4e6c1bSRichard Henderson 3625fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3626fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3627fcf5ef2aSThomas Huth { \ 36282a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3629fcf5ef2aSThomas Huth } 3630fcf5ef2aSThomas Huth 3631fcf5ef2aSThomas Huth /* lwarx */ 3632fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3633fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3634fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3635fcf5ef2aSThomas Huth 363614776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 363720923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 363820923c1dSRichard Henderson { 363920923c1dSRichard Henderson TCGv t = tcg_temp_new(); 364020923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 364120923c1dSRichard Henderson TCGv u = tcg_temp_new(); 364220923c1dSRichard Henderson 364320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 364420923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 364520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 364620923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 364720923c1dSRichard Henderson 364820923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 364920923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 365020923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 365120923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 365220923c1dSRichard Henderson 365320923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 365420923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 365520923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 365620923c1dSRichard Henderson 365720923c1dSRichard Henderson tcg_temp_free(t); 365820923c1dSRichard Henderson tcg_temp_free(t2); 365920923c1dSRichard Henderson tcg_temp_free(u); 366020923c1dSRichard Henderson } 366120923c1dSRichard Henderson 366214776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 366320ba8504SRichard Henderson { 366420ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 366520ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 366620923c1dSRichard Henderson int rt = rD(ctx->opcode); 366720923c1dSRichard Henderson bool need_serial; 366820ba8504SRichard Henderson TCGv src, dst; 366920ba8504SRichard Henderson 367020ba8504SRichard Henderson gen_addr_register(ctx, EA); 367120923c1dSRichard Henderson dst = cpu_gpr[rt]; 367220923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 367320ba8504SRichard Henderson 367420923c1dSRichard Henderson need_serial = false; 367520ba8504SRichard Henderson memop |= MO_ALIGN; 367620ba8504SRichard Henderson switch (gpr_FC) { 367720ba8504SRichard Henderson case 0: /* Fetch and add */ 367820ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 367920ba8504SRichard Henderson break; 368020ba8504SRichard Henderson case 1: /* Fetch and xor */ 368120ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 368220ba8504SRichard Henderson break; 368320ba8504SRichard Henderson case 2: /* Fetch and or */ 368420ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 368520ba8504SRichard Henderson break; 368620ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 368720ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 368820ba8504SRichard Henderson break; 3689b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3690b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3691b8ce0f86SRichard Henderson break; 3692b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3693b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3694b8ce0f86SRichard Henderson break; 3695b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3696b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3697b8ce0f86SRichard Henderson break; 3698b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3699b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3700b8ce0f86SRichard Henderson break; 370120ba8504SRichard Henderson case 8: /* Swap */ 370220ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 370320ba8504SRichard Henderson break; 370420923c1dSRichard Henderson 370520923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 370620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 370720923c1dSRichard Henderson need_serial = true; 370820923c1dSRichard Henderson } else { 370920923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 371020923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 371120923c1dSRichard Henderson 371220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 371320923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 371420923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 371520923c1dSRichard Henderson } else { 371620923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 371720923c1dSRichard Henderson } 371820923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 371920923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 372020923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 372120923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 372220923c1dSRichard Henderson 372320923c1dSRichard Henderson tcg_temp_free(t0); 372420923c1dSRichard Henderson tcg_temp_free(t1); 372520923c1dSRichard Henderson } 372620ba8504SRichard Henderson break; 372720923c1dSRichard Henderson 372820923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 372920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 373020923c1dSRichard Henderson need_serial = true; 373120923c1dSRichard Henderson } else { 373220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 373320923c1dSRichard Henderson } 373420923c1dSRichard Henderson break; 373520923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 373620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 373720923c1dSRichard Henderson need_serial = true; 373820923c1dSRichard Henderson } else { 373920923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 374020923c1dSRichard Henderson } 374120923c1dSRichard Henderson break; 374220923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 374320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374420923c1dSRichard Henderson need_serial = true; 374520923c1dSRichard Henderson } else { 374620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 374720923c1dSRichard Henderson } 374820923c1dSRichard Henderson break; 374920923c1dSRichard Henderson 375020ba8504SRichard Henderson default: 375120ba8504SRichard Henderson /* invoke data storage error handler */ 375220ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 375320ba8504SRichard Henderson } 375420ba8504SRichard Henderson tcg_temp_free(EA); 375520923c1dSRichard Henderson 375620923c1dSRichard Henderson if (need_serial) { 375720923c1dSRichard Henderson /* Restart with exclusive lock. */ 375820923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 375920923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 376020923c1dSRichard Henderson } 3761a68a6146SBalamuruhan S } 3762a68a6146SBalamuruhan S 376320ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 376420ba8504SRichard Henderson { 376520ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 376620ba8504SRichard Henderson } 376720ba8504SRichard Henderson 376820ba8504SRichard Henderson #ifdef TARGET_PPC64 376920ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 377020ba8504SRichard Henderson { 3771fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 377220ba8504SRichard Henderson } 3773a68a6146SBalamuruhan S #endif 3774a68a6146SBalamuruhan S 377514776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 37769deb041cSRichard Henderson { 37779deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 37789deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 37799deb041cSRichard Henderson TCGv src, discard; 37809deb041cSRichard Henderson 37819deb041cSRichard Henderson gen_addr_register(ctx, EA); 37829deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 37839deb041cSRichard Henderson discard = tcg_temp_new(); 37849deb041cSRichard Henderson 37859deb041cSRichard Henderson memop |= MO_ALIGN; 37869deb041cSRichard Henderson switch (gpr_FC) { 37879deb041cSRichard Henderson case 0: /* add and Store */ 37889deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37899deb041cSRichard Henderson break; 37909deb041cSRichard Henderson case 1: /* xor and Store */ 37919deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37929deb041cSRichard Henderson break; 37939deb041cSRichard Henderson case 2: /* Or and Store */ 37949deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37959deb041cSRichard Henderson break; 37969deb041cSRichard Henderson case 3: /* 'and' and Store */ 37979deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37989deb041cSRichard Henderson break; 37999deb041cSRichard Henderson case 4: /* Store max unsigned */ 3800b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3801b8ce0f86SRichard Henderson break; 38029deb041cSRichard Henderson case 5: /* Store max signed */ 3803b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3804b8ce0f86SRichard Henderson break; 38059deb041cSRichard Henderson case 6: /* Store min unsigned */ 3806b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3807b8ce0f86SRichard Henderson break; 38089deb041cSRichard Henderson case 7: /* Store min signed */ 3809b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3810b8ce0f86SRichard Henderson break; 38119deb041cSRichard Henderson case 24: /* Store twin */ 38127fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 38137fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 38147fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 38157fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 38167fbc2b20SRichard Henderson } else { 38177fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 38187fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 38197fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 38207fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 38217fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 38227fbc2b20SRichard Henderson 38237fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 38247fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 38257fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 38267fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 38277fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 38287fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 38297fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 38307fbc2b20SRichard Henderson 38317fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 38327fbc2b20SRichard Henderson tcg_temp_free(s2); 38337fbc2b20SRichard Henderson tcg_temp_free(s); 38347fbc2b20SRichard Henderson tcg_temp_free(t2); 38357fbc2b20SRichard Henderson tcg_temp_free(t); 38367fbc2b20SRichard Henderson } 38379deb041cSRichard Henderson break; 38389deb041cSRichard Henderson default: 38399deb041cSRichard Henderson /* invoke data storage error handler */ 38409deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 38419deb041cSRichard Henderson } 38429deb041cSRichard Henderson tcg_temp_free(discard); 38439deb041cSRichard Henderson tcg_temp_free(EA); 3844a3401188SBalamuruhan S } 3845a3401188SBalamuruhan S 38469deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 38479deb041cSRichard Henderson { 38489deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 38499deb041cSRichard Henderson } 38509deb041cSRichard Henderson 38519deb041cSRichard Henderson #ifdef TARGET_PPC64 38529deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 38539deb041cSRichard Henderson { 3854fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 38559deb041cSRichard Henderson } 3856a3401188SBalamuruhan S #endif 3857a3401188SBalamuruhan S 385814776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3859fcf5ef2aSThomas Huth { 3860253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3861253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3862d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3863d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3864fcf5ef2aSThomas Huth 3865d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3866d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3867d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3868d8b86898SRichard Henderson tcg_temp_free(t0); 3869253ce7b2SNikunj A Dadhania 3870253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3871253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3872253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3873253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3874253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3875253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3876253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3877253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3878253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3879253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3880253ce7b2SNikunj A Dadhania 3881fcf5ef2aSThomas Huth gen_set_label(l1); 38824771df23SNikunj A Dadhania 3883efe843d8SDavid Gibson /* 3884efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3885efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3886efe843d8SDavid Gibson */ 38874771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3888253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3889253ce7b2SNikunj A Dadhania 3890253ce7b2SNikunj A Dadhania gen_set_label(l2); 3891fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3892fcf5ef2aSThomas Huth } 3893fcf5ef2aSThomas Huth 3894fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3895fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3896fcf5ef2aSThomas Huth { \ 3897d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3898fcf5ef2aSThomas Huth } 3899fcf5ef2aSThomas Huth 3900fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3901fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3902fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3903fcf5ef2aSThomas Huth 3904fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3905fcf5ef2aSThomas Huth /* ldarx */ 3906fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3907fcf5ef2aSThomas Huth /* stdcx. */ 3908fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3909fcf5ef2aSThomas Huth 3910fcf5ef2aSThomas Huth /* lqarx */ 3911fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3912fcf5ef2aSThomas Huth { 3913fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 391494bf2658SRichard Henderson TCGv EA, hi, lo; 3915fcf5ef2aSThomas Huth 3916fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3917fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3918fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3919fcf5ef2aSThomas Huth return; 3920fcf5ef2aSThomas Huth } 3921fcf5ef2aSThomas Huth 3922fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 392394bf2658SRichard Henderson EA = tcg_temp_new(); 3924fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 392594bf2658SRichard Henderson 392694bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 392794bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 392894bf2658SRichard Henderson hi = cpu_gpr[rd]; 392994bf2658SRichard Henderson 393094bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3931f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 393294bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 393394bf2658SRichard Henderson if (ctx->le_mode) { 393468e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 393594bf2658SRichard Henderson ctx->mem_idx)); 393694bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3937fcf5ef2aSThomas Huth } else { 393868e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 393994bf2658SRichard Henderson ctx->mem_idx)); 394094bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3941fcf5ef2aSThomas Huth } 394294bf2658SRichard Henderson tcg_temp_free_i32(oi); 394394bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3944f34ec0f6SRichard Henderson } else { 394594bf2658SRichard Henderson /* Restart with exclusive lock. */ 394694bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 394794bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 394894bf2658SRichard Henderson tcg_temp_free(EA); 394994bf2658SRichard Henderson return; 3950f34ec0f6SRichard Henderson } 395194bf2658SRichard Henderson } else if (ctx->le_mode) { 3952fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEUQ | MO_ALIGN_16); 3953fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3954fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3955fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEUQ); 395694bf2658SRichard Henderson } else { 3957fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEUQ | MO_ALIGN_16); 395894bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 395994bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3960fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ); 396194bf2658SRichard Henderson } 3962fcf5ef2aSThomas Huth tcg_temp_free(EA); 396394bf2658SRichard Henderson 396494bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 396594bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3966fcf5ef2aSThomas Huth } 3967fcf5ef2aSThomas Huth 3968fcf5ef2aSThomas Huth /* stqcx. */ 3969fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3970fcf5ef2aSThomas Huth { 39714a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 39724a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3973fcf5ef2aSThomas Huth 39744a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3975fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3976fcf5ef2aSThomas Huth return; 3977fcf5ef2aSThomas Huth } 39784a9b3c5dSRichard Henderson 3979fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 39804a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3981fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3982fcf5ef2aSThomas Huth 39834a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 39844a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 39854a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3986fcf5ef2aSThomas Huth 39874a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3988f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 398968e33d86SRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 39904a9b3c5dSRichard Henderson if (ctx->le_mode) { 3991f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3992f34ec0f6SRichard Henderson EA, lo, hi, oi); 3993fcf5ef2aSThomas Huth } else { 3994f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3995f34ec0f6SRichard Henderson EA, lo, hi, oi); 3996fcf5ef2aSThomas Huth } 3997f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 3998f34ec0f6SRichard Henderson } else { 39994a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 40004a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 40014a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4002f34ec0f6SRichard Henderson } 4003fcf5ef2aSThomas Huth tcg_temp_free(EA); 40044a9b3c5dSRichard Henderson } else { 40054a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 40064a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 40074a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 40084a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4009fcf5ef2aSThomas Huth 40104a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 40114a9b3c5dSRichard Henderson tcg_temp_free(EA); 40124a9b3c5dSRichard Henderson 40134a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 40144a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40154a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 40164a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 40174a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40184a9b3c5dSRichard Henderson 40194a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40204a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 40214a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40224a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 40234a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 40244a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40254a9b3c5dSRichard Henderson 40264a9b3c5dSRichard Henderson /* Success */ 40274a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 40284a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40294a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 40304a9b3c5dSRichard Henderson 40314a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40324a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 40334a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 40344a9b3c5dSRichard Henderson 40354a9b3c5dSRichard Henderson gen_set_label(lab_fail); 40364a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40374a9b3c5dSRichard Henderson 40384a9b3c5dSRichard Henderson gen_set_label(lab_over); 40394a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 40404a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 40414a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 40424a9b3c5dSRichard Henderson } 40434a9b3c5dSRichard Henderson } 4044fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4045fcf5ef2aSThomas Huth 4046fcf5ef2aSThomas Huth /* sync */ 4047fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4048fcf5ef2aSThomas Huth { 404903abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 4050fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4051fcf5ef2aSThomas Huth 405203abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 405303abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 405403abfd90SNicholas Piggin } 405503abfd90SNicholas Piggin 4056fcf5ef2aSThomas Huth /* 4057fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4058fcf5ef2aSThomas Huth * 4059fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4060fcf5ef2aSThomas Huth * 4061fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4062fcf5ef2aSThomas Huth * check MSR_PR as well. 4063fcf5ef2aSThomas Huth */ 4064fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4065fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4066fcf5ef2aSThomas Huth } 406703abfd90SNicholas Piggin 406803abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 4069fcf5ef2aSThomas Huth } 4070fcf5ef2aSThomas Huth 4071fcf5ef2aSThomas Huth /* wait */ 4072fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4073fcf5ef2aSThomas Huth { 40740c9717ffSNicholas Piggin uint32_t wc; 40750c9717ffSNicholas Piggin 40760c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 40770c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 40780c9717ffSNicholas Piggin 40790c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 40800c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 40810c9717ffSNicholas Piggin wc = WC(ctx->opcode); 40820c9717ffSNicholas Piggin } else { 40830c9717ffSNicholas Piggin wc = 0; 40840c9717ffSNicholas Piggin } 40850c9717ffSNicholas Piggin 40860c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 40870c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 40880c9717ffSNicholas Piggin wc = WC(ctx->opcode); 40890c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 40900c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 40910c9717ffSNicholas Piggin 40920c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 40930c9717ffSNicholas Piggin if (wc == 3) { 40940c9717ffSNicholas Piggin gen_invalid(ctx); 40950c9717ffSNicholas Piggin return; 40960c9717ffSNicholas Piggin } 40970c9717ffSNicholas Piggin 40980c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 40990c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 41000c9717ffSNicholas Piggin gen_invalid(ctx); 41010c9717ffSNicholas Piggin return; 41020c9717ffSNicholas Piggin } 41030c9717ffSNicholas Piggin 41040c9717ffSNicholas Piggin } else { /* ISA300 */ 41050c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 41060c9717ffSNicholas Piggin if (wc > 0) { 41070c9717ffSNicholas Piggin gen_invalid(ctx); 41080c9717ffSNicholas Piggin return; 41090c9717ffSNicholas Piggin } 41100c9717ffSNicholas Piggin } 41110c9717ffSNicholas Piggin 41120c9717ffSNicholas Piggin } else { 41130c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 41140c9717ffSNicholas Piggin gen_invalid(ctx); 41150c9717ffSNicholas Piggin return; 41160c9717ffSNicholas Piggin } 41170c9717ffSNicholas Piggin 41180c9717ffSNicholas Piggin /* 41190c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 41200c9717ffSNicholas Piggin * to occur. 41210c9717ffSNicholas Piggin */ 41220c9717ffSNicholas Piggin if (wc == 0) { 4123fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4124fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4125fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4126fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4127fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4128b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4129fcf5ef2aSThomas Huth } 4130fcf5ef2aSThomas Huth 41310c9717ffSNicholas Piggin /* 41320c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 41330c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 41340c9717ffSNicholas Piggin * 41350c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 41360c9717ffSNicholas Piggin * no-ops. 41370c9717ffSNicholas Piggin * 41380c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 41390c9717ffSNicholas Piggin * 41400c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 41410c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 41420c9717ffSNicholas Piggin * 41430c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 41440c9717ffSNicholas Piggin * 41450c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 41460c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 41470c9717ffSNicholas Piggin * can be implemented as a no-op. 41480c9717ffSNicholas Piggin * 41490c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 41500c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 41510c9717ffSNicholas Piggin * no-op. 41520c9717ffSNicholas Piggin * 41530c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 41540c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 41550c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 41560c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 41570c9717ffSNicholas Piggin * (if suboptimal). 41580c9717ffSNicholas Piggin */ 41590c9717ffSNicholas Piggin } 41600c9717ffSNicholas Piggin 4161fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4162fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4163fcf5ef2aSThomas Huth { 4164fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41659f0cf041SMatheus Ferst GEN_PRIV(ctx); 4166fcf5ef2aSThomas Huth #else 4167fcf5ef2aSThomas Huth TCGv_i32 t; 4168fcf5ef2aSThomas Huth 41699f0cf041SMatheus Ferst CHK_HV(ctx); 4170fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4171fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4172fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4173154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4174154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4175fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4176fcf5ef2aSThomas Huth } 4177fcf5ef2aSThomas Huth 4178fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4179fcf5ef2aSThomas Huth { 4180fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41819f0cf041SMatheus Ferst GEN_PRIV(ctx); 4182fcf5ef2aSThomas Huth #else 4183fcf5ef2aSThomas Huth TCGv_i32 t; 4184fcf5ef2aSThomas Huth 41859f0cf041SMatheus Ferst CHK_HV(ctx); 4186fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4187fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4188fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4189154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4190154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4191fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4192fcf5ef2aSThomas Huth } 4193fcf5ef2aSThomas Huth 4194cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4195cdee0e72SNikunj A Dadhania { 419621c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 41979f0cf041SMatheus Ferst GEN_PRIV(ctx); 419821c0d66aSBenjamin Herrenschmidt #else 419921c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 420021c0d66aSBenjamin Herrenschmidt 42019f0cf041SMatheus Ferst CHK_HV(ctx); 420221c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 420321c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 420421c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 420521c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 420621c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 420721c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4208cdee0e72SNikunj A Dadhania } 4209cdee0e72SNikunj A Dadhania 4210fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4211fcf5ef2aSThomas Huth { 4212fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42139f0cf041SMatheus Ferst GEN_PRIV(ctx); 4214fcf5ef2aSThomas Huth #else 4215fcf5ef2aSThomas Huth TCGv_i32 t; 4216fcf5ef2aSThomas Huth 42179f0cf041SMatheus Ferst CHK_HV(ctx); 4218fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4219fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4220fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4221154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4222154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4223fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4224fcf5ef2aSThomas Huth } 4225fcf5ef2aSThomas Huth 4226fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4227fcf5ef2aSThomas Huth { 4228fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 42299f0cf041SMatheus Ferst GEN_PRIV(ctx); 4230fcf5ef2aSThomas Huth #else 4231fcf5ef2aSThomas Huth TCGv_i32 t; 4232fcf5ef2aSThomas Huth 42339f0cf041SMatheus Ferst CHK_HV(ctx); 4234fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4235fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4236fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4237154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4238154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4239fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4240fcf5ef2aSThomas Huth } 4241fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4242fcf5ef2aSThomas Huth 4243fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4244fcf5ef2aSThomas Huth { 4245fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4246efe843d8SDavid Gibson if (ctx->has_cfar) { 4247fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4248efe843d8SDavid Gibson } 4249fcf5ef2aSThomas Huth #endif 4250fcf5ef2aSThomas Huth } 4251fcf5ef2aSThomas Huth 425246d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 425346d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 425446d396bdSDaniel Henrique Barboza { 425546d396bdSDaniel Henrique Barboza /* 425646d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 425746d396bdSDaniel Henrique Barboza * instructions. 425846d396bdSDaniel Henrique Barboza */ 425946d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 426046d396bdSDaniel Henrique Barboza return; 426146d396bdSDaniel Henrique Barboza } 426246d396bdSDaniel Henrique Barboza 426346d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 426446d396bdSDaniel Henrique Barboza /* 426546d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 426646d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 426746d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 426846d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 426946d396bdSDaniel Henrique Barboza */ 427046d396bdSDaniel Henrique Barboza gen_icount_io_start(ctx); 427146d396bdSDaniel Henrique Barboza 427246d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 427346d396bdSDaniel Henrique Barboza #else 427446d396bdSDaniel Henrique Barboza /* 427546d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 427646d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 427746d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 427846d396bdSDaniel Henrique Barboza */ 427946d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 428046d396bdSDaniel Henrique Barboza 428146d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 428246d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 428346d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 428446d396bdSDaniel Henrique Barboza 428546d396bdSDaniel Henrique Barboza tcg_temp_free(t0); 428646d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 428746d396bdSDaniel Henrique Barboza } 428846d396bdSDaniel Henrique Barboza #else 428946d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 429046d396bdSDaniel Henrique Barboza { 429146d396bdSDaniel Henrique Barboza return; 429246d396bdSDaniel Henrique Barboza } 429346d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 429446d396bdSDaniel Henrique Barboza 4295fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4296fcf5ef2aSThomas Huth { 42976e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4298fcf5ef2aSThomas Huth } 4299fcf5ef2aSThomas Huth 43000e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 43010e3bf489SRoman Kapl { 43029498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 43030e3bf489SRoman Kapl gen_debug_exception(ctx); 43040e3bf489SRoman Kapl } else { 430546d396bdSDaniel Henrique Barboza /* 430646d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 430746d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 430846d396bdSDaniel Henrique Barboza */ 430946d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 431046d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 431146d396bdSDaniel Henrique Barboza } 431246d396bdSDaniel Henrique Barboza 43130e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 43140e3bf489SRoman Kapl } 43150e3bf489SRoman Kapl } 43160e3bf489SRoman Kapl 4317fcf5ef2aSThomas Huth /*** Branch ***/ 4318c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4319fcf5ef2aSThomas Huth { 4320fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4321fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4322fcf5ef2aSThomas Huth } 4323fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 432446d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4325fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4326fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 432707ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4328fcf5ef2aSThomas Huth } else { 4329fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 43300e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4331fcf5ef2aSThomas Huth } 4332fcf5ef2aSThomas Huth } 4333fcf5ef2aSThomas Huth 4334fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4335fcf5ef2aSThomas Huth { 4336fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4337fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4338fcf5ef2aSThomas Huth } 4339fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4340fcf5ef2aSThomas Huth } 4341fcf5ef2aSThomas Huth 4342fcf5ef2aSThomas Huth /* b ba bl bla */ 4343fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4344fcf5ef2aSThomas Huth { 4345fcf5ef2aSThomas Huth target_ulong li, target; 4346fcf5ef2aSThomas Huth 4347fcf5ef2aSThomas Huth /* sign extend LI */ 4348fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4349fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4350fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43512c2bcb1bSRichard Henderson target = ctx->cia + li; 4352fcf5ef2aSThomas Huth } else { 4353fcf5ef2aSThomas Huth target = li; 4354fcf5ef2aSThomas Huth } 4355fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4356b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4357fcf5ef2aSThomas Huth } 43582c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4359fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 43606086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4361fcf5ef2aSThomas Huth } 4362fcf5ef2aSThomas Huth 4363fcf5ef2aSThomas Huth #define BCOND_IM 0 4364fcf5ef2aSThomas Huth #define BCOND_LR 1 4365fcf5ef2aSThomas Huth #define BCOND_CTR 2 4366fcf5ef2aSThomas Huth #define BCOND_TAR 3 4367fcf5ef2aSThomas Huth 4368c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4369fcf5ef2aSThomas Huth { 4370fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4371fcf5ef2aSThomas Huth TCGLabel *l1; 4372fcf5ef2aSThomas Huth TCGv target; 43730e3bf489SRoman Kapl 4374fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4375fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4376efe843d8SDavid Gibson if (type == BCOND_CTR) { 4377fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4378efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4379fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4380efe843d8SDavid Gibson } else { 4381fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4382efe843d8SDavid Gibson } 4383fcf5ef2aSThomas Huth } else { 4384f764718dSRichard Henderson target = NULL; 4385fcf5ef2aSThomas Huth } 4386efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4387b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4388efe843d8SDavid Gibson } 4389fcf5ef2aSThomas Huth l1 = gen_new_label(); 4390fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4391fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4392fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4393fa200c95SGreg Kurz 4394fa200c95SGreg Kurz if (type == BCOND_CTR) { 4395fa200c95SGreg Kurz /* 4396fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4397fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4398fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 439915d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 440015d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 440115d68c5eSGreg Kurz * it basically useless and thus never used in real code. 440215d68c5eSGreg Kurz * 440315d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 440415d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 440515d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 440615d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 440715d68c5eSGreg Kurz * doing anything else harmful. 4408fa200c95SGreg Kurz */ 4409d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4410fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 44119acc95cdSGreg Kurz tcg_temp_free(temp); 44129acc95cdSGreg Kurz tcg_temp_free(target); 4413fcf5ef2aSThomas Huth return; 4414fcf5ef2aSThomas Huth } 4415fa200c95SGreg Kurz 4416fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4417fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4418fa200c95SGreg Kurz } else { 4419fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4420fa200c95SGreg Kurz } 4421fa200c95SGreg Kurz if (bo & 0x2) { 4422fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4423fa200c95SGreg Kurz } else { 4424fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4425fa200c95SGreg Kurz } 4426fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4427fa200c95SGreg Kurz } else { 4428fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4429fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4430fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4431fcf5ef2aSThomas Huth } else { 4432fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4433fcf5ef2aSThomas Huth } 4434fcf5ef2aSThomas Huth if (bo & 0x2) { 4435fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4436fcf5ef2aSThomas Huth } else { 4437fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4438fcf5ef2aSThomas Huth } 4439fa200c95SGreg Kurz } 4440fcf5ef2aSThomas Huth tcg_temp_free(temp); 4441fcf5ef2aSThomas Huth } 4442fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4443fcf5ef2aSThomas Huth /* Test CR */ 4444fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4445fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4446fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4447fcf5ef2aSThomas Huth 4448fcf5ef2aSThomas Huth if (bo & 0x8) { 4449fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4450fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4451fcf5ef2aSThomas Huth } else { 4452fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4453fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4454fcf5ef2aSThomas Huth } 4455fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4456fcf5ef2aSThomas Huth } 44572c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4458fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4459fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4460fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 44612c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4462fcf5ef2aSThomas Huth } else { 4463fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4464fcf5ef2aSThomas Huth } 4465fcf5ef2aSThomas Huth } else { 4466fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4467fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4468fcf5ef2aSThomas Huth } else { 4469fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4470fcf5ef2aSThomas Huth } 44710e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4472c4a2e3a9SRichard Henderson tcg_temp_free(target); 4473c4a2e3a9SRichard Henderson } 4474fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 44750e3bf489SRoman Kapl /* fallthrough case */ 4476fcf5ef2aSThomas Huth gen_set_label(l1); 4477b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4478fcf5ef2aSThomas Huth } 44796086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4480fcf5ef2aSThomas Huth } 4481fcf5ef2aSThomas Huth 4482fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4483fcf5ef2aSThomas Huth { 4484fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4485fcf5ef2aSThomas Huth } 4486fcf5ef2aSThomas Huth 4487fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4488fcf5ef2aSThomas Huth { 4489fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4490fcf5ef2aSThomas Huth } 4491fcf5ef2aSThomas Huth 4492fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4493fcf5ef2aSThomas Huth { 4494fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4495fcf5ef2aSThomas Huth } 4496fcf5ef2aSThomas Huth 4497fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4498fcf5ef2aSThomas Huth { 4499fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4500fcf5ef2aSThomas Huth } 4501fcf5ef2aSThomas Huth 4502fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4503fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4504fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4505fcf5ef2aSThomas Huth { \ 4506fcf5ef2aSThomas Huth uint8_t bitmask; \ 4507fcf5ef2aSThomas Huth int sh; \ 4508fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4509fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4510fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4511fcf5ef2aSThomas Huth if (sh > 0) \ 4512fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4513fcf5ef2aSThomas Huth else if (sh < 0) \ 4514fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4515fcf5ef2aSThomas Huth else \ 4516fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4517fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4518fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4519fcf5ef2aSThomas Huth if (sh > 0) \ 4520fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4521fcf5ef2aSThomas Huth else if (sh < 0) \ 4522fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4523fcf5ef2aSThomas Huth else \ 4524fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4525fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4526fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4527fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4528fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4529fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4530fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4531fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4532fcf5ef2aSThomas Huth } 4533fcf5ef2aSThomas Huth 4534fcf5ef2aSThomas Huth /* crand */ 4535fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4536fcf5ef2aSThomas Huth /* crandc */ 4537fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4538fcf5ef2aSThomas Huth /* creqv */ 4539fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4540fcf5ef2aSThomas Huth /* crnand */ 4541fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4542fcf5ef2aSThomas Huth /* crnor */ 4543fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4544fcf5ef2aSThomas Huth /* cror */ 4545fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4546fcf5ef2aSThomas Huth /* crorc */ 4547fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4548fcf5ef2aSThomas Huth /* crxor */ 4549fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4550fcf5ef2aSThomas Huth 4551fcf5ef2aSThomas Huth /* mcrf */ 4552fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4553fcf5ef2aSThomas Huth { 4554fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4555fcf5ef2aSThomas Huth } 4556fcf5ef2aSThomas Huth 4557fcf5ef2aSThomas Huth /*** System linkage ***/ 4558fcf5ef2aSThomas Huth 4559fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4560fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4561fcf5ef2aSThomas Huth { 4562fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 45639f0cf041SMatheus Ferst GEN_PRIV(ctx); 4564fcf5ef2aSThomas Huth #else 4565efe843d8SDavid Gibson /* 4566efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4567fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4568fcf5ef2aSThomas Huth */ 4569d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4570fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4571fcf5ef2aSThomas Huth return; 4572fcf5ef2aSThomas Huth } 4573fcf5ef2aSThomas Huth /* Restore CPU state */ 45749f0cf041SMatheus Ferst CHK_SV(ctx); 4575f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45762c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4577fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 457859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4579fcf5ef2aSThomas Huth #endif 4580fcf5ef2aSThomas Huth } 4581fcf5ef2aSThomas Huth 4582fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4583fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4584fcf5ef2aSThomas Huth { 4585fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 45869f0cf041SMatheus Ferst GEN_PRIV(ctx); 4587fcf5ef2aSThomas Huth #else 4588fcf5ef2aSThomas Huth /* Restore CPU state */ 45899f0cf041SMatheus Ferst CHK_SV(ctx); 4590f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45912c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4592fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 459359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4594fcf5ef2aSThomas Huth #endif 4595fcf5ef2aSThomas Huth } 4596fcf5ef2aSThomas Huth 45973c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45983c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 45993c89b8d6SNicholas Piggin { 46003c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 46019f0cf041SMatheus Ferst GEN_PRIV(ctx); 46023c89b8d6SNicholas Piggin #else 46033c89b8d6SNicholas Piggin /* Restore CPU state */ 46049f0cf041SMatheus Ferst CHK_SV(ctx); 4605f5b6daacSRichard Henderson gen_icount_io_start(ctx); 46062c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 46073c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 460859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 46093c89b8d6SNicholas Piggin #endif 46103c89b8d6SNicholas Piggin } 46113c89b8d6SNicholas Piggin #endif 46123c89b8d6SNicholas Piggin 4613fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4614fcf5ef2aSThomas Huth { 4615fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 46169f0cf041SMatheus Ferst GEN_PRIV(ctx); 4617fcf5ef2aSThomas Huth #else 4618fcf5ef2aSThomas Huth /* Restore CPU state */ 46199f0cf041SMatheus Ferst CHK_HV(ctx); 4620fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 462159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4622fcf5ef2aSThomas Huth #endif 4623fcf5ef2aSThomas Huth } 4624fcf5ef2aSThomas Huth #endif 4625fcf5ef2aSThomas Huth 4626fcf5ef2aSThomas Huth /* sc */ 4627fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4628fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4629fcf5ef2aSThomas Huth #else 4630fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 46313c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4632fcf5ef2aSThomas Huth #endif 4633fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4634fcf5ef2aSThomas Huth { 4635fcf5ef2aSThomas Huth uint32_t lev; 4636fcf5ef2aSThomas Huth 4637fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4638fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4639fcf5ef2aSThomas Huth } 4640fcf5ef2aSThomas Huth 46413c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 46423c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 46433c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 46443c89b8d6SNicholas Piggin { 4645f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 46463c89b8d6SNicholas Piggin 4647f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 46482c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4649f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 46503c89b8d6SNicholas Piggin 46517a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 46523c89b8d6SNicholas Piggin } 46533c89b8d6SNicholas Piggin #endif 46543c89b8d6SNicholas Piggin #endif 46553c89b8d6SNicholas Piggin 4656fcf5ef2aSThomas Huth /*** Trap ***/ 4657fcf5ef2aSThomas Huth 4658fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4659fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4660fcf5ef2aSThomas Huth { 4661fcf5ef2aSThomas Huth /* Trap never */ 4662fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4663fcf5ef2aSThomas Huth return true; 4664fcf5ef2aSThomas Huth } 4665fcf5ef2aSThomas Huth /* Trap always */ 4666fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4667fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4668fcf5ef2aSThomas Huth return true; 4669fcf5ef2aSThomas Huth } 4670fcf5ef2aSThomas Huth return false; 4671fcf5ef2aSThomas Huth } 4672fcf5ef2aSThomas Huth 4673fcf5ef2aSThomas Huth /* tw */ 4674fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4675fcf5ef2aSThomas Huth { 4676fcf5ef2aSThomas Huth TCGv_i32 t0; 4677fcf5ef2aSThomas Huth 4678fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4679fcf5ef2aSThomas Huth return; 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4682fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4683fcf5ef2aSThomas Huth t0); 4684fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4685fcf5ef2aSThomas Huth } 4686fcf5ef2aSThomas Huth 4687fcf5ef2aSThomas Huth /* twi */ 4688fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4689fcf5ef2aSThomas Huth { 4690fcf5ef2aSThomas Huth TCGv t0; 4691fcf5ef2aSThomas Huth TCGv_i32 t1; 4692fcf5ef2aSThomas Huth 4693fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4694fcf5ef2aSThomas Huth return; 4695fcf5ef2aSThomas Huth } 4696fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4697fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4698fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4699fcf5ef2aSThomas Huth tcg_temp_free(t0); 4700fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4701fcf5ef2aSThomas Huth } 4702fcf5ef2aSThomas Huth 4703fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4704fcf5ef2aSThomas Huth /* td */ 4705fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4706fcf5ef2aSThomas Huth { 4707fcf5ef2aSThomas Huth TCGv_i32 t0; 4708fcf5ef2aSThomas Huth 4709fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4710fcf5ef2aSThomas Huth return; 4711fcf5ef2aSThomas Huth } 4712fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4713fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4714fcf5ef2aSThomas Huth t0); 4715fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4716fcf5ef2aSThomas Huth } 4717fcf5ef2aSThomas Huth 4718fcf5ef2aSThomas Huth /* tdi */ 4719fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4720fcf5ef2aSThomas Huth { 4721fcf5ef2aSThomas Huth TCGv t0; 4722fcf5ef2aSThomas Huth TCGv_i32 t1; 4723fcf5ef2aSThomas Huth 4724fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4725fcf5ef2aSThomas Huth return; 4726fcf5ef2aSThomas Huth } 4727fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4728fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4729fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4730fcf5ef2aSThomas Huth tcg_temp_free(t0); 4731fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4732fcf5ef2aSThomas Huth } 4733fcf5ef2aSThomas Huth #endif 4734fcf5ef2aSThomas Huth 4735fcf5ef2aSThomas Huth /*** Processor control ***/ 4736fcf5ef2aSThomas Huth 4737fcf5ef2aSThomas Huth /* mcrxr */ 4738fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4739fcf5ef2aSThomas Huth { 4740fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4741fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4742fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4743fcf5ef2aSThomas Huth 4744fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4745fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4746fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4747fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4748fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4749fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4750fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4751fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4752fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4753fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4754fcf5ef2aSThomas Huth 4755fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4756fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4757fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4758fcf5ef2aSThomas Huth } 4759fcf5ef2aSThomas Huth 4760b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4761b63d0434SNikunj A Dadhania /* mcrxrx */ 4762b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4763b63d0434SNikunj A Dadhania { 4764b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4765b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4766b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4767b63d0434SNikunj A Dadhania 4768b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4769b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4770b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4771b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4772b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4773b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4774b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4775b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4776b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4777b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4778b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4779b63d0434SNikunj A Dadhania } 4780b63d0434SNikunj A Dadhania #endif 4781b63d0434SNikunj A Dadhania 4782fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4783fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4784fcf5ef2aSThomas Huth { 4785fcf5ef2aSThomas Huth uint32_t crm, crn; 4786fcf5ef2aSThomas Huth 4787fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4788fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4789fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4790fcf5ef2aSThomas Huth crn = ctz32(crm); 4791fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4792fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4793fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4794fcf5ef2aSThomas Huth } 4795fcf5ef2aSThomas Huth } else { 4796fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4797fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4798fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4799fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4800fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4801fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4802fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4803fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4804fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4805fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4806fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4807fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4808fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4809fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4810fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4811fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4812fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4813fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4814fcf5ef2aSThomas Huth } 4815fcf5ef2aSThomas Huth } 4816fcf5ef2aSThomas Huth 4817fcf5ef2aSThomas Huth /* mfmsr */ 4818fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4819fcf5ef2aSThomas Huth { 48209f0cf041SMatheus Ferst CHK_SV(ctx); 4821fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4822fcf5ef2aSThomas Huth } 4823fcf5ef2aSThomas Huth 4824fcf5ef2aSThomas Huth /* mfspr */ 4825fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4826fcf5ef2aSThomas Huth { 4827fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4828fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4829fcf5ef2aSThomas Huth 4830fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4831fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4832fcf5ef2aSThomas Huth #else 4833fcf5ef2aSThomas Huth if (ctx->pr) { 4834fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4835fcf5ef2aSThomas Huth } else if (ctx->hv) { 4836fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4837fcf5ef2aSThomas Huth } else { 4838fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4839fcf5ef2aSThomas Huth } 4840fcf5ef2aSThomas Huth #endif 4841fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4842fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4843fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4844fcf5ef2aSThomas Huth } else { 4845fcf5ef2aSThomas Huth /* Privilege exception */ 4846efe843d8SDavid Gibson /* 4847efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4848fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4849fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4850fcf5ef2aSThomas Huth */ 4851fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 485231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 485331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 48542c2bcb1bSRichard Henderson ctx->cia); 4855fcf5ef2aSThomas Huth } 4856fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4857fcf5ef2aSThomas Huth } 4858fcf5ef2aSThomas Huth } else { 4859fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4860fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4861fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4862fcf5ef2aSThomas Huth /* This is a nop */ 4863fcf5ef2aSThomas Huth return; 4864fcf5ef2aSThomas Huth } 4865fcf5ef2aSThomas Huth /* Not defined */ 486631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 486731085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 48682c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4869fcf5ef2aSThomas Huth 4870efe843d8SDavid Gibson /* 4871efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4872efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4873fcf5ef2aSThomas Huth */ 4874fcf5ef2aSThomas Huth if (sprn & 0x10) { 4875fcf5ef2aSThomas Huth if (ctx->pr) { 48761315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4877fcf5ef2aSThomas Huth } 4878fcf5ef2aSThomas Huth } else { 4879fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 48801315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4881fcf5ef2aSThomas Huth } 4882fcf5ef2aSThomas Huth } 4883fcf5ef2aSThomas Huth } 4884fcf5ef2aSThomas Huth } 4885fcf5ef2aSThomas Huth 4886fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4887fcf5ef2aSThomas Huth { 4888fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4889fcf5ef2aSThomas Huth } 4890fcf5ef2aSThomas Huth 4891fcf5ef2aSThomas Huth /* mftb */ 4892fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4893fcf5ef2aSThomas Huth { 4894fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4895fcf5ef2aSThomas Huth } 4896fcf5ef2aSThomas Huth 4897fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4898fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4899fcf5ef2aSThomas Huth { 4900fcf5ef2aSThomas Huth uint32_t crm, crn; 4901fcf5ef2aSThomas Huth 4902fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4903fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4904fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4905fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4906fcf5ef2aSThomas Huth crn = ctz32(crm); 4907fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4908fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4909fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4910fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4911fcf5ef2aSThomas Huth } 4912fcf5ef2aSThomas Huth } else { 4913fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4914fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4915fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4916fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4917fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4918fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4919fcf5ef2aSThomas Huth } 4920fcf5ef2aSThomas Huth } 4921fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4922fcf5ef2aSThomas Huth } 4923fcf5ef2aSThomas Huth } 4924fcf5ef2aSThomas Huth 4925fcf5ef2aSThomas Huth /* mtmsr */ 4926fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4927fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4928fcf5ef2aSThomas Huth { 4929caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4930caf590ddSNicholas Piggin gen_invalid(ctx); 4931caf590ddSNicholas Piggin return; 4932caf590ddSNicholas Piggin } 4933caf590ddSNicholas Piggin 49349f0cf041SMatheus Ferst CHK_SV(ctx); 4935fcf5ef2aSThomas Huth 4936fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49376fa5726bSMatheus Ferst TCGv t0, t1; 49386fa5726bSMatheus Ferst target_ulong mask; 49396fa5726bSMatheus Ferst 49406fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49416fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49426fa5726bSMatheus Ferst 4943f5b6daacSRichard Henderson gen_icount_io_start(ctx); 49446fa5726bSMatheus Ferst 4945fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49465ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49476fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4948fcf5ef2aSThomas Huth } else { 49496fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 49506fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 49516fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4952efe843d8SDavid Gibson /* 4953efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4954efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4955efe843d8SDavid Gibson * ppc_store_msr 4956fcf5ef2aSThomas Huth */ 4957b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4958fcf5ef2aSThomas Huth } 49596fa5726bSMatheus Ferst 49606fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 49616fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 49626fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 49636fa5726bSMatheus Ferst 49646fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 49656fa5726bSMatheus Ferst 49665ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4967d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 49686fa5726bSMatheus Ferst 49696fa5726bSMatheus Ferst tcg_temp_free(t0); 49706fa5726bSMatheus Ferst tcg_temp_free(t1); 4971fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4972fcf5ef2aSThomas Huth } 4973fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4974fcf5ef2aSThomas Huth 4975fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4976fcf5ef2aSThomas Huth { 49779f0cf041SMatheus Ferst CHK_SV(ctx); 4978fcf5ef2aSThomas Huth 4979fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49806fa5726bSMatheus Ferst TCGv t0, t1; 49816fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 49826fa5726bSMatheus Ferst 49836fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49846fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49856fa5726bSMatheus Ferst 4986f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4987fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49885ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49896fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4990fcf5ef2aSThomas Huth } else { 49916fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 49926fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4993fcf5ef2aSThomas Huth 4994efe843d8SDavid Gibson /* 4995efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4996efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4997efe843d8SDavid Gibson * ppc_store_msr 4998fcf5ef2aSThomas Huth */ 4999b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5000fcf5ef2aSThomas Huth } 50016fa5726bSMatheus Ferst 50026fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 50036fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 50046fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 50056fa5726bSMatheus Ferst 50066fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 50076fa5726bSMatheus Ferst 50085ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 5009d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 50106fa5726bSMatheus Ferst 50116fa5726bSMatheus Ferst tcg_temp_free(t0); 50126fa5726bSMatheus Ferst tcg_temp_free(t1); 5013fcf5ef2aSThomas Huth #endif 5014fcf5ef2aSThomas Huth } 5015fcf5ef2aSThomas Huth 5016fcf5ef2aSThomas Huth /* mtspr */ 5017fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5018fcf5ef2aSThomas Huth { 5019fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5020fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5021fcf5ef2aSThomas Huth 5022fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5023fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5024fcf5ef2aSThomas Huth #else 5025fcf5ef2aSThomas Huth if (ctx->pr) { 5026fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5027fcf5ef2aSThomas Huth } else if (ctx->hv) { 5028fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5029fcf5ef2aSThomas Huth } else { 5030fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5031fcf5ef2aSThomas Huth } 5032fcf5ef2aSThomas Huth #endif 5033fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5034fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5035fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5036fcf5ef2aSThomas Huth } else { 5037fcf5ef2aSThomas Huth /* Privilege exception */ 503831085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 503931085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 50402c2bcb1bSRichard Henderson ctx->cia); 5041fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5042fcf5ef2aSThomas Huth } 5043fcf5ef2aSThomas Huth } else { 5044fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5045fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5046fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5047fcf5ef2aSThomas Huth /* This is a nop */ 5048fcf5ef2aSThomas Huth return; 5049fcf5ef2aSThomas Huth } 5050fcf5ef2aSThomas Huth 5051fcf5ef2aSThomas Huth /* Not defined */ 505231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 505331085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 50542c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5055fcf5ef2aSThomas Huth 5056fcf5ef2aSThomas Huth 5057efe843d8SDavid Gibson /* 5058efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5059efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5060fcf5ef2aSThomas Huth */ 5061fcf5ef2aSThomas Huth if (sprn & 0x10) { 5062fcf5ef2aSThomas Huth if (ctx->pr) { 50631315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5064fcf5ef2aSThomas Huth } 5065fcf5ef2aSThomas Huth } else { 5066fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 50671315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5068fcf5ef2aSThomas Huth } 5069fcf5ef2aSThomas Huth } 5070fcf5ef2aSThomas Huth } 5071fcf5ef2aSThomas Huth } 5072fcf5ef2aSThomas Huth 5073fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5074fcf5ef2aSThomas Huth /* setb */ 5075fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5076fcf5ef2aSThomas Huth { 5077fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 50786f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 50796f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5080fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5081fcf5ef2aSThomas Huth 5082fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5083fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5084fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5085fcf5ef2aSThomas Huth 5086fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5087fcf5ef2aSThomas Huth } 5088fcf5ef2aSThomas Huth #endif 5089fcf5ef2aSThomas Huth 5090fcf5ef2aSThomas Huth /*** Cache management ***/ 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth /* dcbf */ 5093fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5094fcf5ef2aSThomas Huth { 5095fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5096fcf5ef2aSThomas Huth TCGv t0; 5097fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5098fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5099fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5100fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5101fcf5ef2aSThomas Huth tcg_temp_free(t0); 5102fcf5ef2aSThomas Huth } 5103fcf5ef2aSThomas Huth 510450728199SRoman Kapl /* dcbfep (external PID dcbf) */ 510550728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 510650728199SRoman Kapl { 510750728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 510850728199SRoman Kapl TCGv t0; 51099f0cf041SMatheus Ferst CHK_SV(ctx); 511050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 511150728199SRoman Kapl t0 = tcg_temp_new(); 511250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 511350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 511450728199SRoman Kapl tcg_temp_free(t0); 511550728199SRoman Kapl } 511650728199SRoman Kapl 5117fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5118fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5119fcf5ef2aSThomas Huth { 5120fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51219f0cf041SMatheus Ferst GEN_PRIV(ctx); 5122fcf5ef2aSThomas Huth #else 5123fcf5ef2aSThomas Huth TCGv EA, val; 5124fcf5ef2aSThomas Huth 51259f0cf041SMatheus Ferst CHK_SV(ctx); 5126fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5127fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5128fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5129fcf5ef2aSThomas Huth val = tcg_temp_new(); 5130fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5131fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5132fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5133fcf5ef2aSThomas Huth tcg_temp_free(val); 5134fcf5ef2aSThomas Huth tcg_temp_free(EA); 5135fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5136fcf5ef2aSThomas Huth } 5137fcf5ef2aSThomas Huth 5138fcf5ef2aSThomas Huth /* dcdst */ 5139fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5140fcf5ef2aSThomas Huth { 5141fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5142fcf5ef2aSThomas Huth TCGv t0; 5143fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5144fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5145fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5146fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5147fcf5ef2aSThomas Huth tcg_temp_free(t0); 5148fcf5ef2aSThomas Huth } 5149fcf5ef2aSThomas Huth 515050728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 515150728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 515250728199SRoman Kapl { 515350728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 515450728199SRoman Kapl TCGv t0; 515550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 515650728199SRoman Kapl t0 = tcg_temp_new(); 515750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 515850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 515950728199SRoman Kapl tcg_temp_free(t0); 516050728199SRoman Kapl } 516150728199SRoman Kapl 5162fcf5ef2aSThomas Huth /* dcbt */ 5163fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5164fcf5ef2aSThomas Huth { 5165efe843d8SDavid Gibson /* 5166efe843d8SDavid Gibson * interpreted as no-op 5167efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5168efe843d8SDavid Gibson * does not generate any exception 5169fcf5ef2aSThomas Huth */ 5170fcf5ef2aSThomas Huth } 5171fcf5ef2aSThomas Huth 517250728199SRoman Kapl /* dcbtep */ 517350728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 517450728199SRoman Kapl { 5175efe843d8SDavid Gibson /* 5176efe843d8SDavid Gibson * interpreted as no-op 5177efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5178efe843d8SDavid Gibson * does not generate any exception 517950728199SRoman Kapl */ 518050728199SRoman Kapl } 518150728199SRoman Kapl 5182fcf5ef2aSThomas Huth /* dcbtst */ 5183fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5184fcf5ef2aSThomas Huth { 5185efe843d8SDavid Gibson /* 5186efe843d8SDavid Gibson * interpreted as no-op 5187efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5188efe843d8SDavid Gibson * does not generate any exception 5189fcf5ef2aSThomas Huth */ 5190fcf5ef2aSThomas Huth } 5191fcf5ef2aSThomas Huth 519250728199SRoman Kapl /* dcbtstep */ 519350728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 519450728199SRoman Kapl { 5195efe843d8SDavid Gibson /* 5196efe843d8SDavid Gibson * interpreted as no-op 5197efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5198efe843d8SDavid Gibson * does not generate any exception 519950728199SRoman Kapl */ 520050728199SRoman Kapl } 520150728199SRoman Kapl 5202fcf5ef2aSThomas Huth /* dcbtls */ 5203fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5204fcf5ef2aSThomas Huth { 5205fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5206fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5207fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5208fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5209fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5210fcf5ef2aSThomas Huth tcg_temp_free(t0); 5211fcf5ef2aSThomas Huth } 5212fcf5ef2aSThomas Huth 5213fcf5ef2aSThomas Huth /* dcbz */ 5214fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5215fcf5ef2aSThomas Huth { 5216fcf5ef2aSThomas Huth TCGv tcgv_addr; 5217fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5218fcf5ef2aSThomas Huth 5219fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5220fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5221fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5222fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5223fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5224fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5225fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5226fcf5ef2aSThomas Huth } 5227fcf5ef2aSThomas Huth 522850728199SRoman Kapl /* dcbzep */ 522950728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 523050728199SRoman Kapl { 523150728199SRoman Kapl TCGv tcgv_addr; 523250728199SRoman Kapl TCGv_i32 tcgv_op; 523350728199SRoman Kapl 523450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 523550728199SRoman Kapl tcgv_addr = tcg_temp_new(); 523650728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 523750728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 523850728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 523950728199SRoman Kapl tcg_temp_free(tcgv_addr); 524050728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 524150728199SRoman Kapl } 524250728199SRoman Kapl 5243fcf5ef2aSThomas Huth /* dst / dstt */ 5244fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5245fcf5ef2aSThomas Huth { 5246fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5247fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5248fcf5ef2aSThomas Huth } else { 5249fcf5ef2aSThomas Huth /* interpreted as no-op */ 5250fcf5ef2aSThomas Huth } 5251fcf5ef2aSThomas Huth } 5252fcf5ef2aSThomas Huth 5253fcf5ef2aSThomas Huth /* dstst /dststt */ 5254fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5255fcf5ef2aSThomas Huth { 5256fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5257fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5258fcf5ef2aSThomas Huth } else { 5259fcf5ef2aSThomas Huth /* interpreted as no-op */ 5260fcf5ef2aSThomas Huth } 5261fcf5ef2aSThomas Huth 5262fcf5ef2aSThomas Huth } 5263fcf5ef2aSThomas Huth 5264fcf5ef2aSThomas Huth /* dss / dssall */ 5265fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5266fcf5ef2aSThomas Huth { 5267fcf5ef2aSThomas Huth /* interpreted as no-op */ 5268fcf5ef2aSThomas Huth } 5269fcf5ef2aSThomas Huth 5270fcf5ef2aSThomas Huth /* icbi */ 5271fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5272fcf5ef2aSThomas Huth { 5273fcf5ef2aSThomas Huth TCGv t0; 5274fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5275fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5276fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5277fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5278fcf5ef2aSThomas Huth tcg_temp_free(t0); 5279fcf5ef2aSThomas Huth } 5280fcf5ef2aSThomas Huth 528150728199SRoman Kapl /* icbiep */ 528250728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 528350728199SRoman Kapl { 528450728199SRoman Kapl TCGv t0; 528550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 528650728199SRoman Kapl t0 = tcg_temp_new(); 528750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 528850728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 528950728199SRoman Kapl tcg_temp_free(t0); 529050728199SRoman Kapl } 529150728199SRoman Kapl 5292fcf5ef2aSThomas Huth /* Optional: */ 5293fcf5ef2aSThomas Huth /* dcba */ 5294fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5295fcf5ef2aSThomas Huth { 5296efe843d8SDavid Gibson /* 5297efe843d8SDavid Gibson * interpreted as no-op 5298efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5299fcf5ef2aSThomas Huth * but does not generate any exception 5300fcf5ef2aSThomas Huth */ 5301fcf5ef2aSThomas Huth } 5302fcf5ef2aSThomas Huth 5303fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5304fcf5ef2aSThomas Huth /* Supervisor only: */ 5305fcf5ef2aSThomas Huth 5306fcf5ef2aSThomas Huth /* mfsr */ 5307fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5308fcf5ef2aSThomas Huth { 5309fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53109f0cf041SMatheus Ferst GEN_PRIV(ctx); 5311fcf5ef2aSThomas Huth #else 5312fcf5ef2aSThomas Huth TCGv t0; 5313fcf5ef2aSThomas Huth 53149f0cf041SMatheus Ferst CHK_SV(ctx); 5315fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5316fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5317fcf5ef2aSThomas Huth tcg_temp_free(t0); 5318fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5319fcf5ef2aSThomas Huth } 5320fcf5ef2aSThomas Huth 5321fcf5ef2aSThomas Huth /* mfsrin */ 5322fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5323fcf5ef2aSThomas Huth { 5324fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53259f0cf041SMatheus Ferst GEN_PRIV(ctx); 5326fcf5ef2aSThomas Huth #else 5327fcf5ef2aSThomas Huth TCGv t0; 5328fcf5ef2aSThomas Huth 53299f0cf041SMatheus Ferst CHK_SV(ctx); 5330fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5331e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5332fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5333fcf5ef2aSThomas Huth tcg_temp_free(t0); 5334fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5335fcf5ef2aSThomas Huth } 5336fcf5ef2aSThomas Huth 5337fcf5ef2aSThomas Huth /* mtsr */ 5338fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5339fcf5ef2aSThomas Huth { 5340fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53419f0cf041SMatheus Ferst GEN_PRIV(ctx); 5342fcf5ef2aSThomas Huth #else 5343fcf5ef2aSThomas Huth TCGv t0; 5344fcf5ef2aSThomas Huth 53459f0cf041SMatheus Ferst CHK_SV(ctx); 5346fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5347fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5348fcf5ef2aSThomas Huth tcg_temp_free(t0); 5349fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5350fcf5ef2aSThomas Huth } 5351fcf5ef2aSThomas Huth 5352fcf5ef2aSThomas Huth /* mtsrin */ 5353fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5354fcf5ef2aSThomas Huth { 5355fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53569f0cf041SMatheus Ferst GEN_PRIV(ctx); 5357fcf5ef2aSThomas Huth #else 5358fcf5ef2aSThomas Huth TCGv t0; 53599f0cf041SMatheus Ferst CHK_SV(ctx); 5360fcf5ef2aSThomas Huth 5361fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5362e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5363fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5364fcf5ef2aSThomas Huth tcg_temp_free(t0); 5365fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5366fcf5ef2aSThomas Huth } 5367fcf5ef2aSThomas Huth 5368fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5369fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5370fcf5ef2aSThomas Huth 5371fcf5ef2aSThomas Huth /* mfsr */ 5372fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5373fcf5ef2aSThomas Huth { 5374fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53759f0cf041SMatheus Ferst GEN_PRIV(ctx); 5376fcf5ef2aSThomas Huth #else 5377fcf5ef2aSThomas Huth TCGv t0; 5378fcf5ef2aSThomas Huth 53799f0cf041SMatheus Ferst CHK_SV(ctx); 5380fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5381fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5382fcf5ef2aSThomas Huth tcg_temp_free(t0); 5383fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5384fcf5ef2aSThomas Huth } 5385fcf5ef2aSThomas Huth 5386fcf5ef2aSThomas Huth /* mfsrin */ 5387fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5388fcf5ef2aSThomas Huth { 5389fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53909f0cf041SMatheus Ferst GEN_PRIV(ctx); 5391fcf5ef2aSThomas Huth #else 5392fcf5ef2aSThomas Huth TCGv t0; 5393fcf5ef2aSThomas Huth 53949f0cf041SMatheus Ferst CHK_SV(ctx); 5395fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5396e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5397fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5398fcf5ef2aSThomas Huth tcg_temp_free(t0); 5399fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5400fcf5ef2aSThomas Huth } 5401fcf5ef2aSThomas Huth 5402fcf5ef2aSThomas Huth /* mtsr */ 5403fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5404fcf5ef2aSThomas Huth { 5405fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54069f0cf041SMatheus Ferst GEN_PRIV(ctx); 5407fcf5ef2aSThomas Huth #else 5408fcf5ef2aSThomas Huth TCGv t0; 5409fcf5ef2aSThomas Huth 54109f0cf041SMatheus Ferst CHK_SV(ctx); 5411fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5412fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5413fcf5ef2aSThomas Huth tcg_temp_free(t0); 5414fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5415fcf5ef2aSThomas Huth } 5416fcf5ef2aSThomas Huth 5417fcf5ef2aSThomas Huth /* mtsrin */ 5418fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5419fcf5ef2aSThomas Huth { 5420fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54219f0cf041SMatheus Ferst GEN_PRIV(ctx); 5422fcf5ef2aSThomas Huth #else 5423fcf5ef2aSThomas Huth TCGv t0; 5424fcf5ef2aSThomas Huth 54259f0cf041SMatheus Ferst CHK_SV(ctx); 5426fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5427e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5428fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5429fcf5ef2aSThomas Huth tcg_temp_free(t0); 5430fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5431fcf5ef2aSThomas Huth } 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5434fcf5ef2aSThomas Huth 5435fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5436fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5437fcf5ef2aSThomas Huth 5438fcf5ef2aSThomas Huth /* tlbia */ 5439fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5440fcf5ef2aSThomas Huth { 5441fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54429f0cf041SMatheus Ferst GEN_PRIV(ctx); 5443fcf5ef2aSThomas Huth #else 54449f0cf041SMatheus Ferst CHK_HV(ctx); 5445fcf5ef2aSThomas Huth 5446fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5447fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5448fcf5ef2aSThomas Huth } 5449fcf5ef2aSThomas Huth 5450fcf5ef2aSThomas Huth /* tlbsync */ 5451fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5452fcf5ef2aSThomas Huth { 5453fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 54549f0cf041SMatheus Ferst GEN_PRIV(ctx); 5455fcf5ef2aSThomas Huth #else 545691c60f12SCédric Le Goater 545791c60f12SCédric Le Goater if (ctx->gtse) { 54589f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 545991c60f12SCédric Le Goater } else { 54609f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 546191c60f12SCédric Le Goater } 5462fcf5ef2aSThomas Huth 5463fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5464fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5465fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5466fcf5ef2aSThomas Huth } 5467fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5468fcf5ef2aSThomas Huth } 5469fcf5ef2aSThomas Huth 5470fcf5ef2aSThomas Huth /*** External control ***/ 5471fcf5ef2aSThomas Huth /* Optional: */ 5472fcf5ef2aSThomas Huth 5473fcf5ef2aSThomas Huth /* eciwx */ 5474fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5475fcf5ef2aSThomas Huth { 5476fcf5ef2aSThomas Huth TCGv t0; 5477fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5478fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5479fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5480fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5481c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5482c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5483fcf5ef2aSThomas Huth tcg_temp_free(t0); 5484fcf5ef2aSThomas Huth } 5485fcf5ef2aSThomas Huth 5486fcf5ef2aSThomas Huth /* ecowx */ 5487fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5488fcf5ef2aSThomas Huth { 5489fcf5ef2aSThomas Huth TCGv t0; 5490fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5491fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5492fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5493fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5494c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5495c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5496fcf5ef2aSThomas Huth tcg_temp_free(t0); 5497fcf5ef2aSThomas Huth } 5498fcf5ef2aSThomas Huth 5499fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5500fcf5ef2aSThomas Huth 5501fcf5ef2aSThomas Huth /* tlbld */ 5502fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5503fcf5ef2aSThomas Huth { 5504fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55059f0cf041SMatheus Ferst GEN_PRIV(ctx); 5506fcf5ef2aSThomas Huth #else 55079f0cf041SMatheus Ferst CHK_SV(ctx); 5508fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5509fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5510fcf5ef2aSThomas Huth } 5511fcf5ef2aSThomas Huth 5512fcf5ef2aSThomas Huth /* tlbli */ 5513fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5514fcf5ef2aSThomas Huth { 5515fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55169f0cf041SMatheus Ferst GEN_PRIV(ctx); 5517fcf5ef2aSThomas Huth #else 55189f0cf041SMatheus Ferst CHK_SV(ctx); 5519fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5520fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5521fcf5ef2aSThomas Huth } 5522fcf5ef2aSThomas Huth 5523fcf5ef2aSThomas Huth /* BookE specific instructions */ 5524fcf5ef2aSThomas Huth 5525fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5526fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5527fcf5ef2aSThomas Huth { 5528fcf5ef2aSThomas Huth /* XXX: TODO */ 5529fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5530fcf5ef2aSThomas Huth } 5531fcf5ef2aSThomas Huth 5532fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5533fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5534fcf5ef2aSThomas Huth { 5535fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 55369f0cf041SMatheus Ferst GEN_PRIV(ctx); 5537fcf5ef2aSThomas Huth #else 5538fcf5ef2aSThomas Huth TCGv t0; 5539fcf5ef2aSThomas Huth 55409f0cf041SMatheus Ferst CHK_SV(ctx); 5541fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5542fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5543fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5544fcf5ef2aSThomas Huth tcg_temp_free(t0); 5545fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5546fcf5ef2aSThomas Huth } 5547fcf5ef2aSThomas Huth 5548fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5549fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5550fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5551fcf5ef2aSThomas Huth { 5552fcf5ef2aSThomas Huth TCGv t0, t1; 5553fcf5ef2aSThomas Huth 5554fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5555fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5556fcf5ef2aSThomas Huth 5557fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5558fcf5ef2aSThomas Huth case 0x05: 5559fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5560fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5561fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5562fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5563fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5564fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5565fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5566fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5567fcf5ef2aSThomas Huth break; 5568fcf5ef2aSThomas Huth case 0x04: 5569fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5570fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5571fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5572fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5573fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5574fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5575fcf5ef2aSThomas Huth break; 5576fcf5ef2aSThomas Huth case 0x01: 5577fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5578fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5579fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5580fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5581fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5582fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5583fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5584fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5585fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5586fcf5ef2aSThomas Huth break; 5587fcf5ef2aSThomas Huth case 0x00: 5588fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5589fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5590fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5591fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5592fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5593fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5594fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5595fcf5ef2aSThomas Huth break; 5596fcf5ef2aSThomas Huth case 0x0D: 5597fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5598fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5599fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5600fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5601fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5602fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5603fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5604fcf5ef2aSThomas Huth break; 5605fcf5ef2aSThomas Huth case 0x0C: 5606fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5607fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5608fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5609fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5610fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5611fcf5ef2aSThomas Huth break; 5612fcf5ef2aSThomas Huth } 5613fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5614fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5615fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5616fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5617fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5618fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5619fcf5ef2aSThomas Huth } else { 5620fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5621fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5622fcf5ef2aSThomas Huth } 5623fcf5ef2aSThomas Huth 5624fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5625fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5626fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5627fcf5ef2aSThomas Huth 5628fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5629fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5630fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5631fcf5ef2aSThomas Huth } 5632fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5633fcf5ef2aSThomas Huth /* Signed */ 5634fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5635fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5636fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5637fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5638fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5639fcf5ef2aSThomas Huth /* Saturate */ 5640fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5641fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5642fcf5ef2aSThomas Huth } 5643fcf5ef2aSThomas Huth } else { 5644fcf5ef2aSThomas Huth /* Unsigned */ 5645fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5646fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5647fcf5ef2aSThomas Huth /* Saturate */ 5648fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5649fcf5ef2aSThomas Huth } 5650fcf5ef2aSThomas Huth } 5651fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5652fcf5ef2aSThomas Huth /* Check overflow */ 5653fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5654fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5655fcf5ef2aSThomas Huth } 5656fcf5ef2aSThomas Huth gen_set_label(l1); 5657fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5658fcf5ef2aSThomas Huth } 5659fcf5ef2aSThomas Huth } else { 5660fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5661fcf5ef2aSThomas Huth } 5662fcf5ef2aSThomas Huth tcg_temp_free(t0); 5663fcf5ef2aSThomas Huth tcg_temp_free(t1); 5664fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5665fcf5ef2aSThomas Huth /* Update Rc0 */ 5666fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5667fcf5ef2aSThomas Huth } 5668fcf5ef2aSThomas Huth } 5669fcf5ef2aSThomas Huth 5670fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5671fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5672fcf5ef2aSThomas Huth { \ 5673fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5674fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5675fcf5ef2aSThomas Huth } 5676fcf5ef2aSThomas Huth 5677fcf5ef2aSThomas Huth /* macchw - macchw. */ 5678fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5679fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5680fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5681fcf5ef2aSThomas Huth /* macchws - macchws. */ 5682fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5683fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5684fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5685fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5686fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5687fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5688fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5689fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5690fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5691fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5692fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5693fcf5ef2aSThomas Huth /* machhw - machhw. */ 5694fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5695fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5696fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5697fcf5ef2aSThomas Huth /* machhws - machhws. */ 5698fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5699fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5700fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5701fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5702fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5703fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5704fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5705fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5706fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5707fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5708fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5709fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5710fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5711fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5712fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5713fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5714fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5715fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5716fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5717fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5718fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5719fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5720fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5721fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5722fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5723fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5724fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5725fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5726fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5727fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5728fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5729fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5730fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5731fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5732fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5733fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5734fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5735fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5736fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5737fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5738fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5739fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5740fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5741fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5742fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5743fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5744fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5745fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5746fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5747fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5748fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5749fcf5ef2aSThomas Huth 5750fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5751fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5752fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5753fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5754fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5755fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5756fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5757fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5758fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5759fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5760fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5761fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5762fcf5ef2aSThomas Huth 5763fcf5ef2aSThomas Huth /* mfdcr */ 5764fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5765fcf5ef2aSThomas Huth { 5766fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57679f0cf041SMatheus Ferst GEN_PRIV(ctx); 5768fcf5ef2aSThomas Huth #else 5769fcf5ef2aSThomas Huth TCGv dcrn; 5770fcf5ef2aSThomas Huth 57719f0cf041SMatheus Ferst CHK_SV(ctx); 5772fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5773fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5774fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5775fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5776fcf5ef2aSThomas Huth } 5777fcf5ef2aSThomas Huth 5778fcf5ef2aSThomas Huth /* mtdcr */ 5779fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5780fcf5ef2aSThomas Huth { 5781fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57829f0cf041SMatheus Ferst GEN_PRIV(ctx); 5783fcf5ef2aSThomas Huth #else 5784fcf5ef2aSThomas Huth TCGv dcrn; 5785fcf5ef2aSThomas Huth 57869f0cf041SMatheus Ferst CHK_SV(ctx); 5787fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5788fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5789fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5790fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5791fcf5ef2aSThomas Huth } 5792fcf5ef2aSThomas Huth 5793fcf5ef2aSThomas Huth /* mfdcrx */ 5794fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5795fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5796fcf5ef2aSThomas Huth { 5797fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57989f0cf041SMatheus Ferst GEN_PRIV(ctx); 5799fcf5ef2aSThomas Huth #else 58009f0cf041SMatheus Ferst CHK_SV(ctx); 5801fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5802fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5803fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5804fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5805fcf5ef2aSThomas Huth } 5806fcf5ef2aSThomas Huth 5807fcf5ef2aSThomas Huth /* mtdcrx */ 5808fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5809fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5810fcf5ef2aSThomas Huth { 5811fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58129f0cf041SMatheus Ferst GEN_PRIV(ctx); 5813fcf5ef2aSThomas Huth #else 58149f0cf041SMatheus Ferst CHK_SV(ctx); 5815fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5816fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5817fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5818fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5819fcf5ef2aSThomas Huth } 5820fcf5ef2aSThomas Huth 5821fcf5ef2aSThomas Huth /* dccci */ 5822fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5823fcf5ef2aSThomas Huth { 58249f0cf041SMatheus Ferst CHK_SV(ctx); 5825fcf5ef2aSThomas Huth /* interpreted as no-op */ 5826fcf5ef2aSThomas Huth } 5827fcf5ef2aSThomas Huth 5828fcf5ef2aSThomas Huth /* dcread */ 5829fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5830fcf5ef2aSThomas Huth { 5831fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58329f0cf041SMatheus Ferst GEN_PRIV(ctx); 5833fcf5ef2aSThomas Huth #else 5834fcf5ef2aSThomas Huth TCGv EA, val; 5835fcf5ef2aSThomas Huth 58369f0cf041SMatheus Ferst CHK_SV(ctx); 5837fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5838fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5839fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5840fcf5ef2aSThomas Huth val = tcg_temp_new(); 5841fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5842fcf5ef2aSThomas Huth tcg_temp_free(val); 5843fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5844fcf5ef2aSThomas Huth tcg_temp_free(EA); 5845fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5846fcf5ef2aSThomas Huth } 5847fcf5ef2aSThomas Huth 5848fcf5ef2aSThomas Huth /* icbt */ 5849fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5850fcf5ef2aSThomas Huth { 5851efe843d8SDavid Gibson /* 5852efe843d8SDavid Gibson * interpreted as no-op 5853efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5854efe843d8SDavid Gibson * does not generate any exception 5855fcf5ef2aSThomas Huth */ 5856fcf5ef2aSThomas Huth } 5857fcf5ef2aSThomas Huth 5858fcf5ef2aSThomas Huth /* iccci */ 5859fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5860fcf5ef2aSThomas Huth { 58619f0cf041SMatheus Ferst CHK_SV(ctx); 5862fcf5ef2aSThomas Huth /* interpreted as no-op */ 5863fcf5ef2aSThomas Huth } 5864fcf5ef2aSThomas Huth 5865fcf5ef2aSThomas Huth /* icread */ 5866fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5867fcf5ef2aSThomas Huth { 58689f0cf041SMatheus Ferst CHK_SV(ctx); 5869fcf5ef2aSThomas Huth /* interpreted as no-op */ 5870fcf5ef2aSThomas Huth } 5871fcf5ef2aSThomas Huth 5872fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5873fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5874fcf5ef2aSThomas Huth { 5875fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58769f0cf041SMatheus Ferst GEN_PRIV(ctx); 5877fcf5ef2aSThomas Huth #else 58789f0cf041SMatheus Ferst CHK_SV(ctx); 5879fcf5ef2aSThomas Huth /* Restore CPU state */ 5880fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 588159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5882fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5883fcf5ef2aSThomas Huth } 5884fcf5ef2aSThomas Huth 5885fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5886fcf5ef2aSThomas Huth { 5887fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58889f0cf041SMatheus Ferst GEN_PRIV(ctx); 5889fcf5ef2aSThomas Huth #else 58909f0cf041SMatheus Ferst CHK_SV(ctx); 5891fcf5ef2aSThomas Huth /* Restore CPU state */ 5892fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 589359bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5894fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5895fcf5ef2aSThomas Huth } 5896fcf5ef2aSThomas Huth 5897fcf5ef2aSThomas Huth /* BookE specific */ 5898fcf5ef2aSThomas Huth 5899fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5900fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5901fcf5ef2aSThomas Huth { 5902fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59039f0cf041SMatheus Ferst GEN_PRIV(ctx); 5904fcf5ef2aSThomas Huth #else 59059f0cf041SMatheus Ferst CHK_SV(ctx); 5906fcf5ef2aSThomas Huth /* Restore CPU state */ 5907fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 590859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5909fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5910fcf5ef2aSThomas Huth } 5911fcf5ef2aSThomas Huth 5912fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5913fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5914fcf5ef2aSThomas Huth { 5915fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59169f0cf041SMatheus Ferst GEN_PRIV(ctx); 5917fcf5ef2aSThomas Huth #else 59189f0cf041SMatheus Ferst CHK_SV(ctx); 5919fcf5ef2aSThomas Huth /* Restore CPU state */ 5920fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 592159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5922fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5923fcf5ef2aSThomas Huth } 5924fcf5ef2aSThomas Huth 5925fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5926fcf5ef2aSThomas Huth 5927fcf5ef2aSThomas Huth /* tlbre */ 5928fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5929fcf5ef2aSThomas Huth { 5930fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59319f0cf041SMatheus Ferst GEN_PRIV(ctx); 5932fcf5ef2aSThomas Huth #else 59339f0cf041SMatheus Ferst CHK_SV(ctx); 5934fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5935fcf5ef2aSThomas Huth case 0: 5936fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5937fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5938fcf5ef2aSThomas Huth break; 5939fcf5ef2aSThomas Huth case 1: 5940fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5941fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5942fcf5ef2aSThomas Huth break; 5943fcf5ef2aSThomas Huth default: 5944fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5945fcf5ef2aSThomas Huth break; 5946fcf5ef2aSThomas Huth } 5947fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5948fcf5ef2aSThomas Huth } 5949fcf5ef2aSThomas Huth 5950fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5951fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5952fcf5ef2aSThomas Huth { 5953fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59549f0cf041SMatheus Ferst GEN_PRIV(ctx); 5955fcf5ef2aSThomas Huth #else 5956fcf5ef2aSThomas Huth TCGv t0; 5957fcf5ef2aSThomas Huth 59589f0cf041SMatheus Ferst CHK_SV(ctx); 5959fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5960fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5961fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5962fcf5ef2aSThomas Huth tcg_temp_free(t0); 5963fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5964fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5965fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5966fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5967fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5968fcf5ef2aSThomas Huth gen_set_label(l1); 5969fcf5ef2aSThomas Huth } 5970fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5971fcf5ef2aSThomas Huth } 5972fcf5ef2aSThomas Huth 5973fcf5ef2aSThomas Huth /* tlbwe */ 5974fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5975fcf5ef2aSThomas Huth { 5976fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59779f0cf041SMatheus Ferst GEN_PRIV(ctx); 5978fcf5ef2aSThomas Huth #else 59799f0cf041SMatheus Ferst CHK_SV(ctx); 5980fcf5ef2aSThomas Huth 5981fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5982fcf5ef2aSThomas Huth case 0: 5983fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5984fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5985fcf5ef2aSThomas Huth break; 5986fcf5ef2aSThomas Huth case 1: 5987fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5988fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5989fcf5ef2aSThomas Huth break; 5990fcf5ef2aSThomas Huth default: 5991fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5992fcf5ef2aSThomas Huth break; 5993fcf5ef2aSThomas Huth } 5994fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5995fcf5ef2aSThomas Huth } 5996fcf5ef2aSThomas Huth 5997fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5998fcf5ef2aSThomas Huth 5999fcf5ef2aSThomas Huth /* tlbre */ 6000fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6001fcf5ef2aSThomas Huth { 6002fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60039f0cf041SMatheus Ferst GEN_PRIV(ctx); 6004fcf5ef2aSThomas Huth #else 60059f0cf041SMatheus Ferst CHK_SV(ctx); 6006fcf5ef2aSThomas Huth 6007fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6008fcf5ef2aSThomas Huth case 0: 6009fcf5ef2aSThomas Huth case 1: 6010fcf5ef2aSThomas Huth case 2: 6011fcf5ef2aSThomas Huth { 6012fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6013fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6014fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6015fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6016fcf5ef2aSThomas Huth } 6017fcf5ef2aSThomas Huth break; 6018fcf5ef2aSThomas Huth default: 6019fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6020fcf5ef2aSThomas Huth break; 6021fcf5ef2aSThomas Huth } 6022fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6023fcf5ef2aSThomas Huth } 6024fcf5ef2aSThomas Huth 6025fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6026fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6027fcf5ef2aSThomas Huth { 6028fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60299f0cf041SMatheus Ferst GEN_PRIV(ctx); 6030fcf5ef2aSThomas Huth #else 6031fcf5ef2aSThomas Huth TCGv t0; 6032fcf5ef2aSThomas Huth 60339f0cf041SMatheus Ferst CHK_SV(ctx); 6034fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6035fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6036fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6037fcf5ef2aSThomas Huth tcg_temp_free(t0); 6038fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6039fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6040fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6041fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6042fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6043fcf5ef2aSThomas Huth gen_set_label(l1); 6044fcf5ef2aSThomas Huth } 6045fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6046fcf5ef2aSThomas Huth } 6047fcf5ef2aSThomas Huth 6048fcf5ef2aSThomas Huth /* tlbwe */ 6049fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6050fcf5ef2aSThomas Huth { 6051fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60529f0cf041SMatheus Ferst GEN_PRIV(ctx); 6053fcf5ef2aSThomas Huth #else 60549f0cf041SMatheus Ferst CHK_SV(ctx); 6055fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6056fcf5ef2aSThomas Huth case 0: 6057fcf5ef2aSThomas Huth case 1: 6058fcf5ef2aSThomas Huth case 2: 6059fcf5ef2aSThomas Huth { 6060fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6061fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6062fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6063fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6064fcf5ef2aSThomas Huth } 6065fcf5ef2aSThomas Huth break; 6066fcf5ef2aSThomas Huth default: 6067fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6068fcf5ef2aSThomas Huth break; 6069fcf5ef2aSThomas Huth } 6070fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6071fcf5ef2aSThomas Huth } 6072fcf5ef2aSThomas Huth 6073fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6074fcf5ef2aSThomas Huth 6075fcf5ef2aSThomas Huth /* tlbre */ 6076fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6077fcf5ef2aSThomas Huth { 6078fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60799f0cf041SMatheus Ferst GEN_PRIV(ctx); 6080fcf5ef2aSThomas Huth #else 60819f0cf041SMatheus Ferst CHK_SV(ctx); 6082fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6083fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6084fcf5ef2aSThomas Huth } 6085fcf5ef2aSThomas Huth 6086fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6087fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6088fcf5ef2aSThomas Huth { 6089fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60909f0cf041SMatheus Ferst GEN_PRIV(ctx); 6091fcf5ef2aSThomas Huth #else 6092fcf5ef2aSThomas Huth TCGv t0; 6093fcf5ef2aSThomas Huth 60949f0cf041SMatheus Ferst CHK_SV(ctx); 6095fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6096fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6097fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6098fcf5ef2aSThomas Huth } else { 6099fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6100fcf5ef2aSThomas Huth } 6101fcf5ef2aSThomas Huth 6102fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6103fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6104fcf5ef2aSThomas Huth tcg_temp_free(t0); 6105fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6106fcf5ef2aSThomas Huth } 6107fcf5ef2aSThomas Huth 6108fcf5ef2aSThomas Huth /* tlbwe */ 6109fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6110fcf5ef2aSThomas Huth { 6111fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61129f0cf041SMatheus Ferst GEN_PRIV(ctx); 6113fcf5ef2aSThomas Huth #else 61149f0cf041SMatheus Ferst CHK_SV(ctx); 6115fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6116fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6117fcf5ef2aSThomas Huth } 6118fcf5ef2aSThomas Huth 6119fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6120fcf5ef2aSThomas Huth { 6121fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61229f0cf041SMatheus Ferst GEN_PRIV(ctx); 6123fcf5ef2aSThomas Huth #else 6124fcf5ef2aSThomas Huth TCGv t0; 6125fcf5ef2aSThomas Huth 61269f0cf041SMatheus Ferst CHK_SV(ctx); 6127fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6128fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6129fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6130fcf5ef2aSThomas Huth tcg_temp_free(t0); 6131fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6132fcf5ef2aSThomas Huth } 6133fcf5ef2aSThomas Huth 6134fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6135fcf5ef2aSThomas Huth { 6136fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61379f0cf041SMatheus Ferst GEN_PRIV(ctx); 6138fcf5ef2aSThomas Huth #else 6139fcf5ef2aSThomas Huth TCGv t0; 6140fcf5ef2aSThomas Huth 61419f0cf041SMatheus Ferst CHK_SV(ctx); 6142fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6143fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6144fcf5ef2aSThomas Huth 6145fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 6146fcf5ef2aSThomas Huth case 0: 6147fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6148fcf5ef2aSThomas Huth break; 6149fcf5ef2aSThomas Huth case 1: 6150fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6151fcf5ef2aSThomas Huth break; 6152fcf5ef2aSThomas Huth case 3: 6153fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6154fcf5ef2aSThomas Huth break; 6155fcf5ef2aSThomas Huth default: 6156fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6157fcf5ef2aSThomas Huth break; 6158fcf5ef2aSThomas Huth } 6159fcf5ef2aSThomas Huth 6160fcf5ef2aSThomas Huth tcg_temp_free(t0); 6161fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6162fcf5ef2aSThomas Huth } 6163fcf5ef2aSThomas Huth 6164fcf5ef2aSThomas Huth 6165fcf5ef2aSThomas Huth /* wrtee */ 6166fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6167fcf5ef2aSThomas Huth { 6168fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61699f0cf041SMatheus Ferst GEN_PRIV(ctx); 6170fcf5ef2aSThomas Huth #else 6171fcf5ef2aSThomas Huth TCGv t0; 6172fcf5ef2aSThomas Huth 61739f0cf041SMatheus Ferst CHK_SV(ctx); 6174fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6175fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6176fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6177fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6178fcf5ef2aSThomas Huth tcg_temp_free(t0); 6179efe843d8SDavid Gibson /* 6180efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6181efe843d8SDavid Gibson * just set msr_ee to 1 6182fcf5ef2aSThomas Huth */ 6183d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6184fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6185fcf5ef2aSThomas Huth } 6186fcf5ef2aSThomas Huth 6187fcf5ef2aSThomas Huth /* wrteei */ 6188fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6189fcf5ef2aSThomas Huth { 6190fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 61919f0cf041SMatheus Ferst GEN_PRIV(ctx); 6192fcf5ef2aSThomas Huth #else 61939f0cf041SMatheus Ferst CHK_SV(ctx); 6194fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6195fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6196fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6197d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6198fcf5ef2aSThomas Huth } else { 6199fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6200fcf5ef2aSThomas Huth } 6201fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6202fcf5ef2aSThomas Huth } 6203fcf5ef2aSThomas Huth 6204fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6205fcf5ef2aSThomas Huth 6206fcf5ef2aSThomas Huth /* dlmzb */ 6207fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6208fcf5ef2aSThomas Huth { 6209fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6210fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6211fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6212fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6213fcf5ef2aSThomas Huth } 6214fcf5ef2aSThomas Huth 6215fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6216fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6217fcf5ef2aSThomas Huth { 6218fcf5ef2aSThomas Huth /* interpreted as no-op */ 6219fcf5ef2aSThomas Huth } 6220fcf5ef2aSThomas Huth 6221fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6222fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6223fcf5ef2aSThomas Huth { 622427a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 622527a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 622627a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 622727a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 622827a3ea7eSBALATON Zoltan } 622927a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6230fcf5ef2aSThomas Huth } 6231fcf5ef2aSThomas Huth 6232fcf5ef2aSThomas Huth /* icbt */ 6233fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6234fcf5ef2aSThomas Huth { 6235efe843d8SDavid Gibson /* 6236efe843d8SDavid Gibson * interpreted as no-op 6237efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6238efe843d8SDavid Gibson * does not generate any exception 6239fcf5ef2aSThomas Huth */ 6240fcf5ef2aSThomas Huth } 6241fcf5ef2aSThomas Huth 6242fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6243fcf5ef2aSThomas Huth 6244fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6245fcf5ef2aSThomas Huth { 6246fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 62479f0cf041SMatheus Ferst GEN_PRIV(ctx); 6248fcf5ef2aSThomas Huth #else 62499f0cf041SMatheus Ferst CHK_HV(ctx); 6250d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 62517af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 62527af1e7b0SCédric Le Goater } else { 6253fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 62547af1e7b0SCédric Le Goater } 6255fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6256fcf5ef2aSThomas Huth } 6257fcf5ef2aSThomas Huth 6258fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6259fcf5ef2aSThomas Huth { 6260fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 62619f0cf041SMatheus Ferst GEN_PRIV(ctx); 6262fcf5ef2aSThomas Huth #else 62639f0cf041SMatheus Ferst CHK_HV(ctx); 6264d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 62657af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 62667af1e7b0SCédric Le Goater } else { 6267fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 62687af1e7b0SCédric Le Goater } 6269fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6270fcf5ef2aSThomas Huth } 6271fcf5ef2aSThomas Huth 62725ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 62735ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 62745ba7ba1dSCédric Le Goater { 62755ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 62769f0cf041SMatheus Ferst GEN_PRIV(ctx); 62775ba7ba1dSCédric Le Goater #else 62789f0cf041SMatheus Ferst CHK_SV(ctx); 62795ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 62805ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 62815ba7ba1dSCédric Le Goater } 62825ba7ba1dSCédric Le Goater 62835ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 62845ba7ba1dSCédric Le Goater { 62855ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 62869f0cf041SMatheus Ferst GEN_PRIV(ctx); 62875ba7ba1dSCédric Le Goater #else 62889f0cf041SMatheus Ferst CHK_SV(ctx); 62895ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 62905ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 62915ba7ba1dSCédric Le Goater } 62925ba7ba1dSCédric Le Goater #endif 62935ba7ba1dSCédric Le Goater 62947af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 62957af1e7b0SCédric Le Goater { 62967af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 62979f0cf041SMatheus Ferst GEN_PRIV(ctx); 62987af1e7b0SCédric Le Goater #else 62999f0cf041SMatheus Ferst CHK_HV(ctx); 63007af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 63017af1e7b0SCédric Le Goater /* interpreted as no-op */ 63027af1e7b0SCédric Le Goater } 6303fcf5ef2aSThomas Huth 6304fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6305fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6306fcf5ef2aSThomas Huth { 6307fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6308fcf5ef2aSThomas Huth 6309fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6310fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6311fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6312fcf5ef2aSThomas Huth } 6313fcf5ef2aSThomas Huth 6314fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6315fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6316fcf5ef2aSThomas Huth { 6317fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6318fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6319fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6320fcf5ef2aSThomas Huth 6321fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6322fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6323fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6324fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6325fcf5ef2aSThomas Huth } else { 6326fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6327fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6328fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6329fcf5ef2aSThomas Huth } 6330fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6331fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6332fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6333fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6334fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6335fcf5ef2aSThomas Huth } 6336fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6337fcf5ef2aSThomas Huth 6338fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6339fcf5ef2aSThomas Huth { 6340fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6341fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6342fcf5ef2aSThomas Huth return; 6343fcf5ef2aSThomas Huth } 6344fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6345fcf5ef2aSThomas Huth } 6346fcf5ef2aSThomas Huth 6347fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6348fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6349fcf5ef2aSThomas Huth { \ 6350fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6351fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6352fcf5ef2aSThomas Huth return; \ 6353fcf5ef2aSThomas Huth } \ 6354efe843d8SDavid Gibson /* \ 6355efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6356fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6357fcf5ef2aSThomas Huth * \ 6358fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6359fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6360fcf5ef2aSThomas Huth */ \ 6361fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6362fcf5ef2aSThomas Huth } 6363fcf5ef2aSThomas Huth 6364fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6365fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6366fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6367fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6368fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6369fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6370fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6371efe843d8SDavid Gibson 6372b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6373b8b4576eSSuraj Jitindar Singh { 6374efe843d8SDavid Gibson /* Do Nothing */ 6375b8b4576eSSuraj Jitindar Singh } 6376fcf5ef2aSThomas Huth 637780b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 637880b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 637980b8c1eeSNikunj A Dadhania { \ 6380efe843d8SDavid Gibson /* \ 6381efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6382efe843d8SDavid Gibson * implementation of the copy paste facility \ 638380b8c1eeSNikunj A Dadhania */ \ 638480b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 638580b8c1eeSNikunj A Dadhania } 638680b8c1eeSNikunj A Dadhania 638780b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 638880b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 638980b8c1eeSNikunj A Dadhania 6390fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6391fcf5ef2aSThomas Huth { 6392fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6393fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6394fcf5ef2aSThomas Huth return; 6395fcf5ef2aSThomas Huth } 6396efe843d8SDavid Gibson /* 6397efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6398efe843d8SDavid Gibson * simple: 6399fcf5ef2aSThomas Huth * 6400fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6401fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6402fcf5ef2aSThomas Huth */ 6403fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6404fcf5ef2aSThomas Huth } 6405fcf5ef2aSThomas Huth 6406fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6407fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6408fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6409fcf5ef2aSThomas Huth { \ 64109f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6411fcf5ef2aSThomas Huth } 6412fcf5ef2aSThomas Huth 6413fcf5ef2aSThomas Huth #else 6414fcf5ef2aSThomas Huth 6415fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6416fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6417fcf5ef2aSThomas Huth { \ 64189f0cf041SMatheus Ferst CHK_SV(ctx); \ 6419fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6420fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6421fcf5ef2aSThomas Huth return; \ 6422fcf5ef2aSThomas Huth } \ 6423efe843d8SDavid Gibson /* \ 6424efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6425fcf5ef2aSThomas Huth * simple: \ 6426fcf5ef2aSThomas Huth * \ 6427fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6428fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6429fcf5ef2aSThomas Huth */ \ 6430fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6431fcf5ef2aSThomas Huth } 6432fcf5ef2aSThomas Huth 6433fcf5ef2aSThomas Huth #endif 6434fcf5ef2aSThomas Huth 6435fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6436fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6437fcf5ef2aSThomas Huth 64381a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 64391a404c91SMark Cave-Ayland { 6440e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 64411a404c91SMark Cave-Ayland } 64421a404c91SMark Cave-Ayland 64431a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 64441a404c91SMark Cave-Ayland { 6445e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 64461a404c91SMark Cave-Ayland } 64471a404c91SMark Cave-Ayland 6448c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6449c4a18dbfSMark Cave-Ayland { 645037da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6451c4a18dbfSMark Cave-Ayland } 6452c4a18dbfSMark Cave-Ayland 6453c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6454c4a18dbfSMark Cave-Ayland { 645537da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6456c4a18dbfSMark Cave-Ayland } 6457c4a18dbfSMark Cave-Ayland 6458c9826ae9SRichard Henderson /* 6459f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6460f2aabda8SRichard Henderson */ 6461d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6462d39b2cc7SLuis Pires { 6463d39b2cc7SLuis Pires return x * 2; 6464d39b2cc7SLuis Pires } 6465d39b2cc7SLuis Pires 6466f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6467f2aabda8SRichard Henderson { 6468f2aabda8SRichard Henderson return x * 4; 6469f2aabda8SRichard Henderson } 6470f2aabda8SRichard Henderson 6471e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6472e10271e1SMatheus Ferst { 6473e10271e1SMatheus Ferst return x * 16; 6474e10271e1SMatheus Ferst } 6475e10271e1SMatheus Ferst 6476f2aabda8SRichard Henderson /* 6477c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6478c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6479c9826ae9SRichard Henderson * proper variable. 6480c9826ae9SRichard Henderson */ 6481c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6482c9826ae9SRichard Henderson do { \ 6483c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6484c9826ae9SRichard Henderson return false; \ 6485c9826ae9SRichard Henderson } \ 6486c9826ae9SRichard Henderson } while (0) 6487c9826ae9SRichard Henderson 6488c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6489c9826ae9SRichard Henderson do { \ 6490c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6491c9826ae9SRichard Henderson return false; \ 6492c9826ae9SRichard Henderson } \ 6493c9826ae9SRichard Henderson } while (0) 6494c9826ae9SRichard Henderson 6495c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6496c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6497c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6498c9826ae9SRichard Henderson #else 6499c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6500c9826ae9SRichard Henderson #endif 6501c9826ae9SRichard Henderson 6502e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6503e2205a46SBruno Larsen do { \ 6504e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6505e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6506e2205a46SBruno Larsen return true; \ 6507e2205a46SBruno Larsen } \ 6508e2205a46SBruno Larsen } while (0) 6509e2205a46SBruno Larsen 65108226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 65118226cb2dSBruno Larsen (billionai) do { \ 65128226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 65138226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 65148226cb2dSBruno Larsen (billionai) return true; \ 65158226cb2dSBruno Larsen (billionai) } \ 65168226cb2dSBruno Larsen (billionai) } while (0) 65178226cb2dSBruno Larsen (billionai) 651886057426SFernando Valle #define REQUIRE_FPU(ctx) \ 651986057426SFernando Valle do { \ 652086057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 652186057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 652286057426SFernando Valle return true; \ 652386057426SFernando Valle } \ 652486057426SFernando Valle } while (0) 652586057426SFernando Valle 6526fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6527fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6528fc34e81aSMatheus Ferst do { \ 6529fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6530fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6531fc34e81aSMatheus Ferst return true; \ 6532fc34e81aSMatheus Ferst } \ 6533fc34e81aSMatheus Ferst } while (0) 6534fc34e81aSMatheus Ferst 6535fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6536fc34e81aSMatheus Ferst do { \ 6537fc34e81aSMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) \ 6538fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6539fc34e81aSMatheus Ferst return true; \ 6540fc34e81aSMatheus Ferst } \ 6541fc34e81aSMatheus Ferst } while (0) 6542fc34e81aSMatheus Ferst #else 6543fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6544fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6545fc34e81aSMatheus Ferst #endif 6546fc34e81aSMatheus Ferst 6547f2aabda8SRichard Henderson /* 6548f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6549f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6550f2aabda8SRichard Henderson */ 6551f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6552f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6553f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 655419f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 655519f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 655619f0862dSLuis Pires { \ 655719f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 655819f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 655919f0862dSLuis Pires } 656019f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 656119f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 656219f0862dSLuis Pires { \ 656319f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 656419f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 656519f0862dSLuis Pires } 6566f2aabda8SRichard Henderson 6567f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6568f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6569f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 657019f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 657119f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 657219f0862dSLuis Pires { \ 657319f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 657419f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 657519f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 657619f0862dSLuis Pires } 6577f2aabda8SRichard Henderson 6578f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6579f2aabda8SRichard Henderson 6580f2aabda8SRichard Henderson 658199082815SRichard Henderson #include "decode-insn32.c.inc" 658299082815SRichard Henderson #include "decode-insn64.c.inc" 6583565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6584565cb109SGustavo Romero 6585725b2d4dSFernando Eckhardt Valle /* 6586725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6587725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6588725b2d4dSFernando Eckhardt Valle */ 6589725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6590725b2d4dSFernando Eckhardt Valle { 6591725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6592725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6593725b2d4dSFernando Eckhardt Valle d->si = a->si; 6594725b2d4dSFernando Eckhardt Valle if (a->r) { 6595725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6596725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6597725b2d4dSFernando Eckhardt Valle return false; 6598725b2d4dSFernando Eckhardt Valle } 6599725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6600725b2d4dSFernando Eckhardt Valle } 6601725b2d4dSFernando Eckhardt Valle return true; 6602725b2d4dSFernando Eckhardt Valle } 6603725b2d4dSFernando Eckhardt Valle 660499082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 660599082815SRichard Henderson 6606139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6607fcf5ef2aSThomas Huth 6608139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6609fcf5ef2aSThomas Huth 6610139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6611fcf5ef2aSThomas Huth 6612139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6613fcf5ef2aSThomas Huth 6614139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6615fcf5ef2aSThomas Huth 66161f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 66171f26c751SDaniel Henrique Barboza 6618016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6619016b6e1dSLeandro Lupori 662020e2d04eSLeandro Lupori /* Handles lfdp */ 66215cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 66225cb091a4SNikunj A Dadhania { 662320e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 66245cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 66255cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 66265cb091a4SNikunj A Dadhania } 66275cb091a4SNikunj A Dadhania } 66285cb091a4SNikunj A Dadhania return gen_invalid(ctx); 66295cb091a4SNikunj A Dadhania } 66305cb091a4SNikunj A Dadhania 663120e2d04eSLeandro Lupori /* Handles stfdp */ 6632e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6633e3001664SNikunj A Dadhania { 663420e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 663520e2d04eSLeandro Lupori /* stfdp */ 6636e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6637e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6638e3001664SNikunj A Dadhania } 6639e3001664SNikunj A Dadhania } 6640e3001664SNikunj A Dadhania return gen_invalid(ctx); 6641e3001664SNikunj A Dadhania } 6642e3001664SNikunj A Dadhania 66439d69cfa2SLijun Pan #if defined(TARGET_PPC64) 66449d69cfa2SLijun Pan /* brd */ 66459d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 66469d69cfa2SLijun Pan { 66479d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 66489d69cfa2SLijun Pan } 66499d69cfa2SLijun Pan 66509d69cfa2SLijun Pan /* brw */ 66519d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 66529d69cfa2SLijun Pan { 66539d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 66549d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 66559d69cfa2SLijun Pan 66569d69cfa2SLijun Pan } 66579d69cfa2SLijun Pan 66589d69cfa2SLijun Pan /* brh */ 66599d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 66609d69cfa2SLijun Pan { 6661491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 66629d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 66639d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 66649d69cfa2SLijun Pan 66659d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6666491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6667491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 66689d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 66699d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 66709d69cfa2SLijun Pan 66719d69cfa2SLijun Pan tcg_temp_free_i64(t1); 66729d69cfa2SLijun Pan tcg_temp_free_i64(t2); 66739d69cfa2SLijun Pan } 66749d69cfa2SLijun Pan #endif 66759d69cfa2SLijun Pan 6676fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 66779d69cfa2SLijun Pan #if defined(TARGET_PPC64) 66789d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 66799d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 66809d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 66819d69cfa2SLijun Pan #endif 6682fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6683fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6684fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6685fcf5ef2aSThomas Huth #endif 6686fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6687fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6688fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6689fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6690fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6691fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6692fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6693fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6694fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6695fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6696fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6697fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6698fcf5ef2aSThomas Huth #endif 6699fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6700fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6701fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6702fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6703fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6704fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6705fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 670680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6707b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 670880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6709fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6710fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6711fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6712fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6713fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6714fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6715fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6716fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6717fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6718fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6719fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6720fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6721fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6722fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6723fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6724fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6725fcf5ef2aSThomas Huth #endif 6726fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6727fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6728fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6729fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6730fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6731fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6732fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6733fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6734fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6735fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6736fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6737fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6738fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6739fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6740fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6741fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6742fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6743fcf5ef2aSThomas Huth #endif 67445cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 67455cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 674672b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6747e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6748fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6749fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6750fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6751fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6752fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6753fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6754c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6755fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6756fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6757fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6758fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6759a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6760a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6761fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6762fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6763fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6764fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6765a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6766a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6767fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6768fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6769fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6770fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6771fcf5ef2aSThomas Huth #endif 6772fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 67730c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 67740c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 67750c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6776fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6777fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6778fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6779fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6780fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6781fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6782fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6783fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6784fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 67853c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 67863c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 67873c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 67883c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 67893c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 67903c89b8d6SNicholas Piggin #endif 6791cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6792fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6793fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6794fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6795fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6796fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6797fcf5ef2aSThomas Huth #endif 67983c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 67993c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 68003c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6801fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6802fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6803fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6804fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6805fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6806fcf5ef2aSThomas Huth #endif 6807fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6808fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6809fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6810fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6811fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6812fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6813fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6814fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6815fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6816b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6817fcf5ef2aSThomas Huth #endif 6818fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6819fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6820fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 682150728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6822fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6823fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 682450728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6825fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 682650728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6827fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 682850728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6829fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6830fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 683150728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6832fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 683399d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6834fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6835fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 683650728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6837fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6838fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6839fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6840fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6841fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6842fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6843fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6844fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6845fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6846fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6847fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6848fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6849fcf5ef2aSThomas Huth #endif 6850fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6851efe843d8SDavid Gibson /* 6852efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6853efe843d8SDavid Gibson * different ISA versions 6854efe843d8SDavid Gibson */ 6855fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6856fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6857fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6858fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6859fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6860fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6861fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6862fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6863fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6864fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6865fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6866fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6867fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6868fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6869fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6870fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6871fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6872fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6873fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6874fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6875fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6876fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6877fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6878fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6879fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6880fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6881fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6882fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6883fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6884fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6885fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6886fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6887fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6888fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6889fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6890fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6891fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6892fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6893fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6894fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 68957af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 68967af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 6897fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6898fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6899fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6900fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6901fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 690227a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6903fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6904fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 69050c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 69060c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6907fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6908fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6909fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6910fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6911fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6912fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6913fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6914fcf5ef2aSThomas Huth PPC2_ISA300), 6915fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 69165ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 69175ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 69185ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 69195ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 6920fcf5ef2aSThomas Huth #endif 6921fcf5ef2aSThomas Huth 6922fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6923fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6924fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6925fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6926fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6927fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6928fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6929fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6930fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6931fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6932fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6933fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6934fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6935fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6936fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 69374c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6938fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6939fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6940fcf5ef2aSThomas Huth 6941fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6942fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6943fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6944fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6945fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6946fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6947fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6948fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6949fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6950fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6951fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6952fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6953fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6954fcf5ef2aSThomas Huth 6955fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6956fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6957fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6958fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6959fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6960fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6961fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6962fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6963fcf5ef2aSThomas Huth 6964fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6965fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6966fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6967fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6968fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6969fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6970fcf5ef2aSThomas Huth 6971fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6972fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6973fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6974fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6975fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6976fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6977fcf5ef2aSThomas Huth #endif 6978fcf5ef2aSThomas Huth 6979fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6980fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6981fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6982fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6983fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6984fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6985fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6986fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6987fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6988fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6989fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6990fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6991fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6992fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6993fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6994fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6995fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6996fcf5ef2aSThomas Huth 6997fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6998fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6999fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7000fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7001fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7002fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7003fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7004fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7005fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7006fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7007fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7008fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7009fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7010fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7011fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7012fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7013fcf5ef2aSThomas Huth #endif 7014fcf5ef2aSThomas Huth 7015fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7016fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7017fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7018fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7019fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7020fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7021fcf5ef2aSThomas Huth PPC_64B) 7022fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7023fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7024fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7025fcf5ef2aSThomas Huth PPC_64B), \ 7026fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7027fcf5ef2aSThomas Huth PPC_64B), \ 7028fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7029fcf5ef2aSThomas Huth PPC_64B) 7030fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7031fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7032fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7033fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7034fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7035fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7036fcf5ef2aSThomas Huth #endif 7037fcf5ef2aSThomas Huth 7038fcf5ef2aSThomas Huth #undef GEN_LDX_E 7039fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7040fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7041fcf5ef2aSThomas Huth 7042fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7043fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7044fcf5ef2aSThomas Huth 7045fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7046fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7047fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7048fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7049fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7050fcf5ef2aSThomas Huth #endif 7051fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7052fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7053fcf5ef2aSThomas Huth 705450728199SRoman Kapl /* External PID based load */ 705550728199SRoman Kapl #undef GEN_LDEPX 705650728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 705750728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 705850728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 705950728199SRoman Kapl 706050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 706150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 706250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 706350728199SRoman Kapl #if defined(TARGET_PPC64) 7064fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 706550728199SRoman Kapl #endif 706650728199SRoman Kapl 7067fcf5ef2aSThomas Huth #undef GEN_STX_E 7068fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 70690123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7070fcf5ef2aSThomas Huth 7071fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7072fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7073fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7074fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7075fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7076fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7077fcf5ef2aSThomas Huth #endif 7078fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7079fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7080fcf5ef2aSThomas Huth 708150728199SRoman Kapl #undef GEN_STEPX 708250728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 708350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 708450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 708550728199SRoman Kapl 708650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 708750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 708850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 708950728199SRoman Kapl #if defined(TARGET_PPC64) 7090fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 709150728199SRoman Kapl #endif 709250728199SRoman Kapl 7093fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7094fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7095fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7096fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7097fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7098fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7099fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7100fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7101fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7102fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7103fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7104fcf5ef2aSThomas Huth 7105fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7106fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7107fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7108fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7110fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7112fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7114fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7116fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7118fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7120fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7122fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7124fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7126fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7128fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7130fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7132fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7134fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7136fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7138fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7140fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7141fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7142fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7143fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7144fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7145fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7146fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7147fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7148fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7149fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7150fcf5ef2aSThomas Huth 7151fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7152fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7153fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7154fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7155fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7156fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7157fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7158fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7159fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7160fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7161fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7162fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7163fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7164fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7165fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7166fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7167fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7168fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7169fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7170fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7171fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7172fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7173fcf5ef2aSThomas Huth 7174139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 7175fcf5ef2aSThomas Huth 7176139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 7177fcf5ef2aSThomas Huth 7178139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 7179fcf5ef2aSThomas Huth 7180139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 7181fcf5ef2aSThomas Huth }; 7182fcf5ef2aSThomas Huth 71837468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71847468e2c8SBruno Larsen (billionai) /* Opcode types */ 71857468e2c8SBruno Larsen (billionai) enum { 71867468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 71877468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 71887468e2c8SBruno Larsen (billionai) }; 71897468e2c8SBruno Larsen (billionai) 71907468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 71917468e2c8SBruno Larsen (billionai) 71927468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 71937468e2c8SBruno Larsen (billionai) { 71947468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 71957468e2c8SBruno Larsen (billionai) } 71967468e2c8SBruno Larsen (billionai) 71977468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 71987468e2c8SBruno Larsen (billionai) { 71997468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 72007468e2c8SBruno Larsen (billionai) } 72017468e2c8SBruno Larsen (billionai) 72027468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 72037468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 72047468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 72057468e2c8SBruno Larsen (billionai) { 72067468e2c8SBruno Larsen (billionai) int i; 72077468e2c8SBruno Larsen (billionai) 72087468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 72097468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 72107468e2c8SBruno Larsen (billionai) } 72117468e2c8SBruno Larsen (billionai) } 72127468e2c8SBruno Larsen (billionai) 72137468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 72147468e2c8SBruno Larsen (billionai) { 72157468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 72167468e2c8SBruno Larsen (billionai) 72177468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 72187468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 72197468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 72207468e2c8SBruno Larsen (billionai) 72217468e2c8SBruno Larsen (billionai) return 0; 72227468e2c8SBruno Larsen (billionai) } 72237468e2c8SBruno Larsen (billionai) 72247468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 72257468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72267468e2c8SBruno Larsen (billionai) { 72277468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 72287468e2c8SBruno Larsen (billionai) return -1; 72297468e2c8SBruno Larsen (billionai) } 72307468e2c8SBruno Larsen (billionai) table[idx] = handler; 72317468e2c8SBruno Larsen (billionai) 72327468e2c8SBruno Larsen (billionai) return 0; 72337468e2c8SBruno Larsen (billionai) } 72347468e2c8SBruno Larsen (billionai) 72357468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 72367468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 72377468e2c8SBruno Larsen (billionai) { 72387468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 72397468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 72407468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 72417468e2c8SBruno Larsen (billionai) return -1; 72427468e2c8SBruno Larsen (billionai) } 72437468e2c8SBruno Larsen (billionai) 72447468e2c8SBruno Larsen (billionai) return 0; 72457468e2c8SBruno Larsen (billionai) } 72467468e2c8SBruno Larsen (billionai) 72477468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 72487468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72497468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72507468e2c8SBruno Larsen (billionai) { 72517468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 72527468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 72537468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 72547468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 72557468e2c8SBruno Larsen (billionai) return -1; 72567468e2c8SBruno Larsen (billionai) } 72577468e2c8SBruno Larsen (billionai) } else { 72587468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 72597468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 72607468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 72617468e2c8SBruno Larsen (billionai) return -1; 72627468e2c8SBruno Larsen (billionai) } 72637468e2c8SBruno Larsen (billionai) } 72647468e2c8SBruno Larsen (billionai) if (handler != NULL && 72657468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 72667468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 72677468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 72687468e2c8SBruno Larsen (billionai) return -1; 72697468e2c8SBruno Larsen (billionai) } 72707468e2c8SBruno Larsen (billionai) 72717468e2c8SBruno Larsen (billionai) return 0; 72727468e2c8SBruno Larsen (billionai) } 72737468e2c8SBruno Larsen (billionai) 72747468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 72757468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72767468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 72777468e2c8SBruno Larsen (billionai) { 72787468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 72797468e2c8SBruno Larsen (billionai) } 72807468e2c8SBruno Larsen (billionai) 72817468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 72827468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 72837468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 72847468e2c8SBruno Larsen (billionai) { 72857468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 72867468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 72877468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 72887468e2c8SBruno Larsen (billionai) return -1; 72897468e2c8SBruno Larsen (billionai) } 72907468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 72917468e2c8SBruno Larsen (billionai) handler) < 0) { 72927468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 72937468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 72947468e2c8SBruno Larsen (billionai) return -1; 72957468e2c8SBruno Larsen (billionai) } 72967468e2c8SBruno Larsen (billionai) 72977468e2c8SBruno Larsen (billionai) return 0; 72987468e2c8SBruno Larsen (billionai) } 72997468e2c8SBruno Larsen (billionai) 73007468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 73017468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 73027468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 73037468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 73047468e2c8SBruno Larsen (billionai) { 73057468e2c8SBruno Larsen (billionai) opc_handler_t **table; 73067468e2c8SBruno Larsen (billionai) 73077468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 73087468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 73097468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 73107468e2c8SBruno Larsen (billionai) return -1; 73117468e2c8SBruno Larsen (billionai) } 73127468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 73137468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 73147468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 73157468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 73167468e2c8SBruno Larsen (billionai) return -1; 73177468e2c8SBruno Larsen (billionai) } 73187468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 73197468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 73207468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 73217468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 73227468e2c8SBruno Larsen (billionai) return -1; 73237468e2c8SBruno Larsen (billionai) } 73247468e2c8SBruno Larsen (billionai) return 0; 73257468e2c8SBruno Larsen (billionai) } 73267468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 73277468e2c8SBruno Larsen (billionai) { 73287468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 73297468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 73307468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 73317468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 73327468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 73337468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 73347468e2c8SBruno Larsen (billionai) return -1; 73357468e2c8SBruno Larsen (billionai) } 73367468e2c8SBruno Larsen (billionai) } else { 73377468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 73387468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 73397468e2c8SBruno Larsen (billionai) return -1; 73407468e2c8SBruno Larsen (billionai) } 73417468e2c8SBruno Larsen (billionai) } 73427468e2c8SBruno Larsen (billionai) } else { 73437468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 73447468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 73457468e2c8SBruno Larsen (billionai) return -1; 73467468e2c8SBruno Larsen (billionai) } 73477468e2c8SBruno Larsen (billionai) } 73487468e2c8SBruno Larsen (billionai) } else { 73497468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 73507468e2c8SBruno Larsen (billionai) return -1; 73517468e2c8SBruno Larsen (billionai) } 73527468e2c8SBruno Larsen (billionai) } 73537468e2c8SBruno Larsen (billionai) 73547468e2c8SBruno Larsen (billionai) return 0; 73557468e2c8SBruno Larsen (billionai) } 73567468e2c8SBruno Larsen (billionai) 73577468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 73587468e2c8SBruno Larsen (billionai) { 73597468e2c8SBruno Larsen (billionai) int i, count, tmp; 73607468e2c8SBruno Larsen (billionai) 73617468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 73627468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 73637468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 73647468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 73657468e2c8SBruno Larsen (billionai) } 73667468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 73677468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 73687468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 73697468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 73707468e2c8SBruno Larsen (billionai) if (tmp == 0) { 73717468e2c8SBruno Larsen (billionai) free(table[i]); 73727468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 73737468e2c8SBruno Larsen (billionai) } else { 73747468e2c8SBruno Larsen (billionai) count++; 73757468e2c8SBruno Larsen (billionai) } 73767468e2c8SBruno Larsen (billionai) } else { 73777468e2c8SBruno Larsen (billionai) count++; 73787468e2c8SBruno Larsen (billionai) } 73797468e2c8SBruno Larsen (billionai) } 73807468e2c8SBruno Larsen (billionai) } 73817468e2c8SBruno Larsen (billionai) 73827468e2c8SBruno Larsen (billionai) return count; 73837468e2c8SBruno Larsen (billionai) } 73847468e2c8SBruno Larsen (billionai) 73857468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 73867468e2c8SBruno Larsen (billionai) { 73877468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 73887468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 73897468e2c8SBruno Larsen (billionai) } 73907468e2c8SBruno Larsen (billionai) } 73917468e2c8SBruno Larsen (billionai) 73927468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 73937468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 73947468e2c8SBruno Larsen (billionai) { 73957468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 73967468e2c8SBruno Larsen (billionai) opcode_t *opc; 73977468e2c8SBruno Larsen (billionai) 73987468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 73997468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 74007468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 74017468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 74027468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 74037468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 74047468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 74057468e2c8SBruno Larsen (billionai) opc->opc3); 74067468e2c8SBruno Larsen (billionai) return; 74077468e2c8SBruno Larsen (billionai) } 74087468e2c8SBruno Larsen (billionai) } 74097468e2c8SBruno Larsen (billionai) } 74107468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 74117468e2c8SBruno Larsen (billionai) fflush(stdout); 74127468e2c8SBruno Larsen (billionai) fflush(stderr); 74137468e2c8SBruno Larsen (billionai) } 74147468e2c8SBruno Larsen (billionai) 74157468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 74167468e2c8SBruno Larsen (billionai) { 74177468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 74187468e2c8SBruno Larsen (billionai) int i, j, k; 74197468e2c8SBruno Larsen (billionai) 74207468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 74217468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 74227468e2c8SBruno Larsen (billionai) continue; 74237468e2c8SBruno Larsen (billionai) } 74247468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 74257468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 74267468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 74277468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 74287468e2c8SBruno Larsen (billionai) continue; 74297468e2c8SBruno Larsen (billionai) } 74307468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 74317468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 74327468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 74337468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 74347468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 74357468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 74367468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74377468e2c8SBruno Larsen (billionai) } 74387468e2c8SBruno Larsen (billionai) } 74397468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 74407468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74417468e2c8SBruno Larsen (billionai) } 74427468e2c8SBruno Larsen (billionai) } 74437468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 74447468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 74457468e2c8SBruno Larsen (billionai) } 74467468e2c8SBruno Larsen (billionai) } 74477468e2c8SBruno Larsen (billionai) } 74487468e2c8SBruno Larsen (billionai) 74497468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 74507468e2c8SBruno Larsen (billionai) { 74517468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 74527468e2c8SBruno Larsen (billionai) 74537468e2c8SBruno Larsen (billionai) /* 74547468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 74557468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 74567468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 74577468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 74587468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 74597468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 74607468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 74617468e2c8SBruno Larsen (billionai) */ 74627468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 74637468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 74647468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 74657468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 74667468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 74677468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 74687468e2c8SBruno Larsen (billionai) } 74697468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 74707468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 74717468e2c8SBruno Larsen (billionai) return 0; 74727468e2c8SBruno Larsen (billionai) } 74737468e2c8SBruno Larsen (billionai) 7474624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7475624cb07fSRichard Henderson { 7476624cb07fSRichard Henderson opc_handler_t **table, *handler; 7477624cb07fSRichard Henderson uint32_t inval; 7478624cb07fSRichard Henderson 7479624cb07fSRichard Henderson ctx->opcode = insn; 7480624cb07fSRichard Henderson 7481624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7482624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7483624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7484624cb07fSRichard Henderson 7485624cb07fSRichard Henderson table = cpu->opcodes; 7486624cb07fSRichard Henderson handler = table[opc1(insn)]; 7487624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7488624cb07fSRichard Henderson table = ind_table(handler); 7489624cb07fSRichard Henderson handler = table[opc2(insn)]; 7490624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7491624cb07fSRichard Henderson table = ind_table(handler); 7492624cb07fSRichard Henderson handler = table[opc3(insn)]; 7493624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7494624cb07fSRichard Henderson table = ind_table(handler); 7495624cb07fSRichard Henderson handler = table[opc4(insn)]; 7496624cb07fSRichard Henderson } 7497624cb07fSRichard Henderson } 7498624cb07fSRichard Henderson } 7499624cb07fSRichard Henderson 7500624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7501624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7502624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7503624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7504624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7505624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7506624cb07fSRichard Henderson insn, ctx->cia); 7507624cb07fSRichard Henderson return false; 7508624cb07fSRichard Henderson } 7509624cb07fSRichard Henderson 7510624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7511624cb07fSRichard Henderson && Rc(insn))) { 7512624cb07fSRichard Henderson inval = handler->inval2; 7513624cb07fSRichard Henderson } else { 7514624cb07fSRichard Henderson inval = handler->inval1; 7515624cb07fSRichard Henderson } 7516624cb07fSRichard Henderson 7517624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7518624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7519624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7520624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7521624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7522624cb07fSRichard Henderson insn, ctx->cia); 7523624cb07fSRichard Henderson return false; 7524624cb07fSRichard Henderson } 7525624cb07fSRichard Henderson 7526624cb07fSRichard Henderson handler->handler(ctx); 7527624cb07fSRichard Henderson return true; 7528624cb07fSRichard Henderson } 7529624cb07fSRichard Henderson 7530b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7531fcf5ef2aSThomas Huth { 7532b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 75339c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 75342df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7535fcf5ef2aSThomas Huth 7536b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 75372df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7538d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 75392df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 75402df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7541b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7542b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7543b0c2d521SEmilio G. Cota ctx->access_type = -1; 7544d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 75452df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7546b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 75470e3bf489SRoman Kapl ctx->flags = env->flags; 7548fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 75492df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7550b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7551fcf5ef2aSThomas Huth #endif 7552e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7553d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7554fcf5ef2aSThomas Huth 75552df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 75562df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 75572df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 75582df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 75592df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7560f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 75611db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7562f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7563f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 756446d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 75652df4fe7aSRichard Henderson 7566b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 75672df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 75682df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 75699498d103SRichard Henderson ctx->base.max_insns = 1; 7570efe843d8SDavid Gibson } 75712df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7572b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7573efe843d8SDavid Gibson } 757413b45575SRichard Henderson } 7575fcf5ef2aSThomas Huth 7576b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7577b0c2d521SEmilio G. Cota { 7578b0c2d521SEmilio G. Cota } 7579fcf5ef2aSThomas Huth 7580b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7581b0c2d521SEmilio G. Cota { 7582b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7583b0c2d521SEmilio G. Cota } 7584b0c2d521SEmilio G. Cota 758599082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 758699082815SRichard Henderson { 758799082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 758899082815SRichard Henderson return opc1(insn) == 1; 758999082815SRichard Henderson } 759099082815SRichard Henderson 7591b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7592b0c2d521SEmilio G. Cota { 7593b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 759428876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7595b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 759699082815SRichard Henderson target_ulong pc; 7597624cb07fSRichard Henderson uint32_t insn; 7598624cb07fSRichard Henderson bool ok; 7599b0c2d521SEmilio G. Cota 7600fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7601fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7602b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7603b0c2d521SEmilio G. Cota 760499082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 76054e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 760699082815SRichard Henderson ctx->base.pc_next = pc += 4; 7607fcf5ef2aSThomas Huth 760899082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 760999082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 761099082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 761199082815SRichard Henderson } else if ((pc & 63) == 0) { 761299082815SRichard Henderson /* 761399082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 761499082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 761599082815SRichard Henderson * 64-byte address boundary (system alignment error). 761699082815SRichard Henderson */ 761799082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 761899082815SRichard Henderson ok = true; 761999082815SRichard Henderson } else { 76204e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 76214e116893SIlya Leoshkevich need_byteswap(ctx)); 762299082815SRichard Henderson ctx->base.pc_next = pc += 4; 762399082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 762499082815SRichard Henderson } 7625624cb07fSRichard Henderson if (!ok) { 7626624cb07fSRichard Henderson gen_invalid(ctx); 7627fcf5ef2aSThomas Huth } 7628624cb07fSRichard Henderson 762964a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 763099082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 763164a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 763264a0f644SRichard Henderson } 763364a0f644SRichard Henderson 763451eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 7635fcf5ef2aSThomas Huth } 7636b0c2d521SEmilio G. Cota 7637b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7638b0c2d521SEmilio G. Cota { 7639b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7640a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7641a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7642b0c2d521SEmilio G. Cota 7643a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7644a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 76453d8a5b69SRichard Henderson return; 76463d8a5b69SRichard Henderson } 76473d8a5b69SRichard Henderson 7648a9b5b3d0SRichard Henderson /* Honor single stepping. */ 76499498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 76509498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 7651a9b5b3d0SRichard Henderson switch (is_jmp) { 7652a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7653a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7654a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7655a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7656a9b5b3d0SRichard Henderson break; 7657a9b5b3d0SRichard Henderson case DISAS_EXIT: 7658a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7659a9b5b3d0SRichard Henderson break; 7660a9b5b3d0SRichard Henderson default: 7661a9b5b3d0SRichard Henderson g_assert_not_reached(); 7662fcf5ef2aSThomas Huth } 766313b45575SRichard Henderson 7664a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 7665a9b5b3d0SRichard Henderson return; 7666a9b5b3d0SRichard Henderson } 7667a9b5b3d0SRichard Henderson 7668a9b5b3d0SRichard Henderson switch (is_jmp) { 7669a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7670a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 767146d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7672a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7673a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7674a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7675a9b5b3d0SRichard Henderson break; 7676a9b5b3d0SRichard Henderson } 7677a9b5b3d0SRichard Henderson /* fall through */ 7678a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7679a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7680a9b5b3d0SRichard Henderson /* fall through */ 7681a9b5b3d0SRichard Henderson case DISAS_CHAIN: 768246d396bdSDaniel Henrique Barboza /* 768346d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 768446d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 768546d396bdSDaniel Henrique Barboza */ 768646d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 768746d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 768846d396bdSDaniel Henrique Barboza } 768946d396bdSDaniel Henrique Barboza 7690a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7691a9b5b3d0SRichard Henderson break; 7692a9b5b3d0SRichard Henderson 7693a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7694a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7695a9b5b3d0SRichard Henderson /* fall through */ 7696a9b5b3d0SRichard Henderson case DISAS_EXIT: 769746d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 769807ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7699a9b5b3d0SRichard Henderson break; 7700a9b5b3d0SRichard Henderson 7701a9b5b3d0SRichard Henderson default: 7702a9b5b3d0SRichard Henderson g_assert_not_reached(); 7703fcf5ef2aSThomas Huth } 7704fcf5ef2aSThomas Huth } 7705b0c2d521SEmilio G. Cota 77068eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 77078eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7708b0c2d521SEmilio G. Cota { 77098eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 77108eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7711b0c2d521SEmilio G. Cota } 7712b0c2d521SEmilio G. Cota 7713b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7714b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7715b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7716b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7717b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7718b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7719b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7720b0c2d521SEmilio G. Cota }; 7721b0c2d521SEmilio G. Cota 7722*306c8721SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 7723*306c8721SRichard Henderson target_ulong pc, void *host_pc) 7724b0c2d521SEmilio G. Cota { 7725b0c2d521SEmilio G. Cota DisasContext ctx; 7726b0c2d521SEmilio G. Cota 7727*306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7728fcf5ef2aSThomas Huth } 7729fcf5ef2aSThomas Huth 7730fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7731fcf5ef2aSThomas Huth target_ulong *data) 7732fcf5ef2aSThomas Huth { 7733fcf5ef2aSThomas Huth env->nip = data[0]; 7734fcf5ef2aSThomas Huth } 7735