1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39fcf5ef2aSThomas Huth 40fcf5ef2aSThomas Huth 41fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 42fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 43fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 46efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 47efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 157fcf5ef2aSThomas Huth uint32_t opcode; 158fcf5ef2aSThomas Huth uint32_t exception; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 1763c89b8d6SNicholas Piggin bool scv_enabled; 177c6fd28fdSSuraj Jitindar Singh bool gtse; 178fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 179fcf5ef2aSThomas Huth int singlestep_enabled; 1800e3bf489SRoman Kapl uint32_t flags; 181fcf5ef2aSThomas Huth uint64_t insns_flags; 182fcf5ef2aSThomas Huth uint64_t insns_flags2; 183fcf5ef2aSThomas Huth }; 184fcf5ef2aSThomas Huth 185fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 186fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 187fcf5ef2aSThomas Huth { 188fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 189fcf5ef2aSThomas Huth return ctx->le_mode; 190fcf5ef2aSThomas Huth #else 191fcf5ef2aSThomas Huth return !ctx->le_mode; 192fcf5ef2aSThomas Huth #endif 193fcf5ef2aSThomas Huth } 194fcf5ef2aSThomas Huth 195fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 196fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 197fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 198fcf5ef2aSThomas Huth #else 199fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 200fcf5ef2aSThomas Huth #endif 201fcf5ef2aSThomas Huth 202fcf5ef2aSThomas Huth struct opc_handler_t { 203fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 204fcf5ef2aSThomas Huth uint32_t inval1; 205fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 206fcf5ef2aSThomas Huth uint32_t inval2; 207fcf5ef2aSThomas Huth /* instruction type */ 208fcf5ef2aSThomas Huth uint64_t type; 209fcf5ef2aSThomas Huth /* extended instruction type */ 210fcf5ef2aSThomas Huth uint64_t type2; 211fcf5ef2aSThomas Huth /* handler */ 212fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 213fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 214fcf5ef2aSThomas Huth const char *oname; 215fcf5ef2aSThomas Huth #endif 216fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 217fcf5ef2aSThomas Huth uint64_t count; 218fcf5ef2aSThomas Huth #endif 219fcf5ef2aSThomas Huth }; 220fcf5ef2aSThomas Huth 2210e3bf489SRoman Kapl /* SPR load/store helpers */ 2220e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2230e3bf489SRoman Kapl { 2240e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2250e3bf489SRoman Kapl } 2260e3bf489SRoman Kapl 2270e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2280e3bf489SRoman Kapl { 2290e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2300e3bf489SRoman Kapl } 2310e3bf489SRoman Kapl 232fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 233fcf5ef2aSThomas Huth { 234fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 235fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 236fcf5ef2aSThomas Huth ctx->access_type = access_type; 237fcf5ef2aSThomas Huth } 238fcf5ef2aSThomas Huth } 239fcf5ef2aSThomas Huth 240fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 241fcf5ef2aSThomas Huth { 242fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 243fcf5ef2aSThomas Huth nip = (uint32_t)nip; 244fcf5ef2aSThomas Huth } 245fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth 248fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 249fcf5ef2aSThomas Huth { 250fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 251fcf5ef2aSThomas Huth 252efe843d8SDavid Gibson /* 253efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 254efe843d8SDavid Gibson * faulting instruction 255fcf5ef2aSThomas Huth */ 256fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 257b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 258fcf5ef2aSThomas Huth } 259fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 260fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 261fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 262fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 263fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 264fcf5ef2aSThomas Huth ctx->exception = (excp); 265fcf5ef2aSThomas Huth } 266fcf5ef2aSThomas Huth 267fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 268fcf5ef2aSThomas Huth { 269fcf5ef2aSThomas Huth TCGv_i32 t0; 270fcf5ef2aSThomas Huth 271efe843d8SDavid Gibson /* 272efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 273efe843d8SDavid Gibson * faulting instruction 274fcf5ef2aSThomas Huth */ 275fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 276b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 277fcf5ef2aSThomas Huth } 278fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 279fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 280fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 281fcf5ef2aSThomas Huth ctx->exception = (excp); 282fcf5ef2aSThomas Huth } 283fcf5ef2aSThomas Huth 284fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 285fcf5ef2aSThomas Huth target_ulong nip) 286fcf5ef2aSThomas Huth { 287fcf5ef2aSThomas Huth TCGv_i32 t0; 288fcf5ef2aSThomas Huth 289fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 290fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 291fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 292fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 293fcf5ef2aSThomas Huth ctx->exception = (excp); 294fcf5ef2aSThomas Huth } 295fcf5ef2aSThomas Huth 296e150ac89SRoman Kapl /* 297e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 298e150ac89SRoman Kapl * SPR registers for this exception. 299e150ac89SRoman Kapl * 300e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 301e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3020e3bf489SRoman Kapl */ 303e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3040e3bf489SRoman Kapl { 3050e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3060e3bf489SRoman Kapl target_ulong dbsr = 0; 307e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3080e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 309e150ac89SRoman Kapl } else { 310e150ac89SRoman Kapl /* Must have been branch */ 3110e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3120e3bf489SRoman Kapl } 3130e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3140e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3150e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3160e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3170e3bf489SRoman Kapl tcg_temp_free(t0); 3180e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3190e3bf489SRoman Kapl } else { 320e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3210e3bf489SRoman Kapl } 3220e3bf489SRoman Kapl } 3230e3bf489SRoman Kapl 324fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 325fcf5ef2aSThomas Huth { 326fcf5ef2aSThomas Huth TCGv_i32 t0; 327fcf5ef2aSThomas Huth 328efe843d8SDavid Gibson /* 329efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 330efe843d8SDavid Gibson * faulting instruction 331fcf5ef2aSThomas Huth */ 332fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 333fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 334b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 335fcf5ef2aSThomas Huth } 336fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 337fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 338fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 339fcf5ef2aSThomas Huth } 340fcf5ef2aSThomas Huth 341fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 342fcf5ef2aSThomas Huth { 343fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 344fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 345fcf5ef2aSThomas Huth } 346fcf5ef2aSThomas Huth 347fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 348fcf5ef2aSThomas Huth { 349fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 350fcf5ef2aSThomas Huth } 351fcf5ef2aSThomas Huth 352fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 353fcf5ef2aSThomas Huth { 354fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 355fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 356fcf5ef2aSThomas Huth } 357fcf5ef2aSThomas Huth 358fcf5ef2aSThomas Huth /* Stop translation */ 359fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 360fcf5ef2aSThomas Huth { 361b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 362fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 363fcf5ef2aSThomas Huth } 364fcf5ef2aSThomas Huth 365fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 366fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 367fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 368fcf5ef2aSThomas Huth { 369fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 370fcf5ef2aSThomas Huth } 371fcf5ef2aSThomas Huth #endif 372fcf5ef2aSThomas Huth 373fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 374fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 375fcf5ef2aSThomas Huth 376fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 377fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 378fcf5ef2aSThomas Huth 379fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 380fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 381fcf5ef2aSThomas Huth 382fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 383fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 384fcf5ef2aSThomas Huth 385fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 386fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 387fcf5ef2aSThomas Huth 388fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 389fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 390fcf5ef2aSThomas Huth 391fcf5ef2aSThomas Huth typedef struct opcode_t { 392fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 393fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 394fcf5ef2aSThomas Huth unsigned char pad[4]; 395fcf5ef2aSThomas Huth #endif 396fcf5ef2aSThomas Huth opc_handler_t handler; 397fcf5ef2aSThomas Huth const char *oname; 398fcf5ef2aSThomas Huth } opcode_t; 399fcf5ef2aSThomas Huth 400fcf5ef2aSThomas Huth /* Helpers for priv. check */ 401fcf5ef2aSThomas Huth #define GEN_PRIV \ 402fcf5ef2aSThomas Huth do { \ 403fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 404fcf5ef2aSThomas Huth } while (0) 405fcf5ef2aSThomas Huth 406fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 407fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 408fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 409fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 410fcf5ef2aSThomas Huth #else 411fcf5ef2aSThomas Huth #define CHK_HV \ 412fcf5ef2aSThomas Huth do { \ 413fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 414fcf5ef2aSThomas Huth GEN_PRIV; \ 415fcf5ef2aSThomas Huth } \ 416fcf5ef2aSThomas Huth } while (0) 417fcf5ef2aSThomas Huth #define CHK_SV \ 418fcf5ef2aSThomas Huth do { \ 419fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 420fcf5ef2aSThomas Huth GEN_PRIV; \ 421fcf5ef2aSThomas Huth } \ 422fcf5ef2aSThomas Huth } while (0) 423fcf5ef2aSThomas Huth #define CHK_HVRM \ 424fcf5ef2aSThomas Huth do { \ 425fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 426fcf5ef2aSThomas Huth GEN_PRIV; \ 427fcf5ef2aSThomas Huth } \ 428fcf5ef2aSThomas Huth } while (0) 429fcf5ef2aSThomas Huth #endif 430fcf5ef2aSThomas Huth 431fcf5ef2aSThomas Huth #define CHK_NONE 432fcf5ef2aSThomas Huth 433fcf5ef2aSThomas Huth /*****************************************************************************/ 434fcf5ef2aSThomas Huth /* PowerPC instructions table */ 435fcf5ef2aSThomas Huth 436fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 437fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 438fcf5ef2aSThomas Huth { \ 439fcf5ef2aSThomas Huth .opc1 = op1, \ 440fcf5ef2aSThomas Huth .opc2 = op2, \ 441fcf5ef2aSThomas Huth .opc3 = op3, \ 442fcf5ef2aSThomas Huth .opc4 = 0xff, \ 443fcf5ef2aSThomas Huth .handler = { \ 444fcf5ef2aSThomas Huth .inval1 = invl, \ 445fcf5ef2aSThomas Huth .type = _typ, \ 446fcf5ef2aSThomas Huth .type2 = _typ2, \ 447fcf5ef2aSThomas Huth .handler = &gen_##name, \ 448fcf5ef2aSThomas Huth .oname = stringify(name), \ 449fcf5ef2aSThomas Huth }, \ 450fcf5ef2aSThomas Huth .oname = stringify(name), \ 451fcf5ef2aSThomas Huth } 452fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 453fcf5ef2aSThomas Huth { \ 454fcf5ef2aSThomas Huth .opc1 = op1, \ 455fcf5ef2aSThomas Huth .opc2 = op2, \ 456fcf5ef2aSThomas Huth .opc3 = op3, \ 457fcf5ef2aSThomas Huth .opc4 = 0xff, \ 458fcf5ef2aSThomas Huth .handler = { \ 459fcf5ef2aSThomas Huth .inval1 = invl1, \ 460fcf5ef2aSThomas Huth .inval2 = invl2, \ 461fcf5ef2aSThomas Huth .type = _typ, \ 462fcf5ef2aSThomas Huth .type2 = _typ2, \ 463fcf5ef2aSThomas Huth .handler = &gen_##name, \ 464fcf5ef2aSThomas Huth .oname = stringify(name), \ 465fcf5ef2aSThomas Huth }, \ 466fcf5ef2aSThomas Huth .oname = stringify(name), \ 467fcf5ef2aSThomas Huth } 468fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 469fcf5ef2aSThomas Huth { \ 470fcf5ef2aSThomas Huth .opc1 = op1, \ 471fcf5ef2aSThomas Huth .opc2 = op2, \ 472fcf5ef2aSThomas Huth .opc3 = op3, \ 473fcf5ef2aSThomas Huth .opc4 = 0xff, \ 474fcf5ef2aSThomas Huth .handler = { \ 475fcf5ef2aSThomas Huth .inval1 = invl, \ 476fcf5ef2aSThomas Huth .type = _typ, \ 477fcf5ef2aSThomas Huth .type2 = _typ2, \ 478fcf5ef2aSThomas Huth .handler = &gen_##name, \ 479fcf5ef2aSThomas Huth .oname = onam, \ 480fcf5ef2aSThomas Huth }, \ 481fcf5ef2aSThomas Huth .oname = onam, \ 482fcf5ef2aSThomas Huth } 483fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 484fcf5ef2aSThomas Huth { \ 485fcf5ef2aSThomas Huth .opc1 = op1, \ 486fcf5ef2aSThomas Huth .opc2 = op2, \ 487fcf5ef2aSThomas Huth .opc3 = op3, \ 488fcf5ef2aSThomas Huth .opc4 = op4, \ 489fcf5ef2aSThomas Huth .handler = { \ 490fcf5ef2aSThomas Huth .inval1 = invl, \ 491fcf5ef2aSThomas Huth .type = _typ, \ 492fcf5ef2aSThomas Huth .type2 = _typ2, \ 493fcf5ef2aSThomas Huth .handler = &gen_##name, \ 494fcf5ef2aSThomas Huth .oname = stringify(name), \ 495fcf5ef2aSThomas Huth }, \ 496fcf5ef2aSThomas Huth .oname = stringify(name), \ 497fcf5ef2aSThomas Huth } 498fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 499fcf5ef2aSThomas Huth { \ 500fcf5ef2aSThomas Huth .opc1 = op1, \ 501fcf5ef2aSThomas Huth .opc2 = op2, \ 502fcf5ef2aSThomas Huth .opc3 = op3, \ 503fcf5ef2aSThomas Huth .opc4 = op4, \ 504fcf5ef2aSThomas Huth .handler = { \ 505fcf5ef2aSThomas Huth .inval1 = invl, \ 506fcf5ef2aSThomas Huth .type = _typ, \ 507fcf5ef2aSThomas Huth .type2 = _typ2, \ 508fcf5ef2aSThomas Huth .handler = &gen_##name, \ 509fcf5ef2aSThomas Huth .oname = onam, \ 510fcf5ef2aSThomas Huth }, \ 511fcf5ef2aSThomas Huth .oname = onam, \ 512fcf5ef2aSThomas Huth } 513fcf5ef2aSThomas Huth #else 514fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 515fcf5ef2aSThomas Huth { \ 516fcf5ef2aSThomas Huth .opc1 = op1, \ 517fcf5ef2aSThomas Huth .opc2 = op2, \ 518fcf5ef2aSThomas Huth .opc3 = op3, \ 519fcf5ef2aSThomas Huth .opc4 = 0xff, \ 520fcf5ef2aSThomas Huth .handler = { \ 521fcf5ef2aSThomas Huth .inval1 = invl, \ 522fcf5ef2aSThomas Huth .type = _typ, \ 523fcf5ef2aSThomas Huth .type2 = _typ2, \ 524fcf5ef2aSThomas Huth .handler = &gen_##name, \ 525fcf5ef2aSThomas Huth }, \ 526fcf5ef2aSThomas Huth .oname = stringify(name), \ 527fcf5ef2aSThomas Huth } 528fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 529fcf5ef2aSThomas Huth { \ 530fcf5ef2aSThomas Huth .opc1 = op1, \ 531fcf5ef2aSThomas Huth .opc2 = op2, \ 532fcf5ef2aSThomas Huth .opc3 = op3, \ 533fcf5ef2aSThomas Huth .opc4 = 0xff, \ 534fcf5ef2aSThomas Huth .handler = { \ 535fcf5ef2aSThomas Huth .inval1 = invl1, \ 536fcf5ef2aSThomas Huth .inval2 = invl2, \ 537fcf5ef2aSThomas Huth .type = _typ, \ 538fcf5ef2aSThomas Huth .type2 = _typ2, \ 539fcf5ef2aSThomas Huth .handler = &gen_##name, \ 540fcf5ef2aSThomas Huth }, \ 541fcf5ef2aSThomas Huth .oname = stringify(name), \ 542fcf5ef2aSThomas Huth } 543fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 544fcf5ef2aSThomas Huth { \ 545fcf5ef2aSThomas Huth .opc1 = op1, \ 546fcf5ef2aSThomas Huth .opc2 = op2, \ 547fcf5ef2aSThomas Huth .opc3 = op3, \ 548fcf5ef2aSThomas Huth .opc4 = 0xff, \ 549fcf5ef2aSThomas Huth .handler = { \ 550fcf5ef2aSThomas Huth .inval1 = invl, \ 551fcf5ef2aSThomas Huth .type = _typ, \ 552fcf5ef2aSThomas Huth .type2 = _typ2, \ 553fcf5ef2aSThomas Huth .handler = &gen_##name, \ 554fcf5ef2aSThomas Huth }, \ 555fcf5ef2aSThomas Huth .oname = onam, \ 556fcf5ef2aSThomas Huth } 557fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 558fcf5ef2aSThomas Huth { \ 559fcf5ef2aSThomas Huth .opc1 = op1, \ 560fcf5ef2aSThomas Huth .opc2 = op2, \ 561fcf5ef2aSThomas Huth .opc3 = op3, \ 562fcf5ef2aSThomas Huth .opc4 = op4, \ 563fcf5ef2aSThomas Huth .handler = { \ 564fcf5ef2aSThomas Huth .inval1 = invl, \ 565fcf5ef2aSThomas Huth .type = _typ, \ 566fcf5ef2aSThomas Huth .type2 = _typ2, \ 567fcf5ef2aSThomas Huth .handler = &gen_##name, \ 568fcf5ef2aSThomas Huth }, \ 569fcf5ef2aSThomas Huth .oname = stringify(name), \ 570fcf5ef2aSThomas Huth } 571fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 572fcf5ef2aSThomas Huth { \ 573fcf5ef2aSThomas Huth .opc1 = op1, \ 574fcf5ef2aSThomas Huth .opc2 = op2, \ 575fcf5ef2aSThomas Huth .opc3 = op3, \ 576fcf5ef2aSThomas Huth .opc4 = op4, \ 577fcf5ef2aSThomas Huth .handler = { \ 578fcf5ef2aSThomas Huth .inval1 = invl, \ 579fcf5ef2aSThomas Huth .type = _typ, \ 580fcf5ef2aSThomas Huth .type2 = _typ2, \ 581fcf5ef2aSThomas Huth .handler = &gen_##name, \ 582fcf5ef2aSThomas Huth }, \ 583fcf5ef2aSThomas Huth .oname = onam, \ 584fcf5ef2aSThomas Huth } 585fcf5ef2aSThomas Huth #endif 586fcf5ef2aSThomas Huth 587fcf5ef2aSThomas Huth /* Invalid instruction */ 588fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 589fcf5ef2aSThomas Huth { 590fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 591fcf5ef2aSThomas Huth } 592fcf5ef2aSThomas Huth 593fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 594fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 595fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 596fcf5ef2aSThomas Huth .type = PPC_NONE, 597fcf5ef2aSThomas Huth .type2 = PPC_NONE, 598fcf5ef2aSThomas Huth .handler = gen_invalid, 599fcf5ef2aSThomas Huth }; 600fcf5ef2aSThomas Huth 601fcf5ef2aSThomas Huth /*** Integer comparison ***/ 602fcf5ef2aSThomas Huth 603fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 604fcf5ef2aSThomas Huth { 605fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 606b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 607b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 608fcf5ef2aSThomas Huth 609b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 610b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 611efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 612efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 613b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 614efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 615efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 616b62b3686Spbonzini@redhat.com 617b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 618fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 619b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 620fcf5ef2aSThomas Huth 621fcf5ef2aSThomas Huth tcg_temp_free(t0); 622b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 623b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 624fcf5ef2aSThomas Huth } 625fcf5ef2aSThomas Huth 626fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 627fcf5ef2aSThomas Huth { 628fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 629fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 630fcf5ef2aSThomas Huth tcg_temp_free(t0); 631fcf5ef2aSThomas Huth } 632fcf5ef2aSThomas Huth 633fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 634fcf5ef2aSThomas Huth { 635fcf5ef2aSThomas Huth TCGv t0, t1; 636fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 637fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 638fcf5ef2aSThomas Huth if (s) { 639fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 640fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 641fcf5ef2aSThomas Huth } else { 642fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 643fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 644fcf5ef2aSThomas Huth } 645fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 646fcf5ef2aSThomas Huth tcg_temp_free(t1); 647fcf5ef2aSThomas Huth tcg_temp_free(t0); 648fcf5ef2aSThomas Huth } 649fcf5ef2aSThomas Huth 650fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 651fcf5ef2aSThomas Huth { 652fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 653fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 654fcf5ef2aSThomas Huth tcg_temp_free(t0); 655fcf5ef2aSThomas Huth } 656fcf5ef2aSThomas Huth 657fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 658fcf5ef2aSThomas Huth { 659fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 660fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 661fcf5ef2aSThomas Huth } else { 662fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 663fcf5ef2aSThomas Huth } 664fcf5ef2aSThomas Huth } 665fcf5ef2aSThomas Huth 666fcf5ef2aSThomas Huth /* cmp */ 667fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 668fcf5ef2aSThomas Huth { 669fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 670fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 671fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 672fcf5ef2aSThomas Huth } else { 673fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 674fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 675fcf5ef2aSThomas Huth } 676fcf5ef2aSThomas Huth } 677fcf5ef2aSThomas Huth 678fcf5ef2aSThomas Huth /* cmpi */ 679fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 680fcf5ef2aSThomas Huth { 681fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 682fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 683fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 684fcf5ef2aSThomas Huth } else { 685fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 686fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 687fcf5ef2aSThomas Huth } 688fcf5ef2aSThomas Huth } 689fcf5ef2aSThomas Huth 690fcf5ef2aSThomas Huth /* cmpl */ 691fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 692fcf5ef2aSThomas Huth { 693fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 694fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 695fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 696fcf5ef2aSThomas Huth } else { 697fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 698fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 699fcf5ef2aSThomas Huth } 700fcf5ef2aSThomas Huth } 701fcf5ef2aSThomas Huth 702fcf5ef2aSThomas Huth /* cmpli */ 703fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 704fcf5ef2aSThomas Huth { 705fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 706fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 707fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 708fcf5ef2aSThomas Huth } else { 709fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 710fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 711fcf5ef2aSThomas Huth } 712fcf5ef2aSThomas Huth } 713fcf5ef2aSThomas Huth 714fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 715fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 716fcf5ef2aSThomas Huth { 717fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 718fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 719fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 720fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 721fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 722fcf5ef2aSThomas Huth 723fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 724fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 725fcf5ef2aSThomas Huth 726fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 727fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 728fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 729fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 730fcf5ef2aSThomas Huth 731fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 732fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 733fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 734fcf5ef2aSThomas Huth 735fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 736fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 737fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 738fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 739fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 740fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 741fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 742fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 743fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 744fcf5ef2aSThomas Huth } 745efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 746fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 747fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 748fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 749fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 750fcf5ef2aSThomas Huth } 751fcf5ef2aSThomas Huth 752fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 753fcf5ef2aSThomas Huth /* cmpeqb */ 754fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 755fcf5ef2aSThomas Huth { 756fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 757fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 758fcf5ef2aSThomas Huth } 759fcf5ef2aSThomas Huth #endif 760fcf5ef2aSThomas Huth 761fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 762fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 763fcf5ef2aSThomas Huth { 764fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 765fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 766fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 767fcf5ef2aSThomas Huth TCGv zr; 768fcf5ef2aSThomas Huth 769fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 770fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 771fcf5ef2aSThomas Huth 772fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 773fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 774fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 775fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 776fcf5ef2aSThomas Huth tcg_temp_free(zr); 777fcf5ef2aSThomas Huth tcg_temp_free(t0); 778fcf5ef2aSThomas Huth } 779fcf5ef2aSThomas Huth 780fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 781fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 782fcf5ef2aSThomas Huth { 783fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 784fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 785fcf5ef2aSThomas Huth } 786fcf5ef2aSThomas Huth 787fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 788fcf5ef2aSThomas Huth 789fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 790fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 791fcf5ef2aSThomas Huth { 792fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 793fcf5ef2aSThomas Huth 794fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 795fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 796fcf5ef2aSThomas Huth if (sub) { 797fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 798fcf5ef2aSThomas Huth } else { 799fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 800fcf5ef2aSThomas Huth } 801fcf5ef2aSThomas Huth tcg_temp_free(t0); 802fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 803dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 804dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 805dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 806fcf5ef2aSThomas Huth } 807dc0ad844SNikunj A Dadhania } else { 808dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 809dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 810dc0ad844SNikunj A Dadhania } 81138a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 812dc0ad844SNikunj A Dadhania } 813fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 814fcf5ef2aSThomas Huth } 815fcf5ef2aSThomas Huth 8166b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8176b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 8184c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 8196b10d008SNikunj A Dadhania { 8206b10d008SNikunj A Dadhania TCGv t0; 8216b10d008SNikunj A Dadhania 8226b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8236b10d008SNikunj A Dadhania return; 8246b10d008SNikunj A Dadhania } 8256b10d008SNikunj A Dadhania 8266b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 82733903d0aSNikunj A Dadhania if (sub) { 82833903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 82933903d0aSNikunj A Dadhania } else { 8306b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 83133903d0aSNikunj A Dadhania } 8326b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 8334c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 8346b10d008SNikunj A Dadhania tcg_temp_free(t0); 8356b10d008SNikunj A Dadhania } 8366b10d008SNikunj A Dadhania 837fcf5ef2aSThomas Huth /* Common add function */ 838fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 8394c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 8404c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 841fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 842fcf5ef2aSThomas Huth { 843fcf5ef2aSThomas Huth TCGv t0 = ret; 844fcf5ef2aSThomas Huth 845fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 846fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 847fcf5ef2aSThomas Huth } 848fcf5ef2aSThomas Huth 849fcf5ef2aSThomas Huth if (compute_ca) { 850fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 851efe843d8SDavid Gibson /* 852efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 853efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 854efe843d8SDavid Gibson * produce the carry into bit 32. 855efe843d8SDavid Gibson */ 856fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 857fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 858fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 859fcf5ef2aSThomas Huth if (add_ca) { 8604c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 861fcf5ef2aSThomas Huth } 8624c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 863fcf5ef2aSThomas Huth tcg_temp_free(t1); 8644c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 8656b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 8664c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 8676b10d008SNikunj A Dadhania } 868fcf5ef2aSThomas Huth } else { 869fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 870fcf5ef2aSThomas Huth if (add_ca) { 8714c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 8724c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 873fcf5ef2aSThomas Huth } else { 8744c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 875fcf5ef2aSThomas Huth } 8764c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 877fcf5ef2aSThomas Huth tcg_temp_free(zero); 878fcf5ef2aSThomas Huth } 879fcf5ef2aSThomas Huth } else { 880fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 881fcf5ef2aSThomas Huth if (add_ca) { 8824c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 883fcf5ef2aSThomas Huth } 884fcf5ef2aSThomas Huth } 885fcf5ef2aSThomas Huth 886fcf5ef2aSThomas Huth if (compute_ov) { 887fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 888fcf5ef2aSThomas Huth } 889fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 890fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 891fcf5ef2aSThomas Huth } 892fcf5ef2aSThomas Huth 89311f4e8f8SRichard Henderson if (t0 != ret) { 894fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 895fcf5ef2aSThomas Huth tcg_temp_free(t0); 896fcf5ef2aSThomas Huth } 897fcf5ef2aSThomas Huth } 898fcf5ef2aSThomas Huth /* Add functions with two operands */ 8994c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 900fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 901fcf5ef2aSThomas Huth { \ 902fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 903fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 9044c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 905fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 906fcf5ef2aSThomas Huth } 907fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 9084c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 909fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 910fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 911fcf5ef2aSThomas Huth { \ 912fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 913fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 914fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 9154c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 916fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 917fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 918fcf5ef2aSThomas Huth } 919fcf5ef2aSThomas Huth 920fcf5ef2aSThomas Huth /* add add. addo addo. */ 9214c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 9224c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 923fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 9244c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 9254c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 926fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 9274c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 9284c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 929fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 9304c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 9314c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 9324c5920afSSuraj Jitindar Singh /* addex */ 9334c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 934fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 9354c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 9364c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 937fcf5ef2aSThomas Huth /* addi */ 938fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 939fcf5ef2aSThomas Huth { 940fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 941fcf5ef2aSThomas Huth 942fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 943fcf5ef2aSThomas Huth /* li case */ 944fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 945fcf5ef2aSThomas Huth } else { 946fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 947fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 948fcf5ef2aSThomas Huth } 949fcf5ef2aSThomas Huth } 950fcf5ef2aSThomas Huth /* addic addic.*/ 951fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 952fcf5ef2aSThomas Huth { 953fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 954fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 9554c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 956fcf5ef2aSThomas Huth tcg_temp_free(c); 957fcf5ef2aSThomas Huth } 958fcf5ef2aSThomas Huth 959fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 960fcf5ef2aSThomas Huth { 961fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 962fcf5ef2aSThomas Huth } 963fcf5ef2aSThomas Huth 964fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 965fcf5ef2aSThomas Huth { 966fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 967fcf5ef2aSThomas Huth } 968fcf5ef2aSThomas Huth 969fcf5ef2aSThomas Huth /* addis */ 970fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 971fcf5ef2aSThomas Huth { 972fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 973fcf5ef2aSThomas Huth 974fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 975fcf5ef2aSThomas Huth /* lis case */ 976fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 977fcf5ef2aSThomas Huth } else { 978fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 979fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 980fcf5ef2aSThomas Huth } 981fcf5ef2aSThomas Huth } 982fcf5ef2aSThomas Huth 983fcf5ef2aSThomas Huth /* addpcis */ 984fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 985fcf5ef2aSThomas Huth { 986fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 987fcf5ef2aSThomas Huth 988b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 989fcf5ef2aSThomas Huth } 990fcf5ef2aSThomas Huth 991fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 992fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 993fcf5ef2aSThomas Huth { 994fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 995fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 996fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 997fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 998fcf5ef2aSThomas Huth 999fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1000fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1001fcf5ef2aSThomas Huth if (sign) { 1002fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1003fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1004fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1005fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1006fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1007fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1008fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1009fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1010fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1011fcf5ef2aSThomas Huth } else { 1012fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1013fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1014fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1015fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1016fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1017fcf5ef2aSThomas Huth } 1018fcf5ef2aSThomas Huth if (compute_ov) { 1019fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1020c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1021c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1022c44027ffSNikunj A Dadhania } 1023fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1024fcf5ef2aSThomas Huth } 1025fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1026fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1027fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1028fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1029fcf5ef2aSThomas Huth 1030efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1031fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1032fcf5ef2aSThomas Huth } 1033efe843d8SDavid Gibson } 1034fcf5ef2aSThomas Huth /* Div functions */ 1035fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1036fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1037fcf5ef2aSThomas Huth { \ 1038fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1039fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1040fcf5ef2aSThomas Huth sign, compute_ov); \ 1041fcf5ef2aSThomas Huth } 1042fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1043fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1044fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1045fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1046fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1047fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1048fcf5ef2aSThomas Huth 1049fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1050fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1051fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1052fcf5ef2aSThomas Huth { \ 1053fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1054fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1055fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1056fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1057fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1058fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1059fcf5ef2aSThomas Huth } \ 1060fcf5ef2aSThomas Huth } 1061fcf5ef2aSThomas Huth 1062fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1063fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1064fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1065fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1066fcf5ef2aSThomas Huth 1067fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1068fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1069fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1070fcf5ef2aSThomas Huth { 1071fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1072fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1073fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1074fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1075fcf5ef2aSThomas Huth 1076fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1077fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1078fcf5ef2aSThomas Huth if (sign) { 1079fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1080fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1081fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1082fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1083fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1084fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1085fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1086fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1087fcf5ef2aSThomas Huth } else { 1088fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1089fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1090fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1091fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1092fcf5ef2aSThomas Huth } 1093fcf5ef2aSThomas Huth if (compute_ov) { 1094fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1095c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1096c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1097c44027ffSNikunj A Dadhania } 1098fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1099fcf5ef2aSThomas Huth } 1100fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1101fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1102fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1103fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1104fcf5ef2aSThomas Huth 1105efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1106fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1107fcf5ef2aSThomas Huth } 1108efe843d8SDavid Gibson } 1109fcf5ef2aSThomas Huth 1110fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1111fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1112fcf5ef2aSThomas Huth { \ 1113fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1114fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1115fcf5ef2aSThomas Huth sign, compute_ov); \ 1116fcf5ef2aSThomas Huth } 1117c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1118fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1119fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1120c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1121fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1122fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1123fcf5ef2aSThomas Huth 1124fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1125fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1126fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1127fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1128fcf5ef2aSThomas Huth #endif 1129fcf5ef2aSThomas Huth 1130fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1131fcf5ef2aSThomas Huth TCGv arg2, int sign) 1132fcf5ef2aSThomas Huth { 1133fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1134fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1135fcf5ef2aSThomas Huth 1136fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1137fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1138fcf5ef2aSThomas Huth if (sign) { 1139fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1140fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1141fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1142fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1143fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1144fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1145fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1146fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1147fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1148fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1149fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1150fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1151fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1152fcf5ef2aSThomas Huth } else { 1153fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1154fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1155fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1156fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1157fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1158fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1159fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1160fcf5ef2aSThomas Huth } 1161fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1162fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1163fcf5ef2aSThomas Huth } 1164fcf5ef2aSThomas Huth 1165fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1166fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1167fcf5ef2aSThomas Huth { \ 1168fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1169fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1170fcf5ef2aSThomas Huth sign); \ 1171fcf5ef2aSThomas Huth } 1172fcf5ef2aSThomas Huth 1173fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1174fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1175fcf5ef2aSThomas Huth 1176fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1177fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1178fcf5ef2aSThomas Huth TCGv arg2, int sign) 1179fcf5ef2aSThomas Huth { 1180fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1181fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1182fcf5ef2aSThomas Huth 1183fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1184fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1185fcf5ef2aSThomas Huth if (sign) { 1186fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1187fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1188fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1189fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1190fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1191fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1192fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1193fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1194fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1195fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1196fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1197fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1198fcf5ef2aSThomas Huth } else { 1199fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1200fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1201fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1202fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1203fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1204fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1205fcf5ef2aSThomas Huth } 1206fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1207fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1208fcf5ef2aSThomas Huth } 1209fcf5ef2aSThomas Huth 1210fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1211fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1212fcf5ef2aSThomas Huth { \ 1213fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1214fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1215fcf5ef2aSThomas Huth sign); \ 1216fcf5ef2aSThomas Huth } 1217fcf5ef2aSThomas Huth 1218fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1219fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1220fcf5ef2aSThomas Huth #endif 1221fcf5ef2aSThomas Huth 1222fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1223fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1224fcf5ef2aSThomas Huth { 1225fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1226fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1227fcf5ef2aSThomas Huth 1228fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1229fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1230fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1231fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1232fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1233fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1234efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1235fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1236fcf5ef2aSThomas Huth } 1237efe843d8SDavid Gibson } 1238fcf5ef2aSThomas Huth 1239fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1240fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1241fcf5ef2aSThomas Huth { 1242fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1243fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1244fcf5ef2aSThomas Huth 1245fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1246fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1247fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1248fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1249fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1250fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1251efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1252fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1253fcf5ef2aSThomas Huth } 1254efe843d8SDavid Gibson } 1255fcf5ef2aSThomas Huth 1256fcf5ef2aSThomas Huth /* mullw mullw. */ 1257fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1258fcf5ef2aSThomas Huth { 1259fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1260fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1261fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1262fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1263fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1264fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1265fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1266fcf5ef2aSThomas Huth tcg_temp_free(t0); 1267fcf5ef2aSThomas Huth tcg_temp_free(t1); 1268fcf5ef2aSThomas Huth #else 1269fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1270fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1271fcf5ef2aSThomas Huth #endif 1272efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1273fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1274fcf5ef2aSThomas Huth } 1275efe843d8SDavid Gibson } 1276fcf5ef2aSThomas Huth 1277fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1278fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1279fcf5ef2aSThomas Huth { 1280fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1281fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1282fcf5ef2aSThomas Huth 1283fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1284fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1285fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1286fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1287fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1288fcf5ef2aSThomas Huth #else 1289fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1290fcf5ef2aSThomas Huth #endif 1291fcf5ef2aSThomas Huth 1292fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1293fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1294fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 129561aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 129661aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 129761aa9a69SNikunj A Dadhania } 1298fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1299fcf5ef2aSThomas Huth 1300fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1301fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1302efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1303fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1304fcf5ef2aSThomas Huth } 1305efe843d8SDavid Gibson } 1306fcf5ef2aSThomas Huth 1307fcf5ef2aSThomas Huth /* mulli */ 1308fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1309fcf5ef2aSThomas Huth { 1310fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1311fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1312fcf5ef2aSThomas Huth } 1313fcf5ef2aSThomas Huth 1314fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1315fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1316fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1317fcf5ef2aSThomas Huth { 1318fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1319fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1320fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1321fcf5ef2aSThomas Huth tcg_temp_free(lo); 1322fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1323fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1324fcf5ef2aSThomas Huth } 1325fcf5ef2aSThomas Huth } 1326fcf5ef2aSThomas Huth 1327fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1328fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1329fcf5ef2aSThomas Huth { 1330fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1331fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1332fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1333fcf5ef2aSThomas Huth tcg_temp_free(lo); 1334fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1335fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1336fcf5ef2aSThomas Huth } 1337fcf5ef2aSThomas Huth } 1338fcf5ef2aSThomas Huth 1339fcf5ef2aSThomas Huth /* mulld mulld. */ 1340fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1341fcf5ef2aSThomas Huth { 1342fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1343fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1344efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1345fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1346fcf5ef2aSThomas Huth } 1347efe843d8SDavid Gibson } 1348fcf5ef2aSThomas Huth 1349fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1350fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1351fcf5ef2aSThomas Huth { 1352fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1353fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1354fcf5ef2aSThomas Huth 1355fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1356fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1357fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1358fcf5ef2aSThomas Huth 1359fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1360fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 136161aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 136261aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 136361aa9a69SNikunj A Dadhania } 1364fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1365fcf5ef2aSThomas Huth 1366fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1367fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1368fcf5ef2aSThomas Huth 1369fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1370fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1371fcf5ef2aSThomas Huth } 1372fcf5ef2aSThomas Huth } 1373fcf5ef2aSThomas Huth #endif 1374fcf5ef2aSThomas Huth 1375fcf5ef2aSThomas Huth /* Common subf function */ 1376fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1377fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1378fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1379fcf5ef2aSThomas Huth { 1380fcf5ef2aSThomas Huth TCGv t0 = ret; 1381fcf5ef2aSThomas Huth 1382fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1383fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1384fcf5ef2aSThomas Huth } 1385fcf5ef2aSThomas Huth 1386fcf5ef2aSThomas Huth if (compute_ca) { 1387fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1388fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1389efe843d8SDavid Gibson /* 1390efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1391efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1392efe843d8SDavid Gibson * produce the carry into bit 32. 1393efe843d8SDavid Gibson */ 1394fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1395fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1396fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1397fcf5ef2aSThomas Huth if (add_ca) { 1398fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1399fcf5ef2aSThomas Huth } else { 1400fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1401fcf5ef2aSThomas Huth } 1402fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1403fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1404fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1405fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1406fcf5ef2aSThomas Huth tcg_temp_free(t1); 1407e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 140833903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 140933903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 141033903d0aSNikunj A Dadhania } 1411fcf5ef2aSThomas Huth } else if (add_ca) { 1412fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1413fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1414fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1415fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1416fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 14174c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 1418fcf5ef2aSThomas Huth tcg_temp_free(zero); 1419fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1420fcf5ef2aSThomas Huth } else { 1421fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1422fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 14234c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 1424fcf5ef2aSThomas Huth } 1425fcf5ef2aSThomas Huth } else if (add_ca) { 1426efe843d8SDavid Gibson /* 1427efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 1428efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 1429efe843d8SDavid Gibson */ 1430fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1431fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1432fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1433fcf5ef2aSThomas Huth } else { 1434fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1435fcf5ef2aSThomas Huth } 1436fcf5ef2aSThomas Huth 1437fcf5ef2aSThomas Huth if (compute_ov) { 1438fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1439fcf5ef2aSThomas Huth } 1440fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1441fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1442fcf5ef2aSThomas Huth } 1443fcf5ef2aSThomas Huth 144411f4e8f8SRichard Henderson if (t0 != ret) { 1445fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1446fcf5ef2aSThomas Huth tcg_temp_free(t0); 1447fcf5ef2aSThomas Huth } 1448fcf5ef2aSThomas Huth } 1449fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1450fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1451fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1452fcf5ef2aSThomas Huth { \ 1453fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1454fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1455fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1456fcf5ef2aSThomas Huth } 1457fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1458fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1459fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1460fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1461fcf5ef2aSThomas Huth { \ 1462fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1463fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1464fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1465fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1466fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1467fcf5ef2aSThomas Huth } 1468fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1469fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1470fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1471fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1472fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1473fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1474fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1475fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1476fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1477fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1478fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1479fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1480fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1481fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1482fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1483fcf5ef2aSThomas Huth 1484fcf5ef2aSThomas Huth /* subfic */ 1485fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1486fcf5ef2aSThomas Huth { 1487fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1488fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1489fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1490fcf5ef2aSThomas Huth tcg_temp_free(c); 1491fcf5ef2aSThomas Huth } 1492fcf5ef2aSThomas Huth 1493fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1494fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1495fcf5ef2aSThomas Huth { 1496fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1497fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1498fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1499fcf5ef2aSThomas Huth tcg_temp_free(zero); 1500fcf5ef2aSThomas Huth } 1501fcf5ef2aSThomas Huth 1502fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1503fcf5ef2aSThomas Huth { 15041480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 15051480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 15061480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 15071480d71cSNikunj A Dadhania } 1508fcf5ef2aSThomas Huth } 1509fcf5ef2aSThomas Huth 1510fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1511fcf5ef2aSThomas Huth { 1512fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1513fcf5ef2aSThomas Huth } 1514fcf5ef2aSThomas Huth 1515fcf5ef2aSThomas Huth /*** Integer logical ***/ 1516fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1517fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1518fcf5ef2aSThomas Huth { \ 1519fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1520fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1521fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1522fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1523fcf5ef2aSThomas Huth } 1524fcf5ef2aSThomas Huth 1525fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1526fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1527fcf5ef2aSThomas Huth { \ 1528fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1529fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1530fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1531fcf5ef2aSThomas Huth } 1532fcf5ef2aSThomas Huth 1533fcf5ef2aSThomas Huth /* and & and. */ 1534fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1535fcf5ef2aSThomas Huth /* andc & andc. */ 1536fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1537fcf5ef2aSThomas Huth 1538fcf5ef2aSThomas Huth /* andi. */ 1539fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1540fcf5ef2aSThomas Huth { 1541efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1542efe843d8SDavid Gibson UIMM(ctx->opcode)); 1543fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1544fcf5ef2aSThomas Huth } 1545fcf5ef2aSThomas Huth 1546fcf5ef2aSThomas Huth /* andis. */ 1547fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1548fcf5ef2aSThomas Huth { 1549efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1550efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 1551fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1552fcf5ef2aSThomas Huth } 1553fcf5ef2aSThomas Huth 1554fcf5ef2aSThomas Huth /* cntlzw */ 1555fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1556fcf5ef2aSThomas Huth { 15579b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15589b8514e5SRichard Henderson 15599b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15609b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15619b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15629b8514e5SRichard Henderson tcg_temp_free_i32(t); 15639b8514e5SRichard Henderson 1564efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1565fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1566fcf5ef2aSThomas Huth } 1567efe843d8SDavid Gibson } 1568fcf5ef2aSThomas Huth 1569fcf5ef2aSThomas Huth /* cnttzw */ 1570fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1571fcf5ef2aSThomas Huth { 15729b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15739b8514e5SRichard Henderson 15749b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15759b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15769b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15779b8514e5SRichard Henderson tcg_temp_free_i32(t); 15789b8514e5SRichard Henderson 1579fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1580fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1581fcf5ef2aSThomas Huth } 1582fcf5ef2aSThomas Huth } 1583fcf5ef2aSThomas Huth 1584fcf5ef2aSThomas Huth /* eqv & eqv. */ 1585fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1586fcf5ef2aSThomas Huth /* extsb & extsb. */ 1587fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1588fcf5ef2aSThomas Huth /* extsh & extsh. */ 1589fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1590fcf5ef2aSThomas Huth /* nand & nand. */ 1591fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1592fcf5ef2aSThomas Huth /* nor & nor. */ 1593fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1594fcf5ef2aSThomas Huth 1595fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1596fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1597fcf5ef2aSThomas Huth { 1598fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1599fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1600fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1601fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1602fcf5ef2aSThomas Huth 1603fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1604b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1605fcf5ef2aSThomas Huth } 1606fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1607fcf5ef2aSThomas Huth 1608fcf5ef2aSThomas Huth /* or & or. */ 1609fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1610fcf5ef2aSThomas Huth { 1611fcf5ef2aSThomas Huth int rs, ra, rb; 1612fcf5ef2aSThomas Huth 1613fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1614fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1615fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1616fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1617fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1618efe843d8SDavid Gibson if (rs != rb) { 1619fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1620efe843d8SDavid Gibson } else { 1621fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1622efe843d8SDavid Gibson } 1623efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1624fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1625efe843d8SDavid Gibson } 1626fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1627fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1628fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1629fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1630fcf5ef2aSThomas Huth int prio = 0; 1631fcf5ef2aSThomas Huth 1632fcf5ef2aSThomas Huth switch (rs) { 1633fcf5ef2aSThomas Huth case 1: 1634fcf5ef2aSThomas Huth /* Set process priority to low */ 1635fcf5ef2aSThomas Huth prio = 2; 1636fcf5ef2aSThomas Huth break; 1637fcf5ef2aSThomas Huth case 6: 1638fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1639fcf5ef2aSThomas Huth prio = 3; 1640fcf5ef2aSThomas Huth break; 1641fcf5ef2aSThomas Huth case 2: 1642fcf5ef2aSThomas Huth /* Set process priority to normal */ 1643fcf5ef2aSThomas Huth prio = 4; 1644fcf5ef2aSThomas Huth break; 1645fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1646fcf5ef2aSThomas Huth case 31: 1647fcf5ef2aSThomas Huth if (!ctx->pr) { 1648fcf5ef2aSThomas Huth /* Set process priority to very low */ 1649fcf5ef2aSThomas Huth prio = 1; 1650fcf5ef2aSThomas Huth } 1651fcf5ef2aSThomas Huth break; 1652fcf5ef2aSThomas Huth case 5: 1653fcf5ef2aSThomas Huth if (!ctx->pr) { 1654fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1655fcf5ef2aSThomas Huth prio = 5; 1656fcf5ef2aSThomas Huth } 1657fcf5ef2aSThomas Huth break; 1658fcf5ef2aSThomas Huth case 3: 1659fcf5ef2aSThomas Huth if (!ctx->pr) { 1660fcf5ef2aSThomas Huth /* Set process priority to high */ 1661fcf5ef2aSThomas Huth prio = 6; 1662fcf5ef2aSThomas Huth } 1663fcf5ef2aSThomas Huth break; 1664fcf5ef2aSThomas Huth case 7: 1665fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1666fcf5ef2aSThomas Huth /* Set process priority to very high */ 1667fcf5ef2aSThomas Huth prio = 7; 1668fcf5ef2aSThomas Huth } 1669fcf5ef2aSThomas Huth break; 1670fcf5ef2aSThomas Huth #endif 1671fcf5ef2aSThomas Huth default: 1672fcf5ef2aSThomas Huth break; 1673fcf5ef2aSThomas Huth } 1674fcf5ef2aSThomas Huth if (prio) { 1675fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1676fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1677fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1678fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1679fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1680fcf5ef2aSThomas Huth tcg_temp_free(t0); 1681fcf5ef2aSThomas Huth } 1682fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1683efe843d8SDavid Gibson /* 1684efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 1685efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 1686efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 1687efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 1688fcf5ef2aSThomas Huth */ 1689fcf5ef2aSThomas Huth gen_pause(ctx); 1690fcf5ef2aSThomas Huth #endif 1691fcf5ef2aSThomas Huth #endif 1692fcf5ef2aSThomas Huth } 1693fcf5ef2aSThomas Huth } 1694fcf5ef2aSThomas Huth /* orc & orc. */ 1695fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1696fcf5ef2aSThomas Huth 1697fcf5ef2aSThomas Huth /* xor & xor. */ 1698fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1699fcf5ef2aSThomas Huth { 1700fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1701efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 1702efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1703efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 1704efe843d8SDavid Gibson } else { 1705fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1706efe843d8SDavid Gibson } 1707efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1708fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1709fcf5ef2aSThomas Huth } 1710efe843d8SDavid Gibson } 1711fcf5ef2aSThomas Huth 1712fcf5ef2aSThomas Huth /* ori */ 1713fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1714fcf5ef2aSThomas Huth { 1715fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1716fcf5ef2aSThomas Huth 1717fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1718fcf5ef2aSThomas Huth return; 1719fcf5ef2aSThomas Huth } 1720fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1721fcf5ef2aSThomas Huth } 1722fcf5ef2aSThomas Huth 1723fcf5ef2aSThomas Huth /* oris */ 1724fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1725fcf5ef2aSThomas Huth { 1726fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1727fcf5ef2aSThomas Huth 1728fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1729fcf5ef2aSThomas Huth /* NOP */ 1730fcf5ef2aSThomas Huth return; 1731fcf5ef2aSThomas Huth } 1732efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1733efe843d8SDavid Gibson uimm << 16); 1734fcf5ef2aSThomas Huth } 1735fcf5ef2aSThomas Huth 1736fcf5ef2aSThomas Huth /* xori */ 1737fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1738fcf5ef2aSThomas Huth { 1739fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1740fcf5ef2aSThomas Huth 1741fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1742fcf5ef2aSThomas Huth /* NOP */ 1743fcf5ef2aSThomas Huth return; 1744fcf5ef2aSThomas Huth } 1745fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1746fcf5ef2aSThomas Huth } 1747fcf5ef2aSThomas Huth 1748fcf5ef2aSThomas Huth /* xoris */ 1749fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1750fcf5ef2aSThomas Huth { 1751fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1752fcf5ef2aSThomas Huth 1753fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1754fcf5ef2aSThomas Huth /* NOP */ 1755fcf5ef2aSThomas Huth return; 1756fcf5ef2aSThomas Huth } 1757efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1758efe843d8SDavid Gibson uimm << 16); 1759fcf5ef2aSThomas Huth } 1760fcf5ef2aSThomas Huth 1761fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1762fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1763fcf5ef2aSThomas Huth { 1764fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1765fcf5ef2aSThomas Huth } 1766fcf5ef2aSThomas Huth 1767fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1768fcf5ef2aSThomas Huth { 176979770002SRichard Henderson #if defined(TARGET_PPC64) 1770fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 177179770002SRichard Henderson #else 177279770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 177379770002SRichard Henderson #endif 1774fcf5ef2aSThomas Huth } 1775fcf5ef2aSThomas Huth 1776fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1777fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1778fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1779fcf5ef2aSThomas Huth { 178079770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1781fcf5ef2aSThomas Huth } 1782fcf5ef2aSThomas Huth #endif 1783fcf5ef2aSThomas Huth 1784fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1785fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1786fcf5ef2aSThomas Huth { 1787fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1788fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1789fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1790fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1791fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1792fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1793fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1794fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1795fcf5ef2aSThomas Huth tcg_temp_free(t0); 1796fcf5ef2aSThomas Huth } 1797fcf5ef2aSThomas Huth 1798fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1799fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1800fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1801fcf5ef2aSThomas Huth { 1802fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1803fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1804fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1805fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1806fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1807fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1808fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1809fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1810fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1811fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1812fcf5ef2aSThomas Huth tcg_temp_free(t0); 1813fcf5ef2aSThomas Huth } 1814fcf5ef2aSThomas Huth #endif 1815fcf5ef2aSThomas Huth 1816fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1817fcf5ef2aSThomas Huth /* bpermd */ 1818fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1819fcf5ef2aSThomas Huth { 1820fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1821fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1822fcf5ef2aSThomas Huth } 1823fcf5ef2aSThomas Huth #endif 1824fcf5ef2aSThomas Huth 1825fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1826fcf5ef2aSThomas Huth /* extsw & extsw. */ 1827fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1828fcf5ef2aSThomas Huth 1829fcf5ef2aSThomas Huth /* cntlzd */ 1830fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1831fcf5ef2aSThomas Huth { 18329b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1833efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1834fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1835fcf5ef2aSThomas Huth } 1836efe843d8SDavid Gibson } 1837fcf5ef2aSThomas Huth 1838fcf5ef2aSThomas Huth /* cnttzd */ 1839fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1840fcf5ef2aSThomas Huth { 18419b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1842fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1843fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1844fcf5ef2aSThomas Huth } 1845fcf5ef2aSThomas Huth } 1846fcf5ef2aSThomas Huth 1847fcf5ef2aSThomas Huth /* darn */ 1848fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1849fcf5ef2aSThomas Huth { 1850fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1851fcf5ef2aSThomas Huth 18527e4357f6SRichard Henderson if (l > 2) { 18537e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 18547e4357f6SRichard Henderson } else { 18557e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 18567e4357f6SRichard Henderson gen_io_start(); 18577e4357f6SRichard Henderson } 1858fcf5ef2aSThomas Huth if (l == 0) { 1859fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 18607e4357f6SRichard Henderson } else { 1861fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1862fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 18637e4357f6SRichard Henderson } 18647e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 18657e4357f6SRichard Henderson gen_stop_exception(ctx); 18667e4357f6SRichard Henderson } 1867fcf5ef2aSThomas Huth } 1868fcf5ef2aSThomas Huth } 1869fcf5ef2aSThomas Huth #endif 1870fcf5ef2aSThomas Huth 1871fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1872fcf5ef2aSThomas Huth 1873fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1874fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1875fcf5ef2aSThomas Huth { 1876fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1877fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1878fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1879fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1880fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1881fcf5ef2aSThomas Huth 1882fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 1883fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1884fcf5ef2aSThomas Huth } else { 1885fcf5ef2aSThomas Huth target_ulong mask; 1886c4f6a4a3SDaniele Buono bool mask_in_32b = true; 1887fcf5ef2aSThomas Huth TCGv t1; 1888fcf5ef2aSThomas Huth 1889fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1890fcf5ef2aSThomas Huth mb += 32; 1891fcf5ef2aSThomas Huth me += 32; 1892fcf5ef2aSThomas Huth #endif 1893fcf5ef2aSThomas Huth mask = MASK(mb, me); 1894fcf5ef2aSThomas Huth 1895c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 1896c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 1897c4f6a4a3SDaniele Buono mask_in_32b = false; 1898c4f6a4a3SDaniele Buono } 1899c4f6a4a3SDaniele Buono #endif 1900fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1901c4f6a4a3SDaniele Buono if (mask_in_32b) { 1902fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1903fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1904fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1905fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1906fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1907fcf5ef2aSThomas Huth } else { 1908fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1909fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1910fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1911fcf5ef2aSThomas Huth #else 1912fcf5ef2aSThomas Huth g_assert_not_reached(); 1913fcf5ef2aSThomas Huth #endif 1914fcf5ef2aSThomas Huth } 1915fcf5ef2aSThomas Huth 1916fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1917fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1918fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1919fcf5ef2aSThomas Huth tcg_temp_free(t1); 1920fcf5ef2aSThomas Huth } 1921fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1922fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1923fcf5ef2aSThomas Huth } 1924fcf5ef2aSThomas Huth } 1925fcf5ef2aSThomas Huth 1926fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1927fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1928fcf5ef2aSThomas Huth { 1929fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1930fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 19317b4d326fSRichard Henderson int sh = SH(ctx->opcode); 19327b4d326fSRichard Henderson int mb = MB(ctx->opcode); 19337b4d326fSRichard Henderson int me = ME(ctx->opcode); 19347b4d326fSRichard Henderson int len = me - mb + 1; 19357b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1936fcf5ef2aSThomas Huth 19377b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 19387b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 19397b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 19407b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1941fcf5ef2aSThomas Huth } else { 1942fcf5ef2aSThomas Huth target_ulong mask; 1943c4f6a4a3SDaniele Buono bool mask_in_32b = true; 1944fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1945fcf5ef2aSThomas Huth mb += 32; 1946fcf5ef2aSThomas Huth me += 32; 1947fcf5ef2aSThomas Huth #endif 1948fcf5ef2aSThomas Huth mask = MASK(mb, me); 1949c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 1950c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 1951c4f6a4a3SDaniele Buono mask_in_32b = false; 1952c4f6a4a3SDaniele Buono } 1953c4f6a4a3SDaniele Buono #endif 1954c4f6a4a3SDaniele Buono if (mask_in_32b) { 19557b4d326fSRichard Henderson if (sh == 0) { 19567b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 195794f040aaSVitaly Chikunov } else { 1958fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1959fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1960fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1961fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1962fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1963fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 196494f040aaSVitaly Chikunov } 1965fcf5ef2aSThomas Huth } else { 1966fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1967fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1968fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1969fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1970fcf5ef2aSThomas Huth #else 1971fcf5ef2aSThomas Huth g_assert_not_reached(); 1972fcf5ef2aSThomas Huth #endif 1973fcf5ef2aSThomas Huth } 1974fcf5ef2aSThomas Huth } 1975fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1976fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1977fcf5ef2aSThomas Huth } 1978fcf5ef2aSThomas Huth } 1979fcf5ef2aSThomas Huth 1980fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1981fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1982fcf5ef2aSThomas Huth { 1983fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1984fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1985fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1986fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1987fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1988fcf5ef2aSThomas Huth target_ulong mask; 1989c4f6a4a3SDaniele Buono bool mask_in_32b = true; 1990fcf5ef2aSThomas Huth 1991fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1992fcf5ef2aSThomas Huth mb += 32; 1993fcf5ef2aSThomas Huth me += 32; 1994fcf5ef2aSThomas Huth #endif 1995fcf5ef2aSThomas Huth mask = MASK(mb, me); 1996fcf5ef2aSThomas Huth 1997c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 1998c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 1999c4f6a4a3SDaniele Buono mask_in_32b = false; 2000c4f6a4a3SDaniele Buono } 2001c4f6a4a3SDaniele Buono #endif 2002c4f6a4a3SDaniele Buono if (mask_in_32b) { 2003fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2004fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2005fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2006fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2007fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2008fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2009fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2010fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2011fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2012fcf5ef2aSThomas Huth } else { 2013fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2014fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2015fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2016fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2017fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2018fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2019fcf5ef2aSThomas Huth #else 2020fcf5ef2aSThomas Huth g_assert_not_reached(); 2021fcf5ef2aSThomas Huth #endif 2022fcf5ef2aSThomas Huth } 2023fcf5ef2aSThomas Huth 2024fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2025fcf5ef2aSThomas Huth 2026fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2027fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2028fcf5ef2aSThomas Huth } 2029fcf5ef2aSThomas Huth } 2030fcf5ef2aSThomas Huth 2031fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2032fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2033fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2034fcf5ef2aSThomas Huth { \ 2035fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2036fcf5ef2aSThomas Huth } \ 2037fcf5ef2aSThomas Huth \ 2038fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2039fcf5ef2aSThomas Huth { \ 2040fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2041fcf5ef2aSThomas Huth } 2042fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2043fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2044fcf5ef2aSThomas Huth { \ 2045fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2046fcf5ef2aSThomas Huth } \ 2047fcf5ef2aSThomas Huth \ 2048fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2049fcf5ef2aSThomas Huth { \ 2050fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2051fcf5ef2aSThomas Huth } \ 2052fcf5ef2aSThomas Huth \ 2053fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2054fcf5ef2aSThomas Huth { \ 2055fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2056fcf5ef2aSThomas Huth } \ 2057fcf5ef2aSThomas Huth \ 2058fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2059fcf5ef2aSThomas Huth { \ 2060fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2061fcf5ef2aSThomas Huth } 2062fcf5ef2aSThomas Huth 2063fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2064fcf5ef2aSThomas Huth { 2065fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2066fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20677b4d326fSRichard Henderson int len = me - mb + 1; 20687b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2069fcf5ef2aSThomas Huth 20707b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20717b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20727b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20737b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2074fcf5ef2aSThomas Huth } else { 2075fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2076fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2077fcf5ef2aSThomas Huth } 2078fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2079fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2080fcf5ef2aSThomas Huth } 2081fcf5ef2aSThomas Huth } 2082fcf5ef2aSThomas Huth 2083fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2084fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2085fcf5ef2aSThomas Huth { 2086fcf5ef2aSThomas Huth uint32_t sh, mb; 2087fcf5ef2aSThomas Huth 2088fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2089fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2090fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2091fcf5ef2aSThomas Huth } 2092fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2093fcf5ef2aSThomas Huth 2094fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2095fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2096fcf5ef2aSThomas Huth { 2097fcf5ef2aSThomas Huth uint32_t sh, me; 2098fcf5ef2aSThomas Huth 2099fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2100fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2101fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2102fcf5ef2aSThomas Huth } 2103fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2104fcf5ef2aSThomas Huth 2105fcf5ef2aSThomas Huth /* rldic - rldic. */ 2106fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2107fcf5ef2aSThomas Huth { 2108fcf5ef2aSThomas Huth uint32_t sh, mb; 2109fcf5ef2aSThomas Huth 2110fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2111fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2112fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2113fcf5ef2aSThomas Huth } 2114fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2115fcf5ef2aSThomas Huth 2116fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2117fcf5ef2aSThomas Huth { 2118fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2119fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2120fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2121fcf5ef2aSThomas Huth TCGv t0; 2122fcf5ef2aSThomas Huth 2123fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2124fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2125fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2126fcf5ef2aSThomas Huth tcg_temp_free(t0); 2127fcf5ef2aSThomas Huth 2128fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2129fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2130fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2131fcf5ef2aSThomas Huth } 2132fcf5ef2aSThomas Huth } 2133fcf5ef2aSThomas Huth 2134fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2135fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2136fcf5ef2aSThomas Huth { 2137fcf5ef2aSThomas Huth uint32_t mb; 2138fcf5ef2aSThomas Huth 2139fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2140fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2141fcf5ef2aSThomas Huth } 2142fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2143fcf5ef2aSThomas Huth 2144fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2145fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2146fcf5ef2aSThomas Huth { 2147fcf5ef2aSThomas Huth uint32_t me; 2148fcf5ef2aSThomas Huth 2149fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2150fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2151fcf5ef2aSThomas Huth } 2152fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2153fcf5ef2aSThomas Huth 2154fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2155fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2156fcf5ef2aSThomas Huth { 2157fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2158fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2159fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2160fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2161fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2162fcf5ef2aSThomas Huth 2163fcf5ef2aSThomas Huth if (mb <= me) { 2164fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2165fcf5ef2aSThomas Huth } else { 2166fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2167fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2168fcf5ef2aSThomas Huth 2169fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2170fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2171fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2172fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2173fcf5ef2aSThomas Huth tcg_temp_free(t1); 2174fcf5ef2aSThomas Huth } 2175fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2176fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2177fcf5ef2aSThomas Huth } 2178fcf5ef2aSThomas Huth } 2179fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2180fcf5ef2aSThomas Huth #endif 2181fcf5ef2aSThomas Huth 2182fcf5ef2aSThomas Huth /*** Integer shift ***/ 2183fcf5ef2aSThomas Huth 2184fcf5ef2aSThomas Huth /* slw & slw. */ 2185fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2186fcf5ef2aSThomas Huth { 2187fcf5ef2aSThomas Huth TCGv t0, t1; 2188fcf5ef2aSThomas Huth 2189fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2190fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2191fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2192fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2193fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2194fcf5ef2aSThomas Huth #else 2195fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2196fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2197fcf5ef2aSThomas Huth #endif 2198fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2199fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2200fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2201fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2202fcf5ef2aSThomas Huth tcg_temp_free(t1); 2203fcf5ef2aSThomas Huth tcg_temp_free(t0); 2204fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2205efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2206fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2207fcf5ef2aSThomas Huth } 2208efe843d8SDavid Gibson } 2209fcf5ef2aSThomas Huth 2210fcf5ef2aSThomas Huth /* sraw & sraw. */ 2211fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2212fcf5ef2aSThomas Huth { 2213fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2214fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2215efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2216fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2217fcf5ef2aSThomas Huth } 2218efe843d8SDavid Gibson } 2219fcf5ef2aSThomas Huth 2220fcf5ef2aSThomas Huth /* srawi & srawi. */ 2221fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2222fcf5ef2aSThomas Huth { 2223fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2224fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2225fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2226fcf5ef2aSThomas Huth if (sh == 0) { 2227fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2228fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2229af1c259fSSandipan Das if (is_isa300(ctx)) { 2230af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2231af1c259fSSandipan Das } 2232fcf5ef2aSThomas Huth } else { 2233fcf5ef2aSThomas Huth TCGv t0; 2234fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2235fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2236fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2237fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2238fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2239fcf5ef2aSThomas Huth tcg_temp_free(t0); 2240fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2241af1c259fSSandipan Das if (is_isa300(ctx)) { 2242af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2243af1c259fSSandipan Das } 2244fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2245fcf5ef2aSThomas Huth } 2246fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2247fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2248fcf5ef2aSThomas Huth } 2249fcf5ef2aSThomas Huth } 2250fcf5ef2aSThomas Huth 2251fcf5ef2aSThomas Huth /* srw & srw. */ 2252fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2253fcf5ef2aSThomas Huth { 2254fcf5ef2aSThomas Huth TCGv t0, t1; 2255fcf5ef2aSThomas Huth 2256fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2257fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2258fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2259fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2260fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2261fcf5ef2aSThomas Huth #else 2262fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2263fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2264fcf5ef2aSThomas Huth #endif 2265fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2266fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2267fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2268fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2269fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2270fcf5ef2aSThomas Huth tcg_temp_free(t1); 2271fcf5ef2aSThomas Huth tcg_temp_free(t0); 2272efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2273fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2274fcf5ef2aSThomas Huth } 2275efe843d8SDavid Gibson } 2276fcf5ef2aSThomas Huth 2277fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2278fcf5ef2aSThomas Huth /* sld & sld. */ 2279fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2280fcf5ef2aSThomas Huth { 2281fcf5ef2aSThomas Huth TCGv t0, t1; 2282fcf5ef2aSThomas Huth 2283fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2284fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2285fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2286fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2287fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2288fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2289fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2290fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2291fcf5ef2aSThomas Huth tcg_temp_free(t1); 2292fcf5ef2aSThomas Huth tcg_temp_free(t0); 2293efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2294fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2295fcf5ef2aSThomas Huth } 2296efe843d8SDavid Gibson } 2297fcf5ef2aSThomas Huth 2298fcf5ef2aSThomas Huth /* srad & srad. */ 2299fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2300fcf5ef2aSThomas Huth { 2301fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2302fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2303efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2304fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2305fcf5ef2aSThomas Huth } 2306efe843d8SDavid Gibson } 2307fcf5ef2aSThomas Huth /* sradi & sradi. */ 2308fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2309fcf5ef2aSThomas Huth { 2310fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2311fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2312fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2313fcf5ef2aSThomas Huth if (sh == 0) { 2314fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2315fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2316af1c259fSSandipan Das if (is_isa300(ctx)) { 2317af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2318af1c259fSSandipan Das } 2319fcf5ef2aSThomas Huth } else { 2320fcf5ef2aSThomas Huth TCGv t0; 2321fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2322fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2323fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2324fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2325fcf5ef2aSThomas Huth tcg_temp_free(t0); 2326fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2327af1c259fSSandipan Das if (is_isa300(ctx)) { 2328af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2329af1c259fSSandipan Das } 2330fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2331fcf5ef2aSThomas Huth } 2332fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2333fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2334fcf5ef2aSThomas Huth } 2335fcf5ef2aSThomas Huth } 2336fcf5ef2aSThomas Huth 2337fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2338fcf5ef2aSThomas Huth { 2339fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2340fcf5ef2aSThomas Huth } 2341fcf5ef2aSThomas Huth 2342fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2343fcf5ef2aSThomas Huth { 2344fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2345fcf5ef2aSThomas Huth } 2346fcf5ef2aSThomas Huth 2347fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2348fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2349fcf5ef2aSThomas Huth { 2350fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2351fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2352fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2353fcf5ef2aSThomas Huth 2354fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2355fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2356fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2357fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2358fcf5ef2aSThomas Huth } 2359fcf5ef2aSThomas Huth } 2360fcf5ef2aSThomas Huth 2361fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2362fcf5ef2aSThomas Huth { 2363fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2364fcf5ef2aSThomas Huth } 2365fcf5ef2aSThomas Huth 2366fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2367fcf5ef2aSThomas Huth { 2368fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2369fcf5ef2aSThomas Huth } 2370fcf5ef2aSThomas Huth 2371fcf5ef2aSThomas Huth /* srd & srd. */ 2372fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2373fcf5ef2aSThomas Huth { 2374fcf5ef2aSThomas Huth TCGv t0, t1; 2375fcf5ef2aSThomas Huth 2376fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2377fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2378fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2379fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2380fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2381fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2382fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2383fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2384fcf5ef2aSThomas Huth tcg_temp_free(t1); 2385fcf5ef2aSThomas Huth tcg_temp_free(t0); 2386efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2387fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2388fcf5ef2aSThomas Huth } 2389efe843d8SDavid Gibson } 2390fcf5ef2aSThomas Huth #endif 2391fcf5ef2aSThomas Huth 2392fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2393fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2394fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2395fcf5ef2aSThomas Huth target_long maskl) 2396fcf5ef2aSThomas Huth { 2397fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2398fcf5ef2aSThomas Huth 2399fcf5ef2aSThomas Huth simm &= ~maskl; 2400fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2401fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2402fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2403fcf5ef2aSThomas Huth } 2404fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2405fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2406fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2407fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2408fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2409fcf5ef2aSThomas Huth } 2410fcf5ef2aSThomas Huth } else { 2411fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2412fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2413fcf5ef2aSThomas Huth } else { 2414fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2415fcf5ef2aSThomas Huth } 2416fcf5ef2aSThomas Huth } 2417fcf5ef2aSThomas Huth } 2418fcf5ef2aSThomas Huth 2419fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2420fcf5ef2aSThomas Huth { 2421fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2422fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2423fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2424fcf5ef2aSThomas Huth } else { 2425fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2426fcf5ef2aSThomas Huth } 2427fcf5ef2aSThomas Huth } else { 2428fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2429fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2430fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2431fcf5ef2aSThomas Huth } 2432fcf5ef2aSThomas Huth } 2433fcf5ef2aSThomas Huth } 2434fcf5ef2aSThomas Huth 2435fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2436fcf5ef2aSThomas Huth { 2437fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2438fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2439fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2440fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2441fcf5ef2aSThomas Huth } else { 2442fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2443fcf5ef2aSThomas Huth } 2444fcf5ef2aSThomas Huth } 2445fcf5ef2aSThomas Huth 2446fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2447fcf5ef2aSThomas Huth target_long val) 2448fcf5ef2aSThomas Huth { 2449fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2450fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2451fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2452fcf5ef2aSThomas Huth } 2453fcf5ef2aSThomas Huth } 2454fcf5ef2aSThomas Huth 2455fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2456fcf5ef2aSThomas Huth { 2457fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2458fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2459fcf5ef2aSThomas Huth } 2460fcf5ef2aSThomas Huth 2461fcf5ef2aSThomas Huth /*** Integer load ***/ 2462fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2463fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2464fcf5ef2aSThomas Huth 2465fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2466fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2467fcf5ef2aSThomas Huth TCGv val, \ 2468fcf5ef2aSThomas Huth TCGv addr) \ 2469fcf5ef2aSThomas Huth { \ 2470fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2471fcf5ef2aSThomas Huth } 2472fcf5ef2aSThomas Huth 2473fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2474fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2475fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2476fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2477fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2478fcf5ef2aSThomas Huth 2479fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2480fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2481fcf5ef2aSThomas Huth 2482fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2483fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2484fcf5ef2aSThomas Huth TCGv_i64 val, \ 2485fcf5ef2aSThomas Huth TCGv addr) \ 2486fcf5ef2aSThomas Huth { \ 2487fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2488fcf5ef2aSThomas Huth } 2489fcf5ef2aSThomas Huth 2490fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2491fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2492fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2493fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2494fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2495fcf5ef2aSThomas Huth 2496fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2497fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2498fcf5ef2aSThomas Huth #endif 2499fcf5ef2aSThomas Huth 2500fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2501fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2502fcf5ef2aSThomas Huth TCGv val, \ 2503fcf5ef2aSThomas Huth TCGv addr) \ 2504fcf5ef2aSThomas Huth { \ 2505fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2506fcf5ef2aSThomas Huth } 2507fcf5ef2aSThomas Huth 2508fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2509fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2510fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2511fcf5ef2aSThomas Huth 2512fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2513fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2514fcf5ef2aSThomas Huth 2515fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2516fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2517fcf5ef2aSThomas Huth TCGv_i64 val, \ 2518fcf5ef2aSThomas Huth TCGv addr) \ 2519fcf5ef2aSThomas Huth { \ 2520fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2521fcf5ef2aSThomas Huth } 2522fcf5ef2aSThomas Huth 2523fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2524fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2525fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2526fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2527fcf5ef2aSThomas Huth 2528fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2529fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2530fcf5ef2aSThomas Huth #endif 2531fcf5ef2aSThomas Huth 2532fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2533fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2534fcf5ef2aSThomas Huth { \ 2535fcf5ef2aSThomas Huth TCGv EA; \ 2536fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2537fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2538fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2539fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2540fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2541fcf5ef2aSThomas Huth } 2542fcf5ef2aSThomas Huth 2543fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2544fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2545fcf5ef2aSThomas Huth { \ 2546fcf5ef2aSThomas Huth TCGv EA; \ 2547fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2548fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2549fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2550fcf5ef2aSThomas Huth return; \ 2551fcf5ef2aSThomas Huth } \ 2552fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2553fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2554fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2555fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2556fcf5ef2aSThomas Huth else \ 2557fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2558fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2559fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2560fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2561fcf5ef2aSThomas Huth } 2562fcf5ef2aSThomas Huth 2563fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2564fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2565fcf5ef2aSThomas Huth { \ 2566fcf5ef2aSThomas Huth TCGv EA; \ 2567fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2568fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2569fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2570fcf5ef2aSThomas Huth return; \ 2571fcf5ef2aSThomas Huth } \ 2572fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2573fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2574fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2575fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2576fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2577fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2578fcf5ef2aSThomas Huth } 2579fcf5ef2aSThomas Huth 2580fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2581fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2582fcf5ef2aSThomas Huth { \ 2583fcf5ef2aSThomas Huth TCGv EA; \ 2584fcf5ef2aSThomas Huth chk; \ 2585fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2586fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2587fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2588fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2589fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2590fcf5ef2aSThomas Huth } 2591fcf5ef2aSThomas Huth 2592fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2593fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2594fcf5ef2aSThomas Huth 2595fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2596fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2597fcf5ef2aSThomas Huth 2598fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2599fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2600fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2601fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2602fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2603fcf5ef2aSThomas Huth 2604fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2605fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2606fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2607fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2608fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2609fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2610fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2611fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 261250728199SRoman Kapl 261350728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 261450728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 261550728199SRoman Kapl { \ 261650728199SRoman Kapl TCGv EA; \ 261750728199SRoman Kapl CHK_SV; \ 261850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 261950728199SRoman Kapl EA = tcg_temp_new(); \ 262050728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 262150728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 262250728199SRoman Kapl tcg_temp_free(EA); \ 262350728199SRoman Kapl } 262450728199SRoman Kapl 262550728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 262650728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 262750728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 262850728199SRoman Kapl #if defined(TARGET_PPC64) 262950728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 263050728199SRoman Kapl #endif 263150728199SRoman Kapl 2632fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2633fcf5ef2aSThomas Huth /* lwaux */ 2634fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2635fcf5ef2aSThomas Huth /* lwax */ 2636fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2637fcf5ef2aSThomas Huth /* ldux */ 2638fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2639fcf5ef2aSThomas Huth /* ldx */ 2640fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2641fcf5ef2aSThomas Huth 2642fcf5ef2aSThomas Huth /* CI load/store variants */ 2643fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2644fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2645fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2646fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2647fcf5ef2aSThomas Huth 2648fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2649fcf5ef2aSThomas Huth { 2650fcf5ef2aSThomas Huth TCGv EA; 2651fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2652fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2653fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2654fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2655fcf5ef2aSThomas Huth return; 2656fcf5ef2aSThomas Huth } 2657fcf5ef2aSThomas Huth } 2658fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2659fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2660fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2661fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2662fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2663fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2664fcf5ef2aSThomas Huth } else { 2665fcf5ef2aSThomas Huth /* ld - ldu */ 2666fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2667fcf5ef2aSThomas Huth } 2668efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 2669fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2670efe843d8SDavid Gibson } 2671fcf5ef2aSThomas Huth tcg_temp_free(EA); 2672fcf5ef2aSThomas Huth } 2673fcf5ef2aSThomas Huth 2674fcf5ef2aSThomas Huth /* lq */ 2675fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2676fcf5ef2aSThomas Huth { 2677fcf5ef2aSThomas Huth int ra, rd; 267894bf2658SRichard Henderson TCGv EA, hi, lo; 2679fcf5ef2aSThomas Huth 2680fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2681fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2682fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2683fcf5ef2aSThomas Huth 2684fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2685fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2686fcf5ef2aSThomas Huth return; 2687fcf5ef2aSThomas Huth } 2688fcf5ef2aSThomas Huth 2689fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2690fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2691fcf5ef2aSThomas Huth return; 2692fcf5ef2aSThomas Huth } 2693fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2694fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2695fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2696fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2697fcf5ef2aSThomas Huth return; 2698fcf5ef2aSThomas Huth } 2699fcf5ef2aSThomas Huth 2700fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2701fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2702fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2703fcf5ef2aSThomas Huth 270494bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 270594bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 270694bf2658SRichard Henderson hi = cpu_gpr[rd]; 270794bf2658SRichard Henderson 270894bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2709f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 271094bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 271194bf2658SRichard Henderson if (ctx->le_mode) { 271294bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 271394bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2714fcf5ef2aSThomas Huth } else { 271594bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 271694bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 271794bf2658SRichard Henderson } 271894bf2658SRichard Henderson tcg_temp_free_i32(oi); 271994bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 2720f34ec0f6SRichard Henderson } else { 272194bf2658SRichard Henderson /* Restart with exclusive lock. */ 272294bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 272394bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2724f34ec0f6SRichard Henderson } 272594bf2658SRichard Henderson } else if (ctx->le_mode) { 272694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2727fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 272894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 272994bf2658SRichard Henderson } else { 273094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 273194bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 273294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2733fcf5ef2aSThomas Huth } 2734fcf5ef2aSThomas Huth tcg_temp_free(EA); 2735fcf5ef2aSThomas Huth } 2736fcf5ef2aSThomas Huth #endif 2737fcf5ef2aSThomas Huth 2738fcf5ef2aSThomas Huth /*** Integer store ***/ 2739fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2740fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2741fcf5ef2aSThomas Huth { \ 2742fcf5ef2aSThomas Huth TCGv EA; \ 2743fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2744fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2745fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2746fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2747fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2748fcf5ef2aSThomas Huth } 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2751fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2752fcf5ef2aSThomas Huth { \ 2753fcf5ef2aSThomas Huth TCGv EA; \ 2754fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2755fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2756fcf5ef2aSThomas Huth return; \ 2757fcf5ef2aSThomas Huth } \ 2758fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2759fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2760fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2761fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2762fcf5ef2aSThomas Huth else \ 2763fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2764fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2765fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2766fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2767fcf5ef2aSThomas Huth } 2768fcf5ef2aSThomas Huth 2769fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2770fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2771fcf5ef2aSThomas Huth { \ 2772fcf5ef2aSThomas Huth TCGv EA; \ 2773fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2774fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2775fcf5ef2aSThomas Huth return; \ 2776fcf5ef2aSThomas Huth } \ 2777fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2778fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2779fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2780fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2781fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2782fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2783fcf5ef2aSThomas Huth } 2784fcf5ef2aSThomas Huth 2785fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2786fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2787fcf5ef2aSThomas Huth { \ 2788fcf5ef2aSThomas Huth TCGv EA; \ 2789fcf5ef2aSThomas Huth chk; \ 2790fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2791fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2792fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2793fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2794fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2795fcf5ef2aSThomas Huth } 2796fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2797fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2798fcf5ef2aSThomas Huth 2799fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2800fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2801fcf5ef2aSThomas Huth 2802fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2803fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2804fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2805fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2806fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2807fcf5ef2aSThomas Huth 2808fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2809fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2810fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2811fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2812fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2813fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 281450728199SRoman Kapl 281550728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 281650728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 281750728199SRoman Kapl { \ 281850728199SRoman Kapl TCGv EA; \ 281950728199SRoman Kapl CHK_SV; \ 282050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 282150728199SRoman Kapl EA = tcg_temp_new(); \ 282250728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 282350728199SRoman Kapl tcg_gen_qemu_st_tl( \ 282450728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 282550728199SRoman Kapl tcg_temp_free(EA); \ 282650728199SRoman Kapl } 282750728199SRoman Kapl 282850728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 282950728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 283050728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 283150728199SRoman Kapl #if defined(TARGET_PPC64) 283250728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 283350728199SRoman Kapl #endif 283450728199SRoman Kapl 2835fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2836fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2837fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2838fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2839fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2840fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2841fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2842fcf5ef2aSThomas Huth 2843fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2844fcf5ef2aSThomas Huth { 2845fcf5ef2aSThomas Huth int rs; 2846fcf5ef2aSThomas Huth TCGv EA; 2847fcf5ef2aSThomas Huth 2848fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2849fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2850fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2851fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2852f89ced5fSRichard Henderson TCGv hi, lo; 2853fcf5ef2aSThomas Huth 2854fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2855fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2856fcf5ef2aSThomas Huth } 2857fcf5ef2aSThomas Huth 2858fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2859fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2860fcf5ef2aSThomas Huth return; 2861fcf5ef2aSThomas Huth } 2862fcf5ef2aSThomas Huth 2863fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2864fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2865fcf5ef2aSThomas Huth return; 2866fcf5ef2aSThomas Huth } 2867fcf5ef2aSThomas Huth 2868fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2869fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2870fcf5ef2aSThomas Huth return; 2871fcf5ef2aSThomas Huth } 2872fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2873fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2874fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2875fcf5ef2aSThomas Huth 2876f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 2877f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 2878f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 2879f89ced5fSRichard Henderson 2880f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2881f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 2882f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 2883f89ced5fSRichard Henderson if (ctx->le_mode) { 2884f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2885f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2886fcf5ef2aSThomas Huth } else { 2887f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2888f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2889f89ced5fSRichard Henderson } 2890f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 2891f34ec0f6SRichard Henderson } else { 2892f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 2893f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 2894f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2895f34ec0f6SRichard Henderson } 2896f89ced5fSRichard Henderson } else if (ctx->le_mode) { 2897f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2898fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2899f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2900f89ced5fSRichard Henderson } else { 2901f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2902f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 2903f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2904fcf5ef2aSThomas Huth } 2905fcf5ef2aSThomas Huth tcg_temp_free(EA); 2906fcf5ef2aSThomas Huth } else { 2907fcf5ef2aSThomas Huth /* std / stdu */ 2908fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2909fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2910fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2911fcf5ef2aSThomas Huth return; 2912fcf5ef2aSThomas Huth } 2913fcf5ef2aSThomas Huth } 2914fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2915fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2916fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2917fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2918efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 2919fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2920efe843d8SDavid Gibson } 2921fcf5ef2aSThomas Huth tcg_temp_free(EA); 2922fcf5ef2aSThomas Huth } 2923fcf5ef2aSThomas Huth } 2924fcf5ef2aSThomas Huth #endif 2925fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2926fcf5ef2aSThomas Huth 2927fcf5ef2aSThomas Huth /* lhbrx */ 2928fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2929fcf5ef2aSThomas Huth 2930fcf5ef2aSThomas Huth /* lwbrx */ 2931fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2932fcf5ef2aSThomas Huth 2933fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2934fcf5ef2aSThomas Huth /* ldbrx */ 2935fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2936fcf5ef2aSThomas Huth /* stdbrx */ 2937fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2938fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2939fcf5ef2aSThomas Huth 2940fcf5ef2aSThomas Huth /* sthbrx */ 2941fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2942fcf5ef2aSThomas Huth /* stwbrx */ 2943fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2944fcf5ef2aSThomas Huth 2945fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2946fcf5ef2aSThomas Huth 2947fcf5ef2aSThomas Huth /* lmw */ 2948fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2949fcf5ef2aSThomas Huth { 2950fcf5ef2aSThomas Huth TCGv t0; 2951fcf5ef2aSThomas Huth TCGv_i32 t1; 2952fcf5ef2aSThomas Huth 2953fcf5ef2aSThomas Huth if (ctx->le_mode) { 2954fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2955fcf5ef2aSThomas Huth return; 2956fcf5ef2aSThomas Huth } 2957fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2958fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2959fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2960fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2961fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2962fcf5ef2aSThomas Huth tcg_temp_free(t0); 2963fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2964fcf5ef2aSThomas Huth } 2965fcf5ef2aSThomas Huth 2966fcf5ef2aSThomas Huth /* stmw */ 2967fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2968fcf5ef2aSThomas Huth { 2969fcf5ef2aSThomas Huth TCGv t0; 2970fcf5ef2aSThomas Huth TCGv_i32 t1; 2971fcf5ef2aSThomas Huth 2972fcf5ef2aSThomas Huth if (ctx->le_mode) { 2973fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2974fcf5ef2aSThomas Huth return; 2975fcf5ef2aSThomas Huth } 2976fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2977fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2978fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2979fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2980fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2981fcf5ef2aSThomas Huth tcg_temp_free(t0); 2982fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2983fcf5ef2aSThomas Huth } 2984fcf5ef2aSThomas Huth 2985fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2986fcf5ef2aSThomas Huth 2987fcf5ef2aSThomas Huth /* lswi */ 2988efe843d8SDavid Gibson /* 2989efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 2990efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 2991efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 2992efe843d8SDavid Gibson * spec... 2993fcf5ef2aSThomas Huth */ 2994fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2995fcf5ef2aSThomas Huth { 2996fcf5ef2aSThomas Huth TCGv t0; 2997fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2998fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2999fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3000fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3001fcf5ef2aSThomas Huth int nr; 3002fcf5ef2aSThomas Huth 3003fcf5ef2aSThomas Huth if (ctx->le_mode) { 3004fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3005fcf5ef2aSThomas Huth return; 3006fcf5ef2aSThomas Huth } 3007efe843d8SDavid Gibson if (nb == 0) { 3008fcf5ef2aSThomas Huth nb = 32; 3009efe843d8SDavid Gibson } 3010f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3011fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3012fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3013fcf5ef2aSThomas Huth return; 3014fcf5ef2aSThomas Huth } 3015fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3016fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3017fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3018fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3019fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3020fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3021fcf5ef2aSThomas Huth tcg_temp_free(t0); 3022fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3023fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3024fcf5ef2aSThomas Huth } 3025fcf5ef2aSThomas Huth 3026fcf5ef2aSThomas Huth /* lswx */ 3027fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3028fcf5ef2aSThomas Huth { 3029fcf5ef2aSThomas Huth TCGv t0; 3030fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3031fcf5ef2aSThomas Huth 3032fcf5ef2aSThomas Huth if (ctx->le_mode) { 3033fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3034fcf5ef2aSThomas Huth return; 3035fcf5ef2aSThomas Huth } 3036fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3037fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3038fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3039fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3040fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3041fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3042fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3043fcf5ef2aSThomas Huth tcg_temp_free(t0); 3044fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3045fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3046fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3047fcf5ef2aSThomas Huth } 3048fcf5ef2aSThomas Huth 3049fcf5ef2aSThomas Huth /* stswi */ 3050fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3051fcf5ef2aSThomas Huth { 3052fcf5ef2aSThomas Huth TCGv t0; 3053fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3054fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3055fcf5ef2aSThomas Huth 3056fcf5ef2aSThomas Huth if (ctx->le_mode) { 3057fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3058fcf5ef2aSThomas Huth return; 3059fcf5ef2aSThomas Huth } 3060fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3061fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3062fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3063efe843d8SDavid Gibson if (nb == 0) { 3064fcf5ef2aSThomas Huth nb = 32; 3065efe843d8SDavid Gibson } 3066fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3067fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3068fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3069fcf5ef2aSThomas Huth tcg_temp_free(t0); 3070fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3071fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3072fcf5ef2aSThomas Huth } 3073fcf5ef2aSThomas Huth 3074fcf5ef2aSThomas Huth /* stswx */ 3075fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3076fcf5ef2aSThomas Huth { 3077fcf5ef2aSThomas Huth TCGv t0; 3078fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3079fcf5ef2aSThomas Huth 3080fcf5ef2aSThomas Huth if (ctx->le_mode) { 3081fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3082fcf5ef2aSThomas Huth return; 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3085fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3086fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3087fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3088fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3089fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3090fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3091fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3092fcf5ef2aSThomas Huth tcg_temp_free(t0); 3093fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3094fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3095fcf5ef2aSThomas Huth } 3096fcf5ef2aSThomas Huth 3097fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3098fcf5ef2aSThomas Huth /* eieio */ 3099fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3100fcf5ef2aSThomas Huth { 3101c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3102c8fd8373SCédric Le Goater 3103c8fd8373SCédric Le Goater /* 3104c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3105c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3106c8fd8373SCédric Le Goater */ 3107c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3108c8fd8373SCédric Le Goater /* 3109c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3110c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3111c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3112c8fd8373SCédric Le Goater * complain to the user. 3113c8fd8373SCédric Le Goater */ 3114c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3115c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3116c8fd8373SCédric Le Goater TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3117c8fd8373SCédric Le Goater } else { 3118c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3119c8fd8373SCédric Le Goater } 3120c8fd8373SCédric Le Goater } 3121c8fd8373SCédric Le Goater 3122c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3123fcf5ef2aSThomas Huth } 3124fcf5ef2aSThomas Huth 3125fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3126fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3127fcf5ef2aSThomas Huth { 3128fcf5ef2aSThomas Huth TCGv_i32 t; 3129fcf5ef2aSThomas Huth TCGLabel *l; 3130fcf5ef2aSThomas Huth 3131fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3132fcf5ef2aSThomas Huth return; 3133fcf5ef2aSThomas Huth } 3134fcf5ef2aSThomas Huth l = gen_new_label(); 3135fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3136fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3137fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3138fcf5ef2aSThomas Huth if (global) { 3139fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3140fcf5ef2aSThomas Huth } else { 3141fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3142fcf5ef2aSThomas Huth } 3143fcf5ef2aSThomas Huth gen_set_label(l); 3144fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3145fcf5ef2aSThomas Huth } 3146fcf5ef2aSThomas Huth #else 3147fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3148fcf5ef2aSThomas Huth #endif 3149fcf5ef2aSThomas Huth 3150fcf5ef2aSThomas Huth /* isync */ 3151fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3152fcf5ef2aSThomas Huth { 3153fcf5ef2aSThomas Huth /* 3154fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3155fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3156fcf5ef2aSThomas Huth */ 3157fcf5ef2aSThomas Huth if (!ctx->pr) { 3158fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3159fcf5ef2aSThomas Huth } 31604771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3161fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3162fcf5ef2aSThomas Huth } 3163fcf5ef2aSThomas Huth 3164fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3165fcf5ef2aSThomas Huth 316614776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 31672a4e6c1bSRichard Henderson { 31682a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 31692a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 31702a4e6c1bSRichard Henderson 31712a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 31722a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 31732a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 31742a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 31752a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 31762a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 31772a4e6c1bSRichard Henderson tcg_temp_free(t0); 31782a4e6c1bSRichard Henderson } 31792a4e6c1bSRichard Henderson 3180fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3181fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3182fcf5ef2aSThomas Huth { \ 31832a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3184fcf5ef2aSThomas Huth } 3185fcf5ef2aSThomas Huth 3186fcf5ef2aSThomas Huth /* lwarx */ 3187fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3188fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3189fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3190fcf5ef2aSThomas Huth 319114776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 319220923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 319320923c1dSRichard Henderson { 319420923c1dSRichard Henderson TCGv t = tcg_temp_new(); 319520923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 319620923c1dSRichard Henderson TCGv u = tcg_temp_new(); 319720923c1dSRichard Henderson 319820923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 319920923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 320020923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 320120923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 320220923c1dSRichard Henderson 320320923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 320420923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 320520923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 320620923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 320720923c1dSRichard Henderson 320820923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 320920923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 321020923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 321120923c1dSRichard Henderson 321220923c1dSRichard Henderson tcg_temp_free(t); 321320923c1dSRichard Henderson tcg_temp_free(t2); 321420923c1dSRichard Henderson tcg_temp_free(u); 321520923c1dSRichard Henderson } 321620923c1dSRichard Henderson 321714776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 321820ba8504SRichard Henderson { 321920ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 322020ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 322120923c1dSRichard Henderson int rt = rD(ctx->opcode); 322220923c1dSRichard Henderson bool need_serial; 322320ba8504SRichard Henderson TCGv src, dst; 322420ba8504SRichard Henderson 322520ba8504SRichard Henderson gen_addr_register(ctx, EA); 322620923c1dSRichard Henderson dst = cpu_gpr[rt]; 322720923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 322820ba8504SRichard Henderson 322920923c1dSRichard Henderson need_serial = false; 323020ba8504SRichard Henderson memop |= MO_ALIGN; 323120ba8504SRichard Henderson switch (gpr_FC) { 323220ba8504SRichard Henderson case 0: /* Fetch and add */ 323320ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 323420ba8504SRichard Henderson break; 323520ba8504SRichard Henderson case 1: /* Fetch and xor */ 323620ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 323720ba8504SRichard Henderson break; 323820ba8504SRichard Henderson case 2: /* Fetch and or */ 323920ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 324020ba8504SRichard Henderson break; 324120ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 324220ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 324320ba8504SRichard Henderson break; 3244b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3245b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3246b8ce0f86SRichard Henderson break; 3247b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3248b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3249b8ce0f86SRichard Henderson break; 3250b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3251b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3252b8ce0f86SRichard Henderson break; 3253b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3254b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3255b8ce0f86SRichard Henderson break; 325620ba8504SRichard Henderson case 8: /* Swap */ 325720ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 325820ba8504SRichard Henderson break; 325920923c1dSRichard Henderson 326020923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 326120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 326220923c1dSRichard Henderson need_serial = true; 326320923c1dSRichard Henderson } else { 326420923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 326520923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 326620923c1dSRichard Henderson 326720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 326820923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 326920923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 327020923c1dSRichard Henderson } else { 327120923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 327220923c1dSRichard Henderson } 327320923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 327420923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 327520923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 327620923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 327720923c1dSRichard Henderson 327820923c1dSRichard Henderson tcg_temp_free(t0); 327920923c1dSRichard Henderson tcg_temp_free(t1); 328020923c1dSRichard Henderson } 328120ba8504SRichard Henderson break; 328220923c1dSRichard Henderson 328320923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 328420923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 328520923c1dSRichard Henderson need_serial = true; 328620923c1dSRichard Henderson } else { 328720923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 328820923c1dSRichard Henderson } 328920923c1dSRichard Henderson break; 329020923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 329120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 329220923c1dSRichard Henderson need_serial = true; 329320923c1dSRichard Henderson } else { 329420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 329520923c1dSRichard Henderson } 329620923c1dSRichard Henderson break; 329720923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 329820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 329920923c1dSRichard Henderson need_serial = true; 330020923c1dSRichard Henderson } else { 330120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 330220923c1dSRichard Henderson } 330320923c1dSRichard Henderson break; 330420923c1dSRichard Henderson 330520ba8504SRichard Henderson default: 330620ba8504SRichard Henderson /* invoke data storage error handler */ 330720ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 330820ba8504SRichard Henderson } 330920ba8504SRichard Henderson tcg_temp_free(EA); 331020923c1dSRichard Henderson 331120923c1dSRichard Henderson if (need_serial) { 331220923c1dSRichard Henderson /* Restart with exclusive lock. */ 331320923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 331420923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 331520923c1dSRichard Henderson } 3316a68a6146SBalamuruhan S } 3317a68a6146SBalamuruhan S 331820ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 331920ba8504SRichard Henderson { 332020ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 332120ba8504SRichard Henderson } 332220ba8504SRichard Henderson 332320ba8504SRichard Henderson #ifdef TARGET_PPC64 332420ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 332520ba8504SRichard Henderson { 332620ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 332720ba8504SRichard Henderson } 3328a68a6146SBalamuruhan S #endif 3329a68a6146SBalamuruhan S 333014776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 33319deb041cSRichard Henderson { 33329deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 33339deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 33349deb041cSRichard Henderson TCGv src, discard; 33359deb041cSRichard Henderson 33369deb041cSRichard Henderson gen_addr_register(ctx, EA); 33379deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 33389deb041cSRichard Henderson discard = tcg_temp_new(); 33399deb041cSRichard Henderson 33409deb041cSRichard Henderson memop |= MO_ALIGN; 33419deb041cSRichard Henderson switch (gpr_FC) { 33429deb041cSRichard Henderson case 0: /* add and Store */ 33439deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33449deb041cSRichard Henderson break; 33459deb041cSRichard Henderson case 1: /* xor and Store */ 33469deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33479deb041cSRichard Henderson break; 33489deb041cSRichard Henderson case 2: /* Or and Store */ 33499deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33509deb041cSRichard Henderson break; 33519deb041cSRichard Henderson case 3: /* 'and' and Store */ 33529deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 33539deb041cSRichard Henderson break; 33549deb041cSRichard Henderson case 4: /* Store max unsigned */ 3355b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3356b8ce0f86SRichard Henderson break; 33579deb041cSRichard Henderson case 5: /* Store max signed */ 3358b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3359b8ce0f86SRichard Henderson break; 33609deb041cSRichard Henderson case 6: /* Store min unsigned */ 3361b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3362b8ce0f86SRichard Henderson break; 33639deb041cSRichard Henderson case 7: /* Store min signed */ 3364b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3365b8ce0f86SRichard Henderson break; 33669deb041cSRichard Henderson case 24: /* Store twin */ 33677fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 33687fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 33697fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 33707fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 33717fbc2b20SRichard Henderson } else { 33727fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 33737fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 33747fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 33757fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 33767fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 33777fbc2b20SRichard Henderson 33787fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 33797fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 33807fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 33817fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 33827fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 33837fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 33847fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 33857fbc2b20SRichard Henderson 33867fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 33877fbc2b20SRichard Henderson tcg_temp_free(s2); 33887fbc2b20SRichard Henderson tcg_temp_free(s); 33897fbc2b20SRichard Henderson tcg_temp_free(t2); 33907fbc2b20SRichard Henderson tcg_temp_free(t); 33917fbc2b20SRichard Henderson } 33929deb041cSRichard Henderson break; 33939deb041cSRichard Henderson default: 33949deb041cSRichard Henderson /* invoke data storage error handler */ 33959deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 33969deb041cSRichard Henderson } 33979deb041cSRichard Henderson tcg_temp_free(discard); 33989deb041cSRichard Henderson tcg_temp_free(EA); 3399a3401188SBalamuruhan S } 3400a3401188SBalamuruhan S 34019deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 34029deb041cSRichard Henderson { 34039deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 34049deb041cSRichard Henderson } 34059deb041cSRichard Henderson 34069deb041cSRichard Henderson #ifdef TARGET_PPC64 34079deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 34089deb041cSRichard Henderson { 34099deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 34109deb041cSRichard Henderson } 3411a3401188SBalamuruhan S #endif 3412a3401188SBalamuruhan S 341314776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3414fcf5ef2aSThomas Huth { 3415253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3416253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3417d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3418d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3419fcf5ef2aSThomas Huth 3420d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3421d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3422d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3423d8b86898SRichard Henderson tcg_temp_free(t0); 3424253ce7b2SNikunj A Dadhania 3425253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3426253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3427253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3428253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3429253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3430253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3431253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3432253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3433253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3434253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3435253ce7b2SNikunj A Dadhania 3436fcf5ef2aSThomas Huth gen_set_label(l1); 34374771df23SNikunj A Dadhania 3438efe843d8SDavid Gibson /* 3439efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3440efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3441efe843d8SDavid Gibson */ 34424771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3443253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3444253ce7b2SNikunj A Dadhania 3445253ce7b2SNikunj A Dadhania gen_set_label(l2); 3446fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3447fcf5ef2aSThomas Huth } 3448fcf5ef2aSThomas Huth 3449fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3450fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3451fcf5ef2aSThomas Huth { \ 3452d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3453fcf5ef2aSThomas Huth } 3454fcf5ef2aSThomas Huth 3455fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3456fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3457fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3458fcf5ef2aSThomas Huth 3459fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3460fcf5ef2aSThomas Huth /* ldarx */ 3461fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3462fcf5ef2aSThomas Huth /* stdcx. */ 3463fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3464fcf5ef2aSThomas Huth 3465fcf5ef2aSThomas Huth /* lqarx */ 3466fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3467fcf5ef2aSThomas Huth { 3468fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 346994bf2658SRichard Henderson TCGv EA, hi, lo; 3470fcf5ef2aSThomas Huth 3471fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3472fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3473fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3474fcf5ef2aSThomas Huth return; 3475fcf5ef2aSThomas Huth } 3476fcf5ef2aSThomas Huth 3477fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 347894bf2658SRichard Henderson EA = tcg_temp_new(); 3479fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 348094bf2658SRichard Henderson 348194bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 348294bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 348394bf2658SRichard Henderson hi = cpu_gpr[rd]; 348494bf2658SRichard Henderson 348594bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3486f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 348794bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 348894bf2658SRichard Henderson if (ctx->le_mode) { 348994bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 349094bf2658SRichard Henderson ctx->mem_idx)); 349194bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3492fcf5ef2aSThomas Huth } else { 349394bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 349494bf2658SRichard Henderson ctx->mem_idx)); 349594bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3496fcf5ef2aSThomas Huth } 349794bf2658SRichard Henderson tcg_temp_free_i32(oi); 349894bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3499f34ec0f6SRichard Henderson } else { 350094bf2658SRichard Henderson /* Restart with exclusive lock. */ 350194bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 350294bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 350394bf2658SRichard Henderson tcg_temp_free(EA); 350494bf2658SRichard Henderson return; 3505f34ec0f6SRichard Henderson } 350694bf2658SRichard Henderson } else if (ctx->le_mode) { 350794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3508fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3509fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 351094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 351194bf2658SRichard Henderson } else { 351294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 351394bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 351494bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 351594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 351694bf2658SRichard Henderson } 3517fcf5ef2aSThomas Huth tcg_temp_free(EA); 351894bf2658SRichard Henderson 351994bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 352094bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3521fcf5ef2aSThomas Huth } 3522fcf5ef2aSThomas Huth 3523fcf5ef2aSThomas Huth /* stqcx. */ 3524fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3525fcf5ef2aSThomas Huth { 35264a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 35274a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3528fcf5ef2aSThomas Huth 35294a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3530fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3531fcf5ef2aSThomas Huth return; 3532fcf5ef2aSThomas Huth } 35334a9b3c5dSRichard Henderson 3534fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 35354a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3536fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3537fcf5ef2aSThomas Huth 35384a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 35394a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 35404a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3541fcf5ef2aSThomas Huth 35424a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3543f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 35444a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 35454a9b3c5dSRichard Henderson if (ctx->le_mode) { 3546f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 3547f34ec0f6SRichard Henderson EA, lo, hi, oi); 3548fcf5ef2aSThomas Huth } else { 3549f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 3550f34ec0f6SRichard Henderson EA, lo, hi, oi); 3551fcf5ef2aSThomas Huth } 3552f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 3553f34ec0f6SRichard Henderson } else { 35544a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 35554a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 35564a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3557f34ec0f6SRichard Henderson } 3558fcf5ef2aSThomas Huth tcg_temp_free(EA); 35594a9b3c5dSRichard Henderson } else { 35604a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 35614a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 35624a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 35634a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 3564fcf5ef2aSThomas Huth 35654a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 35664a9b3c5dSRichard Henderson tcg_temp_free(EA); 35674a9b3c5dSRichard Henderson 35684a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 35694a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35704a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 35714a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 35724a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35734a9b3c5dSRichard Henderson 35744a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35754a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 35764a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 35774a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 35784a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 35794a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 35804a9b3c5dSRichard Henderson 35814a9b3c5dSRichard Henderson /* Success */ 35824a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 35834a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35844a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 35854a9b3c5dSRichard Henderson 35864a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35874a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 35884a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 35894a9b3c5dSRichard Henderson 35904a9b3c5dSRichard Henderson gen_set_label(lab_fail); 35914a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35924a9b3c5dSRichard Henderson 35934a9b3c5dSRichard Henderson gen_set_label(lab_over); 35944a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 35954a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 35964a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 35974a9b3c5dSRichard Henderson } 35984a9b3c5dSRichard Henderson } 3599fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3600fcf5ef2aSThomas Huth 3601fcf5ef2aSThomas Huth /* sync */ 3602fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3603fcf5ef2aSThomas Huth { 3604fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3605fcf5ef2aSThomas Huth 3606fcf5ef2aSThomas Huth /* 3607fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3608fcf5ef2aSThomas Huth * 3609fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3610fcf5ef2aSThomas Huth * 3611fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3612fcf5ef2aSThomas Huth * check MSR_PR as well. 3613fcf5ef2aSThomas Huth */ 3614fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3615fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3616fcf5ef2aSThomas Huth } 36174771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3618fcf5ef2aSThomas Huth } 3619fcf5ef2aSThomas Huth 3620fcf5ef2aSThomas Huth /* wait */ 3621fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3622fcf5ef2aSThomas Huth { 3623fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3624fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3625fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3626fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3627fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3628b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3629fcf5ef2aSThomas Huth } 3630fcf5ef2aSThomas Huth 3631fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3632fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3633fcf5ef2aSThomas Huth { 3634fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3635fcf5ef2aSThomas Huth GEN_PRIV; 3636fcf5ef2aSThomas Huth #else 3637fcf5ef2aSThomas Huth TCGv_i32 t; 3638fcf5ef2aSThomas Huth 3639fcf5ef2aSThomas Huth CHK_HV; 3640fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3641fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3642fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3643154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3644154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3645fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3646fcf5ef2aSThomas Huth } 3647fcf5ef2aSThomas Huth 3648fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3649fcf5ef2aSThomas Huth { 3650fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3651fcf5ef2aSThomas Huth GEN_PRIV; 3652fcf5ef2aSThomas Huth #else 3653fcf5ef2aSThomas Huth TCGv_i32 t; 3654fcf5ef2aSThomas Huth 3655fcf5ef2aSThomas Huth CHK_HV; 3656fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3657fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3658fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3659154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3660154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3661fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3662fcf5ef2aSThomas Huth } 3663fcf5ef2aSThomas Huth 3664cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3665cdee0e72SNikunj A Dadhania { 366621c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 366721c0d66aSBenjamin Herrenschmidt GEN_PRIV; 366821c0d66aSBenjamin Herrenschmidt #else 366921c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 367021c0d66aSBenjamin Herrenschmidt 367121c0d66aSBenjamin Herrenschmidt CHK_HV; 367221c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 367321c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 367421c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 367521c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 367621c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 367721c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 3678cdee0e72SNikunj A Dadhania } 3679cdee0e72SNikunj A Dadhania 3680fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3681fcf5ef2aSThomas Huth { 3682fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3683fcf5ef2aSThomas Huth GEN_PRIV; 3684fcf5ef2aSThomas Huth #else 3685fcf5ef2aSThomas Huth TCGv_i32 t; 3686fcf5ef2aSThomas Huth 3687fcf5ef2aSThomas Huth CHK_HV; 3688fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3689fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3690fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3691154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3692154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3693fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3694fcf5ef2aSThomas Huth } 3695fcf5ef2aSThomas Huth 3696fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3697fcf5ef2aSThomas Huth { 3698fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3699fcf5ef2aSThomas Huth GEN_PRIV; 3700fcf5ef2aSThomas Huth #else 3701fcf5ef2aSThomas Huth TCGv_i32 t; 3702fcf5ef2aSThomas Huth 3703fcf5ef2aSThomas Huth CHK_HV; 3704fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3705fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3706fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3707154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 3708154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3709fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3710fcf5ef2aSThomas Huth } 3711fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3712fcf5ef2aSThomas Huth 3713fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3714fcf5ef2aSThomas Huth { 3715fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3716efe843d8SDavid Gibson if (ctx->has_cfar) { 3717fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3718efe843d8SDavid Gibson } 3719fcf5ef2aSThomas Huth #endif 3720fcf5ef2aSThomas Huth } 3721fcf5ef2aSThomas Huth 3722fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3723fcf5ef2aSThomas Huth { 3724fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3725fcf5ef2aSThomas Huth return false; 3726fcf5ef2aSThomas Huth } 3727fcf5ef2aSThomas Huth 3728fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3729b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3730fcf5ef2aSThomas Huth #else 3731fcf5ef2aSThomas Huth return true; 3732fcf5ef2aSThomas Huth #endif 3733fcf5ef2aSThomas Huth } 3734fcf5ef2aSThomas Huth 37350e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 37360e3bf489SRoman Kapl { 37370e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 37380e3bf489SRoman Kapl if (unlikely(sse)) { 37390e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 37400e3bf489SRoman Kapl gen_debug_exception(ctx); 37410e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3742e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 37430e3bf489SRoman Kapl gen_exception(ctx, excp); 37440e3bf489SRoman Kapl } 37450e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 37460e3bf489SRoman Kapl } else { 37470e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 37480e3bf489SRoman Kapl } 37490e3bf489SRoman Kapl } 37500e3bf489SRoman Kapl 3751fcf5ef2aSThomas Huth /*** Branch ***/ 3752c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3753fcf5ef2aSThomas Huth { 3754fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3755fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3756fcf5ef2aSThomas Huth } 3757fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3758fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3759fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 376007ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 3761fcf5ef2aSThomas Huth } else { 3762fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 37630e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3764fcf5ef2aSThomas Huth } 3765fcf5ef2aSThomas Huth } 3766fcf5ef2aSThomas Huth 3767fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3768fcf5ef2aSThomas Huth { 3769fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3770fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3771fcf5ef2aSThomas Huth } 3772fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3773fcf5ef2aSThomas Huth } 3774fcf5ef2aSThomas Huth 3775fcf5ef2aSThomas Huth /* b ba bl bla */ 3776fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3777fcf5ef2aSThomas Huth { 3778fcf5ef2aSThomas Huth target_ulong li, target; 3779fcf5ef2aSThomas Huth 3780fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3781fcf5ef2aSThomas Huth /* sign extend LI */ 3782fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3783fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3784fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3785b6bac4bcSEmilio G. Cota target = ctx->base.pc_next + li - 4; 3786fcf5ef2aSThomas Huth } else { 3787fcf5ef2aSThomas Huth target = li; 3788fcf5ef2aSThomas Huth } 3789fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3790b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3791fcf5ef2aSThomas Huth } 3792b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3793fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3794fcf5ef2aSThomas Huth } 3795fcf5ef2aSThomas Huth 3796fcf5ef2aSThomas Huth #define BCOND_IM 0 3797fcf5ef2aSThomas Huth #define BCOND_LR 1 3798fcf5ef2aSThomas Huth #define BCOND_CTR 2 3799fcf5ef2aSThomas Huth #define BCOND_TAR 3 3800fcf5ef2aSThomas Huth 3801c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 3802fcf5ef2aSThomas Huth { 3803fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3804fcf5ef2aSThomas Huth TCGLabel *l1; 3805fcf5ef2aSThomas Huth TCGv target; 3806fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 38070e3bf489SRoman Kapl 3808fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3809fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3810efe843d8SDavid Gibson if (type == BCOND_CTR) { 3811fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3812efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 3813fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3814efe843d8SDavid Gibson } else { 3815fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3816efe843d8SDavid Gibson } 3817fcf5ef2aSThomas Huth } else { 3818f764718dSRichard Henderson target = NULL; 3819fcf5ef2aSThomas Huth } 3820efe843d8SDavid Gibson if (LK(ctx->opcode)) { 3821b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3822efe843d8SDavid Gibson } 3823fcf5ef2aSThomas Huth l1 = gen_new_label(); 3824fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3825fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3826fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3827fa200c95SGreg Kurz 3828fa200c95SGreg Kurz if (type == BCOND_CTR) { 3829fa200c95SGreg Kurz /* 3830fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 3831fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 3832fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 383315d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 383415d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 383515d68c5eSGreg Kurz * it basically useless and thus never used in real code. 383615d68c5eSGreg Kurz * 383715d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 383815d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 383915d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 384015d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 384115d68c5eSGreg Kurz * doing anything else harmful. 3842fa200c95SGreg Kurz */ 3843d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 3844fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 38459acc95cdSGreg Kurz tcg_temp_free(temp); 38469acc95cdSGreg Kurz tcg_temp_free(target); 3847fcf5ef2aSThomas Huth return; 3848fcf5ef2aSThomas Huth } 3849fa200c95SGreg Kurz 3850fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 3851fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 3852fa200c95SGreg Kurz } else { 3853fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 3854fa200c95SGreg Kurz } 3855fa200c95SGreg Kurz if (bo & 0x2) { 3856fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3857fa200c95SGreg Kurz } else { 3858fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3859fa200c95SGreg Kurz } 3860fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3861fa200c95SGreg Kurz } else { 3862fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3863fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3864fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3865fcf5ef2aSThomas Huth } else { 3866fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3867fcf5ef2aSThomas Huth } 3868fcf5ef2aSThomas Huth if (bo & 0x2) { 3869fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3870fcf5ef2aSThomas Huth } else { 3871fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3872fcf5ef2aSThomas Huth } 3873fa200c95SGreg Kurz } 3874fcf5ef2aSThomas Huth tcg_temp_free(temp); 3875fcf5ef2aSThomas Huth } 3876fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3877fcf5ef2aSThomas Huth /* Test CR */ 3878fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3879fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3880fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3881fcf5ef2aSThomas Huth 3882fcf5ef2aSThomas Huth if (bo & 0x8) { 3883fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3884fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3885fcf5ef2aSThomas Huth } else { 3886fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3887fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3888fcf5ef2aSThomas Huth } 3889fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3890fcf5ef2aSThomas Huth } 3891b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3892fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3893fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3894fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3895b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3896fcf5ef2aSThomas Huth } else { 3897fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3898fcf5ef2aSThomas Huth } 3899fcf5ef2aSThomas Huth } else { 3900fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3901fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3902fcf5ef2aSThomas Huth } else { 3903fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3904fcf5ef2aSThomas Huth } 39050e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3906c4a2e3a9SRichard Henderson tcg_temp_free(target); 3907c4a2e3a9SRichard Henderson } 3908fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 39090e3bf489SRoman Kapl /* fallthrough case */ 3910fcf5ef2aSThomas Huth gen_set_label(l1); 3911b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 3912fcf5ef2aSThomas Huth } 3913fcf5ef2aSThomas Huth } 3914fcf5ef2aSThomas Huth 3915fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3916fcf5ef2aSThomas Huth { 3917fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3918fcf5ef2aSThomas Huth } 3919fcf5ef2aSThomas Huth 3920fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3921fcf5ef2aSThomas Huth { 3922fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3923fcf5ef2aSThomas Huth } 3924fcf5ef2aSThomas Huth 3925fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3926fcf5ef2aSThomas Huth { 3927fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3928fcf5ef2aSThomas Huth } 3929fcf5ef2aSThomas Huth 3930fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3931fcf5ef2aSThomas Huth { 3932fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3933fcf5ef2aSThomas Huth } 3934fcf5ef2aSThomas Huth 3935fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3936fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3937fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3938fcf5ef2aSThomas Huth { \ 3939fcf5ef2aSThomas Huth uint8_t bitmask; \ 3940fcf5ef2aSThomas Huth int sh; \ 3941fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3942fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3943fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3944fcf5ef2aSThomas Huth if (sh > 0) \ 3945fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3946fcf5ef2aSThomas Huth else if (sh < 0) \ 3947fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3948fcf5ef2aSThomas Huth else \ 3949fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3950fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3951fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3952fcf5ef2aSThomas Huth if (sh > 0) \ 3953fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3954fcf5ef2aSThomas Huth else if (sh < 0) \ 3955fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3956fcf5ef2aSThomas Huth else \ 3957fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3958fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3959fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3960fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3961fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3962fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3963fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3964fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3965fcf5ef2aSThomas Huth } 3966fcf5ef2aSThomas Huth 3967fcf5ef2aSThomas Huth /* crand */ 3968fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3969fcf5ef2aSThomas Huth /* crandc */ 3970fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3971fcf5ef2aSThomas Huth /* creqv */ 3972fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3973fcf5ef2aSThomas Huth /* crnand */ 3974fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3975fcf5ef2aSThomas Huth /* crnor */ 3976fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3977fcf5ef2aSThomas Huth /* cror */ 3978fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3979fcf5ef2aSThomas Huth /* crorc */ 3980fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3981fcf5ef2aSThomas Huth /* crxor */ 3982fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3983fcf5ef2aSThomas Huth 3984fcf5ef2aSThomas Huth /* mcrf */ 3985fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3986fcf5ef2aSThomas Huth { 3987fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3988fcf5ef2aSThomas Huth } 3989fcf5ef2aSThomas Huth 3990fcf5ef2aSThomas Huth /*** System linkage ***/ 3991fcf5ef2aSThomas Huth 3992fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3993fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3994fcf5ef2aSThomas Huth { 3995fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3996fcf5ef2aSThomas Huth GEN_PRIV; 3997fcf5ef2aSThomas Huth #else 3998efe843d8SDavid Gibson /* 3999efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4000fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4001fcf5ef2aSThomas Huth */ 4002d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4003fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4004fcf5ef2aSThomas Huth return; 4005fcf5ef2aSThomas Huth } 4006fcf5ef2aSThomas Huth /* Restore CPU state */ 4007fcf5ef2aSThomas Huth CHK_SV; 4008a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4009a59d628fSMaria Klimushenkova gen_io_start(); 4010a59d628fSMaria Klimushenkova } 4011b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 4012fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 4013fcf5ef2aSThomas Huth gen_sync_exception(ctx); 4014fcf5ef2aSThomas Huth #endif 4015fcf5ef2aSThomas Huth } 4016fcf5ef2aSThomas Huth 4017fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4018fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4019fcf5ef2aSThomas Huth { 4020fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4021fcf5ef2aSThomas Huth GEN_PRIV; 4022fcf5ef2aSThomas Huth #else 4023fcf5ef2aSThomas Huth /* Restore CPU state */ 4024fcf5ef2aSThomas Huth CHK_SV; 4025a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 4026a59d628fSMaria Klimushenkova gen_io_start(); 4027a59d628fSMaria Klimushenkova } 4028b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 4029fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 4030fcf5ef2aSThomas Huth gen_sync_exception(ctx); 4031fcf5ef2aSThomas Huth #endif 4032fcf5ef2aSThomas Huth } 4033fcf5ef2aSThomas Huth 40343c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 40353c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 40363c89b8d6SNicholas Piggin { 40373c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 40383c89b8d6SNicholas Piggin GEN_PRIV; 40393c89b8d6SNicholas Piggin #else 40403c89b8d6SNicholas Piggin /* Restore CPU state */ 40413c89b8d6SNicholas Piggin CHK_SV; 40423c89b8d6SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 40433c89b8d6SNicholas Piggin gen_io_start(); 40443c89b8d6SNicholas Piggin } 40453c89b8d6SNicholas Piggin gen_update_cfar(ctx, ctx->base.pc_next - 4); 40463c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 40473c89b8d6SNicholas Piggin gen_sync_exception(ctx); 40483c89b8d6SNicholas Piggin #endif 40493c89b8d6SNicholas Piggin } 40503c89b8d6SNicholas Piggin #endif 40513c89b8d6SNicholas Piggin 4052fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4053fcf5ef2aSThomas Huth { 4054fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4055fcf5ef2aSThomas Huth GEN_PRIV; 4056fcf5ef2aSThomas Huth #else 4057fcf5ef2aSThomas Huth /* Restore CPU state */ 4058fcf5ef2aSThomas Huth CHK_HV; 4059fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 4060fcf5ef2aSThomas Huth gen_sync_exception(ctx); 4061fcf5ef2aSThomas Huth #endif 4062fcf5ef2aSThomas Huth } 4063fcf5ef2aSThomas Huth #endif 4064fcf5ef2aSThomas Huth 4065fcf5ef2aSThomas Huth /* sc */ 4066fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4067fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4068fcf5ef2aSThomas Huth #else 4069fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 40703c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4071fcf5ef2aSThomas Huth #endif 4072fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4073fcf5ef2aSThomas Huth { 4074fcf5ef2aSThomas Huth uint32_t lev; 4075fcf5ef2aSThomas Huth 4076fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4077fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4078fcf5ef2aSThomas Huth } 4079fcf5ef2aSThomas Huth 40803c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 40813c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 40823c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 40833c89b8d6SNicholas Piggin { 40843c89b8d6SNicholas Piggin uint32_t lev; 40853c89b8d6SNicholas Piggin 40863c89b8d6SNicholas Piggin if (unlikely(!ctx->scv_enabled)) { 40873c89b8d6SNicholas Piggin gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_SCV); 40883c89b8d6SNicholas Piggin return; 40893c89b8d6SNicholas Piggin } 40903c89b8d6SNicholas Piggin 40913c89b8d6SNicholas Piggin lev = (ctx->opcode >> 5) & 0x7F; 40923c89b8d6SNicholas Piggin gen_exception_err(ctx, POWERPC_SYSCALL_VECTORED, lev); 40933c89b8d6SNicholas Piggin } 40943c89b8d6SNicholas Piggin #endif 40953c89b8d6SNicholas Piggin #endif 40963c89b8d6SNicholas Piggin 4097fcf5ef2aSThomas Huth /*** Trap ***/ 4098fcf5ef2aSThomas Huth 4099fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4100fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4101fcf5ef2aSThomas Huth { 4102fcf5ef2aSThomas Huth /* Trap never */ 4103fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4104fcf5ef2aSThomas Huth return true; 4105fcf5ef2aSThomas Huth } 4106fcf5ef2aSThomas Huth /* Trap always */ 4107fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4108fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4109fcf5ef2aSThomas Huth return true; 4110fcf5ef2aSThomas Huth } 4111fcf5ef2aSThomas Huth return false; 4112fcf5ef2aSThomas Huth } 4113fcf5ef2aSThomas Huth 4114fcf5ef2aSThomas Huth /* tw */ 4115fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4116fcf5ef2aSThomas Huth { 4117fcf5ef2aSThomas Huth TCGv_i32 t0; 4118fcf5ef2aSThomas Huth 4119fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4120fcf5ef2aSThomas Huth return; 4121fcf5ef2aSThomas Huth } 4122fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4123fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4124fcf5ef2aSThomas Huth t0); 4125fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4126fcf5ef2aSThomas Huth } 4127fcf5ef2aSThomas Huth 4128fcf5ef2aSThomas Huth /* twi */ 4129fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4130fcf5ef2aSThomas Huth { 4131fcf5ef2aSThomas Huth TCGv t0; 4132fcf5ef2aSThomas Huth TCGv_i32 t1; 4133fcf5ef2aSThomas Huth 4134fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4135fcf5ef2aSThomas Huth return; 4136fcf5ef2aSThomas Huth } 4137fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4138fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4139fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4140fcf5ef2aSThomas Huth tcg_temp_free(t0); 4141fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4142fcf5ef2aSThomas Huth } 4143fcf5ef2aSThomas Huth 4144fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4145fcf5ef2aSThomas Huth /* td */ 4146fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4147fcf5ef2aSThomas Huth { 4148fcf5ef2aSThomas Huth TCGv_i32 t0; 4149fcf5ef2aSThomas Huth 4150fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4151fcf5ef2aSThomas Huth return; 4152fcf5ef2aSThomas Huth } 4153fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4154fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4155fcf5ef2aSThomas Huth t0); 4156fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4157fcf5ef2aSThomas Huth } 4158fcf5ef2aSThomas Huth 4159fcf5ef2aSThomas Huth /* tdi */ 4160fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4161fcf5ef2aSThomas Huth { 4162fcf5ef2aSThomas Huth TCGv t0; 4163fcf5ef2aSThomas Huth TCGv_i32 t1; 4164fcf5ef2aSThomas Huth 4165fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4166fcf5ef2aSThomas Huth return; 4167fcf5ef2aSThomas Huth } 4168fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4169fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4170fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4171fcf5ef2aSThomas Huth tcg_temp_free(t0); 4172fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4173fcf5ef2aSThomas Huth } 4174fcf5ef2aSThomas Huth #endif 4175fcf5ef2aSThomas Huth 4176fcf5ef2aSThomas Huth /*** Processor control ***/ 4177fcf5ef2aSThomas Huth 4178dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 4179fcf5ef2aSThomas Huth { 4180fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4181fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4182fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4183fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 4184fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4185fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4186fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4187fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 4188fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 4189fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 4190dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 4191dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4192dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4193dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4194dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4195dd09c361SNikunj A Dadhania } 4196fcf5ef2aSThomas Huth tcg_temp_free(t0); 4197fcf5ef2aSThomas Huth tcg_temp_free(t1); 4198fcf5ef2aSThomas Huth tcg_temp_free(t2); 4199fcf5ef2aSThomas Huth } 4200fcf5ef2aSThomas Huth 4201fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 4202fcf5ef2aSThomas Huth { 4203dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 4204fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 4205dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 4206dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 4207dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 4208dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4209dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 42101bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 42111bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 42121bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4213fcf5ef2aSThomas Huth } 4214fcf5ef2aSThomas Huth 4215fcf5ef2aSThomas Huth /* mcrxr */ 4216fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4217fcf5ef2aSThomas Huth { 4218fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4219fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4220fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4221fcf5ef2aSThomas Huth 4222fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4223fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4224fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4225fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4226fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4227fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4228fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4229fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4230fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4231fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4232fcf5ef2aSThomas Huth 4233fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4234fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4235fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4236fcf5ef2aSThomas Huth } 4237fcf5ef2aSThomas Huth 4238b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4239b63d0434SNikunj A Dadhania /* mcrxrx */ 4240b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4241b63d0434SNikunj A Dadhania { 4242b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4243b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4244b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4245b63d0434SNikunj A Dadhania 4246b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4247b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4248b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4249b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4250b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4251b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4252b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4253b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4254b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4255b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4256b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4257b63d0434SNikunj A Dadhania } 4258b63d0434SNikunj A Dadhania #endif 4259b63d0434SNikunj A Dadhania 4260fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4261fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4262fcf5ef2aSThomas Huth { 4263fcf5ef2aSThomas Huth uint32_t crm, crn; 4264fcf5ef2aSThomas Huth 4265fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4266fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4267fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4268fcf5ef2aSThomas Huth crn = ctz32(crm); 4269fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4270fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4271fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4272fcf5ef2aSThomas Huth } 4273fcf5ef2aSThomas Huth } else { 4274fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4275fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4276fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4277fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4278fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4279fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4280fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4281fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4282fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4283fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4284fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4285fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4286fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4287fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4288fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4289fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4290fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4291fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4292fcf5ef2aSThomas Huth } 4293fcf5ef2aSThomas Huth } 4294fcf5ef2aSThomas Huth 4295fcf5ef2aSThomas Huth /* mfmsr */ 4296fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4297fcf5ef2aSThomas Huth { 4298fcf5ef2aSThomas Huth CHK_SV; 4299fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4300fcf5ef2aSThomas Huth } 4301fcf5ef2aSThomas Huth 4302fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4303fcf5ef2aSThomas Huth { 4304fcf5ef2aSThomas Huth #if 0 4305fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4306fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 4307fcf5ef2aSThomas Huth #endif 4308fcf5ef2aSThomas Huth } 4309fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 4310fcf5ef2aSThomas Huth 4311fcf5ef2aSThomas Huth /* mfspr */ 4312fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4313fcf5ef2aSThomas Huth { 4314fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4315fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4316fcf5ef2aSThomas Huth 4317fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4318fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4319fcf5ef2aSThomas Huth #else 4320fcf5ef2aSThomas Huth if (ctx->pr) { 4321fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4322fcf5ef2aSThomas Huth } else if (ctx->hv) { 4323fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4324fcf5ef2aSThomas Huth } else { 4325fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4326fcf5ef2aSThomas Huth } 4327fcf5ef2aSThomas Huth #endif 4328fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4329fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4330fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4331fcf5ef2aSThomas Huth } else { 4332fcf5ef2aSThomas Huth /* Privilege exception */ 4333efe843d8SDavid Gibson /* 4334efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4335fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4336fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4337fcf5ef2aSThomas Huth */ 4338fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 433931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 434031085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4341b6bac4bcSEmilio G. Cota ctx->base.pc_next - 4); 4342fcf5ef2aSThomas Huth } 4343fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4344fcf5ef2aSThomas Huth } 4345fcf5ef2aSThomas Huth } else { 4346fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4347fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4348fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4349fcf5ef2aSThomas Huth /* This is a nop */ 4350fcf5ef2aSThomas Huth return; 4351fcf5ef2aSThomas Huth } 4352fcf5ef2aSThomas Huth /* Not defined */ 435331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 435431085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 4355b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4356fcf5ef2aSThomas Huth 4357efe843d8SDavid Gibson /* 4358efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4359efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4360fcf5ef2aSThomas Huth */ 4361fcf5ef2aSThomas Huth if (sprn & 0x10) { 4362fcf5ef2aSThomas Huth if (ctx->pr) { 4363fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4364fcf5ef2aSThomas Huth } 4365fcf5ef2aSThomas Huth } else { 4366fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4367fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4368fcf5ef2aSThomas Huth } 4369fcf5ef2aSThomas Huth } 4370fcf5ef2aSThomas Huth } 4371fcf5ef2aSThomas Huth } 4372fcf5ef2aSThomas Huth 4373fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4374fcf5ef2aSThomas Huth { 4375fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4376fcf5ef2aSThomas Huth } 4377fcf5ef2aSThomas Huth 4378fcf5ef2aSThomas Huth /* mftb */ 4379fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4380fcf5ef2aSThomas Huth { 4381fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4382fcf5ef2aSThomas Huth } 4383fcf5ef2aSThomas Huth 4384fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4385fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4386fcf5ef2aSThomas Huth { 4387fcf5ef2aSThomas Huth uint32_t crm, crn; 4388fcf5ef2aSThomas Huth 4389fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4390fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4391fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4392fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4393fcf5ef2aSThomas Huth crn = ctz32(crm); 4394fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4395fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4396fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4397fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4398fcf5ef2aSThomas Huth } 4399fcf5ef2aSThomas Huth } else { 4400fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4401fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4402fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4403fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4404fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4405fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4406fcf5ef2aSThomas Huth } 4407fcf5ef2aSThomas Huth } 4408fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4409fcf5ef2aSThomas Huth } 4410fcf5ef2aSThomas Huth } 4411fcf5ef2aSThomas Huth 4412fcf5ef2aSThomas Huth /* mtmsr */ 4413fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4414fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4415fcf5ef2aSThomas Huth { 4416fcf5ef2aSThomas Huth CHK_SV; 4417fcf5ef2aSThomas Huth 4418fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 44195ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 44205ed19506SNicholas Piggin gen_io_start(); 44215ed19506SNicholas Piggin } 4422fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 44235ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 4424fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 44255ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 4426efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4427efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 44285ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 4429efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 44305ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 44315ed19506SNicholas Piggin 44325ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 4433fcf5ef2aSThomas Huth tcg_temp_free(t0); 44345ed19506SNicholas Piggin tcg_temp_free(t1); 44355ed19506SNicholas Piggin 4436fcf5ef2aSThomas Huth } else { 4437efe843d8SDavid Gibson /* 4438efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4439efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4440efe843d8SDavid Gibson * ppc_store_msr 4441fcf5ef2aSThomas Huth */ 4442b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4443fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4444fcf5ef2aSThomas Huth } 44455ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 44465ed19506SNicholas Piggin gen_stop_exception(ctx); 4447fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4448fcf5ef2aSThomas Huth } 4449fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4450fcf5ef2aSThomas Huth 4451fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4452fcf5ef2aSThomas Huth { 4453fcf5ef2aSThomas Huth CHK_SV; 4454fcf5ef2aSThomas Huth 4455fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 44565ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 44575ed19506SNicholas Piggin gen_io_start(); 44585ed19506SNicholas Piggin } 4459fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 44605ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 4461fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 44625ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 4463efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 4464efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 44655ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 4466efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 44675ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 44685ed19506SNicholas Piggin 44695ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 4470fcf5ef2aSThomas Huth tcg_temp_free(t0); 44715ed19506SNicholas Piggin tcg_temp_free(t1); 44725ed19506SNicholas Piggin 4473fcf5ef2aSThomas Huth } else { 4474fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4475fcf5ef2aSThomas Huth 4476efe843d8SDavid Gibson /* 4477efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4478efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4479efe843d8SDavid Gibson * ppc_store_msr 4480fcf5ef2aSThomas Huth */ 4481b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4482fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4483fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4484fcf5ef2aSThomas Huth #else 4485fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4486fcf5ef2aSThomas Huth #endif 4487fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4488fcf5ef2aSThomas Huth tcg_temp_free(msr); 4489fcf5ef2aSThomas Huth } 44905ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 44915ed19506SNicholas Piggin gen_stop_exception(ctx); 4492fcf5ef2aSThomas Huth #endif 4493fcf5ef2aSThomas Huth } 4494fcf5ef2aSThomas Huth 4495fcf5ef2aSThomas Huth /* mtspr */ 4496fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4497fcf5ef2aSThomas Huth { 4498fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4499fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4500fcf5ef2aSThomas Huth 4501fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4502fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4503fcf5ef2aSThomas Huth #else 4504fcf5ef2aSThomas Huth if (ctx->pr) { 4505fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4506fcf5ef2aSThomas Huth } else if (ctx->hv) { 4507fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4508fcf5ef2aSThomas Huth } else { 4509fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4510fcf5ef2aSThomas Huth } 4511fcf5ef2aSThomas Huth #endif 4512fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4513fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4514fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4515fcf5ef2aSThomas Huth } else { 4516fcf5ef2aSThomas Huth /* Privilege exception */ 451731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 451831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 451931085338SThomas Huth ctx->base.pc_next - 4); 4520fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4521fcf5ef2aSThomas Huth } 4522fcf5ef2aSThomas Huth } else { 4523fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4524fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4525fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4526fcf5ef2aSThomas Huth /* This is a nop */ 4527fcf5ef2aSThomas Huth return; 4528fcf5ef2aSThomas Huth } 4529fcf5ef2aSThomas Huth 4530fcf5ef2aSThomas Huth /* Not defined */ 453131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 453231085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 4533b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4534fcf5ef2aSThomas Huth 4535fcf5ef2aSThomas Huth 4536efe843d8SDavid Gibson /* 4537efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4538efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4539fcf5ef2aSThomas Huth */ 4540fcf5ef2aSThomas Huth if (sprn & 0x10) { 4541fcf5ef2aSThomas Huth if (ctx->pr) { 4542fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4543fcf5ef2aSThomas Huth } 4544fcf5ef2aSThomas Huth } else { 4545fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4546fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4547fcf5ef2aSThomas Huth } 4548fcf5ef2aSThomas Huth } 4549fcf5ef2aSThomas Huth } 4550fcf5ef2aSThomas Huth } 4551fcf5ef2aSThomas Huth 4552fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4553fcf5ef2aSThomas Huth /* setb */ 4554fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4555fcf5ef2aSThomas Huth { 4556fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4557fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4558fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4559fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4560fcf5ef2aSThomas Huth 4561fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4562fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4563fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4564fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4565fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4566fcf5ef2aSThomas Huth 4567fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4568fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4569fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4570fcf5ef2aSThomas Huth } 4571fcf5ef2aSThomas Huth #endif 4572fcf5ef2aSThomas Huth 4573fcf5ef2aSThomas Huth /*** Cache management ***/ 4574fcf5ef2aSThomas Huth 4575fcf5ef2aSThomas Huth /* dcbf */ 4576fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4577fcf5ef2aSThomas Huth { 4578fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4579fcf5ef2aSThomas Huth TCGv t0; 4580fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4581fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4582fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4583fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4584fcf5ef2aSThomas Huth tcg_temp_free(t0); 4585fcf5ef2aSThomas Huth } 4586fcf5ef2aSThomas Huth 458750728199SRoman Kapl /* dcbfep (external PID dcbf) */ 458850728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 458950728199SRoman Kapl { 459050728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 459150728199SRoman Kapl TCGv t0; 459250728199SRoman Kapl CHK_SV; 459350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 459450728199SRoman Kapl t0 = tcg_temp_new(); 459550728199SRoman Kapl gen_addr_reg_index(ctx, t0); 459650728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 459750728199SRoman Kapl tcg_temp_free(t0); 459850728199SRoman Kapl } 459950728199SRoman Kapl 4600fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4601fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4602fcf5ef2aSThomas Huth { 4603fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4604fcf5ef2aSThomas Huth GEN_PRIV; 4605fcf5ef2aSThomas Huth #else 4606fcf5ef2aSThomas Huth TCGv EA, val; 4607fcf5ef2aSThomas Huth 4608fcf5ef2aSThomas Huth CHK_SV; 4609fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4610fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4611fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4612fcf5ef2aSThomas Huth val = tcg_temp_new(); 4613fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4614fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4615fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4616fcf5ef2aSThomas Huth tcg_temp_free(val); 4617fcf5ef2aSThomas Huth tcg_temp_free(EA); 4618fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4619fcf5ef2aSThomas Huth } 4620fcf5ef2aSThomas Huth 4621fcf5ef2aSThomas Huth /* dcdst */ 4622fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4623fcf5ef2aSThomas Huth { 4624fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4625fcf5ef2aSThomas Huth TCGv t0; 4626fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4627fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4628fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4629fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4630fcf5ef2aSThomas Huth tcg_temp_free(t0); 4631fcf5ef2aSThomas Huth } 4632fcf5ef2aSThomas Huth 463350728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 463450728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 463550728199SRoman Kapl { 463650728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 463750728199SRoman Kapl TCGv t0; 463850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 463950728199SRoman Kapl t0 = tcg_temp_new(); 464050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 464150728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 464250728199SRoman Kapl tcg_temp_free(t0); 464350728199SRoman Kapl } 464450728199SRoman Kapl 4645fcf5ef2aSThomas Huth /* dcbt */ 4646fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4647fcf5ef2aSThomas Huth { 4648efe843d8SDavid Gibson /* 4649efe843d8SDavid Gibson * interpreted as no-op 4650efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4651efe843d8SDavid Gibson * does not generate any exception 4652fcf5ef2aSThomas Huth */ 4653fcf5ef2aSThomas Huth } 4654fcf5ef2aSThomas Huth 465550728199SRoman Kapl /* dcbtep */ 465650728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 465750728199SRoman Kapl { 4658efe843d8SDavid Gibson /* 4659efe843d8SDavid Gibson * interpreted as no-op 4660efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4661efe843d8SDavid Gibson * does not generate any exception 466250728199SRoman Kapl */ 466350728199SRoman Kapl } 466450728199SRoman Kapl 4665fcf5ef2aSThomas Huth /* dcbtst */ 4666fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4667fcf5ef2aSThomas Huth { 4668efe843d8SDavid Gibson /* 4669efe843d8SDavid Gibson * interpreted as no-op 4670efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4671efe843d8SDavid Gibson * does not generate any exception 4672fcf5ef2aSThomas Huth */ 4673fcf5ef2aSThomas Huth } 4674fcf5ef2aSThomas Huth 467550728199SRoman Kapl /* dcbtstep */ 467650728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 467750728199SRoman Kapl { 4678efe843d8SDavid Gibson /* 4679efe843d8SDavid Gibson * interpreted as no-op 4680efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 4681efe843d8SDavid Gibson * does not generate any exception 468250728199SRoman Kapl */ 468350728199SRoman Kapl } 468450728199SRoman Kapl 4685fcf5ef2aSThomas Huth /* dcbtls */ 4686fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4687fcf5ef2aSThomas Huth { 4688fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4689fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4690fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4691fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4692fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4693fcf5ef2aSThomas Huth tcg_temp_free(t0); 4694fcf5ef2aSThomas Huth } 4695fcf5ef2aSThomas Huth 4696fcf5ef2aSThomas Huth /* dcbz */ 4697fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4698fcf5ef2aSThomas Huth { 4699fcf5ef2aSThomas Huth TCGv tcgv_addr; 4700fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4701fcf5ef2aSThomas Huth 4702fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4703fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4704fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4705fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4706fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4707fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4708fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4709fcf5ef2aSThomas Huth } 4710fcf5ef2aSThomas Huth 471150728199SRoman Kapl /* dcbzep */ 471250728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 471350728199SRoman Kapl { 471450728199SRoman Kapl TCGv tcgv_addr; 471550728199SRoman Kapl TCGv_i32 tcgv_op; 471650728199SRoman Kapl 471750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 471850728199SRoman Kapl tcgv_addr = tcg_temp_new(); 471950728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 472050728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 472150728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 472250728199SRoman Kapl tcg_temp_free(tcgv_addr); 472350728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 472450728199SRoman Kapl } 472550728199SRoman Kapl 4726fcf5ef2aSThomas Huth /* dst / dstt */ 4727fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4728fcf5ef2aSThomas Huth { 4729fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4730fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4731fcf5ef2aSThomas Huth } else { 4732fcf5ef2aSThomas Huth /* interpreted as no-op */ 4733fcf5ef2aSThomas Huth } 4734fcf5ef2aSThomas Huth } 4735fcf5ef2aSThomas Huth 4736fcf5ef2aSThomas Huth /* dstst /dststt */ 4737fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4738fcf5ef2aSThomas Huth { 4739fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4740fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4741fcf5ef2aSThomas Huth } else { 4742fcf5ef2aSThomas Huth /* interpreted as no-op */ 4743fcf5ef2aSThomas Huth } 4744fcf5ef2aSThomas Huth 4745fcf5ef2aSThomas Huth } 4746fcf5ef2aSThomas Huth 4747fcf5ef2aSThomas Huth /* dss / dssall */ 4748fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4749fcf5ef2aSThomas Huth { 4750fcf5ef2aSThomas Huth /* interpreted as no-op */ 4751fcf5ef2aSThomas Huth } 4752fcf5ef2aSThomas Huth 4753fcf5ef2aSThomas Huth /* icbi */ 4754fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4755fcf5ef2aSThomas Huth { 4756fcf5ef2aSThomas Huth TCGv t0; 4757fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4758fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4759fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4760fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4761fcf5ef2aSThomas Huth tcg_temp_free(t0); 4762fcf5ef2aSThomas Huth } 4763fcf5ef2aSThomas Huth 476450728199SRoman Kapl /* icbiep */ 476550728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 476650728199SRoman Kapl { 476750728199SRoman Kapl TCGv t0; 476850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 476950728199SRoman Kapl t0 = tcg_temp_new(); 477050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 477150728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 477250728199SRoman Kapl tcg_temp_free(t0); 477350728199SRoman Kapl } 477450728199SRoman Kapl 4775fcf5ef2aSThomas Huth /* Optional: */ 4776fcf5ef2aSThomas Huth /* dcba */ 4777fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4778fcf5ef2aSThomas Huth { 4779efe843d8SDavid Gibson /* 4780efe843d8SDavid Gibson * interpreted as no-op 4781efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 4782fcf5ef2aSThomas Huth * but does not generate any exception 4783fcf5ef2aSThomas Huth */ 4784fcf5ef2aSThomas Huth } 4785fcf5ef2aSThomas Huth 4786fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4787fcf5ef2aSThomas Huth /* Supervisor only: */ 4788fcf5ef2aSThomas Huth 4789fcf5ef2aSThomas Huth /* mfsr */ 4790fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4791fcf5ef2aSThomas Huth { 4792fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4793fcf5ef2aSThomas Huth GEN_PRIV; 4794fcf5ef2aSThomas Huth #else 4795fcf5ef2aSThomas Huth TCGv t0; 4796fcf5ef2aSThomas Huth 4797fcf5ef2aSThomas Huth CHK_SV; 4798fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4799fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4800fcf5ef2aSThomas Huth tcg_temp_free(t0); 4801fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4802fcf5ef2aSThomas Huth } 4803fcf5ef2aSThomas Huth 4804fcf5ef2aSThomas Huth /* mfsrin */ 4805fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4806fcf5ef2aSThomas Huth { 4807fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4808fcf5ef2aSThomas Huth GEN_PRIV; 4809fcf5ef2aSThomas Huth #else 4810fcf5ef2aSThomas Huth TCGv t0; 4811fcf5ef2aSThomas Huth 4812fcf5ef2aSThomas Huth CHK_SV; 4813fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4814e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4815fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4816fcf5ef2aSThomas Huth tcg_temp_free(t0); 4817fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4818fcf5ef2aSThomas Huth } 4819fcf5ef2aSThomas Huth 4820fcf5ef2aSThomas Huth /* mtsr */ 4821fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4822fcf5ef2aSThomas Huth { 4823fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4824fcf5ef2aSThomas Huth GEN_PRIV; 4825fcf5ef2aSThomas Huth #else 4826fcf5ef2aSThomas Huth TCGv t0; 4827fcf5ef2aSThomas Huth 4828fcf5ef2aSThomas Huth CHK_SV; 4829fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4830fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4831fcf5ef2aSThomas Huth tcg_temp_free(t0); 4832fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4833fcf5ef2aSThomas Huth } 4834fcf5ef2aSThomas Huth 4835fcf5ef2aSThomas Huth /* mtsrin */ 4836fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4837fcf5ef2aSThomas Huth { 4838fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4839fcf5ef2aSThomas Huth GEN_PRIV; 4840fcf5ef2aSThomas Huth #else 4841fcf5ef2aSThomas Huth TCGv t0; 4842fcf5ef2aSThomas Huth CHK_SV; 4843fcf5ef2aSThomas Huth 4844fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4845e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4846fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4847fcf5ef2aSThomas Huth tcg_temp_free(t0); 4848fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4849fcf5ef2aSThomas Huth } 4850fcf5ef2aSThomas Huth 4851fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4852fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4853fcf5ef2aSThomas Huth 4854fcf5ef2aSThomas Huth /* mfsr */ 4855fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4856fcf5ef2aSThomas Huth { 4857fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4858fcf5ef2aSThomas Huth GEN_PRIV; 4859fcf5ef2aSThomas Huth #else 4860fcf5ef2aSThomas Huth TCGv t0; 4861fcf5ef2aSThomas Huth 4862fcf5ef2aSThomas Huth CHK_SV; 4863fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4864fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4865fcf5ef2aSThomas Huth tcg_temp_free(t0); 4866fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4867fcf5ef2aSThomas Huth } 4868fcf5ef2aSThomas Huth 4869fcf5ef2aSThomas Huth /* mfsrin */ 4870fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4871fcf5ef2aSThomas Huth { 4872fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4873fcf5ef2aSThomas Huth GEN_PRIV; 4874fcf5ef2aSThomas Huth #else 4875fcf5ef2aSThomas Huth TCGv t0; 4876fcf5ef2aSThomas Huth 4877fcf5ef2aSThomas Huth CHK_SV; 4878fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4879e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4880fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4881fcf5ef2aSThomas Huth tcg_temp_free(t0); 4882fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4883fcf5ef2aSThomas Huth } 4884fcf5ef2aSThomas Huth 4885fcf5ef2aSThomas Huth /* mtsr */ 4886fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4887fcf5ef2aSThomas Huth { 4888fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4889fcf5ef2aSThomas Huth GEN_PRIV; 4890fcf5ef2aSThomas Huth #else 4891fcf5ef2aSThomas Huth TCGv t0; 4892fcf5ef2aSThomas Huth 4893fcf5ef2aSThomas Huth CHK_SV; 4894fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4895fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4896fcf5ef2aSThomas Huth tcg_temp_free(t0); 4897fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4898fcf5ef2aSThomas Huth } 4899fcf5ef2aSThomas Huth 4900fcf5ef2aSThomas Huth /* mtsrin */ 4901fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4902fcf5ef2aSThomas Huth { 4903fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4904fcf5ef2aSThomas Huth GEN_PRIV; 4905fcf5ef2aSThomas Huth #else 4906fcf5ef2aSThomas Huth TCGv t0; 4907fcf5ef2aSThomas Huth 4908fcf5ef2aSThomas Huth CHK_SV; 4909fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4910e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4911fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4912fcf5ef2aSThomas Huth tcg_temp_free(t0); 4913fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4914fcf5ef2aSThomas Huth } 4915fcf5ef2aSThomas Huth 4916fcf5ef2aSThomas Huth /* slbmte */ 4917fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4918fcf5ef2aSThomas Huth { 4919fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4920fcf5ef2aSThomas Huth GEN_PRIV; 4921fcf5ef2aSThomas Huth #else 4922fcf5ef2aSThomas Huth CHK_SV; 4923fcf5ef2aSThomas Huth 4924fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4925fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4926fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4927fcf5ef2aSThomas Huth } 4928fcf5ef2aSThomas Huth 4929fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4930fcf5ef2aSThomas Huth { 4931fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4932fcf5ef2aSThomas Huth GEN_PRIV; 4933fcf5ef2aSThomas Huth #else 4934fcf5ef2aSThomas Huth CHK_SV; 4935fcf5ef2aSThomas Huth 4936fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4937fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4938fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4939fcf5ef2aSThomas Huth } 4940fcf5ef2aSThomas Huth 4941fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4942fcf5ef2aSThomas Huth { 4943fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4944fcf5ef2aSThomas Huth GEN_PRIV; 4945fcf5ef2aSThomas Huth #else 4946fcf5ef2aSThomas Huth CHK_SV; 4947fcf5ef2aSThomas Huth 4948fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4949fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4950fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4951fcf5ef2aSThomas Huth } 4952fcf5ef2aSThomas Huth 4953fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4954fcf5ef2aSThomas Huth { 4955fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4956fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4957fcf5ef2aSThomas Huth #else 4958fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4959fcf5ef2aSThomas Huth 4960fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4961fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4962fcf5ef2aSThomas Huth return; 4963fcf5ef2aSThomas Huth } 4964fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4965fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4966fcf5ef2aSThomas Huth l1 = gen_new_label(); 4967fcf5ef2aSThomas Huth l2 = gen_new_label(); 4968fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4969fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4970efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4971fcf5ef2aSThomas Huth tcg_gen_br(l2); 4972fcf5ef2aSThomas Huth gen_set_label(l1); 4973fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4974fcf5ef2aSThomas Huth gen_set_label(l2); 4975fcf5ef2aSThomas Huth #endif 4976fcf5ef2aSThomas Huth } 4977fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4978fcf5ef2aSThomas Huth 4979fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4980fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4981fcf5ef2aSThomas Huth 4982fcf5ef2aSThomas Huth /* tlbia */ 4983fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4984fcf5ef2aSThomas Huth { 4985fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4986fcf5ef2aSThomas Huth GEN_PRIV; 4987fcf5ef2aSThomas Huth #else 4988fcf5ef2aSThomas Huth CHK_HV; 4989fcf5ef2aSThomas Huth 4990fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4991fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4992fcf5ef2aSThomas Huth } 4993fcf5ef2aSThomas Huth 4994fcf5ef2aSThomas Huth /* tlbiel */ 4995fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4996fcf5ef2aSThomas Huth { 4997fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4998fcf5ef2aSThomas Huth GEN_PRIV; 4999fcf5ef2aSThomas Huth #else 5000fcf5ef2aSThomas Huth CHK_SV; 5001fcf5ef2aSThomas Huth 5002fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5003fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5004fcf5ef2aSThomas Huth } 5005fcf5ef2aSThomas Huth 5006fcf5ef2aSThomas Huth /* tlbie */ 5007fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5008fcf5ef2aSThomas Huth { 5009fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5010fcf5ef2aSThomas Huth GEN_PRIV; 5011fcf5ef2aSThomas Huth #else 5012fcf5ef2aSThomas Huth TCGv_i32 t1; 5013c6fd28fdSSuraj Jitindar Singh 5014c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 501591c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5016c6fd28fdSSuraj Jitindar Singh } else { 5017c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5018c6fd28fdSSuraj Jitindar Singh } 5019fcf5ef2aSThomas Huth 5020fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5021fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5022fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5023fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5024fcf5ef2aSThomas Huth tcg_temp_free(t0); 5025fcf5ef2aSThomas Huth } else { 5026fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5027fcf5ef2aSThomas Huth } 5028fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5029fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5030fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5031fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5032fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5033fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5034fcf5ef2aSThomas Huth } 5035fcf5ef2aSThomas Huth 5036fcf5ef2aSThomas Huth /* tlbsync */ 5037fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5038fcf5ef2aSThomas Huth { 5039fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5040fcf5ef2aSThomas Huth GEN_PRIV; 5041fcf5ef2aSThomas Huth #else 504291c60f12SCédric Le Goater 504391c60f12SCédric Le Goater if (ctx->gtse) { 504491c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 504591c60f12SCédric Le Goater } else { 504691c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 504791c60f12SCédric Le Goater } 5048fcf5ef2aSThomas Huth 5049fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5050fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5051fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5052fcf5ef2aSThomas Huth } 5053fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5054fcf5ef2aSThomas Huth } 5055fcf5ef2aSThomas Huth 5056fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5057fcf5ef2aSThomas Huth /* slbia */ 5058fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5059fcf5ef2aSThomas Huth { 5060fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5061fcf5ef2aSThomas Huth GEN_PRIV; 5062fcf5ef2aSThomas Huth #else 50630418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 50640418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 50650418bf78SNicholas Piggin 5066fcf5ef2aSThomas Huth CHK_SV; 5067fcf5ef2aSThomas Huth 50680418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 50693119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5070fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5071fcf5ef2aSThomas Huth } 5072fcf5ef2aSThomas Huth 5073fcf5ef2aSThomas Huth /* slbie */ 5074fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5075fcf5ef2aSThomas Huth { 5076fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5077fcf5ef2aSThomas Huth GEN_PRIV; 5078fcf5ef2aSThomas Huth #else 5079fcf5ef2aSThomas Huth CHK_SV; 5080fcf5ef2aSThomas Huth 5081fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5082fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5083fcf5ef2aSThomas Huth } 5084a63f1dfcSNikunj A Dadhania 5085a63f1dfcSNikunj A Dadhania /* slbieg */ 5086a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5087a63f1dfcSNikunj A Dadhania { 5088a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5089a63f1dfcSNikunj A Dadhania GEN_PRIV; 5090a63f1dfcSNikunj A Dadhania #else 5091a63f1dfcSNikunj A Dadhania CHK_SV; 5092a63f1dfcSNikunj A Dadhania 5093a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5094a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5095a63f1dfcSNikunj A Dadhania } 5096a63f1dfcSNikunj A Dadhania 509762d897caSNikunj A Dadhania /* slbsync */ 509862d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 509962d897caSNikunj A Dadhania { 510062d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 510162d897caSNikunj A Dadhania GEN_PRIV; 510262d897caSNikunj A Dadhania #else 510362d897caSNikunj A Dadhania CHK_SV; 510462d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 510562d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 510662d897caSNikunj A Dadhania } 510762d897caSNikunj A Dadhania 5108fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5109fcf5ef2aSThomas Huth 5110fcf5ef2aSThomas Huth /*** External control ***/ 5111fcf5ef2aSThomas Huth /* Optional: */ 5112fcf5ef2aSThomas Huth 5113fcf5ef2aSThomas Huth /* eciwx */ 5114fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5115fcf5ef2aSThomas Huth { 5116fcf5ef2aSThomas Huth TCGv t0; 5117fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5118fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5119fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5120fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5121c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5122c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5123fcf5ef2aSThomas Huth tcg_temp_free(t0); 5124fcf5ef2aSThomas Huth } 5125fcf5ef2aSThomas Huth 5126fcf5ef2aSThomas Huth /* ecowx */ 5127fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5128fcf5ef2aSThomas Huth { 5129fcf5ef2aSThomas Huth TCGv t0; 5130fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5131fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5132fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5133fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5134c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5135c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5136fcf5ef2aSThomas Huth tcg_temp_free(t0); 5137fcf5ef2aSThomas Huth } 5138fcf5ef2aSThomas Huth 5139fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5140fcf5ef2aSThomas Huth 5141fcf5ef2aSThomas Huth /* abs - abs. */ 5142fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5143fcf5ef2aSThomas Huth { 5144fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5145fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5146fe21b785SRichard Henderson 5147fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5148efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5149fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5150fcf5ef2aSThomas Huth } 5151efe843d8SDavid Gibson } 5152fcf5ef2aSThomas Huth 5153fcf5ef2aSThomas Huth /* abso - abso. */ 5154fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5155fcf5ef2aSThomas Huth { 5156fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5157fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5158fe21b785SRichard Henderson 5159fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5160fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5161fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5162efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5163fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5164fcf5ef2aSThomas Huth } 5165efe843d8SDavid Gibson } 5166fcf5ef2aSThomas Huth 5167fcf5ef2aSThomas Huth /* clcs */ 5168fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5169fcf5ef2aSThomas Huth { 5170fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5171fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5172fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5173fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5174fcf5ef2aSThomas Huth } 5175fcf5ef2aSThomas Huth 5176fcf5ef2aSThomas Huth /* div - div. */ 5177fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5178fcf5ef2aSThomas Huth { 5179fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5180fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5181efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5182fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5183fcf5ef2aSThomas Huth } 5184efe843d8SDavid Gibson } 5185fcf5ef2aSThomas Huth 5186fcf5ef2aSThomas Huth /* divo - divo. */ 5187fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5188fcf5ef2aSThomas Huth { 5189fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5190fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5191efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5192fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5193fcf5ef2aSThomas Huth } 5194efe843d8SDavid Gibson } 5195fcf5ef2aSThomas Huth 5196fcf5ef2aSThomas Huth /* divs - divs. */ 5197fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5198fcf5ef2aSThomas Huth { 5199fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5200fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5201efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5202fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5203fcf5ef2aSThomas Huth } 5204efe843d8SDavid Gibson } 5205fcf5ef2aSThomas Huth 5206fcf5ef2aSThomas Huth /* divso - divso. */ 5207fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5208fcf5ef2aSThomas Huth { 5209fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5210fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5211efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5212fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5213fcf5ef2aSThomas Huth } 5214efe843d8SDavid Gibson } 5215fcf5ef2aSThomas Huth 5216fcf5ef2aSThomas Huth /* doz - doz. */ 5217fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5218fcf5ef2aSThomas Huth { 5219fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5220fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5221efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5222efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5223efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5224efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5225fcf5ef2aSThomas Huth tcg_gen_br(l2); 5226fcf5ef2aSThomas Huth gen_set_label(l1); 5227fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5228fcf5ef2aSThomas Huth gen_set_label(l2); 5229efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5230fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5231fcf5ef2aSThomas Huth } 5232efe843d8SDavid Gibson } 5233fcf5ef2aSThomas Huth 5234fcf5ef2aSThomas Huth /* dozo - dozo. */ 5235fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5236fcf5ef2aSThomas Huth { 5237fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5238fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5239fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5240fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5241fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5242fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5243fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5244efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5245efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5246fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5247fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5248fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5249fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5250fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5251fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5252fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5253fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5254fcf5ef2aSThomas Huth tcg_gen_br(l2); 5255fcf5ef2aSThomas Huth gen_set_label(l1); 5256fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5257fcf5ef2aSThomas Huth gen_set_label(l2); 5258fcf5ef2aSThomas Huth tcg_temp_free(t0); 5259fcf5ef2aSThomas Huth tcg_temp_free(t1); 5260fcf5ef2aSThomas Huth tcg_temp_free(t2); 5261efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5262fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5263fcf5ef2aSThomas Huth } 5264efe843d8SDavid Gibson } 5265fcf5ef2aSThomas Huth 5266fcf5ef2aSThomas Huth /* dozi */ 5267fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5268fcf5ef2aSThomas Huth { 5269fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5270fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5271fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5272fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5273fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5274fcf5ef2aSThomas Huth tcg_gen_br(l2); 5275fcf5ef2aSThomas Huth gen_set_label(l1); 5276fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5277fcf5ef2aSThomas Huth gen_set_label(l2); 5278efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5279fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5280fcf5ef2aSThomas Huth } 5281efe843d8SDavid Gibson } 5282fcf5ef2aSThomas Huth 5283fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5284fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5285fcf5ef2aSThomas Huth { 5286fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5287fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5288fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5289fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5290fcf5ef2aSThomas Huth 5291fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5292fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5293fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5294fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5295fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5296fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5297fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5298efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5299fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5300efe843d8SDavid Gibson } 5301fcf5ef2aSThomas Huth tcg_temp_free(t0); 5302fcf5ef2aSThomas Huth } 5303fcf5ef2aSThomas Huth 5304fcf5ef2aSThomas Huth /* maskg - maskg. */ 5305fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5306fcf5ef2aSThomas Huth { 5307fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5308fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5309fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5310fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5311fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5312fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5313fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5314fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5315fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5316fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5317fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5318fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5319fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5320fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5321fcf5ef2aSThomas Huth gen_set_label(l1); 5322fcf5ef2aSThomas Huth tcg_temp_free(t0); 5323fcf5ef2aSThomas Huth tcg_temp_free(t1); 5324fcf5ef2aSThomas Huth tcg_temp_free(t2); 5325fcf5ef2aSThomas Huth tcg_temp_free(t3); 5326efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5327fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5328fcf5ef2aSThomas Huth } 5329efe843d8SDavid Gibson } 5330fcf5ef2aSThomas Huth 5331fcf5ef2aSThomas Huth /* maskir - maskir. */ 5332fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5333fcf5ef2aSThomas Huth { 5334fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5335fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5336fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5337fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5338fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5339fcf5ef2aSThomas Huth tcg_temp_free(t0); 5340fcf5ef2aSThomas Huth tcg_temp_free(t1); 5341efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5342fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5343fcf5ef2aSThomas Huth } 5344efe843d8SDavid Gibson } 5345fcf5ef2aSThomas Huth 5346fcf5ef2aSThomas Huth /* mul - mul. */ 5347fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5348fcf5ef2aSThomas Huth { 5349fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5350fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5351fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5352fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5353fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5354fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5355fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5356fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5357fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5358fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5359fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5360fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5361fcf5ef2aSThomas Huth tcg_temp_free(t2); 5362efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5363fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5364fcf5ef2aSThomas Huth } 5365efe843d8SDavid Gibson } 5366fcf5ef2aSThomas Huth 5367fcf5ef2aSThomas Huth /* mulo - mulo. */ 5368fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5369fcf5ef2aSThomas Huth { 5370fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5371fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5372fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5373fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5374fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5375fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5376fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5377fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5378fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5379fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5380fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5381fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5382fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5383fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5384fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5385fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5386fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5387fcf5ef2aSThomas Huth gen_set_label(l1); 5388fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5389fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5390fcf5ef2aSThomas Huth tcg_temp_free(t2); 5391efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5392fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5393fcf5ef2aSThomas Huth } 5394efe843d8SDavid Gibson } 5395fcf5ef2aSThomas Huth 5396fcf5ef2aSThomas Huth /* nabs - nabs. */ 5397fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5398fcf5ef2aSThomas Huth { 5399fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5400fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5401fe21b785SRichard Henderson 5402fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5403fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5404efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5405fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5406fcf5ef2aSThomas Huth } 5407efe843d8SDavid Gibson } 5408fcf5ef2aSThomas Huth 5409fcf5ef2aSThomas Huth /* nabso - nabso. */ 5410fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5411fcf5ef2aSThomas Huth { 5412fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5413fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5414fe21b785SRichard Henderson 5415fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5416fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5417fcf5ef2aSThomas Huth /* nabs never overflows */ 5418fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5419efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5420fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5421fcf5ef2aSThomas Huth } 5422efe843d8SDavid Gibson } 5423fcf5ef2aSThomas Huth 5424fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5425fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5426fcf5ef2aSThomas Huth { 5427fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5428fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5429fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5430fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5431fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5432fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5433efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5434efe843d8SDavid Gibson ~MASK(mb, me)); 5435fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5436fcf5ef2aSThomas Huth tcg_temp_free(t0); 5437efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5438fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5439fcf5ef2aSThomas Huth } 5440efe843d8SDavid Gibson } 5441fcf5ef2aSThomas Huth 5442fcf5ef2aSThomas Huth /* rrib - rrib. */ 5443fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5444fcf5ef2aSThomas Huth { 5445fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5446fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5447fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5448fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5449fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5450fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5451fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5452fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5453fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5454fcf5ef2aSThomas Huth tcg_temp_free(t0); 5455fcf5ef2aSThomas Huth tcg_temp_free(t1); 5456efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5457fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5458fcf5ef2aSThomas Huth } 5459efe843d8SDavid Gibson } 5460fcf5ef2aSThomas Huth 5461fcf5ef2aSThomas Huth /* sle - sle. */ 5462fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5463fcf5ef2aSThomas Huth { 5464fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5465fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5466fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5467fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5468fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5469fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5470fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5471fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5472fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5473fcf5ef2aSThomas Huth tcg_temp_free(t0); 5474fcf5ef2aSThomas Huth tcg_temp_free(t1); 5475efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5476fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5477fcf5ef2aSThomas Huth } 5478efe843d8SDavid Gibson } 5479fcf5ef2aSThomas Huth 5480fcf5ef2aSThomas Huth /* sleq - sleq. */ 5481fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5482fcf5ef2aSThomas Huth { 5483fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5484fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5485fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5486fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5487fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5488fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5489fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5490fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5491fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5492fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5493fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5494fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5495fcf5ef2aSThomas Huth tcg_temp_free(t0); 5496fcf5ef2aSThomas Huth tcg_temp_free(t1); 5497fcf5ef2aSThomas Huth tcg_temp_free(t2); 5498efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5499fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5500fcf5ef2aSThomas Huth } 5501efe843d8SDavid Gibson } 5502fcf5ef2aSThomas Huth 5503fcf5ef2aSThomas Huth /* sliq - sliq. */ 5504fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5505fcf5ef2aSThomas Huth { 5506fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5507fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5508fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5509fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5510fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5511fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5512fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5513fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5514fcf5ef2aSThomas Huth tcg_temp_free(t0); 5515fcf5ef2aSThomas Huth tcg_temp_free(t1); 5516efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5517fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5518fcf5ef2aSThomas Huth } 5519efe843d8SDavid Gibson } 5520fcf5ef2aSThomas Huth 5521fcf5ef2aSThomas Huth /* slliq - slliq. */ 5522fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5523fcf5ef2aSThomas Huth { 5524fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5525fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5526fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5527fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5528fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5529fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5530fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5531fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5532fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5533fcf5ef2aSThomas Huth tcg_temp_free(t0); 5534fcf5ef2aSThomas Huth tcg_temp_free(t1); 5535efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5536fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5537fcf5ef2aSThomas Huth } 5538efe843d8SDavid Gibson } 5539fcf5ef2aSThomas Huth 5540fcf5ef2aSThomas Huth /* sllq - sllq. */ 5541fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5542fcf5ef2aSThomas Huth { 5543fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5544fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5545fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5546fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5547fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5548fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5549fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5550fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5551fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5552fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5553fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5554fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5555fcf5ef2aSThomas Huth tcg_gen_br(l2); 5556fcf5ef2aSThomas Huth gen_set_label(l1); 5557fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5558fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5559fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5560fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5561fcf5ef2aSThomas Huth gen_set_label(l2); 5562fcf5ef2aSThomas Huth tcg_temp_free(t0); 5563fcf5ef2aSThomas Huth tcg_temp_free(t1); 5564fcf5ef2aSThomas Huth tcg_temp_free(t2); 5565efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5566fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5567fcf5ef2aSThomas Huth } 5568efe843d8SDavid Gibson } 5569fcf5ef2aSThomas Huth 5570fcf5ef2aSThomas Huth /* slq - slq. */ 5571fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5572fcf5ef2aSThomas Huth { 5573fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5574fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5575fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5576fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5577fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5578fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5579fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5580fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5581fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5582fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5583fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5584fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5585fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5586fcf5ef2aSThomas Huth gen_set_label(l1); 5587fcf5ef2aSThomas Huth tcg_temp_free(t0); 5588fcf5ef2aSThomas Huth tcg_temp_free(t1); 5589efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5590fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5591fcf5ef2aSThomas Huth } 5592efe843d8SDavid Gibson } 5593fcf5ef2aSThomas Huth 5594fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5595fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5596fcf5ef2aSThomas Huth { 5597fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5598fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5599fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5600fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5601fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5602fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5603fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5604fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5605fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5606fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5607fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5608fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5609fcf5ef2aSThomas Huth gen_set_label(l1); 5610fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5611fcf5ef2aSThomas Huth tcg_temp_free(t0); 5612fcf5ef2aSThomas Huth tcg_temp_free(t1); 5613efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5614fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5615fcf5ef2aSThomas Huth } 5616efe843d8SDavid Gibson } 5617fcf5ef2aSThomas Huth 5618fcf5ef2aSThomas Huth /* sraq - sraq. */ 5619fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5620fcf5ef2aSThomas Huth { 5621fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5622fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5623fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5624fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5625fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5626fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5627fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5628fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5629fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5630fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5631fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5632fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5633fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5634fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5635fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5636fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5637fcf5ef2aSThomas Huth gen_set_label(l1); 5638fcf5ef2aSThomas Huth tcg_temp_free(t0); 5639fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5640fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5641fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5642fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5643fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5644fcf5ef2aSThomas Huth gen_set_label(l2); 5645fcf5ef2aSThomas Huth tcg_temp_free(t1); 5646fcf5ef2aSThomas Huth tcg_temp_free(t2); 5647efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5648fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5649fcf5ef2aSThomas Huth } 5650efe843d8SDavid Gibson } 5651fcf5ef2aSThomas Huth 5652fcf5ef2aSThomas Huth /* sre - sre. */ 5653fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5654fcf5ef2aSThomas Huth { 5655fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5656fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5657fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5658fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5659fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5660fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5661fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5662fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5663fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5664fcf5ef2aSThomas Huth tcg_temp_free(t0); 5665fcf5ef2aSThomas Huth tcg_temp_free(t1); 5666efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5667fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5668fcf5ef2aSThomas Huth } 5669efe843d8SDavid Gibson } 5670fcf5ef2aSThomas Huth 5671fcf5ef2aSThomas Huth /* srea - srea. */ 5672fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5673fcf5ef2aSThomas Huth { 5674fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5675fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5676fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5677fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5678fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5679fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5680fcf5ef2aSThomas Huth tcg_temp_free(t0); 5681fcf5ef2aSThomas Huth tcg_temp_free(t1); 5682efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5683fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5684fcf5ef2aSThomas Huth } 5685efe843d8SDavid Gibson } 5686fcf5ef2aSThomas Huth 5687fcf5ef2aSThomas Huth /* sreq */ 5688fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5689fcf5ef2aSThomas Huth { 5690fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5691fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5692fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5693fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5694fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5695fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5696fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5697fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5698fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5699fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5700fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5701fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5702fcf5ef2aSThomas Huth tcg_temp_free(t0); 5703fcf5ef2aSThomas Huth tcg_temp_free(t1); 5704fcf5ef2aSThomas Huth tcg_temp_free(t2); 5705efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5706fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5707fcf5ef2aSThomas Huth } 5708efe843d8SDavid Gibson } 5709fcf5ef2aSThomas Huth 5710fcf5ef2aSThomas Huth /* sriq */ 5711fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5712fcf5ef2aSThomas Huth { 5713fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5714fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5715fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5716fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5717fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5718fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5719fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5720fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5721fcf5ef2aSThomas Huth tcg_temp_free(t0); 5722fcf5ef2aSThomas Huth tcg_temp_free(t1); 5723efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5724fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5725fcf5ef2aSThomas Huth } 5726efe843d8SDavid Gibson } 5727fcf5ef2aSThomas Huth 5728fcf5ef2aSThomas Huth /* srliq */ 5729fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5730fcf5ef2aSThomas Huth { 5731fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5732fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5733fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5734fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5735fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5736fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5737fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5738fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5739fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5740fcf5ef2aSThomas Huth tcg_temp_free(t0); 5741fcf5ef2aSThomas Huth tcg_temp_free(t1); 5742efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5743fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5744fcf5ef2aSThomas Huth } 5745efe843d8SDavid Gibson } 5746fcf5ef2aSThomas Huth 5747fcf5ef2aSThomas Huth /* srlq */ 5748fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5749fcf5ef2aSThomas Huth { 5750fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5751fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5752fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5753fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5754fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5755fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5756fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5757fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5758fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5759fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5760fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5761fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5762fcf5ef2aSThomas Huth tcg_gen_br(l2); 5763fcf5ef2aSThomas Huth gen_set_label(l1); 5764fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5765fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5766fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5767fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5768fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5769fcf5ef2aSThomas Huth gen_set_label(l2); 5770fcf5ef2aSThomas Huth tcg_temp_free(t0); 5771fcf5ef2aSThomas Huth tcg_temp_free(t1); 5772fcf5ef2aSThomas Huth tcg_temp_free(t2); 5773efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5774fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5775fcf5ef2aSThomas Huth } 5776efe843d8SDavid Gibson } 5777fcf5ef2aSThomas Huth 5778fcf5ef2aSThomas Huth /* srq */ 5779fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5780fcf5ef2aSThomas Huth { 5781fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5782fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5783fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5784fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5785fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5786fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5787fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5788fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5789fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5790fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5791fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5792fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5793fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5794fcf5ef2aSThomas Huth gen_set_label(l1); 5795fcf5ef2aSThomas Huth tcg_temp_free(t0); 5796fcf5ef2aSThomas Huth tcg_temp_free(t1); 5797efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5798fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5799fcf5ef2aSThomas Huth } 5800efe843d8SDavid Gibson } 5801fcf5ef2aSThomas Huth 5802fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5803fcf5ef2aSThomas Huth 5804fcf5ef2aSThomas Huth /* dsa */ 5805fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5806fcf5ef2aSThomas Huth { 5807fcf5ef2aSThomas Huth /* XXX: TODO */ 5808fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5809fcf5ef2aSThomas Huth } 5810fcf5ef2aSThomas Huth 5811fcf5ef2aSThomas Huth /* esa */ 5812fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5813fcf5ef2aSThomas Huth { 5814fcf5ef2aSThomas Huth /* XXX: TODO */ 5815fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5816fcf5ef2aSThomas Huth } 5817fcf5ef2aSThomas Huth 5818fcf5ef2aSThomas Huth /* mfrom */ 5819fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5820fcf5ef2aSThomas Huth { 5821fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5822fcf5ef2aSThomas Huth GEN_PRIV; 5823fcf5ef2aSThomas Huth #else 5824fcf5ef2aSThomas Huth CHK_SV; 5825fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5826fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5827fcf5ef2aSThomas Huth } 5828fcf5ef2aSThomas Huth 5829fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5830fcf5ef2aSThomas Huth 5831fcf5ef2aSThomas Huth /* tlbld */ 5832fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5833fcf5ef2aSThomas Huth { 5834fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5835fcf5ef2aSThomas Huth GEN_PRIV; 5836fcf5ef2aSThomas Huth #else 5837fcf5ef2aSThomas Huth CHK_SV; 5838fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5839fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5840fcf5ef2aSThomas Huth } 5841fcf5ef2aSThomas Huth 5842fcf5ef2aSThomas Huth /* tlbli */ 5843fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5844fcf5ef2aSThomas Huth { 5845fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5846fcf5ef2aSThomas Huth GEN_PRIV; 5847fcf5ef2aSThomas Huth #else 5848fcf5ef2aSThomas Huth CHK_SV; 5849fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5850fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5851fcf5ef2aSThomas Huth } 5852fcf5ef2aSThomas Huth 5853fcf5ef2aSThomas Huth /* 74xx TLB management */ 5854fcf5ef2aSThomas Huth 5855fcf5ef2aSThomas Huth /* tlbld */ 5856fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5857fcf5ef2aSThomas Huth { 5858fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5859fcf5ef2aSThomas Huth GEN_PRIV; 5860fcf5ef2aSThomas Huth #else 5861fcf5ef2aSThomas Huth CHK_SV; 5862fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5863fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5864fcf5ef2aSThomas Huth } 5865fcf5ef2aSThomas Huth 5866fcf5ef2aSThomas Huth /* tlbli */ 5867fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5868fcf5ef2aSThomas Huth { 5869fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5870fcf5ef2aSThomas Huth GEN_PRIV; 5871fcf5ef2aSThomas Huth #else 5872fcf5ef2aSThomas Huth CHK_SV; 5873fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5874fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5875fcf5ef2aSThomas Huth } 5876fcf5ef2aSThomas Huth 5877fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5878fcf5ef2aSThomas Huth 5879fcf5ef2aSThomas Huth /* clf */ 5880fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5881fcf5ef2aSThomas Huth { 5882fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5883fcf5ef2aSThomas Huth } 5884fcf5ef2aSThomas Huth 5885fcf5ef2aSThomas Huth /* cli */ 5886fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5887fcf5ef2aSThomas Huth { 5888fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5889fcf5ef2aSThomas Huth GEN_PRIV; 5890fcf5ef2aSThomas Huth #else 5891fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5892fcf5ef2aSThomas Huth CHK_SV; 5893fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5894fcf5ef2aSThomas Huth } 5895fcf5ef2aSThomas Huth 5896fcf5ef2aSThomas Huth /* dclst */ 5897fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5898fcf5ef2aSThomas Huth { 5899fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5900fcf5ef2aSThomas Huth } 5901fcf5ef2aSThomas Huth 5902fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5903fcf5ef2aSThomas Huth { 5904fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5905fcf5ef2aSThomas Huth GEN_PRIV; 5906fcf5ef2aSThomas Huth #else 5907fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5908fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5909fcf5ef2aSThomas Huth TCGv t0; 5910fcf5ef2aSThomas Huth 5911fcf5ef2aSThomas Huth CHK_SV; 5912fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5913fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5914e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 5915fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5916fcf5ef2aSThomas Huth tcg_temp_free(t0); 5917efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 5918fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5919efe843d8SDavid Gibson } 5920fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5921fcf5ef2aSThomas Huth } 5922fcf5ef2aSThomas Huth 5923fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5924fcf5ef2aSThomas Huth { 5925fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5926fcf5ef2aSThomas Huth GEN_PRIV; 5927fcf5ef2aSThomas Huth #else 5928fcf5ef2aSThomas Huth TCGv t0; 5929fcf5ef2aSThomas Huth 5930fcf5ef2aSThomas Huth CHK_SV; 5931fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5932fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5933fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5934fcf5ef2aSThomas Huth tcg_temp_free(t0); 5935fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5936fcf5ef2aSThomas Huth } 5937fcf5ef2aSThomas Huth 5938fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5939fcf5ef2aSThomas Huth { 5940fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5941fcf5ef2aSThomas Huth GEN_PRIV; 5942fcf5ef2aSThomas Huth #else 5943fcf5ef2aSThomas Huth CHK_SV; 5944fcf5ef2aSThomas Huth 5945fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5946fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5947fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5948fcf5ef2aSThomas Huth } 5949fcf5ef2aSThomas Huth 5950fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5951fcf5ef2aSThomas Huth 5952fcf5ef2aSThomas Huth /* BookE specific instructions */ 5953fcf5ef2aSThomas Huth 5954fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5955fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5956fcf5ef2aSThomas Huth { 5957fcf5ef2aSThomas Huth /* XXX: TODO */ 5958fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5959fcf5ef2aSThomas Huth } 5960fcf5ef2aSThomas Huth 5961fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5962fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5963fcf5ef2aSThomas Huth { 5964fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5965fcf5ef2aSThomas Huth GEN_PRIV; 5966fcf5ef2aSThomas Huth #else 5967fcf5ef2aSThomas Huth TCGv t0; 5968fcf5ef2aSThomas Huth 5969fcf5ef2aSThomas Huth CHK_SV; 5970fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5971fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5972fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5973fcf5ef2aSThomas Huth tcg_temp_free(t0); 5974fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5975fcf5ef2aSThomas Huth } 5976fcf5ef2aSThomas Huth 5977fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5978fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5979fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5980fcf5ef2aSThomas Huth { 5981fcf5ef2aSThomas Huth TCGv t0, t1; 5982fcf5ef2aSThomas Huth 5983fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5984fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5985fcf5ef2aSThomas Huth 5986fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5987fcf5ef2aSThomas Huth case 0x05: 5988fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5989fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5990fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5991fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5992fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5993fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5994fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5995fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5996fcf5ef2aSThomas Huth break; 5997fcf5ef2aSThomas Huth case 0x04: 5998fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5999fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6000fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6001fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6002fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6003fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6004fcf5ef2aSThomas Huth break; 6005fcf5ef2aSThomas Huth case 0x01: 6006fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6007fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6008fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6009fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6010fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6011fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6012fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6013fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6014fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6015fcf5ef2aSThomas Huth break; 6016fcf5ef2aSThomas Huth case 0x00: 6017fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6018fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6019fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6020fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6021fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6022fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6023fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6024fcf5ef2aSThomas Huth break; 6025fcf5ef2aSThomas Huth case 0x0D: 6026fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6027fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6028fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6029fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6030fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6031fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6032fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6033fcf5ef2aSThomas Huth break; 6034fcf5ef2aSThomas Huth case 0x0C: 6035fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6036fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6037fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6038fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6039fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6040fcf5ef2aSThomas Huth break; 6041fcf5ef2aSThomas Huth } 6042fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6043fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6044fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6045fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6046fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6047fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6048fcf5ef2aSThomas Huth } else { 6049fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6050fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6051fcf5ef2aSThomas Huth } 6052fcf5ef2aSThomas Huth 6053fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6054fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6055fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6056fcf5ef2aSThomas Huth 6057fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6058fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6059fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6060fcf5ef2aSThomas Huth } 6061fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6062fcf5ef2aSThomas Huth /* Signed */ 6063fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6064fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6065fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6066fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6067fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6068fcf5ef2aSThomas Huth /* Saturate */ 6069fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6070fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6071fcf5ef2aSThomas Huth } 6072fcf5ef2aSThomas Huth } else { 6073fcf5ef2aSThomas Huth /* Unsigned */ 6074fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6075fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6076fcf5ef2aSThomas Huth /* Saturate */ 6077fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6078fcf5ef2aSThomas Huth } 6079fcf5ef2aSThomas Huth } 6080fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6081fcf5ef2aSThomas Huth /* Check overflow */ 6082fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6083fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6084fcf5ef2aSThomas Huth } 6085fcf5ef2aSThomas Huth gen_set_label(l1); 6086fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6087fcf5ef2aSThomas Huth } 6088fcf5ef2aSThomas Huth } else { 6089fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6090fcf5ef2aSThomas Huth } 6091fcf5ef2aSThomas Huth tcg_temp_free(t0); 6092fcf5ef2aSThomas Huth tcg_temp_free(t1); 6093fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6094fcf5ef2aSThomas Huth /* Update Rc0 */ 6095fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6096fcf5ef2aSThomas Huth } 6097fcf5ef2aSThomas Huth } 6098fcf5ef2aSThomas Huth 6099fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6100fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6101fcf5ef2aSThomas Huth { \ 6102fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6103fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6104fcf5ef2aSThomas Huth } 6105fcf5ef2aSThomas Huth 6106fcf5ef2aSThomas Huth /* macchw - macchw. */ 6107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6108fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6110fcf5ef2aSThomas Huth /* macchws - macchws. */ 6111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6112fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6114fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6116fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6118fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6120fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6122fcf5ef2aSThomas Huth /* machhw - machhw. */ 6123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6124fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6126fcf5ef2aSThomas Huth /* machhws - machhws. */ 6127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6128fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6130fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6132fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6134fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6136fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6138fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6140fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6141fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6142fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6143fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6144fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6145fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6146fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6147fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6148fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6149fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6150fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6151fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6152fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6153fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6154fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6155fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6156fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6157fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6158fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6159fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6160fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6161fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6162fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6163fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6164fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6165fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6166fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6167fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6168fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6169fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6170fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6171fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6172fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6173fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6174fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6175fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6176fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6177fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6178fcf5ef2aSThomas Huth 6179fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6180fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6181fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6182fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6183fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6184fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6185fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6186fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6187fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6188fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6189fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6190fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6191fcf5ef2aSThomas Huth 6192fcf5ef2aSThomas Huth /* mfdcr */ 6193fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6194fcf5ef2aSThomas Huth { 6195fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6196fcf5ef2aSThomas Huth GEN_PRIV; 6197fcf5ef2aSThomas Huth #else 6198fcf5ef2aSThomas Huth TCGv dcrn; 6199fcf5ef2aSThomas Huth 6200fcf5ef2aSThomas Huth CHK_SV; 6201fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6202fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6203fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6204fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6205fcf5ef2aSThomas Huth } 6206fcf5ef2aSThomas Huth 6207fcf5ef2aSThomas Huth /* mtdcr */ 6208fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6209fcf5ef2aSThomas Huth { 6210fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6211fcf5ef2aSThomas Huth GEN_PRIV; 6212fcf5ef2aSThomas Huth #else 6213fcf5ef2aSThomas Huth TCGv dcrn; 6214fcf5ef2aSThomas Huth 6215fcf5ef2aSThomas Huth CHK_SV; 6216fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6217fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6218fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6219fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6220fcf5ef2aSThomas Huth } 6221fcf5ef2aSThomas Huth 6222fcf5ef2aSThomas Huth /* mfdcrx */ 6223fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6224fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6225fcf5ef2aSThomas Huth { 6226fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6227fcf5ef2aSThomas Huth GEN_PRIV; 6228fcf5ef2aSThomas Huth #else 6229fcf5ef2aSThomas Huth CHK_SV; 6230fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6231fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6232fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6233fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6234fcf5ef2aSThomas Huth } 6235fcf5ef2aSThomas Huth 6236fcf5ef2aSThomas Huth /* mtdcrx */ 6237fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6238fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6239fcf5ef2aSThomas Huth { 6240fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6241fcf5ef2aSThomas Huth GEN_PRIV; 6242fcf5ef2aSThomas Huth #else 6243fcf5ef2aSThomas Huth CHK_SV; 6244fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6245fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6246fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6247fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6248fcf5ef2aSThomas Huth } 6249fcf5ef2aSThomas Huth 6250fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6251fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6252fcf5ef2aSThomas Huth { 6253fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6254fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6255fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6256fcf5ef2aSThomas Huth } 6257fcf5ef2aSThomas Huth 6258fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6259fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6260fcf5ef2aSThomas Huth { 6261fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6262fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6263fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6264fcf5ef2aSThomas Huth } 6265fcf5ef2aSThomas Huth 6266fcf5ef2aSThomas Huth /* dccci */ 6267fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6268fcf5ef2aSThomas Huth { 6269fcf5ef2aSThomas Huth CHK_SV; 6270fcf5ef2aSThomas Huth /* interpreted as no-op */ 6271fcf5ef2aSThomas Huth } 6272fcf5ef2aSThomas Huth 6273fcf5ef2aSThomas Huth /* dcread */ 6274fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6275fcf5ef2aSThomas Huth { 6276fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6277fcf5ef2aSThomas Huth GEN_PRIV; 6278fcf5ef2aSThomas Huth #else 6279fcf5ef2aSThomas Huth TCGv EA, val; 6280fcf5ef2aSThomas Huth 6281fcf5ef2aSThomas Huth CHK_SV; 6282fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6283fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6284fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6285fcf5ef2aSThomas Huth val = tcg_temp_new(); 6286fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6287fcf5ef2aSThomas Huth tcg_temp_free(val); 6288fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6289fcf5ef2aSThomas Huth tcg_temp_free(EA); 6290fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6291fcf5ef2aSThomas Huth } 6292fcf5ef2aSThomas Huth 6293fcf5ef2aSThomas Huth /* icbt */ 6294fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6295fcf5ef2aSThomas Huth { 6296efe843d8SDavid Gibson /* 6297efe843d8SDavid Gibson * interpreted as no-op 6298efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6299efe843d8SDavid Gibson * does not generate any exception 6300fcf5ef2aSThomas Huth */ 6301fcf5ef2aSThomas Huth } 6302fcf5ef2aSThomas Huth 6303fcf5ef2aSThomas Huth /* iccci */ 6304fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6305fcf5ef2aSThomas Huth { 6306fcf5ef2aSThomas Huth CHK_SV; 6307fcf5ef2aSThomas Huth /* interpreted as no-op */ 6308fcf5ef2aSThomas Huth } 6309fcf5ef2aSThomas Huth 6310fcf5ef2aSThomas Huth /* icread */ 6311fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6312fcf5ef2aSThomas Huth { 6313fcf5ef2aSThomas Huth CHK_SV; 6314fcf5ef2aSThomas Huth /* interpreted as no-op */ 6315fcf5ef2aSThomas Huth } 6316fcf5ef2aSThomas Huth 6317fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6318fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6319fcf5ef2aSThomas Huth { 6320fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6321fcf5ef2aSThomas Huth GEN_PRIV; 6322fcf5ef2aSThomas Huth #else 6323fcf5ef2aSThomas Huth CHK_SV; 6324fcf5ef2aSThomas Huth /* Restore CPU state */ 6325fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 6326fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6327fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6328fcf5ef2aSThomas Huth } 6329fcf5ef2aSThomas Huth 6330fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6331fcf5ef2aSThomas Huth { 6332fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6333fcf5ef2aSThomas Huth GEN_PRIV; 6334fcf5ef2aSThomas Huth #else 6335fcf5ef2aSThomas Huth CHK_SV; 6336fcf5ef2aSThomas Huth /* Restore CPU state */ 6337fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 6338fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6339fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6340fcf5ef2aSThomas Huth } 6341fcf5ef2aSThomas Huth 6342fcf5ef2aSThomas Huth /* BookE specific */ 6343fcf5ef2aSThomas Huth 6344fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6345fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6346fcf5ef2aSThomas Huth { 6347fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6348fcf5ef2aSThomas Huth GEN_PRIV; 6349fcf5ef2aSThomas Huth #else 6350fcf5ef2aSThomas Huth CHK_SV; 6351fcf5ef2aSThomas Huth /* Restore CPU state */ 6352fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 6353fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6354fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6355fcf5ef2aSThomas Huth } 6356fcf5ef2aSThomas Huth 6357fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6358fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6359fcf5ef2aSThomas Huth { 6360fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6361fcf5ef2aSThomas Huth GEN_PRIV; 6362fcf5ef2aSThomas Huth #else 6363fcf5ef2aSThomas Huth CHK_SV; 6364fcf5ef2aSThomas Huth /* Restore CPU state */ 6365fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 6366fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6367fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6368fcf5ef2aSThomas Huth } 6369fcf5ef2aSThomas Huth 6370fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6371fcf5ef2aSThomas Huth 6372fcf5ef2aSThomas Huth /* tlbre */ 6373fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6374fcf5ef2aSThomas Huth { 6375fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6376fcf5ef2aSThomas Huth GEN_PRIV; 6377fcf5ef2aSThomas Huth #else 6378fcf5ef2aSThomas Huth CHK_SV; 6379fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6380fcf5ef2aSThomas Huth case 0: 6381fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6382fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6383fcf5ef2aSThomas Huth break; 6384fcf5ef2aSThomas Huth case 1: 6385fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6386fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6387fcf5ef2aSThomas Huth break; 6388fcf5ef2aSThomas Huth default: 6389fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6390fcf5ef2aSThomas Huth break; 6391fcf5ef2aSThomas Huth } 6392fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6393fcf5ef2aSThomas Huth } 6394fcf5ef2aSThomas Huth 6395fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6396fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6397fcf5ef2aSThomas Huth { 6398fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6399fcf5ef2aSThomas Huth GEN_PRIV; 6400fcf5ef2aSThomas Huth #else 6401fcf5ef2aSThomas Huth TCGv t0; 6402fcf5ef2aSThomas Huth 6403fcf5ef2aSThomas Huth CHK_SV; 6404fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6405fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6406fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6407fcf5ef2aSThomas Huth tcg_temp_free(t0); 6408fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6409fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6410fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6411fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6412fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6413fcf5ef2aSThomas Huth gen_set_label(l1); 6414fcf5ef2aSThomas Huth } 6415fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6416fcf5ef2aSThomas Huth } 6417fcf5ef2aSThomas Huth 6418fcf5ef2aSThomas Huth /* tlbwe */ 6419fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6420fcf5ef2aSThomas Huth { 6421fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6422fcf5ef2aSThomas Huth GEN_PRIV; 6423fcf5ef2aSThomas Huth #else 6424fcf5ef2aSThomas Huth CHK_SV; 6425fcf5ef2aSThomas Huth 6426fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6427fcf5ef2aSThomas Huth case 0: 6428fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6429fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6430fcf5ef2aSThomas Huth break; 6431fcf5ef2aSThomas Huth case 1: 6432fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6433fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6434fcf5ef2aSThomas Huth break; 6435fcf5ef2aSThomas Huth default: 6436fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6437fcf5ef2aSThomas Huth break; 6438fcf5ef2aSThomas Huth } 6439fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6440fcf5ef2aSThomas Huth } 6441fcf5ef2aSThomas Huth 6442fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6443fcf5ef2aSThomas Huth 6444fcf5ef2aSThomas Huth /* tlbre */ 6445fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6446fcf5ef2aSThomas Huth { 6447fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6448fcf5ef2aSThomas Huth GEN_PRIV; 6449fcf5ef2aSThomas Huth #else 6450fcf5ef2aSThomas Huth CHK_SV; 6451fcf5ef2aSThomas Huth 6452fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6453fcf5ef2aSThomas Huth case 0: 6454fcf5ef2aSThomas Huth case 1: 6455fcf5ef2aSThomas Huth case 2: 6456fcf5ef2aSThomas Huth { 6457fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6458fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6459fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6460fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6461fcf5ef2aSThomas Huth } 6462fcf5ef2aSThomas Huth break; 6463fcf5ef2aSThomas Huth default: 6464fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6465fcf5ef2aSThomas Huth break; 6466fcf5ef2aSThomas Huth } 6467fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6468fcf5ef2aSThomas Huth } 6469fcf5ef2aSThomas Huth 6470fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6471fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6472fcf5ef2aSThomas Huth { 6473fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6474fcf5ef2aSThomas Huth GEN_PRIV; 6475fcf5ef2aSThomas Huth #else 6476fcf5ef2aSThomas Huth TCGv t0; 6477fcf5ef2aSThomas Huth 6478fcf5ef2aSThomas Huth CHK_SV; 6479fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6480fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6481fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6482fcf5ef2aSThomas Huth tcg_temp_free(t0); 6483fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6484fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6485fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6486fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6487fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6488fcf5ef2aSThomas Huth gen_set_label(l1); 6489fcf5ef2aSThomas Huth } 6490fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6491fcf5ef2aSThomas Huth } 6492fcf5ef2aSThomas Huth 6493fcf5ef2aSThomas Huth /* tlbwe */ 6494fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6495fcf5ef2aSThomas Huth { 6496fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6497fcf5ef2aSThomas Huth GEN_PRIV; 6498fcf5ef2aSThomas Huth #else 6499fcf5ef2aSThomas Huth CHK_SV; 6500fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6501fcf5ef2aSThomas Huth case 0: 6502fcf5ef2aSThomas Huth case 1: 6503fcf5ef2aSThomas Huth case 2: 6504fcf5ef2aSThomas Huth { 6505fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6506fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6507fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6508fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6509fcf5ef2aSThomas Huth } 6510fcf5ef2aSThomas Huth break; 6511fcf5ef2aSThomas Huth default: 6512fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6513fcf5ef2aSThomas Huth break; 6514fcf5ef2aSThomas Huth } 6515fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6516fcf5ef2aSThomas Huth } 6517fcf5ef2aSThomas Huth 6518fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6519fcf5ef2aSThomas Huth 6520fcf5ef2aSThomas Huth /* tlbre */ 6521fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6522fcf5ef2aSThomas Huth { 6523fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6524fcf5ef2aSThomas Huth GEN_PRIV; 6525fcf5ef2aSThomas Huth #else 6526fcf5ef2aSThomas Huth CHK_SV; 6527fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6528fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6529fcf5ef2aSThomas Huth } 6530fcf5ef2aSThomas Huth 6531fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6532fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6533fcf5ef2aSThomas Huth { 6534fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6535fcf5ef2aSThomas Huth GEN_PRIV; 6536fcf5ef2aSThomas Huth #else 6537fcf5ef2aSThomas Huth TCGv t0; 6538fcf5ef2aSThomas Huth 6539fcf5ef2aSThomas Huth CHK_SV; 6540fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6541fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6542fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6543fcf5ef2aSThomas Huth } else { 6544fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6545fcf5ef2aSThomas Huth } 6546fcf5ef2aSThomas Huth 6547fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6548fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6549fcf5ef2aSThomas Huth tcg_temp_free(t0); 6550fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6551fcf5ef2aSThomas Huth } 6552fcf5ef2aSThomas Huth 6553fcf5ef2aSThomas Huth /* tlbwe */ 6554fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6555fcf5ef2aSThomas Huth { 6556fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6557fcf5ef2aSThomas Huth GEN_PRIV; 6558fcf5ef2aSThomas Huth #else 6559fcf5ef2aSThomas Huth CHK_SV; 6560fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6561fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6562fcf5ef2aSThomas Huth } 6563fcf5ef2aSThomas Huth 6564fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6565fcf5ef2aSThomas Huth { 6566fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6567fcf5ef2aSThomas Huth GEN_PRIV; 6568fcf5ef2aSThomas Huth #else 6569fcf5ef2aSThomas Huth TCGv t0; 6570fcf5ef2aSThomas Huth 6571fcf5ef2aSThomas Huth CHK_SV; 6572fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6573fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6574fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6575fcf5ef2aSThomas Huth tcg_temp_free(t0); 6576fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6577fcf5ef2aSThomas Huth } 6578fcf5ef2aSThomas Huth 6579fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6580fcf5ef2aSThomas Huth { 6581fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6582fcf5ef2aSThomas Huth GEN_PRIV; 6583fcf5ef2aSThomas Huth #else 6584fcf5ef2aSThomas Huth TCGv t0; 6585fcf5ef2aSThomas Huth 6586fcf5ef2aSThomas Huth CHK_SV; 6587fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6588fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6589fcf5ef2aSThomas Huth 6590fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 6591fcf5ef2aSThomas Huth case 0: 6592fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6593fcf5ef2aSThomas Huth break; 6594fcf5ef2aSThomas Huth case 1: 6595fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6596fcf5ef2aSThomas Huth break; 6597fcf5ef2aSThomas Huth case 3: 6598fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6599fcf5ef2aSThomas Huth break; 6600fcf5ef2aSThomas Huth default: 6601fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6602fcf5ef2aSThomas Huth break; 6603fcf5ef2aSThomas Huth } 6604fcf5ef2aSThomas Huth 6605fcf5ef2aSThomas Huth tcg_temp_free(t0); 6606fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6607fcf5ef2aSThomas Huth } 6608fcf5ef2aSThomas Huth 6609fcf5ef2aSThomas Huth 6610fcf5ef2aSThomas Huth /* wrtee */ 6611fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6612fcf5ef2aSThomas Huth { 6613fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6614fcf5ef2aSThomas Huth GEN_PRIV; 6615fcf5ef2aSThomas Huth #else 6616fcf5ef2aSThomas Huth TCGv t0; 6617fcf5ef2aSThomas Huth 6618fcf5ef2aSThomas Huth CHK_SV; 6619fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6620fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6621fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6622fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6623fcf5ef2aSThomas Huth tcg_temp_free(t0); 6624efe843d8SDavid Gibson /* 6625efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6626efe843d8SDavid Gibson * just set msr_ee to 1 6627fcf5ef2aSThomas Huth */ 6628fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6629fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6630fcf5ef2aSThomas Huth } 6631fcf5ef2aSThomas Huth 6632fcf5ef2aSThomas Huth /* wrteei */ 6633fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6634fcf5ef2aSThomas Huth { 6635fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6636fcf5ef2aSThomas Huth GEN_PRIV; 6637fcf5ef2aSThomas Huth #else 6638fcf5ef2aSThomas Huth CHK_SV; 6639fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6640fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6641fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6642fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6643fcf5ef2aSThomas Huth } else { 6644fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6645fcf5ef2aSThomas Huth } 6646fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6647fcf5ef2aSThomas Huth } 6648fcf5ef2aSThomas Huth 6649fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6650fcf5ef2aSThomas Huth 6651fcf5ef2aSThomas Huth /* dlmzb */ 6652fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6653fcf5ef2aSThomas Huth { 6654fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6655fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6656fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6657fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6658fcf5ef2aSThomas Huth } 6659fcf5ef2aSThomas Huth 6660fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6661fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6662fcf5ef2aSThomas Huth { 6663fcf5ef2aSThomas Huth /* interpreted as no-op */ 6664fcf5ef2aSThomas Huth } 6665fcf5ef2aSThomas Huth 6666fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6667fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6668fcf5ef2aSThomas Huth { 666927a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 667027a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 667127a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 667227a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 667327a3ea7eSBALATON Zoltan } 667427a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6675fcf5ef2aSThomas Huth } 6676fcf5ef2aSThomas Huth 6677fcf5ef2aSThomas Huth /* icbt */ 6678fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6679fcf5ef2aSThomas Huth { 6680efe843d8SDavid Gibson /* 6681efe843d8SDavid Gibson * interpreted as no-op 6682efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6683efe843d8SDavid Gibson * does not generate any exception 6684fcf5ef2aSThomas Huth */ 6685fcf5ef2aSThomas Huth } 6686fcf5ef2aSThomas Huth 6687fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6688fcf5ef2aSThomas Huth 6689fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6690fcf5ef2aSThomas Huth { 6691fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6692fcf5ef2aSThomas Huth GEN_PRIV; 6693fcf5ef2aSThomas Huth #else 6694ebca5e6dSCédric Le Goater CHK_HV; 6695d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 66967af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 66977af1e7b0SCédric Le Goater } else { 6698fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 66997af1e7b0SCédric Le Goater } 6700fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6701fcf5ef2aSThomas Huth } 6702fcf5ef2aSThomas Huth 6703fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6704fcf5ef2aSThomas Huth { 6705fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6706fcf5ef2aSThomas Huth GEN_PRIV; 6707fcf5ef2aSThomas Huth #else 6708ebca5e6dSCédric Le Goater CHK_HV; 6709d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 67107af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 67117af1e7b0SCédric Le Goater } else { 6712fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 67137af1e7b0SCédric Le Goater } 6714fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6715fcf5ef2aSThomas Huth } 6716fcf5ef2aSThomas Huth 67175ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 67185ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 67195ba7ba1dSCédric Le Goater { 67205ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 67215ba7ba1dSCédric Le Goater GEN_PRIV; 67225ba7ba1dSCédric Le Goater #else 67235ba7ba1dSCédric Le Goater CHK_SV; 67245ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 67255ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 67265ba7ba1dSCédric Le Goater } 67275ba7ba1dSCédric Le Goater 67285ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 67295ba7ba1dSCédric Le Goater { 67305ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 67315ba7ba1dSCédric Le Goater GEN_PRIV; 67325ba7ba1dSCédric Le Goater #else 67335ba7ba1dSCédric Le Goater CHK_SV; 67345ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 67355ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 67365ba7ba1dSCédric Le Goater } 67375ba7ba1dSCédric Le Goater #endif 67385ba7ba1dSCédric Le Goater 67397af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 67407af1e7b0SCédric Le Goater { 67417af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 67427af1e7b0SCédric Le Goater GEN_PRIV; 67437af1e7b0SCédric Le Goater #else 67447af1e7b0SCédric Le Goater CHK_HV; 67457af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 67467af1e7b0SCédric Le Goater /* interpreted as no-op */ 67477af1e7b0SCédric Le Goater } 6748fcf5ef2aSThomas Huth 6749fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6750fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6751fcf5ef2aSThomas Huth { 6752fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6753fcf5ef2aSThomas Huth 6754fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6755fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6756fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6757fcf5ef2aSThomas Huth } 6758fcf5ef2aSThomas Huth 6759fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6760fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6761fcf5ef2aSThomas Huth { 6762fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6763fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6764fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6765fcf5ef2aSThomas Huth 6766fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6767fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6768fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6769fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6770fcf5ef2aSThomas Huth } else { 6771fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6772fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6773fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6774fcf5ef2aSThomas Huth } 6775fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6776fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6777fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6778fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6779fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6780fcf5ef2aSThomas Huth } 6781fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6782fcf5ef2aSThomas Huth 6783fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6784fcf5ef2aSThomas Huth { 6785fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6786fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6787fcf5ef2aSThomas Huth return; 6788fcf5ef2aSThomas Huth } 6789fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6790fcf5ef2aSThomas Huth } 6791fcf5ef2aSThomas Huth 6792fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6793fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6794fcf5ef2aSThomas Huth { \ 6795fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6796fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6797fcf5ef2aSThomas Huth return; \ 6798fcf5ef2aSThomas Huth } \ 6799efe843d8SDavid Gibson /* \ 6800efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6801fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6802fcf5ef2aSThomas Huth * \ 6803fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6804fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6805fcf5ef2aSThomas Huth */ \ 6806fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6807fcf5ef2aSThomas Huth } 6808fcf5ef2aSThomas Huth 6809fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6810fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6811fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6812fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6813fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6814fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6815fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6816efe843d8SDavid Gibson 6817b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6818b8b4576eSSuraj Jitindar Singh { 6819efe843d8SDavid Gibson /* Do Nothing */ 6820b8b4576eSSuraj Jitindar Singh } 6821fcf5ef2aSThomas Huth 682280b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 682380b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 682480b8c1eeSNikunj A Dadhania { \ 6825efe843d8SDavid Gibson /* \ 6826efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6827efe843d8SDavid Gibson * implementation of the copy paste facility \ 682880b8c1eeSNikunj A Dadhania */ \ 682980b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 683080b8c1eeSNikunj A Dadhania } 683180b8c1eeSNikunj A Dadhania 683280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 683380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 683480b8c1eeSNikunj A Dadhania 6835fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6836fcf5ef2aSThomas Huth { 6837fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6838fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6839fcf5ef2aSThomas Huth return; 6840fcf5ef2aSThomas Huth } 6841efe843d8SDavid Gibson /* 6842efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6843efe843d8SDavid Gibson * simple: 6844fcf5ef2aSThomas Huth * 6845fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6846fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6847fcf5ef2aSThomas Huth */ 6848fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6849fcf5ef2aSThomas Huth } 6850fcf5ef2aSThomas Huth 6851fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6852fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6853fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6854fcf5ef2aSThomas Huth { \ 6855fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6856fcf5ef2aSThomas Huth } 6857fcf5ef2aSThomas Huth 6858fcf5ef2aSThomas Huth #else 6859fcf5ef2aSThomas Huth 6860fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6861fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6862fcf5ef2aSThomas Huth { \ 6863fcf5ef2aSThomas Huth CHK_SV; \ 6864fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6865fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6866fcf5ef2aSThomas Huth return; \ 6867fcf5ef2aSThomas Huth } \ 6868efe843d8SDavid Gibson /* \ 6869efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6870fcf5ef2aSThomas Huth * simple: \ 6871fcf5ef2aSThomas Huth * \ 6872fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6873fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6874fcf5ef2aSThomas Huth */ \ 6875fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6876fcf5ef2aSThomas Huth } 6877fcf5ef2aSThomas Huth 6878fcf5ef2aSThomas Huth #endif 6879fcf5ef2aSThomas Huth 6880fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6881fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6882fcf5ef2aSThomas Huth 68831a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 68841a404c91SMark Cave-Ayland { 6885e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 68861a404c91SMark Cave-Ayland } 68871a404c91SMark Cave-Ayland 68881a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 68891a404c91SMark Cave-Ayland { 6890e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 68911a404c91SMark Cave-Ayland } 68921a404c91SMark Cave-Ayland 6893c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6894c4a18dbfSMark Cave-Ayland { 689537da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6896c4a18dbfSMark Cave-Ayland } 6897c4a18dbfSMark Cave-Ayland 6898c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6899c4a18dbfSMark Cave-Ayland { 690037da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6901c4a18dbfSMark Cave-Ayland } 6902c4a18dbfSMark Cave-Ayland 6903139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6904fcf5ef2aSThomas Huth 6905139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6906fcf5ef2aSThomas Huth 6907139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6908fcf5ef2aSThomas Huth 6909139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6910fcf5ef2aSThomas Huth 6911139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6912fcf5ef2aSThomas Huth 69135cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 69145cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 69155cb091a4SNikunj A Dadhania { 69165cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 69175cb091a4SNikunj A Dadhania case 0: /* lfdp */ 69185cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 69195cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 69205cb091a4SNikunj A Dadhania } 69215cb091a4SNikunj A Dadhania break; 69225cb091a4SNikunj A Dadhania case 2: /* lxsd */ 69235cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 69245cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 69255cb091a4SNikunj A Dadhania } 69265cb091a4SNikunj A Dadhania break; 69275cb091a4SNikunj A Dadhania case 3: /* lxssp */ 69285cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 69295cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 69305cb091a4SNikunj A Dadhania } 69315cb091a4SNikunj A Dadhania break; 69325cb091a4SNikunj A Dadhania } 69335cb091a4SNikunj A Dadhania return gen_invalid(ctx); 69345cb091a4SNikunj A Dadhania } 69355cb091a4SNikunj A Dadhania 6936d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6937e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6938e3001664SNikunj A Dadhania { 6939e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6940e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6941e3001664SNikunj A Dadhania case 1: /* lxv */ 6942d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6943d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6944d59ba583SNikunj A Dadhania } 6945e3001664SNikunj A Dadhania break; 6946e3001664SNikunj A Dadhania case 5: /* stxv */ 6947d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6948d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6949d59ba583SNikunj A Dadhania } 6950e3001664SNikunj A Dadhania break; 6951e3001664SNikunj A Dadhania } 6952e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6953e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6954e3001664SNikunj A Dadhania case 0: /* stfdp */ 6955e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6956e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6957e3001664SNikunj A Dadhania } 6958e3001664SNikunj A Dadhania break; 6959e3001664SNikunj A Dadhania case 2: /* stxsd */ 6960e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6961e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6962e3001664SNikunj A Dadhania } 6963e3001664SNikunj A Dadhania break; 6964e3001664SNikunj A Dadhania case 3: /* stxssp */ 6965e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6966e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6967e3001664SNikunj A Dadhania } 6968e3001664SNikunj A Dadhania break; 6969e3001664SNikunj A Dadhania } 6970e3001664SNikunj A Dadhania } 6971e3001664SNikunj A Dadhania return gen_invalid(ctx); 6972e3001664SNikunj A Dadhania } 6973e3001664SNikunj A Dadhania 69749d69cfa2SLijun Pan #if defined(TARGET_PPC64) 69759d69cfa2SLijun Pan /* brd */ 69769d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 69779d69cfa2SLijun Pan { 69789d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 69799d69cfa2SLijun Pan } 69809d69cfa2SLijun Pan 69819d69cfa2SLijun Pan /* brw */ 69829d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 69839d69cfa2SLijun Pan { 69849d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 69859d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 69869d69cfa2SLijun Pan 69879d69cfa2SLijun Pan } 69889d69cfa2SLijun Pan 69899d69cfa2SLijun Pan /* brh */ 69909d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 69919d69cfa2SLijun Pan { 69929d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 69939d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 69949d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 69959d69cfa2SLijun Pan 69969d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 69979d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 69989d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 69999d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 70009d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 70019d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 70029d69cfa2SLijun Pan 70039d69cfa2SLijun Pan tcg_temp_free_i64(t0); 70049d69cfa2SLijun Pan tcg_temp_free_i64(t1); 70059d69cfa2SLijun Pan tcg_temp_free_i64(t2); 70069d69cfa2SLijun Pan } 70079d69cfa2SLijun Pan #endif 70089d69cfa2SLijun Pan 7009fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 70109d69cfa2SLijun Pan #if defined(TARGET_PPC64) 70119d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 70129d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 70139d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 70149d69cfa2SLijun Pan #endif 7015fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7016fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7017fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7018fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7019fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7020fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7021fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7022fcf5ef2aSThomas Huth #endif 7023fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7024fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7025fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7026fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7027fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7028fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7029fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7030fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 7031fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7032fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7033fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7034fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7035fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7036fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7037fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7038fcf5ef2aSThomas Huth #endif 7039fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7040fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7041fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7042fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7043fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7044fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7045fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 704680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7047b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 704880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7049fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7050fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7051fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7052fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7053fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7054fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7055fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7056fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7057fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7058fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7059fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7060fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7061fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7062fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7063fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7064fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7065fcf5ef2aSThomas Huth #endif 7066fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7067fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7068fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7069fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7070fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7071fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7072fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7073fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7074fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7075fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7076fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7077fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7078fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7079fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7080fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7081fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7082fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7083fcf5ef2aSThomas Huth #endif 7084fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7085fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 7086fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 7087fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 7088fcf5ef2aSThomas Huth #endif 70895cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 70905cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7091d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 7092e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7093fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7094fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7095fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7096fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7097fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7098fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7099c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7100fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7101fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7102fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7103fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7104a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7105a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7106fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7107fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7108fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7109fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7110a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7111a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7112fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7113fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7114fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7115fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7116fcf5ef2aSThomas Huth #endif 7117fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7118fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7119c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7120fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7121fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7122fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7123fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7124fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7125fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7126fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7127fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7128fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 71293c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 71303c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 71313c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 71323c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 71333c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 71343c89b8d6SNicholas Piggin #endif 7135cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7136fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7137fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7138fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7139fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7140fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7141fcf5ef2aSThomas Huth #endif 71423c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 71433c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 71443c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7145fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7146fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7147fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7148fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7149fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7150fcf5ef2aSThomas Huth #endif 7151fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7152fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7153fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7154fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7155fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7156fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7157fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7158fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7159fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7160b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7161fcf5ef2aSThomas Huth #endif 7162fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7163fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7164fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 716550728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7166fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7167fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 716850728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7169fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 717050728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7171fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 717250728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7173fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7174fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 717550728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7176fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 717799d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7178fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7179fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 718050728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7181fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7182fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7183fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7184fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7185fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7186fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7187fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7188fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7189fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7190fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7191fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7192fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7193fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7194fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7195fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7196fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7197fcf5ef2aSThomas Huth #endif 7198fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7199efe843d8SDavid Gibson /* 7200efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7201efe843d8SDavid Gibson * different ISA versions 7202efe843d8SDavid Gibson */ 7203fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7204fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7205c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7206c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7207fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7208fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7209fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7210fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7211a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 721262d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7213fcf5ef2aSThomas Huth #endif 7214fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7215fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7216fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7217fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7218fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7219fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7220fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7221fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7222fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7223fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7224fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7225fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7226fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7227fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7228fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7229fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7230fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7231fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7232fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7233fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7234fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7235fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7236fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7237fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7238fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7239fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7240fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7241fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7242fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7243fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7244fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7245fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7246fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7247fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7248fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7249fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7250fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7251fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7252fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7253fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7254fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7255fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 7256fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 7257fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7258fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7259fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7260fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7261fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7262fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7263fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7264fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7265fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7266fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7267fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7268fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7269fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7270fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7271fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7272fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7273fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7274fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7275fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7276fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7277fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7278fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7279fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7280fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7281fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7282fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7283fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7284fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7285fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7286fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7287fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7288fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7289fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7290fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7291fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7292fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7293fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7294fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7295fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7296fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7297fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7298fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7299fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7300fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7301fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7302fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7303fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7304fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7305fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7306fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7307fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 73087af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 73097af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7310fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7311fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7312fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7313fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7314fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 731527a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7316fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7317fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 73180c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 73190c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7320fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7321fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7322fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7323fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7324fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7325fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7326fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7327fcf5ef2aSThomas Huth PPC2_ISA300), 7328fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 73295ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 73305ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 73315ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 73325ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 7333fcf5ef2aSThomas Huth #endif 7334fcf5ef2aSThomas Huth 7335fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7336fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7337fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7338fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7339fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7340fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7341fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7342fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7343fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7344fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7345fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7346fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7347fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7348fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7349fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 73504c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7351fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7352fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7353fcf5ef2aSThomas Huth 7354fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7355fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7356fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7357fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7358fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7359fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7360fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7361fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7362fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7363fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7364fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7365fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7366fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7367fcf5ef2aSThomas Huth 7368fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7369fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7370fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7371fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7372fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7373fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7374fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7375fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7376fcf5ef2aSThomas Huth 7377fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7378fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7379fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7380fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7381fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7382fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7383fcf5ef2aSThomas Huth 7384fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7385fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7386fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7387fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7388fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7389fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7390fcf5ef2aSThomas Huth #endif 7391fcf5ef2aSThomas Huth 7392fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7393fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7394fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7395fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7396fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7397fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7398fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7399fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7400fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7401fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7402fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7403fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7404fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7405fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7406fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7407fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7408fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7409fcf5ef2aSThomas Huth 7410fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7411fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7412fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7413fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7414fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7415fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7416fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7417fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7418fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7419fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7420fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7421fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7422fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7423fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7424fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7425fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7426fcf5ef2aSThomas Huth #endif 7427fcf5ef2aSThomas Huth 7428fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7429fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7430fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7431fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7432fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7433fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7434fcf5ef2aSThomas Huth PPC_64B) 7435fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7436fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7437fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7438fcf5ef2aSThomas Huth PPC_64B), \ 7439fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7440fcf5ef2aSThomas Huth PPC_64B), \ 7441fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7442fcf5ef2aSThomas Huth PPC_64B) 7443fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7444fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7445fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7446fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7447fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7448fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7449fcf5ef2aSThomas Huth #endif 7450fcf5ef2aSThomas Huth 7451fcf5ef2aSThomas Huth #undef GEN_LD 7452fcf5ef2aSThomas Huth #undef GEN_LDU 7453fcf5ef2aSThomas Huth #undef GEN_LDUX 7454fcf5ef2aSThomas Huth #undef GEN_LDX_E 7455fcf5ef2aSThomas Huth #undef GEN_LDS 7456fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 7457fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7458fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 7459fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7460fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7461fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7462fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7463fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7464fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 7465fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 7466fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 7467fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7468fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7469fcf5ef2aSThomas Huth 7470fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7471fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7472fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7473fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7474fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7475fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7476fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7477fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7478fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7479fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7480fcf5ef2aSThomas Huth 7481fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7482fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7483fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7484fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7485fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7486fcf5ef2aSThomas Huth #endif 7487fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7488fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7489fcf5ef2aSThomas Huth 749050728199SRoman Kapl /* External PID based load */ 749150728199SRoman Kapl #undef GEN_LDEPX 749250728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 749350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 749450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 749550728199SRoman Kapl 749650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 749750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 749850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 749950728199SRoman Kapl #if defined(TARGET_PPC64) 750050728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 750150728199SRoman Kapl #endif 750250728199SRoman Kapl 7503fcf5ef2aSThomas Huth #undef GEN_ST 7504fcf5ef2aSThomas Huth #undef GEN_STU 7505fcf5ef2aSThomas Huth #undef GEN_STUX 7506fcf5ef2aSThomas Huth #undef GEN_STX_E 7507fcf5ef2aSThomas Huth #undef GEN_STS 7508fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 7509fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7510fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 7511fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7512fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 7513fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7514fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 75150123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7516fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 7517fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 7518fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 7519fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7520fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 7521fcf5ef2aSThomas Huth 7522fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7523fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7524fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7525fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7526fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7527fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7528fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7529fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7530fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7531fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7532fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7533fcf5ef2aSThomas Huth #endif 7534fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7535fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7536fcf5ef2aSThomas Huth 753750728199SRoman Kapl #undef GEN_STEPX 753850728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 753950728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 754050728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 754150728199SRoman Kapl 754250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 754350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 754450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 754550728199SRoman Kapl #if defined(TARGET_PPC64) 754650728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 754750728199SRoman Kapl #endif 754850728199SRoman Kapl 7549fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7550fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7551fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7552fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7553fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7554fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7555fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7556fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7557fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7558fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7559fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7560fcf5ef2aSThomas Huth 7561fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7562fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7563fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7583fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7584fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7585fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7586fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7587fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7588fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7589fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7590fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7591fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7592fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7593fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7594fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7595fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7596fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7597fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7598fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7599fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7600fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7601fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7602fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7603fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7604fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7605fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7606fcf5ef2aSThomas Huth 7607fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7608fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7609fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7610fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7611fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7612fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7613fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7614fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7615fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7616fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7617fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7618fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7619fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7620fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7621fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7622fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7623fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7624fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7625fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7626fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7627fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7628fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7629fcf5ef2aSThomas Huth 7630139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 7631fcf5ef2aSThomas Huth 7632139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 7633fcf5ef2aSThomas Huth 7634139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 7635fcf5ef2aSThomas Huth 7636139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 7637fcf5ef2aSThomas Huth 7638139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 7639fcf5ef2aSThomas Huth }; 7640fcf5ef2aSThomas Huth 7641fcf5ef2aSThomas Huth #include "helper_regs.h" 7642139c1837SPaolo Bonzini #include "translate_init.c.inc" 7643fcf5ef2aSThomas Huth 7644fcf5ef2aSThomas Huth /*****************************************************************************/ 7645fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 764690c84c56SMarkus Armbruster void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7647fcf5ef2aSThomas Huth { 7648fcf5ef2aSThomas Huth #define RGPL 4 7649fcf5ef2aSThomas Huth #define RFPL 4 7650fcf5ef2aSThomas Huth 7651fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7652fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 7653fcf5ef2aSThomas Huth int i; 7654fcf5ef2aSThomas Huth 765590c84c56SMarkus Armbruster qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7656fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7657fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 7658fcf5ef2aSThomas Huth cs->cpu_index); 765990c84c56SMarkus Armbruster qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7660fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 7661fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 7662fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 7663fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 766490c84c56SMarkus Armbruster qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7665fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7666a8dafa52SSuraj Jitindar Singh " DECR " TARGET_FMT_lu 7667fcf5ef2aSThomas Huth #endif 7668fcf5ef2aSThomas Huth "\n", 7669fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7670fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7671fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 7672fcf5ef2aSThomas Huth #endif 7673fcf5ef2aSThomas Huth ); 7674fcf5ef2aSThomas Huth #endif 7675fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7676efe843d8SDavid Gibson if ((i & (RGPL - 1)) == 0) { 767790c84c56SMarkus Armbruster qemu_fprintf(f, "GPR%02d", i); 7678efe843d8SDavid Gibson } 767990c84c56SMarkus Armbruster qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7680efe843d8SDavid Gibson if ((i & (RGPL - 1)) == (RGPL - 1)) { 768190c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 7682fcf5ef2aSThomas Huth } 7683efe843d8SDavid Gibson } 768490c84c56SMarkus Armbruster qemu_fprintf(f, "CR "); 7685fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 768690c84c56SMarkus Armbruster qemu_fprintf(f, "%01x", env->crf[i]); 768790c84c56SMarkus Armbruster qemu_fprintf(f, " ["); 7688fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 7689fcf5ef2aSThomas Huth char a = '-'; 7690efe843d8SDavid Gibson if (env->crf[i] & 0x08) { 7691fcf5ef2aSThomas Huth a = 'L'; 7692efe843d8SDavid Gibson } else if (env->crf[i] & 0x04) { 7693fcf5ef2aSThomas Huth a = 'G'; 7694efe843d8SDavid Gibson } else if (env->crf[i] & 0x02) { 7695fcf5ef2aSThomas Huth a = 'E'; 7696efe843d8SDavid Gibson } 769790c84c56SMarkus Armbruster qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7698fcf5ef2aSThomas Huth } 769990c84c56SMarkus Armbruster qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7700fcf5ef2aSThomas Huth env->reserve_addr); 7701685f1ce2SRichard Henderson 7702685f1ce2SRichard Henderson if (flags & CPU_DUMP_FPU) { 7703fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7704685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == 0) { 770590c84c56SMarkus Armbruster qemu_fprintf(f, "FPR%02d", i); 7706685f1ce2SRichard Henderson } 770790c84c56SMarkus Armbruster qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7708685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == (RFPL - 1)) { 770990c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 7710fcf5ef2aSThomas Huth } 7711685f1ce2SRichard Henderson } 771290c84c56SMarkus Armbruster qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7713685f1ce2SRichard Henderson } 7714685f1ce2SRichard Henderson 7715fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 771690c84c56SMarkus Armbruster qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7717fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7718fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7719fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7720fcf5ef2aSThomas Huth 772190c84c56SMarkus Armbruster qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7722fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7723fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7724fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7725fcf5ef2aSThomas Huth 772690c84c56SMarkus Armbruster qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7727fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7728fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7729fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7730fcf5ef2aSThomas Huth 7731fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7732fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7733a790e82bSBenjamin Herrenschmidt env->excp_model == POWERPC_EXCP_POWER8 || 7734a790e82bSBenjamin Herrenschmidt env->excp_model == POWERPC_EXCP_POWER9) { 773590c84c56SMarkus Armbruster qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7736fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7737fcf5ef2aSThomas Huth } 7738fcf5ef2aSThomas Huth #endif 7739fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 774090c84c56SMarkus Armbruster qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7741fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7742fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7743fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7744fcf5ef2aSThomas Huth 774590c84c56SMarkus Armbruster qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7746fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7747fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7748fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7749fcf5ef2aSThomas Huth 775090c84c56SMarkus Armbruster qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7751fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7752fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7753fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7754fcf5ef2aSThomas Huth 775590c84c56SMarkus Armbruster qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7756fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7757fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7758fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7759fcf5ef2aSThomas Huth 7760fcf5ef2aSThomas Huth /* FSL-specific */ 776190c84c56SMarkus Armbruster qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7762fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7763fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7764fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7765fcf5ef2aSThomas Huth 7766fcf5ef2aSThomas Huth /* 7767fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7768fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7769fcf5ef2aSThomas Huth */ 7770fcf5ef2aSThomas Huth } 7771fcf5ef2aSThomas Huth 7772fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7773fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 777490c84c56SMarkus Armbruster qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7775fcf5ef2aSThomas Huth } 7776fcf5ef2aSThomas Huth #endif 7777fcf5ef2aSThomas Huth 7778efe843d8SDavid Gibson if (env->spr_cb[SPR_LPCR].name) { 777990c84c56SMarkus Armbruster qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7780efe843d8SDavid Gibson } 7781d801a61eSSuraj Jitindar Singh 77820941d728SDavid Gibson switch (env->mmu_model) { 7783fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7784fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7785fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7786fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7787fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 77880941d728SDavid Gibson case POWERPC_MMU_64B: 77890941d728SDavid Gibson case POWERPC_MMU_2_03: 77900941d728SDavid Gibson case POWERPC_MMU_2_06: 77910941d728SDavid Gibson case POWERPC_MMU_2_07: 77920941d728SDavid Gibson case POWERPC_MMU_3_00: 7793fcf5ef2aSThomas Huth #endif 77944f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 779590c84c56SMarkus Armbruster qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 77964f4f28ffSSuraj Jitindar Singh } 77974a7518e0SCédric Le Goater if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 779890c84c56SMarkus Armbruster qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 77994a7518e0SCédric Le Goater } 780090c84c56SMarkus Armbruster qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7801fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7802fcf5ef2aSThomas Huth break; 7803fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 780490c84c56SMarkus Armbruster qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7805fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7806fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7807fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7808fcf5ef2aSThomas Huth 780990c84c56SMarkus Armbruster qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7810fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7811fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7812fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7813fcf5ef2aSThomas Huth 781490c84c56SMarkus Armbruster qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7815fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7816fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7817fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7818fcf5ef2aSThomas Huth break; 7819fcf5ef2aSThomas Huth default: 7820fcf5ef2aSThomas Huth break; 7821fcf5ef2aSThomas Huth } 7822fcf5ef2aSThomas Huth #endif 7823fcf5ef2aSThomas Huth 7824fcf5ef2aSThomas Huth #undef RGPL 7825fcf5ef2aSThomas Huth #undef RFPL 7826fcf5ef2aSThomas Huth } 7827fcf5ef2aSThomas Huth 782811cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 7829fcf5ef2aSThomas Huth { 7830fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7831fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7832fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7833fcf5ef2aSThomas Huth int op1, op2, op3; 7834fcf5ef2aSThomas Huth 7835fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7836fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7837fcf5ef2aSThomas Huth handler = t1[op1]; 7838fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7839fcf5ef2aSThomas Huth t2 = ind_table(handler); 7840fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7841fcf5ef2aSThomas Huth handler = t2[op2]; 7842fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7843fcf5ef2aSThomas Huth t3 = ind_table(handler); 7844fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7845fcf5ef2aSThomas Huth handler = t3[op3]; 7846efe843d8SDavid Gibson if (handler->count == 0) { 7847fcf5ef2aSThomas Huth continue; 7848efe843d8SDavid Gibson } 784911cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 7850fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7851fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7852fcf5ef2aSThomas Huth handler->oname, 7853fcf5ef2aSThomas Huth handler->count, handler->count); 7854fcf5ef2aSThomas Huth } 7855fcf5ef2aSThomas Huth } else { 7856efe843d8SDavid Gibson if (handler->count == 0) { 7857fcf5ef2aSThomas Huth continue; 7858efe843d8SDavid Gibson } 785911cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 7860fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7861fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7862fcf5ef2aSThomas Huth handler->count, handler->count); 7863fcf5ef2aSThomas Huth } 7864fcf5ef2aSThomas Huth } 7865fcf5ef2aSThomas Huth } else { 7866efe843d8SDavid Gibson if (handler->count == 0) { 7867fcf5ef2aSThomas Huth continue; 7868efe843d8SDavid Gibson } 786911cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 7870fcf5ef2aSThomas Huth " %" PRId64 "\n", 7871fcf5ef2aSThomas Huth op1, op1, handler->oname, 7872fcf5ef2aSThomas Huth handler->count, handler->count); 7873fcf5ef2aSThomas Huth } 7874fcf5ef2aSThomas Huth } 7875fcf5ef2aSThomas Huth #endif 7876fcf5ef2aSThomas Huth } 7877fcf5ef2aSThomas Huth 7878b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7879fcf5ef2aSThomas Huth { 7880b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 78819c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 7882*2df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7883b0c2d521SEmilio G. Cota int bound; 7884fcf5ef2aSThomas Huth 7885b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 7886b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 7887*2df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7888b0c2d521SEmilio G. Cota ctx->mem_idx = env->dmmu_idx; 7889*2df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 7890*2df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7891b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7892b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7893b0c2d521SEmilio G. Cota ctx->access_type = -1; 7894d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 7895*2df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7896b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 78970e3bf489SRoman Kapl ctx->flags = env->flags; 7898fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7899*2df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7900b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7901fcf5ef2aSThomas Huth #endif 7902e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7903e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 7904d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7905fcf5ef2aSThomas Huth 7906*2df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 7907*2df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 7908*2df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 7909*2df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 79103c89b8d6SNicholas Piggin if ((env->flags & POWERPC_FLAG_SCV) 79113c89b8d6SNicholas Piggin && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { 79123c89b8d6SNicholas Piggin ctx->scv_enabled = true; 79133c89b8d6SNicholas Piggin } else { 79143c89b8d6SNicholas Piggin ctx->scv_enabled = false; 79153c89b8d6SNicholas Piggin } 7916*2df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7917b0c2d521SEmilio G. Cota ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7918*2df4fe7aSRichard Henderson 7919b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 7920*2df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 7921*2df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7922efe843d8SDavid Gibson } 7923*2df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7924b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7925efe843d8SDavid Gibson } 79260e3bf489SRoman Kapl if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 79270e3bf489SRoman Kapl ctx->singlestep_enabled = 0; 79280e3bf489SRoman Kapl target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 79290e3bf489SRoman Kapl if (dbcr0 & DBCR0_ICMP) { 79300e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_SINGLE_STEP; 79310e3bf489SRoman Kapl } 79320e3bf489SRoman Kapl if (dbcr0 & DBCR0_BRT) { 79330e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_BRANCH_STEP; 79340e3bf489SRoman Kapl } 79350e3bf489SRoman Kapl 79360e3bf489SRoman Kapl } 7937b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7938b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7939fcf5ef2aSThomas Huth } 7940b0c2d521SEmilio G. Cota 7941b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7942b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7943fcf5ef2aSThomas Huth } 7944fcf5ef2aSThomas Huth 7945b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7946b0c2d521SEmilio G. Cota { 7947b0c2d521SEmilio G. Cota } 7948fcf5ef2aSThomas Huth 7949b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7950b0c2d521SEmilio G. Cota { 7951b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7952b0c2d521SEmilio G. Cota } 7953b0c2d521SEmilio G. Cota 7954b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7955b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 7956b0c2d521SEmilio G. Cota { 7957b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7958b0c2d521SEmilio G. Cota 7959b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 79602a8ceefcSEmilio G. Cota dcbase->is_jmp = DISAS_NORETURN; 7961efe843d8SDavid Gibson /* 7962efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 7963efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 7964efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 7965efe843d8SDavid Gibson * setting tb->size below does the right thing. 7966efe843d8SDavid Gibson */ 7967b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7968b0c2d521SEmilio G. Cota return true; 7969fcf5ef2aSThomas Huth } 7970fcf5ef2aSThomas Huth 7971b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7972b0c2d521SEmilio G. Cota { 7973b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 797428876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7975b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 7976b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 7977b0c2d521SEmilio G. Cota 7978fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7979fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7980b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7981b0c2d521SEmilio G. Cota 798223f42b60SEmilio G. Cota ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, 798323f42b60SEmilio G. Cota need_byteswap(ctx)); 798423f42b60SEmilio G. Cota 7985fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7986b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7987b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7988b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 7989b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 799028876bf2SAlex Bennée table = cpu->opcodes; 7991b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 7992fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7993fcf5ef2aSThomas Huth table = ind_table(handler); 7994b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 7995fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7996fcf5ef2aSThomas Huth table = ind_table(handler); 7997b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 7998fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7999fcf5ef2aSThomas Huth table = ind_table(handler); 8000b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 8001fcf5ef2aSThomas Huth } 8002fcf5ef2aSThomas Huth } 8003fcf5ef2aSThomas Huth } 8004fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 8005fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 8006fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8007fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 8008fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 8009b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 8010b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 8011b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 8012fcf5ef2aSThomas Huth } else { 8013fcf5ef2aSThomas Huth uint32_t inval; 8014fcf5ef2aSThomas Huth 8015b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8016b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 8017fcf5ef2aSThomas Huth inval = handler->inval2; 8018fcf5ef2aSThomas Huth } else { 8019fcf5ef2aSThomas Huth inval = handler->inval1; 8020fcf5ef2aSThomas Huth } 8021fcf5ef2aSThomas Huth 8022b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 8023fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8024fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 8025b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 8026b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 8027b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 8028b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4); 8029b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 8030b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 8031b0c2d521SEmilio G. Cota return; 8032fcf5ef2aSThomas Huth } 8033fcf5ef2aSThomas Huth } 8034b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 8035fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 8036fcf5ef2aSThomas Huth handler->count++; 8037fcf5ef2aSThomas Huth #endif 8038fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 8039b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 8040b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 8041b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 8042b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 8043b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 8044e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 80450e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 8046fcf5ef2aSThomas Huth } 8047b0c2d521SEmilio G. Cota 8048fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 8049b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 8050b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 8051b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 8052fcf5ef2aSThomas Huth } 8053b0c2d521SEmilio G. Cota 8054b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 8055b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 8056fcf5ef2aSThomas Huth } 8057b0c2d521SEmilio G. Cota 8058b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8059b0c2d521SEmilio G. Cota { 8060b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8061b0c2d521SEmilio G. Cota 8062b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 8063b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 8064b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 8065b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 8066b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 8067fcf5ef2aSThomas Huth } 8068fcf5ef2aSThomas Huth /* Generate the return instruction */ 806907ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8070fcf5ef2aSThomas Huth } 8071fcf5ef2aSThomas Huth } 8072b0c2d521SEmilio G. Cota 8073b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8074b0c2d521SEmilio G. Cota { 8075b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8076b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8077b0c2d521SEmilio G. Cota } 8078b0c2d521SEmilio G. Cota 8079b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8080b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8081b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8082b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8083b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 8084b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8085b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8086b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8087b0c2d521SEmilio G. Cota }; 8088b0c2d521SEmilio G. Cota 80898b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8090b0c2d521SEmilio G. Cota { 8091b0c2d521SEmilio G. Cota DisasContext ctx; 8092b0c2d521SEmilio G. Cota 80938b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8094fcf5ef2aSThomas Huth } 8095fcf5ef2aSThomas Huth 8096fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8097fcf5ef2aSThomas Huth target_ulong *data) 8098fcf5ef2aSThomas Huth { 8099fcf5ef2aSThomas Huth env->nip = data[0]; 8100fcf5ef2aSThomas Huth } 8101