1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char *p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 125fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 131fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 133fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 135fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 137dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 139dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 143fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 144fcf5ef2aSThomas Huth "reserve_addr"); 145253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 146253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 147253ce7b2SNikunj A Dadhania "reserve_val"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 150fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 153efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 154efe843d8SDavid Gibson "access_type"); 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth /* internal defines */ 158fcf5ef2aSThomas Huth struct DisasContext { 159b6bac4bcSEmilio G. Cota DisasContextBase base; 160*2c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 161fcf5ef2aSThomas Huth uint32_t opcode; 162fcf5ef2aSThomas Huth uint32_t exception; 163fcf5ef2aSThomas Huth /* Routine used to access memory */ 164fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 165fcf5ef2aSThomas Huth bool lazy_tlb_flush; 166fcf5ef2aSThomas Huth bool need_access_type; 167fcf5ef2aSThomas Huth int mem_idx; 168fcf5ef2aSThomas Huth int access_type; 169fcf5ef2aSThomas Huth /* Translation flags */ 17014776ab5STony Nguyen MemOp default_tcg_memop_mask; 171fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 172fcf5ef2aSThomas Huth bool sf_mode; 173fcf5ef2aSThomas Huth bool has_cfar; 174fcf5ef2aSThomas Huth #endif 175fcf5ef2aSThomas Huth bool fpu_enabled; 176fcf5ef2aSThomas Huth bool altivec_enabled; 177fcf5ef2aSThomas Huth bool vsx_enabled; 178fcf5ef2aSThomas Huth bool spe_enabled; 179fcf5ef2aSThomas Huth bool tm_enabled; 180c6fd28fdSSuraj Jitindar Singh bool gtse; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 189fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 190fcf5ef2aSThomas Huth { 191fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 192fcf5ef2aSThomas Huth return ctx->le_mode; 193fcf5ef2aSThomas Huth #else 194fcf5ef2aSThomas Huth return !ctx->le_mode; 195fcf5ef2aSThomas Huth #endif 196fcf5ef2aSThomas Huth } 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 199fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 200fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 201fcf5ef2aSThomas Huth #else 202fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 203fcf5ef2aSThomas Huth #endif 204fcf5ef2aSThomas Huth 205fcf5ef2aSThomas Huth struct opc_handler_t { 206fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 207fcf5ef2aSThomas Huth uint32_t inval1; 208fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 209fcf5ef2aSThomas Huth uint32_t inval2; 210fcf5ef2aSThomas Huth /* instruction type */ 211fcf5ef2aSThomas Huth uint64_t type; 212fcf5ef2aSThomas Huth /* extended instruction type */ 213fcf5ef2aSThomas Huth uint64_t type2; 214fcf5ef2aSThomas Huth /* handler */ 215fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 216fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 217fcf5ef2aSThomas Huth const char *oname; 218fcf5ef2aSThomas Huth #endif 219fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 220fcf5ef2aSThomas Huth uint64_t count; 221fcf5ef2aSThomas Huth #endif 222fcf5ef2aSThomas Huth }; 223fcf5ef2aSThomas Huth 2240e3bf489SRoman Kapl /* SPR load/store helpers */ 2250e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2260e3bf489SRoman Kapl { 2270e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2280e3bf489SRoman Kapl } 2290e3bf489SRoman Kapl 2300e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2310e3bf489SRoman Kapl { 2320e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2330e3bf489SRoman Kapl } 2340e3bf489SRoman Kapl 235fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 236fcf5ef2aSThomas Huth { 237fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 238fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 239fcf5ef2aSThomas Huth ctx->access_type = access_type; 240fcf5ef2aSThomas Huth } 241fcf5ef2aSThomas Huth } 242fcf5ef2aSThomas Huth 243fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 244fcf5ef2aSThomas Huth { 245fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 246fcf5ef2aSThomas Huth nip = (uint32_t)nip; 247fcf5ef2aSThomas Huth } 248fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 249fcf5ef2aSThomas Huth } 250fcf5ef2aSThomas Huth 251fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 252fcf5ef2aSThomas Huth { 253fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 254fcf5ef2aSThomas Huth 255efe843d8SDavid Gibson /* 256efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 257efe843d8SDavid Gibson * faulting instruction 258fcf5ef2aSThomas Huth */ 259fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 260*2c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 261fcf5ef2aSThomas Huth } 262fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 263fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 264fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 265fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 266fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 267fcf5ef2aSThomas Huth ctx->exception = (excp); 268fcf5ef2aSThomas Huth } 269fcf5ef2aSThomas Huth 270fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 271fcf5ef2aSThomas Huth { 272fcf5ef2aSThomas Huth TCGv_i32 t0; 273fcf5ef2aSThomas Huth 274efe843d8SDavid Gibson /* 275efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 276efe843d8SDavid Gibson * faulting instruction 277fcf5ef2aSThomas Huth */ 278fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 279*2c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 282fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 283fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 284fcf5ef2aSThomas Huth ctx->exception = (excp); 285fcf5ef2aSThomas Huth } 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 288fcf5ef2aSThomas Huth target_ulong nip) 289fcf5ef2aSThomas Huth { 290fcf5ef2aSThomas Huth TCGv_i32 t0; 291fcf5ef2aSThomas Huth 292fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 293fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 294fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 295fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 296fcf5ef2aSThomas Huth ctx->exception = (excp); 297fcf5ef2aSThomas Huth } 298fcf5ef2aSThomas Huth 299e150ac89SRoman Kapl /* 300e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 301e150ac89SRoman Kapl * SPR registers for this exception. 302e150ac89SRoman Kapl * 303e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 304e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3050e3bf489SRoman Kapl */ 306e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3070e3bf489SRoman Kapl { 3080e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3090e3bf489SRoman Kapl target_ulong dbsr = 0; 310e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3110e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 312e150ac89SRoman Kapl } else { 313e150ac89SRoman Kapl /* Must have been branch */ 3140e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3150e3bf489SRoman Kapl } 3160e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3170e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3180e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3190e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3200e3bf489SRoman Kapl tcg_temp_free(t0); 3210e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3220e3bf489SRoman Kapl } else { 323e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3240e3bf489SRoman Kapl } 3250e3bf489SRoman Kapl } 3260e3bf489SRoman Kapl 327fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 328fcf5ef2aSThomas Huth { 329fcf5ef2aSThomas Huth TCGv_i32 t0; 330fcf5ef2aSThomas Huth 331efe843d8SDavid Gibson /* 332efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 333efe843d8SDavid Gibson * faulting instruction 334fcf5ef2aSThomas Huth */ 335fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 336fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 337b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 338fcf5ef2aSThomas Huth } 339fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 340fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 341fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 342fcf5ef2aSThomas Huth } 343fcf5ef2aSThomas Huth 344fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 345fcf5ef2aSThomas Huth { 346fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 347fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 348fcf5ef2aSThomas Huth } 349fcf5ef2aSThomas Huth 350fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 351fcf5ef2aSThomas Huth { 352fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 353fcf5ef2aSThomas Huth } 354fcf5ef2aSThomas Huth 355fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 356fcf5ef2aSThomas Huth { 357fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 358fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 359fcf5ef2aSThomas Huth } 360fcf5ef2aSThomas Huth 361fcf5ef2aSThomas Huth /* Stop translation */ 362fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 363fcf5ef2aSThomas Huth { 364b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 365fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 366fcf5ef2aSThomas Huth } 367fcf5ef2aSThomas Huth 368fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 369fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 370fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 371fcf5ef2aSThomas Huth { 372fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 373fcf5ef2aSThomas Huth } 374fcf5ef2aSThomas Huth #endif 375fcf5ef2aSThomas Huth 37637f219c8SBruno Larsen (billionai) /*****************************************************************************/ 37737f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 37837f219c8SBruno Larsen (billionai) 379a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 38037f219c8SBruno Larsen (billionai) { 38137f219c8SBruno Larsen (billionai) #if 0 38237f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 38337f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 38437f219c8SBruno Larsen (billionai) #endif 38537f219c8SBruno Larsen (billionai) } 38637f219c8SBruno Larsen (billionai) 38737f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 38837f219c8SBruno Larsen (billionai) 38937f219c8SBruno Larsen (billionai) /* 39037f219c8SBruno Larsen (billionai) * Generic callbacks: 39137f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 39237f219c8SBruno Larsen (billionai) */ 39337f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 39437f219c8SBruno Larsen (billionai) { 39537f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39737f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 39837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39937f219c8SBruno Larsen (billionai) #endif 40037f219c8SBruno Larsen (billionai) } 40137f219c8SBruno Larsen (billionai) 402a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 40337f219c8SBruno Larsen (billionai) { 40437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 40537f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 40637f219c8SBruno Larsen (billionai) } 40737f219c8SBruno Larsen (billionai) 40837f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 40937f219c8SBruno Larsen (billionai) { 41037f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 41137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 41237f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 41337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 41437f219c8SBruno Larsen (billionai) #endif 41537f219c8SBruno Larsen (billionai) } 41637f219c8SBruno Larsen (billionai) 417a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 41837f219c8SBruno Larsen (billionai) { 41937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 42037f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42137f219c8SBruno Larsen (billionai) } 42237f219c8SBruno Larsen (billionai) 42337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 424a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 42537f219c8SBruno Larsen (billionai) { 42637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 42737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42837f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 42937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 43137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43237f219c8SBruno Larsen (billionai) #else 43337f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43437f219c8SBruno Larsen (billionai) #endif 43537f219c8SBruno Larsen (billionai) } 43637f219c8SBruno Larsen (billionai) 437a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 43837f219c8SBruno Larsen (billionai) { 43937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 44037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 44137f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 44237f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 44337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 44437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 44637f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 44737f219c8SBruno Larsen (billionai) } 44837f219c8SBruno Larsen (billionai) 449a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 45037f219c8SBruno Larsen (billionai) { 45137f219c8SBruno Larsen (billionai) } 45237f219c8SBruno Larsen (billionai) 45337f219c8SBruno Larsen (billionai) #endif 45437f219c8SBruno Larsen (billionai) 45537f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 45637f219c8SBruno Larsen (billionai) /* XER */ 457a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 45837f219c8SBruno Larsen (billionai) { 45937f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 46037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 46137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 46237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 46337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 46437f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 46537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 46637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 46737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 46837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 46937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47037f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 47137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 47237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 47437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47537f219c8SBruno Larsen (billionai) } 47637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 47737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 47837f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 47937f219c8SBruno Larsen (billionai) } 48037f219c8SBruno Larsen (billionai) 481a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 48237f219c8SBruno Larsen (billionai) { 48337f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 48437f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 48537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 48637f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 48737f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 48837f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 48937f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 49037f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 49137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 49237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 49337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 49437f219c8SBruno Larsen (billionai) } 49537f219c8SBruno Larsen (billionai) 49637f219c8SBruno Larsen (billionai) /* LR */ 497a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 49837f219c8SBruno Larsen (billionai) { 49937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 50037f219c8SBruno Larsen (billionai) } 50137f219c8SBruno Larsen (billionai) 502a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 50337f219c8SBruno Larsen (billionai) { 50437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 50537f219c8SBruno Larsen (billionai) } 50637f219c8SBruno Larsen (billionai) 50737f219c8SBruno Larsen (billionai) /* CFAR */ 50837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 509a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 51037f219c8SBruno Larsen (billionai) { 51137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 51237f219c8SBruno Larsen (billionai) } 51337f219c8SBruno Larsen (billionai) 514a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 51537f219c8SBruno Larsen (billionai) { 51637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 51737f219c8SBruno Larsen (billionai) } 51837f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 51937f219c8SBruno Larsen (billionai) 52037f219c8SBruno Larsen (billionai) /* CTR */ 521a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 52237f219c8SBruno Larsen (billionai) { 52337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 52437f219c8SBruno Larsen (billionai) } 52537f219c8SBruno Larsen (billionai) 526a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 52737f219c8SBruno Larsen (billionai) { 52837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 52937f219c8SBruno Larsen (billionai) } 53037f219c8SBruno Larsen (billionai) 53137f219c8SBruno Larsen (billionai) /* User read access to SPR */ 53237f219c8SBruno Larsen (billionai) /* USPRx */ 53337f219c8SBruno Larsen (billionai) /* UMMCRx */ 53437f219c8SBruno Larsen (billionai) /* UPMCx */ 53537f219c8SBruno Larsen (billionai) /* USIA */ 53637f219c8SBruno Larsen (billionai) /* UDECR */ 537a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 53837f219c8SBruno Larsen (billionai) { 53937f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 54037f219c8SBruno Larsen (billionai) } 54137f219c8SBruno Larsen (billionai) 54237f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 543a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 54437f219c8SBruno Larsen (billionai) { 54537f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 54637f219c8SBruno Larsen (billionai) } 54737f219c8SBruno Larsen (billionai) #endif 54837f219c8SBruno Larsen (billionai) 54937f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 55037f219c8SBruno Larsen (billionai) /* DECR */ 55137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 552a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 55337f219c8SBruno Larsen (billionai) { 55437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 55537f219c8SBruno Larsen (billionai) gen_io_start(); 55637f219c8SBruno Larsen (billionai) } 55737f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 55837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 55937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 56037f219c8SBruno Larsen (billionai) } 56137f219c8SBruno Larsen (billionai) } 56237f219c8SBruno Larsen (billionai) 563a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 56437f219c8SBruno Larsen (billionai) { 56537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 56637f219c8SBruno Larsen (billionai) gen_io_start(); 56737f219c8SBruno Larsen (billionai) } 56837f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 56937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 57037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 57137f219c8SBruno Larsen (billionai) } 57237f219c8SBruno Larsen (billionai) } 57337f219c8SBruno Larsen (billionai) #endif 57437f219c8SBruno Larsen (billionai) 57537f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 57637f219c8SBruno Larsen (billionai) /* Time base */ 577a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 57837f219c8SBruno Larsen (billionai) { 57937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 58037f219c8SBruno Larsen (billionai) gen_io_start(); 58137f219c8SBruno Larsen (billionai) } 58237f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 58337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 58437f219c8SBruno Larsen (billionai) gen_io_end(); 58537f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 58637f219c8SBruno Larsen (billionai) } 58737f219c8SBruno Larsen (billionai) } 58837f219c8SBruno Larsen (billionai) 589a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 59037f219c8SBruno Larsen (billionai) { 59137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 59237f219c8SBruno Larsen (billionai) gen_io_start(); 59337f219c8SBruno Larsen (billionai) } 59437f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 59537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 59637f219c8SBruno Larsen (billionai) gen_io_end(); 59737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 59837f219c8SBruno Larsen (billionai) } 59937f219c8SBruno Larsen (billionai) } 60037f219c8SBruno Larsen (billionai) 601a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 60237f219c8SBruno Larsen (billionai) { 60337f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 60437f219c8SBruno Larsen (billionai) } 60537f219c8SBruno Larsen (billionai) 606a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 60737f219c8SBruno Larsen (billionai) { 60837f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 60937f219c8SBruno Larsen (billionai) } 61037f219c8SBruno Larsen (billionai) 61137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 612a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 61337f219c8SBruno Larsen (billionai) { 61437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 61537f219c8SBruno Larsen (billionai) gen_io_start(); 61637f219c8SBruno Larsen (billionai) } 61737f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 61837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 61937f219c8SBruno Larsen (billionai) gen_io_end(); 62037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 62137f219c8SBruno Larsen (billionai) } 62237f219c8SBruno Larsen (billionai) } 62337f219c8SBruno Larsen (billionai) 624a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 62537f219c8SBruno Larsen (billionai) { 62637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 62737f219c8SBruno Larsen (billionai) gen_io_start(); 62837f219c8SBruno Larsen (billionai) } 62937f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 63037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 63137f219c8SBruno Larsen (billionai) gen_io_end(); 63237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 63337f219c8SBruno Larsen (billionai) } 63437f219c8SBruno Larsen (billionai) } 63537f219c8SBruno Larsen (billionai) 636a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 63737f219c8SBruno Larsen (billionai) { 63837f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 63937f219c8SBruno Larsen (billionai) } 64037f219c8SBruno Larsen (billionai) 641a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 64237f219c8SBruno Larsen (billionai) { 64337f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 64437f219c8SBruno Larsen (billionai) } 64537f219c8SBruno Larsen (billionai) 64637f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 647a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 64837f219c8SBruno Larsen (billionai) { 64937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 65037f219c8SBruno Larsen (billionai) gen_io_start(); 65137f219c8SBruno Larsen (billionai) } 65237f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 65337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 65437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) } 65737f219c8SBruno Larsen (billionai) 658a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 65937f219c8SBruno Larsen (billionai) { 66037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 66137f219c8SBruno Larsen (billionai) gen_io_start(); 66237f219c8SBruno Larsen (billionai) } 66337f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 66437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 66537f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 66637f219c8SBruno Larsen (billionai) } 66737f219c8SBruno Larsen (billionai) } 66837f219c8SBruno Larsen (billionai) 66937f219c8SBruno Larsen (billionai) /* HDECR */ 670a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 67137f219c8SBruno Larsen (billionai) { 67237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 67337f219c8SBruno Larsen (billionai) gen_io_start(); 67437f219c8SBruno Larsen (billionai) } 67537f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 67637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 67737f219c8SBruno Larsen (billionai) gen_io_end(); 67837f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 67937f219c8SBruno Larsen (billionai) } 68037f219c8SBruno Larsen (billionai) } 68137f219c8SBruno Larsen (billionai) 682a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 68337f219c8SBruno Larsen (billionai) { 68437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 68537f219c8SBruno Larsen (billionai) gen_io_start(); 68637f219c8SBruno Larsen (billionai) } 68737f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 68837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 68937f219c8SBruno Larsen (billionai) gen_io_end(); 69037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 69137f219c8SBruno Larsen (billionai) } 69237f219c8SBruno Larsen (billionai) } 69337f219c8SBruno Larsen (billionai) 694a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 69537f219c8SBruno Larsen (billionai) { 69637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 69737f219c8SBruno Larsen (billionai) gen_io_start(); 69837f219c8SBruno Larsen (billionai) } 69937f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 70037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 70137f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 70237f219c8SBruno Larsen (billionai) } 70337f219c8SBruno Larsen (billionai) } 70437f219c8SBruno Larsen (billionai) 705a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 70637f219c8SBruno Larsen (billionai) { 70737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 70837f219c8SBruno Larsen (billionai) gen_io_start(); 70937f219c8SBruno Larsen (billionai) } 71037f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 71137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 71237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) } 71537f219c8SBruno Larsen (billionai) 716a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 71737f219c8SBruno Larsen (billionai) { 71837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 71937f219c8SBruno Larsen (billionai) gen_io_start(); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 72237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 72337f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 72437f219c8SBruno Larsen (billionai) } 72537f219c8SBruno Larsen (billionai) } 72637f219c8SBruno Larsen (billionai) 72737f219c8SBruno Larsen (billionai) #endif 72837f219c8SBruno Larsen (billionai) #endif 72937f219c8SBruno Larsen (billionai) 73037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 73137f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 73237f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 733a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 73437f219c8SBruno Larsen (billionai) { 73537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 73637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 73737f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 73837f219c8SBruno Larsen (billionai) } 73937f219c8SBruno Larsen (billionai) 740a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 74137f219c8SBruno Larsen (billionai) { 74237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 74337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 74437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 74537f219c8SBruno Larsen (billionai) } 74637f219c8SBruno Larsen (billionai) 747a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 74837f219c8SBruno Larsen (billionai) { 74937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 75037f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 75137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75237f219c8SBruno Larsen (billionai) } 75337f219c8SBruno Larsen (billionai) 754a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 75537f219c8SBruno Larsen (billionai) { 75637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 75737f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 75837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75937f219c8SBruno Larsen (billionai) } 76037f219c8SBruno Larsen (billionai) 761a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 76237f219c8SBruno Larsen (billionai) { 76337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 76437f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 76537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 76637f219c8SBruno Larsen (billionai) } 76737f219c8SBruno Larsen (billionai) 768a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 76937f219c8SBruno Larsen (billionai) { 77037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 77137f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 77237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 77337f219c8SBruno Larsen (billionai) } 77437f219c8SBruno Larsen (billionai) 77537f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 77637f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 777a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 77837f219c8SBruno Larsen (billionai) { 77937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 78037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 78137f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 78237f219c8SBruno Larsen (billionai) } 78337f219c8SBruno Larsen (billionai) 784a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 78537f219c8SBruno Larsen (billionai) { 78637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 78737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 78837f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 78937f219c8SBruno Larsen (billionai) } 79037f219c8SBruno Larsen (billionai) 791a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 79237f219c8SBruno Larsen (billionai) { 79337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 79437f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 79537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 79637f219c8SBruno Larsen (billionai) } 79737f219c8SBruno Larsen (billionai) 798a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 79937f219c8SBruno Larsen (billionai) { 80037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 80137f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 80237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 80337f219c8SBruno Larsen (billionai) } 80437f219c8SBruno Larsen (billionai) 805a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 80637f219c8SBruno Larsen (billionai) { 80737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 80837f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 80937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 81037f219c8SBruno Larsen (billionai) } 81137f219c8SBruno Larsen (billionai) 812a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 81337f219c8SBruno Larsen (billionai) { 81437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 81537f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 81637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 81737f219c8SBruno Larsen (billionai) } 81837f219c8SBruno Larsen (billionai) 81937f219c8SBruno Larsen (billionai) /* SDR1 */ 820a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 82137f219c8SBruno Larsen (billionai) { 82237f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 82337f219c8SBruno Larsen (billionai) } 82437f219c8SBruno Larsen (billionai) 82537f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 82637f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 82737f219c8SBruno Larsen (billionai) /* PIDR */ 828a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 82937f219c8SBruno Larsen (billionai) { 83037f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 83137f219c8SBruno Larsen (billionai) } 83237f219c8SBruno Larsen (billionai) 833a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 83437f219c8SBruno Larsen (billionai) { 83537f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 83637f219c8SBruno Larsen (billionai) } 83737f219c8SBruno Larsen (billionai) 838a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 83937f219c8SBruno Larsen (billionai) { 84037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 84137f219c8SBruno Larsen (billionai) } 84237f219c8SBruno Larsen (billionai) 843a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 84437f219c8SBruno Larsen (billionai) { 84537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 84637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 84737f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 84837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 84937f219c8SBruno Larsen (billionai) } 850a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 85137f219c8SBruno Larsen (billionai) { 85237f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 85337f219c8SBruno Larsen (billionai) } 85437f219c8SBruno Larsen (billionai) 855a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 85637f219c8SBruno Larsen (billionai) { 85737f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 85837f219c8SBruno Larsen (billionai) } 85937f219c8SBruno Larsen (billionai) 86037f219c8SBruno Larsen (billionai) /* DPDES */ 861a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 86237f219c8SBruno Larsen (billionai) { 86337f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 86437f219c8SBruno Larsen (billionai) } 86537f219c8SBruno Larsen (billionai) 866a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 86737f219c8SBruno Larsen (billionai) { 86837f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 86937f219c8SBruno Larsen (billionai) } 87037f219c8SBruno Larsen (billionai) #endif 87137f219c8SBruno Larsen (billionai) #endif 87237f219c8SBruno Larsen (billionai) 87337f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 87437f219c8SBruno Larsen (billionai) /* RTC */ 875a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 87637f219c8SBruno Larsen (billionai) { 87737f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 87837f219c8SBruno Larsen (billionai) } 87937f219c8SBruno Larsen (billionai) 880a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 88137f219c8SBruno Larsen (billionai) { 88237f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 88337f219c8SBruno Larsen (billionai) } 88437f219c8SBruno Larsen (billionai) 88537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 886a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 88737f219c8SBruno Larsen (billionai) { 88837f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 88937f219c8SBruno Larsen (billionai) } 89037f219c8SBruno Larsen (billionai) 891a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 89237f219c8SBruno Larsen (billionai) { 89337f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 89437f219c8SBruno Larsen (billionai) } 89537f219c8SBruno Larsen (billionai) 896a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 89737f219c8SBruno Larsen (billionai) { 89837f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 89937f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 90037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 90137f219c8SBruno Larsen (billionai) } 90237f219c8SBruno Larsen (billionai) #endif 90337f219c8SBruno Larsen (billionai) 90437f219c8SBruno Larsen (billionai) /* Unified bats */ 90537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 906a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 90737f219c8SBruno Larsen (billionai) { 90837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 90937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 91037f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 91137f219c8SBruno Larsen (billionai) } 91237f219c8SBruno Larsen (billionai) 913a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 91437f219c8SBruno Larsen (billionai) { 91537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 91637f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 91737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91837f219c8SBruno Larsen (billionai) } 91937f219c8SBruno Larsen (billionai) 920a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 92137f219c8SBruno Larsen (billionai) { 92237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 92337f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 92437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92537f219c8SBruno Larsen (billionai) } 92637f219c8SBruno Larsen (billionai) #endif 92737f219c8SBruno Larsen (billionai) 92837f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 92937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 930a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 93137f219c8SBruno Larsen (billionai) { 93237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 93337f219c8SBruno Larsen (billionai) gen_io_start(); 93437f219c8SBruno Larsen (billionai) } 93537f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 93637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 93737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 93837f219c8SBruno Larsen (billionai) } 93937f219c8SBruno Larsen (billionai) } 94037f219c8SBruno Larsen (billionai) 941a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 94237f219c8SBruno Larsen (billionai) { 94337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 94437f219c8SBruno Larsen (billionai) gen_io_start(); 94537f219c8SBruno Larsen (billionai) } 94637f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 94737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 94837f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 94937f219c8SBruno Larsen (billionai) } 95037f219c8SBruno Larsen (billionai) } 95137f219c8SBruno Larsen (billionai) 952a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 95337f219c8SBruno Larsen (billionai) { 95437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 95537f219c8SBruno Larsen (billionai) gen_io_start(); 95637f219c8SBruno Larsen (billionai) } 95737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 95837f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 95937f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 96037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 96137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 96237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 96337f219c8SBruno Larsen (billionai) } 96437f219c8SBruno Larsen (billionai) } 96537f219c8SBruno Larsen (billionai) 966a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 96737f219c8SBruno Larsen (billionai) { 96837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 96937f219c8SBruno Larsen (billionai) gen_io_start(); 97037f219c8SBruno Larsen (billionai) } 97137f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 97237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 97337f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 97437f219c8SBruno Larsen (billionai) } 97537f219c8SBruno Larsen (billionai) } 97637f219c8SBruno Larsen (billionai) 977a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 97837f219c8SBruno Larsen (billionai) { 97937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 98037f219c8SBruno Larsen (billionai) gen_io_start(); 98137f219c8SBruno Larsen (billionai) } 98237f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 98337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 98437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 98537f219c8SBruno Larsen (billionai) } 98637f219c8SBruno Larsen (billionai) } 98737f219c8SBruno Larsen (billionai) 988a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 98937f219c8SBruno Larsen (billionai) { 99037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 99137f219c8SBruno Larsen (billionai) gen_io_start(); 99237f219c8SBruno Larsen (billionai) } 99337f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 99437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 99537f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 99637f219c8SBruno Larsen (billionai) } 99737f219c8SBruno Larsen (billionai) } 99837f219c8SBruno Larsen (billionai) #endif 99937f219c8SBruno Larsen (billionai) 100037f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 100137f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 100237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1003a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 100437f219c8SBruno Larsen (billionai) { 100537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 100637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 100737f219c8SBruno Larsen (billionai) } 100837f219c8SBruno Larsen (billionai) 1009a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 101037f219c8SBruno Larsen (billionai) { 101137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 101237f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 101337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 101437f219c8SBruno Larsen (billionai) } 101537f219c8SBruno Larsen (billionai) 1016a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 101737f219c8SBruno Larsen (billionai) { 101837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 101937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 102037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 102137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 102237f219c8SBruno Larsen (billionai) } 102337f219c8SBruno Larsen (billionai) #endif 102437f219c8SBruno Larsen (billionai) 102537f219c8SBruno Larsen (billionai) /* SPE specific registers */ 1026a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 102737f219c8SBruno Larsen (billionai) { 102837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 102937f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 103037f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 103137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 103237f219c8SBruno Larsen (billionai) } 103337f219c8SBruno Larsen (billionai) 1034a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 103537f219c8SBruno Larsen (billionai) { 103637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 103737f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 103837f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 103937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 104037f219c8SBruno Larsen (billionai) } 104137f219c8SBruno Larsen (billionai) 104237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 104337f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 1044a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 104537f219c8SBruno Larsen (billionai) { 104637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 104737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 104837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 104937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 105037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 105137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 105237f219c8SBruno Larsen (billionai) } 105337f219c8SBruno Larsen (billionai) 1054a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 105537f219c8SBruno Larsen (billionai) { 105637f219c8SBruno Larsen (billionai) int sprn_offs; 105737f219c8SBruno Larsen (billionai) 105837f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 105937f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 106037f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 106137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 106237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 106337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 106437f219c8SBruno Larsen (billionai) } else { 106537f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 106637f219c8SBruno Larsen (billionai) sprn, sprn); 106737f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 106837f219c8SBruno Larsen (billionai) return; 106937f219c8SBruno Larsen (billionai) } 107037f219c8SBruno Larsen (billionai) 107137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 107337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 107437f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 107537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 107637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 107737f219c8SBruno Larsen (billionai) } 107837f219c8SBruno Larsen (billionai) #endif 107937f219c8SBruno Larsen (billionai) 108037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 108137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1082a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 108337f219c8SBruno Larsen (billionai) { 108437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 108637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 108737f219c8SBruno Larsen (billionai) 108837f219c8SBruno Larsen (billionai) /* 108937f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 109037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 109137f219c8SBruno Larsen (billionai) */ 109237f219c8SBruno Larsen (billionai) 109337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 109437f219c8SBruno Larsen (billionai) if (ctx->pr) { 109537f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 109637f219c8SBruno Larsen (billionai) } else { 109737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 109837f219c8SBruno Larsen (billionai) } 109937f219c8SBruno Larsen (billionai) 110037f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 110137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 110237f219c8SBruno Larsen (billionai) 110337f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 110437f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 110537f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 110637f219c8SBruno Larsen (billionai) 110737f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 110837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 110937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 111037f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 111137f219c8SBruno Larsen (billionai) 111237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 111337f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 111437f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 111537f219c8SBruno Larsen (billionai) } 111637f219c8SBruno Larsen (billionai) 1117a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 111837f219c8SBruno Larsen (billionai) { 111937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 112037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 112137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 112237f219c8SBruno Larsen (billionai) 112337f219c8SBruno Larsen (billionai) /* 112437f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 112537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 112637f219c8SBruno Larsen (billionai) */ 112737f219c8SBruno Larsen (billionai) 112837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 112937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 113037f219c8SBruno Larsen (billionai) 113137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 113237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 113337f219c8SBruno Larsen (billionai) 113437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 113537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 113637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 113737f219c8SBruno Larsen (billionai) 113837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 113937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 114037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 114137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 114237f219c8SBruno Larsen (billionai) 114337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 114437f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 114537f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 114637f219c8SBruno Larsen (billionai) } 114737f219c8SBruno Larsen (billionai) 1148a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 114937f219c8SBruno Larsen (billionai) { 115037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 115137f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 115237f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 115337f219c8SBruno Larsen (billionai) 115437f219c8SBruno Larsen (billionai) /* 115537f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 115637f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 115737f219c8SBruno Larsen (billionai) */ 115837f219c8SBruno Larsen (billionai) 115937f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 116037f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 116137f219c8SBruno Larsen (billionai) 116237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 116337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 116437f219c8SBruno Larsen (billionai) 116537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 116637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 116737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 116837f219c8SBruno Larsen (billionai) 116937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 117037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 117137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 117237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 117337f219c8SBruno Larsen (billionai) 117437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 117537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 117637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 117737f219c8SBruno Larsen (billionai) } 117837f219c8SBruno Larsen (billionai) #endif 117937f219c8SBruno Larsen (billionai) #endif 118037f219c8SBruno Larsen (billionai) 118137f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1182a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 118337f219c8SBruno Larsen (billionai) { 118437f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 118537f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 118637f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 118737f219c8SBruno Larsen (billionai) } 118837f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 118937f219c8SBruno Larsen (billionai) 119037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1191a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 119237f219c8SBruno Larsen (billionai) { 119337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 119437f219c8SBruno Larsen (billionai) 119537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 119637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 119737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 119837f219c8SBruno Larsen (billionai) } 119937f219c8SBruno Larsen (billionai) 1200a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 120137f219c8SBruno Larsen (billionai) { 120237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 120337f219c8SBruno Larsen (billionai) 120437f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 120537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 120637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 120737f219c8SBruno Larsen (billionai) } 120837f219c8SBruno Larsen (billionai) 1209a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 121037f219c8SBruno Larsen (billionai) { 121137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 121237f219c8SBruno Larsen (billionai) 121337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 121437f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 121537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 121637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 121737f219c8SBruno Larsen (billionai) } 121837f219c8SBruno Larsen (billionai) 1219a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 122037f219c8SBruno Larsen (billionai) { 122137f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 122237f219c8SBruno Larsen (billionai) } 122337f219c8SBruno Larsen (billionai) 1224a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 122537f219c8SBruno Larsen (billionai) { 122637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 122737f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 122837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 122937f219c8SBruno Larsen (billionai) } 1230a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 123137f219c8SBruno Larsen (billionai) { 123237f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 123337f219c8SBruno Larsen (billionai) } 1234a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 123537f219c8SBruno Larsen (billionai) { 123637f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 123737f219c8SBruno Larsen (billionai) } 123837f219c8SBruno Larsen (billionai) 123937f219c8SBruno Larsen (billionai) #endif 124037f219c8SBruno Larsen (billionai) 124137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1242a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 124337f219c8SBruno Larsen (billionai) { 124437f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 124537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 124637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 124737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 124837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 124937f219c8SBruno Larsen (billionai) tcg_temp_free(val); 125037f219c8SBruno Larsen (billionai) } 125137f219c8SBruno Larsen (billionai) 1252a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 125337f219c8SBruno Larsen (billionai) { 125437f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 125537f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 125637f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 125737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 125837f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 125937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 126037f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 126137f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 126237f219c8SBruno Larsen (billionai) } 126337f219c8SBruno Larsen (billionai) 126437f219c8SBruno Larsen (billionai) #endif 126537f219c8SBruno Larsen (billionai) 126637f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 126737f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 126837f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 126937f219c8SBruno Larsen (billionai) { 127037f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 127137f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 127237f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 127337f219c8SBruno Larsen (billionai) 127437f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 127537f219c8SBruno Larsen (billionai) 127637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 127737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 127837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 127937f219c8SBruno Larsen (billionai) } 128037f219c8SBruno Larsen (billionai) 128137f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 128237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 128337f219c8SBruno Larsen (billionai) { 128437f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 128537f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 128637f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 128737f219c8SBruno Larsen (billionai) 128837f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 128937f219c8SBruno Larsen (billionai) 129037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 129137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 129237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 129337f219c8SBruno Larsen (billionai) } 129437f219c8SBruno Larsen (billionai) 1295a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 129637f219c8SBruno Larsen (billionai) { 129737f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 129837f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 129937f219c8SBruno Larsen (billionai) 130037f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 130137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 130237f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 130337f219c8SBruno Larsen (billionai) 130437f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 130537f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 130637f219c8SBruno Larsen (billionai) } 130737f219c8SBruno Larsen (billionai) 1308a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 130937f219c8SBruno Larsen (billionai) { 131037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 131137f219c8SBruno Larsen (billionai) 131237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 131337f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 131437f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 131537f219c8SBruno Larsen (billionai) 131637f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 131737f219c8SBruno Larsen (billionai) } 131837f219c8SBruno Larsen (billionai) 131937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1320a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 132137f219c8SBruno Larsen (billionai) { 132237f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 132337f219c8SBruno Larsen (billionai) 132437f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 132537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 132637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 132737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 132837f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 132937f219c8SBruno Larsen (billionai) } 133037f219c8SBruno Larsen (billionai) 1331a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 133237f219c8SBruno Larsen (billionai) { 133337f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 133437f219c8SBruno Larsen (billionai) } 133537f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 133637f219c8SBruno Larsen (billionai) 1337a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 133837f219c8SBruno Larsen (billionai) { 133937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 134037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 134137f219c8SBruno Larsen (billionai) } 134237f219c8SBruno Larsen (billionai) 1343a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 134437f219c8SBruno Larsen (billionai) { 134537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 134637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 134737f219c8SBruno Larsen (billionai) } 134837f219c8SBruno Larsen (billionai) 1349a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 135037f219c8SBruno Larsen (billionai) { 135137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 135237f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 135337f219c8SBruno Larsen (billionai) } 135437f219c8SBruno Larsen (billionai) 1355a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 135637f219c8SBruno Larsen (billionai) { 135737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 135837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 135937f219c8SBruno Larsen (billionai) } 136037f219c8SBruno Larsen (billionai) 1361a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 136237f219c8SBruno Larsen (billionai) { 136337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 136437f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 136537f219c8SBruno Larsen (billionai) } 136637f219c8SBruno Larsen (billionai) 1367a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 136837f219c8SBruno Larsen (billionai) { 136937f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 137037f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 137137f219c8SBruno Larsen (billionai) } 137237f219c8SBruno Larsen (billionai) 1373a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 137437f219c8SBruno Larsen (billionai) { 137537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 137637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 137737f219c8SBruno Larsen (billionai) } 137837f219c8SBruno Larsen (billionai) 1379a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 138037f219c8SBruno Larsen (billionai) { 138137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 138237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 138337f219c8SBruno Larsen (billionai) } 138437f219c8SBruno Larsen (billionai) 1385a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 138637f219c8SBruno Larsen (billionai) { 138737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 138837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 138937f219c8SBruno Larsen (billionai) } 139037f219c8SBruno Larsen (billionai) 1391a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 139237f219c8SBruno Larsen (billionai) { 139337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 139437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 139537f219c8SBruno Larsen (billionai) } 139637f219c8SBruno Larsen (billionai) #endif 139737f219c8SBruno Larsen (billionai) 1398fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1399fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1400fcf5ef2aSThomas Huth 1401fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1402fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1403fcf5ef2aSThomas Huth 1404fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1405fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1406fcf5ef2aSThomas Huth 1407fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1408fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1409fcf5ef2aSThomas Huth 1410fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1411fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1412fcf5ef2aSThomas Huth 1413fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1414fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1415fcf5ef2aSThomas Huth 1416fcf5ef2aSThomas Huth typedef struct opcode_t { 1417fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1418fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1419fcf5ef2aSThomas Huth unsigned char pad[4]; 1420fcf5ef2aSThomas Huth #endif 1421fcf5ef2aSThomas Huth opc_handler_t handler; 1422fcf5ef2aSThomas Huth const char *oname; 1423fcf5ef2aSThomas Huth } opcode_t; 1424fcf5ef2aSThomas Huth 1425fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1426fcf5ef2aSThomas Huth #define GEN_PRIV \ 1427fcf5ef2aSThomas Huth do { \ 1428fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1429fcf5ef2aSThomas Huth } while (0) 1430fcf5ef2aSThomas Huth 1431fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1432fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1433fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1434fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1435fcf5ef2aSThomas Huth #else 1436fcf5ef2aSThomas Huth #define CHK_HV \ 1437fcf5ef2aSThomas Huth do { \ 1438fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1439fcf5ef2aSThomas Huth GEN_PRIV; \ 1440fcf5ef2aSThomas Huth } \ 1441fcf5ef2aSThomas Huth } while (0) 1442fcf5ef2aSThomas Huth #define CHK_SV \ 1443fcf5ef2aSThomas Huth do { \ 1444fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1445fcf5ef2aSThomas Huth GEN_PRIV; \ 1446fcf5ef2aSThomas Huth } \ 1447fcf5ef2aSThomas Huth } while (0) 1448fcf5ef2aSThomas Huth #define CHK_HVRM \ 1449fcf5ef2aSThomas Huth do { \ 1450fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1451fcf5ef2aSThomas Huth GEN_PRIV; \ 1452fcf5ef2aSThomas Huth } \ 1453fcf5ef2aSThomas Huth } while (0) 1454fcf5ef2aSThomas Huth #endif 1455fcf5ef2aSThomas Huth 1456fcf5ef2aSThomas Huth #define CHK_NONE 1457fcf5ef2aSThomas Huth 1458fcf5ef2aSThomas Huth /*****************************************************************************/ 1459fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1460fcf5ef2aSThomas Huth 1461fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 1462fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1463fcf5ef2aSThomas Huth { \ 1464fcf5ef2aSThomas Huth .opc1 = op1, \ 1465fcf5ef2aSThomas Huth .opc2 = op2, \ 1466fcf5ef2aSThomas Huth .opc3 = op3, \ 1467fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1468fcf5ef2aSThomas Huth .handler = { \ 1469fcf5ef2aSThomas Huth .inval1 = invl, \ 1470fcf5ef2aSThomas Huth .type = _typ, \ 1471fcf5ef2aSThomas Huth .type2 = _typ2, \ 1472fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1473fcf5ef2aSThomas Huth .oname = stringify(name), \ 1474fcf5ef2aSThomas Huth }, \ 1475fcf5ef2aSThomas Huth .oname = stringify(name), \ 1476fcf5ef2aSThomas Huth } 1477fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1478fcf5ef2aSThomas Huth { \ 1479fcf5ef2aSThomas Huth .opc1 = op1, \ 1480fcf5ef2aSThomas Huth .opc2 = op2, \ 1481fcf5ef2aSThomas Huth .opc3 = op3, \ 1482fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1483fcf5ef2aSThomas Huth .handler = { \ 1484fcf5ef2aSThomas Huth .inval1 = invl1, \ 1485fcf5ef2aSThomas Huth .inval2 = invl2, \ 1486fcf5ef2aSThomas Huth .type = _typ, \ 1487fcf5ef2aSThomas Huth .type2 = _typ2, \ 1488fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1489fcf5ef2aSThomas Huth .oname = stringify(name), \ 1490fcf5ef2aSThomas Huth }, \ 1491fcf5ef2aSThomas Huth .oname = stringify(name), \ 1492fcf5ef2aSThomas Huth } 1493fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1494fcf5ef2aSThomas Huth { \ 1495fcf5ef2aSThomas Huth .opc1 = op1, \ 1496fcf5ef2aSThomas Huth .opc2 = op2, \ 1497fcf5ef2aSThomas Huth .opc3 = op3, \ 1498fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1499fcf5ef2aSThomas Huth .handler = { \ 1500fcf5ef2aSThomas Huth .inval1 = invl, \ 1501fcf5ef2aSThomas Huth .type = _typ, \ 1502fcf5ef2aSThomas Huth .type2 = _typ2, \ 1503fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1504fcf5ef2aSThomas Huth .oname = onam, \ 1505fcf5ef2aSThomas Huth }, \ 1506fcf5ef2aSThomas Huth .oname = onam, \ 1507fcf5ef2aSThomas Huth } 1508fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1509fcf5ef2aSThomas Huth { \ 1510fcf5ef2aSThomas Huth .opc1 = op1, \ 1511fcf5ef2aSThomas Huth .opc2 = op2, \ 1512fcf5ef2aSThomas Huth .opc3 = op3, \ 1513fcf5ef2aSThomas Huth .opc4 = op4, \ 1514fcf5ef2aSThomas Huth .handler = { \ 1515fcf5ef2aSThomas Huth .inval1 = invl, \ 1516fcf5ef2aSThomas Huth .type = _typ, \ 1517fcf5ef2aSThomas Huth .type2 = _typ2, \ 1518fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1519fcf5ef2aSThomas Huth .oname = stringify(name), \ 1520fcf5ef2aSThomas Huth }, \ 1521fcf5ef2aSThomas Huth .oname = stringify(name), \ 1522fcf5ef2aSThomas Huth } 1523fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1524fcf5ef2aSThomas Huth { \ 1525fcf5ef2aSThomas Huth .opc1 = op1, \ 1526fcf5ef2aSThomas Huth .opc2 = op2, \ 1527fcf5ef2aSThomas Huth .opc3 = op3, \ 1528fcf5ef2aSThomas Huth .opc4 = op4, \ 1529fcf5ef2aSThomas Huth .handler = { \ 1530fcf5ef2aSThomas Huth .inval1 = invl, \ 1531fcf5ef2aSThomas Huth .type = _typ, \ 1532fcf5ef2aSThomas Huth .type2 = _typ2, \ 1533fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1534fcf5ef2aSThomas Huth .oname = onam, \ 1535fcf5ef2aSThomas Huth }, \ 1536fcf5ef2aSThomas Huth .oname = onam, \ 1537fcf5ef2aSThomas Huth } 1538fcf5ef2aSThomas Huth #else 1539fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1540fcf5ef2aSThomas Huth { \ 1541fcf5ef2aSThomas Huth .opc1 = op1, \ 1542fcf5ef2aSThomas Huth .opc2 = op2, \ 1543fcf5ef2aSThomas Huth .opc3 = op3, \ 1544fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1545fcf5ef2aSThomas Huth .handler = { \ 1546fcf5ef2aSThomas Huth .inval1 = invl, \ 1547fcf5ef2aSThomas Huth .type = _typ, \ 1548fcf5ef2aSThomas Huth .type2 = _typ2, \ 1549fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1550fcf5ef2aSThomas Huth }, \ 1551fcf5ef2aSThomas Huth .oname = stringify(name), \ 1552fcf5ef2aSThomas Huth } 1553fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1554fcf5ef2aSThomas Huth { \ 1555fcf5ef2aSThomas Huth .opc1 = op1, \ 1556fcf5ef2aSThomas Huth .opc2 = op2, \ 1557fcf5ef2aSThomas Huth .opc3 = op3, \ 1558fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1559fcf5ef2aSThomas Huth .handler = { \ 1560fcf5ef2aSThomas Huth .inval1 = invl1, \ 1561fcf5ef2aSThomas Huth .inval2 = invl2, \ 1562fcf5ef2aSThomas Huth .type = _typ, \ 1563fcf5ef2aSThomas Huth .type2 = _typ2, \ 1564fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1565fcf5ef2aSThomas Huth }, \ 1566fcf5ef2aSThomas Huth .oname = stringify(name), \ 1567fcf5ef2aSThomas Huth } 1568fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1569fcf5ef2aSThomas Huth { \ 1570fcf5ef2aSThomas Huth .opc1 = op1, \ 1571fcf5ef2aSThomas Huth .opc2 = op2, \ 1572fcf5ef2aSThomas Huth .opc3 = op3, \ 1573fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1574fcf5ef2aSThomas Huth .handler = { \ 1575fcf5ef2aSThomas Huth .inval1 = invl, \ 1576fcf5ef2aSThomas Huth .type = _typ, \ 1577fcf5ef2aSThomas Huth .type2 = _typ2, \ 1578fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1579fcf5ef2aSThomas Huth }, \ 1580fcf5ef2aSThomas Huth .oname = onam, \ 1581fcf5ef2aSThomas Huth } 1582fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1583fcf5ef2aSThomas Huth { \ 1584fcf5ef2aSThomas Huth .opc1 = op1, \ 1585fcf5ef2aSThomas Huth .opc2 = op2, \ 1586fcf5ef2aSThomas Huth .opc3 = op3, \ 1587fcf5ef2aSThomas Huth .opc4 = op4, \ 1588fcf5ef2aSThomas Huth .handler = { \ 1589fcf5ef2aSThomas Huth .inval1 = invl, \ 1590fcf5ef2aSThomas Huth .type = _typ, \ 1591fcf5ef2aSThomas Huth .type2 = _typ2, \ 1592fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1593fcf5ef2aSThomas Huth }, \ 1594fcf5ef2aSThomas Huth .oname = stringify(name), \ 1595fcf5ef2aSThomas Huth } 1596fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1597fcf5ef2aSThomas Huth { \ 1598fcf5ef2aSThomas Huth .opc1 = op1, \ 1599fcf5ef2aSThomas Huth .opc2 = op2, \ 1600fcf5ef2aSThomas Huth .opc3 = op3, \ 1601fcf5ef2aSThomas Huth .opc4 = op4, \ 1602fcf5ef2aSThomas Huth .handler = { \ 1603fcf5ef2aSThomas Huth .inval1 = invl, \ 1604fcf5ef2aSThomas Huth .type = _typ, \ 1605fcf5ef2aSThomas Huth .type2 = _typ2, \ 1606fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1607fcf5ef2aSThomas Huth }, \ 1608fcf5ef2aSThomas Huth .oname = onam, \ 1609fcf5ef2aSThomas Huth } 1610fcf5ef2aSThomas Huth #endif 1611fcf5ef2aSThomas Huth 1612fcf5ef2aSThomas Huth /* Invalid instruction */ 1613fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1614fcf5ef2aSThomas Huth { 1615fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1616fcf5ef2aSThomas Huth } 1617fcf5ef2aSThomas Huth 1618fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1619fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1620fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1621fcf5ef2aSThomas Huth .type = PPC_NONE, 1622fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1623fcf5ef2aSThomas Huth .handler = gen_invalid, 1624fcf5ef2aSThomas Huth }; 1625fcf5ef2aSThomas Huth 1626fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1627fcf5ef2aSThomas Huth 1628fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1629fcf5ef2aSThomas Huth { 1630fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1631b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1632b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1633fcf5ef2aSThomas Huth 1634b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1635b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1636efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1637efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1638b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1639efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1640efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1641b62b3686Spbonzini@redhat.com 1642b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1643fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1644b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1645fcf5ef2aSThomas Huth 1646fcf5ef2aSThomas Huth tcg_temp_free(t0); 1647b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1648b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1649fcf5ef2aSThomas Huth } 1650fcf5ef2aSThomas Huth 1651fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1652fcf5ef2aSThomas Huth { 1653fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1654fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1655fcf5ef2aSThomas Huth tcg_temp_free(t0); 1656fcf5ef2aSThomas Huth } 1657fcf5ef2aSThomas Huth 1658fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1659fcf5ef2aSThomas Huth { 1660fcf5ef2aSThomas Huth TCGv t0, t1; 1661fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1662fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1663fcf5ef2aSThomas Huth if (s) { 1664fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1665fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1666fcf5ef2aSThomas Huth } else { 1667fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1668fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1669fcf5ef2aSThomas Huth } 1670fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1671fcf5ef2aSThomas Huth tcg_temp_free(t1); 1672fcf5ef2aSThomas Huth tcg_temp_free(t0); 1673fcf5ef2aSThomas Huth } 1674fcf5ef2aSThomas Huth 1675fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1676fcf5ef2aSThomas Huth { 1677fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1678fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1679fcf5ef2aSThomas Huth tcg_temp_free(t0); 1680fcf5ef2aSThomas Huth } 1681fcf5ef2aSThomas Huth 1682fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1683fcf5ef2aSThomas Huth { 1684fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1685fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1686fcf5ef2aSThomas Huth } else { 1687fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1688fcf5ef2aSThomas Huth } 1689fcf5ef2aSThomas Huth } 1690fcf5ef2aSThomas Huth 1691fcf5ef2aSThomas Huth /* cmp */ 1692fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1693fcf5ef2aSThomas Huth { 1694fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1695fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1696fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1697fcf5ef2aSThomas Huth } else { 1698fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1699fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1700fcf5ef2aSThomas Huth } 1701fcf5ef2aSThomas Huth } 1702fcf5ef2aSThomas Huth 1703fcf5ef2aSThomas Huth /* cmpi */ 1704fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1705fcf5ef2aSThomas Huth { 1706fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1707fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1708fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1709fcf5ef2aSThomas Huth } else { 1710fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1711fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1712fcf5ef2aSThomas Huth } 1713fcf5ef2aSThomas Huth } 1714fcf5ef2aSThomas Huth 1715fcf5ef2aSThomas Huth /* cmpl */ 1716fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1717fcf5ef2aSThomas Huth { 1718fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1719fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1720fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1721fcf5ef2aSThomas Huth } else { 1722fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1723fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1724fcf5ef2aSThomas Huth } 1725fcf5ef2aSThomas Huth } 1726fcf5ef2aSThomas Huth 1727fcf5ef2aSThomas Huth /* cmpli */ 1728fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1729fcf5ef2aSThomas Huth { 1730fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1731fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1732fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1733fcf5ef2aSThomas Huth } else { 1734fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1735fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1736fcf5ef2aSThomas Huth } 1737fcf5ef2aSThomas Huth } 1738fcf5ef2aSThomas Huth 1739fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1740fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1741fcf5ef2aSThomas Huth { 1742fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1743fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1744fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1745fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1746fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1747fcf5ef2aSThomas Huth 1748fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1749fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1750fcf5ef2aSThomas Huth 1751fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1752fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1753fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1754fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1755fcf5ef2aSThomas Huth 1756fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1757fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1758fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1759fcf5ef2aSThomas Huth 1760fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1761fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1762fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1763fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1764fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1765fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1766fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1767fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1768fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1769fcf5ef2aSThomas Huth } 1770efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1771fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1772fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1773fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1774fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1775fcf5ef2aSThomas Huth } 1776fcf5ef2aSThomas Huth 1777fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1778fcf5ef2aSThomas Huth /* cmpeqb */ 1779fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1780fcf5ef2aSThomas Huth { 1781fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1782fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1783fcf5ef2aSThomas Huth } 1784fcf5ef2aSThomas Huth #endif 1785fcf5ef2aSThomas Huth 1786fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1787fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1788fcf5ef2aSThomas Huth { 1789fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1790fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1791fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1792fcf5ef2aSThomas Huth TCGv zr; 1793fcf5ef2aSThomas Huth 1794fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1795fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1796fcf5ef2aSThomas Huth 1797fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1798fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1799fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1800fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1801fcf5ef2aSThomas Huth tcg_temp_free(zr); 1802fcf5ef2aSThomas Huth tcg_temp_free(t0); 1803fcf5ef2aSThomas Huth } 1804fcf5ef2aSThomas Huth 1805fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1806fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1807fcf5ef2aSThomas Huth { 1808fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1809fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1810fcf5ef2aSThomas Huth } 1811fcf5ef2aSThomas Huth 1812fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1813fcf5ef2aSThomas Huth 1814fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1815fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1816fcf5ef2aSThomas Huth { 1817fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1818fcf5ef2aSThomas Huth 1819fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1820fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1821fcf5ef2aSThomas Huth if (sub) { 1822fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1823fcf5ef2aSThomas Huth } else { 1824fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1825fcf5ef2aSThomas Huth } 1826fcf5ef2aSThomas Huth tcg_temp_free(t0); 1827fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1828dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1829dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1830dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1831fcf5ef2aSThomas Huth } 1832dc0ad844SNikunj A Dadhania } else { 1833dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1834dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1835dc0ad844SNikunj A Dadhania } 183638a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1837dc0ad844SNikunj A Dadhania } 1838fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1839fcf5ef2aSThomas Huth } 1840fcf5ef2aSThomas Huth 18416b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 18426b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 18434c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 18446b10d008SNikunj A Dadhania { 18456b10d008SNikunj A Dadhania TCGv t0; 18466b10d008SNikunj A Dadhania 18476b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 18486b10d008SNikunj A Dadhania return; 18496b10d008SNikunj A Dadhania } 18506b10d008SNikunj A Dadhania 18516b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 185233903d0aSNikunj A Dadhania if (sub) { 185333903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 185433903d0aSNikunj A Dadhania } else { 18556b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 185633903d0aSNikunj A Dadhania } 18576b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 18584c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 18596b10d008SNikunj A Dadhania tcg_temp_free(t0); 18606b10d008SNikunj A Dadhania } 18616b10d008SNikunj A Dadhania 1862fcf5ef2aSThomas Huth /* Common add function */ 1863fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 18644c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 18654c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1866fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1867fcf5ef2aSThomas Huth { 1868fcf5ef2aSThomas Huth TCGv t0 = ret; 1869fcf5ef2aSThomas Huth 1870fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1871fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1872fcf5ef2aSThomas Huth } 1873fcf5ef2aSThomas Huth 1874fcf5ef2aSThomas Huth if (compute_ca) { 1875fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1876efe843d8SDavid Gibson /* 1877efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1878efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1879efe843d8SDavid Gibson * produce the carry into bit 32. 1880efe843d8SDavid Gibson */ 1881fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1882fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1883fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1884fcf5ef2aSThomas Huth if (add_ca) { 18854c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1886fcf5ef2aSThomas Huth } 18874c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1888fcf5ef2aSThomas Huth tcg_temp_free(t1); 18894c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 18906b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 18914c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 18926b10d008SNikunj A Dadhania } 1893fcf5ef2aSThomas Huth } else { 1894fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1895fcf5ef2aSThomas Huth if (add_ca) { 18964c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 18974c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1898fcf5ef2aSThomas Huth } else { 18994c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1900fcf5ef2aSThomas Huth } 19014c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1902fcf5ef2aSThomas Huth tcg_temp_free(zero); 1903fcf5ef2aSThomas Huth } 1904fcf5ef2aSThomas Huth } else { 1905fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1906fcf5ef2aSThomas Huth if (add_ca) { 19074c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1908fcf5ef2aSThomas Huth } 1909fcf5ef2aSThomas Huth } 1910fcf5ef2aSThomas Huth 1911fcf5ef2aSThomas Huth if (compute_ov) { 1912fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1915fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1916fcf5ef2aSThomas Huth } 1917fcf5ef2aSThomas Huth 191811f4e8f8SRichard Henderson if (t0 != ret) { 1919fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1920fcf5ef2aSThomas Huth tcg_temp_free(t0); 1921fcf5ef2aSThomas Huth } 1922fcf5ef2aSThomas Huth } 1923fcf5ef2aSThomas Huth /* Add functions with two operands */ 19244c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1925fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1926fcf5ef2aSThomas Huth { \ 1927fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1928fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 19294c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1930fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1931fcf5ef2aSThomas Huth } 1932fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 19334c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1934fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1935fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1936fcf5ef2aSThomas Huth { \ 1937fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1938fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1939fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 19404c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1941fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1942fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1943fcf5ef2aSThomas Huth } 1944fcf5ef2aSThomas Huth 1945fcf5ef2aSThomas Huth /* add add. addo addo. */ 19464c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 19474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1948fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 19494c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 19504c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1951fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 19524c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 19534c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1954fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 19554c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 19564c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 19574c5920afSSuraj Jitindar Singh /* addex */ 19584c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1959fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 19604c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 19614c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1962fcf5ef2aSThomas Huth /* addi */ 1963fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 1964fcf5ef2aSThomas Huth { 1965fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1966fcf5ef2aSThomas Huth 1967fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1968fcf5ef2aSThomas Huth /* li case */ 1969fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 1970fcf5ef2aSThomas Huth } else { 1971fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1972fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 1973fcf5ef2aSThomas Huth } 1974fcf5ef2aSThomas Huth } 1975fcf5ef2aSThomas Huth /* addic addic.*/ 1976fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1977fcf5ef2aSThomas Huth { 1978fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1979fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 19804c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1981fcf5ef2aSThomas Huth tcg_temp_free(c); 1982fcf5ef2aSThomas Huth } 1983fcf5ef2aSThomas Huth 1984fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1985fcf5ef2aSThomas Huth { 1986fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1987fcf5ef2aSThomas Huth } 1988fcf5ef2aSThomas Huth 1989fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1990fcf5ef2aSThomas Huth { 1991fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1992fcf5ef2aSThomas Huth } 1993fcf5ef2aSThomas Huth 1994fcf5ef2aSThomas Huth /* addis */ 1995fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 1996fcf5ef2aSThomas Huth { 1997fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1998fcf5ef2aSThomas Huth 1999fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2000fcf5ef2aSThomas Huth /* lis case */ 2001fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 2002fcf5ef2aSThomas Huth } else { 2003fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 2004fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 2005fcf5ef2aSThomas Huth } 2006fcf5ef2aSThomas Huth } 2007fcf5ef2aSThomas Huth 2008fcf5ef2aSThomas Huth /* addpcis */ 2009fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 2010fcf5ef2aSThomas Huth { 2011fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 2012fcf5ef2aSThomas Huth 2013b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 2014fcf5ef2aSThomas Huth } 2015fcf5ef2aSThomas Huth 2016fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 2017fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2018fcf5ef2aSThomas Huth { 2019fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2020fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2021fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2022fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2023fcf5ef2aSThomas Huth 2024fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2025fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2026fcf5ef2aSThomas Huth if (sign) { 2027fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2028fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2029fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2030fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2031fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2032fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2033fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2034fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 2035fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2036fcf5ef2aSThomas Huth } else { 2037fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 2038fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2039fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2040fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 2041fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2042fcf5ef2aSThomas Huth } 2043fcf5ef2aSThomas Huth if (compute_ov) { 2044fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 2045c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2046c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 2047c44027ffSNikunj A Dadhania } 2048fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2049fcf5ef2aSThomas Huth } 2050fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2051fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2052fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2053fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2054fcf5ef2aSThomas Huth 2055efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2056fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2057fcf5ef2aSThomas Huth } 2058efe843d8SDavid Gibson } 2059fcf5ef2aSThomas Huth /* Div functions */ 2060fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 2061fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2062fcf5ef2aSThomas Huth { \ 2063fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2064fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2065fcf5ef2aSThomas Huth sign, compute_ov); \ 2066fcf5ef2aSThomas Huth } 2067fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 2068fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 2069fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 2070fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 2071fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 2072fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 2073fcf5ef2aSThomas Huth 2074fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 2075fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 2076fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 2077fcf5ef2aSThomas Huth { \ 2078fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 2079fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 2080fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 2081fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 2082fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 2083fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 2084fcf5ef2aSThomas Huth } \ 2085fcf5ef2aSThomas Huth } 2086fcf5ef2aSThomas Huth 2087fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 2088fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 2089fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 2090fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 2091fcf5ef2aSThomas Huth 2092fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2093fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 2094fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2095fcf5ef2aSThomas Huth { 2096fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2097fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2098fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2099fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2100fcf5ef2aSThomas Huth 2101fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2102fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2103fcf5ef2aSThomas Huth if (sign) { 2104fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2105fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2106fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2107fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2108fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2109fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2110fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2111fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 2112fcf5ef2aSThomas Huth } else { 2113fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 2114fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2115fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2116fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 2117fcf5ef2aSThomas Huth } 2118fcf5ef2aSThomas Huth if (compute_ov) { 2119fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 2120c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2121c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 2122c44027ffSNikunj A Dadhania } 2123fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2124fcf5ef2aSThomas Huth } 2125fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2126fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2127fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2128fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2129fcf5ef2aSThomas Huth 2130efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2131fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2132fcf5ef2aSThomas Huth } 2133efe843d8SDavid Gibson } 2134fcf5ef2aSThomas Huth 2135fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 2136fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2137fcf5ef2aSThomas Huth { \ 2138fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2139fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2140fcf5ef2aSThomas Huth sign, compute_ov); \ 2141fcf5ef2aSThomas Huth } 2142c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 2143fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 2144fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 2145c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 2146fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 2147fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 2148fcf5ef2aSThomas Huth 2149fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 2150fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 2151fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 2152fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 2153fcf5ef2aSThomas Huth #endif 2154fcf5ef2aSThomas Huth 2155fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 2156fcf5ef2aSThomas Huth TCGv arg2, int sign) 2157fcf5ef2aSThomas Huth { 2158fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2159fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2160fcf5ef2aSThomas Huth 2161fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2162fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2163fcf5ef2aSThomas Huth if (sign) { 2164fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2165fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2166fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2167fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2168fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2169fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2170fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2171fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2172fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2173fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 2174fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 2175fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2176fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2177fcf5ef2aSThomas Huth } else { 2178fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 2179fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 2180fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 2181fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 2182fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2183fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2184fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2185fcf5ef2aSThomas Huth } 2186fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2187fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2188fcf5ef2aSThomas Huth } 2189fcf5ef2aSThomas Huth 2190fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 2191fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2192fcf5ef2aSThomas Huth { \ 2193fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2194fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2195fcf5ef2aSThomas Huth sign); \ 2196fcf5ef2aSThomas Huth } 2197fcf5ef2aSThomas Huth 2198fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 2199fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 2200fcf5ef2aSThomas Huth 2201fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2202fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 2203fcf5ef2aSThomas Huth TCGv arg2, int sign) 2204fcf5ef2aSThomas Huth { 2205fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2206fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2207fcf5ef2aSThomas Huth 2208fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2209fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2210fcf5ef2aSThomas Huth if (sign) { 2211fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2212fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2213fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2214fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2215fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2216fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2217fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2218fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2219fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2220fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 2221fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2222fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2223fcf5ef2aSThomas Huth } else { 2224fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 2225fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2226fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2227fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2228fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2229fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2230fcf5ef2aSThomas Huth } 2231fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2232fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2233fcf5ef2aSThomas Huth } 2234fcf5ef2aSThomas Huth 2235fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2236fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2237fcf5ef2aSThomas Huth { \ 2238fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2239fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2240fcf5ef2aSThomas Huth sign); \ 2241fcf5ef2aSThomas Huth } 2242fcf5ef2aSThomas Huth 2243fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2244fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2245fcf5ef2aSThomas Huth #endif 2246fcf5ef2aSThomas Huth 2247fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2248fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2249fcf5ef2aSThomas Huth { 2250fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2251fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2252fcf5ef2aSThomas Huth 2253fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2254fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2255fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2256fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2257fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2258fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2259efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2260fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2261fcf5ef2aSThomas Huth } 2262efe843d8SDavid Gibson } 2263fcf5ef2aSThomas Huth 2264fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2265fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2266fcf5ef2aSThomas Huth { 2267fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2268fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2269fcf5ef2aSThomas Huth 2270fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2271fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2272fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2273fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2274fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2275fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2276efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2277fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2278fcf5ef2aSThomas Huth } 2279efe843d8SDavid Gibson } 2280fcf5ef2aSThomas Huth 2281fcf5ef2aSThomas Huth /* mullw mullw. */ 2282fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2283fcf5ef2aSThomas Huth { 2284fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2285fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2286fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2287fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2288fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2289fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2290fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2291fcf5ef2aSThomas Huth tcg_temp_free(t0); 2292fcf5ef2aSThomas Huth tcg_temp_free(t1); 2293fcf5ef2aSThomas Huth #else 2294fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2295fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2296fcf5ef2aSThomas Huth #endif 2297efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2298fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2299fcf5ef2aSThomas Huth } 2300efe843d8SDavid Gibson } 2301fcf5ef2aSThomas Huth 2302fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2303fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2304fcf5ef2aSThomas Huth { 2305fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2306fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2307fcf5ef2aSThomas Huth 2308fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2309fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2310fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2311fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2312fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2313fcf5ef2aSThomas Huth #else 2314fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2315fcf5ef2aSThomas Huth #endif 2316fcf5ef2aSThomas Huth 2317fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2318fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2319fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 232061aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 232161aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 232261aa9a69SNikunj A Dadhania } 2323fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2324fcf5ef2aSThomas Huth 2325fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2326fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2327efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2328fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2329fcf5ef2aSThomas Huth } 2330efe843d8SDavid Gibson } 2331fcf5ef2aSThomas Huth 2332fcf5ef2aSThomas Huth /* mulli */ 2333fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2334fcf5ef2aSThomas Huth { 2335fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2336fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2337fcf5ef2aSThomas Huth } 2338fcf5ef2aSThomas Huth 2339fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2340fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2341fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2342fcf5ef2aSThomas Huth { 2343fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2344fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2345fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2346fcf5ef2aSThomas Huth tcg_temp_free(lo); 2347fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2348fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2349fcf5ef2aSThomas Huth } 2350fcf5ef2aSThomas Huth } 2351fcf5ef2aSThomas Huth 2352fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2353fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2354fcf5ef2aSThomas Huth { 2355fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2356fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2357fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2358fcf5ef2aSThomas Huth tcg_temp_free(lo); 2359fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2360fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2361fcf5ef2aSThomas Huth } 2362fcf5ef2aSThomas Huth } 2363fcf5ef2aSThomas Huth 2364fcf5ef2aSThomas Huth /* mulld mulld. */ 2365fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2366fcf5ef2aSThomas Huth { 2367fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2368fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2369efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2370fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2371fcf5ef2aSThomas Huth } 2372efe843d8SDavid Gibson } 2373fcf5ef2aSThomas Huth 2374fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2375fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2376fcf5ef2aSThomas Huth { 2377fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2378fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2379fcf5ef2aSThomas Huth 2380fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2381fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2382fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2383fcf5ef2aSThomas Huth 2384fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2385fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 238661aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 238761aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 238861aa9a69SNikunj A Dadhania } 2389fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2390fcf5ef2aSThomas Huth 2391fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2392fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2393fcf5ef2aSThomas Huth 2394fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2395fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2396fcf5ef2aSThomas Huth } 2397fcf5ef2aSThomas Huth } 2398fcf5ef2aSThomas Huth #endif 2399fcf5ef2aSThomas Huth 2400fcf5ef2aSThomas Huth /* Common subf function */ 2401fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2402fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2403fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2404fcf5ef2aSThomas Huth { 2405fcf5ef2aSThomas Huth TCGv t0 = ret; 2406fcf5ef2aSThomas Huth 2407fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2408fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2409fcf5ef2aSThomas Huth } 2410fcf5ef2aSThomas Huth 2411fcf5ef2aSThomas Huth if (compute_ca) { 2412fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2413fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2414efe843d8SDavid Gibson /* 2415efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2416efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2417efe843d8SDavid Gibson * produce the carry into bit 32. 2418efe843d8SDavid Gibson */ 2419fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2420fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2421fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2422fcf5ef2aSThomas Huth if (add_ca) { 2423fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2424fcf5ef2aSThomas Huth } else { 2425fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2426fcf5ef2aSThomas Huth } 2427fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2428fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2429fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2430fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2431fcf5ef2aSThomas Huth tcg_temp_free(t1); 2432e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 243333903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 243433903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 243533903d0aSNikunj A Dadhania } 2436fcf5ef2aSThomas Huth } else if (add_ca) { 2437fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2438fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2439fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2440fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2441fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 24424c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2443fcf5ef2aSThomas Huth tcg_temp_free(zero); 2444fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2445fcf5ef2aSThomas Huth } else { 2446fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2447fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 24484c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2449fcf5ef2aSThomas Huth } 2450fcf5ef2aSThomas Huth } else if (add_ca) { 2451efe843d8SDavid Gibson /* 2452efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2453efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2454efe843d8SDavid Gibson */ 2455fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2456fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2457fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2458fcf5ef2aSThomas Huth } else { 2459fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2460fcf5ef2aSThomas Huth } 2461fcf5ef2aSThomas Huth 2462fcf5ef2aSThomas Huth if (compute_ov) { 2463fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2464fcf5ef2aSThomas Huth } 2465fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2466fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2467fcf5ef2aSThomas Huth } 2468fcf5ef2aSThomas Huth 246911f4e8f8SRichard Henderson if (t0 != ret) { 2470fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2471fcf5ef2aSThomas Huth tcg_temp_free(t0); 2472fcf5ef2aSThomas Huth } 2473fcf5ef2aSThomas Huth } 2474fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2475fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2476fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2477fcf5ef2aSThomas Huth { \ 2478fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2479fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2480fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2481fcf5ef2aSThomas Huth } 2482fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2483fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2484fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2485fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2486fcf5ef2aSThomas Huth { \ 2487fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2488fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2489fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2490fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2491fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2492fcf5ef2aSThomas Huth } 2493fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2494fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2495fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2496fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2497fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2498fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2499fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2500fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2501fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2502fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2503fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2504fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2505fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2506fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2507fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2508fcf5ef2aSThomas Huth 2509fcf5ef2aSThomas Huth /* subfic */ 2510fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2511fcf5ef2aSThomas Huth { 2512fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2513fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2514fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2515fcf5ef2aSThomas Huth tcg_temp_free(c); 2516fcf5ef2aSThomas Huth } 2517fcf5ef2aSThomas Huth 2518fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2519fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2520fcf5ef2aSThomas Huth { 2521fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2522fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2523fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2524fcf5ef2aSThomas Huth tcg_temp_free(zero); 2525fcf5ef2aSThomas Huth } 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2528fcf5ef2aSThomas Huth { 25291480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 25301480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 25311480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 25321480d71cSNikunj A Dadhania } 2533fcf5ef2aSThomas Huth } 2534fcf5ef2aSThomas Huth 2535fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2536fcf5ef2aSThomas Huth { 2537fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2538fcf5ef2aSThomas Huth } 2539fcf5ef2aSThomas Huth 2540fcf5ef2aSThomas Huth /*** Integer logical ***/ 2541fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2542fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2543fcf5ef2aSThomas Huth { \ 2544fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2545fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2546fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2547fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2548fcf5ef2aSThomas Huth } 2549fcf5ef2aSThomas Huth 2550fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2551fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2552fcf5ef2aSThomas Huth { \ 2553fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2554fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2555fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2556fcf5ef2aSThomas Huth } 2557fcf5ef2aSThomas Huth 2558fcf5ef2aSThomas Huth /* and & and. */ 2559fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2560fcf5ef2aSThomas Huth /* andc & andc. */ 2561fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2562fcf5ef2aSThomas Huth 2563fcf5ef2aSThomas Huth /* andi. */ 2564fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2565fcf5ef2aSThomas Huth { 2566efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2567efe843d8SDavid Gibson UIMM(ctx->opcode)); 2568fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2569fcf5ef2aSThomas Huth } 2570fcf5ef2aSThomas Huth 2571fcf5ef2aSThomas Huth /* andis. */ 2572fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2573fcf5ef2aSThomas Huth { 2574efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2575efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2576fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2577fcf5ef2aSThomas Huth } 2578fcf5ef2aSThomas Huth 2579fcf5ef2aSThomas Huth /* cntlzw */ 2580fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2581fcf5ef2aSThomas Huth { 25829b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 25839b8514e5SRichard Henderson 25849b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 25859b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 25869b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 25879b8514e5SRichard Henderson tcg_temp_free_i32(t); 25889b8514e5SRichard Henderson 2589efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2590fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2591fcf5ef2aSThomas Huth } 2592efe843d8SDavid Gibson } 2593fcf5ef2aSThomas Huth 2594fcf5ef2aSThomas Huth /* cnttzw */ 2595fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2596fcf5ef2aSThomas Huth { 25979b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 25989b8514e5SRichard Henderson 25999b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 26009b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 26019b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 26029b8514e5SRichard Henderson tcg_temp_free_i32(t); 26039b8514e5SRichard Henderson 2604fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2605fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2606fcf5ef2aSThomas Huth } 2607fcf5ef2aSThomas Huth } 2608fcf5ef2aSThomas Huth 2609fcf5ef2aSThomas Huth /* eqv & eqv. */ 2610fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2611fcf5ef2aSThomas Huth /* extsb & extsb. */ 2612fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2613fcf5ef2aSThomas Huth /* extsh & extsh. */ 2614fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2615fcf5ef2aSThomas Huth /* nand & nand. */ 2616fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2617fcf5ef2aSThomas Huth /* nor & nor. */ 2618fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2619fcf5ef2aSThomas Huth 2620fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2621fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2622fcf5ef2aSThomas Huth { 2623fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2624fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2625fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2626fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2627fcf5ef2aSThomas Huth 2628fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2629b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2630fcf5ef2aSThomas Huth } 2631fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2632fcf5ef2aSThomas Huth 2633fcf5ef2aSThomas Huth /* or & or. */ 2634fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2635fcf5ef2aSThomas Huth { 2636fcf5ef2aSThomas Huth int rs, ra, rb; 2637fcf5ef2aSThomas Huth 2638fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2639fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2640fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2641fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2642fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2643efe843d8SDavid Gibson if (rs != rb) { 2644fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2645efe843d8SDavid Gibson } else { 2646fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2647efe843d8SDavid Gibson } 2648efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2649fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2650efe843d8SDavid Gibson } 2651fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2652fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2653fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2654fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2655fcf5ef2aSThomas Huth int prio = 0; 2656fcf5ef2aSThomas Huth 2657fcf5ef2aSThomas Huth switch (rs) { 2658fcf5ef2aSThomas Huth case 1: 2659fcf5ef2aSThomas Huth /* Set process priority to low */ 2660fcf5ef2aSThomas Huth prio = 2; 2661fcf5ef2aSThomas Huth break; 2662fcf5ef2aSThomas Huth case 6: 2663fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2664fcf5ef2aSThomas Huth prio = 3; 2665fcf5ef2aSThomas Huth break; 2666fcf5ef2aSThomas Huth case 2: 2667fcf5ef2aSThomas Huth /* Set process priority to normal */ 2668fcf5ef2aSThomas Huth prio = 4; 2669fcf5ef2aSThomas Huth break; 2670fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2671fcf5ef2aSThomas Huth case 31: 2672fcf5ef2aSThomas Huth if (!ctx->pr) { 2673fcf5ef2aSThomas Huth /* Set process priority to very low */ 2674fcf5ef2aSThomas Huth prio = 1; 2675fcf5ef2aSThomas Huth } 2676fcf5ef2aSThomas Huth break; 2677fcf5ef2aSThomas Huth case 5: 2678fcf5ef2aSThomas Huth if (!ctx->pr) { 2679fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2680fcf5ef2aSThomas Huth prio = 5; 2681fcf5ef2aSThomas Huth } 2682fcf5ef2aSThomas Huth break; 2683fcf5ef2aSThomas Huth case 3: 2684fcf5ef2aSThomas Huth if (!ctx->pr) { 2685fcf5ef2aSThomas Huth /* Set process priority to high */ 2686fcf5ef2aSThomas Huth prio = 6; 2687fcf5ef2aSThomas Huth } 2688fcf5ef2aSThomas Huth break; 2689fcf5ef2aSThomas Huth case 7: 2690fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2691fcf5ef2aSThomas Huth /* Set process priority to very high */ 2692fcf5ef2aSThomas Huth prio = 7; 2693fcf5ef2aSThomas Huth } 2694fcf5ef2aSThomas Huth break; 2695fcf5ef2aSThomas Huth #endif 2696fcf5ef2aSThomas Huth default: 2697fcf5ef2aSThomas Huth break; 2698fcf5ef2aSThomas Huth } 2699fcf5ef2aSThomas Huth if (prio) { 2700fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2701fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2702fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2703fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2704fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2705fcf5ef2aSThomas Huth tcg_temp_free(t0); 2706fcf5ef2aSThomas Huth } 2707fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2708efe843d8SDavid Gibson /* 2709efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2710efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2711efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2712efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2713fcf5ef2aSThomas Huth */ 2714fcf5ef2aSThomas Huth gen_pause(ctx); 2715fcf5ef2aSThomas Huth #endif 2716fcf5ef2aSThomas Huth #endif 2717fcf5ef2aSThomas Huth } 2718fcf5ef2aSThomas Huth } 2719fcf5ef2aSThomas Huth /* orc & orc. */ 2720fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2721fcf5ef2aSThomas Huth 2722fcf5ef2aSThomas Huth /* xor & xor. */ 2723fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2724fcf5ef2aSThomas Huth { 2725fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2726efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2727efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2728efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2729efe843d8SDavid Gibson } else { 2730fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2731efe843d8SDavid Gibson } 2732efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2733fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2734fcf5ef2aSThomas Huth } 2735efe843d8SDavid Gibson } 2736fcf5ef2aSThomas Huth 2737fcf5ef2aSThomas Huth /* ori */ 2738fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2739fcf5ef2aSThomas Huth { 2740fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2741fcf5ef2aSThomas Huth 2742fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2743fcf5ef2aSThomas Huth return; 2744fcf5ef2aSThomas Huth } 2745fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2746fcf5ef2aSThomas Huth } 2747fcf5ef2aSThomas Huth 2748fcf5ef2aSThomas Huth /* oris */ 2749fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2750fcf5ef2aSThomas Huth { 2751fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2752fcf5ef2aSThomas Huth 2753fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2754fcf5ef2aSThomas Huth /* NOP */ 2755fcf5ef2aSThomas Huth return; 2756fcf5ef2aSThomas Huth } 2757efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2758efe843d8SDavid Gibson uimm << 16); 2759fcf5ef2aSThomas Huth } 2760fcf5ef2aSThomas Huth 2761fcf5ef2aSThomas Huth /* xori */ 2762fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2763fcf5ef2aSThomas Huth { 2764fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2765fcf5ef2aSThomas Huth 2766fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2767fcf5ef2aSThomas Huth /* NOP */ 2768fcf5ef2aSThomas Huth return; 2769fcf5ef2aSThomas Huth } 2770fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2771fcf5ef2aSThomas Huth } 2772fcf5ef2aSThomas Huth 2773fcf5ef2aSThomas Huth /* xoris */ 2774fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2775fcf5ef2aSThomas Huth { 2776fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2777fcf5ef2aSThomas Huth 2778fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2779fcf5ef2aSThomas Huth /* NOP */ 2780fcf5ef2aSThomas Huth return; 2781fcf5ef2aSThomas Huth } 2782efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2783efe843d8SDavid Gibson uimm << 16); 2784fcf5ef2aSThomas Huth } 2785fcf5ef2aSThomas Huth 2786fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2787fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2788fcf5ef2aSThomas Huth { 2789fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2790fcf5ef2aSThomas Huth } 2791fcf5ef2aSThomas Huth 2792fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2793fcf5ef2aSThomas Huth { 279479770002SRichard Henderson #if defined(TARGET_PPC64) 2795fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 279679770002SRichard Henderson #else 279779770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 279879770002SRichard Henderson #endif 2799fcf5ef2aSThomas Huth } 2800fcf5ef2aSThomas Huth 2801fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2802fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2803fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2804fcf5ef2aSThomas Huth { 280579770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2806fcf5ef2aSThomas Huth } 2807fcf5ef2aSThomas Huth #endif 2808fcf5ef2aSThomas Huth 2809fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2810fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2811fcf5ef2aSThomas Huth { 2812fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2813fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2814fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2815fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2816fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2817fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2818fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2819fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2820fcf5ef2aSThomas Huth tcg_temp_free(t0); 2821fcf5ef2aSThomas Huth } 2822fcf5ef2aSThomas Huth 2823fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2824fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2825fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2826fcf5ef2aSThomas Huth { 2827fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2828fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2829fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2830fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2831fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2832fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2833fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2834fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2835fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2836fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2837fcf5ef2aSThomas Huth tcg_temp_free(t0); 2838fcf5ef2aSThomas Huth } 2839fcf5ef2aSThomas Huth #endif 2840fcf5ef2aSThomas Huth 2841fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2842fcf5ef2aSThomas Huth /* bpermd */ 2843fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2844fcf5ef2aSThomas Huth { 2845fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2846fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2847fcf5ef2aSThomas Huth } 2848fcf5ef2aSThomas Huth #endif 2849fcf5ef2aSThomas Huth 2850fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2851fcf5ef2aSThomas Huth /* extsw & extsw. */ 2852fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2853fcf5ef2aSThomas Huth 2854fcf5ef2aSThomas Huth /* cntlzd */ 2855fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2856fcf5ef2aSThomas Huth { 28579b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2858efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2859fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2860fcf5ef2aSThomas Huth } 2861efe843d8SDavid Gibson } 2862fcf5ef2aSThomas Huth 2863fcf5ef2aSThomas Huth /* cnttzd */ 2864fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2865fcf5ef2aSThomas Huth { 28669b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2867fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2868fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2869fcf5ef2aSThomas Huth } 2870fcf5ef2aSThomas Huth } 2871fcf5ef2aSThomas Huth 2872fcf5ef2aSThomas Huth /* darn */ 2873fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2874fcf5ef2aSThomas Huth { 2875fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2876fcf5ef2aSThomas Huth 28777e4357f6SRichard Henderson if (l > 2) { 28787e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 28797e4357f6SRichard Henderson } else { 28807e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28817e4357f6SRichard Henderson gen_io_start(); 28827e4357f6SRichard Henderson } 2883fcf5ef2aSThomas Huth if (l == 0) { 2884fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 28857e4357f6SRichard Henderson } else { 2886fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2887fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 28887e4357f6SRichard Henderson } 28897e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28907e4357f6SRichard Henderson gen_stop_exception(ctx); 28917e4357f6SRichard Henderson } 2892fcf5ef2aSThomas Huth } 2893fcf5ef2aSThomas Huth } 2894fcf5ef2aSThomas Huth #endif 2895fcf5ef2aSThomas Huth 2896fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2897fcf5ef2aSThomas Huth 2898fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2899fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2900fcf5ef2aSThomas Huth { 2901fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2902fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2903fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2904fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2905fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2906fcf5ef2aSThomas Huth 2907fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2908fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2909fcf5ef2aSThomas Huth } else { 2910fcf5ef2aSThomas Huth target_ulong mask; 2911c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2912fcf5ef2aSThomas Huth TCGv t1; 2913fcf5ef2aSThomas Huth 2914fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2915fcf5ef2aSThomas Huth mb += 32; 2916fcf5ef2aSThomas Huth me += 32; 2917fcf5ef2aSThomas Huth #endif 2918fcf5ef2aSThomas Huth mask = MASK(mb, me); 2919fcf5ef2aSThomas Huth 2920c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2921c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2922c4f6a4a3SDaniele Buono mask_in_32b = false; 2923c4f6a4a3SDaniele Buono } 2924c4f6a4a3SDaniele Buono #endif 2925fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2926c4f6a4a3SDaniele Buono if (mask_in_32b) { 2927fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2928fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2929fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2930fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2931fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2932fcf5ef2aSThomas Huth } else { 2933fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2934fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2935fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2936fcf5ef2aSThomas Huth #else 2937fcf5ef2aSThomas Huth g_assert_not_reached(); 2938fcf5ef2aSThomas Huth #endif 2939fcf5ef2aSThomas Huth } 2940fcf5ef2aSThomas Huth 2941fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2942fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2943fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2944fcf5ef2aSThomas Huth tcg_temp_free(t1); 2945fcf5ef2aSThomas Huth } 2946fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2947fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2948fcf5ef2aSThomas Huth } 2949fcf5ef2aSThomas Huth } 2950fcf5ef2aSThomas Huth 2951fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2952fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2953fcf5ef2aSThomas Huth { 2954fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2955fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 29567b4d326fSRichard Henderson int sh = SH(ctx->opcode); 29577b4d326fSRichard Henderson int mb = MB(ctx->opcode); 29587b4d326fSRichard Henderson int me = ME(ctx->opcode); 29597b4d326fSRichard Henderson int len = me - mb + 1; 29607b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2961fcf5ef2aSThomas Huth 29627b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 29637b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 29647b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 29657b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2966fcf5ef2aSThomas Huth } else { 2967fcf5ef2aSThomas Huth target_ulong mask; 2968c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2969fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2970fcf5ef2aSThomas Huth mb += 32; 2971fcf5ef2aSThomas Huth me += 32; 2972fcf5ef2aSThomas Huth #endif 2973fcf5ef2aSThomas Huth mask = MASK(mb, me); 2974c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2975c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2976c4f6a4a3SDaniele Buono mask_in_32b = false; 2977c4f6a4a3SDaniele Buono } 2978c4f6a4a3SDaniele Buono #endif 2979c4f6a4a3SDaniele Buono if (mask_in_32b) { 29807b4d326fSRichard Henderson if (sh == 0) { 29817b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 298294f040aaSVitaly Chikunov } else { 2983fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2984fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2985fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2986fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2987fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2988fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 298994f040aaSVitaly Chikunov } 2990fcf5ef2aSThomas Huth } else { 2991fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2992fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2993fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2994fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2995fcf5ef2aSThomas Huth #else 2996fcf5ef2aSThomas Huth g_assert_not_reached(); 2997fcf5ef2aSThomas Huth #endif 2998fcf5ef2aSThomas Huth } 2999fcf5ef2aSThomas Huth } 3000fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3001fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3002fcf5ef2aSThomas Huth } 3003fcf5ef2aSThomas Huth } 3004fcf5ef2aSThomas Huth 3005fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 3006fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 3007fcf5ef2aSThomas Huth { 3008fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3009fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3010fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3011fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 3012fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 3013fcf5ef2aSThomas Huth target_ulong mask; 3014c4f6a4a3SDaniele Buono bool mask_in_32b = true; 3015fcf5ef2aSThomas Huth 3016fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3017fcf5ef2aSThomas Huth mb += 32; 3018fcf5ef2aSThomas Huth me += 32; 3019fcf5ef2aSThomas Huth #endif 3020fcf5ef2aSThomas Huth mask = MASK(mb, me); 3021fcf5ef2aSThomas Huth 3022c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 3023c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 3024c4f6a4a3SDaniele Buono mask_in_32b = false; 3025c4f6a4a3SDaniele Buono } 3026c4f6a4a3SDaniele Buono #endif 3027c4f6a4a3SDaniele Buono if (mask_in_32b) { 3028fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3029fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3030fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 3031fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 3032fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 3033fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 3034fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 3035fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3036fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3037fcf5ef2aSThomas Huth } else { 3038fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3039fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 3040fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 3041fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 3042fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 3043fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 3044fcf5ef2aSThomas Huth #else 3045fcf5ef2aSThomas Huth g_assert_not_reached(); 3046fcf5ef2aSThomas Huth #endif 3047fcf5ef2aSThomas Huth } 3048fcf5ef2aSThomas Huth 3049fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 3050fcf5ef2aSThomas Huth 3051fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3052fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3053fcf5ef2aSThomas Huth } 3054fcf5ef2aSThomas Huth } 3055fcf5ef2aSThomas Huth 3056fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3057fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 3058fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3059fcf5ef2aSThomas Huth { \ 3060fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 3061fcf5ef2aSThomas Huth } \ 3062fcf5ef2aSThomas Huth \ 3063fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3064fcf5ef2aSThomas Huth { \ 3065fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 3066fcf5ef2aSThomas Huth } 3067fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 3068fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3069fcf5ef2aSThomas Huth { \ 3070fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 3071fcf5ef2aSThomas Huth } \ 3072fcf5ef2aSThomas Huth \ 3073fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3074fcf5ef2aSThomas Huth { \ 3075fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 3076fcf5ef2aSThomas Huth } \ 3077fcf5ef2aSThomas Huth \ 3078fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 3079fcf5ef2aSThomas Huth { \ 3080fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 3081fcf5ef2aSThomas Huth } \ 3082fcf5ef2aSThomas Huth \ 3083fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 3084fcf5ef2aSThomas Huth { \ 3085fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 3086fcf5ef2aSThomas Huth } 3087fcf5ef2aSThomas Huth 3088fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 3089fcf5ef2aSThomas Huth { 3090fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3091fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 30927b4d326fSRichard Henderson int len = me - mb + 1; 30937b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 3094fcf5ef2aSThomas Huth 30957b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 30967b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 30977b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 30987b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 3099fcf5ef2aSThomas Huth } else { 3100fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 3101fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3102fcf5ef2aSThomas Huth } 3103fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3104fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3105fcf5ef2aSThomas Huth } 3106fcf5ef2aSThomas Huth } 3107fcf5ef2aSThomas Huth 3108fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 3109fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 3110fcf5ef2aSThomas Huth { 3111fcf5ef2aSThomas Huth uint32_t sh, mb; 3112fcf5ef2aSThomas Huth 3113fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3114fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3115fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 3116fcf5ef2aSThomas Huth } 3117fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 3118fcf5ef2aSThomas Huth 3119fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 3120fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 3121fcf5ef2aSThomas Huth { 3122fcf5ef2aSThomas Huth uint32_t sh, me; 3123fcf5ef2aSThomas Huth 3124fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3125fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3126fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 3127fcf5ef2aSThomas Huth } 3128fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 3129fcf5ef2aSThomas Huth 3130fcf5ef2aSThomas Huth /* rldic - rldic. */ 3131fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 3132fcf5ef2aSThomas Huth { 3133fcf5ef2aSThomas Huth uint32_t sh, mb; 3134fcf5ef2aSThomas Huth 3135fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3136fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3137fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 3138fcf5ef2aSThomas Huth } 3139fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 3140fcf5ef2aSThomas Huth 3141fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 3142fcf5ef2aSThomas Huth { 3143fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3144fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3145fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3146fcf5ef2aSThomas Huth TCGv t0; 3147fcf5ef2aSThomas Huth 3148fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3149fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 3150fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 3151fcf5ef2aSThomas Huth tcg_temp_free(t0); 3152fcf5ef2aSThomas Huth 3153fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3154fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3155fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3156fcf5ef2aSThomas Huth } 3157fcf5ef2aSThomas Huth } 3158fcf5ef2aSThomas Huth 3159fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 3160fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 3161fcf5ef2aSThomas Huth { 3162fcf5ef2aSThomas Huth uint32_t mb; 3163fcf5ef2aSThomas Huth 3164fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3165fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 3166fcf5ef2aSThomas Huth } 3167fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 3168fcf5ef2aSThomas Huth 3169fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 3170fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 3171fcf5ef2aSThomas Huth { 3172fcf5ef2aSThomas Huth uint32_t me; 3173fcf5ef2aSThomas Huth 3174fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3175fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 3176fcf5ef2aSThomas Huth } 3177fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 3178fcf5ef2aSThomas Huth 3179fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 3180fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 3181fcf5ef2aSThomas Huth { 3182fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3183fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3184fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 3185fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 3186fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 3187fcf5ef2aSThomas Huth 3188fcf5ef2aSThomas Huth if (mb <= me) { 3189fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 3190fcf5ef2aSThomas Huth } else { 3191fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 3192fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3193fcf5ef2aSThomas Huth 3194fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 3195fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 3196fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 3197fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 3198fcf5ef2aSThomas Huth tcg_temp_free(t1); 3199fcf5ef2aSThomas Huth } 3200fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3201fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3202fcf5ef2aSThomas Huth } 3203fcf5ef2aSThomas Huth } 3204fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 3205fcf5ef2aSThomas Huth #endif 3206fcf5ef2aSThomas Huth 3207fcf5ef2aSThomas Huth /*** Integer shift ***/ 3208fcf5ef2aSThomas Huth 3209fcf5ef2aSThomas Huth /* slw & slw. */ 3210fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 3211fcf5ef2aSThomas Huth { 3212fcf5ef2aSThomas Huth TCGv t0, t1; 3213fcf5ef2aSThomas Huth 3214fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3215fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3216fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3217fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3218fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3219fcf5ef2aSThomas Huth #else 3220fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3221fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3222fcf5ef2aSThomas Huth #endif 3223fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3224fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3225fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3226fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3227fcf5ef2aSThomas Huth tcg_temp_free(t1); 3228fcf5ef2aSThomas Huth tcg_temp_free(t0); 3229fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 3230efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3231fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3232fcf5ef2aSThomas Huth } 3233efe843d8SDavid Gibson } 3234fcf5ef2aSThomas Huth 3235fcf5ef2aSThomas Huth /* sraw & sraw. */ 3236fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3237fcf5ef2aSThomas Huth { 3238fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3239fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3240efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3241fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3242fcf5ef2aSThomas Huth } 3243efe843d8SDavid Gibson } 3244fcf5ef2aSThomas Huth 3245fcf5ef2aSThomas Huth /* srawi & srawi. */ 3246fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3247fcf5ef2aSThomas Huth { 3248fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3249fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3250fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3251fcf5ef2aSThomas Huth if (sh == 0) { 3252fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3253fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3254af1c259fSSandipan Das if (is_isa300(ctx)) { 3255af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3256af1c259fSSandipan Das } 3257fcf5ef2aSThomas Huth } else { 3258fcf5ef2aSThomas Huth TCGv t0; 3259fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3260fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3261fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3262fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3263fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3264fcf5ef2aSThomas Huth tcg_temp_free(t0); 3265fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3266af1c259fSSandipan Das if (is_isa300(ctx)) { 3267af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3268af1c259fSSandipan Das } 3269fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3270fcf5ef2aSThomas Huth } 3271fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3272fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3273fcf5ef2aSThomas Huth } 3274fcf5ef2aSThomas Huth } 3275fcf5ef2aSThomas Huth 3276fcf5ef2aSThomas Huth /* srw & srw. */ 3277fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3278fcf5ef2aSThomas Huth { 3279fcf5ef2aSThomas Huth TCGv t0, t1; 3280fcf5ef2aSThomas Huth 3281fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3282fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3283fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3284fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3285fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3286fcf5ef2aSThomas Huth #else 3287fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3288fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3289fcf5ef2aSThomas Huth #endif 3290fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3291fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3292fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3293fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3294fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3295fcf5ef2aSThomas Huth tcg_temp_free(t1); 3296fcf5ef2aSThomas Huth tcg_temp_free(t0); 3297efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3298fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3299fcf5ef2aSThomas Huth } 3300efe843d8SDavid Gibson } 3301fcf5ef2aSThomas Huth 3302fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3303fcf5ef2aSThomas Huth /* sld & sld. */ 3304fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3305fcf5ef2aSThomas Huth { 3306fcf5ef2aSThomas Huth TCGv t0, t1; 3307fcf5ef2aSThomas Huth 3308fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3309fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3310fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3311fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3312fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3313fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3314fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3315fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3316fcf5ef2aSThomas Huth tcg_temp_free(t1); 3317fcf5ef2aSThomas Huth tcg_temp_free(t0); 3318efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3319fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3320fcf5ef2aSThomas Huth } 3321efe843d8SDavid Gibson } 3322fcf5ef2aSThomas Huth 3323fcf5ef2aSThomas Huth /* srad & srad. */ 3324fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3325fcf5ef2aSThomas Huth { 3326fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3327fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3328efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3329fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3330fcf5ef2aSThomas Huth } 3331efe843d8SDavid Gibson } 3332fcf5ef2aSThomas Huth /* sradi & sradi. */ 3333fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3334fcf5ef2aSThomas Huth { 3335fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3336fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3337fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3338fcf5ef2aSThomas Huth if (sh == 0) { 3339fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3340fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3341af1c259fSSandipan Das if (is_isa300(ctx)) { 3342af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3343af1c259fSSandipan Das } 3344fcf5ef2aSThomas Huth } else { 3345fcf5ef2aSThomas Huth TCGv t0; 3346fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3347fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3348fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3349fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3350fcf5ef2aSThomas Huth tcg_temp_free(t0); 3351fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3352af1c259fSSandipan Das if (is_isa300(ctx)) { 3353af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3354af1c259fSSandipan Das } 3355fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3356fcf5ef2aSThomas Huth } 3357fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3358fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3359fcf5ef2aSThomas Huth } 3360fcf5ef2aSThomas Huth } 3361fcf5ef2aSThomas Huth 3362fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3363fcf5ef2aSThomas Huth { 3364fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3365fcf5ef2aSThomas Huth } 3366fcf5ef2aSThomas Huth 3367fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3368fcf5ef2aSThomas Huth { 3369fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3370fcf5ef2aSThomas Huth } 3371fcf5ef2aSThomas Huth 3372fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3373fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3374fcf5ef2aSThomas Huth { 3375fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3376fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3377fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3378fcf5ef2aSThomas Huth 3379fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3380fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3381fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3382fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3383fcf5ef2aSThomas Huth } 3384fcf5ef2aSThomas Huth } 3385fcf5ef2aSThomas Huth 3386fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3387fcf5ef2aSThomas Huth { 3388fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3389fcf5ef2aSThomas Huth } 3390fcf5ef2aSThomas Huth 3391fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3392fcf5ef2aSThomas Huth { 3393fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3394fcf5ef2aSThomas Huth } 3395fcf5ef2aSThomas Huth 3396fcf5ef2aSThomas Huth /* srd & srd. */ 3397fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3398fcf5ef2aSThomas Huth { 3399fcf5ef2aSThomas Huth TCGv t0, t1; 3400fcf5ef2aSThomas Huth 3401fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3402fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3403fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3404fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3405fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3406fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3407fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3408fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3409fcf5ef2aSThomas Huth tcg_temp_free(t1); 3410fcf5ef2aSThomas Huth tcg_temp_free(t0); 3411efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3412fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3413fcf5ef2aSThomas Huth } 3414efe843d8SDavid Gibson } 3415fcf5ef2aSThomas Huth #endif 3416fcf5ef2aSThomas Huth 3417fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3418fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3419fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3420fcf5ef2aSThomas Huth target_long maskl) 3421fcf5ef2aSThomas Huth { 3422fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3423fcf5ef2aSThomas Huth 3424fcf5ef2aSThomas Huth simm &= ~maskl; 3425fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3426fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3427fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3428fcf5ef2aSThomas Huth } 3429fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3430fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3431fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3432fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3433fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3434fcf5ef2aSThomas Huth } 3435fcf5ef2aSThomas Huth } else { 3436fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3437fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3438fcf5ef2aSThomas Huth } else { 3439fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3440fcf5ef2aSThomas Huth } 3441fcf5ef2aSThomas Huth } 3442fcf5ef2aSThomas Huth } 3443fcf5ef2aSThomas Huth 3444fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3445fcf5ef2aSThomas Huth { 3446fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3447fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3448fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3449fcf5ef2aSThomas Huth } else { 3450fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3451fcf5ef2aSThomas Huth } 3452fcf5ef2aSThomas Huth } else { 3453fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3454fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3455fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3456fcf5ef2aSThomas Huth } 3457fcf5ef2aSThomas Huth } 3458fcf5ef2aSThomas Huth } 3459fcf5ef2aSThomas Huth 3460fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3461fcf5ef2aSThomas Huth { 3462fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3463fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3464fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3465fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3466fcf5ef2aSThomas Huth } else { 3467fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3468fcf5ef2aSThomas Huth } 3469fcf5ef2aSThomas Huth } 3470fcf5ef2aSThomas Huth 3471fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3472fcf5ef2aSThomas Huth target_long val) 3473fcf5ef2aSThomas Huth { 3474fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3475fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3476fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3477fcf5ef2aSThomas Huth } 3478fcf5ef2aSThomas Huth } 3479fcf5ef2aSThomas Huth 3480fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3481fcf5ef2aSThomas Huth { 3482fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3483fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3484fcf5ef2aSThomas Huth } 3485fcf5ef2aSThomas Huth 3486fcf5ef2aSThomas Huth /*** Integer load ***/ 3487fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3488fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3489fcf5ef2aSThomas Huth 3490fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3491fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3492fcf5ef2aSThomas Huth TCGv val, \ 3493fcf5ef2aSThomas Huth TCGv addr) \ 3494fcf5ef2aSThomas Huth { \ 3495fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3496fcf5ef2aSThomas Huth } 3497fcf5ef2aSThomas Huth 3498fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3499fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3500fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3501fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3502fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3503fcf5ef2aSThomas Huth 3504fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3505fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3506fcf5ef2aSThomas Huth 3507fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3508fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3509fcf5ef2aSThomas Huth TCGv_i64 val, \ 3510fcf5ef2aSThomas Huth TCGv addr) \ 3511fcf5ef2aSThomas Huth { \ 3512fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3513fcf5ef2aSThomas Huth } 3514fcf5ef2aSThomas Huth 3515fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3516fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3517fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3518fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3519fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3520fcf5ef2aSThomas Huth 3521fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3522fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3523fcf5ef2aSThomas Huth #endif 3524fcf5ef2aSThomas Huth 3525fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3526fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3527fcf5ef2aSThomas Huth TCGv val, \ 3528fcf5ef2aSThomas Huth TCGv addr) \ 3529fcf5ef2aSThomas Huth { \ 3530fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3531fcf5ef2aSThomas Huth } 3532fcf5ef2aSThomas Huth 3533fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3534fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3535fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3536fcf5ef2aSThomas Huth 3537fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3538fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3539fcf5ef2aSThomas Huth 3540fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3541fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3542fcf5ef2aSThomas Huth TCGv_i64 val, \ 3543fcf5ef2aSThomas Huth TCGv addr) \ 3544fcf5ef2aSThomas Huth { \ 3545fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3546fcf5ef2aSThomas Huth } 3547fcf5ef2aSThomas Huth 3548fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3549fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3550fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3551fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3552fcf5ef2aSThomas Huth 3553fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3554fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3555fcf5ef2aSThomas Huth #endif 3556fcf5ef2aSThomas Huth 3557fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 3558fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3559fcf5ef2aSThomas Huth { \ 3560fcf5ef2aSThomas Huth TCGv EA; \ 3561fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3562fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3563fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3564fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3565fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3566fcf5ef2aSThomas Huth } 3567fcf5ef2aSThomas Huth 3568fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 3569fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 3570fcf5ef2aSThomas Huth { \ 3571fcf5ef2aSThomas Huth TCGv EA; \ 3572fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3573fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3574fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3575fcf5ef2aSThomas Huth return; \ 3576fcf5ef2aSThomas Huth } \ 3577fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3578fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3579fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3580fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3581fcf5ef2aSThomas Huth else \ 3582fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3583fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3584fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3585fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3586fcf5ef2aSThomas Huth } 3587fcf5ef2aSThomas Huth 3588fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 3589fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3590fcf5ef2aSThomas Huth { \ 3591fcf5ef2aSThomas Huth TCGv EA; \ 3592fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3593fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3594fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3595fcf5ef2aSThomas Huth return; \ 3596fcf5ef2aSThomas Huth } \ 3597fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3598fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3599fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3600fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3601fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3602fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3603fcf5ef2aSThomas Huth } 3604fcf5ef2aSThomas Huth 3605fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3606fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3607fcf5ef2aSThomas Huth { \ 3608fcf5ef2aSThomas Huth TCGv EA; \ 3609fcf5ef2aSThomas Huth chk; \ 3610fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3611fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3612fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3613fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3614fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3615fcf5ef2aSThomas Huth } 3616fcf5ef2aSThomas Huth 3617fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3618fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3619fcf5ef2aSThomas Huth 3620fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3621fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3622fcf5ef2aSThomas Huth 3623fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 3624fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 3625fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 3626fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 3627fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 3628fcf5ef2aSThomas Huth 3629fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 3630fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 3631fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 3632fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 3633fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 3634fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 3635fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 3636fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 363750728199SRoman Kapl 363850728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 363950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 364050728199SRoman Kapl { \ 364150728199SRoman Kapl TCGv EA; \ 364250728199SRoman Kapl CHK_SV; \ 364350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 364450728199SRoman Kapl EA = tcg_temp_new(); \ 364550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 364650728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 364750728199SRoman Kapl tcg_temp_free(EA); \ 364850728199SRoman Kapl } 364950728199SRoman Kapl 365050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 365150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 365250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 365350728199SRoman Kapl #if defined(TARGET_PPC64) 365450728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 365550728199SRoman Kapl #endif 365650728199SRoman Kapl 3657fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3658fcf5ef2aSThomas Huth /* lwaux */ 3659fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 3660fcf5ef2aSThomas Huth /* lwax */ 3661fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 3662fcf5ef2aSThomas Huth /* ldux */ 3663fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 3664fcf5ef2aSThomas Huth /* ldx */ 3665fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 3666fcf5ef2aSThomas Huth 3667fcf5ef2aSThomas Huth /* CI load/store variants */ 3668fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3669fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3670fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3671fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3672fcf5ef2aSThomas Huth 3673fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 3674fcf5ef2aSThomas Huth { 3675fcf5ef2aSThomas Huth TCGv EA; 3676fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3677fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 3678fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 3679fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3680fcf5ef2aSThomas Huth return; 3681fcf5ef2aSThomas Huth } 3682fcf5ef2aSThomas Huth } 3683fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3684fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3685fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3686fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 3687fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 3688fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3689fcf5ef2aSThomas Huth } else { 3690fcf5ef2aSThomas Huth /* ld - ldu */ 3691fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3692fcf5ef2aSThomas Huth } 3693efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3694fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3695efe843d8SDavid Gibson } 3696fcf5ef2aSThomas Huth tcg_temp_free(EA); 3697fcf5ef2aSThomas Huth } 3698fcf5ef2aSThomas Huth 3699fcf5ef2aSThomas Huth /* lq */ 3700fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3701fcf5ef2aSThomas Huth { 3702fcf5ef2aSThomas Huth int ra, rd; 370394bf2658SRichard Henderson TCGv EA, hi, lo; 3704fcf5ef2aSThomas Huth 3705fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3706fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3707fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3708fcf5ef2aSThomas Huth 3709fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3710fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3711fcf5ef2aSThomas Huth return; 3712fcf5ef2aSThomas Huth } 3713fcf5ef2aSThomas Huth 3714fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3715fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3716fcf5ef2aSThomas Huth return; 3717fcf5ef2aSThomas Huth } 3718fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3719fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3720fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3721fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3722fcf5ef2aSThomas Huth return; 3723fcf5ef2aSThomas Huth } 3724fcf5ef2aSThomas Huth 3725fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3726fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3727fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3728fcf5ef2aSThomas Huth 372994bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 373094bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 373194bf2658SRichard Henderson hi = cpu_gpr[rd]; 373294bf2658SRichard Henderson 373394bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3734f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 373594bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 373694bf2658SRichard Henderson if (ctx->le_mode) { 373794bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 373894bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3739fcf5ef2aSThomas Huth } else { 374094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 374194bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 374294bf2658SRichard Henderson } 374394bf2658SRichard Henderson tcg_temp_free_i32(oi); 374494bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3745f34ec0f6SRichard Henderson } else { 374694bf2658SRichard Henderson /* Restart with exclusive lock. */ 374794bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 374894bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3749f34ec0f6SRichard Henderson } 375094bf2658SRichard Henderson } else if (ctx->le_mode) { 375194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3752fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 375394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 375494bf2658SRichard Henderson } else { 375594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 375694bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 375794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3758fcf5ef2aSThomas Huth } 3759fcf5ef2aSThomas Huth tcg_temp_free(EA); 3760fcf5ef2aSThomas Huth } 3761fcf5ef2aSThomas Huth #endif 3762fcf5ef2aSThomas Huth 3763fcf5ef2aSThomas Huth /*** Integer store ***/ 3764fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3765fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3766fcf5ef2aSThomas Huth { \ 3767fcf5ef2aSThomas Huth TCGv EA; \ 3768fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3769fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3770fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3771fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3772fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3773fcf5ef2aSThomas Huth } 3774fcf5ef2aSThomas Huth 3775fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3776fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3777fcf5ef2aSThomas Huth { \ 3778fcf5ef2aSThomas Huth TCGv EA; \ 3779fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3780fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3781fcf5ef2aSThomas Huth return; \ 3782fcf5ef2aSThomas Huth } \ 3783fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3784fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3785fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3786fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3787fcf5ef2aSThomas Huth else \ 3788fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3789fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3790fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3791fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3792fcf5ef2aSThomas Huth } 3793fcf5ef2aSThomas Huth 3794fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3795fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3796fcf5ef2aSThomas Huth { \ 3797fcf5ef2aSThomas Huth TCGv EA; \ 3798fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3799fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3800fcf5ef2aSThomas Huth return; \ 3801fcf5ef2aSThomas Huth } \ 3802fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3803fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3804fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3805fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3806fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3807fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3808fcf5ef2aSThomas Huth } 3809fcf5ef2aSThomas Huth 3810fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3811fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3812fcf5ef2aSThomas Huth { \ 3813fcf5ef2aSThomas Huth TCGv EA; \ 3814fcf5ef2aSThomas Huth chk; \ 3815fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3816fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3817fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3818fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3819fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3820fcf5ef2aSThomas Huth } 3821fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3822fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3823fcf5ef2aSThomas Huth 3824fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3825fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3826fcf5ef2aSThomas Huth 3827fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3828fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3829fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3830fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3831fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3832fcf5ef2aSThomas Huth 3833fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3834fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3835fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3836fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3837fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3838fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 383950728199SRoman Kapl 384050728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 384150728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 384250728199SRoman Kapl { \ 384350728199SRoman Kapl TCGv EA; \ 384450728199SRoman Kapl CHK_SV; \ 384550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 384650728199SRoman Kapl EA = tcg_temp_new(); \ 384750728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 384850728199SRoman Kapl tcg_gen_qemu_st_tl( \ 384950728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 385050728199SRoman Kapl tcg_temp_free(EA); \ 385150728199SRoman Kapl } 385250728199SRoman Kapl 385350728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 385450728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 385550728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 385650728199SRoman Kapl #if defined(TARGET_PPC64) 385750728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 385850728199SRoman Kapl #endif 385950728199SRoman Kapl 3860fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3861fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3862fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3863fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3864fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3865fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3866fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3867fcf5ef2aSThomas Huth 3868fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3869fcf5ef2aSThomas Huth { 3870fcf5ef2aSThomas Huth int rs; 3871fcf5ef2aSThomas Huth TCGv EA; 3872fcf5ef2aSThomas Huth 3873fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3874fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3875fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3876fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3877f89ced5fSRichard Henderson TCGv hi, lo; 3878fcf5ef2aSThomas Huth 3879fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3880fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3881fcf5ef2aSThomas Huth } 3882fcf5ef2aSThomas Huth 3883fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3884fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3885fcf5ef2aSThomas Huth return; 3886fcf5ef2aSThomas Huth } 3887fcf5ef2aSThomas Huth 3888fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3889fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3890fcf5ef2aSThomas Huth return; 3891fcf5ef2aSThomas Huth } 3892fcf5ef2aSThomas Huth 3893fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3894fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3895fcf5ef2aSThomas Huth return; 3896fcf5ef2aSThomas Huth } 3897fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3898fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3899fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3900fcf5ef2aSThomas Huth 3901f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3902f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3903f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3904f89ced5fSRichard Henderson 3905f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3906f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3907f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3908f89ced5fSRichard Henderson if (ctx->le_mode) { 3909f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3910f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3911fcf5ef2aSThomas Huth } else { 3912f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3913f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3914f89ced5fSRichard Henderson } 3915f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3916f34ec0f6SRichard Henderson } else { 3917f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3918f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3919f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3920f34ec0f6SRichard Henderson } 3921f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3922f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3923fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3924f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3925f89ced5fSRichard Henderson } else { 3926f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3927f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3928f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3929fcf5ef2aSThomas Huth } 3930fcf5ef2aSThomas Huth tcg_temp_free(EA); 3931fcf5ef2aSThomas Huth } else { 3932fcf5ef2aSThomas Huth /* std / stdu */ 3933fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3934fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3935fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3936fcf5ef2aSThomas Huth return; 3937fcf5ef2aSThomas Huth } 3938fcf5ef2aSThomas Huth } 3939fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3940fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3941fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3942fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3943efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3944fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3945efe843d8SDavid Gibson } 3946fcf5ef2aSThomas Huth tcg_temp_free(EA); 3947fcf5ef2aSThomas Huth } 3948fcf5ef2aSThomas Huth } 3949fcf5ef2aSThomas Huth #endif 3950fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3951fcf5ef2aSThomas Huth 3952fcf5ef2aSThomas Huth /* lhbrx */ 3953fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3954fcf5ef2aSThomas Huth 3955fcf5ef2aSThomas Huth /* lwbrx */ 3956fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3957fcf5ef2aSThomas Huth 3958fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3959fcf5ef2aSThomas Huth /* ldbrx */ 3960fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3961fcf5ef2aSThomas Huth /* stdbrx */ 3962fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3963fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3964fcf5ef2aSThomas Huth 3965fcf5ef2aSThomas Huth /* sthbrx */ 3966fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3967fcf5ef2aSThomas Huth /* stwbrx */ 3968fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3969fcf5ef2aSThomas Huth 3970fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3971fcf5ef2aSThomas Huth 3972fcf5ef2aSThomas Huth /* lmw */ 3973fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3974fcf5ef2aSThomas Huth { 3975fcf5ef2aSThomas Huth TCGv t0; 3976fcf5ef2aSThomas Huth TCGv_i32 t1; 3977fcf5ef2aSThomas Huth 3978fcf5ef2aSThomas Huth if (ctx->le_mode) { 3979fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3980fcf5ef2aSThomas Huth return; 3981fcf5ef2aSThomas Huth } 3982fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3983fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3984fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3985fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3986fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3987fcf5ef2aSThomas Huth tcg_temp_free(t0); 3988fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3989fcf5ef2aSThomas Huth } 3990fcf5ef2aSThomas Huth 3991fcf5ef2aSThomas Huth /* stmw */ 3992fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3993fcf5ef2aSThomas Huth { 3994fcf5ef2aSThomas Huth TCGv t0; 3995fcf5ef2aSThomas Huth TCGv_i32 t1; 3996fcf5ef2aSThomas Huth 3997fcf5ef2aSThomas Huth if (ctx->le_mode) { 3998fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3999fcf5ef2aSThomas Huth return; 4000fcf5ef2aSThomas Huth } 4001fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4002fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4003fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 4004fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 4005fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 4006fcf5ef2aSThomas Huth tcg_temp_free(t0); 4007fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4008fcf5ef2aSThomas Huth } 4009fcf5ef2aSThomas Huth 4010fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 4011fcf5ef2aSThomas Huth 4012fcf5ef2aSThomas Huth /* lswi */ 4013efe843d8SDavid Gibson /* 4014efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 4015efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 4016efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 4017efe843d8SDavid Gibson * spec... 4018fcf5ef2aSThomas Huth */ 4019fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 4020fcf5ef2aSThomas Huth { 4021fcf5ef2aSThomas Huth TCGv t0; 4022fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4023fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4024fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 4025fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 4026fcf5ef2aSThomas Huth int nr; 4027fcf5ef2aSThomas Huth 4028fcf5ef2aSThomas Huth if (ctx->le_mode) { 4029fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4030fcf5ef2aSThomas Huth return; 4031fcf5ef2aSThomas Huth } 4032efe843d8SDavid Gibson if (nb == 0) { 4033fcf5ef2aSThomas Huth nb = 32; 4034efe843d8SDavid Gibson } 4035f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 4036fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 4037fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 4038fcf5ef2aSThomas Huth return; 4039fcf5ef2aSThomas Huth } 4040fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4041fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4042fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4043fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4044fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 4045fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 4046fcf5ef2aSThomas Huth tcg_temp_free(t0); 4047fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4048fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4049fcf5ef2aSThomas Huth } 4050fcf5ef2aSThomas Huth 4051fcf5ef2aSThomas Huth /* lswx */ 4052fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 4053fcf5ef2aSThomas Huth { 4054fcf5ef2aSThomas Huth TCGv t0; 4055fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 4056fcf5ef2aSThomas Huth 4057fcf5ef2aSThomas Huth if (ctx->le_mode) { 4058fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4059fcf5ef2aSThomas Huth return; 4060fcf5ef2aSThomas Huth } 4061fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4062fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4063fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4064fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 4065fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 4066fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 4067fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 4068fcf5ef2aSThomas Huth tcg_temp_free(t0); 4069fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4070fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4071fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4072fcf5ef2aSThomas Huth } 4073fcf5ef2aSThomas Huth 4074fcf5ef2aSThomas Huth /* stswi */ 4075fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 4076fcf5ef2aSThomas Huth { 4077fcf5ef2aSThomas Huth TCGv t0; 4078fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4079fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4080fcf5ef2aSThomas Huth 4081fcf5ef2aSThomas Huth if (ctx->le_mode) { 4082fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4083fcf5ef2aSThomas Huth return; 4084fcf5ef2aSThomas Huth } 4085fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4086fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4087fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4088efe843d8SDavid Gibson if (nb == 0) { 4089fcf5ef2aSThomas Huth nb = 32; 4090efe843d8SDavid Gibson } 4091fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4092fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4093fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4094fcf5ef2aSThomas Huth tcg_temp_free(t0); 4095fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4096fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4097fcf5ef2aSThomas Huth } 4098fcf5ef2aSThomas Huth 4099fcf5ef2aSThomas Huth /* stswx */ 4100fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 4101fcf5ef2aSThomas Huth { 4102fcf5ef2aSThomas Huth TCGv t0; 4103fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4104fcf5ef2aSThomas Huth 4105fcf5ef2aSThomas Huth if (ctx->le_mode) { 4106fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4107fcf5ef2aSThomas Huth return; 4108fcf5ef2aSThomas Huth } 4109fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4110fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4111fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4112fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4113fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 4114fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 4115fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4116fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4117fcf5ef2aSThomas Huth tcg_temp_free(t0); 4118fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4119fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4120fcf5ef2aSThomas Huth } 4121fcf5ef2aSThomas Huth 4122fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 4123fcf5ef2aSThomas Huth /* eieio */ 4124fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 4125fcf5ef2aSThomas Huth { 4126c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 4127c8fd8373SCédric Le Goater 4128c8fd8373SCédric Le Goater /* 4129c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 4130c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 4131c8fd8373SCédric Le Goater */ 4132c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 4133c8fd8373SCédric Le Goater /* 4134c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 4135c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 4136c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 4137c8fd8373SCédric Le Goater * complain to the user. 4138c8fd8373SCédric Le Goater */ 4139c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 4140c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 4141*2c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 4142c8fd8373SCédric Le Goater } else { 4143c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 4144c8fd8373SCédric Le Goater } 4145c8fd8373SCédric Le Goater } 4146c8fd8373SCédric Le Goater 4147c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 4148fcf5ef2aSThomas Huth } 4149fcf5ef2aSThomas Huth 4150fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4151fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 4152fcf5ef2aSThomas Huth { 4153fcf5ef2aSThomas Huth TCGv_i32 t; 4154fcf5ef2aSThomas Huth TCGLabel *l; 4155fcf5ef2aSThomas Huth 4156fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 4157fcf5ef2aSThomas Huth return; 4158fcf5ef2aSThomas Huth } 4159fcf5ef2aSThomas Huth l = gen_new_label(); 4160fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 4161fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4162fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 4163fcf5ef2aSThomas Huth if (global) { 4164fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 4165fcf5ef2aSThomas Huth } else { 4166fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 4167fcf5ef2aSThomas Huth } 4168fcf5ef2aSThomas Huth gen_set_label(l); 4169fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4170fcf5ef2aSThomas Huth } 4171fcf5ef2aSThomas Huth #else 4172fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 4173fcf5ef2aSThomas Huth #endif 4174fcf5ef2aSThomas Huth 4175fcf5ef2aSThomas Huth /* isync */ 4176fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 4177fcf5ef2aSThomas Huth { 4178fcf5ef2aSThomas Huth /* 4179fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 4180fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 4181fcf5ef2aSThomas Huth */ 4182fcf5ef2aSThomas Huth if (!ctx->pr) { 4183fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 4184fcf5ef2aSThomas Huth } 41854771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4186fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4187fcf5ef2aSThomas Huth } 4188fcf5ef2aSThomas Huth 4189fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 4190fcf5ef2aSThomas Huth 419114776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 41922a4e6c1bSRichard Henderson { 41932a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 41942a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 41952a4e6c1bSRichard Henderson 41962a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 41972a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 41982a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 41992a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 42002a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 42012a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 42022a4e6c1bSRichard Henderson tcg_temp_free(t0); 42032a4e6c1bSRichard Henderson } 42042a4e6c1bSRichard Henderson 4205fcf5ef2aSThomas Huth #define LARX(name, memop) \ 4206fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4207fcf5ef2aSThomas Huth { \ 42082a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 4209fcf5ef2aSThomas Huth } 4210fcf5ef2aSThomas Huth 4211fcf5ef2aSThomas Huth /* lwarx */ 4212fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 4213fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 4214fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 4215fcf5ef2aSThomas Huth 421614776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 421720923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 421820923c1dSRichard Henderson { 421920923c1dSRichard Henderson TCGv t = tcg_temp_new(); 422020923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 422120923c1dSRichard Henderson TCGv u = tcg_temp_new(); 422220923c1dSRichard Henderson 422320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 422420923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 422520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 422620923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 422720923c1dSRichard Henderson 422820923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 422920923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 423020923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 423120923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 423220923c1dSRichard Henderson 423320923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 423420923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 423520923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 423620923c1dSRichard Henderson 423720923c1dSRichard Henderson tcg_temp_free(t); 423820923c1dSRichard Henderson tcg_temp_free(t2); 423920923c1dSRichard Henderson tcg_temp_free(u); 424020923c1dSRichard Henderson } 424120923c1dSRichard Henderson 424214776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 424320ba8504SRichard Henderson { 424420ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 424520ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 424620923c1dSRichard Henderson int rt = rD(ctx->opcode); 424720923c1dSRichard Henderson bool need_serial; 424820ba8504SRichard Henderson TCGv src, dst; 424920ba8504SRichard Henderson 425020ba8504SRichard Henderson gen_addr_register(ctx, EA); 425120923c1dSRichard Henderson dst = cpu_gpr[rt]; 425220923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 425320ba8504SRichard Henderson 425420923c1dSRichard Henderson need_serial = false; 425520ba8504SRichard Henderson memop |= MO_ALIGN; 425620ba8504SRichard Henderson switch (gpr_FC) { 425720ba8504SRichard Henderson case 0: /* Fetch and add */ 425820ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 425920ba8504SRichard Henderson break; 426020ba8504SRichard Henderson case 1: /* Fetch and xor */ 426120ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 426220ba8504SRichard Henderson break; 426320ba8504SRichard Henderson case 2: /* Fetch and or */ 426420ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 426520ba8504SRichard Henderson break; 426620ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 426720ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 426820ba8504SRichard Henderson break; 4269b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 4270b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 4271b8ce0f86SRichard Henderson break; 4272b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 4273b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 4274b8ce0f86SRichard Henderson break; 4275b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 4276b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 4277b8ce0f86SRichard Henderson break; 4278b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 4279b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 4280b8ce0f86SRichard Henderson break; 428120ba8504SRichard Henderson case 8: /* Swap */ 428220ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 428320ba8504SRichard Henderson break; 428420923c1dSRichard Henderson 428520923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 428620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 428720923c1dSRichard Henderson need_serial = true; 428820923c1dSRichard Henderson } else { 428920923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 429020923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 429120923c1dSRichard Henderson 429220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 429320923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 429420923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 429520923c1dSRichard Henderson } else { 429620923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 429720923c1dSRichard Henderson } 429820923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 429920923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 430020923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 430120923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 430220923c1dSRichard Henderson 430320923c1dSRichard Henderson tcg_temp_free(t0); 430420923c1dSRichard Henderson tcg_temp_free(t1); 430520923c1dSRichard Henderson } 430620ba8504SRichard Henderson break; 430720923c1dSRichard Henderson 430820923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 430920923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 431020923c1dSRichard Henderson need_serial = true; 431120923c1dSRichard Henderson } else { 431220923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 431320923c1dSRichard Henderson } 431420923c1dSRichard Henderson break; 431520923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 431620923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 431720923c1dSRichard Henderson need_serial = true; 431820923c1dSRichard Henderson } else { 431920923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 432020923c1dSRichard Henderson } 432120923c1dSRichard Henderson break; 432220923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 432320923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 432420923c1dSRichard Henderson need_serial = true; 432520923c1dSRichard Henderson } else { 432620923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 432720923c1dSRichard Henderson } 432820923c1dSRichard Henderson break; 432920923c1dSRichard Henderson 433020ba8504SRichard Henderson default: 433120ba8504SRichard Henderson /* invoke data storage error handler */ 433220ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 433320ba8504SRichard Henderson } 433420ba8504SRichard Henderson tcg_temp_free(EA); 433520923c1dSRichard Henderson 433620923c1dSRichard Henderson if (need_serial) { 433720923c1dSRichard Henderson /* Restart with exclusive lock. */ 433820923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 433920923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 434020923c1dSRichard Henderson } 4341a68a6146SBalamuruhan S } 4342a68a6146SBalamuruhan S 434320ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 434420ba8504SRichard Henderson { 434520ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 434620ba8504SRichard Henderson } 434720ba8504SRichard Henderson 434820ba8504SRichard Henderson #ifdef TARGET_PPC64 434920ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 435020ba8504SRichard Henderson { 435120ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 435220ba8504SRichard Henderson } 4353a68a6146SBalamuruhan S #endif 4354a68a6146SBalamuruhan S 435514776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 43569deb041cSRichard Henderson { 43579deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 43589deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 43599deb041cSRichard Henderson TCGv src, discard; 43609deb041cSRichard Henderson 43619deb041cSRichard Henderson gen_addr_register(ctx, EA); 43629deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 43639deb041cSRichard Henderson discard = tcg_temp_new(); 43649deb041cSRichard Henderson 43659deb041cSRichard Henderson memop |= MO_ALIGN; 43669deb041cSRichard Henderson switch (gpr_FC) { 43679deb041cSRichard Henderson case 0: /* add and Store */ 43689deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43699deb041cSRichard Henderson break; 43709deb041cSRichard Henderson case 1: /* xor and Store */ 43719deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43729deb041cSRichard Henderson break; 43739deb041cSRichard Henderson case 2: /* Or and Store */ 43749deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43759deb041cSRichard Henderson break; 43769deb041cSRichard Henderson case 3: /* 'and' and Store */ 43779deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43789deb041cSRichard Henderson break; 43799deb041cSRichard Henderson case 4: /* Store max unsigned */ 4380b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4381b8ce0f86SRichard Henderson break; 43829deb041cSRichard Henderson case 5: /* Store max signed */ 4383b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4384b8ce0f86SRichard Henderson break; 43859deb041cSRichard Henderson case 6: /* Store min unsigned */ 4386b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4387b8ce0f86SRichard Henderson break; 43889deb041cSRichard Henderson case 7: /* Store min signed */ 4389b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4390b8ce0f86SRichard Henderson break; 43919deb041cSRichard Henderson case 24: /* Store twin */ 43927fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 43937fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 43947fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 43957fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 43967fbc2b20SRichard Henderson } else { 43977fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 43987fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 43997fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 44007fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 44017fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 44027fbc2b20SRichard Henderson 44037fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 44047fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 44057fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 44067fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 44077fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 44087fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 44097fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 44107fbc2b20SRichard Henderson 44117fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 44127fbc2b20SRichard Henderson tcg_temp_free(s2); 44137fbc2b20SRichard Henderson tcg_temp_free(s); 44147fbc2b20SRichard Henderson tcg_temp_free(t2); 44157fbc2b20SRichard Henderson tcg_temp_free(t); 44167fbc2b20SRichard Henderson } 44179deb041cSRichard Henderson break; 44189deb041cSRichard Henderson default: 44199deb041cSRichard Henderson /* invoke data storage error handler */ 44209deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 44219deb041cSRichard Henderson } 44229deb041cSRichard Henderson tcg_temp_free(discard); 44239deb041cSRichard Henderson tcg_temp_free(EA); 4424a3401188SBalamuruhan S } 4425a3401188SBalamuruhan S 44269deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 44279deb041cSRichard Henderson { 44289deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 44299deb041cSRichard Henderson } 44309deb041cSRichard Henderson 44319deb041cSRichard Henderson #ifdef TARGET_PPC64 44329deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 44339deb041cSRichard Henderson { 44349deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 44359deb041cSRichard Henderson } 4436a3401188SBalamuruhan S #endif 4437a3401188SBalamuruhan S 443814776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4439fcf5ef2aSThomas Huth { 4440253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4441253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4442d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4443d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4444fcf5ef2aSThomas Huth 4445d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4446d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4447d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4448d8b86898SRichard Henderson tcg_temp_free(t0); 4449253ce7b2SNikunj A Dadhania 4450253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4451253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4452253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4453253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4454253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4455253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4456253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4457253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4458253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4459253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4460253ce7b2SNikunj A Dadhania 4461fcf5ef2aSThomas Huth gen_set_label(l1); 44624771df23SNikunj A Dadhania 4463efe843d8SDavid Gibson /* 4464efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4465efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4466efe843d8SDavid Gibson */ 44674771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4468253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4469253ce7b2SNikunj A Dadhania 4470253ce7b2SNikunj A Dadhania gen_set_label(l2); 4471fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4472fcf5ef2aSThomas Huth } 4473fcf5ef2aSThomas Huth 4474fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4475fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4476fcf5ef2aSThomas Huth { \ 4477d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4478fcf5ef2aSThomas Huth } 4479fcf5ef2aSThomas Huth 4480fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4481fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4482fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4483fcf5ef2aSThomas Huth 4484fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4485fcf5ef2aSThomas Huth /* ldarx */ 4486fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4487fcf5ef2aSThomas Huth /* stdcx. */ 4488fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4489fcf5ef2aSThomas Huth 4490fcf5ef2aSThomas Huth /* lqarx */ 4491fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4492fcf5ef2aSThomas Huth { 4493fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 449494bf2658SRichard Henderson TCGv EA, hi, lo; 4495fcf5ef2aSThomas Huth 4496fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4497fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4498fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4499fcf5ef2aSThomas Huth return; 4500fcf5ef2aSThomas Huth } 4501fcf5ef2aSThomas Huth 4502fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 450394bf2658SRichard Henderson EA = tcg_temp_new(); 4504fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 450594bf2658SRichard Henderson 450694bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 450794bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 450894bf2658SRichard Henderson hi = cpu_gpr[rd]; 450994bf2658SRichard Henderson 451094bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4511f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 451294bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 451394bf2658SRichard Henderson if (ctx->le_mode) { 451494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 451594bf2658SRichard Henderson ctx->mem_idx)); 451694bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4517fcf5ef2aSThomas Huth } else { 451894bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 451994bf2658SRichard Henderson ctx->mem_idx)); 452094bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4521fcf5ef2aSThomas Huth } 452294bf2658SRichard Henderson tcg_temp_free_i32(oi); 452394bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4524f34ec0f6SRichard Henderson } else { 452594bf2658SRichard Henderson /* Restart with exclusive lock. */ 452694bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 452794bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 452894bf2658SRichard Henderson tcg_temp_free(EA); 452994bf2658SRichard Henderson return; 4530f34ec0f6SRichard Henderson } 453194bf2658SRichard Henderson } else if (ctx->le_mode) { 453294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4533fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4534fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 453594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 453694bf2658SRichard Henderson } else { 453794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 453894bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 453994bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 454094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 454194bf2658SRichard Henderson } 4542fcf5ef2aSThomas Huth tcg_temp_free(EA); 454394bf2658SRichard Henderson 454494bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 454594bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4546fcf5ef2aSThomas Huth } 4547fcf5ef2aSThomas Huth 4548fcf5ef2aSThomas Huth /* stqcx. */ 4549fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4550fcf5ef2aSThomas Huth { 45514a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 45524a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4553fcf5ef2aSThomas Huth 45544a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4555fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4556fcf5ef2aSThomas Huth return; 4557fcf5ef2aSThomas Huth } 45584a9b3c5dSRichard Henderson 4559fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 45604a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4561fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4562fcf5ef2aSThomas Huth 45634a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 45644a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 45654a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4566fcf5ef2aSThomas Huth 45674a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4568f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 45694a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 45704a9b3c5dSRichard Henderson if (ctx->le_mode) { 4571f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4572f34ec0f6SRichard Henderson EA, lo, hi, oi); 4573fcf5ef2aSThomas Huth } else { 4574f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4575f34ec0f6SRichard Henderson EA, lo, hi, oi); 4576fcf5ef2aSThomas Huth } 4577f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4578f34ec0f6SRichard Henderson } else { 45794a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 45804a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 45814a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4582f34ec0f6SRichard Henderson } 4583fcf5ef2aSThomas Huth tcg_temp_free(EA); 45844a9b3c5dSRichard Henderson } else { 45854a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 45864a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 45874a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 45884a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4589fcf5ef2aSThomas Huth 45904a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 45914a9b3c5dSRichard Henderson tcg_temp_free(EA); 45924a9b3c5dSRichard Henderson 45934a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 45944a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 45954a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 45964a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 45974a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 45984a9b3c5dSRichard Henderson 45994a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 46004a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 46014a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 46024a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 46034a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 46044a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 46054a9b3c5dSRichard Henderson 46064a9b3c5dSRichard Henderson /* Success */ 46074a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 46084a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 46094a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 46104a9b3c5dSRichard Henderson 46114a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46124a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 46134a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 46144a9b3c5dSRichard Henderson 46154a9b3c5dSRichard Henderson gen_set_label(lab_fail); 46164a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46174a9b3c5dSRichard Henderson 46184a9b3c5dSRichard Henderson gen_set_label(lab_over); 46194a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 46204a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 46214a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 46224a9b3c5dSRichard Henderson } 46234a9b3c5dSRichard Henderson } 4624fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4625fcf5ef2aSThomas Huth 4626fcf5ef2aSThomas Huth /* sync */ 4627fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4628fcf5ef2aSThomas Huth { 4629fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4630fcf5ef2aSThomas Huth 4631fcf5ef2aSThomas Huth /* 4632fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4633fcf5ef2aSThomas Huth * 4634fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4635fcf5ef2aSThomas Huth * 4636fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4637fcf5ef2aSThomas Huth * check MSR_PR as well. 4638fcf5ef2aSThomas Huth */ 4639fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4640fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4641fcf5ef2aSThomas Huth } 46424771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4643fcf5ef2aSThomas Huth } 4644fcf5ef2aSThomas Huth 4645fcf5ef2aSThomas Huth /* wait */ 4646fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4647fcf5ef2aSThomas Huth { 4648fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4649fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4650fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4651fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4652fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4653b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4654fcf5ef2aSThomas Huth } 4655fcf5ef2aSThomas Huth 4656fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4657fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4658fcf5ef2aSThomas Huth { 4659fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4660fcf5ef2aSThomas Huth GEN_PRIV; 4661fcf5ef2aSThomas Huth #else 4662fcf5ef2aSThomas Huth TCGv_i32 t; 4663fcf5ef2aSThomas Huth 4664fcf5ef2aSThomas Huth CHK_HV; 4665fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4666fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4667fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4668154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4669154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4670fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4671fcf5ef2aSThomas Huth } 4672fcf5ef2aSThomas Huth 4673fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4674fcf5ef2aSThomas Huth { 4675fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4676fcf5ef2aSThomas Huth GEN_PRIV; 4677fcf5ef2aSThomas Huth #else 4678fcf5ef2aSThomas Huth TCGv_i32 t; 4679fcf5ef2aSThomas Huth 4680fcf5ef2aSThomas Huth CHK_HV; 4681fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4682fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4683fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4684154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4685154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4686fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4687fcf5ef2aSThomas Huth } 4688fcf5ef2aSThomas Huth 4689cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4690cdee0e72SNikunj A Dadhania { 469121c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 469221c0d66aSBenjamin Herrenschmidt GEN_PRIV; 469321c0d66aSBenjamin Herrenschmidt #else 469421c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 469521c0d66aSBenjamin Herrenschmidt 469621c0d66aSBenjamin Herrenschmidt CHK_HV; 469721c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 469821c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 469921c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 470021c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 470121c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 470221c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4703cdee0e72SNikunj A Dadhania } 4704cdee0e72SNikunj A Dadhania 4705fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4706fcf5ef2aSThomas Huth { 4707fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4708fcf5ef2aSThomas Huth GEN_PRIV; 4709fcf5ef2aSThomas Huth #else 4710fcf5ef2aSThomas Huth TCGv_i32 t; 4711fcf5ef2aSThomas Huth 4712fcf5ef2aSThomas Huth CHK_HV; 4713fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4714fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4715fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4716154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4717154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4718fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4719fcf5ef2aSThomas Huth } 4720fcf5ef2aSThomas Huth 4721fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4722fcf5ef2aSThomas Huth { 4723fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4724fcf5ef2aSThomas Huth GEN_PRIV; 4725fcf5ef2aSThomas Huth #else 4726fcf5ef2aSThomas Huth TCGv_i32 t; 4727fcf5ef2aSThomas Huth 4728fcf5ef2aSThomas Huth CHK_HV; 4729fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4730fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4731fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4732154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4733154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4734fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4735fcf5ef2aSThomas Huth } 4736fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4737fcf5ef2aSThomas Huth 4738fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4739fcf5ef2aSThomas Huth { 4740fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4741efe843d8SDavid Gibson if (ctx->has_cfar) { 4742fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4743efe843d8SDavid Gibson } 4744fcf5ef2aSThomas Huth #endif 4745fcf5ef2aSThomas Huth } 4746fcf5ef2aSThomas Huth 4747fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4748fcf5ef2aSThomas Huth { 4749fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4750fcf5ef2aSThomas Huth return false; 4751fcf5ef2aSThomas Huth } 4752fcf5ef2aSThomas Huth 4753fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4754b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4755fcf5ef2aSThomas Huth #else 4756fcf5ef2aSThomas Huth return true; 4757fcf5ef2aSThomas Huth #endif 4758fcf5ef2aSThomas Huth } 4759fcf5ef2aSThomas Huth 47600e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 47610e3bf489SRoman Kapl { 47620e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 47630e3bf489SRoman Kapl if (unlikely(sse)) { 47640e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 47650e3bf489SRoman Kapl gen_debug_exception(ctx); 47660e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4767e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 47680e3bf489SRoman Kapl gen_exception(ctx, excp); 47690e3bf489SRoman Kapl } 47700e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 47710e3bf489SRoman Kapl } else { 47720e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 47730e3bf489SRoman Kapl } 47740e3bf489SRoman Kapl } 47750e3bf489SRoman Kapl 4776fcf5ef2aSThomas Huth /*** Branch ***/ 4777c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4778fcf5ef2aSThomas Huth { 4779fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4780fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4781fcf5ef2aSThomas Huth } 4782fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4783fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4784fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 478507ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4786fcf5ef2aSThomas Huth } else { 4787fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 47880e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4789fcf5ef2aSThomas Huth } 4790fcf5ef2aSThomas Huth } 4791fcf5ef2aSThomas Huth 4792fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4793fcf5ef2aSThomas Huth { 4794fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4795fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4796fcf5ef2aSThomas Huth } 4797fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4798fcf5ef2aSThomas Huth } 4799fcf5ef2aSThomas Huth 4800fcf5ef2aSThomas Huth /* b ba bl bla */ 4801fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4802fcf5ef2aSThomas Huth { 4803fcf5ef2aSThomas Huth target_ulong li, target; 4804fcf5ef2aSThomas Huth 4805fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 4806fcf5ef2aSThomas Huth /* sign extend LI */ 4807fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4808fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4809fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 4810*2c2bcb1bSRichard Henderson target = ctx->cia + li; 4811fcf5ef2aSThomas Huth } else { 4812fcf5ef2aSThomas Huth target = li; 4813fcf5ef2aSThomas Huth } 4814fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4815b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4816fcf5ef2aSThomas Huth } 4817*2c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4818fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 4819fcf5ef2aSThomas Huth } 4820fcf5ef2aSThomas Huth 4821fcf5ef2aSThomas Huth #define BCOND_IM 0 4822fcf5ef2aSThomas Huth #define BCOND_LR 1 4823fcf5ef2aSThomas Huth #define BCOND_CTR 2 4824fcf5ef2aSThomas Huth #define BCOND_TAR 3 4825fcf5ef2aSThomas Huth 4826c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4827fcf5ef2aSThomas Huth { 4828fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4829fcf5ef2aSThomas Huth TCGLabel *l1; 4830fcf5ef2aSThomas Huth TCGv target; 4831fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 48320e3bf489SRoman Kapl 4833fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4834fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4835efe843d8SDavid Gibson if (type == BCOND_CTR) { 4836fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4837efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4838fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4839efe843d8SDavid Gibson } else { 4840fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4841efe843d8SDavid Gibson } 4842fcf5ef2aSThomas Huth } else { 4843f764718dSRichard Henderson target = NULL; 4844fcf5ef2aSThomas Huth } 4845efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4846b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4847efe843d8SDavid Gibson } 4848fcf5ef2aSThomas Huth l1 = gen_new_label(); 4849fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4850fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4851fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4852fa200c95SGreg Kurz 4853fa200c95SGreg Kurz if (type == BCOND_CTR) { 4854fa200c95SGreg Kurz /* 4855fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4856fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4857fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 485815d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 485915d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 486015d68c5eSGreg Kurz * it basically useless and thus never used in real code. 486115d68c5eSGreg Kurz * 486215d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 486315d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 486415d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 486515d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 486615d68c5eSGreg Kurz * doing anything else harmful. 4867fa200c95SGreg Kurz */ 4868d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4869fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 48709acc95cdSGreg Kurz tcg_temp_free(temp); 48719acc95cdSGreg Kurz tcg_temp_free(target); 4872fcf5ef2aSThomas Huth return; 4873fcf5ef2aSThomas Huth } 4874fa200c95SGreg Kurz 4875fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4876fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4877fa200c95SGreg Kurz } else { 4878fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4879fa200c95SGreg Kurz } 4880fa200c95SGreg Kurz if (bo & 0x2) { 4881fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4882fa200c95SGreg Kurz } else { 4883fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4884fa200c95SGreg Kurz } 4885fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4886fa200c95SGreg Kurz } else { 4887fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4888fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4889fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4890fcf5ef2aSThomas Huth } else { 4891fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4892fcf5ef2aSThomas Huth } 4893fcf5ef2aSThomas Huth if (bo & 0x2) { 4894fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4895fcf5ef2aSThomas Huth } else { 4896fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4897fcf5ef2aSThomas Huth } 4898fa200c95SGreg Kurz } 4899fcf5ef2aSThomas Huth tcg_temp_free(temp); 4900fcf5ef2aSThomas Huth } 4901fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4902fcf5ef2aSThomas Huth /* Test CR */ 4903fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4904fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4905fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4906fcf5ef2aSThomas Huth 4907fcf5ef2aSThomas Huth if (bo & 0x8) { 4908fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4909fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4910fcf5ef2aSThomas Huth } else { 4911fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4912fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4913fcf5ef2aSThomas Huth } 4914fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4915fcf5ef2aSThomas Huth } 4916*2c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4917fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4918fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4919fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 4920*2c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4921fcf5ef2aSThomas Huth } else { 4922fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4923fcf5ef2aSThomas Huth } 4924fcf5ef2aSThomas Huth } else { 4925fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4926fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4927fcf5ef2aSThomas Huth } else { 4928fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4929fcf5ef2aSThomas Huth } 49300e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4931c4a2e3a9SRichard Henderson tcg_temp_free(target); 4932c4a2e3a9SRichard Henderson } 4933fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 49340e3bf489SRoman Kapl /* fallthrough case */ 4935fcf5ef2aSThomas Huth gen_set_label(l1); 4936b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4937fcf5ef2aSThomas Huth } 4938fcf5ef2aSThomas Huth } 4939fcf5ef2aSThomas Huth 4940fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4941fcf5ef2aSThomas Huth { 4942fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4943fcf5ef2aSThomas Huth } 4944fcf5ef2aSThomas Huth 4945fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4946fcf5ef2aSThomas Huth { 4947fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4948fcf5ef2aSThomas Huth } 4949fcf5ef2aSThomas Huth 4950fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4951fcf5ef2aSThomas Huth { 4952fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4953fcf5ef2aSThomas Huth } 4954fcf5ef2aSThomas Huth 4955fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4956fcf5ef2aSThomas Huth { 4957fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4958fcf5ef2aSThomas Huth } 4959fcf5ef2aSThomas Huth 4960fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4961fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4962fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4963fcf5ef2aSThomas Huth { \ 4964fcf5ef2aSThomas Huth uint8_t bitmask; \ 4965fcf5ef2aSThomas Huth int sh; \ 4966fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4967fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4968fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4969fcf5ef2aSThomas Huth if (sh > 0) \ 4970fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4971fcf5ef2aSThomas Huth else if (sh < 0) \ 4972fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4973fcf5ef2aSThomas Huth else \ 4974fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4975fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4976fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4977fcf5ef2aSThomas Huth if (sh > 0) \ 4978fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4979fcf5ef2aSThomas Huth else if (sh < 0) \ 4980fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4981fcf5ef2aSThomas Huth else \ 4982fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4983fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4984fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4985fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4986fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4987fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4988fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4989fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4990fcf5ef2aSThomas Huth } 4991fcf5ef2aSThomas Huth 4992fcf5ef2aSThomas Huth /* crand */ 4993fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4994fcf5ef2aSThomas Huth /* crandc */ 4995fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4996fcf5ef2aSThomas Huth /* creqv */ 4997fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4998fcf5ef2aSThomas Huth /* crnand */ 4999fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 5000fcf5ef2aSThomas Huth /* crnor */ 5001fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 5002fcf5ef2aSThomas Huth /* cror */ 5003fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 5004fcf5ef2aSThomas Huth /* crorc */ 5005fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 5006fcf5ef2aSThomas Huth /* crxor */ 5007fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 5008fcf5ef2aSThomas Huth 5009fcf5ef2aSThomas Huth /* mcrf */ 5010fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 5011fcf5ef2aSThomas Huth { 5012fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 5013fcf5ef2aSThomas Huth } 5014fcf5ef2aSThomas Huth 5015fcf5ef2aSThomas Huth /*** System linkage ***/ 5016fcf5ef2aSThomas Huth 5017fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 5018fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 5019fcf5ef2aSThomas Huth { 5020fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5021fcf5ef2aSThomas Huth GEN_PRIV; 5022fcf5ef2aSThomas Huth #else 5023efe843d8SDavid Gibson /* 5024efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 5025fcf5ef2aSThomas Huth * processors compliant with arch 2.x 5026fcf5ef2aSThomas Huth */ 5027d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 5028fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5029fcf5ef2aSThomas Huth return; 5030fcf5ef2aSThomas Huth } 5031fcf5ef2aSThomas Huth /* Restore CPU state */ 5032fcf5ef2aSThomas Huth CHK_SV; 5033a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5034a59d628fSMaria Klimushenkova gen_io_start(); 5035a59d628fSMaria Klimushenkova } 5036*2c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 5037fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 5038fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5039fcf5ef2aSThomas Huth #endif 5040fcf5ef2aSThomas Huth } 5041fcf5ef2aSThomas Huth 5042fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5043fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 5044fcf5ef2aSThomas Huth { 5045fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5046fcf5ef2aSThomas Huth GEN_PRIV; 5047fcf5ef2aSThomas Huth #else 5048fcf5ef2aSThomas Huth /* Restore CPU state */ 5049fcf5ef2aSThomas Huth CHK_SV; 5050a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5051a59d628fSMaria Klimushenkova gen_io_start(); 5052a59d628fSMaria Klimushenkova } 5053*2c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 5054fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 5055fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5056fcf5ef2aSThomas Huth #endif 5057fcf5ef2aSThomas Huth } 5058fcf5ef2aSThomas Huth 50593c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 50603c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 50613c89b8d6SNicholas Piggin { 50623c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 50633c89b8d6SNicholas Piggin GEN_PRIV; 50643c89b8d6SNicholas Piggin #else 50653c89b8d6SNicholas Piggin /* Restore CPU state */ 50663c89b8d6SNicholas Piggin CHK_SV; 50673c89b8d6SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 50683c89b8d6SNicholas Piggin gen_io_start(); 50693c89b8d6SNicholas Piggin } 5070*2c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 50713c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 50723c89b8d6SNicholas Piggin gen_sync_exception(ctx); 50733c89b8d6SNicholas Piggin #endif 50743c89b8d6SNicholas Piggin } 50753c89b8d6SNicholas Piggin #endif 50763c89b8d6SNicholas Piggin 5077fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 5078fcf5ef2aSThomas Huth { 5079fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5080fcf5ef2aSThomas Huth GEN_PRIV; 5081fcf5ef2aSThomas Huth #else 5082fcf5ef2aSThomas Huth /* Restore CPU state */ 5083fcf5ef2aSThomas Huth CHK_HV; 5084fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 5085fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5086fcf5ef2aSThomas Huth #endif 5087fcf5ef2aSThomas Huth } 5088fcf5ef2aSThomas Huth #endif 5089fcf5ef2aSThomas Huth 5090fcf5ef2aSThomas Huth /* sc */ 5091fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5092fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 5093fcf5ef2aSThomas Huth #else 5094fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 50953c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 5096fcf5ef2aSThomas Huth #endif 5097fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 5098fcf5ef2aSThomas Huth { 5099fcf5ef2aSThomas Huth uint32_t lev; 5100fcf5ef2aSThomas Huth 5101fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 5102fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 5103fcf5ef2aSThomas Huth } 5104fcf5ef2aSThomas Huth 51053c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 51063c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 51073c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 51083c89b8d6SNicholas Piggin { 5109f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 51103c89b8d6SNicholas Piggin 5111f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 5112f43520e5SRichard Henderson if (ctx->exception == POWERPC_EXCP_NONE) { 5113*2c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 51143c89b8d6SNicholas Piggin } 5115f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 51163c89b8d6SNicholas Piggin 5117f43520e5SRichard Henderson /* This need not be exact, just not POWERPC_EXCP_NONE */ 5118f43520e5SRichard Henderson ctx->exception = POWERPC_SYSCALL_VECTORED; 51193c89b8d6SNicholas Piggin } 51203c89b8d6SNicholas Piggin #endif 51213c89b8d6SNicholas Piggin #endif 51223c89b8d6SNicholas Piggin 5123fcf5ef2aSThomas Huth /*** Trap ***/ 5124fcf5ef2aSThomas Huth 5125fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 5126fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 5127fcf5ef2aSThomas Huth { 5128fcf5ef2aSThomas Huth /* Trap never */ 5129fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 5130fcf5ef2aSThomas Huth return true; 5131fcf5ef2aSThomas Huth } 5132fcf5ef2aSThomas Huth /* Trap always */ 5133fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 5134fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 5135fcf5ef2aSThomas Huth return true; 5136fcf5ef2aSThomas Huth } 5137fcf5ef2aSThomas Huth return false; 5138fcf5ef2aSThomas Huth } 5139fcf5ef2aSThomas Huth 5140fcf5ef2aSThomas Huth /* tw */ 5141fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 5142fcf5ef2aSThomas Huth { 5143fcf5ef2aSThomas Huth TCGv_i32 t0; 5144fcf5ef2aSThomas Huth 5145fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5146fcf5ef2aSThomas Huth return; 5147fcf5ef2aSThomas Huth } 5148fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5149fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5150fcf5ef2aSThomas Huth t0); 5151fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5152fcf5ef2aSThomas Huth } 5153fcf5ef2aSThomas Huth 5154fcf5ef2aSThomas Huth /* twi */ 5155fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 5156fcf5ef2aSThomas Huth { 5157fcf5ef2aSThomas Huth TCGv t0; 5158fcf5ef2aSThomas Huth TCGv_i32 t1; 5159fcf5ef2aSThomas Huth 5160fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5161fcf5ef2aSThomas Huth return; 5162fcf5ef2aSThomas Huth } 5163fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5164fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5165fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5166fcf5ef2aSThomas Huth tcg_temp_free(t0); 5167fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5168fcf5ef2aSThomas Huth } 5169fcf5ef2aSThomas Huth 5170fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5171fcf5ef2aSThomas Huth /* td */ 5172fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 5173fcf5ef2aSThomas Huth { 5174fcf5ef2aSThomas Huth TCGv_i32 t0; 5175fcf5ef2aSThomas Huth 5176fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5177fcf5ef2aSThomas Huth return; 5178fcf5ef2aSThomas Huth } 5179fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5180fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5181fcf5ef2aSThomas Huth t0); 5182fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5183fcf5ef2aSThomas Huth } 5184fcf5ef2aSThomas Huth 5185fcf5ef2aSThomas Huth /* tdi */ 5186fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 5187fcf5ef2aSThomas Huth { 5188fcf5ef2aSThomas Huth TCGv t0; 5189fcf5ef2aSThomas Huth TCGv_i32 t1; 5190fcf5ef2aSThomas Huth 5191fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5192fcf5ef2aSThomas Huth return; 5193fcf5ef2aSThomas Huth } 5194fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5195fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5196fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5197fcf5ef2aSThomas Huth tcg_temp_free(t0); 5198fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5199fcf5ef2aSThomas Huth } 5200fcf5ef2aSThomas Huth #endif 5201fcf5ef2aSThomas Huth 5202fcf5ef2aSThomas Huth /*** Processor control ***/ 5203fcf5ef2aSThomas Huth 5204fcf5ef2aSThomas Huth /* mcrxr */ 5205fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 5206fcf5ef2aSThomas Huth { 5207fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5208fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 5209fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5210fcf5ef2aSThomas Huth 5211fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 5212fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 5213fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 5214fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 5215fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 5216fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 5217fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 5218fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 5219fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5220fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5221fcf5ef2aSThomas Huth 5222fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 5223fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5224fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5225fcf5ef2aSThomas Huth } 5226fcf5ef2aSThomas Huth 5227b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 5228b63d0434SNikunj A Dadhania /* mcrxrx */ 5229b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 5230b63d0434SNikunj A Dadhania { 5231b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 5232b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 5233b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5234b63d0434SNikunj A Dadhania 5235b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 5236b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 5237b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 5238b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 5239b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 5240b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 5241b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 5242b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 5243b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 5244b63d0434SNikunj A Dadhania tcg_temp_free(t0); 5245b63d0434SNikunj A Dadhania tcg_temp_free(t1); 5246b63d0434SNikunj A Dadhania } 5247b63d0434SNikunj A Dadhania #endif 5248b63d0434SNikunj A Dadhania 5249fcf5ef2aSThomas Huth /* mfcr mfocrf */ 5250fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 5251fcf5ef2aSThomas Huth { 5252fcf5ef2aSThomas Huth uint32_t crm, crn; 5253fcf5ef2aSThomas Huth 5254fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 5255fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5256fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 5257fcf5ef2aSThomas Huth crn = ctz32(crm); 5258fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 5259fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 5260fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 5261fcf5ef2aSThomas Huth } 5262fcf5ef2aSThomas Huth } else { 5263fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5264fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 5265fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5266fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 5267fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5268fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 5269fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5270fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 5271fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5272fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 5273fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5274fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 5275fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5276fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 5277fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5278fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 5279fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5280fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5281fcf5ef2aSThomas Huth } 5282fcf5ef2aSThomas Huth } 5283fcf5ef2aSThomas Huth 5284fcf5ef2aSThomas Huth /* mfmsr */ 5285fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 5286fcf5ef2aSThomas Huth { 5287fcf5ef2aSThomas Huth CHK_SV; 5288fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 5289fcf5ef2aSThomas Huth } 5290fcf5ef2aSThomas Huth 5291fcf5ef2aSThomas Huth /* mfspr */ 5292fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 5293fcf5ef2aSThomas Huth { 5294fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 5295fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5296fcf5ef2aSThomas Huth 5297fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5298fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5299fcf5ef2aSThomas Huth #else 5300fcf5ef2aSThomas Huth if (ctx->pr) { 5301fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5302fcf5ef2aSThomas Huth } else if (ctx->hv) { 5303fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 5304fcf5ef2aSThomas Huth } else { 5305fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 5306fcf5ef2aSThomas Huth } 5307fcf5ef2aSThomas Huth #endif 5308fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 5309fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 5310fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 5311fcf5ef2aSThomas Huth } else { 5312fcf5ef2aSThomas Huth /* Privilege exception */ 5313efe843d8SDavid Gibson /* 5314efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 5315fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 5316fcf5ef2aSThomas Huth * allowing userland application to read the PVR 5317fcf5ef2aSThomas Huth */ 5318fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 531931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 532031085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 5321*2c2bcb1bSRichard Henderson ctx->cia); 5322fcf5ef2aSThomas Huth } 5323fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5324fcf5ef2aSThomas Huth } 5325fcf5ef2aSThomas Huth } else { 5326fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5327fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5328fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5329fcf5ef2aSThomas Huth /* This is a nop */ 5330fcf5ef2aSThomas Huth return; 5331fcf5ef2aSThomas Huth } 5332fcf5ef2aSThomas Huth /* Not defined */ 533331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 533431085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 5335*2c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5336fcf5ef2aSThomas Huth 5337efe843d8SDavid Gibson /* 5338efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5339efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5340fcf5ef2aSThomas Huth */ 5341fcf5ef2aSThomas Huth if (sprn & 0x10) { 5342fcf5ef2aSThomas Huth if (ctx->pr) { 5343fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5344fcf5ef2aSThomas Huth } 5345fcf5ef2aSThomas Huth } else { 5346fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5347fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5348fcf5ef2aSThomas Huth } 5349fcf5ef2aSThomas Huth } 5350fcf5ef2aSThomas Huth } 5351fcf5ef2aSThomas Huth } 5352fcf5ef2aSThomas Huth 5353fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5354fcf5ef2aSThomas Huth { 5355fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5356fcf5ef2aSThomas Huth } 5357fcf5ef2aSThomas Huth 5358fcf5ef2aSThomas Huth /* mftb */ 5359fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5360fcf5ef2aSThomas Huth { 5361fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5362fcf5ef2aSThomas Huth } 5363fcf5ef2aSThomas Huth 5364fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5365fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5366fcf5ef2aSThomas Huth { 5367fcf5ef2aSThomas Huth uint32_t crm, crn; 5368fcf5ef2aSThomas Huth 5369fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5370fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5371fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5372fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5373fcf5ef2aSThomas Huth crn = ctz32(crm); 5374fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5375fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5376fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5377fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5378fcf5ef2aSThomas Huth } 5379fcf5ef2aSThomas Huth } else { 5380fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5381fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5382fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5383fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5384fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5385fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5386fcf5ef2aSThomas Huth } 5387fcf5ef2aSThomas Huth } 5388fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5389fcf5ef2aSThomas Huth } 5390fcf5ef2aSThomas Huth } 5391fcf5ef2aSThomas Huth 5392fcf5ef2aSThomas Huth /* mtmsr */ 5393fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5394fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5395fcf5ef2aSThomas Huth { 5396fcf5ef2aSThomas Huth CHK_SV; 5397fcf5ef2aSThomas Huth 5398fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 53995ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54005ed19506SNicholas Piggin gen_io_start(); 54015ed19506SNicholas Piggin } 5402fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54035ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5404fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54055ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5406efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5407efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54085ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5409efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54105ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54115ed19506SNicholas Piggin 54125ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5413fcf5ef2aSThomas Huth tcg_temp_free(t0); 54145ed19506SNicholas Piggin tcg_temp_free(t1); 54155ed19506SNicholas Piggin 5416fcf5ef2aSThomas Huth } else { 5417efe843d8SDavid Gibson /* 5418efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5419efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5420efe843d8SDavid Gibson * ppc_store_msr 5421fcf5ef2aSThomas Huth */ 5422b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5423fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5424fcf5ef2aSThomas Huth } 54255ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54265ed19506SNicholas Piggin gen_stop_exception(ctx); 5427fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5428fcf5ef2aSThomas Huth } 5429fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5430fcf5ef2aSThomas Huth 5431fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5432fcf5ef2aSThomas Huth { 5433fcf5ef2aSThomas Huth CHK_SV; 5434fcf5ef2aSThomas Huth 5435fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 54365ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54375ed19506SNicholas Piggin gen_io_start(); 54385ed19506SNicholas Piggin } 5439fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54405ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5441fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54425ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5443efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5444efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54455ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5446efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54475ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54485ed19506SNicholas Piggin 54495ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5450fcf5ef2aSThomas Huth tcg_temp_free(t0); 54515ed19506SNicholas Piggin tcg_temp_free(t1); 54525ed19506SNicholas Piggin 5453fcf5ef2aSThomas Huth } else { 5454fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5455fcf5ef2aSThomas Huth 5456efe843d8SDavid Gibson /* 5457efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5458efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5459efe843d8SDavid Gibson * ppc_store_msr 5460fcf5ef2aSThomas Huth */ 5461b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5462fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5463fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5464fcf5ef2aSThomas Huth #else 5465fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5466fcf5ef2aSThomas Huth #endif 5467fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5468fcf5ef2aSThomas Huth tcg_temp_free(msr); 5469fcf5ef2aSThomas Huth } 54705ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54715ed19506SNicholas Piggin gen_stop_exception(ctx); 5472fcf5ef2aSThomas Huth #endif 5473fcf5ef2aSThomas Huth } 5474fcf5ef2aSThomas Huth 5475fcf5ef2aSThomas Huth /* mtspr */ 5476fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5477fcf5ef2aSThomas Huth { 5478fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5479fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5480fcf5ef2aSThomas Huth 5481fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5482fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5483fcf5ef2aSThomas Huth #else 5484fcf5ef2aSThomas Huth if (ctx->pr) { 5485fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5486fcf5ef2aSThomas Huth } else if (ctx->hv) { 5487fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5488fcf5ef2aSThomas Huth } else { 5489fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5490fcf5ef2aSThomas Huth } 5491fcf5ef2aSThomas Huth #endif 5492fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5493fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5494fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5495fcf5ef2aSThomas Huth } else { 5496fcf5ef2aSThomas Huth /* Privilege exception */ 549731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 549831085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 5499*2c2bcb1bSRichard Henderson ctx->cia); 5500fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5501fcf5ef2aSThomas Huth } 5502fcf5ef2aSThomas Huth } else { 5503fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5504fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5505fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5506fcf5ef2aSThomas Huth /* This is a nop */ 5507fcf5ef2aSThomas Huth return; 5508fcf5ef2aSThomas Huth } 5509fcf5ef2aSThomas Huth 5510fcf5ef2aSThomas Huth /* Not defined */ 551131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 551231085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 5513*2c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5514fcf5ef2aSThomas Huth 5515fcf5ef2aSThomas Huth 5516efe843d8SDavid Gibson /* 5517efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5518efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5519fcf5ef2aSThomas Huth */ 5520fcf5ef2aSThomas Huth if (sprn & 0x10) { 5521fcf5ef2aSThomas Huth if (ctx->pr) { 5522fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5523fcf5ef2aSThomas Huth } 5524fcf5ef2aSThomas Huth } else { 5525fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5526fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5527fcf5ef2aSThomas Huth } 5528fcf5ef2aSThomas Huth } 5529fcf5ef2aSThomas Huth } 5530fcf5ef2aSThomas Huth } 5531fcf5ef2aSThomas Huth 5532fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5533fcf5ef2aSThomas Huth /* setb */ 5534fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5535fcf5ef2aSThomas Huth { 5536fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5537fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5538fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5539fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5540fcf5ef2aSThomas Huth 5541fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5542fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5543fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5544fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5545fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5546fcf5ef2aSThomas Huth 5547fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5548fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5549fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5550fcf5ef2aSThomas Huth } 5551fcf5ef2aSThomas Huth #endif 5552fcf5ef2aSThomas Huth 5553fcf5ef2aSThomas Huth /*** Cache management ***/ 5554fcf5ef2aSThomas Huth 5555fcf5ef2aSThomas Huth /* dcbf */ 5556fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5557fcf5ef2aSThomas Huth { 5558fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5559fcf5ef2aSThomas Huth TCGv t0; 5560fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5561fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5562fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5563fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5564fcf5ef2aSThomas Huth tcg_temp_free(t0); 5565fcf5ef2aSThomas Huth } 5566fcf5ef2aSThomas Huth 556750728199SRoman Kapl /* dcbfep (external PID dcbf) */ 556850728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 556950728199SRoman Kapl { 557050728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 557150728199SRoman Kapl TCGv t0; 557250728199SRoman Kapl CHK_SV; 557350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 557450728199SRoman Kapl t0 = tcg_temp_new(); 557550728199SRoman Kapl gen_addr_reg_index(ctx, t0); 557650728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 557750728199SRoman Kapl tcg_temp_free(t0); 557850728199SRoman Kapl } 557950728199SRoman Kapl 5580fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5581fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5582fcf5ef2aSThomas Huth { 5583fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5584fcf5ef2aSThomas Huth GEN_PRIV; 5585fcf5ef2aSThomas Huth #else 5586fcf5ef2aSThomas Huth TCGv EA, val; 5587fcf5ef2aSThomas Huth 5588fcf5ef2aSThomas Huth CHK_SV; 5589fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5590fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5591fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5592fcf5ef2aSThomas Huth val = tcg_temp_new(); 5593fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5594fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5595fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5596fcf5ef2aSThomas Huth tcg_temp_free(val); 5597fcf5ef2aSThomas Huth tcg_temp_free(EA); 5598fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5599fcf5ef2aSThomas Huth } 5600fcf5ef2aSThomas Huth 5601fcf5ef2aSThomas Huth /* dcdst */ 5602fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5603fcf5ef2aSThomas Huth { 5604fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5605fcf5ef2aSThomas Huth TCGv t0; 5606fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5607fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5608fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5609fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5610fcf5ef2aSThomas Huth tcg_temp_free(t0); 5611fcf5ef2aSThomas Huth } 5612fcf5ef2aSThomas Huth 561350728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 561450728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 561550728199SRoman Kapl { 561650728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 561750728199SRoman Kapl TCGv t0; 561850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 561950728199SRoman Kapl t0 = tcg_temp_new(); 562050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 562150728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 562250728199SRoman Kapl tcg_temp_free(t0); 562350728199SRoman Kapl } 562450728199SRoman Kapl 5625fcf5ef2aSThomas Huth /* dcbt */ 5626fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5627fcf5ef2aSThomas Huth { 5628efe843d8SDavid Gibson /* 5629efe843d8SDavid Gibson * interpreted as no-op 5630efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5631efe843d8SDavid Gibson * does not generate any exception 5632fcf5ef2aSThomas Huth */ 5633fcf5ef2aSThomas Huth } 5634fcf5ef2aSThomas Huth 563550728199SRoman Kapl /* dcbtep */ 563650728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 563750728199SRoman Kapl { 5638efe843d8SDavid Gibson /* 5639efe843d8SDavid Gibson * interpreted as no-op 5640efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5641efe843d8SDavid Gibson * does not generate any exception 564250728199SRoman Kapl */ 564350728199SRoman Kapl } 564450728199SRoman Kapl 5645fcf5ef2aSThomas Huth /* dcbtst */ 5646fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5647fcf5ef2aSThomas Huth { 5648efe843d8SDavid Gibson /* 5649efe843d8SDavid Gibson * interpreted as no-op 5650efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5651efe843d8SDavid Gibson * does not generate any exception 5652fcf5ef2aSThomas Huth */ 5653fcf5ef2aSThomas Huth } 5654fcf5ef2aSThomas Huth 565550728199SRoman Kapl /* dcbtstep */ 565650728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 565750728199SRoman Kapl { 5658efe843d8SDavid Gibson /* 5659efe843d8SDavid Gibson * interpreted as no-op 5660efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5661efe843d8SDavid Gibson * does not generate any exception 566250728199SRoman Kapl */ 566350728199SRoman Kapl } 566450728199SRoman Kapl 5665fcf5ef2aSThomas Huth /* dcbtls */ 5666fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5667fcf5ef2aSThomas Huth { 5668fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5669fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5670fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5671fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5672fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5673fcf5ef2aSThomas Huth tcg_temp_free(t0); 5674fcf5ef2aSThomas Huth } 5675fcf5ef2aSThomas Huth 5676fcf5ef2aSThomas Huth /* dcbz */ 5677fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5678fcf5ef2aSThomas Huth { 5679fcf5ef2aSThomas Huth TCGv tcgv_addr; 5680fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5681fcf5ef2aSThomas Huth 5682fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5683fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5684fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5685fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5686fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5687fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5688fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5689fcf5ef2aSThomas Huth } 5690fcf5ef2aSThomas Huth 569150728199SRoman Kapl /* dcbzep */ 569250728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 569350728199SRoman Kapl { 569450728199SRoman Kapl TCGv tcgv_addr; 569550728199SRoman Kapl TCGv_i32 tcgv_op; 569650728199SRoman Kapl 569750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 569850728199SRoman Kapl tcgv_addr = tcg_temp_new(); 569950728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 570050728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 570150728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 570250728199SRoman Kapl tcg_temp_free(tcgv_addr); 570350728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 570450728199SRoman Kapl } 570550728199SRoman Kapl 5706fcf5ef2aSThomas Huth /* dst / dstt */ 5707fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5708fcf5ef2aSThomas Huth { 5709fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5710fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5711fcf5ef2aSThomas Huth } else { 5712fcf5ef2aSThomas Huth /* interpreted as no-op */ 5713fcf5ef2aSThomas Huth } 5714fcf5ef2aSThomas Huth } 5715fcf5ef2aSThomas Huth 5716fcf5ef2aSThomas Huth /* dstst /dststt */ 5717fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5718fcf5ef2aSThomas Huth { 5719fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5720fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5721fcf5ef2aSThomas Huth } else { 5722fcf5ef2aSThomas Huth /* interpreted as no-op */ 5723fcf5ef2aSThomas Huth } 5724fcf5ef2aSThomas Huth 5725fcf5ef2aSThomas Huth } 5726fcf5ef2aSThomas Huth 5727fcf5ef2aSThomas Huth /* dss / dssall */ 5728fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5729fcf5ef2aSThomas Huth { 5730fcf5ef2aSThomas Huth /* interpreted as no-op */ 5731fcf5ef2aSThomas Huth } 5732fcf5ef2aSThomas Huth 5733fcf5ef2aSThomas Huth /* icbi */ 5734fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5735fcf5ef2aSThomas Huth { 5736fcf5ef2aSThomas Huth TCGv t0; 5737fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5738fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5739fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5740fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5741fcf5ef2aSThomas Huth tcg_temp_free(t0); 5742fcf5ef2aSThomas Huth } 5743fcf5ef2aSThomas Huth 574450728199SRoman Kapl /* icbiep */ 574550728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 574650728199SRoman Kapl { 574750728199SRoman Kapl TCGv t0; 574850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 574950728199SRoman Kapl t0 = tcg_temp_new(); 575050728199SRoman Kapl gen_addr_reg_index(ctx, t0); 575150728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 575250728199SRoman Kapl tcg_temp_free(t0); 575350728199SRoman Kapl } 575450728199SRoman Kapl 5755fcf5ef2aSThomas Huth /* Optional: */ 5756fcf5ef2aSThomas Huth /* dcba */ 5757fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5758fcf5ef2aSThomas Huth { 5759efe843d8SDavid Gibson /* 5760efe843d8SDavid Gibson * interpreted as no-op 5761efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5762fcf5ef2aSThomas Huth * but does not generate any exception 5763fcf5ef2aSThomas Huth */ 5764fcf5ef2aSThomas Huth } 5765fcf5ef2aSThomas Huth 5766fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5767fcf5ef2aSThomas Huth /* Supervisor only: */ 5768fcf5ef2aSThomas Huth 5769fcf5ef2aSThomas Huth /* mfsr */ 5770fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5771fcf5ef2aSThomas Huth { 5772fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5773fcf5ef2aSThomas Huth GEN_PRIV; 5774fcf5ef2aSThomas Huth #else 5775fcf5ef2aSThomas Huth TCGv t0; 5776fcf5ef2aSThomas Huth 5777fcf5ef2aSThomas Huth CHK_SV; 5778fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5779fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5780fcf5ef2aSThomas Huth tcg_temp_free(t0); 5781fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5782fcf5ef2aSThomas Huth } 5783fcf5ef2aSThomas Huth 5784fcf5ef2aSThomas Huth /* mfsrin */ 5785fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5786fcf5ef2aSThomas Huth { 5787fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5788fcf5ef2aSThomas Huth GEN_PRIV; 5789fcf5ef2aSThomas Huth #else 5790fcf5ef2aSThomas Huth TCGv t0; 5791fcf5ef2aSThomas Huth 5792fcf5ef2aSThomas Huth CHK_SV; 5793fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5794e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5795fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5796fcf5ef2aSThomas Huth tcg_temp_free(t0); 5797fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5798fcf5ef2aSThomas Huth } 5799fcf5ef2aSThomas Huth 5800fcf5ef2aSThomas Huth /* mtsr */ 5801fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5802fcf5ef2aSThomas Huth { 5803fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5804fcf5ef2aSThomas Huth GEN_PRIV; 5805fcf5ef2aSThomas Huth #else 5806fcf5ef2aSThomas Huth TCGv t0; 5807fcf5ef2aSThomas Huth 5808fcf5ef2aSThomas Huth CHK_SV; 5809fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5810fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5811fcf5ef2aSThomas Huth tcg_temp_free(t0); 5812fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5813fcf5ef2aSThomas Huth } 5814fcf5ef2aSThomas Huth 5815fcf5ef2aSThomas Huth /* mtsrin */ 5816fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5817fcf5ef2aSThomas Huth { 5818fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5819fcf5ef2aSThomas Huth GEN_PRIV; 5820fcf5ef2aSThomas Huth #else 5821fcf5ef2aSThomas Huth TCGv t0; 5822fcf5ef2aSThomas Huth CHK_SV; 5823fcf5ef2aSThomas Huth 5824fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5825e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5826fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5827fcf5ef2aSThomas Huth tcg_temp_free(t0); 5828fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5829fcf5ef2aSThomas Huth } 5830fcf5ef2aSThomas Huth 5831fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5832fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5833fcf5ef2aSThomas Huth 5834fcf5ef2aSThomas Huth /* mfsr */ 5835fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5836fcf5ef2aSThomas Huth { 5837fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5838fcf5ef2aSThomas Huth GEN_PRIV; 5839fcf5ef2aSThomas Huth #else 5840fcf5ef2aSThomas Huth TCGv t0; 5841fcf5ef2aSThomas Huth 5842fcf5ef2aSThomas Huth CHK_SV; 5843fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5844fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5845fcf5ef2aSThomas Huth tcg_temp_free(t0); 5846fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5847fcf5ef2aSThomas Huth } 5848fcf5ef2aSThomas Huth 5849fcf5ef2aSThomas Huth /* mfsrin */ 5850fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5851fcf5ef2aSThomas Huth { 5852fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5853fcf5ef2aSThomas Huth GEN_PRIV; 5854fcf5ef2aSThomas Huth #else 5855fcf5ef2aSThomas Huth TCGv t0; 5856fcf5ef2aSThomas Huth 5857fcf5ef2aSThomas Huth CHK_SV; 5858fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5859e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5860fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5861fcf5ef2aSThomas Huth tcg_temp_free(t0); 5862fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5863fcf5ef2aSThomas Huth } 5864fcf5ef2aSThomas Huth 5865fcf5ef2aSThomas Huth /* mtsr */ 5866fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5867fcf5ef2aSThomas Huth { 5868fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5869fcf5ef2aSThomas Huth GEN_PRIV; 5870fcf5ef2aSThomas Huth #else 5871fcf5ef2aSThomas Huth TCGv t0; 5872fcf5ef2aSThomas Huth 5873fcf5ef2aSThomas Huth CHK_SV; 5874fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5875fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5876fcf5ef2aSThomas Huth tcg_temp_free(t0); 5877fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5878fcf5ef2aSThomas Huth } 5879fcf5ef2aSThomas Huth 5880fcf5ef2aSThomas Huth /* mtsrin */ 5881fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5882fcf5ef2aSThomas Huth { 5883fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5884fcf5ef2aSThomas Huth GEN_PRIV; 5885fcf5ef2aSThomas Huth #else 5886fcf5ef2aSThomas Huth TCGv t0; 5887fcf5ef2aSThomas Huth 5888fcf5ef2aSThomas Huth CHK_SV; 5889fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5890e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5891fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5892fcf5ef2aSThomas Huth tcg_temp_free(t0); 5893fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5894fcf5ef2aSThomas Huth } 5895fcf5ef2aSThomas Huth 5896fcf5ef2aSThomas Huth /* slbmte */ 5897fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5898fcf5ef2aSThomas Huth { 5899fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5900fcf5ef2aSThomas Huth GEN_PRIV; 5901fcf5ef2aSThomas Huth #else 5902fcf5ef2aSThomas Huth CHK_SV; 5903fcf5ef2aSThomas Huth 5904fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5905fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5906fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5907fcf5ef2aSThomas Huth } 5908fcf5ef2aSThomas Huth 5909fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5910fcf5ef2aSThomas Huth { 5911fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5912fcf5ef2aSThomas Huth GEN_PRIV; 5913fcf5ef2aSThomas Huth #else 5914fcf5ef2aSThomas Huth CHK_SV; 5915fcf5ef2aSThomas Huth 5916fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5917fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5918fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5919fcf5ef2aSThomas Huth } 5920fcf5ef2aSThomas Huth 5921fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5922fcf5ef2aSThomas Huth { 5923fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5924fcf5ef2aSThomas Huth GEN_PRIV; 5925fcf5ef2aSThomas Huth #else 5926fcf5ef2aSThomas Huth CHK_SV; 5927fcf5ef2aSThomas Huth 5928fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5929fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5930fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5931fcf5ef2aSThomas Huth } 5932fcf5ef2aSThomas Huth 5933fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5934fcf5ef2aSThomas Huth { 5935fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5936fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5937fcf5ef2aSThomas Huth #else 5938fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5939fcf5ef2aSThomas Huth 5940fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5941fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5942fcf5ef2aSThomas Huth return; 5943fcf5ef2aSThomas Huth } 5944fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5945fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5946fcf5ef2aSThomas Huth l1 = gen_new_label(); 5947fcf5ef2aSThomas Huth l2 = gen_new_label(); 5948fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5949fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5950efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5951fcf5ef2aSThomas Huth tcg_gen_br(l2); 5952fcf5ef2aSThomas Huth gen_set_label(l1); 5953fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5954fcf5ef2aSThomas Huth gen_set_label(l2); 5955fcf5ef2aSThomas Huth #endif 5956fcf5ef2aSThomas Huth } 5957fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5958fcf5ef2aSThomas Huth 5959fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5960fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5961fcf5ef2aSThomas Huth 5962fcf5ef2aSThomas Huth /* tlbia */ 5963fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5964fcf5ef2aSThomas Huth { 5965fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5966fcf5ef2aSThomas Huth GEN_PRIV; 5967fcf5ef2aSThomas Huth #else 5968fcf5ef2aSThomas Huth CHK_HV; 5969fcf5ef2aSThomas Huth 5970fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5971fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5972fcf5ef2aSThomas Huth } 5973fcf5ef2aSThomas Huth 5974fcf5ef2aSThomas Huth /* tlbiel */ 5975fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5976fcf5ef2aSThomas Huth { 5977fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5978fcf5ef2aSThomas Huth GEN_PRIV; 5979fcf5ef2aSThomas Huth #else 5980fcf5ef2aSThomas Huth CHK_SV; 5981fcf5ef2aSThomas Huth 5982fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5983fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5984fcf5ef2aSThomas Huth } 5985fcf5ef2aSThomas Huth 5986fcf5ef2aSThomas Huth /* tlbie */ 5987fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5988fcf5ef2aSThomas Huth { 5989fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5990fcf5ef2aSThomas Huth GEN_PRIV; 5991fcf5ef2aSThomas Huth #else 5992fcf5ef2aSThomas Huth TCGv_i32 t1; 5993c6fd28fdSSuraj Jitindar Singh 5994c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 599591c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5996c6fd28fdSSuraj Jitindar Singh } else { 5997c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5998c6fd28fdSSuraj Jitindar Singh } 5999fcf5ef2aSThomas Huth 6000fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 6001fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6002fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 6003fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 6004fcf5ef2aSThomas Huth tcg_temp_free(t0); 6005fcf5ef2aSThomas Huth } else { 6006fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6007fcf5ef2aSThomas Huth } 6008fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 6009fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6010fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 6011fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6012fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6013fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6014fcf5ef2aSThomas Huth } 6015fcf5ef2aSThomas Huth 6016fcf5ef2aSThomas Huth /* tlbsync */ 6017fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 6018fcf5ef2aSThomas Huth { 6019fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6020fcf5ef2aSThomas Huth GEN_PRIV; 6021fcf5ef2aSThomas Huth #else 602291c60f12SCédric Le Goater 602391c60f12SCédric Le Goater if (ctx->gtse) { 602491c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 602591c60f12SCédric Le Goater } else { 602691c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 602791c60f12SCédric Le Goater } 6028fcf5ef2aSThomas Huth 6029fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 6030fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 6031fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 6032fcf5ef2aSThomas Huth } 6033fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6034fcf5ef2aSThomas Huth } 6035fcf5ef2aSThomas Huth 6036fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6037fcf5ef2aSThomas Huth /* slbia */ 6038fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 6039fcf5ef2aSThomas Huth { 6040fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6041fcf5ef2aSThomas Huth GEN_PRIV; 6042fcf5ef2aSThomas Huth #else 60430418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 60440418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 60450418bf78SNicholas Piggin 6046fcf5ef2aSThomas Huth CHK_SV; 6047fcf5ef2aSThomas Huth 60480418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 60493119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 6050fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6051fcf5ef2aSThomas Huth } 6052fcf5ef2aSThomas Huth 6053fcf5ef2aSThomas Huth /* slbie */ 6054fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 6055fcf5ef2aSThomas Huth { 6056fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6057fcf5ef2aSThomas Huth GEN_PRIV; 6058fcf5ef2aSThomas Huth #else 6059fcf5ef2aSThomas Huth CHK_SV; 6060fcf5ef2aSThomas Huth 6061fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6062fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6063fcf5ef2aSThomas Huth } 6064a63f1dfcSNikunj A Dadhania 6065a63f1dfcSNikunj A Dadhania /* slbieg */ 6066a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 6067a63f1dfcSNikunj A Dadhania { 6068a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 6069a63f1dfcSNikunj A Dadhania GEN_PRIV; 6070a63f1dfcSNikunj A Dadhania #else 6071a63f1dfcSNikunj A Dadhania CHK_SV; 6072a63f1dfcSNikunj A Dadhania 6073a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6074a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 6075a63f1dfcSNikunj A Dadhania } 6076a63f1dfcSNikunj A Dadhania 607762d897caSNikunj A Dadhania /* slbsync */ 607862d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 607962d897caSNikunj A Dadhania { 608062d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 608162d897caSNikunj A Dadhania GEN_PRIV; 608262d897caSNikunj A Dadhania #else 608362d897caSNikunj A Dadhania CHK_SV; 608462d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 608562d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 608662d897caSNikunj A Dadhania } 608762d897caSNikunj A Dadhania 6088fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6089fcf5ef2aSThomas Huth 6090fcf5ef2aSThomas Huth /*** External control ***/ 6091fcf5ef2aSThomas Huth /* Optional: */ 6092fcf5ef2aSThomas Huth 6093fcf5ef2aSThomas Huth /* eciwx */ 6094fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 6095fcf5ef2aSThomas Huth { 6096fcf5ef2aSThomas Huth TCGv t0; 6097fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6098fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6099fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6100fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6101c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6102c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6103fcf5ef2aSThomas Huth tcg_temp_free(t0); 6104fcf5ef2aSThomas Huth } 6105fcf5ef2aSThomas Huth 6106fcf5ef2aSThomas Huth /* ecowx */ 6107fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 6108fcf5ef2aSThomas Huth { 6109fcf5ef2aSThomas Huth TCGv t0; 6110fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6111fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6112fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6113fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6114c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6115c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6116fcf5ef2aSThomas Huth tcg_temp_free(t0); 6117fcf5ef2aSThomas Huth } 6118fcf5ef2aSThomas Huth 6119fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 6120fcf5ef2aSThomas Huth 6121fcf5ef2aSThomas Huth /* abs - abs. */ 6122fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 6123fcf5ef2aSThomas Huth { 6124fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6125fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6126fe21b785SRichard Henderson 6127fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6128efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6129fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6130fcf5ef2aSThomas Huth } 6131efe843d8SDavid Gibson } 6132fcf5ef2aSThomas Huth 6133fcf5ef2aSThomas Huth /* abso - abso. */ 6134fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 6135fcf5ef2aSThomas Huth { 6136fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6137fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6138fe21b785SRichard Henderson 6139fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 6140fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6141fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 6142efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6143fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6144fcf5ef2aSThomas Huth } 6145efe843d8SDavid Gibson } 6146fcf5ef2aSThomas Huth 6147fcf5ef2aSThomas Huth /* clcs */ 6148fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 6149fcf5ef2aSThomas Huth { 6150fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 6151fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6152fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6153fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 6154fcf5ef2aSThomas Huth } 6155fcf5ef2aSThomas Huth 6156fcf5ef2aSThomas Huth /* div - div. */ 6157fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 6158fcf5ef2aSThomas Huth { 6159fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6160fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6161efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6162fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6163fcf5ef2aSThomas Huth } 6164efe843d8SDavid Gibson } 6165fcf5ef2aSThomas Huth 6166fcf5ef2aSThomas Huth /* divo - divo. */ 6167fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 6168fcf5ef2aSThomas Huth { 6169fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6170fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6171efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6172fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6173fcf5ef2aSThomas Huth } 6174efe843d8SDavid Gibson } 6175fcf5ef2aSThomas Huth 6176fcf5ef2aSThomas Huth /* divs - divs. */ 6177fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 6178fcf5ef2aSThomas Huth { 6179fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6180fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6181efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6182fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6183fcf5ef2aSThomas Huth } 6184efe843d8SDavid Gibson } 6185fcf5ef2aSThomas Huth 6186fcf5ef2aSThomas Huth /* divso - divso. */ 6187fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 6188fcf5ef2aSThomas Huth { 6189fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 6190fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6191efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6192fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6193fcf5ef2aSThomas Huth } 6194efe843d8SDavid Gibson } 6195fcf5ef2aSThomas Huth 6196fcf5ef2aSThomas Huth /* doz - doz. */ 6197fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 6198fcf5ef2aSThomas Huth { 6199fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6200fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6201efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6202efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6203efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 6204efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 6205fcf5ef2aSThomas Huth tcg_gen_br(l2); 6206fcf5ef2aSThomas Huth gen_set_label(l1); 6207fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6208fcf5ef2aSThomas Huth gen_set_label(l2); 6209efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6210fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6211fcf5ef2aSThomas Huth } 6212efe843d8SDavid Gibson } 6213fcf5ef2aSThomas Huth 6214fcf5ef2aSThomas Huth /* dozo - dozo. */ 6215fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 6216fcf5ef2aSThomas Huth { 6217fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6218fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6219fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6220fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6221fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6222fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6223fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6224efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6225efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6226fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6227fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6228fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 6229fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6230fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 6231fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6232fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6233fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6234fcf5ef2aSThomas Huth tcg_gen_br(l2); 6235fcf5ef2aSThomas Huth gen_set_label(l1); 6236fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6237fcf5ef2aSThomas Huth gen_set_label(l2); 6238fcf5ef2aSThomas Huth tcg_temp_free(t0); 6239fcf5ef2aSThomas Huth tcg_temp_free(t1); 6240fcf5ef2aSThomas Huth tcg_temp_free(t2); 6241efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6242fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6243fcf5ef2aSThomas Huth } 6244efe843d8SDavid Gibson } 6245fcf5ef2aSThomas Huth 6246fcf5ef2aSThomas Huth /* dozi */ 6247fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 6248fcf5ef2aSThomas Huth { 6249fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 6250fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6251fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6252fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 6253fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 6254fcf5ef2aSThomas Huth tcg_gen_br(l2); 6255fcf5ef2aSThomas Huth gen_set_label(l1); 6256fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6257fcf5ef2aSThomas Huth gen_set_label(l2); 6258efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6259fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6260fcf5ef2aSThomas Huth } 6261efe843d8SDavid Gibson } 6262fcf5ef2aSThomas Huth 6263fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 6264fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 6265fcf5ef2aSThomas Huth { 6266fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6267fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 6268fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 6269fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 6270fcf5ef2aSThomas Huth 6271fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6272fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 6273fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6274fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 6275fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 6276fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 6277fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 6278efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6279fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 6280efe843d8SDavid Gibson } 6281fcf5ef2aSThomas Huth tcg_temp_free(t0); 6282fcf5ef2aSThomas Huth } 6283fcf5ef2aSThomas Huth 6284fcf5ef2aSThomas Huth /* maskg - maskg. */ 6285fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 6286fcf5ef2aSThomas Huth { 6287fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6288fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6289fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6290fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6291fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 6292fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 6293fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6294fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 6295fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 6296fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 6297fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 6298fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 6299fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 6300fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6301fcf5ef2aSThomas Huth gen_set_label(l1); 6302fcf5ef2aSThomas Huth tcg_temp_free(t0); 6303fcf5ef2aSThomas Huth tcg_temp_free(t1); 6304fcf5ef2aSThomas Huth tcg_temp_free(t2); 6305fcf5ef2aSThomas Huth tcg_temp_free(t3); 6306efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6307fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6308fcf5ef2aSThomas Huth } 6309efe843d8SDavid Gibson } 6310fcf5ef2aSThomas Huth 6311fcf5ef2aSThomas Huth /* maskir - maskir. */ 6312fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 6313fcf5ef2aSThomas Huth { 6314fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6315fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6316fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6317fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6318fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6319fcf5ef2aSThomas Huth tcg_temp_free(t0); 6320fcf5ef2aSThomas Huth tcg_temp_free(t1); 6321efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6322fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6323fcf5ef2aSThomas Huth } 6324efe843d8SDavid Gibson } 6325fcf5ef2aSThomas Huth 6326fcf5ef2aSThomas Huth /* mul - mul. */ 6327fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 6328fcf5ef2aSThomas Huth { 6329fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6330fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6331fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6332fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6333fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6334fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6335fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6336fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6337fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6338fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6339fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6340fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6341fcf5ef2aSThomas Huth tcg_temp_free(t2); 6342efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6343fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6344fcf5ef2aSThomas Huth } 6345efe843d8SDavid Gibson } 6346fcf5ef2aSThomas Huth 6347fcf5ef2aSThomas Huth /* mulo - mulo. */ 6348fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6349fcf5ef2aSThomas Huth { 6350fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6351fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6352fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6353fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6354fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6355fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6356fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6357fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6358fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6359fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6360fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6361fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6362fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6363fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6364fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6365fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6366fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6367fcf5ef2aSThomas Huth gen_set_label(l1); 6368fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6369fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6370fcf5ef2aSThomas Huth tcg_temp_free(t2); 6371efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6372fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6373fcf5ef2aSThomas Huth } 6374efe843d8SDavid Gibson } 6375fcf5ef2aSThomas Huth 6376fcf5ef2aSThomas Huth /* nabs - nabs. */ 6377fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6378fcf5ef2aSThomas Huth { 6379fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6380fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6381fe21b785SRichard Henderson 6382fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6383fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6384efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6385fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6386fcf5ef2aSThomas Huth } 6387efe843d8SDavid Gibson } 6388fcf5ef2aSThomas Huth 6389fcf5ef2aSThomas Huth /* nabso - nabso. */ 6390fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6391fcf5ef2aSThomas Huth { 6392fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6393fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6394fe21b785SRichard Henderson 6395fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6396fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6397fcf5ef2aSThomas Huth /* nabs never overflows */ 6398fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6399efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6400fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6401fcf5ef2aSThomas Huth } 6402efe843d8SDavid Gibson } 6403fcf5ef2aSThomas Huth 6404fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6405fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6406fcf5ef2aSThomas Huth { 6407fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6408fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6409fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6410fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6411fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6412fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6413efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6414efe843d8SDavid Gibson ~MASK(mb, me)); 6415fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6416fcf5ef2aSThomas Huth tcg_temp_free(t0); 6417efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6418fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6419fcf5ef2aSThomas Huth } 6420efe843d8SDavid Gibson } 6421fcf5ef2aSThomas Huth 6422fcf5ef2aSThomas Huth /* rrib - rrib. */ 6423fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6424fcf5ef2aSThomas Huth { 6425fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6426fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6427fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6428fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6429fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6430fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6431fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6432fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6433fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6434fcf5ef2aSThomas Huth tcg_temp_free(t0); 6435fcf5ef2aSThomas Huth tcg_temp_free(t1); 6436efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6437fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6438fcf5ef2aSThomas Huth } 6439efe843d8SDavid Gibson } 6440fcf5ef2aSThomas Huth 6441fcf5ef2aSThomas Huth /* sle - sle. */ 6442fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6443fcf5ef2aSThomas Huth { 6444fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6445fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6446fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6447fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6448fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6449fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6450fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6451fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6452fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6453fcf5ef2aSThomas Huth tcg_temp_free(t0); 6454fcf5ef2aSThomas Huth tcg_temp_free(t1); 6455efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6456fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6457fcf5ef2aSThomas Huth } 6458efe843d8SDavid Gibson } 6459fcf5ef2aSThomas Huth 6460fcf5ef2aSThomas Huth /* sleq - sleq. */ 6461fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6462fcf5ef2aSThomas Huth { 6463fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6464fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6465fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6466fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6467fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6468fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6469fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6470fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6471fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6472fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6473fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6474fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6475fcf5ef2aSThomas Huth tcg_temp_free(t0); 6476fcf5ef2aSThomas Huth tcg_temp_free(t1); 6477fcf5ef2aSThomas Huth tcg_temp_free(t2); 6478efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6479fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6480fcf5ef2aSThomas Huth } 6481efe843d8SDavid Gibson } 6482fcf5ef2aSThomas Huth 6483fcf5ef2aSThomas Huth /* sliq - sliq. */ 6484fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6485fcf5ef2aSThomas Huth { 6486fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6487fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6488fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6489fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6490fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6491fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6492fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6493fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6494fcf5ef2aSThomas Huth tcg_temp_free(t0); 6495fcf5ef2aSThomas Huth tcg_temp_free(t1); 6496efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6497fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6498fcf5ef2aSThomas Huth } 6499efe843d8SDavid Gibson } 6500fcf5ef2aSThomas Huth 6501fcf5ef2aSThomas Huth /* slliq - slliq. */ 6502fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6503fcf5ef2aSThomas Huth { 6504fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6505fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6506fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6507fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6508fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6509fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6510fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6511fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6512fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6513fcf5ef2aSThomas Huth tcg_temp_free(t0); 6514fcf5ef2aSThomas Huth tcg_temp_free(t1); 6515efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6516fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6517fcf5ef2aSThomas Huth } 6518efe843d8SDavid Gibson } 6519fcf5ef2aSThomas Huth 6520fcf5ef2aSThomas Huth /* sllq - sllq. */ 6521fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6522fcf5ef2aSThomas Huth { 6523fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6524fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6525fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6526fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6527fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6528fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6529fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6530fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6531fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6532fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6533fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6534fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6535fcf5ef2aSThomas Huth tcg_gen_br(l2); 6536fcf5ef2aSThomas Huth gen_set_label(l1); 6537fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6538fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6539fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6540fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6541fcf5ef2aSThomas Huth gen_set_label(l2); 6542fcf5ef2aSThomas Huth tcg_temp_free(t0); 6543fcf5ef2aSThomas Huth tcg_temp_free(t1); 6544fcf5ef2aSThomas Huth tcg_temp_free(t2); 6545efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6546fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6547fcf5ef2aSThomas Huth } 6548efe843d8SDavid Gibson } 6549fcf5ef2aSThomas Huth 6550fcf5ef2aSThomas Huth /* slq - slq. */ 6551fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6552fcf5ef2aSThomas Huth { 6553fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6554fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6555fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6556fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6557fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6558fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6559fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6560fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6561fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6562fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6563fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6564fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6565fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6566fcf5ef2aSThomas Huth gen_set_label(l1); 6567fcf5ef2aSThomas Huth tcg_temp_free(t0); 6568fcf5ef2aSThomas Huth tcg_temp_free(t1); 6569efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6570fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6571fcf5ef2aSThomas Huth } 6572efe843d8SDavid Gibson } 6573fcf5ef2aSThomas Huth 6574fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6575fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6576fcf5ef2aSThomas Huth { 6577fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6578fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6579fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6580fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6581fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6582fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6583fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6584fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6585fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6586fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6587fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6588fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6589fcf5ef2aSThomas Huth gen_set_label(l1); 6590fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6591fcf5ef2aSThomas Huth tcg_temp_free(t0); 6592fcf5ef2aSThomas Huth tcg_temp_free(t1); 6593efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6594fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6595fcf5ef2aSThomas Huth } 6596efe843d8SDavid Gibson } 6597fcf5ef2aSThomas Huth 6598fcf5ef2aSThomas Huth /* sraq - sraq. */ 6599fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6600fcf5ef2aSThomas Huth { 6601fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6602fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6603fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6604fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6605fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6606fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6607fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6608fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6609fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6610fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6611fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6612fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6613fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6614fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6615fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6616fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6617fcf5ef2aSThomas Huth gen_set_label(l1); 6618fcf5ef2aSThomas Huth tcg_temp_free(t0); 6619fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6620fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6621fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6622fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6623fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6624fcf5ef2aSThomas Huth gen_set_label(l2); 6625fcf5ef2aSThomas Huth tcg_temp_free(t1); 6626fcf5ef2aSThomas Huth tcg_temp_free(t2); 6627efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6628fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6629fcf5ef2aSThomas Huth } 6630efe843d8SDavid Gibson } 6631fcf5ef2aSThomas Huth 6632fcf5ef2aSThomas Huth /* sre - sre. */ 6633fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6634fcf5ef2aSThomas Huth { 6635fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6636fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6637fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6638fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6639fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6640fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6641fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6642fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6643fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6644fcf5ef2aSThomas Huth tcg_temp_free(t0); 6645fcf5ef2aSThomas Huth tcg_temp_free(t1); 6646efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6647fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6648fcf5ef2aSThomas Huth } 6649efe843d8SDavid Gibson } 6650fcf5ef2aSThomas Huth 6651fcf5ef2aSThomas Huth /* srea - srea. */ 6652fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6653fcf5ef2aSThomas Huth { 6654fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6655fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6656fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6657fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6658fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6659fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6660fcf5ef2aSThomas Huth tcg_temp_free(t0); 6661fcf5ef2aSThomas Huth tcg_temp_free(t1); 6662efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6663fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6664fcf5ef2aSThomas Huth } 6665efe843d8SDavid Gibson } 6666fcf5ef2aSThomas Huth 6667fcf5ef2aSThomas Huth /* sreq */ 6668fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6669fcf5ef2aSThomas Huth { 6670fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6671fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6672fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6673fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6674fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6675fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6676fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6677fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6678fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6679fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6680fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6681fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6682fcf5ef2aSThomas Huth tcg_temp_free(t0); 6683fcf5ef2aSThomas Huth tcg_temp_free(t1); 6684fcf5ef2aSThomas Huth tcg_temp_free(t2); 6685efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6686fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6687fcf5ef2aSThomas Huth } 6688efe843d8SDavid Gibson } 6689fcf5ef2aSThomas Huth 6690fcf5ef2aSThomas Huth /* sriq */ 6691fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6692fcf5ef2aSThomas Huth { 6693fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6694fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6695fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6696fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6697fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6698fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6699fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6700fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6701fcf5ef2aSThomas Huth tcg_temp_free(t0); 6702fcf5ef2aSThomas Huth tcg_temp_free(t1); 6703efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6704fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6705fcf5ef2aSThomas Huth } 6706efe843d8SDavid Gibson } 6707fcf5ef2aSThomas Huth 6708fcf5ef2aSThomas Huth /* srliq */ 6709fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6710fcf5ef2aSThomas Huth { 6711fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6712fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6713fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6714fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6715fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6716fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6717fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6718fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6719fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6720fcf5ef2aSThomas Huth tcg_temp_free(t0); 6721fcf5ef2aSThomas Huth tcg_temp_free(t1); 6722efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6723fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6724fcf5ef2aSThomas Huth } 6725efe843d8SDavid Gibson } 6726fcf5ef2aSThomas Huth 6727fcf5ef2aSThomas Huth /* srlq */ 6728fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6729fcf5ef2aSThomas Huth { 6730fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6731fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6732fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6733fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6734fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6735fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6736fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6737fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6738fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6739fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6740fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6741fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6742fcf5ef2aSThomas Huth tcg_gen_br(l2); 6743fcf5ef2aSThomas Huth gen_set_label(l1); 6744fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6745fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6746fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6747fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6748fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6749fcf5ef2aSThomas Huth gen_set_label(l2); 6750fcf5ef2aSThomas Huth tcg_temp_free(t0); 6751fcf5ef2aSThomas Huth tcg_temp_free(t1); 6752fcf5ef2aSThomas Huth tcg_temp_free(t2); 6753efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6754fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6755fcf5ef2aSThomas Huth } 6756efe843d8SDavid Gibson } 6757fcf5ef2aSThomas Huth 6758fcf5ef2aSThomas Huth /* srq */ 6759fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6760fcf5ef2aSThomas Huth { 6761fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6762fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6763fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6764fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6765fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6766fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6767fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6768fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6769fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6770fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6771fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6772fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6773fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6774fcf5ef2aSThomas Huth gen_set_label(l1); 6775fcf5ef2aSThomas Huth tcg_temp_free(t0); 6776fcf5ef2aSThomas Huth tcg_temp_free(t1); 6777efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6778fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6779fcf5ef2aSThomas Huth } 6780efe843d8SDavid Gibson } 6781fcf5ef2aSThomas Huth 6782fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6783fcf5ef2aSThomas Huth 6784fcf5ef2aSThomas Huth /* dsa */ 6785fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6786fcf5ef2aSThomas Huth { 6787fcf5ef2aSThomas Huth /* XXX: TODO */ 6788fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6789fcf5ef2aSThomas Huth } 6790fcf5ef2aSThomas Huth 6791fcf5ef2aSThomas Huth /* esa */ 6792fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6793fcf5ef2aSThomas Huth { 6794fcf5ef2aSThomas Huth /* XXX: TODO */ 6795fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6796fcf5ef2aSThomas Huth } 6797fcf5ef2aSThomas Huth 6798fcf5ef2aSThomas Huth /* mfrom */ 6799fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6800fcf5ef2aSThomas Huth { 6801fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6802fcf5ef2aSThomas Huth GEN_PRIV; 6803fcf5ef2aSThomas Huth #else 6804fcf5ef2aSThomas Huth CHK_SV; 6805fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6806fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6807fcf5ef2aSThomas Huth } 6808fcf5ef2aSThomas Huth 6809fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6810fcf5ef2aSThomas Huth 6811fcf5ef2aSThomas Huth /* tlbld */ 6812fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6813fcf5ef2aSThomas Huth { 6814fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6815fcf5ef2aSThomas Huth GEN_PRIV; 6816fcf5ef2aSThomas Huth #else 6817fcf5ef2aSThomas Huth CHK_SV; 6818fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6819fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6820fcf5ef2aSThomas Huth } 6821fcf5ef2aSThomas Huth 6822fcf5ef2aSThomas Huth /* tlbli */ 6823fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6824fcf5ef2aSThomas Huth { 6825fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6826fcf5ef2aSThomas Huth GEN_PRIV; 6827fcf5ef2aSThomas Huth #else 6828fcf5ef2aSThomas Huth CHK_SV; 6829fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6830fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6831fcf5ef2aSThomas Huth } 6832fcf5ef2aSThomas Huth 6833fcf5ef2aSThomas Huth /* 74xx TLB management */ 6834fcf5ef2aSThomas Huth 6835fcf5ef2aSThomas Huth /* tlbld */ 6836fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6837fcf5ef2aSThomas Huth { 6838fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6839fcf5ef2aSThomas Huth GEN_PRIV; 6840fcf5ef2aSThomas Huth #else 6841fcf5ef2aSThomas Huth CHK_SV; 6842fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6843fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6844fcf5ef2aSThomas Huth } 6845fcf5ef2aSThomas Huth 6846fcf5ef2aSThomas Huth /* tlbli */ 6847fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6848fcf5ef2aSThomas Huth { 6849fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6850fcf5ef2aSThomas Huth GEN_PRIV; 6851fcf5ef2aSThomas Huth #else 6852fcf5ef2aSThomas Huth CHK_SV; 6853fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6854fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6855fcf5ef2aSThomas Huth } 6856fcf5ef2aSThomas Huth 6857fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6858fcf5ef2aSThomas Huth 6859fcf5ef2aSThomas Huth /* clf */ 6860fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6861fcf5ef2aSThomas Huth { 6862fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6863fcf5ef2aSThomas Huth } 6864fcf5ef2aSThomas Huth 6865fcf5ef2aSThomas Huth /* cli */ 6866fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6867fcf5ef2aSThomas Huth { 6868fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6869fcf5ef2aSThomas Huth GEN_PRIV; 6870fcf5ef2aSThomas Huth #else 6871fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6872fcf5ef2aSThomas Huth CHK_SV; 6873fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6874fcf5ef2aSThomas Huth } 6875fcf5ef2aSThomas Huth 6876fcf5ef2aSThomas Huth /* dclst */ 6877fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6878fcf5ef2aSThomas Huth { 6879fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6880fcf5ef2aSThomas Huth } 6881fcf5ef2aSThomas Huth 6882fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6883fcf5ef2aSThomas Huth { 6884fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6885fcf5ef2aSThomas Huth GEN_PRIV; 6886fcf5ef2aSThomas Huth #else 6887fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6888fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6889fcf5ef2aSThomas Huth TCGv t0; 6890fcf5ef2aSThomas Huth 6891fcf5ef2aSThomas Huth CHK_SV; 6892fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6893fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6894e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6895fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6896fcf5ef2aSThomas Huth tcg_temp_free(t0); 6897efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6898fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6899efe843d8SDavid Gibson } 6900fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6901fcf5ef2aSThomas Huth } 6902fcf5ef2aSThomas Huth 6903fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6904fcf5ef2aSThomas Huth { 6905fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6906fcf5ef2aSThomas Huth GEN_PRIV; 6907fcf5ef2aSThomas Huth #else 6908fcf5ef2aSThomas Huth TCGv t0; 6909fcf5ef2aSThomas Huth 6910fcf5ef2aSThomas Huth CHK_SV; 6911fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6912fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6913fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6914fcf5ef2aSThomas Huth tcg_temp_free(t0); 6915fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6916fcf5ef2aSThomas Huth } 6917fcf5ef2aSThomas Huth 6918fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6919fcf5ef2aSThomas Huth { 6920fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6921fcf5ef2aSThomas Huth GEN_PRIV; 6922fcf5ef2aSThomas Huth #else 6923fcf5ef2aSThomas Huth CHK_SV; 6924fcf5ef2aSThomas Huth 6925fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 6926fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6927fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6928fcf5ef2aSThomas Huth } 6929fcf5ef2aSThomas Huth 6930fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6931fcf5ef2aSThomas Huth 6932fcf5ef2aSThomas Huth /* BookE specific instructions */ 6933fcf5ef2aSThomas Huth 6934fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6935fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6936fcf5ef2aSThomas Huth { 6937fcf5ef2aSThomas Huth /* XXX: TODO */ 6938fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6939fcf5ef2aSThomas Huth } 6940fcf5ef2aSThomas Huth 6941fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6942fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6943fcf5ef2aSThomas Huth { 6944fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6945fcf5ef2aSThomas Huth GEN_PRIV; 6946fcf5ef2aSThomas Huth #else 6947fcf5ef2aSThomas Huth TCGv t0; 6948fcf5ef2aSThomas Huth 6949fcf5ef2aSThomas Huth CHK_SV; 6950fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6951fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6952fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6953fcf5ef2aSThomas Huth tcg_temp_free(t0); 6954fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6955fcf5ef2aSThomas Huth } 6956fcf5ef2aSThomas Huth 6957fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6958fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6959fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6960fcf5ef2aSThomas Huth { 6961fcf5ef2aSThomas Huth TCGv t0, t1; 6962fcf5ef2aSThomas Huth 6963fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6964fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6965fcf5ef2aSThomas Huth 6966fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6967fcf5ef2aSThomas Huth case 0x05: 6968fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6969fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6970fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6971fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6972fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6973fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6974fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6975fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6976fcf5ef2aSThomas Huth break; 6977fcf5ef2aSThomas Huth case 0x04: 6978fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6979fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6980fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6981fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6982fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6983fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6984fcf5ef2aSThomas Huth break; 6985fcf5ef2aSThomas Huth case 0x01: 6986fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6987fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6988fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6989fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6990fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6991fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6992fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6993fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6994fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6995fcf5ef2aSThomas Huth break; 6996fcf5ef2aSThomas Huth case 0x00: 6997fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6998fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6999fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7000fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 7001fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 7002fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 7003fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 7004fcf5ef2aSThomas Huth break; 7005fcf5ef2aSThomas Huth case 0x0D: 7006fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 7007fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 7008fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 7009fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 7010fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7011fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 7012fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 7013fcf5ef2aSThomas Huth break; 7014fcf5ef2aSThomas Huth case 0x0C: 7015fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 7016fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 7017fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7018fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 7019fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 7020fcf5ef2aSThomas Huth break; 7021fcf5ef2aSThomas Huth } 7022fcf5ef2aSThomas Huth if (opc2 & 0x04) { 7023fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 7024fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 7025fcf5ef2aSThomas Huth if (opc2 & 0x02) { 7026fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 7027fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 7028fcf5ef2aSThomas Huth } else { 7029fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 7030fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 7031fcf5ef2aSThomas Huth } 7032fcf5ef2aSThomas Huth 7033fcf5ef2aSThomas Huth if (opc3 & 0x12) { 7034fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 7035fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7036fcf5ef2aSThomas Huth 7037fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7038fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 7039fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 7040fcf5ef2aSThomas Huth } 7041fcf5ef2aSThomas Huth if (opc3 & 0x01) { 7042fcf5ef2aSThomas Huth /* Signed */ 7043fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 7044fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 7045fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 7046fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 7047fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7048fcf5ef2aSThomas Huth /* Saturate */ 7049fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 7050fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 7051fcf5ef2aSThomas Huth } 7052fcf5ef2aSThomas Huth } else { 7053fcf5ef2aSThomas Huth /* Unsigned */ 7054fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 7055fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7056fcf5ef2aSThomas Huth /* Saturate */ 7057fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 7058fcf5ef2aSThomas Huth } 7059fcf5ef2aSThomas Huth } 7060fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7061fcf5ef2aSThomas Huth /* Check overflow */ 7062fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 7063fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 7064fcf5ef2aSThomas Huth } 7065fcf5ef2aSThomas Huth gen_set_label(l1); 7066fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 7067fcf5ef2aSThomas Huth } 7068fcf5ef2aSThomas Huth } else { 7069fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 7070fcf5ef2aSThomas Huth } 7071fcf5ef2aSThomas Huth tcg_temp_free(t0); 7072fcf5ef2aSThomas Huth tcg_temp_free(t1); 7073fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 7074fcf5ef2aSThomas Huth /* Update Rc0 */ 7075fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 7076fcf5ef2aSThomas Huth } 7077fcf5ef2aSThomas Huth } 7078fcf5ef2aSThomas Huth 7079fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7080fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 7081fcf5ef2aSThomas Huth { \ 7082fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 7083fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 7084fcf5ef2aSThomas Huth } 7085fcf5ef2aSThomas Huth 7086fcf5ef2aSThomas Huth /* macchw - macchw. */ 7087fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 7088fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 7089fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 7090fcf5ef2aSThomas Huth /* macchws - macchws. */ 7091fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 7092fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 7093fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 7094fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 7095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 7096fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 7097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 7098fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 7099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 7100fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 7101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 7102fcf5ef2aSThomas Huth /* machhw - machhw. */ 7103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 7104fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 7105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 7106fcf5ef2aSThomas Huth /* machhws - machhws. */ 7107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 7108fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 7109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 7110fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 7111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 7112fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 7113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 7114fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 7115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 7116fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 7117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 7118fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 7119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 7120fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 7121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 7122fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 7123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 7124fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 7125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 7126fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 7127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 7128fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 7129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 7130fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 7131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 7132fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 7133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 7134fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 7135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 7136fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 7137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 7138fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 7139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 7140fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 7141fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 7142fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 7143fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 7144fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 7145fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 7146fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 7147fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 7148fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 7149fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 7150fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 7151fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 7152fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 7153fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 7154fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 7155fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 7156fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 7157fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 7158fcf5ef2aSThomas Huth 7159fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 7160fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 7161fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 7162fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 7163fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 7164fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 7165fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7166fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 7167fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7168fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 7169fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7170fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 7171fcf5ef2aSThomas Huth 7172fcf5ef2aSThomas Huth /* mfdcr */ 7173fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 7174fcf5ef2aSThomas Huth { 7175fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7176fcf5ef2aSThomas Huth GEN_PRIV; 7177fcf5ef2aSThomas Huth #else 7178fcf5ef2aSThomas Huth TCGv dcrn; 7179fcf5ef2aSThomas Huth 7180fcf5ef2aSThomas Huth CHK_SV; 7181fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7182fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 7183fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7184fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7185fcf5ef2aSThomas Huth } 7186fcf5ef2aSThomas Huth 7187fcf5ef2aSThomas Huth /* mtdcr */ 7188fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 7189fcf5ef2aSThomas Huth { 7190fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7191fcf5ef2aSThomas Huth GEN_PRIV; 7192fcf5ef2aSThomas Huth #else 7193fcf5ef2aSThomas Huth TCGv dcrn; 7194fcf5ef2aSThomas Huth 7195fcf5ef2aSThomas Huth CHK_SV; 7196fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7197fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 7198fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7199fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7200fcf5ef2aSThomas Huth } 7201fcf5ef2aSThomas Huth 7202fcf5ef2aSThomas Huth /* mfdcrx */ 7203fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7204fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 7205fcf5ef2aSThomas Huth { 7206fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7207fcf5ef2aSThomas Huth GEN_PRIV; 7208fcf5ef2aSThomas Huth #else 7209fcf5ef2aSThomas Huth CHK_SV; 7210fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7211fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7212fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7213fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7214fcf5ef2aSThomas Huth } 7215fcf5ef2aSThomas Huth 7216fcf5ef2aSThomas Huth /* mtdcrx */ 7217fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7218fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 7219fcf5ef2aSThomas Huth { 7220fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7221fcf5ef2aSThomas Huth GEN_PRIV; 7222fcf5ef2aSThomas Huth #else 7223fcf5ef2aSThomas Huth CHK_SV; 7224fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7225fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7226fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7227fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7228fcf5ef2aSThomas Huth } 7229fcf5ef2aSThomas Huth 7230fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 7231fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 7232fcf5ef2aSThomas Huth { 7233fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7234fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7235fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7236fcf5ef2aSThomas Huth } 7237fcf5ef2aSThomas Huth 7238fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 7239fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 7240fcf5ef2aSThomas Huth { 7241fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7242fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7243fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7244fcf5ef2aSThomas Huth } 7245fcf5ef2aSThomas Huth 7246fcf5ef2aSThomas Huth /* dccci */ 7247fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 7248fcf5ef2aSThomas Huth { 7249fcf5ef2aSThomas Huth CHK_SV; 7250fcf5ef2aSThomas Huth /* interpreted as no-op */ 7251fcf5ef2aSThomas Huth } 7252fcf5ef2aSThomas Huth 7253fcf5ef2aSThomas Huth /* dcread */ 7254fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 7255fcf5ef2aSThomas Huth { 7256fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7257fcf5ef2aSThomas Huth GEN_PRIV; 7258fcf5ef2aSThomas Huth #else 7259fcf5ef2aSThomas Huth TCGv EA, val; 7260fcf5ef2aSThomas Huth 7261fcf5ef2aSThomas Huth CHK_SV; 7262fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 7263fcf5ef2aSThomas Huth EA = tcg_temp_new(); 7264fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 7265fcf5ef2aSThomas Huth val = tcg_temp_new(); 7266fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 7267fcf5ef2aSThomas Huth tcg_temp_free(val); 7268fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 7269fcf5ef2aSThomas Huth tcg_temp_free(EA); 7270fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7271fcf5ef2aSThomas Huth } 7272fcf5ef2aSThomas Huth 7273fcf5ef2aSThomas Huth /* icbt */ 7274fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 7275fcf5ef2aSThomas Huth { 7276efe843d8SDavid Gibson /* 7277efe843d8SDavid Gibson * interpreted as no-op 7278efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7279efe843d8SDavid Gibson * does not generate any exception 7280fcf5ef2aSThomas Huth */ 7281fcf5ef2aSThomas Huth } 7282fcf5ef2aSThomas Huth 7283fcf5ef2aSThomas Huth /* iccci */ 7284fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 7285fcf5ef2aSThomas Huth { 7286fcf5ef2aSThomas Huth CHK_SV; 7287fcf5ef2aSThomas Huth /* interpreted as no-op */ 7288fcf5ef2aSThomas Huth } 7289fcf5ef2aSThomas Huth 7290fcf5ef2aSThomas Huth /* icread */ 7291fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 7292fcf5ef2aSThomas Huth { 7293fcf5ef2aSThomas Huth CHK_SV; 7294fcf5ef2aSThomas Huth /* interpreted as no-op */ 7295fcf5ef2aSThomas Huth } 7296fcf5ef2aSThomas Huth 7297fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 7298fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 7299fcf5ef2aSThomas Huth { 7300fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7301fcf5ef2aSThomas Huth GEN_PRIV; 7302fcf5ef2aSThomas Huth #else 7303fcf5ef2aSThomas Huth CHK_SV; 7304fcf5ef2aSThomas Huth /* Restore CPU state */ 7305fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 7306fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7307fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7308fcf5ef2aSThomas Huth } 7309fcf5ef2aSThomas Huth 7310fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 7311fcf5ef2aSThomas Huth { 7312fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7313fcf5ef2aSThomas Huth GEN_PRIV; 7314fcf5ef2aSThomas Huth #else 7315fcf5ef2aSThomas Huth CHK_SV; 7316fcf5ef2aSThomas Huth /* Restore CPU state */ 7317fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 7318fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7319fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7320fcf5ef2aSThomas Huth } 7321fcf5ef2aSThomas Huth 7322fcf5ef2aSThomas Huth /* BookE specific */ 7323fcf5ef2aSThomas Huth 7324fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7325fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 7326fcf5ef2aSThomas Huth { 7327fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7328fcf5ef2aSThomas Huth GEN_PRIV; 7329fcf5ef2aSThomas Huth #else 7330fcf5ef2aSThomas Huth CHK_SV; 7331fcf5ef2aSThomas Huth /* Restore CPU state */ 7332fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 7333fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7334fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7335fcf5ef2aSThomas Huth } 7336fcf5ef2aSThomas Huth 7337fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7338fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 7339fcf5ef2aSThomas Huth { 7340fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7341fcf5ef2aSThomas Huth GEN_PRIV; 7342fcf5ef2aSThomas Huth #else 7343fcf5ef2aSThomas Huth CHK_SV; 7344fcf5ef2aSThomas Huth /* Restore CPU state */ 7345fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 7346fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7347fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7348fcf5ef2aSThomas Huth } 7349fcf5ef2aSThomas Huth 7350fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7351fcf5ef2aSThomas Huth 7352fcf5ef2aSThomas Huth /* tlbre */ 7353fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7354fcf5ef2aSThomas Huth { 7355fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7356fcf5ef2aSThomas Huth GEN_PRIV; 7357fcf5ef2aSThomas Huth #else 7358fcf5ef2aSThomas Huth CHK_SV; 7359fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7360fcf5ef2aSThomas Huth case 0: 7361fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7362fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7363fcf5ef2aSThomas Huth break; 7364fcf5ef2aSThomas Huth case 1: 7365fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7366fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7367fcf5ef2aSThomas Huth break; 7368fcf5ef2aSThomas Huth default: 7369fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7370fcf5ef2aSThomas Huth break; 7371fcf5ef2aSThomas Huth } 7372fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7373fcf5ef2aSThomas Huth } 7374fcf5ef2aSThomas Huth 7375fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7376fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7377fcf5ef2aSThomas Huth { 7378fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7379fcf5ef2aSThomas Huth GEN_PRIV; 7380fcf5ef2aSThomas Huth #else 7381fcf5ef2aSThomas Huth TCGv t0; 7382fcf5ef2aSThomas Huth 7383fcf5ef2aSThomas Huth CHK_SV; 7384fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7385fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7386fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7387fcf5ef2aSThomas Huth tcg_temp_free(t0); 7388fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7389fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7390fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7391fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7392fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7393fcf5ef2aSThomas Huth gen_set_label(l1); 7394fcf5ef2aSThomas Huth } 7395fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7396fcf5ef2aSThomas Huth } 7397fcf5ef2aSThomas Huth 7398fcf5ef2aSThomas Huth /* tlbwe */ 7399fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7400fcf5ef2aSThomas Huth { 7401fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7402fcf5ef2aSThomas Huth GEN_PRIV; 7403fcf5ef2aSThomas Huth #else 7404fcf5ef2aSThomas Huth CHK_SV; 7405fcf5ef2aSThomas Huth 7406fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7407fcf5ef2aSThomas Huth case 0: 7408fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7409fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7410fcf5ef2aSThomas Huth break; 7411fcf5ef2aSThomas Huth case 1: 7412fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7413fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7414fcf5ef2aSThomas Huth break; 7415fcf5ef2aSThomas Huth default: 7416fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7417fcf5ef2aSThomas Huth break; 7418fcf5ef2aSThomas Huth } 7419fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7420fcf5ef2aSThomas Huth } 7421fcf5ef2aSThomas Huth 7422fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7423fcf5ef2aSThomas Huth 7424fcf5ef2aSThomas Huth /* tlbre */ 7425fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7426fcf5ef2aSThomas Huth { 7427fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7428fcf5ef2aSThomas Huth GEN_PRIV; 7429fcf5ef2aSThomas Huth #else 7430fcf5ef2aSThomas Huth CHK_SV; 7431fcf5ef2aSThomas Huth 7432fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7433fcf5ef2aSThomas Huth case 0: 7434fcf5ef2aSThomas Huth case 1: 7435fcf5ef2aSThomas Huth case 2: 7436fcf5ef2aSThomas Huth { 7437fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7438fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7439fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7440fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7441fcf5ef2aSThomas Huth } 7442fcf5ef2aSThomas Huth break; 7443fcf5ef2aSThomas Huth default: 7444fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7445fcf5ef2aSThomas Huth break; 7446fcf5ef2aSThomas Huth } 7447fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7448fcf5ef2aSThomas Huth } 7449fcf5ef2aSThomas Huth 7450fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7451fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7452fcf5ef2aSThomas Huth { 7453fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7454fcf5ef2aSThomas Huth GEN_PRIV; 7455fcf5ef2aSThomas Huth #else 7456fcf5ef2aSThomas Huth TCGv t0; 7457fcf5ef2aSThomas Huth 7458fcf5ef2aSThomas Huth CHK_SV; 7459fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7460fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7461fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7462fcf5ef2aSThomas Huth tcg_temp_free(t0); 7463fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7464fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7465fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7466fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7467fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7468fcf5ef2aSThomas Huth gen_set_label(l1); 7469fcf5ef2aSThomas Huth } 7470fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7471fcf5ef2aSThomas Huth } 7472fcf5ef2aSThomas Huth 7473fcf5ef2aSThomas Huth /* tlbwe */ 7474fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7475fcf5ef2aSThomas Huth { 7476fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7477fcf5ef2aSThomas Huth GEN_PRIV; 7478fcf5ef2aSThomas Huth #else 7479fcf5ef2aSThomas Huth CHK_SV; 7480fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7481fcf5ef2aSThomas Huth case 0: 7482fcf5ef2aSThomas Huth case 1: 7483fcf5ef2aSThomas Huth case 2: 7484fcf5ef2aSThomas Huth { 7485fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7486fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7487fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7488fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7489fcf5ef2aSThomas Huth } 7490fcf5ef2aSThomas Huth break; 7491fcf5ef2aSThomas Huth default: 7492fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7493fcf5ef2aSThomas Huth break; 7494fcf5ef2aSThomas Huth } 7495fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7496fcf5ef2aSThomas Huth } 7497fcf5ef2aSThomas Huth 7498fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7499fcf5ef2aSThomas Huth 7500fcf5ef2aSThomas Huth /* tlbre */ 7501fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7502fcf5ef2aSThomas Huth { 7503fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7504fcf5ef2aSThomas Huth GEN_PRIV; 7505fcf5ef2aSThomas Huth #else 7506fcf5ef2aSThomas Huth CHK_SV; 7507fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7508fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7509fcf5ef2aSThomas Huth } 7510fcf5ef2aSThomas Huth 7511fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7512fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7513fcf5ef2aSThomas Huth { 7514fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7515fcf5ef2aSThomas Huth GEN_PRIV; 7516fcf5ef2aSThomas Huth #else 7517fcf5ef2aSThomas Huth TCGv t0; 7518fcf5ef2aSThomas Huth 7519fcf5ef2aSThomas Huth CHK_SV; 7520fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7521fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7522fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7523fcf5ef2aSThomas Huth } else { 7524fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7525fcf5ef2aSThomas Huth } 7526fcf5ef2aSThomas Huth 7527fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7528fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7529fcf5ef2aSThomas Huth tcg_temp_free(t0); 7530fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7531fcf5ef2aSThomas Huth } 7532fcf5ef2aSThomas Huth 7533fcf5ef2aSThomas Huth /* tlbwe */ 7534fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7535fcf5ef2aSThomas Huth { 7536fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7537fcf5ef2aSThomas Huth GEN_PRIV; 7538fcf5ef2aSThomas Huth #else 7539fcf5ef2aSThomas Huth CHK_SV; 7540fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7541fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7542fcf5ef2aSThomas Huth } 7543fcf5ef2aSThomas Huth 7544fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7545fcf5ef2aSThomas Huth { 7546fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7547fcf5ef2aSThomas Huth GEN_PRIV; 7548fcf5ef2aSThomas Huth #else 7549fcf5ef2aSThomas Huth TCGv t0; 7550fcf5ef2aSThomas Huth 7551fcf5ef2aSThomas Huth CHK_SV; 7552fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7553fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7554fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7555fcf5ef2aSThomas Huth tcg_temp_free(t0); 7556fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7557fcf5ef2aSThomas Huth } 7558fcf5ef2aSThomas Huth 7559fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7560fcf5ef2aSThomas Huth { 7561fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7562fcf5ef2aSThomas Huth GEN_PRIV; 7563fcf5ef2aSThomas Huth #else 7564fcf5ef2aSThomas Huth TCGv t0; 7565fcf5ef2aSThomas Huth 7566fcf5ef2aSThomas Huth CHK_SV; 7567fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7568fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7569fcf5ef2aSThomas Huth 7570fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7571fcf5ef2aSThomas Huth case 0: 7572fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7573fcf5ef2aSThomas Huth break; 7574fcf5ef2aSThomas Huth case 1: 7575fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7576fcf5ef2aSThomas Huth break; 7577fcf5ef2aSThomas Huth case 3: 7578fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7579fcf5ef2aSThomas Huth break; 7580fcf5ef2aSThomas Huth default: 7581fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7582fcf5ef2aSThomas Huth break; 7583fcf5ef2aSThomas Huth } 7584fcf5ef2aSThomas Huth 7585fcf5ef2aSThomas Huth tcg_temp_free(t0); 7586fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7587fcf5ef2aSThomas Huth } 7588fcf5ef2aSThomas Huth 7589fcf5ef2aSThomas Huth 7590fcf5ef2aSThomas Huth /* wrtee */ 7591fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7592fcf5ef2aSThomas Huth { 7593fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7594fcf5ef2aSThomas Huth GEN_PRIV; 7595fcf5ef2aSThomas Huth #else 7596fcf5ef2aSThomas Huth TCGv t0; 7597fcf5ef2aSThomas Huth 7598fcf5ef2aSThomas Huth CHK_SV; 7599fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7600fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7601fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7602fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7603fcf5ef2aSThomas Huth tcg_temp_free(t0); 7604efe843d8SDavid Gibson /* 7605efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7606efe843d8SDavid Gibson * just set msr_ee to 1 7607fcf5ef2aSThomas Huth */ 7608fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7609fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7610fcf5ef2aSThomas Huth } 7611fcf5ef2aSThomas Huth 7612fcf5ef2aSThomas Huth /* wrteei */ 7613fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7614fcf5ef2aSThomas Huth { 7615fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7616fcf5ef2aSThomas Huth GEN_PRIV; 7617fcf5ef2aSThomas Huth #else 7618fcf5ef2aSThomas Huth CHK_SV; 7619fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7620fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7621fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7622fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7623fcf5ef2aSThomas Huth } else { 7624fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7625fcf5ef2aSThomas Huth } 7626fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7627fcf5ef2aSThomas Huth } 7628fcf5ef2aSThomas Huth 7629fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7630fcf5ef2aSThomas Huth 7631fcf5ef2aSThomas Huth /* dlmzb */ 7632fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7633fcf5ef2aSThomas Huth { 7634fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7635fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7636fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7637fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7638fcf5ef2aSThomas Huth } 7639fcf5ef2aSThomas Huth 7640fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7641fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7642fcf5ef2aSThomas Huth { 7643fcf5ef2aSThomas Huth /* interpreted as no-op */ 7644fcf5ef2aSThomas Huth } 7645fcf5ef2aSThomas Huth 7646fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7647fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7648fcf5ef2aSThomas Huth { 764927a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 765027a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 765127a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 765227a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 765327a3ea7eSBALATON Zoltan } 765427a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7655fcf5ef2aSThomas Huth } 7656fcf5ef2aSThomas Huth 7657fcf5ef2aSThomas Huth /* icbt */ 7658fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7659fcf5ef2aSThomas Huth { 7660efe843d8SDavid Gibson /* 7661efe843d8SDavid Gibson * interpreted as no-op 7662efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7663efe843d8SDavid Gibson * does not generate any exception 7664fcf5ef2aSThomas Huth */ 7665fcf5ef2aSThomas Huth } 7666fcf5ef2aSThomas Huth 7667fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7668fcf5ef2aSThomas Huth 7669fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7670fcf5ef2aSThomas Huth { 7671fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7672fcf5ef2aSThomas Huth GEN_PRIV; 7673fcf5ef2aSThomas Huth #else 7674ebca5e6dSCédric Le Goater CHK_HV; 7675d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76767af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76777af1e7b0SCédric Le Goater } else { 7678fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76797af1e7b0SCédric Le Goater } 7680fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7681fcf5ef2aSThomas Huth } 7682fcf5ef2aSThomas Huth 7683fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7684fcf5ef2aSThomas Huth { 7685fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7686fcf5ef2aSThomas Huth GEN_PRIV; 7687fcf5ef2aSThomas Huth #else 7688ebca5e6dSCédric Le Goater CHK_HV; 7689d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76907af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76917af1e7b0SCédric Le Goater } else { 7692fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76937af1e7b0SCédric Le Goater } 7694fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7695fcf5ef2aSThomas Huth } 7696fcf5ef2aSThomas Huth 76975ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 76985ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 76995ba7ba1dSCédric Le Goater { 77005ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 77015ba7ba1dSCédric Le Goater GEN_PRIV; 77025ba7ba1dSCédric Le Goater #else 77035ba7ba1dSCédric Le Goater CHK_SV; 77045ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77055ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77065ba7ba1dSCédric Le Goater } 77075ba7ba1dSCédric Le Goater 77085ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 77095ba7ba1dSCédric Le Goater { 77105ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 77115ba7ba1dSCédric Le Goater GEN_PRIV; 77125ba7ba1dSCédric Le Goater #else 77135ba7ba1dSCédric Le Goater CHK_SV; 77145ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77155ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77165ba7ba1dSCédric Le Goater } 77175ba7ba1dSCédric Le Goater #endif 77185ba7ba1dSCédric Le Goater 77197af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 77207af1e7b0SCédric Le Goater { 77217af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 77227af1e7b0SCédric Le Goater GEN_PRIV; 77237af1e7b0SCédric Le Goater #else 77247af1e7b0SCédric Le Goater CHK_HV; 77257af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77267af1e7b0SCédric Le Goater /* interpreted as no-op */ 77277af1e7b0SCédric Le Goater } 7728fcf5ef2aSThomas Huth 7729fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7730fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7731fcf5ef2aSThomas Huth { 7732fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7733fcf5ef2aSThomas Huth 7734fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7735fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7736fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7737fcf5ef2aSThomas Huth } 7738fcf5ef2aSThomas Huth 7739fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7740fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7741fcf5ef2aSThomas Huth { 7742fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7743fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7744fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7745fcf5ef2aSThomas Huth 7746fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7747fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7748fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7749fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7750fcf5ef2aSThomas Huth } else { 7751fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7752fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7753fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7754fcf5ef2aSThomas Huth } 7755fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7756fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7757fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7758fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7759fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7760fcf5ef2aSThomas Huth } 7761fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7762fcf5ef2aSThomas Huth 7763fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7764fcf5ef2aSThomas Huth { 7765fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7766fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7767fcf5ef2aSThomas Huth return; 7768fcf5ef2aSThomas Huth } 7769fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7770fcf5ef2aSThomas Huth } 7771fcf5ef2aSThomas Huth 7772fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7773fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7774fcf5ef2aSThomas Huth { \ 7775fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7776fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7777fcf5ef2aSThomas Huth return; \ 7778fcf5ef2aSThomas Huth } \ 7779efe843d8SDavid Gibson /* \ 7780efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7781fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7782fcf5ef2aSThomas Huth * \ 7783fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7784fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7785fcf5ef2aSThomas Huth */ \ 7786fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7787fcf5ef2aSThomas Huth } 7788fcf5ef2aSThomas Huth 7789fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7790fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7791fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7792fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7793fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7794fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7795fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7796efe843d8SDavid Gibson 7797b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7798b8b4576eSSuraj Jitindar Singh { 7799efe843d8SDavid Gibson /* Do Nothing */ 7800b8b4576eSSuraj Jitindar Singh } 7801fcf5ef2aSThomas Huth 780280b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 780380b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 780480b8c1eeSNikunj A Dadhania { \ 7805efe843d8SDavid Gibson /* \ 7806efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7807efe843d8SDavid Gibson * implementation of the copy paste facility \ 780880b8c1eeSNikunj A Dadhania */ \ 780980b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 781080b8c1eeSNikunj A Dadhania } 781180b8c1eeSNikunj A Dadhania 781280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 781380b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 781480b8c1eeSNikunj A Dadhania 7815fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7816fcf5ef2aSThomas Huth { 7817fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7818fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7819fcf5ef2aSThomas Huth return; 7820fcf5ef2aSThomas Huth } 7821efe843d8SDavid Gibson /* 7822efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7823efe843d8SDavid Gibson * simple: 7824fcf5ef2aSThomas Huth * 7825fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7826fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7827fcf5ef2aSThomas Huth */ 7828fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7829fcf5ef2aSThomas Huth } 7830fcf5ef2aSThomas Huth 7831fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7832fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7833fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7834fcf5ef2aSThomas Huth { \ 7835fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7836fcf5ef2aSThomas Huth } 7837fcf5ef2aSThomas Huth 7838fcf5ef2aSThomas Huth #else 7839fcf5ef2aSThomas Huth 7840fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7841fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7842fcf5ef2aSThomas Huth { \ 7843fcf5ef2aSThomas Huth CHK_SV; \ 7844fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7845fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7846fcf5ef2aSThomas Huth return; \ 7847fcf5ef2aSThomas Huth } \ 7848efe843d8SDavid Gibson /* \ 7849efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7850fcf5ef2aSThomas Huth * simple: \ 7851fcf5ef2aSThomas Huth * \ 7852fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7853fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7854fcf5ef2aSThomas Huth */ \ 7855fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7856fcf5ef2aSThomas Huth } 7857fcf5ef2aSThomas Huth 7858fcf5ef2aSThomas Huth #endif 7859fcf5ef2aSThomas Huth 7860fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7861fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7862fcf5ef2aSThomas Huth 78631a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 78641a404c91SMark Cave-Ayland { 7865e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 78661a404c91SMark Cave-Ayland } 78671a404c91SMark Cave-Ayland 78681a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 78691a404c91SMark Cave-Ayland { 7870e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 78711a404c91SMark Cave-Ayland } 78721a404c91SMark Cave-Ayland 7873c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7874c4a18dbfSMark Cave-Ayland { 787537da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7876c4a18dbfSMark Cave-Ayland } 7877c4a18dbfSMark Cave-Ayland 7878c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7879c4a18dbfSMark Cave-Ayland { 788037da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7881c4a18dbfSMark Cave-Ayland } 7882c4a18dbfSMark Cave-Ayland 7883139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7884fcf5ef2aSThomas Huth 7885139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7886fcf5ef2aSThomas Huth 7887139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7888fcf5ef2aSThomas Huth 7889139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7890fcf5ef2aSThomas Huth 7891139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7892fcf5ef2aSThomas Huth 78935cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 78945cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 78955cb091a4SNikunj A Dadhania { 78965cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 78975cb091a4SNikunj A Dadhania case 0: /* lfdp */ 78985cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 78995cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 79005cb091a4SNikunj A Dadhania } 79015cb091a4SNikunj A Dadhania break; 79025cb091a4SNikunj A Dadhania case 2: /* lxsd */ 79035cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79045cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 79055cb091a4SNikunj A Dadhania } 79065cb091a4SNikunj A Dadhania break; 79075cb091a4SNikunj A Dadhania case 3: /* lxssp */ 79085cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79095cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 79105cb091a4SNikunj A Dadhania } 79115cb091a4SNikunj A Dadhania break; 79125cb091a4SNikunj A Dadhania } 79135cb091a4SNikunj A Dadhania return gen_invalid(ctx); 79145cb091a4SNikunj A Dadhania } 79155cb091a4SNikunj A Dadhania 7916d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7917e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7918e3001664SNikunj A Dadhania { 7919e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7920e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7921e3001664SNikunj A Dadhania case 1: /* lxv */ 7922d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7923d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7924d59ba583SNikunj A Dadhania } 7925e3001664SNikunj A Dadhania break; 7926e3001664SNikunj A Dadhania case 5: /* stxv */ 7927d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7928d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7929d59ba583SNikunj A Dadhania } 7930e3001664SNikunj A Dadhania break; 7931e3001664SNikunj A Dadhania } 7932e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7933e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7934e3001664SNikunj A Dadhania case 0: /* stfdp */ 7935e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7936e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7937e3001664SNikunj A Dadhania } 7938e3001664SNikunj A Dadhania break; 7939e3001664SNikunj A Dadhania case 2: /* stxsd */ 7940e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7941e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7942e3001664SNikunj A Dadhania } 7943e3001664SNikunj A Dadhania break; 7944e3001664SNikunj A Dadhania case 3: /* stxssp */ 7945e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7946e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7947e3001664SNikunj A Dadhania } 7948e3001664SNikunj A Dadhania break; 7949e3001664SNikunj A Dadhania } 7950e3001664SNikunj A Dadhania } 7951e3001664SNikunj A Dadhania return gen_invalid(ctx); 7952e3001664SNikunj A Dadhania } 7953e3001664SNikunj A Dadhania 79549d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79559d69cfa2SLijun Pan /* brd */ 79569d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 79579d69cfa2SLijun Pan { 79589d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79599d69cfa2SLijun Pan } 79609d69cfa2SLijun Pan 79619d69cfa2SLijun Pan /* brw */ 79629d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 79639d69cfa2SLijun Pan { 79649d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79659d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 79669d69cfa2SLijun Pan 79679d69cfa2SLijun Pan } 79689d69cfa2SLijun Pan 79699d69cfa2SLijun Pan /* brh */ 79709d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 79719d69cfa2SLijun Pan { 79729d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 79739d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 79749d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 79759d69cfa2SLijun Pan 79769d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 79779d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 79789d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 79799d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 79809d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 79819d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 79829d69cfa2SLijun Pan 79839d69cfa2SLijun Pan tcg_temp_free_i64(t0); 79849d69cfa2SLijun Pan tcg_temp_free_i64(t1); 79859d69cfa2SLijun Pan tcg_temp_free_i64(t2); 79869d69cfa2SLijun Pan } 79879d69cfa2SLijun Pan #endif 79889d69cfa2SLijun Pan 7989fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 79909d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79919d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 79929d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 79939d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 79949d69cfa2SLijun Pan #endif 7995fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7996fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7997fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7998fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7999fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 8000fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8001fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 8002fcf5ef2aSThomas Huth #endif 8003fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 8004fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 8005fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 8006fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8007fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8008fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8009fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8010fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 8011fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 8012fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 8013fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 8014fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 8015fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8016fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8017fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 8018fcf5ef2aSThomas Huth #endif 8019fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 8020fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 8021fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8022fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8023fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8024fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 8025fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 802680b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 8027b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 802880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 8029fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 8030fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 8031fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8032fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8033fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8034fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8035fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 8036fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 8037fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 8038fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8039fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 8040fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 8041fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 8042fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 8043fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 8044fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 8045fcf5ef2aSThomas Huth #endif 8046fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8047fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8048fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8049fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 8050fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 8051fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 8052fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 8053fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8054fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 8055fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 8056fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 8057fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 8058fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 8059fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 8060fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8061fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 8062fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8063fcf5ef2aSThomas Huth #endif 8064fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8065fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 8066fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 8067fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 8068fcf5ef2aSThomas Huth #endif 80695cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 80705cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8071d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 8072e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8073fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8074fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8075fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 8076fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 8077fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 8078fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 8079c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 8080fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 8081fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8082fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8083fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 8084a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 8085a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 8086fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8087fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8088fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 8089fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8090a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 8091a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 8092fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 8093fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 8094fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 8095fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 8096fcf5ef2aSThomas Huth #endif 8097fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 8098fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 8099c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 8100fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8101fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8102fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 8103fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 8104fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 8105fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 8106fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 8107fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8108fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 81093c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 81103c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81113c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81123c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81133c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 81143c89b8d6SNicholas Piggin #endif 8115cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8116fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8117fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8118fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8119fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8120fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 8121fcf5ef2aSThomas Huth #endif 81223c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81233c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 81243c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 8125fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 8126fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8127fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8128fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 8129fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 8130fcf5ef2aSThomas Huth #endif 8131fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 8132fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 8133fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 8134fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 8135fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 8136fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 8137fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8138fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 8139fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 8140b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 8141fcf5ef2aSThomas Huth #endif 8142fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 8143fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 8144fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 814550728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8146fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 8147fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 814850728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8149fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 815050728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8151fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 815250728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8153fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 8154fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 815550728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8156fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 815799d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 8158fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 8159fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 816050728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8161fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 8162fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 8163fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 8164fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 8165fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 8166fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8167fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 8168fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 8169fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8170fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 8171fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 8172fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8173fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 8174fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 8175fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 8176fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 8177fcf5ef2aSThomas Huth #endif 8178fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 8179efe843d8SDavid Gibson /* 8180efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 8181efe843d8SDavid Gibson * different ISA versions 8182efe843d8SDavid Gibson */ 8183fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 8184fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 8185c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 8186c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 8187fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 8188fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8189fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 8190fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 8191a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 819262d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8193fcf5ef2aSThomas Huth #endif 8194fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 8195fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 8196fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 8197fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 8198fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 8199fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 8200fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 8201fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 8202fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 8203fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 8204fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 8205fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8206fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 8207fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 8208fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 8209fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 8210fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 8211fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 8212fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 8213fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8214fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 8215fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 8216fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 8217fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 8218fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 8219fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 8220fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 8221fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 8222fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 8223fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 8224fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 8225fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 8226fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 8227fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 8228fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 8229fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 8230fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 8231fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 8232fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 8233fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 8234fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 8235fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 8236fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 8237fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 8238fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 8239fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 8240fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 8241fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 8242fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 8243fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8244fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8245fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 8246fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 8247fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8248fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8249fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 8250fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 8251fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 8252fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 8253fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 8254fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 8255fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 8256fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 8257fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 8258fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 8259fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 8260fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 8261fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 8262fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 8263fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 8264fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 8265fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 8266fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 8267fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 8268fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 8269fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 8270fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 8271fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 8272fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 8273fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 8274fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 8275fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8276fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 8277fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8278fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 8279fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8280fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 8281fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8282fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 8283fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8284fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 8285fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 8286fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 8287fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 82887af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 82897af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 8290fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8291fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8292fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8293fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8294fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 829527a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8296fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8297fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 82980c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 82990c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8300fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8301fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8302fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8303fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8304fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8305fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8306fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8307fcf5ef2aSThomas Huth PPC2_ISA300), 8308fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 83095ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 83105ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 83115ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 83125ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8313fcf5ef2aSThomas Huth #endif 8314fcf5ef2aSThomas Huth 8315fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8316fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8317fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8318fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8319fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8320fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8321fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8322fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8323fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8324fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8325fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8326fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8327fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8328fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8329fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 83304c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8331fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8332fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8333fcf5ef2aSThomas Huth 8334fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8335fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8336fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8337fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8338fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8339fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8340fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8341fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8342fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8343fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8344fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8345fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8346fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8347fcf5ef2aSThomas Huth 8348fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8349fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8350fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8351fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8352fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8353fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8354fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8355fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8356fcf5ef2aSThomas Huth 8357fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8358fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8359fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8360fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8361fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8362fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8363fcf5ef2aSThomas Huth 8364fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8365fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8366fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8367fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8368fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8369fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8370fcf5ef2aSThomas Huth #endif 8371fcf5ef2aSThomas Huth 8372fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8373fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8374fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8375fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8376fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8377fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8378fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8379fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8380fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8381fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8382fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8383fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8384fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8385fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8386fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8387fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8388fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8389fcf5ef2aSThomas Huth 8390fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8391fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8392fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8393fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8394fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8395fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8396fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8397fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8398fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8399fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8400fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8401fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8402fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8403fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8404fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8405fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8406fcf5ef2aSThomas Huth #endif 8407fcf5ef2aSThomas Huth 8408fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8409fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8410fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8411fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8412fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8413fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8414fcf5ef2aSThomas Huth PPC_64B) 8415fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8416fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8417fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8418fcf5ef2aSThomas Huth PPC_64B), \ 8419fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8420fcf5ef2aSThomas Huth PPC_64B), \ 8421fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8422fcf5ef2aSThomas Huth PPC_64B) 8423fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8424fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8425fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8426fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8427fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8428fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8429fcf5ef2aSThomas Huth #endif 8430fcf5ef2aSThomas Huth 8431fcf5ef2aSThomas Huth #undef GEN_LD 8432fcf5ef2aSThomas Huth #undef GEN_LDU 8433fcf5ef2aSThomas Huth #undef GEN_LDUX 8434fcf5ef2aSThomas Huth #undef GEN_LDX_E 8435fcf5ef2aSThomas Huth #undef GEN_LDS 8436fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 8437fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8438fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 8439fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 8440fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 8441fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8442fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8443fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8444fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 8445fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 8446fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 8447fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 8448fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 8449fcf5ef2aSThomas Huth 8450fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 8451fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 8452fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 8453fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 8454fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8455fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 8456fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 8457fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 8458fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 8459fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8460fcf5ef2aSThomas Huth 8461fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8462fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8463fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8464fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8465fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8466fcf5ef2aSThomas Huth #endif 8467fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8468fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8469fcf5ef2aSThomas Huth 847050728199SRoman Kapl /* External PID based load */ 847150728199SRoman Kapl #undef GEN_LDEPX 847250728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 847350728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 847450728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 847550728199SRoman Kapl 847650728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 847750728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 847850728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 847950728199SRoman Kapl #if defined(TARGET_PPC64) 848050728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 848150728199SRoman Kapl #endif 848250728199SRoman Kapl 8483fcf5ef2aSThomas Huth #undef GEN_ST 8484fcf5ef2aSThomas Huth #undef GEN_STU 8485fcf5ef2aSThomas Huth #undef GEN_STUX 8486fcf5ef2aSThomas Huth #undef GEN_STX_E 8487fcf5ef2aSThomas Huth #undef GEN_STS 8488fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8489fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8490fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8491fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8492fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8493fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8494fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 84950123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8496fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8497fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8498fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8499fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8500fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8501fcf5ef2aSThomas Huth 8502fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8503fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8504fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8505fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8506fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8507fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8508fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8509fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8510fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8511fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8512fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8513fcf5ef2aSThomas Huth #endif 8514fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8515fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8516fcf5ef2aSThomas Huth 851750728199SRoman Kapl #undef GEN_STEPX 851850728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 851950728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 852050728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 852150728199SRoman Kapl 852250728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 852350728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 852450728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 852550728199SRoman Kapl #if defined(TARGET_PPC64) 852650728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 852750728199SRoman Kapl #endif 852850728199SRoman Kapl 8529fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8530fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8531fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8532fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8533fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8534fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8535fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8536fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8537fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8538fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8539fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8540fcf5ef2aSThomas Huth 8541fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8542fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8543fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8544fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8545fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8546fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8547fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8579fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8581fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8583fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8584fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8585fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8586fcf5ef2aSThomas Huth 8587fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8588fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8589fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8590fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8591fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8592fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8593fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8594fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8595fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8596fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8597fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8598fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8599fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8600fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8601fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8602fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8603fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8604fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8605fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8606fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8607fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8608fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8609fcf5ef2aSThomas Huth 8610139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8611fcf5ef2aSThomas Huth 8612139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8613fcf5ef2aSThomas Huth 8614139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8615fcf5ef2aSThomas Huth 8616139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8617fcf5ef2aSThomas Huth 8618139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8619fcf5ef2aSThomas Huth }; 8620fcf5ef2aSThomas Huth 86217468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 86227468e2c8SBruno Larsen (billionai) /* Opcode types */ 86237468e2c8SBruno Larsen (billionai) enum { 86247468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 86257468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 86267468e2c8SBruno Larsen (billionai) }; 86277468e2c8SBruno Larsen (billionai) 86287468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 86297468e2c8SBruno Larsen (billionai) 86307468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 86317468e2c8SBruno Larsen (billionai) { 86327468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 86337468e2c8SBruno Larsen (billionai) } 86347468e2c8SBruno Larsen (billionai) 86357468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 86367468e2c8SBruno Larsen (billionai) { 86377468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 86387468e2c8SBruno Larsen (billionai) } 86397468e2c8SBruno Larsen (billionai) 86407468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 86417468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 86427468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 86437468e2c8SBruno Larsen (billionai) { 86447468e2c8SBruno Larsen (billionai) int i; 86457468e2c8SBruno Larsen (billionai) 86467468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 86477468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86487468e2c8SBruno Larsen (billionai) } 86497468e2c8SBruno Larsen (billionai) } 86507468e2c8SBruno Larsen (billionai) 86517468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 86527468e2c8SBruno Larsen (billionai) { 86537468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 86547468e2c8SBruno Larsen (billionai) 86557468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 86567468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 86577468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 86587468e2c8SBruno Larsen (billionai) 86597468e2c8SBruno Larsen (billionai) return 0; 86607468e2c8SBruno Larsen (billionai) } 86617468e2c8SBruno Larsen (billionai) 86627468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 86637468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86647468e2c8SBruno Larsen (billionai) { 86657468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 86667468e2c8SBruno Larsen (billionai) return -1; 86677468e2c8SBruno Larsen (billionai) } 86687468e2c8SBruno Larsen (billionai) table[idx] = handler; 86697468e2c8SBruno Larsen (billionai) 86707468e2c8SBruno Larsen (billionai) return 0; 86717468e2c8SBruno Larsen (billionai) } 86727468e2c8SBruno Larsen (billionai) 86737468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 86747468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 86757468e2c8SBruno Larsen (billionai) { 86767468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 86777468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 86787468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 86797468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 86807468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 86817468e2c8SBruno Larsen (billionai) ppc_opcodes[idx]->oname, handler->oname); 86827468e2c8SBruno Larsen (billionai) #endif 86837468e2c8SBruno Larsen (billionai) return -1; 86847468e2c8SBruno Larsen (billionai) } 86857468e2c8SBruno Larsen (billionai) 86867468e2c8SBruno Larsen (billionai) return 0; 86877468e2c8SBruno Larsen (billionai) } 86887468e2c8SBruno Larsen (billionai) 86897468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 86907468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86917468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86927468e2c8SBruno Larsen (billionai) { 86937468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 86947468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 86957468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 86967468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 86977468e2c8SBruno Larsen (billionai) return -1; 86987468e2c8SBruno Larsen (billionai) } 86997468e2c8SBruno Larsen (billionai) } else { 87007468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 87017468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 87027468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 87037468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 87047468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 87057468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 87067468e2c8SBruno Larsen (billionai) #endif 87077468e2c8SBruno Larsen (billionai) return -1; 87087468e2c8SBruno Larsen (billionai) } 87097468e2c8SBruno Larsen (billionai) } 87107468e2c8SBruno Larsen (billionai) if (handler != NULL && 87117468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 87127468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 87137468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 87147468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 87157468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 87167468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 87177468e2c8SBruno Larsen (billionai) #endif 87187468e2c8SBruno Larsen (billionai) return -1; 87197468e2c8SBruno Larsen (billionai) } 87207468e2c8SBruno Larsen (billionai) 87217468e2c8SBruno Larsen (billionai) return 0; 87227468e2c8SBruno Larsen (billionai) } 87237468e2c8SBruno Larsen (billionai) 87247468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 87257468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87267468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 87277468e2c8SBruno Larsen (billionai) { 87287468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 87297468e2c8SBruno Larsen (billionai) } 87307468e2c8SBruno Larsen (billionai) 87317468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 87327468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87337468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 87347468e2c8SBruno Larsen (billionai) { 87357468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 87367468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 87377468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 87387468e2c8SBruno Larsen (billionai) return -1; 87397468e2c8SBruno Larsen (billionai) } 87407468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 87417468e2c8SBruno Larsen (billionai) handler) < 0) { 87427468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 87437468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 87447468e2c8SBruno Larsen (billionai) return -1; 87457468e2c8SBruno Larsen (billionai) } 87467468e2c8SBruno Larsen (billionai) 87477468e2c8SBruno Larsen (billionai) return 0; 87487468e2c8SBruno Larsen (billionai) } 87497468e2c8SBruno Larsen (billionai) 87507468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 87517468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87527468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 87537468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 87547468e2c8SBruno Larsen (billionai) { 87557468e2c8SBruno Larsen (billionai) opc_handler_t **table; 87567468e2c8SBruno Larsen (billionai) 87577468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 87587468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 87597468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 87607468e2c8SBruno Larsen (billionai) return -1; 87617468e2c8SBruno Larsen (billionai) } 87627468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 87637468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 87647468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 87657468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 87667468e2c8SBruno Larsen (billionai) return -1; 87677468e2c8SBruno Larsen (billionai) } 87687468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 87697468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 87707468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 87717468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 87727468e2c8SBruno Larsen (billionai) return -1; 87737468e2c8SBruno Larsen (billionai) } 87747468e2c8SBruno Larsen (billionai) return 0; 87757468e2c8SBruno Larsen (billionai) } 87767468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 87777468e2c8SBruno Larsen (billionai) { 87787468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 87797468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 87807468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 87817468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 87827468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 87837468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 87847468e2c8SBruno Larsen (billionai) return -1; 87857468e2c8SBruno Larsen (billionai) } 87867468e2c8SBruno Larsen (billionai) } else { 87877468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 87887468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 87897468e2c8SBruno Larsen (billionai) return -1; 87907468e2c8SBruno Larsen (billionai) } 87917468e2c8SBruno Larsen (billionai) } 87927468e2c8SBruno Larsen (billionai) } else { 87937468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 87947468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 87957468e2c8SBruno Larsen (billionai) return -1; 87967468e2c8SBruno Larsen (billionai) } 87977468e2c8SBruno Larsen (billionai) } 87987468e2c8SBruno Larsen (billionai) } else { 87997468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 88007468e2c8SBruno Larsen (billionai) return -1; 88017468e2c8SBruno Larsen (billionai) } 88027468e2c8SBruno Larsen (billionai) } 88037468e2c8SBruno Larsen (billionai) 88047468e2c8SBruno Larsen (billionai) return 0; 88057468e2c8SBruno Larsen (billionai) } 88067468e2c8SBruno Larsen (billionai) 88077468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 88087468e2c8SBruno Larsen (billionai) { 88097468e2c8SBruno Larsen (billionai) int i, count, tmp; 88107468e2c8SBruno Larsen (billionai) 88117468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 88127468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 88137468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 88147468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88157468e2c8SBruno Larsen (billionai) } 88167468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 88177468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 88187468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 88197468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 88207468e2c8SBruno Larsen (billionai) if (tmp == 0) { 88217468e2c8SBruno Larsen (billionai) free(table[i]); 88227468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88237468e2c8SBruno Larsen (billionai) } else { 88247468e2c8SBruno Larsen (billionai) count++; 88257468e2c8SBruno Larsen (billionai) } 88267468e2c8SBruno Larsen (billionai) } else { 88277468e2c8SBruno Larsen (billionai) count++; 88287468e2c8SBruno Larsen (billionai) } 88297468e2c8SBruno Larsen (billionai) } 88307468e2c8SBruno Larsen (billionai) } 88317468e2c8SBruno Larsen (billionai) 88327468e2c8SBruno Larsen (billionai) return count; 88337468e2c8SBruno Larsen (billionai) } 88347468e2c8SBruno Larsen (billionai) 88357468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 88367468e2c8SBruno Larsen (billionai) { 88377468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 88387468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 88397468e2c8SBruno Larsen (billionai) } 88407468e2c8SBruno Larsen (billionai) } 88417468e2c8SBruno Larsen (billionai) 88427468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 88437468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 88447468e2c8SBruno Larsen (billionai) { 88457468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 88467468e2c8SBruno Larsen (billionai) opcode_t *opc; 88477468e2c8SBruno Larsen (billionai) 88487468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 88497468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 88507468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 88517468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 88527468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 88537468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 88547468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 88557468e2c8SBruno Larsen (billionai) opc->opc3); 88567468e2c8SBruno Larsen (billionai) return; 88577468e2c8SBruno Larsen (billionai) } 88587468e2c8SBruno Larsen (billionai) } 88597468e2c8SBruno Larsen (billionai) } 88607468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 88617468e2c8SBruno Larsen (billionai) fflush(stdout); 88627468e2c8SBruno Larsen (billionai) fflush(stderr); 88637468e2c8SBruno Larsen (billionai) } 88647468e2c8SBruno Larsen (billionai) 88657468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 88667468e2c8SBruno Larsen (billionai) { 88677468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 88687468e2c8SBruno Larsen (billionai) int i, j, k; 88697468e2c8SBruno Larsen (billionai) 88707468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 88717468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 88727468e2c8SBruno Larsen (billionai) continue; 88737468e2c8SBruno Larsen (billionai) } 88747468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 88757468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 88767468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 88777468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 88787468e2c8SBruno Larsen (billionai) continue; 88797468e2c8SBruno Larsen (billionai) } 88807468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 88817468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 88827468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 88837468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 88847468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 88857468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 88867468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88877468e2c8SBruno Larsen (billionai) } 88887468e2c8SBruno Larsen (billionai) } 88897468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 88907468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88917468e2c8SBruno Larsen (billionai) } 88927468e2c8SBruno Larsen (billionai) } 88937468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 88947468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88957468e2c8SBruno Larsen (billionai) } 88967468e2c8SBruno Larsen (billionai) } 88977468e2c8SBruno Larsen (billionai) } 88987468e2c8SBruno Larsen (billionai) 88997468e2c8SBruno Larsen (billionai) #if defined(PPC_DUMP_CPU) 89007468e2c8SBruno Larsen (billionai) static void dump_ppc_insns(CPUPPCState *env) 89017468e2c8SBruno Larsen (billionai) { 89027468e2c8SBruno Larsen (billionai) opc_handler_t **table, *handler; 89037468e2c8SBruno Larsen (billionai) const char *p, *q; 89047468e2c8SBruno Larsen (billionai) uint8_t opc1, opc2, opc3, opc4; 89057468e2c8SBruno Larsen (billionai) 89067468e2c8SBruno Larsen (billionai) printf("Instructions set:\n"); 89077468e2c8SBruno Larsen (billionai) /* opc1 is 6 bits long */ 89087468e2c8SBruno Larsen (billionai) for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 89097468e2c8SBruno Larsen (billionai) table = env->opcodes; 89107468e2c8SBruno Larsen (billionai) handler = table[opc1]; 89117468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89127468e2c8SBruno Larsen (billionai) /* opc2 is 5 bits long */ 89137468e2c8SBruno Larsen (billionai) for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 89147468e2c8SBruno Larsen (billionai) table = env->opcodes; 89157468e2c8SBruno Larsen (billionai) handler = env->opcodes[opc1]; 89167468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89177468e2c8SBruno Larsen (billionai) handler = table[opc2]; 89187468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89197468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89207468e2c8SBruno Larsen (billionai) /* opc3 is 5 bits long */ 89217468e2c8SBruno Larsen (billionai) for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 89227468e2c8SBruno Larsen (billionai) opc3++) { 89237468e2c8SBruno Larsen (billionai) handler = table[opc3]; 89247468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89257468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89267468e2c8SBruno Larsen (billionai) /* opc4 is 5 bits long */ 89277468e2c8SBruno Larsen (billionai) for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 89287468e2c8SBruno Larsen (billionai) opc4++) { 89297468e2c8SBruno Larsen (billionai) handler = table[opc4]; 89307468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89317468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x %02x -- " 89327468e2c8SBruno Larsen (billionai) "(%02d %04d %02d) : %s\n", 89337468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc4, 89347468e2c8SBruno Larsen (billionai) opc1, (opc3 << 5) | opc2, opc4, 89357468e2c8SBruno Larsen (billionai) handler->oname); 89367468e2c8SBruno Larsen (billionai) } 89377468e2c8SBruno Larsen (billionai) } 89387468e2c8SBruno Larsen (billionai) } else { 89397468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89407468e2c8SBruno Larsen (billionai) /* Special hack to properly dump SPE insns */ 89417468e2c8SBruno Larsen (billionai) p = strchr(handler->oname, '_'); 89427468e2c8SBruno Larsen (billionai) if (p == NULL) { 89437468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x (%02d %04d) : " 89447468e2c8SBruno Larsen (billionai) "%s\n", 89457468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc1, 89467468e2c8SBruno Larsen (billionai) (opc3 << 5) | opc2, 89477468e2c8SBruno Larsen (billionai) handler->oname); 89487468e2c8SBruno Larsen (billionai) } else { 89497468e2c8SBruno Larsen (billionai) q = "speundef"; 89507468e2c8SBruno Larsen (billionai) if ((p - handler->oname) != strlen(q) 89517468e2c8SBruno Larsen (billionai) || (memcmp(handler->oname, q, strlen(q)) 89527468e2c8SBruno Larsen (billionai) != 0)) { 89537468e2c8SBruno Larsen (billionai) /* First instruction */ 89547468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x" 89557468e2c8SBruno Larsen (billionai) "(%02d %04d) : %.*s\n", 89567468e2c8SBruno Larsen (billionai) opc1, opc2 << 1, opc3, opc1, 89577468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1), 89587468e2c8SBruno Larsen (billionai) (int)(p - handler->oname), 89597468e2c8SBruno Larsen (billionai) handler->oname); 89607468e2c8SBruno Larsen (billionai) } 89617468e2c8SBruno Larsen (billionai) if (strcmp(p + 1, q) != 0) { 89627468e2c8SBruno Larsen (billionai) /* Second instruction */ 89637468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x " 89647468e2c8SBruno Larsen (billionai) "(%02d %04d) : %s\n", opc1, 89657468e2c8SBruno Larsen (billionai) (opc2 << 1) | 1, opc3, opc1, 89667468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1) | 1, 89677468e2c8SBruno Larsen (billionai) p + 1); 89687468e2c8SBruno Larsen (billionai) } 89697468e2c8SBruno Larsen (billionai) } 89707468e2c8SBruno Larsen (billionai) } 89717468e2c8SBruno Larsen (billionai) } 89727468e2c8SBruno Larsen (billionai) } 89737468e2c8SBruno Larsen (billionai) } else { 89747468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89757468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 89767468e2c8SBruno Larsen (billionai) opc1, opc2, opc1, opc2, handler->oname); 89777468e2c8SBruno Larsen (billionai) } 89787468e2c8SBruno Larsen (billionai) } 89797468e2c8SBruno Larsen (billionai) } 89807468e2c8SBruno Larsen (billionai) } else { 89817468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89827468e2c8SBruno Larsen (billionai) printf("INSN: %02x -- -- (%02d ----) : %s\n", 89837468e2c8SBruno Larsen (billionai) opc1, opc1, handler->oname); 89847468e2c8SBruno Larsen (billionai) } 89857468e2c8SBruno Larsen (billionai) } 89867468e2c8SBruno Larsen (billionai) } 89877468e2c8SBruno Larsen (billionai) } 89887468e2c8SBruno Larsen (billionai) #endif 89897468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 89907468e2c8SBruno Larsen (billionai) { 89917468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 89927468e2c8SBruno Larsen (billionai) 89937468e2c8SBruno Larsen (billionai) /* 89947468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 89957468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 89967468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 89977468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 89987468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 89997468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 90007468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 90017468e2c8SBruno Larsen (billionai) */ 90027468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 90037468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 90047468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 90057468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 90067468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 90077468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 90087468e2c8SBruno Larsen (billionai) } 90097468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 90107468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 90117468e2c8SBruno Larsen (billionai) return 0; 90127468e2c8SBruno Larsen (billionai) } 90137468e2c8SBruno Larsen (billionai) 90147468e2c8SBruno Larsen (billionai) 901511cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 9016fcf5ef2aSThomas Huth { 9017fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9018fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 9019fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 9020fcf5ef2aSThomas Huth int op1, op2, op3; 9021fcf5ef2aSThomas Huth 9022fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 9023fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 9024fcf5ef2aSThomas Huth handler = t1[op1]; 9025fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9026fcf5ef2aSThomas Huth t2 = ind_table(handler); 9027fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 9028fcf5ef2aSThomas Huth handler = t2[op2]; 9029fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9030fcf5ef2aSThomas Huth t3 = ind_table(handler); 9031fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 9032fcf5ef2aSThomas Huth handler = t3[op3]; 9033efe843d8SDavid Gibson if (handler->count == 0) { 9034fcf5ef2aSThomas Huth continue; 9035efe843d8SDavid Gibson } 903611cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 9037fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9038fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 9039fcf5ef2aSThomas Huth handler->oname, 9040fcf5ef2aSThomas Huth handler->count, handler->count); 9041fcf5ef2aSThomas Huth } 9042fcf5ef2aSThomas Huth } else { 9043efe843d8SDavid Gibson if (handler->count == 0) { 9044fcf5ef2aSThomas Huth continue; 9045efe843d8SDavid Gibson } 904611cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 9047fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9048fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 9049fcf5ef2aSThomas Huth handler->count, handler->count); 9050fcf5ef2aSThomas Huth } 9051fcf5ef2aSThomas Huth } 9052fcf5ef2aSThomas Huth } else { 9053efe843d8SDavid Gibson if (handler->count == 0) { 9054fcf5ef2aSThomas Huth continue; 9055efe843d8SDavid Gibson } 905611cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 9057fcf5ef2aSThomas Huth " %" PRId64 "\n", 9058fcf5ef2aSThomas Huth op1, op1, handler->oname, 9059fcf5ef2aSThomas Huth handler->count, handler->count); 9060fcf5ef2aSThomas Huth } 9061fcf5ef2aSThomas Huth } 9062fcf5ef2aSThomas Huth #endif 9063fcf5ef2aSThomas Huth } 9064fcf5ef2aSThomas Huth 9065b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 9066fcf5ef2aSThomas Huth { 9067b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 90689c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 90692df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 9070b0c2d521SEmilio G. Cota int bound; 9071fcf5ef2aSThomas Huth 9072b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 9073b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 90742df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 9075d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 90762df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 90772df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 9078b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 9079b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 9080b0c2d521SEmilio G. Cota ctx->access_type = -1; 9081d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 90822df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 9083b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 90840e3bf489SRoman Kapl ctx->flags = env->flags; 9085fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 90862df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 9087b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 9088fcf5ef2aSThomas Huth #endif 9089e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 9090e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 9091d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 9092fcf5ef2aSThomas Huth 90932df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 90942df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 90952df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 90962df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 90972df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 9098f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 90992df4fe7aSRichard Henderson 9100b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 91012df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 91022df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 9103efe843d8SDavid Gibson } 91042df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 9105b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 9106efe843d8SDavid Gibson } 9107b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9108b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 9109fcf5ef2aSThomas Huth } 9110b0c2d521SEmilio G. Cota 9111b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 9112b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 9113fcf5ef2aSThomas Huth } 9114fcf5ef2aSThomas Huth 9115b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 9116b0c2d521SEmilio G. Cota { 9117b0c2d521SEmilio G. Cota } 9118fcf5ef2aSThomas Huth 9119b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 9120b0c2d521SEmilio G. Cota { 9121b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 9122b0c2d521SEmilio G. Cota } 9123b0c2d521SEmilio G. Cota 9124b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 9125b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 9126b0c2d521SEmilio G. Cota { 9127b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9128b0c2d521SEmilio G. Cota 9129b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 91302a8ceefcSEmilio G. Cota dcbase->is_jmp = DISAS_NORETURN; 9131efe843d8SDavid Gibson /* 9132efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 9133efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 9134efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 9135efe843d8SDavid Gibson * setting tb->size below does the right thing. 9136efe843d8SDavid Gibson */ 9137b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9138b0c2d521SEmilio G. Cota return true; 9139fcf5ef2aSThomas Huth } 9140fcf5ef2aSThomas Huth 9141b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 9142b0c2d521SEmilio G. Cota { 9143b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 914428876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 9145b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 9146b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 9147b0c2d521SEmilio G. Cota 9148fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 9149fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 9150b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 9151b0c2d521SEmilio G. Cota 9152*2c2bcb1bSRichard Henderson ctx->cia = ctx->base.pc_next; 915323f42b60SEmilio G. Cota ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, 915423f42b60SEmilio G. Cota need_byteswap(ctx)); 915523f42b60SEmilio G. Cota 9156fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 9157b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 9158b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 9159b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 9160b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 916128876bf2SAlex Bennée table = cpu->opcodes; 9162b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 9163fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9164fcf5ef2aSThomas Huth table = ind_table(handler); 9165b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 9166fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9167fcf5ef2aSThomas Huth table = ind_table(handler); 9168b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 9169fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9170fcf5ef2aSThomas Huth table = ind_table(handler); 9171b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 9172fcf5ef2aSThomas Huth } 9173fcf5ef2aSThomas Huth } 9174fcf5ef2aSThomas Huth } 9175fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 9176fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 9177fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 9178fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 9179fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 9180b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 9181b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 9182*2c2bcb1bSRichard Henderson ctx->opcode, ctx->cia, (int)msr_ir); 9183fcf5ef2aSThomas Huth } else { 9184fcf5ef2aSThomas Huth uint32_t inval; 9185fcf5ef2aSThomas Huth 9186b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 9187b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 9188fcf5ef2aSThomas Huth inval = handler->inval2; 9189fcf5ef2aSThomas Huth } else { 9190fcf5ef2aSThomas Huth inval = handler->inval1; 9191fcf5ef2aSThomas Huth } 9192fcf5ef2aSThomas Huth 9193b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 9194fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 9195fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 9196b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 9197b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 9198b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 9199*2c2bcb1bSRichard Henderson ctx->opcode, ctx->cia); 9200b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 9201b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 9202b0c2d521SEmilio G. Cota return; 9203fcf5ef2aSThomas Huth } 9204fcf5ef2aSThomas Huth } 9205b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 9206fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9207fcf5ef2aSThomas Huth handler->count++; 9208fcf5ef2aSThomas Huth #endif 9209fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 9210b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 9211b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 9212b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 9213b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 9214b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 9215e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 92160e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 9217fcf5ef2aSThomas Huth } 9218b0c2d521SEmilio G. Cota 9219fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 9220b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 9221b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 9222b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 9223fcf5ef2aSThomas Huth } 9224b0c2d521SEmilio G. Cota 9225b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 9226b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 9227fcf5ef2aSThomas Huth } 9228b0c2d521SEmilio G. Cota 9229b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 9230b0c2d521SEmilio G. Cota { 9231b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9232b0c2d521SEmilio G. Cota 9233b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 9234b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 9235b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 9236b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9237b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9238fcf5ef2aSThomas Huth } 9239fcf5ef2aSThomas Huth /* Generate the return instruction */ 924007ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 9241fcf5ef2aSThomas Huth } 9242fcf5ef2aSThomas Huth } 9243b0c2d521SEmilio G. Cota 9244b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 9245b0c2d521SEmilio G. Cota { 9246b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 9247b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 9248b0c2d521SEmilio G. Cota } 9249b0c2d521SEmilio G. Cota 9250b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 9251b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 9252b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 9253b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 9254b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 9255b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 9256b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 9257b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 9258b0c2d521SEmilio G. Cota }; 9259b0c2d521SEmilio G. Cota 92608b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 9261b0c2d521SEmilio G. Cota { 9262b0c2d521SEmilio G. Cota DisasContext ctx; 9263b0c2d521SEmilio G. Cota 92648b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 9265fcf5ef2aSThomas Huth } 9266fcf5ef2aSThomas Huth 9267fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 9268fcf5ef2aSThomas Huth target_ulong *data) 9269fcf5ef2aSThomas Huth { 9270fcf5ef2aSThomas Huth env->nip = data[0]; 9271fcf5ef2aSThomas Huth } 9272