1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35fcf5ef2aSThomas Huth #include "trace-tcg.h" 36b6bac4bcSEmilio G. Cota #include "exec/translator.h" 37fcf5ef2aSThomas Huth #include "exec/log.h" 38f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 39a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 40fcf5ef2aSThomas Huth 413e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 423e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 43fcf5ef2aSThomas Huth 44fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 45fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 46fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 47fcf5ef2aSThomas Huth 48fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 49efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 50efe843d8SDavid Gibson /* #define DO_PPC_STATISTICS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char *p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 125fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 131fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 133fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 135fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 137dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 139dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 143fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 144fcf5ef2aSThomas Huth "reserve_addr"); 145253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 146253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 147253ce7b2SNikunj A Dadhania "reserve_val"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 150fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 153efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 154efe843d8SDavid Gibson "access_type"); 155fcf5ef2aSThomas Huth } 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth /* internal defines */ 158fcf5ef2aSThomas Huth struct DisasContext { 159b6bac4bcSEmilio G. Cota DisasContextBase base; 1602c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 161fcf5ef2aSThomas Huth uint32_t opcode; 162fcf5ef2aSThomas Huth uint32_t exception; 163fcf5ef2aSThomas Huth /* Routine used to access memory */ 164fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 165fcf5ef2aSThomas Huth bool lazy_tlb_flush; 166fcf5ef2aSThomas Huth bool need_access_type; 167fcf5ef2aSThomas Huth int mem_idx; 168fcf5ef2aSThomas Huth int access_type; 169fcf5ef2aSThomas Huth /* Translation flags */ 17014776ab5STony Nguyen MemOp default_tcg_memop_mask; 171fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 172fcf5ef2aSThomas Huth bool sf_mode; 173fcf5ef2aSThomas Huth bool has_cfar; 174fcf5ef2aSThomas Huth #endif 175fcf5ef2aSThomas Huth bool fpu_enabled; 176fcf5ef2aSThomas Huth bool altivec_enabled; 177fcf5ef2aSThomas Huth bool vsx_enabled; 178fcf5ef2aSThomas Huth bool spe_enabled; 179fcf5ef2aSThomas Huth bool tm_enabled; 180c6fd28fdSSuraj Jitindar Singh bool gtse; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 189fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 190fcf5ef2aSThomas Huth { 191fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 192fcf5ef2aSThomas Huth return ctx->le_mode; 193fcf5ef2aSThomas Huth #else 194fcf5ef2aSThomas Huth return !ctx->le_mode; 195fcf5ef2aSThomas Huth #endif 196fcf5ef2aSThomas Huth } 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 199fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 200fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 201fcf5ef2aSThomas Huth #else 202fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 203fcf5ef2aSThomas Huth #endif 204fcf5ef2aSThomas Huth 205fcf5ef2aSThomas Huth struct opc_handler_t { 206fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 207fcf5ef2aSThomas Huth uint32_t inval1; 208fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 209fcf5ef2aSThomas Huth uint32_t inval2; 210fcf5ef2aSThomas Huth /* instruction type */ 211fcf5ef2aSThomas Huth uint64_t type; 212fcf5ef2aSThomas Huth /* extended instruction type */ 213fcf5ef2aSThomas Huth uint64_t type2; 214fcf5ef2aSThomas Huth /* handler */ 215fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 216fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 217fcf5ef2aSThomas Huth const char *oname; 218fcf5ef2aSThomas Huth #endif 219fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 220fcf5ef2aSThomas Huth uint64_t count; 221fcf5ef2aSThomas Huth #endif 222fcf5ef2aSThomas Huth }; 223fcf5ef2aSThomas Huth 2240e3bf489SRoman Kapl /* SPR load/store helpers */ 2250e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2260e3bf489SRoman Kapl { 2270e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2280e3bf489SRoman Kapl } 2290e3bf489SRoman Kapl 2300e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2310e3bf489SRoman Kapl { 2320e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2330e3bf489SRoman Kapl } 2340e3bf489SRoman Kapl 235fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 236fcf5ef2aSThomas Huth { 237fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 238fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 239fcf5ef2aSThomas Huth ctx->access_type = access_type; 240fcf5ef2aSThomas Huth } 241fcf5ef2aSThomas Huth } 242fcf5ef2aSThomas Huth 243fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 244fcf5ef2aSThomas Huth { 245fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 246fcf5ef2aSThomas Huth nip = (uint32_t)nip; 247fcf5ef2aSThomas Huth } 248fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 249fcf5ef2aSThomas Huth } 250fcf5ef2aSThomas Huth 251fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 252fcf5ef2aSThomas Huth { 253fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 254fcf5ef2aSThomas Huth 255efe843d8SDavid Gibson /* 256efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 257efe843d8SDavid Gibson * faulting instruction 258fcf5ef2aSThomas Huth */ 259fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 2602c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 261fcf5ef2aSThomas Huth } 262fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 263fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 264fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 265fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 266fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2673d8a5b69SRichard Henderson ctx->exception = excp; 2683d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 269fcf5ef2aSThomas Huth } 270fcf5ef2aSThomas Huth 271fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 272fcf5ef2aSThomas Huth { 273fcf5ef2aSThomas Huth TCGv_i32 t0; 274fcf5ef2aSThomas Huth 275efe843d8SDavid Gibson /* 276efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 277efe843d8SDavid Gibson * faulting instruction 278fcf5ef2aSThomas Huth */ 279fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 2802c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 281fcf5ef2aSThomas Huth } 282fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 283fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 284fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2853d8a5b69SRichard Henderson ctx->exception = excp; 2863d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 287fcf5ef2aSThomas Huth } 288fcf5ef2aSThomas Huth 289fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 290fcf5ef2aSThomas Huth target_ulong nip) 291fcf5ef2aSThomas Huth { 292fcf5ef2aSThomas Huth TCGv_i32 t0; 293fcf5ef2aSThomas Huth 294fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 295fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 296fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 297fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2983d8a5b69SRichard Henderson ctx->exception = excp; 2993d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 300fcf5ef2aSThomas Huth } 301fcf5ef2aSThomas Huth 302e150ac89SRoman Kapl /* 303e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 304e150ac89SRoman Kapl * SPR registers for this exception. 305e150ac89SRoman Kapl * 306e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 307e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3080e3bf489SRoman Kapl */ 309e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3100e3bf489SRoman Kapl { 3110e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3120e3bf489SRoman Kapl target_ulong dbsr = 0; 313e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3140e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 315e150ac89SRoman Kapl } else { 316e150ac89SRoman Kapl /* Must have been branch */ 3170e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3180e3bf489SRoman Kapl } 3190e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3200e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3210e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3220e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3230e3bf489SRoman Kapl tcg_temp_free(t0); 3240e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3250e3bf489SRoman Kapl } else { 326e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3270e3bf489SRoman Kapl } 3280e3bf489SRoman Kapl } 3290e3bf489SRoman Kapl 330fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 331fcf5ef2aSThomas Huth { 332*2736fc61SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 3333d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 334fcf5ef2aSThomas Huth } 335fcf5ef2aSThomas Huth 336fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 337fcf5ef2aSThomas Huth { 338fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 339fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 340fcf5ef2aSThomas Huth } 341fcf5ef2aSThomas Huth 342fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 343fcf5ef2aSThomas Huth { 344fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 345fcf5ef2aSThomas Huth } 346fcf5ef2aSThomas Huth 347fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 348fcf5ef2aSThomas Huth { 349fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 350fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 353fcf5ef2aSThomas Huth /* Stop translation */ 354fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 355fcf5ef2aSThomas Huth { 356b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 357fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 358fcf5ef2aSThomas Huth } 359fcf5ef2aSThomas Huth 360fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 361fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 362fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 363fcf5ef2aSThomas Huth { 364fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 365fcf5ef2aSThomas Huth } 366fcf5ef2aSThomas Huth #endif 367fcf5ef2aSThomas Huth 36837f219c8SBruno Larsen (billionai) /*****************************************************************************/ 36937f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 37037f219c8SBruno Larsen (billionai) 371a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 37237f219c8SBruno Larsen (billionai) { 37337f219c8SBruno Larsen (billionai) #if 0 37437f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 37537f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 37637f219c8SBruno Larsen (billionai) #endif 37737f219c8SBruno Larsen (billionai) } 37837f219c8SBruno Larsen (billionai) 37937f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 38037f219c8SBruno Larsen (billionai) 38137f219c8SBruno Larsen (billionai) /* 38237f219c8SBruno Larsen (billionai) * Generic callbacks: 38337f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 38437f219c8SBruno Larsen (billionai) */ 38537f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 38637f219c8SBruno Larsen (billionai) { 38737f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 38837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 38937f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 39037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39137f219c8SBruno Larsen (billionai) #endif 39237f219c8SBruno Larsen (billionai) } 39337f219c8SBruno Larsen (billionai) 394a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 39537f219c8SBruno Larsen (billionai) { 39637f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 39737f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 39837f219c8SBruno Larsen (billionai) } 39937f219c8SBruno Larsen (billionai) 40037f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 40137f219c8SBruno Larsen (billionai) { 40237f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 40337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 40437f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 40537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 40637f219c8SBruno Larsen (billionai) #endif 40737f219c8SBruno Larsen (billionai) } 40837f219c8SBruno Larsen (billionai) 409a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 41037f219c8SBruno Larsen (billionai) { 41137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 41237f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 41337f219c8SBruno Larsen (billionai) } 41437f219c8SBruno Larsen (billionai) 41537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 416a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 41737f219c8SBruno Larsen (billionai) { 41837f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 41937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42037f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 42137f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42437f219c8SBruno Larsen (billionai) #else 42537f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 42637f219c8SBruno Larsen (billionai) #endif 42737f219c8SBruno Larsen (billionai) } 42837f219c8SBruno Larsen (billionai) 429a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 43037f219c8SBruno Larsen (billionai) { 43137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 43337f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 43437f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 43537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 43637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 43837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 43937f219c8SBruno Larsen (billionai) } 44037f219c8SBruno Larsen (billionai) 441a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 44237f219c8SBruno Larsen (billionai) { 44337f219c8SBruno Larsen (billionai) } 44437f219c8SBruno Larsen (billionai) 44537f219c8SBruno Larsen (billionai) #endif 44637f219c8SBruno Larsen (billionai) 44737f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 44837f219c8SBruno Larsen (billionai) /* XER */ 449a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 45037f219c8SBruno Larsen (billionai) { 45137f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 45237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 45337f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 45437f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 45537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 45637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 45737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 45837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 45937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 46037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 46137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46237f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 46337f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 46437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46537f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 46637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46737f219c8SBruno Larsen (billionai) } 46837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 46937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 47037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 47137f219c8SBruno Larsen (billionai) } 47237f219c8SBruno Larsen (billionai) 473a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 47437f219c8SBruno Larsen (billionai) { 47537f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 47637f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 47737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 47837f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 47937f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 48037f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 48137f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 48237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 48337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 48437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 48537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 48637f219c8SBruno Larsen (billionai) } 48737f219c8SBruno Larsen (billionai) 48837f219c8SBruno Larsen (billionai) /* LR */ 489a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 49037f219c8SBruno Larsen (billionai) { 49137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 49237f219c8SBruno Larsen (billionai) } 49337f219c8SBruno Larsen (billionai) 494a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 49537f219c8SBruno Larsen (billionai) { 49637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 49737f219c8SBruno Larsen (billionai) } 49837f219c8SBruno Larsen (billionai) 49937f219c8SBruno Larsen (billionai) /* CFAR */ 50037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 501a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 50237f219c8SBruno Larsen (billionai) { 50337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 50437f219c8SBruno Larsen (billionai) } 50537f219c8SBruno Larsen (billionai) 506a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 50737f219c8SBruno Larsen (billionai) { 50837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 50937f219c8SBruno Larsen (billionai) } 51037f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 51137f219c8SBruno Larsen (billionai) 51237f219c8SBruno Larsen (billionai) /* CTR */ 513a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 51437f219c8SBruno Larsen (billionai) { 51537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 51637f219c8SBruno Larsen (billionai) } 51737f219c8SBruno Larsen (billionai) 518a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 51937f219c8SBruno Larsen (billionai) { 52037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 52137f219c8SBruno Larsen (billionai) } 52237f219c8SBruno Larsen (billionai) 52337f219c8SBruno Larsen (billionai) /* User read access to SPR */ 52437f219c8SBruno Larsen (billionai) /* USPRx */ 52537f219c8SBruno Larsen (billionai) /* UMMCRx */ 52637f219c8SBruno Larsen (billionai) /* UPMCx */ 52737f219c8SBruno Larsen (billionai) /* USIA */ 52837f219c8SBruno Larsen (billionai) /* UDECR */ 529a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 53037f219c8SBruno Larsen (billionai) { 53137f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 53237f219c8SBruno Larsen (billionai) } 53337f219c8SBruno Larsen (billionai) 53437f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 535a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 53637f219c8SBruno Larsen (billionai) { 53737f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 53837f219c8SBruno Larsen (billionai) } 53937f219c8SBruno Larsen (billionai) #endif 54037f219c8SBruno Larsen (billionai) 54137f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 54237f219c8SBruno Larsen (billionai) /* DECR */ 54337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 544a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 54537f219c8SBruno Larsen (billionai) { 54637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54737f219c8SBruno Larsen (billionai) gen_io_start(); 54837f219c8SBruno Larsen (billionai) } 54937f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 55037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 55137f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 55237f219c8SBruno Larsen (billionai) } 55337f219c8SBruno Larsen (billionai) } 55437f219c8SBruno Larsen (billionai) 555a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 55637f219c8SBruno Larsen (billionai) { 55737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 55837f219c8SBruno Larsen (billionai) gen_io_start(); 55937f219c8SBruno Larsen (billionai) } 56037f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 56137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 56237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 56337f219c8SBruno Larsen (billionai) } 56437f219c8SBruno Larsen (billionai) } 56537f219c8SBruno Larsen (billionai) #endif 56637f219c8SBruno Larsen (billionai) 56737f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 56837f219c8SBruno Larsen (billionai) /* Time base */ 569a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 57037f219c8SBruno Larsen (billionai) { 57137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 57237f219c8SBruno Larsen (billionai) gen_io_start(); 57337f219c8SBruno Larsen (billionai) } 57437f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 57537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 57637f219c8SBruno Larsen (billionai) gen_io_end(); 57737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 57837f219c8SBruno Larsen (billionai) } 57937f219c8SBruno Larsen (billionai) } 58037f219c8SBruno Larsen (billionai) 581a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 58237f219c8SBruno Larsen (billionai) { 58337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 58437f219c8SBruno Larsen (billionai) gen_io_start(); 58537f219c8SBruno Larsen (billionai) } 58637f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 58737f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 58837f219c8SBruno Larsen (billionai) gen_io_end(); 58937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 59037f219c8SBruno Larsen (billionai) } 59137f219c8SBruno Larsen (billionai) } 59237f219c8SBruno Larsen (billionai) 593a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 59437f219c8SBruno Larsen (billionai) { 59537f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 59637f219c8SBruno Larsen (billionai) } 59737f219c8SBruno Larsen (billionai) 598a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 59937f219c8SBruno Larsen (billionai) { 60037f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 60137f219c8SBruno Larsen (billionai) } 60237f219c8SBruno Larsen (billionai) 60337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 604a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 60537f219c8SBruno Larsen (billionai) { 60637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 60737f219c8SBruno Larsen (billionai) gen_io_start(); 60837f219c8SBruno Larsen (billionai) } 60937f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 61037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 61137f219c8SBruno Larsen (billionai) gen_io_end(); 61237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 61337f219c8SBruno Larsen (billionai) } 61437f219c8SBruno Larsen (billionai) } 61537f219c8SBruno Larsen (billionai) 616a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 61737f219c8SBruno Larsen (billionai) { 61837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 61937f219c8SBruno Larsen (billionai) gen_io_start(); 62037f219c8SBruno Larsen (billionai) } 62137f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 62237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 62337f219c8SBruno Larsen (billionai) gen_io_end(); 62437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 62537f219c8SBruno Larsen (billionai) } 62637f219c8SBruno Larsen (billionai) } 62737f219c8SBruno Larsen (billionai) 628a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 62937f219c8SBruno Larsen (billionai) { 63037f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 63137f219c8SBruno Larsen (billionai) } 63237f219c8SBruno Larsen (billionai) 633a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 63437f219c8SBruno Larsen (billionai) { 63537f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 63637f219c8SBruno Larsen (billionai) } 63737f219c8SBruno Larsen (billionai) 63837f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 639a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 64037f219c8SBruno Larsen (billionai) { 64137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 64237f219c8SBruno Larsen (billionai) gen_io_start(); 64337f219c8SBruno Larsen (billionai) } 64437f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 64537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 64637f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 64737f219c8SBruno Larsen (billionai) } 64837f219c8SBruno Larsen (billionai) } 64937f219c8SBruno Larsen (billionai) 650a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 65137f219c8SBruno Larsen (billionai) { 65237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 65337f219c8SBruno Larsen (billionai) gen_io_start(); 65437f219c8SBruno Larsen (billionai) } 65537f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 65637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 65737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 65837f219c8SBruno Larsen (billionai) } 65937f219c8SBruno Larsen (billionai) } 66037f219c8SBruno Larsen (billionai) 66137f219c8SBruno Larsen (billionai) /* HDECR */ 662a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 66337f219c8SBruno Larsen (billionai) { 66437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 66537f219c8SBruno Larsen (billionai) gen_io_start(); 66637f219c8SBruno Larsen (billionai) } 66737f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 66837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 66937f219c8SBruno Larsen (billionai) gen_io_end(); 67037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 67137f219c8SBruno Larsen (billionai) } 67237f219c8SBruno Larsen (billionai) } 67337f219c8SBruno Larsen (billionai) 674a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 67537f219c8SBruno Larsen (billionai) { 67637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 67737f219c8SBruno Larsen (billionai) gen_io_start(); 67837f219c8SBruno Larsen (billionai) } 67937f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 68037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 68137f219c8SBruno Larsen (billionai) gen_io_end(); 68237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) } 68537f219c8SBruno Larsen (billionai) 686a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 68737f219c8SBruno Larsen (billionai) { 68837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 68937f219c8SBruno Larsen (billionai) gen_io_start(); 69037f219c8SBruno Larsen (billionai) } 69137f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 69237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 69337f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 69437f219c8SBruno Larsen (billionai) } 69537f219c8SBruno Larsen (billionai) } 69637f219c8SBruno Larsen (billionai) 697a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 69837f219c8SBruno Larsen (billionai) { 69937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 70037f219c8SBruno Larsen (billionai) gen_io_start(); 70137f219c8SBruno Larsen (billionai) } 70237f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 70337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 70437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 70537f219c8SBruno Larsen (billionai) } 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) 708a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 70937f219c8SBruno Larsen (billionai) { 71037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 71137f219c8SBruno Larsen (billionai) gen_io_start(); 71237f219c8SBruno Larsen (billionai) } 71337f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 71437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 71537f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 71637f219c8SBruno Larsen (billionai) } 71737f219c8SBruno Larsen (billionai) } 71837f219c8SBruno Larsen (billionai) 71937f219c8SBruno Larsen (billionai) #endif 72037f219c8SBruno Larsen (billionai) #endif 72137f219c8SBruno Larsen (billionai) 72237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 72337f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 72437f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 725a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 72637f219c8SBruno Larsen (billionai) { 72737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 72837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 72937f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 73037f219c8SBruno Larsen (billionai) } 73137f219c8SBruno Larsen (billionai) 732a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 73337f219c8SBruno Larsen (billionai) { 73437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 73537f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 73637f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 73737f219c8SBruno Larsen (billionai) } 73837f219c8SBruno Larsen (billionai) 739a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 74037f219c8SBruno Larsen (billionai) { 74137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 74237f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 74337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74437f219c8SBruno Larsen (billionai) } 74537f219c8SBruno Larsen (billionai) 746a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 74737f219c8SBruno Larsen (billionai) { 74837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 74937f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 75037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75137f219c8SBruno Larsen (billionai) } 75237f219c8SBruno Larsen (billionai) 753a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 75437f219c8SBruno Larsen (billionai) { 75537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 75637f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 75737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 75837f219c8SBruno Larsen (billionai) } 75937f219c8SBruno Larsen (billionai) 760a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 76137f219c8SBruno Larsen (billionai) { 76237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 76337f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 76437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 76537f219c8SBruno Larsen (billionai) } 76637f219c8SBruno Larsen (billionai) 76737f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 76837f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 769a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 77037f219c8SBruno Larsen (billionai) { 77137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 77237f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 77337f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 77437f219c8SBruno Larsen (billionai) } 77537f219c8SBruno Larsen (billionai) 776a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 77737f219c8SBruno Larsen (billionai) { 77837f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 77937f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 78037f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 78137f219c8SBruno Larsen (billionai) } 78237f219c8SBruno Larsen (billionai) 783a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 78437f219c8SBruno Larsen (billionai) { 78537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 78637f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 78737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 79337f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 79437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 79537f219c8SBruno Larsen (billionai) } 79637f219c8SBruno Larsen (billionai) 797a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 79837f219c8SBruno Larsen (billionai) { 79937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 80037f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 80137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 80237f219c8SBruno Larsen (billionai) } 80337f219c8SBruno Larsen (billionai) 804a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 80537f219c8SBruno Larsen (billionai) { 80637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 80737f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 80837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 80937f219c8SBruno Larsen (billionai) } 81037f219c8SBruno Larsen (billionai) 81137f219c8SBruno Larsen (billionai) /* SDR1 */ 812a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 81337f219c8SBruno Larsen (billionai) { 81437f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 81537f219c8SBruno Larsen (billionai) } 81637f219c8SBruno Larsen (billionai) 81737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 81837f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 81937f219c8SBruno Larsen (billionai) /* PIDR */ 820a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 82137f219c8SBruno Larsen (billionai) { 82237f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 82337f219c8SBruno Larsen (billionai) } 82437f219c8SBruno Larsen (billionai) 825a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 82637f219c8SBruno Larsen (billionai) { 82737f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 82837f219c8SBruno Larsen (billionai) } 82937f219c8SBruno Larsen (billionai) 830a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 83137f219c8SBruno Larsen (billionai) { 83237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 83337f219c8SBruno Larsen (billionai) } 83437f219c8SBruno Larsen (billionai) 835a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 83637f219c8SBruno Larsen (billionai) { 83737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 83837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 83937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 84037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 84137f219c8SBruno Larsen (billionai) } 842a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 84337f219c8SBruno Larsen (billionai) { 84437f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 84537f219c8SBruno Larsen (billionai) } 84637f219c8SBruno Larsen (billionai) 847a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 84837f219c8SBruno Larsen (billionai) { 84937f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 85037f219c8SBruno Larsen (billionai) } 85137f219c8SBruno Larsen (billionai) 85237f219c8SBruno Larsen (billionai) /* DPDES */ 853a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 85437f219c8SBruno Larsen (billionai) { 85537f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 85637f219c8SBruno Larsen (billionai) } 85737f219c8SBruno Larsen (billionai) 858a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 85937f219c8SBruno Larsen (billionai) { 86037f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 86137f219c8SBruno Larsen (billionai) } 86237f219c8SBruno Larsen (billionai) #endif 86337f219c8SBruno Larsen (billionai) #endif 86437f219c8SBruno Larsen (billionai) 86537f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 86637f219c8SBruno Larsen (billionai) /* RTC */ 867a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 86837f219c8SBruno Larsen (billionai) { 86937f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 87037f219c8SBruno Larsen (billionai) } 87137f219c8SBruno Larsen (billionai) 872a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 87337f219c8SBruno Larsen (billionai) { 87437f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 87537f219c8SBruno Larsen (billionai) } 87637f219c8SBruno Larsen (billionai) 87737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 878a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 87937f219c8SBruno Larsen (billionai) { 88037f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 88137f219c8SBruno Larsen (billionai) } 88237f219c8SBruno Larsen (billionai) 883a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 88437f219c8SBruno Larsen (billionai) { 88537f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 88637f219c8SBruno Larsen (billionai) } 88737f219c8SBruno Larsen (billionai) 888a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 88937f219c8SBruno Larsen (billionai) { 89037f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 89137f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 89237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 89337f219c8SBruno Larsen (billionai) } 89437f219c8SBruno Larsen (billionai) #endif 89537f219c8SBruno Larsen (billionai) 89637f219c8SBruno Larsen (billionai) /* Unified bats */ 89737f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 898a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 89937f219c8SBruno Larsen (billionai) { 90037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 90137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 90237f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 90337f219c8SBruno Larsen (billionai) } 90437f219c8SBruno Larsen (billionai) 905a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 90637f219c8SBruno Larsen (billionai) { 90737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 90837f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 90937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91037f219c8SBruno Larsen (billionai) } 91137f219c8SBruno Larsen (billionai) 912a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 91337f219c8SBruno Larsen (billionai) { 91437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 91537f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 91637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 91737f219c8SBruno Larsen (billionai) } 91837f219c8SBruno Larsen (billionai) #endif 91937f219c8SBruno Larsen (billionai) 92037f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 92137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 922a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 92337f219c8SBruno Larsen (billionai) { 92437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 92537f219c8SBruno Larsen (billionai) gen_io_start(); 92637f219c8SBruno Larsen (billionai) } 92737f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 92837f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 92937f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 93037f219c8SBruno Larsen (billionai) } 93137f219c8SBruno Larsen (billionai) } 93237f219c8SBruno Larsen (billionai) 933a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 93437f219c8SBruno Larsen (billionai) { 93537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 93637f219c8SBruno Larsen (billionai) gen_io_start(); 93737f219c8SBruno Larsen (billionai) } 93837f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 93937f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 94037f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 94137f219c8SBruno Larsen (billionai) } 94237f219c8SBruno Larsen (billionai) } 94337f219c8SBruno Larsen (billionai) 944a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 94537f219c8SBruno Larsen (billionai) { 94637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 94737f219c8SBruno Larsen (billionai) gen_io_start(); 94837f219c8SBruno Larsen (billionai) } 94937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 95037f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 95137f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 95237f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 95337f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 95437f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 95537f219c8SBruno Larsen (billionai) } 95637f219c8SBruno Larsen (billionai) } 95737f219c8SBruno Larsen (billionai) 958a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 95937f219c8SBruno Larsen (billionai) { 96037f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 96137f219c8SBruno Larsen (billionai) gen_io_start(); 96237f219c8SBruno Larsen (billionai) } 96337f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 96437f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 96537f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 96637f219c8SBruno Larsen (billionai) } 96737f219c8SBruno Larsen (billionai) } 96837f219c8SBruno Larsen (billionai) 969a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 97037f219c8SBruno Larsen (billionai) { 97137f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 97237f219c8SBruno Larsen (billionai) gen_io_start(); 97337f219c8SBruno Larsen (billionai) } 97437f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 97537f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 97637f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 97737f219c8SBruno Larsen (billionai) } 97837f219c8SBruno Larsen (billionai) } 97937f219c8SBruno Larsen (billionai) 980a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 98137f219c8SBruno Larsen (billionai) { 98237f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 98337f219c8SBruno Larsen (billionai) gen_io_start(); 98437f219c8SBruno Larsen (billionai) } 98537f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 98637f219c8SBruno Larsen (billionai) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 98737f219c8SBruno Larsen (billionai) gen_stop_exception(ctx); 98837f219c8SBruno Larsen (billionai) } 98937f219c8SBruno Larsen (billionai) } 99037f219c8SBruno Larsen (billionai) #endif 99137f219c8SBruno Larsen (billionai) 99237f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 99337f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 99437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 995a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 99637f219c8SBruno Larsen (billionai) { 99737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 99837f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 99937f219c8SBruno Larsen (billionai) } 100037f219c8SBruno Larsen (billionai) 1001a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 100237f219c8SBruno Larsen (billionai) { 100337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 100437f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 100537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 100637f219c8SBruno Larsen (billionai) } 100737f219c8SBruno Larsen (billionai) 1008a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 100937f219c8SBruno Larsen (billionai) { 101037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 101137f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 101237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 101337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 101437f219c8SBruno Larsen (billionai) } 101537f219c8SBruno Larsen (billionai) #endif 101637f219c8SBruno Larsen (billionai) 101737f219c8SBruno Larsen (billionai) /* SPE specific registers */ 1018a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 101937f219c8SBruno Larsen (billionai) { 102037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 102137f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 102237f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 102337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 102437f219c8SBruno Larsen (billionai) } 102537f219c8SBruno Larsen (billionai) 1026a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 102737f219c8SBruno Larsen (billionai) { 102837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 102937f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 103037f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 103137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 103237f219c8SBruno Larsen (billionai) } 103337f219c8SBruno Larsen (billionai) 103437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 103537f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 1036a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 103737f219c8SBruno Larsen (billionai) { 103837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 103937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 104037f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 104137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 104237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 104337f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 104437f219c8SBruno Larsen (billionai) } 104537f219c8SBruno Larsen (billionai) 1046a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 104737f219c8SBruno Larsen (billionai) { 104837f219c8SBruno Larsen (billionai) int sprn_offs; 104937f219c8SBruno Larsen (billionai) 105037f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 105137f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 105237f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 105337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 105437f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 105537f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 105637f219c8SBruno Larsen (billionai) } else { 105737f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 105837f219c8SBruno Larsen (billionai) sprn, sprn); 105937f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 106037f219c8SBruno Larsen (billionai) return; 106137f219c8SBruno Larsen (billionai) } 106237f219c8SBruno Larsen (billionai) 106337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 106437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 106537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 106637f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 106737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 106837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 106937f219c8SBruno Larsen (billionai) } 107037f219c8SBruno Larsen (billionai) #endif 107137f219c8SBruno Larsen (billionai) 107237f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 107337f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1074a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 107537f219c8SBruno Larsen (billionai) { 107637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 107737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 107837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 107937f219c8SBruno Larsen (billionai) 108037f219c8SBruno Larsen (billionai) /* 108137f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 108237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 108337f219c8SBruno Larsen (billionai) */ 108437f219c8SBruno Larsen (billionai) 108537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 108637f219c8SBruno Larsen (billionai) if (ctx->pr) { 108737f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 108837f219c8SBruno Larsen (billionai) } else { 108937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 109037f219c8SBruno Larsen (billionai) } 109137f219c8SBruno Larsen (billionai) 109237f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 109337f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 109437f219c8SBruno Larsen (billionai) 109537f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 109637f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 109737f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 109837f219c8SBruno Larsen (billionai) 109937f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 110037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 110137f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 110237f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 110337f219c8SBruno Larsen (billionai) 110437f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 110537f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 110637f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 110737f219c8SBruno Larsen (billionai) } 110837f219c8SBruno Larsen (billionai) 1109a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 111037f219c8SBruno Larsen (billionai) { 111137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 111237f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 111337f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 111437f219c8SBruno Larsen (billionai) 111537f219c8SBruno Larsen (billionai) /* 111637f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 111737f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 111837f219c8SBruno Larsen (billionai) */ 111937f219c8SBruno Larsen (billionai) 112037f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 112137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 112237f219c8SBruno Larsen (billionai) 112337f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 112437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 112537f219c8SBruno Larsen (billionai) 112637f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 112737f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 112837f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 112937f219c8SBruno Larsen (billionai) 113037f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 113137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 113237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 113337f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 113437f219c8SBruno Larsen (billionai) 113537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 113637f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 113737f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 113837f219c8SBruno Larsen (billionai) } 113937f219c8SBruno Larsen (billionai) 1140a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 114137f219c8SBruno Larsen (billionai) { 114237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 114337f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 114437f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 114537f219c8SBruno Larsen (billionai) 114637f219c8SBruno Larsen (billionai) /* 114737f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 114837f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 114937f219c8SBruno Larsen (billionai) */ 115037f219c8SBruno Larsen (billionai) 115137f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 115237f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 115337f219c8SBruno Larsen (billionai) 115437f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 115537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 115637f219c8SBruno Larsen (billionai) 115737f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 115837f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 115937f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 116037f219c8SBruno Larsen (billionai) 116137f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 116237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 116337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 116437f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 116537f219c8SBruno Larsen (billionai) 116637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 116737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 116837f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 116937f219c8SBruno Larsen (billionai) } 117037f219c8SBruno Larsen (billionai) #endif 117137f219c8SBruno Larsen (billionai) #endif 117237f219c8SBruno Larsen (billionai) 117337f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1174a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 117537f219c8SBruno Larsen (billionai) { 117637f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 117737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 117837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 117937f219c8SBruno Larsen (billionai) } 118037f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 118137f219c8SBruno Larsen (billionai) 118237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1183a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 118437f219c8SBruno Larsen (billionai) { 118537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 118637f219c8SBruno Larsen (billionai) 118737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 118837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 118937f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 119037f219c8SBruno Larsen (billionai) } 119137f219c8SBruno Larsen (billionai) 1192a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 119337f219c8SBruno Larsen (billionai) { 119437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 119537f219c8SBruno Larsen (billionai) 119637f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 119737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 119837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 119937f219c8SBruno Larsen (billionai) } 120037f219c8SBruno Larsen (billionai) 1201a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 120237f219c8SBruno Larsen (billionai) { 120337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 120437f219c8SBruno Larsen (billionai) 120537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 120637f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 120737f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 120837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 120937f219c8SBruno Larsen (billionai) } 121037f219c8SBruno Larsen (billionai) 1211a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 121237f219c8SBruno Larsen (billionai) { 121337f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 121437f219c8SBruno Larsen (billionai) } 121537f219c8SBruno Larsen (billionai) 1216a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 121737f219c8SBruno Larsen (billionai) { 121837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 121937f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 122037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 122137f219c8SBruno Larsen (billionai) } 1222a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 122337f219c8SBruno Larsen (billionai) { 122437f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 122537f219c8SBruno Larsen (billionai) } 1226a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 122737f219c8SBruno Larsen (billionai) { 122837f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 122937f219c8SBruno Larsen (billionai) } 123037f219c8SBruno Larsen (billionai) 123137f219c8SBruno Larsen (billionai) #endif 123237f219c8SBruno Larsen (billionai) 123337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1234a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 123537f219c8SBruno Larsen (billionai) { 123637f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 123737f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 123837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 123937f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 124037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 124137f219c8SBruno Larsen (billionai) tcg_temp_free(val); 124237f219c8SBruno Larsen (billionai) } 124337f219c8SBruno Larsen (billionai) 1244a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 124537f219c8SBruno Larsen (billionai) { 124637f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 124737f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 124837f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 124937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 125037f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 125137f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 125237f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 125337f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 125437f219c8SBruno Larsen (billionai) } 125537f219c8SBruno Larsen (billionai) 125637f219c8SBruno Larsen (billionai) #endif 125737f219c8SBruno Larsen (billionai) 125837f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 125937f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 126037f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 126137f219c8SBruno Larsen (billionai) { 126237f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 126337f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 126437f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 126537f219c8SBruno Larsen (billionai) 126637f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 126737f219c8SBruno Larsen (billionai) 126837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 126937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 127037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 127137f219c8SBruno Larsen (billionai) } 127237f219c8SBruno Larsen (billionai) 127337f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 127437f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 127537f219c8SBruno Larsen (billionai) { 127637f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 127737f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 127837f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 127937f219c8SBruno Larsen (billionai) 128037f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 128137f219c8SBruno Larsen (billionai) 128237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 128337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 128437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 128537f219c8SBruno Larsen (billionai) } 128637f219c8SBruno Larsen (billionai) 1287a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 128837f219c8SBruno Larsen (billionai) { 128937f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 129037f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 129137f219c8SBruno Larsen (billionai) 129237f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 129337f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 129437f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 129537f219c8SBruno Larsen (billionai) 129637f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 129737f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 129837f219c8SBruno Larsen (billionai) } 129937f219c8SBruno Larsen (billionai) 1300a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 130137f219c8SBruno Larsen (billionai) { 130237f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 130337f219c8SBruno Larsen (billionai) 130437f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 130537f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 130637f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 130737f219c8SBruno Larsen (billionai) 130837f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 130937f219c8SBruno Larsen (billionai) } 131037f219c8SBruno Larsen (billionai) 131137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1312a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 131337f219c8SBruno Larsen (billionai) { 131437f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 131537f219c8SBruno Larsen (billionai) 131637f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 131737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 131837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 131937f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 132037f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 132137f219c8SBruno Larsen (billionai) } 132237f219c8SBruno Larsen (billionai) 1323a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 132437f219c8SBruno Larsen (billionai) { 132537f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 132637f219c8SBruno Larsen (billionai) } 132737f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 132837f219c8SBruno Larsen (billionai) 1329a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 133037f219c8SBruno Larsen (billionai) { 133137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 133237f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 133337f219c8SBruno Larsen (billionai) } 133437f219c8SBruno Larsen (billionai) 1335a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 133637f219c8SBruno Larsen (billionai) { 133737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 133837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 133937f219c8SBruno Larsen (billionai) } 134037f219c8SBruno Larsen (billionai) 1341a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 134237f219c8SBruno Larsen (billionai) { 134337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 134437f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 134537f219c8SBruno Larsen (billionai) } 134637f219c8SBruno Larsen (billionai) 1347a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 134837f219c8SBruno Larsen (billionai) { 134937f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 135037f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 135137f219c8SBruno Larsen (billionai) } 135237f219c8SBruno Larsen (billionai) 1353a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 135437f219c8SBruno Larsen (billionai) { 135537f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 135637f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 135737f219c8SBruno Larsen (billionai) } 135837f219c8SBruno Larsen (billionai) 1359a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 136037f219c8SBruno Larsen (billionai) { 136137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 136237f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 136337f219c8SBruno Larsen (billionai) } 136437f219c8SBruno Larsen (billionai) 1365a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 136637f219c8SBruno Larsen (billionai) { 136737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 136837f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 136937f219c8SBruno Larsen (billionai) } 137037f219c8SBruno Larsen (billionai) 1371a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 137237f219c8SBruno Larsen (billionai) { 137337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 137437f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 137537f219c8SBruno Larsen (billionai) } 137637f219c8SBruno Larsen (billionai) 1377a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 137837f219c8SBruno Larsen (billionai) { 137937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 138037f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 138137f219c8SBruno Larsen (billionai) } 138237f219c8SBruno Larsen (billionai) 1383a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 138437f219c8SBruno Larsen (billionai) { 138537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 138637f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 138737f219c8SBruno Larsen (billionai) } 138837f219c8SBruno Larsen (billionai) #endif 138937f219c8SBruno Larsen (billionai) 1390fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1391fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1392fcf5ef2aSThomas Huth 1393fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1394fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1395fcf5ef2aSThomas Huth 1396fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1397fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1398fcf5ef2aSThomas Huth 1399fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1400fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1401fcf5ef2aSThomas Huth 1402fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1403fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1404fcf5ef2aSThomas Huth 1405fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1406fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1407fcf5ef2aSThomas Huth 1408fcf5ef2aSThomas Huth typedef struct opcode_t { 1409fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1410fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1411fcf5ef2aSThomas Huth unsigned char pad[4]; 1412fcf5ef2aSThomas Huth #endif 1413fcf5ef2aSThomas Huth opc_handler_t handler; 1414fcf5ef2aSThomas Huth const char *oname; 1415fcf5ef2aSThomas Huth } opcode_t; 1416fcf5ef2aSThomas Huth 1417fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1418fcf5ef2aSThomas Huth #define GEN_PRIV \ 1419fcf5ef2aSThomas Huth do { \ 1420fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1421fcf5ef2aSThomas Huth } while (0) 1422fcf5ef2aSThomas Huth 1423fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1424fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1425fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1426fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1427fcf5ef2aSThomas Huth #else 1428fcf5ef2aSThomas Huth #define CHK_HV \ 1429fcf5ef2aSThomas Huth do { \ 1430fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1431fcf5ef2aSThomas Huth GEN_PRIV; \ 1432fcf5ef2aSThomas Huth } \ 1433fcf5ef2aSThomas Huth } while (0) 1434fcf5ef2aSThomas Huth #define CHK_SV \ 1435fcf5ef2aSThomas Huth do { \ 1436fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1437fcf5ef2aSThomas Huth GEN_PRIV; \ 1438fcf5ef2aSThomas Huth } \ 1439fcf5ef2aSThomas Huth } while (0) 1440fcf5ef2aSThomas Huth #define CHK_HVRM \ 1441fcf5ef2aSThomas Huth do { \ 1442fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1443fcf5ef2aSThomas Huth GEN_PRIV; \ 1444fcf5ef2aSThomas Huth } \ 1445fcf5ef2aSThomas Huth } while (0) 1446fcf5ef2aSThomas Huth #endif 1447fcf5ef2aSThomas Huth 1448fcf5ef2aSThomas Huth #define CHK_NONE 1449fcf5ef2aSThomas Huth 1450fcf5ef2aSThomas Huth /*****************************************************************************/ 1451fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 1454fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1455fcf5ef2aSThomas Huth { \ 1456fcf5ef2aSThomas Huth .opc1 = op1, \ 1457fcf5ef2aSThomas Huth .opc2 = op2, \ 1458fcf5ef2aSThomas Huth .opc3 = op3, \ 1459fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1460fcf5ef2aSThomas Huth .handler = { \ 1461fcf5ef2aSThomas Huth .inval1 = invl, \ 1462fcf5ef2aSThomas Huth .type = _typ, \ 1463fcf5ef2aSThomas Huth .type2 = _typ2, \ 1464fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1465fcf5ef2aSThomas Huth .oname = stringify(name), \ 1466fcf5ef2aSThomas Huth }, \ 1467fcf5ef2aSThomas Huth .oname = stringify(name), \ 1468fcf5ef2aSThomas Huth } 1469fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1470fcf5ef2aSThomas Huth { \ 1471fcf5ef2aSThomas Huth .opc1 = op1, \ 1472fcf5ef2aSThomas Huth .opc2 = op2, \ 1473fcf5ef2aSThomas Huth .opc3 = op3, \ 1474fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1475fcf5ef2aSThomas Huth .handler = { \ 1476fcf5ef2aSThomas Huth .inval1 = invl1, \ 1477fcf5ef2aSThomas Huth .inval2 = invl2, \ 1478fcf5ef2aSThomas Huth .type = _typ, \ 1479fcf5ef2aSThomas Huth .type2 = _typ2, \ 1480fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1481fcf5ef2aSThomas Huth .oname = stringify(name), \ 1482fcf5ef2aSThomas Huth }, \ 1483fcf5ef2aSThomas Huth .oname = stringify(name), \ 1484fcf5ef2aSThomas Huth } 1485fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1486fcf5ef2aSThomas Huth { \ 1487fcf5ef2aSThomas Huth .opc1 = op1, \ 1488fcf5ef2aSThomas Huth .opc2 = op2, \ 1489fcf5ef2aSThomas Huth .opc3 = op3, \ 1490fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1491fcf5ef2aSThomas Huth .handler = { \ 1492fcf5ef2aSThomas Huth .inval1 = invl, \ 1493fcf5ef2aSThomas Huth .type = _typ, \ 1494fcf5ef2aSThomas Huth .type2 = _typ2, \ 1495fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1496fcf5ef2aSThomas Huth .oname = onam, \ 1497fcf5ef2aSThomas Huth }, \ 1498fcf5ef2aSThomas Huth .oname = onam, \ 1499fcf5ef2aSThomas Huth } 1500fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1501fcf5ef2aSThomas Huth { \ 1502fcf5ef2aSThomas Huth .opc1 = op1, \ 1503fcf5ef2aSThomas Huth .opc2 = op2, \ 1504fcf5ef2aSThomas Huth .opc3 = op3, \ 1505fcf5ef2aSThomas Huth .opc4 = op4, \ 1506fcf5ef2aSThomas Huth .handler = { \ 1507fcf5ef2aSThomas Huth .inval1 = invl, \ 1508fcf5ef2aSThomas Huth .type = _typ, \ 1509fcf5ef2aSThomas Huth .type2 = _typ2, \ 1510fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1511fcf5ef2aSThomas Huth .oname = stringify(name), \ 1512fcf5ef2aSThomas Huth }, \ 1513fcf5ef2aSThomas Huth .oname = stringify(name), \ 1514fcf5ef2aSThomas Huth } 1515fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1516fcf5ef2aSThomas Huth { \ 1517fcf5ef2aSThomas Huth .opc1 = op1, \ 1518fcf5ef2aSThomas Huth .opc2 = op2, \ 1519fcf5ef2aSThomas Huth .opc3 = op3, \ 1520fcf5ef2aSThomas Huth .opc4 = op4, \ 1521fcf5ef2aSThomas Huth .handler = { \ 1522fcf5ef2aSThomas Huth .inval1 = invl, \ 1523fcf5ef2aSThomas Huth .type = _typ, \ 1524fcf5ef2aSThomas Huth .type2 = _typ2, \ 1525fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1526fcf5ef2aSThomas Huth .oname = onam, \ 1527fcf5ef2aSThomas Huth }, \ 1528fcf5ef2aSThomas Huth .oname = onam, \ 1529fcf5ef2aSThomas Huth } 1530fcf5ef2aSThomas Huth #else 1531fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1532fcf5ef2aSThomas Huth { \ 1533fcf5ef2aSThomas Huth .opc1 = op1, \ 1534fcf5ef2aSThomas Huth .opc2 = op2, \ 1535fcf5ef2aSThomas Huth .opc3 = op3, \ 1536fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1537fcf5ef2aSThomas Huth .handler = { \ 1538fcf5ef2aSThomas Huth .inval1 = invl, \ 1539fcf5ef2aSThomas Huth .type = _typ, \ 1540fcf5ef2aSThomas Huth .type2 = _typ2, \ 1541fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1542fcf5ef2aSThomas Huth }, \ 1543fcf5ef2aSThomas Huth .oname = stringify(name), \ 1544fcf5ef2aSThomas Huth } 1545fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1546fcf5ef2aSThomas Huth { \ 1547fcf5ef2aSThomas Huth .opc1 = op1, \ 1548fcf5ef2aSThomas Huth .opc2 = op2, \ 1549fcf5ef2aSThomas Huth .opc3 = op3, \ 1550fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1551fcf5ef2aSThomas Huth .handler = { \ 1552fcf5ef2aSThomas Huth .inval1 = invl1, \ 1553fcf5ef2aSThomas Huth .inval2 = invl2, \ 1554fcf5ef2aSThomas Huth .type = _typ, \ 1555fcf5ef2aSThomas Huth .type2 = _typ2, \ 1556fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1557fcf5ef2aSThomas Huth }, \ 1558fcf5ef2aSThomas Huth .oname = stringify(name), \ 1559fcf5ef2aSThomas Huth } 1560fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1561fcf5ef2aSThomas Huth { \ 1562fcf5ef2aSThomas Huth .opc1 = op1, \ 1563fcf5ef2aSThomas Huth .opc2 = op2, \ 1564fcf5ef2aSThomas Huth .opc3 = op3, \ 1565fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1566fcf5ef2aSThomas Huth .handler = { \ 1567fcf5ef2aSThomas Huth .inval1 = invl, \ 1568fcf5ef2aSThomas Huth .type = _typ, \ 1569fcf5ef2aSThomas Huth .type2 = _typ2, \ 1570fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1571fcf5ef2aSThomas Huth }, \ 1572fcf5ef2aSThomas Huth .oname = onam, \ 1573fcf5ef2aSThomas Huth } 1574fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1575fcf5ef2aSThomas Huth { \ 1576fcf5ef2aSThomas Huth .opc1 = op1, \ 1577fcf5ef2aSThomas Huth .opc2 = op2, \ 1578fcf5ef2aSThomas Huth .opc3 = op3, \ 1579fcf5ef2aSThomas Huth .opc4 = op4, \ 1580fcf5ef2aSThomas Huth .handler = { \ 1581fcf5ef2aSThomas Huth .inval1 = invl, \ 1582fcf5ef2aSThomas Huth .type = _typ, \ 1583fcf5ef2aSThomas Huth .type2 = _typ2, \ 1584fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1585fcf5ef2aSThomas Huth }, \ 1586fcf5ef2aSThomas Huth .oname = stringify(name), \ 1587fcf5ef2aSThomas Huth } 1588fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1589fcf5ef2aSThomas Huth { \ 1590fcf5ef2aSThomas Huth .opc1 = op1, \ 1591fcf5ef2aSThomas Huth .opc2 = op2, \ 1592fcf5ef2aSThomas Huth .opc3 = op3, \ 1593fcf5ef2aSThomas Huth .opc4 = op4, \ 1594fcf5ef2aSThomas Huth .handler = { \ 1595fcf5ef2aSThomas Huth .inval1 = invl, \ 1596fcf5ef2aSThomas Huth .type = _typ, \ 1597fcf5ef2aSThomas Huth .type2 = _typ2, \ 1598fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1599fcf5ef2aSThomas Huth }, \ 1600fcf5ef2aSThomas Huth .oname = onam, \ 1601fcf5ef2aSThomas Huth } 1602fcf5ef2aSThomas Huth #endif 1603fcf5ef2aSThomas Huth 1604fcf5ef2aSThomas Huth /* Invalid instruction */ 1605fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1606fcf5ef2aSThomas Huth { 1607fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1608fcf5ef2aSThomas Huth } 1609fcf5ef2aSThomas Huth 1610fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1611fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1612fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1613fcf5ef2aSThomas Huth .type = PPC_NONE, 1614fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1615fcf5ef2aSThomas Huth .handler = gen_invalid, 1616fcf5ef2aSThomas Huth }; 1617fcf5ef2aSThomas Huth 1618fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1619fcf5ef2aSThomas Huth 1620fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1621fcf5ef2aSThomas Huth { 1622fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1623b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1624b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1625fcf5ef2aSThomas Huth 1626b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1627b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1628efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1629efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1630b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1631efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1632efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1633b62b3686Spbonzini@redhat.com 1634b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1635fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1636b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1637fcf5ef2aSThomas Huth 1638fcf5ef2aSThomas Huth tcg_temp_free(t0); 1639b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1640b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1641fcf5ef2aSThomas Huth } 1642fcf5ef2aSThomas Huth 1643fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1644fcf5ef2aSThomas Huth { 1645fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1646fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1647fcf5ef2aSThomas Huth tcg_temp_free(t0); 1648fcf5ef2aSThomas Huth } 1649fcf5ef2aSThomas Huth 1650fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1651fcf5ef2aSThomas Huth { 1652fcf5ef2aSThomas Huth TCGv t0, t1; 1653fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1654fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1655fcf5ef2aSThomas Huth if (s) { 1656fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1657fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1658fcf5ef2aSThomas Huth } else { 1659fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1660fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1661fcf5ef2aSThomas Huth } 1662fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1663fcf5ef2aSThomas Huth tcg_temp_free(t1); 1664fcf5ef2aSThomas Huth tcg_temp_free(t0); 1665fcf5ef2aSThomas Huth } 1666fcf5ef2aSThomas Huth 1667fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1668fcf5ef2aSThomas Huth { 1669fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1670fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1671fcf5ef2aSThomas Huth tcg_temp_free(t0); 1672fcf5ef2aSThomas Huth } 1673fcf5ef2aSThomas Huth 1674fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1675fcf5ef2aSThomas Huth { 1676fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1677fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1678fcf5ef2aSThomas Huth } else { 1679fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1680fcf5ef2aSThomas Huth } 1681fcf5ef2aSThomas Huth } 1682fcf5ef2aSThomas Huth 1683fcf5ef2aSThomas Huth /* cmp */ 1684fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 1685fcf5ef2aSThomas Huth { 1686fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1687fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1688fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1689fcf5ef2aSThomas Huth } else { 1690fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1691fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1692fcf5ef2aSThomas Huth } 1693fcf5ef2aSThomas Huth } 1694fcf5ef2aSThomas Huth 1695fcf5ef2aSThomas Huth /* cmpi */ 1696fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 1697fcf5ef2aSThomas Huth { 1698fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1699fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1700fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1701fcf5ef2aSThomas Huth } else { 1702fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 1703fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 1704fcf5ef2aSThomas Huth } 1705fcf5ef2aSThomas Huth } 1706fcf5ef2aSThomas Huth 1707fcf5ef2aSThomas Huth /* cmpl */ 1708fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 1709fcf5ef2aSThomas Huth { 1710fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1711fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1712fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1713fcf5ef2aSThomas Huth } else { 1714fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 1715fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1716fcf5ef2aSThomas Huth } 1717fcf5ef2aSThomas Huth } 1718fcf5ef2aSThomas Huth 1719fcf5ef2aSThomas Huth /* cmpli */ 1720fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 1721fcf5ef2aSThomas Huth { 1722fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 1723fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1724fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1725fcf5ef2aSThomas Huth } else { 1726fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 1727fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 1728fcf5ef2aSThomas Huth } 1729fcf5ef2aSThomas Huth } 1730fcf5ef2aSThomas Huth 1731fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1732fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1733fcf5ef2aSThomas Huth { 1734fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1735fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1736fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1737fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1738fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1739fcf5ef2aSThomas Huth 1740fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1741fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1742fcf5ef2aSThomas Huth 1743fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1744fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1745fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1746fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1747fcf5ef2aSThomas Huth 1748fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1749fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1750fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1751fcf5ef2aSThomas Huth 1752fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1753fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1754fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1755fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1756fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1757fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1758fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1759fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1760fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1761fcf5ef2aSThomas Huth } 1762efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1763fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1764fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1765fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1766fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1767fcf5ef2aSThomas Huth } 1768fcf5ef2aSThomas Huth 1769fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1770fcf5ef2aSThomas Huth /* cmpeqb */ 1771fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1772fcf5ef2aSThomas Huth { 1773fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1774fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1775fcf5ef2aSThomas Huth } 1776fcf5ef2aSThomas Huth #endif 1777fcf5ef2aSThomas Huth 1778fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1779fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1780fcf5ef2aSThomas Huth { 1781fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1782fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1783fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1784fcf5ef2aSThomas Huth TCGv zr; 1785fcf5ef2aSThomas Huth 1786fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1787fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1788fcf5ef2aSThomas Huth 1789fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1790fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1791fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1792fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1793fcf5ef2aSThomas Huth tcg_temp_free(zr); 1794fcf5ef2aSThomas Huth tcg_temp_free(t0); 1795fcf5ef2aSThomas Huth } 1796fcf5ef2aSThomas Huth 1797fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1798fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1799fcf5ef2aSThomas Huth { 1800fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1801fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1802fcf5ef2aSThomas Huth } 1803fcf5ef2aSThomas Huth 1804fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1805fcf5ef2aSThomas Huth 1806fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1807fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1808fcf5ef2aSThomas Huth { 1809fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1810fcf5ef2aSThomas Huth 1811fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1812fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1813fcf5ef2aSThomas Huth if (sub) { 1814fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1815fcf5ef2aSThomas Huth } else { 1816fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1817fcf5ef2aSThomas Huth } 1818fcf5ef2aSThomas Huth tcg_temp_free(t0); 1819fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1820dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1821dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1822dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1823fcf5ef2aSThomas Huth } 1824dc0ad844SNikunj A Dadhania } else { 1825dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1826dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1827dc0ad844SNikunj A Dadhania } 182838a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1829dc0ad844SNikunj A Dadhania } 1830fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1831fcf5ef2aSThomas Huth } 1832fcf5ef2aSThomas Huth 18336b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 18346b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 18354c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 18366b10d008SNikunj A Dadhania { 18376b10d008SNikunj A Dadhania TCGv t0; 18386b10d008SNikunj A Dadhania 18396b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 18406b10d008SNikunj A Dadhania return; 18416b10d008SNikunj A Dadhania } 18426b10d008SNikunj A Dadhania 18436b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 184433903d0aSNikunj A Dadhania if (sub) { 184533903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 184633903d0aSNikunj A Dadhania } else { 18476b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 184833903d0aSNikunj A Dadhania } 18496b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 18504c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 18516b10d008SNikunj A Dadhania tcg_temp_free(t0); 18526b10d008SNikunj A Dadhania } 18536b10d008SNikunj A Dadhania 1854fcf5ef2aSThomas Huth /* Common add function */ 1855fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 18564c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 18574c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1858fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1859fcf5ef2aSThomas Huth { 1860fcf5ef2aSThomas Huth TCGv t0 = ret; 1861fcf5ef2aSThomas Huth 1862fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1863fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1864fcf5ef2aSThomas Huth } 1865fcf5ef2aSThomas Huth 1866fcf5ef2aSThomas Huth if (compute_ca) { 1867fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1868efe843d8SDavid Gibson /* 1869efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1870efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1871efe843d8SDavid Gibson * produce the carry into bit 32. 1872efe843d8SDavid Gibson */ 1873fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1874fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1875fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1876fcf5ef2aSThomas Huth if (add_ca) { 18774c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1878fcf5ef2aSThomas Huth } 18794c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1880fcf5ef2aSThomas Huth tcg_temp_free(t1); 18814c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 18826b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 18834c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 18846b10d008SNikunj A Dadhania } 1885fcf5ef2aSThomas Huth } else { 1886fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1887fcf5ef2aSThomas Huth if (add_ca) { 18884c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 18894c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1890fcf5ef2aSThomas Huth } else { 18914c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1892fcf5ef2aSThomas Huth } 18934c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1894fcf5ef2aSThomas Huth tcg_temp_free(zero); 1895fcf5ef2aSThomas Huth } 1896fcf5ef2aSThomas Huth } else { 1897fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1898fcf5ef2aSThomas Huth if (add_ca) { 18994c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1900fcf5ef2aSThomas Huth } 1901fcf5ef2aSThomas Huth } 1902fcf5ef2aSThomas Huth 1903fcf5ef2aSThomas Huth if (compute_ov) { 1904fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1905fcf5ef2aSThomas Huth } 1906fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1907fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1908fcf5ef2aSThomas Huth } 1909fcf5ef2aSThomas Huth 191011f4e8f8SRichard Henderson if (t0 != ret) { 1911fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1912fcf5ef2aSThomas Huth tcg_temp_free(t0); 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth } 1915fcf5ef2aSThomas Huth /* Add functions with two operands */ 19164c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1917fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1918fcf5ef2aSThomas Huth { \ 1919fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1920fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 19214c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1922fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1923fcf5ef2aSThomas Huth } 1924fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 19254c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1926fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1927fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1928fcf5ef2aSThomas Huth { \ 1929fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1930fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1931fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 19324c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1933fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1934fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1935fcf5ef2aSThomas Huth } 1936fcf5ef2aSThomas Huth 1937fcf5ef2aSThomas Huth /* add add. addo addo. */ 19384c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 19394c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1940fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 19414c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 19424c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1943fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 19444c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 19454c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1946fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 19474c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 19484c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 19494c5920afSSuraj Jitindar Singh /* addex */ 19504c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1951fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 19524c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 19534c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1954fcf5ef2aSThomas Huth /* addi */ 1955fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 1956fcf5ef2aSThomas Huth { 1957fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1958fcf5ef2aSThomas Huth 1959fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1960fcf5ef2aSThomas Huth /* li case */ 1961fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 1962fcf5ef2aSThomas Huth } else { 1963fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1964fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 1965fcf5ef2aSThomas Huth } 1966fcf5ef2aSThomas Huth } 1967fcf5ef2aSThomas Huth /* addic addic.*/ 1968fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1969fcf5ef2aSThomas Huth { 1970fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1971fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 19724c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1973fcf5ef2aSThomas Huth tcg_temp_free(c); 1974fcf5ef2aSThomas Huth } 1975fcf5ef2aSThomas Huth 1976fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1977fcf5ef2aSThomas Huth { 1978fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1979fcf5ef2aSThomas Huth } 1980fcf5ef2aSThomas Huth 1981fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1982fcf5ef2aSThomas Huth { 1983fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1984fcf5ef2aSThomas Huth } 1985fcf5ef2aSThomas Huth 1986fcf5ef2aSThomas Huth /* addis */ 1987fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 1988fcf5ef2aSThomas Huth { 1989fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 1990fcf5ef2aSThomas Huth 1991fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1992fcf5ef2aSThomas Huth /* lis case */ 1993fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 1994fcf5ef2aSThomas Huth } else { 1995fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1996fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 1997fcf5ef2aSThomas Huth } 1998fcf5ef2aSThomas Huth } 1999fcf5ef2aSThomas Huth 2000fcf5ef2aSThomas Huth /* addpcis */ 2001fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 2002fcf5ef2aSThomas Huth { 2003fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 2004fcf5ef2aSThomas Huth 2005b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 2006fcf5ef2aSThomas Huth } 2007fcf5ef2aSThomas Huth 2008fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 2009fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2010fcf5ef2aSThomas Huth { 2011fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2012fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2013fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2014fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2015fcf5ef2aSThomas Huth 2016fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2017fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2018fcf5ef2aSThomas Huth if (sign) { 2019fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2020fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2021fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2022fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2023fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2024fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2025fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2026fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 2027fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2028fcf5ef2aSThomas Huth } else { 2029fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 2030fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2031fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2032fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 2033fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2034fcf5ef2aSThomas Huth } 2035fcf5ef2aSThomas Huth if (compute_ov) { 2036fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 2037c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2038c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 2039c44027ffSNikunj A Dadhania } 2040fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2041fcf5ef2aSThomas Huth } 2042fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2043fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2044fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2045fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2046fcf5ef2aSThomas Huth 2047efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2048fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2049fcf5ef2aSThomas Huth } 2050efe843d8SDavid Gibson } 2051fcf5ef2aSThomas Huth /* Div functions */ 2052fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 2053fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2054fcf5ef2aSThomas Huth { \ 2055fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2056fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2057fcf5ef2aSThomas Huth sign, compute_ov); \ 2058fcf5ef2aSThomas Huth } 2059fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 2060fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 2061fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 2062fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 2063fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 2064fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 2065fcf5ef2aSThomas Huth 2066fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 2067fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 2068fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 2069fcf5ef2aSThomas Huth { \ 2070fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 2071fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 2072fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 2073fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 2074fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 2075fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 2076fcf5ef2aSThomas Huth } \ 2077fcf5ef2aSThomas Huth } 2078fcf5ef2aSThomas Huth 2079fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 2080fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 2081fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 2082fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 2083fcf5ef2aSThomas Huth 2084fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2085fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 2086fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 2087fcf5ef2aSThomas Huth { 2088fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2089fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2090fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2091fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2092fcf5ef2aSThomas Huth 2093fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2094fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2095fcf5ef2aSThomas Huth if (sign) { 2096fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2097fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2098fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2099fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2100fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2101fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2102fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2103fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 2104fcf5ef2aSThomas Huth } else { 2105fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 2106fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2107fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2108fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 2109fcf5ef2aSThomas Huth } 2110fcf5ef2aSThomas Huth if (compute_ov) { 2111fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 2112c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 2113c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 2114c44027ffSNikunj A Dadhania } 2115fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2116fcf5ef2aSThomas Huth } 2117fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2118fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2119fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2120fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2121fcf5ef2aSThomas Huth 2122efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2123fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 2124fcf5ef2aSThomas Huth } 2125efe843d8SDavid Gibson } 2126fcf5ef2aSThomas Huth 2127fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 2128fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2129fcf5ef2aSThomas Huth { \ 2130fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2131fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2132fcf5ef2aSThomas Huth sign, compute_ov); \ 2133fcf5ef2aSThomas Huth } 2134c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 2135fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 2136fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 2137c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 2138fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 2139fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 2140fcf5ef2aSThomas Huth 2141fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 2142fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 2143fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 2144fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 2145fcf5ef2aSThomas Huth #endif 2146fcf5ef2aSThomas Huth 2147fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 2148fcf5ef2aSThomas Huth TCGv arg2, int sign) 2149fcf5ef2aSThomas Huth { 2150fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2151fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2152fcf5ef2aSThomas Huth 2153fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 2154fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 2155fcf5ef2aSThomas Huth if (sign) { 2156fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 2157fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 2158fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 2159fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 2160fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 2161fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 2162fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 2163fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 2164fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 2165fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 2166fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 2167fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2168fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2169fcf5ef2aSThomas Huth } else { 2170fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 2171fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 2172fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 2173fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 2174fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 2175fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2176fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2177fcf5ef2aSThomas Huth } 2178fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2179fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2180fcf5ef2aSThomas Huth } 2181fcf5ef2aSThomas Huth 2182fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 2183fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2184fcf5ef2aSThomas Huth { \ 2185fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 2186fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2187fcf5ef2aSThomas Huth sign); \ 2188fcf5ef2aSThomas Huth } 2189fcf5ef2aSThomas Huth 2190fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 2191fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 2192fcf5ef2aSThomas Huth 2193fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2194fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 2195fcf5ef2aSThomas Huth TCGv arg2, int sign) 2196fcf5ef2aSThomas Huth { 2197fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2198fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2199fcf5ef2aSThomas Huth 2200fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 2201fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 2202fcf5ef2aSThomas Huth if (sign) { 2203fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 2204fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 2205fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 2206fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 2207fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 2208fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 2209fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 2210fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 2211fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 2212fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 2213fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2214fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2215fcf5ef2aSThomas Huth } else { 2216fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 2217fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 2218fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 2219fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 2220fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 2221fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 2222fcf5ef2aSThomas Huth } 2223fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2224fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2225fcf5ef2aSThomas Huth } 2226fcf5ef2aSThomas Huth 2227fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 2228fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2229fcf5ef2aSThomas Huth { \ 2230fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 2231fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2232fcf5ef2aSThomas Huth sign); \ 2233fcf5ef2aSThomas Huth } 2234fcf5ef2aSThomas Huth 2235fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 2236fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 2237fcf5ef2aSThomas Huth #endif 2238fcf5ef2aSThomas Huth 2239fcf5ef2aSThomas Huth /* mulhw mulhw. */ 2240fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 2241fcf5ef2aSThomas Huth { 2242fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2243fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2244fcf5ef2aSThomas Huth 2245fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2246fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2247fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2248fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2249fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2250fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2251efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2252fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2253fcf5ef2aSThomas Huth } 2254efe843d8SDavid Gibson } 2255fcf5ef2aSThomas Huth 2256fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 2257fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 2258fcf5ef2aSThomas Huth { 2259fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2260fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2261fcf5ef2aSThomas Huth 2262fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2263fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2264fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2265fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2266fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2267fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2268efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2269fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2270fcf5ef2aSThomas Huth } 2271efe843d8SDavid Gibson } 2272fcf5ef2aSThomas Huth 2273fcf5ef2aSThomas Huth /* mullw mullw. */ 2274fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2275fcf5ef2aSThomas Huth { 2276fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2277fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2278fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2279fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2280fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2281fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2282fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2283fcf5ef2aSThomas Huth tcg_temp_free(t0); 2284fcf5ef2aSThomas Huth tcg_temp_free(t1); 2285fcf5ef2aSThomas Huth #else 2286fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2287fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2288fcf5ef2aSThomas Huth #endif 2289efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2290fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2291fcf5ef2aSThomas Huth } 2292efe843d8SDavid Gibson } 2293fcf5ef2aSThomas Huth 2294fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2295fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2296fcf5ef2aSThomas Huth { 2297fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2298fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2299fcf5ef2aSThomas Huth 2300fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2301fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2302fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2303fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2304fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2305fcf5ef2aSThomas Huth #else 2306fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2307fcf5ef2aSThomas Huth #endif 2308fcf5ef2aSThomas Huth 2309fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2310fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2311fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 231261aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 231361aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 231461aa9a69SNikunj A Dadhania } 2315fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2316fcf5ef2aSThomas Huth 2317fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2318fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2319efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2320fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2321fcf5ef2aSThomas Huth } 2322efe843d8SDavid Gibson } 2323fcf5ef2aSThomas Huth 2324fcf5ef2aSThomas Huth /* mulli */ 2325fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2326fcf5ef2aSThomas Huth { 2327fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2328fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2329fcf5ef2aSThomas Huth } 2330fcf5ef2aSThomas Huth 2331fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2332fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2333fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2334fcf5ef2aSThomas Huth { 2335fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2336fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2337fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2338fcf5ef2aSThomas Huth tcg_temp_free(lo); 2339fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2340fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2341fcf5ef2aSThomas Huth } 2342fcf5ef2aSThomas Huth } 2343fcf5ef2aSThomas Huth 2344fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2345fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2346fcf5ef2aSThomas Huth { 2347fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2348fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2349fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2350fcf5ef2aSThomas Huth tcg_temp_free(lo); 2351fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2352fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2353fcf5ef2aSThomas Huth } 2354fcf5ef2aSThomas Huth } 2355fcf5ef2aSThomas Huth 2356fcf5ef2aSThomas Huth /* mulld mulld. */ 2357fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2358fcf5ef2aSThomas Huth { 2359fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2360fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2361efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2362fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2363fcf5ef2aSThomas Huth } 2364efe843d8SDavid Gibson } 2365fcf5ef2aSThomas Huth 2366fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2367fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2368fcf5ef2aSThomas Huth { 2369fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2370fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2371fcf5ef2aSThomas Huth 2372fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2373fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2374fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2375fcf5ef2aSThomas Huth 2376fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2377fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 237861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 237961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 238061aa9a69SNikunj A Dadhania } 2381fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2382fcf5ef2aSThomas Huth 2383fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2384fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2385fcf5ef2aSThomas Huth 2386fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2387fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2388fcf5ef2aSThomas Huth } 2389fcf5ef2aSThomas Huth } 2390fcf5ef2aSThomas Huth #endif 2391fcf5ef2aSThomas Huth 2392fcf5ef2aSThomas Huth /* Common subf function */ 2393fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2394fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2395fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2396fcf5ef2aSThomas Huth { 2397fcf5ef2aSThomas Huth TCGv t0 = ret; 2398fcf5ef2aSThomas Huth 2399fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2400fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2401fcf5ef2aSThomas Huth } 2402fcf5ef2aSThomas Huth 2403fcf5ef2aSThomas Huth if (compute_ca) { 2404fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2405fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2406efe843d8SDavid Gibson /* 2407efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2408efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2409efe843d8SDavid Gibson * produce the carry into bit 32. 2410efe843d8SDavid Gibson */ 2411fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2412fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2413fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2414fcf5ef2aSThomas Huth if (add_ca) { 2415fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2416fcf5ef2aSThomas Huth } else { 2417fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2418fcf5ef2aSThomas Huth } 2419fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2420fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2421fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2422fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2423fcf5ef2aSThomas Huth tcg_temp_free(t1); 2424e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 242533903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 242633903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 242733903d0aSNikunj A Dadhania } 2428fcf5ef2aSThomas Huth } else if (add_ca) { 2429fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2430fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2431fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2432fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2433fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 24344c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2435fcf5ef2aSThomas Huth tcg_temp_free(zero); 2436fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2437fcf5ef2aSThomas Huth } else { 2438fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2439fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 24404c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2441fcf5ef2aSThomas Huth } 2442fcf5ef2aSThomas Huth } else if (add_ca) { 2443efe843d8SDavid Gibson /* 2444efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2445efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2446efe843d8SDavid Gibson */ 2447fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2448fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2449fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2450fcf5ef2aSThomas Huth } else { 2451fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2452fcf5ef2aSThomas Huth } 2453fcf5ef2aSThomas Huth 2454fcf5ef2aSThomas Huth if (compute_ov) { 2455fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2456fcf5ef2aSThomas Huth } 2457fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2458fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2459fcf5ef2aSThomas Huth } 2460fcf5ef2aSThomas Huth 246111f4e8f8SRichard Henderson if (t0 != ret) { 2462fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2463fcf5ef2aSThomas Huth tcg_temp_free(t0); 2464fcf5ef2aSThomas Huth } 2465fcf5ef2aSThomas Huth } 2466fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2467fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2468fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2469fcf5ef2aSThomas Huth { \ 2470fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2471fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2472fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2473fcf5ef2aSThomas Huth } 2474fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2475fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2476fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2477fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2478fcf5ef2aSThomas Huth { \ 2479fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2480fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2481fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2482fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2483fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2484fcf5ef2aSThomas Huth } 2485fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2486fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2487fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2488fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2489fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2490fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2491fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2492fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2493fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2494fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2495fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2496fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2497fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2498fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2499fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2500fcf5ef2aSThomas Huth 2501fcf5ef2aSThomas Huth /* subfic */ 2502fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2503fcf5ef2aSThomas Huth { 2504fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2505fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2506fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2507fcf5ef2aSThomas Huth tcg_temp_free(c); 2508fcf5ef2aSThomas Huth } 2509fcf5ef2aSThomas Huth 2510fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2511fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2512fcf5ef2aSThomas Huth { 2513fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2514fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2515fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2516fcf5ef2aSThomas Huth tcg_temp_free(zero); 2517fcf5ef2aSThomas Huth } 2518fcf5ef2aSThomas Huth 2519fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2520fcf5ef2aSThomas Huth { 25211480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 25221480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 25231480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 25241480d71cSNikunj A Dadhania } 2525fcf5ef2aSThomas Huth } 2526fcf5ef2aSThomas Huth 2527fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2528fcf5ef2aSThomas Huth { 2529fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2530fcf5ef2aSThomas Huth } 2531fcf5ef2aSThomas Huth 2532fcf5ef2aSThomas Huth /*** Integer logical ***/ 2533fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2534fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2535fcf5ef2aSThomas Huth { \ 2536fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2537fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2538fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2539fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2540fcf5ef2aSThomas Huth } 2541fcf5ef2aSThomas Huth 2542fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2543fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2544fcf5ef2aSThomas Huth { \ 2545fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2546fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2547fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2548fcf5ef2aSThomas Huth } 2549fcf5ef2aSThomas Huth 2550fcf5ef2aSThomas Huth /* and & and. */ 2551fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2552fcf5ef2aSThomas Huth /* andc & andc. */ 2553fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2554fcf5ef2aSThomas Huth 2555fcf5ef2aSThomas Huth /* andi. */ 2556fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2557fcf5ef2aSThomas Huth { 2558efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2559efe843d8SDavid Gibson UIMM(ctx->opcode)); 2560fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2561fcf5ef2aSThomas Huth } 2562fcf5ef2aSThomas Huth 2563fcf5ef2aSThomas Huth /* andis. */ 2564fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2565fcf5ef2aSThomas Huth { 2566efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2567efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2568fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2569fcf5ef2aSThomas Huth } 2570fcf5ef2aSThomas Huth 2571fcf5ef2aSThomas Huth /* cntlzw */ 2572fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2573fcf5ef2aSThomas Huth { 25749b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 25759b8514e5SRichard Henderson 25769b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 25779b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 25789b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 25799b8514e5SRichard Henderson tcg_temp_free_i32(t); 25809b8514e5SRichard Henderson 2581efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2582fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2583fcf5ef2aSThomas Huth } 2584efe843d8SDavid Gibson } 2585fcf5ef2aSThomas Huth 2586fcf5ef2aSThomas Huth /* cnttzw */ 2587fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2588fcf5ef2aSThomas Huth { 25899b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 25909b8514e5SRichard Henderson 25919b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 25929b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 25939b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 25949b8514e5SRichard Henderson tcg_temp_free_i32(t); 25959b8514e5SRichard Henderson 2596fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2597fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2598fcf5ef2aSThomas Huth } 2599fcf5ef2aSThomas Huth } 2600fcf5ef2aSThomas Huth 2601fcf5ef2aSThomas Huth /* eqv & eqv. */ 2602fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2603fcf5ef2aSThomas Huth /* extsb & extsb. */ 2604fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2605fcf5ef2aSThomas Huth /* extsh & extsh. */ 2606fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2607fcf5ef2aSThomas Huth /* nand & nand. */ 2608fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2609fcf5ef2aSThomas Huth /* nor & nor. */ 2610fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2611fcf5ef2aSThomas Huth 2612fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2613fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2614fcf5ef2aSThomas Huth { 2615fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2616fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2617fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2618fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2619fcf5ef2aSThomas Huth 2620fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2621b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2622fcf5ef2aSThomas Huth } 2623fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2624fcf5ef2aSThomas Huth 2625fcf5ef2aSThomas Huth /* or & or. */ 2626fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2627fcf5ef2aSThomas Huth { 2628fcf5ef2aSThomas Huth int rs, ra, rb; 2629fcf5ef2aSThomas Huth 2630fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2631fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2632fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2633fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2634fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2635efe843d8SDavid Gibson if (rs != rb) { 2636fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2637efe843d8SDavid Gibson } else { 2638fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2639efe843d8SDavid Gibson } 2640efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2641fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2642efe843d8SDavid Gibson } 2643fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2644fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2645fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2646fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2647fcf5ef2aSThomas Huth int prio = 0; 2648fcf5ef2aSThomas Huth 2649fcf5ef2aSThomas Huth switch (rs) { 2650fcf5ef2aSThomas Huth case 1: 2651fcf5ef2aSThomas Huth /* Set process priority to low */ 2652fcf5ef2aSThomas Huth prio = 2; 2653fcf5ef2aSThomas Huth break; 2654fcf5ef2aSThomas Huth case 6: 2655fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2656fcf5ef2aSThomas Huth prio = 3; 2657fcf5ef2aSThomas Huth break; 2658fcf5ef2aSThomas Huth case 2: 2659fcf5ef2aSThomas Huth /* Set process priority to normal */ 2660fcf5ef2aSThomas Huth prio = 4; 2661fcf5ef2aSThomas Huth break; 2662fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2663fcf5ef2aSThomas Huth case 31: 2664fcf5ef2aSThomas Huth if (!ctx->pr) { 2665fcf5ef2aSThomas Huth /* Set process priority to very low */ 2666fcf5ef2aSThomas Huth prio = 1; 2667fcf5ef2aSThomas Huth } 2668fcf5ef2aSThomas Huth break; 2669fcf5ef2aSThomas Huth case 5: 2670fcf5ef2aSThomas Huth if (!ctx->pr) { 2671fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2672fcf5ef2aSThomas Huth prio = 5; 2673fcf5ef2aSThomas Huth } 2674fcf5ef2aSThomas Huth break; 2675fcf5ef2aSThomas Huth case 3: 2676fcf5ef2aSThomas Huth if (!ctx->pr) { 2677fcf5ef2aSThomas Huth /* Set process priority to high */ 2678fcf5ef2aSThomas Huth prio = 6; 2679fcf5ef2aSThomas Huth } 2680fcf5ef2aSThomas Huth break; 2681fcf5ef2aSThomas Huth case 7: 2682fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2683fcf5ef2aSThomas Huth /* Set process priority to very high */ 2684fcf5ef2aSThomas Huth prio = 7; 2685fcf5ef2aSThomas Huth } 2686fcf5ef2aSThomas Huth break; 2687fcf5ef2aSThomas Huth #endif 2688fcf5ef2aSThomas Huth default: 2689fcf5ef2aSThomas Huth break; 2690fcf5ef2aSThomas Huth } 2691fcf5ef2aSThomas Huth if (prio) { 2692fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2693fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2694fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2695fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2696fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2697fcf5ef2aSThomas Huth tcg_temp_free(t0); 2698fcf5ef2aSThomas Huth } 2699fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2700efe843d8SDavid Gibson /* 2701efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2702efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2703efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2704efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2705fcf5ef2aSThomas Huth */ 2706fcf5ef2aSThomas Huth gen_pause(ctx); 2707fcf5ef2aSThomas Huth #endif 2708fcf5ef2aSThomas Huth #endif 2709fcf5ef2aSThomas Huth } 2710fcf5ef2aSThomas Huth } 2711fcf5ef2aSThomas Huth /* orc & orc. */ 2712fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2713fcf5ef2aSThomas Huth 2714fcf5ef2aSThomas Huth /* xor & xor. */ 2715fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2716fcf5ef2aSThomas Huth { 2717fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2718efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2719efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2720efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2721efe843d8SDavid Gibson } else { 2722fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2723efe843d8SDavid Gibson } 2724efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2725fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2726fcf5ef2aSThomas Huth } 2727efe843d8SDavid Gibson } 2728fcf5ef2aSThomas Huth 2729fcf5ef2aSThomas Huth /* ori */ 2730fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2731fcf5ef2aSThomas Huth { 2732fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2733fcf5ef2aSThomas Huth 2734fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2735fcf5ef2aSThomas Huth return; 2736fcf5ef2aSThomas Huth } 2737fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2738fcf5ef2aSThomas Huth } 2739fcf5ef2aSThomas Huth 2740fcf5ef2aSThomas Huth /* oris */ 2741fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2742fcf5ef2aSThomas Huth { 2743fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2744fcf5ef2aSThomas Huth 2745fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2746fcf5ef2aSThomas Huth /* NOP */ 2747fcf5ef2aSThomas Huth return; 2748fcf5ef2aSThomas Huth } 2749efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2750efe843d8SDavid Gibson uimm << 16); 2751fcf5ef2aSThomas Huth } 2752fcf5ef2aSThomas Huth 2753fcf5ef2aSThomas Huth /* xori */ 2754fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2755fcf5ef2aSThomas Huth { 2756fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2757fcf5ef2aSThomas Huth 2758fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2759fcf5ef2aSThomas Huth /* NOP */ 2760fcf5ef2aSThomas Huth return; 2761fcf5ef2aSThomas Huth } 2762fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2763fcf5ef2aSThomas Huth } 2764fcf5ef2aSThomas Huth 2765fcf5ef2aSThomas Huth /* xoris */ 2766fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2767fcf5ef2aSThomas Huth { 2768fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2769fcf5ef2aSThomas Huth 2770fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2771fcf5ef2aSThomas Huth /* NOP */ 2772fcf5ef2aSThomas Huth return; 2773fcf5ef2aSThomas Huth } 2774efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2775efe843d8SDavid Gibson uimm << 16); 2776fcf5ef2aSThomas Huth } 2777fcf5ef2aSThomas Huth 2778fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2779fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2780fcf5ef2aSThomas Huth { 2781fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2782fcf5ef2aSThomas Huth } 2783fcf5ef2aSThomas Huth 2784fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2785fcf5ef2aSThomas Huth { 278679770002SRichard Henderson #if defined(TARGET_PPC64) 2787fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 278879770002SRichard Henderson #else 278979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 279079770002SRichard Henderson #endif 2791fcf5ef2aSThomas Huth } 2792fcf5ef2aSThomas Huth 2793fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2794fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2795fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2796fcf5ef2aSThomas Huth { 279779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2798fcf5ef2aSThomas Huth } 2799fcf5ef2aSThomas Huth #endif 2800fcf5ef2aSThomas Huth 2801fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2802fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2803fcf5ef2aSThomas Huth { 2804fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2805fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2806fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2807fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2808fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2809fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2810fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2811fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2812fcf5ef2aSThomas Huth tcg_temp_free(t0); 2813fcf5ef2aSThomas Huth } 2814fcf5ef2aSThomas Huth 2815fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2816fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2817fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2818fcf5ef2aSThomas Huth { 2819fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2820fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2821fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2822fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2823fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2824fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2825fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2826fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2827fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2828fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2829fcf5ef2aSThomas Huth tcg_temp_free(t0); 2830fcf5ef2aSThomas Huth } 2831fcf5ef2aSThomas Huth #endif 2832fcf5ef2aSThomas Huth 2833fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2834fcf5ef2aSThomas Huth /* bpermd */ 2835fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2836fcf5ef2aSThomas Huth { 2837fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2838fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2839fcf5ef2aSThomas Huth } 2840fcf5ef2aSThomas Huth #endif 2841fcf5ef2aSThomas Huth 2842fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2843fcf5ef2aSThomas Huth /* extsw & extsw. */ 2844fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2845fcf5ef2aSThomas Huth 2846fcf5ef2aSThomas Huth /* cntlzd */ 2847fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2848fcf5ef2aSThomas Huth { 28499b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2850efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2851fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2852fcf5ef2aSThomas Huth } 2853efe843d8SDavid Gibson } 2854fcf5ef2aSThomas Huth 2855fcf5ef2aSThomas Huth /* cnttzd */ 2856fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2857fcf5ef2aSThomas Huth { 28589b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2859fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2860fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2861fcf5ef2aSThomas Huth } 2862fcf5ef2aSThomas Huth } 2863fcf5ef2aSThomas Huth 2864fcf5ef2aSThomas Huth /* darn */ 2865fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2866fcf5ef2aSThomas Huth { 2867fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2868fcf5ef2aSThomas Huth 28697e4357f6SRichard Henderson if (l > 2) { 28707e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 28717e4357f6SRichard Henderson } else { 28727e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28737e4357f6SRichard Henderson gen_io_start(); 28747e4357f6SRichard Henderson } 2875fcf5ef2aSThomas Huth if (l == 0) { 2876fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 28777e4357f6SRichard Henderson } else { 2878fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2879fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 28807e4357f6SRichard Henderson } 28817e4357f6SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 28827e4357f6SRichard Henderson gen_stop_exception(ctx); 28837e4357f6SRichard Henderson } 2884fcf5ef2aSThomas Huth } 2885fcf5ef2aSThomas Huth } 2886fcf5ef2aSThomas Huth #endif 2887fcf5ef2aSThomas Huth 2888fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2889fcf5ef2aSThomas Huth 2890fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2891fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2892fcf5ef2aSThomas Huth { 2893fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2894fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2895fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2896fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2897fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2898fcf5ef2aSThomas Huth 2899fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2900fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2901fcf5ef2aSThomas Huth } else { 2902fcf5ef2aSThomas Huth target_ulong mask; 2903c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2904fcf5ef2aSThomas Huth TCGv t1; 2905fcf5ef2aSThomas Huth 2906fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2907fcf5ef2aSThomas Huth mb += 32; 2908fcf5ef2aSThomas Huth me += 32; 2909fcf5ef2aSThomas Huth #endif 2910fcf5ef2aSThomas Huth mask = MASK(mb, me); 2911fcf5ef2aSThomas Huth 2912c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2913c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2914c4f6a4a3SDaniele Buono mask_in_32b = false; 2915c4f6a4a3SDaniele Buono } 2916c4f6a4a3SDaniele Buono #endif 2917fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2918c4f6a4a3SDaniele Buono if (mask_in_32b) { 2919fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2920fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2921fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2922fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2923fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2924fcf5ef2aSThomas Huth } else { 2925fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2926fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2927fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2928fcf5ef2aSThomas Huth #else 2929fcf5ef2aSThomas Huth g_assert_not_reached(); 2930fcf5ef2aSThomas Huth #endif 2931fcf5ef2aSThomas Huth } 2932fcf5ef2aSThomas Huth 2933fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2934fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2935fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2936fcf5ef2aSThomas Huth tcg_temp_free(t1); 2937fcf5ef2aSThomas Huth } 2938fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2939fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2940fcf5ef2aSThomas Huth } 2941fcf5ef2aSThomas Huth } 2942fcf5ef2aSThomas Huth 2943fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2944fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2945fcf5ef2aSThomas Huth { 2946fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2947fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 29487b4d326fSRichard Henderson int sh = SH(ctx->opcode); 29497b4d326fSRichard Henderson int mb = MB(ctx->opcode); 29507b4d326fSRichard Henderson int me = ME(ctx->opcode); 29517b4d326fSRichard Henderson int len = me - mb + 1; 29527b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2953fcf5ef2aSThomas Huth 29547b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 29557b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 29567b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 29577b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2958fcf5ef2aSThomas Huth } else { 2959fcf5ef2aSThomas Huth target_ulong mask; 2960c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2961fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2962fcf5ef2aSThomas Huth mb += 32; 2963fcf5ef2aSThomas Huth me += 32; 2964fcf5ef2aSThomas Huth #endif 2965fcf5ef2aSThomas Huth mask = MASK(mb, me); 2966c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2967c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2968c4f6a4a3SDaniele Buono mask_in_32b = false; 2969c4f6a4a3SDaniele Buono } 2970c4f6a4a3SDaniele Buono #endif 2971c4f6a4a3SDaniele Buono if (mask_in_32b) { 29727b4d326fSRichard Henderson if (sh == 0) { 29737b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 297494f040aaSVitaly Chikunov } else { 2975fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2976fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2977fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2978fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2979fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2980fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 298194f040aaSVitaly Chikunov } 2982fcf5ef2aSThomas Huth } else { 2983fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2984fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2985fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2986fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2987fcf5ef2aSThomas Huth #else 2988fcf5ef2aSThomas Huth g_assert_not_reached(); 2989fcf5ef2aSThomas Huth #endif 2990fcf5ef2aSThomas Huth } 2991fcf5ef2aSThomas Huth } 2992fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2993fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2994fcf5ef2aSThomas Huth } 2995fcf5ef2aSThomas Huth } 2996fcf5ef2aSThomas Huth 2997fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2998fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2999fcf5ef2aSThomas Huth { 3000fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3001fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3002fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3003fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 3004fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 3005fcf5ef2aSThomas Huth target_ulong mask; 3006c4f6a4a3SDaniele Buono bool mask_in_32b = true; 3007fcf5ef2aSThomas Huth 3008fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3009fcf5ef2aSThomas Huth mb += 32; 3010fcf5ef2aSThomas Huth me += 32; 3011fcf5ef2aSThomas Huth #endif 3012fcf5ef2aSThomas Huth mask = MASK(mb, me); 3013fcf5ef2aSThomas Huth 3014c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 3015c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 3016c4f6a4a3SDaniele Buono mask_in_32b = false; 3017c4f6a4a3SDaniele Buono } 3018c4f6a4a3SDaniele Buono #endif 3019c4f6a4a3SDaniele Buono if (mask_in_32b) { 3020fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3021fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3022fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 3023fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 3024fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 3025fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 3026fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 3027fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3028fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3029fcf5ef2aSThomas Huth } else { 3030fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3031fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 3032fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 3033fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 3034fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 3035fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 3036fcf5ef2aSThomas Huth #else 3037fcf5ef2aSThomas Huth g_assert_not_reached(); 3038fcf5ef2aSThomas Huth #endif 3039fcf5ef2aSThomas Huth } 3040fcf5ef2aSThomas Huth 3041fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 3042fcf5ef2aSThomas Huth 3043fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3044fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3045fcf5ef2aSThomas Huth } 3046fcf5ef2aSThomas Huth } 3047fcf5ef2aSThomas Huth 3048fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3049fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 3050fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3051fcf5ef2aSThomas Huth { \ 3052fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 3053fcf5ef2aSThomas Huth } \ 3054fcf5ef2aSThomas Huth \ 3055fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3056fcf5ef2aSThomas Huth { \ 3057fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 3058fcf5ef2aSThomas Huth } 3059fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 3060fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 3061fcf5ef2aSThomas Huth { \ 3062fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 3063fcf5ef2aSThomas Huth } \ 3064fcf5ef2aSThomas Huth \ 3065fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 3066fcf5ef2aSThomas Huth { \ 3067fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 3068fcf5ef2aSThomas Huth } \ 3069fcf5ef2aSThomas Huth \ 3070fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 3071fcf5ef2aSThomas Huth { \ 3072fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 3073fcf5ef2aSThomas Huth } \ 3074fcf5ef2aSThomas Huth \ 3075fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 3076fcf5ef2aSThomas Huth { \ 3077fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 3078fcf5ef2aSThomas Huth } 3079fcf5ef2aSThomas Huth 3080fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 3081fcf5ef2aSThomas Huth { 3082fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3083fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 30847b4d326fSRichard Henderson int len = me - mb + 1; 30857b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 3086fcf5ef2aSThomas Huth 30877b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 30887b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 30897b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 30907b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 3091fcf5ef2aSThomas Huth } else { 3092fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 3093fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3094fcf5ef2aSThomas Huth } 3095fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3096fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3097fcf5ef2aSThomas Huth } 3098fcf5ef2aSThomas Huth } 3099fcf5ef2aSThomas Huth 3100fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 3101fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 3102fcf5ef2aSThomas Huth { 3103fcf5ef2aSThomas Huth uint32_t sh, mb; 3104fcf5ef2aSThomas Huth 3105fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3106fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3107fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 3108fcf5ef2aSThomas Huth } 3109fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 3110fcf5ef2aSThomas Huth 3111fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 3112fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 3113fcf5ef2aSThomas Huth { 3114fcf5ef2aSThomas Huth uint32_t sh, me; 3115fcf5ef2aSThomas Huth 3116fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3117fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3118fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 3119fcf5ef2aSThomas Huth } 3120fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 3121fcf5ef2aSThomas Huth 3122fcf5ef2aSThomas Huth /* rldic - rldic. */ 3123fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 3124fcf5ef2aSThomas Huth { 3125fcf5ef2aSThomas Huth uint32_t sh, mb; 3126fcf5ef2aSThomas Huth 3127fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 3128fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3129fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 3130fcf5ef2aSThomas Huth } 3131fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 3132fcf5ef2aSThomas Huth 3133fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 3134fcf5ef2aSThomas Huth { 3135fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3136fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3137fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 3138fcf5ef2aSThomas Huth TCGv t0; 3139fcf5ef2aSThomas Huth 3140fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3141fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 3142fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 3143fcf5ef2aSThomas Huth tcg_temp_free(t0); 3144fcf5ef2aSThomas Huth 3145fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 3146fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3147fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3148fcf5ef2aSThomas Huth } 3149fcf5ef2aSThomas Huth } 3150fcf5ef2aSThomas Huth 3151fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 3152fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 3153fcf5ef2aSThomas Huth { 3154fcf5ef2aSThomas Huth uint32_t mb; 3155fcf5ef2aSThomas Huth 3156fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 3157fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 3158fcf5ef2aSThomas Huth } 3159fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 3160fcf5ef2aSThomas Huth 3161fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 3162fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 3163fcf5ef2aSThomas Huth { 3164fcf5ef2aSThomas Huth uint32_t me; 3165fcf5ef2aSThomas Huth 3166fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 3167fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 3168fcf5ef2aSThomas Huth } 3169fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 3170fcf5ef2aSThomas Huth 3171fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 3172fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 3173fcf5ef2aSThomas Huth { 3174fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 3175fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 3176fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 3177fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 3178fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 3179fcf5ef2aSThomas Huth 3180fcf5ef2aSThomas Huth if (mb <= me) { 3181fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 3182fcf5ef2aSThomas Huth } else { 3183fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 3184fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3185fcf5ef2aSThomas Huth 3186fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 3187fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 3188fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 3189fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 3190fcf5ef2aSThomas Huth tcg_temp_free(t1); 3191fcf5ef2aSThomas Huth } 3192fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3193fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 3194fcf5ef2aSThomas Huth } 3195fcf5ef2aSThomas Huth } 3196fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 3197fcf5ef2aSThomas Huth #endif 3198fcf5ef2aSThomas Huth 3199fcf5ef2aSThomas Huth /*** Integer shift ***/ 3200fcf5ef2aSThomas Huth 3201fcf5ef2aSThomas Huth /* slw & slw. */ 3202fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 3203fcf5ef2aSThomas Huth { 3204fcf5ef2aSThomas Huth TCGv t0, t1; 3205fcf5ef2aSThomas Huth 3206fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3207fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3208fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3209fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3210fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3211fcf5ef2aSThomas Huth #else 3212fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3213fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3214fcf5ef2aSThomas Huth #endif 3215fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3216fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3217fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3218fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3219fcf5ef2aSThomas Huth tcg_temp_free(t1); 3220fcf5ef2aSThomas Huth tcg_temp_free(t0); 3221fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 3222efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3223fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3224fcf5ef2aSThomas Huth } 3225efe843d8SDavid Gibson } 3226fcf5ef2aSThomas Huth 3227fcf5ef2aSThomas Huth /* sraw & sraw. */ 3228fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 3229fcf5ef2aSThomas Huth { 3230fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 3231fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3232efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3233fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3234fcf5ef2aSThomas Huth } 3235efe843d8SDavid Gibson } 3236fcf5ef2aSThomas Huth 3237fcf5ef2aSThomas Huth /* srawi & srawi. */ 3238fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 3239fcf5ef2aSThomas Huth { 3240fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 3241fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3242fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3243fcf5ef2aSThomas Huth if (sh == 0) { 3244fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3245fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3246af1c259fSSandipan Das if (is_isa300(ctx)) { 3247af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3248af1c259fSSandipan Das } 3249fcf5ef2aSThomas Huth } else { 3250fcf5ef2aSThomas Huth TCGv t0; 3251fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3252fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 3253fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3254fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 3255fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3256fcf5ef2aSThomas Huth tcg_temp_free(t0); 3257fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3258af1c259fSSandipan Das if (is_isa300(ctx)) { 3259af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3260af1c259fSSandipan Das } 3261fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 3262fcf5ef2aSThomas Huth } 3263fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3264fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3265fcf5ef2aSThomas Huth } 3266fcf5ef2aSThomas Huth } 3267fcf5ef2aSThomas Huth 3268fcf5ef2aSThomas Huth /* srw & srw. */ 3269fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3270fcf5ef2aSThomas Huth { 3271fcf5ef2aSThomas Huth TCGv t0, t1; 3272fcf5ef2aSThomas Huth 3273fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3274fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3275fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3276fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3277fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3278fcf5ef2aSThomas Huth #else 3279fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3280fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3281fcf5ef2aSThomas Huth #endif 3282fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3283fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3284fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3285fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3286fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3287fcf5ef2aSThomas Huth tcg_temp_free(t1); 3288fcf5ef2aSThomas Huth tcg_temp_free(t0); 3289efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3290fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3291fcf5ef2aSThomas Huth } 3292efe843d8SDavid Gibson } 3293fcf5ef2aSThomas Huth 3294fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3295fcf5ef2aSThomas Huth /* sld & sld. */ 3296fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3297fcf5ef2aSThomas Huth { 3298fcf5ef2aSThomas Huth TCGv t0, t1; 3299fcf5ef2aSThomas Huth 3300fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3301fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3302fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3303fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3304fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3305fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3306fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3307fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3308fcf5ef2aSThomas Huth tcg_temp_free(t1); 3309fcf5ef2aSThomas Huth tcg_temp_free(t0); 3310efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3311fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3312fcf5ef2aSThomas Huth } 3313efe843d8SDavid Gibson } 3314fcf5ef2aSThomas Huth 3315fcf5ef2aSThomas Huth /* srad & srad. */ 3316fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3317fcf5ef2aSThomas Huth { 3318fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3319fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3320efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3321fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3322fcf5ef2aSThomas Huth } 3323efe843d8SDavid Gibson } 3324fcf5ef2aSThomas Huth /* sradi & sradi. */ 3325fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3326fcf5ef2aSThomas Huth { 3327fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3328fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3329fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3330fcf5ef2aSThomas Huth if (sh == 0) { 3331fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3332fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3333af1c259fSSandipan Das if (is_isa300(ctx)) { 3334af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3335af1c259fSSandipan Das } 3336fcf5ef2aSThomas Huth } else { 3337fcf5ef2aSThomas Huth TCGv t0; 3338fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3339fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3340fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3341fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3342fcf5ef2aSThomas Huth tcg_temp_free(t0); 3343fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3344af1c259fSSandipan Das if (is_isa300(ctx)) { 3345af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3346af1c259fSSandipan Das } 3347fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3348fcf5ef2aSThomas Huth } 3349fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3350fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3351fcf5ef2aSThomas Huth } 3352fcf5ef2aSThomas Huth } 3353fcf5ef2aSThomas Huth 3354fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3355fcf5ef2aSThomas Huth { 3356fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3357fcf5ef2aSThomas Huth } 3358fcf5ef2aSThomas Huth 3359fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3360fcf5ef2aSThomas Huth { 3361fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3362fcf5ef2aSThomas Huth } 3363fcf5ef2aSThomas Huth 3364fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3365fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3366fcf5ef2aSThomas Huth { 3367fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3368fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3369fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3370fcf5ef2aSThomas Huth 3371fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3372fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3373fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3374fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3375fcf5ef2aSThomas Huth } 3376fcf5ef2aSThomas Huth } 3377fcf5ef2aSThomas Huth 3378fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3379fcf5ef2aSThomas Huth { 3380fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3381fcf5ef2aSThomas Huth } 3382fcf5ef2aSThomas Huth 3383fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3384fcf5ef2aSThomas Huth { 3385fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3386fcf5ef2aSThomas Huth } 3387fcf5ef2aSThomas Huth 3388fcf5ef2aSThomas Huth /* srd & srd. */ 3389fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3390fcf5ef2aSThomas Huth { 3391fcf5ef2aSThomas Huth TCGv t0, t1; 3392fcf5ef2aSThomas Huth 3393fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3394fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3395fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3396fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3397fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3398fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3399fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3400fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3401fcf5ef2aSThomas Huth tcg_temp_free(t1); 3402fcf5ef2aSThomas Huth tcg_temp_free(t0); 3403efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3404fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3405fcf5ef2aSThomas Huth } 3406efe843d8SDavid Gibson } 3407fcf5ef2aSThomas Huth #endif 3408fcf5ef2aSThomas Huth 3409fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3410fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3411fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3412fcf5ef2aSThomas Huth target_long maskl) 3413fcf5ef2aSThomas Huth { 3414fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3415fcf5ef2aSThomas Huth 3416fcf5ef2aSThomas Huth simm &= ~maskl; 3417fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3418fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3419fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3420fcf5ef2aSThomas Huth } 3421fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3422fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3423fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3424fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3425fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3426fcf5ef2aSThomas Huth } 3427fcf5ef2aSThomas Huth } else { 3428fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3429fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3430fcf5ef2aSThomas Huth } else { 3431fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3432fcf5ef2aSThomas Huth } 3433fcf5ef2aSThomas Huth } 3434fcf5ef2aSThomas Huth } 3435fcf5ef2aSThomas Huth 3436fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3437fcf5ef2aSThomas Huth { 3438fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3439fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3440fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3441fcf5ef2aSThomas Huth } else { 3442fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3443fcf5ef2aSThomas Huth } 3444fcf5ef2aSThomas Huth } else { 3445fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3446fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3447fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3448fcf5ef2aSThomas Huth } 3449fcf5ef2aSThomas Huth } 3450fcf5ef2aSThomas Huth } 3451fcf5ef2aSThomas Huth 3452fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3453fcf5ef2aSThomas Huth { 3454fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3455fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3456fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3457fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3458fcf5ef2aSThomas Huth } else { 3459fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3460fcf5ef2aSThomas Huth } 3461fcf5ef2aSThomas Huth } 3462fcf5ef2aSThomas Huth 3463fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3464fcf5ef2aSThomas Huth target_long val) 3465fcf5ef2aSThomas Huth { 3466fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3467fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3468fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3469fcf5ef2aSThomas Huth } 3470fcf5ef2aSThomas Huth } 3471fcf5ef2aSThomas Huth 3472fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3473fcf5ef2aSThomas Huth { 3474fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3475fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3476fcf5ef2aSThomas Huth } 3477fcf5ef2aSThomas Huth 3478fcf5ef2aSThomas Huth /*** Integer load ***/ 3479fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3480fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3481fcf5ef2aSThomas Huth 3482fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3483fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3484fcf5ef2aSThomas Huth TCGv val, \ 3485fcf5ef2aSThomas Huth TCGv addr) \ 3486fcf5ef2aSThomas Huth { \ 3487fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3488fcf5ef2aSThomas Huth } 3489fcf5ef2aSThomas Huth 3490fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3491fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3492fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3493fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3494fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3495fcf5ef2aSThomas Huth 3496fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3497fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3498fcf5ef2aSThomas Huth 3499fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3500fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3501fcf5ef2aSThomas Huth TCGv_i64 val, \ 3502fcf5ef2aSThomas Huth TCGv addr) \ 3503fcf5ef2aSThomas Huth { \ 3504fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3505fcf5ef2aSThomas Huth } 3506fcf5ef2aSThomas Huth 3507fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3508fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3509fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3510fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3511fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3512fcf5ef2aSThomas Huth 3513fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3514fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3515fcf5ef2aSThomas Huth #endif 3516fcf5ef2aSThomas Huth 3517fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3518fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3519fcf5ef2aSThomas Huth TCGv val, \ 3520fcf5ef2aSThomas Huth TCGv addr) \ 3521fcf5ef2aSThomas Huth { \ 3522fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3523fcf5ef2aSThomas Huth } 3524fcf5ef2aSThomas Huth 3525fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3526fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3527fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3528fcf5ef2aSThomas Huth 3529fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3530fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3531fcf5ef2aSThomas Huth 3532fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3533fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3534fcf5ef2aSThomas Huth TCGv_i64 val, \ 3535fcf5ef2aSThomas Huth TCGv addr) \ 3536fcf5ef2aSThomas Huth { \ 3537fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3538fcf5ef2aSThomas Huth } 3539fcf5ef2aSThomas Huth 3540fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3541fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3542fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3543fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3544fcf5ef2aSThomas Huth 3545fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3546fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3547fcf5ef2aSThomas Huth #endif 3548fcf5ef2aSThomas Huth 3549fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 3550fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3551fcf5ef2aSThomas Huth { \ 3552fcf5ef2aSThomas Huth TCGv EA; \ 3553fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3554fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3555fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3556fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3557fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3558fcf5ef2aSThomas Huth } 3559fcf5ef2aSThomas Huth 3560fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 3561fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 3562fcf5ef2aSThomas Huth { \ 3563fcf5ef2aSThomas Huth TCGv EA; \ 3564fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3565fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3566fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3567fcf5ef2aSThomas Huth return; \ 3568fcf5ef2aSThomas Huth } \ 3569fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3570fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3571fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3572fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3573fcf5ef2aSThomas Huth else \ 3574fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3575fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3576fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3577fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3578fcf5ef2aSThomas Huth } 3579fcf5ef2aSThomas Huth 3580fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 3581fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3582fcf5ef2aSThomas Huth { \ 3583fcf5ef2aSThomas Huth TCGv EA; \ 3584fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 3585fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 3586fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3587fcf5ef2aSThomas Huth return; \ 3588fcf5ef2aSThomas Huth } \ 3589fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3590fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3591fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3592fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3593fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3594fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3595fcf5ef2aSThomas Huth } 3596fcf5ef2aSThomas Huth 3597fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3598fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3599fcf5ef2aSThomas Huth { \ 3600fcf5ef2aSThomas Huth TCGv EA; \ 3601fcf5ef2aSThomas Huth chk; \ 3602fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3603fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3604fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3605fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3606fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3607fcf5ef2aSThomas Huth } 3608fcf5ef2aSThomas Huth 3609fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3610fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3611fcf5ef2aSThomas Huth 3612fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3613fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3614fcf5ef2aSThomas Huth 3615fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 3616fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 3617fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 3618fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 3619fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 3620fcf5ef2aSThomas Huth 3621fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 3622fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 3623fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 3624fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 3625fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 3626fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 3627fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 3628fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 362950728199SRoman Kapl 363050728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 363150728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 363250728199SRoman Kapl { \ 363350728199SRoman Kapl TCGv EA; \ 363450728199SRoman Kapl CHK_SV; \ 363550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 363650728199SRoman Kapl EA = tcg_temp_new(); \ 363750728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 363850728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 363950728199SRoman Kapl tcg_temp_free(EA); \ 364050728199SRoman Kapl } 364150728199SRoman Kapl 364250728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 364350728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 364450728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 364550728199SRoman Kapl #if defined(TARGET_PPC64) 364650728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 364750728199SRoman Kapl #endif 364850728199SRoman Kapl 3649fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3650fcf5ef2aSThomas Huth /* lwaux */ 3651fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 3652fcf5ef2aSThomas Huth /* lwax */ 3653fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 3654fcf5ef2aSThomas Huth /* ldux */ 3655fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 3656fcf5ef2aSThomas Huth /* ldx */ 3657fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 3658fcf5ef2aSThomas Huth 3659fcf5ef2aSThomas Huth /* CI load/store variants */ 3660fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3661fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3662fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3663fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3664fcf5ef2aSThomas Huth 3665fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 3666fcf5ef2aSThomas Huth { 3667fcf5ef2aSThomas Huth TCGv EA; 3668fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3669fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 3670fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 3671fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3672fcf5ef2aSThomas Huth return; 3673fcf5ef2aSThomas Huth } 3674fcf5ef2aSThomas Huth } 3675fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3676fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3677fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3678fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 3679fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 3680fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3681fcf5ef2aSThomas Huth } else { 3682fcf5ef2aSThomas Huth /* ld - ldu */ 3683fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 3684fcf5ef2aSThomas Huth } 3685efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3686fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3687efe843d8SDavid Gibson } 3688fcf5ef2aSThomas Huth tcg_temp_free(EA); 3689fcf5ef2aSThomas Huth } 3690fcf5ef2aSThomas Huth 3691fcf5ef2aSThomas Huth /* lq */ 3692fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 3693fcf5ef2aSThomas Huth { 3694fcf5ef2aSThomas Huth int ra, rd; 369594bf2658SRichard Henderson TCGv EA, hi, lo; 3696fcf5ef2aSThomas Huth 3697fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 3698fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3699fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3700fcf5ef2aSThomas Huth 3701fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3702fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3703fcf5ef2aSThomas Huth return; 3704fcf5ef2aSThomas Huth } 3705fcf5ef2aSThomas Huth 3706fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3707fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3708fcf5ef2aSThomas Huth return; 3709fcf5ef2aSThomas Huth } 3710fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 3711fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 3712fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 3713fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3714fcf5ef2aSThomas Huth return; 3715fcf5ef2aSThomas Huth } 3716fcf5ef2aSThomas Huth 3717fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3718fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3719fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 3720fcf5ef2aSThomas Huth 372194bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 372294bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 372394bf2658SRichard Henderson hi = cpu_gpr[rd]; 372494bf2658SRichard Henderson 372594bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3726f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 372794bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 372894bf2658SRichard Henderson if (ctx->le_mode) { 372994bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 373094bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3731fcf5ef2aSThomas Huth } else { 373294bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 373394bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 373494bf2658SRichard Henderson } 373594bf2658SRichard Henderson tcg_temp_free_i32(oi); 373694bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3737f34ec0f6SRichard Henderson } else { 373894bf2658SRichard Henderson /* Restart with exclusive lock. */ 373994bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 374094bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3741f34ec0f6SRichard Henderson } 374294bf2658SRichard Henderson } else if (ctx->le_mode) { 374394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3744fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 374594bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 374694bf2658SRichard Henderson } else { 374794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 374894bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 374994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3750fcf5ef2aSThomas Huth } 3751fcf5ef2aSThomas Huth tcg_temp_free(EA); 3752fcf5ef2aSThomas Huth } 3753fcf5ef2aSThomas Huth #endif 3754fcf5ef2aSThomas Huth 3755fcf5ef2aSThomas Huth /*** Integer store ***/ 3756fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 3757fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3758fcf5ef2aSThomas Huth { \ 3759fcf5ef2aSThomas Huth TCGv EA; \ 3760fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3761fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3762fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3763fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3764fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3765fcf5ef2aSThomas Huth } 3766fcf5ef2aSThomas Huth 3767fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 3768fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 3769fcf5ef2aSThomas Huth { \ 3770fcf5ef2aSThomas Huth TCGv EA; \ 3771fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3772fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3773fcf5ef2aSThomas Huth return; \ 3774fcf5ef2aSThomas Huth } \ 3775fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3776fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3777fcf5ef2aSThomas Huth if (type == PPC_64B) \ 3778fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 3779fcf5ef2aSThomas Huth else \ 3780fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 3781fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3782fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3783fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3784fcf5ef2aSThomas Huth } 3785fcf5ef2aSThomas Huth 3786fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 3787fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 3788fcf5ef2aSThomas Huth { \ 3789fcf5ef2aSThomas Huth TCGv EA; \ 3790fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 3791fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 3792fcf5ef2aSThomas Huth return; \ 3793fcf5ef2aSThomas Huth } \ 3794fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3795fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3796fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3797fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3798fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 3799fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3800fcf5ef2aSThomas Huth } 3801fcf5ef2aSThomas Huth 3802fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3803fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3804fcf5ef2aSThomas Huth { \ 3805fcf5ef2aSThomas Huth TCGv EA; \ 3806fcf5ef2aSThomas Huth chk; \ 3807fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3808fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3809fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3810fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3811fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3812fcf5ef2aSThomas Huth } 3813fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3814fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3815fcf5ef2aSThomas Huth 3816fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3817fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3818fcf5ef2aSThomas Huth 3819fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 3820fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 3821fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 3822fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 3823fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 3824fcf5ef2aSThomas Huth 3825fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 3826fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 3827fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 3828fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 3829fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 3830fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 383150728199SRoman Kapl 383250728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 383350728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 383450728199SRoman Kapl { \ 383550728199SRoman Kapl TCGv EA; \ 383650728199SRoman Kapl CHK_SV; \ 383750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 383850728199SRoman Kapl EA = tcg_temp_new(); \ 383950728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 384050728199SRoman Kapl tcg_gen_qemu_st_tl( \ 384150728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 384250728199SRoman Kapl tcg_temp_free(EA); \ 384350728199SRoman Kapl } 384450728199SRoman Kapl 384550728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 384650728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 384750728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 384850728199SRoman Kapl #if defined(TARGET_PPC64) 384950728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 385050728199SRoman Kapl #endif 385150728199SRoman Kapl 3852fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3853fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 3854fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 3855fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3856fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3857fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3858fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3859fcf5ef2aSThomas Huth 3860fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 3861fcf5ef2aSThomas Huth { 3862fcf5ef2aSThomas Huth int rs; 3863fcf5ef2aSThomas Huth TCGv EA; 3864fcf5ef2aSThomas Huth 3865fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 3866fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 3867fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3868fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 3869f89ced5fSRichard Henderson TCGv hi, lo; 3870fcf5ef2aSThomas Huth 3871fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 3872fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3873fcf5ef2aSThomas Huth } 3874fcf5ef2aSThomas Huth 3875fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 3876fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 3877fcf5ef2aSThomas Huth return; 3878fcf5ef2aSThomas Huth } 3879fcf5ef2aSThomas Huth 3880fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 3881fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3882fcf5ef2aSThomas Huth return; 3883fcf5ef2aSThomas Huth } 3884fcf5ef2aSThomas Huth 3885fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 3886fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3887fcf5ef2aSThomas Huth return; 3888fcf5ef2aSThomas Huth } 3889fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3890fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3891fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3892fcf5ef2aSThomas Huth 3893f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3894f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 3895f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 3896f89ced5fSRichard Henderson 3897f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3898f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 3899f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 3900f89ced5fSRichard Henderson if (ctx->le_mode) { 3901f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 3902f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 3903fcf5ef2aSThomas Huth } else { 3904f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 3905f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 3906f89ced5fSRichard Henderson } 3907f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 3908f34ec0f6SRichard Henderson } else { 3909f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 3910f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 3911f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3912f34ec0f6SRichard Henderson } 3913f89ced5fSRichard Henderson } else if (ctx->le_mode) { 3914f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 3915fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3916f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 3917f89ced5fSRichard Henderson } else { 3918f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 3919f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 3920f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 3921fcf5ef2aSThomas Huth } 3922fcf5ef2aSThomas Huth tcg_temp_free(EA); 3923fcf5ef2aSThomas Huth } else { 3924fcf5ef2aSThomas Huth /* std / stdu */ 3925fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 3926fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 3927fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3928fcf5ef2aSThomas Huth return; 3929fcf5ef2aSThomas Huth } 3930fcf5ef2aSThomas Huth } 3931fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3932fcf5ef2aSThomas Huth EA = tcg_temp_new(); 3933fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 3934fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 3935efe843d8SDavid Gibson if (Rc(ctx->opcode)) { 3936fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 3937efe843d8SDavid Gibson } 3938fcf5ef2aSThomas Huth tcg_temp_free(EA); 3939fcf5ef2aSThomas Huth } 3940fcf5ef2aSThomas Huth } 3941fcf5ef2aSThomas Huth #endif 3942fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3943fcf5ef2aSThomas Huth 3944fcf5ef2aSThomas Huth /* lhbrx */ 3945fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3946fcf5ef2aSThomas Huth 3947fcf5ef2aSThomas Huth /* lwbrx */ 3948fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3949fcf5ef2aSThomas Huth 3950fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3951fcf5ef2aSThomas Huth /* ldbrx */ 3952fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3953fcf5ef2aSThomas Huth /* stdbrx */ 3954fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3955fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3956fcf5ef2aSThomas Huth 3957fcf5ef2aSThomas Huth /* sthbrx */ 3958fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3959fcf5ef2aSThomas Huth /* stwbrx */ 3960fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3961fcf5ef2aSThomas Huth 3962fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3963fcf5ef2aSThomas Huth 3964fcf5ef2aSThomas Huth /* lmw */ 3965fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3966fcf5ef2aSThomas Huth { 3967fcf5ef2aSThomas Huth TCGv t0; 3968fcf5ef2aSThomas Huth TCGv_i32 t1; 3969fcf5ef2aSThomas Huth 3970fcf5ef2aSThomas Huth if (ctx->le_mode) { 3971fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3972fcf5ef2aSThomas Huth return; 3973fcf5ef2aSThomas Huth } 3974fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3975fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3976fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3977fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3978fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3979fcf5ef2aSThomas Huth tcg_temp_free(t0); 3980fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3981fcf5ef2aSThomas Huth } 3982fcf5ef2aSThomas Huth 3983fcf5ef2aSThomas Huth /* stmw */ 3984fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3985fcf5ef2aSThomas Huth { 3986fcf5ef2aSThomas Huth TCGv t0; 3987fcf5ef2aSThomas Huth TCGv_i32 t1; 3988fcf5ef2aSThomas Huth 3989fcf5ef2aSThomas Huth if (ctx->le_mode) { 3990fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3991fcf5ef2aSThomas Huth return; 3992fcf5ef2aSThomas Huth } 3993fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3994fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3995fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3996fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3997fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3998fcf5ef2aSThomas Huth tcg_temp_free(t0); 3999fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4000fcf5ef2aSThomas Huth } 4001fcf5ef2aSThomas Huth 4002fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 4003fcf5ef2aSThomas Huth 4004fcf5ef2aSThomas Huth /* lswi */ 4005efe843d8SDavid Gibson /* 4006efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 4007efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 4008efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 4009efe843d8SDavid Gibson * spec... 4010fcf5ef2aSThomas Huth */ 4011fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 4012fcf5ef2aSThomas Huth { 4013fcf5ef2aSThomas Huth TCGv t0; 4014fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4015fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4016fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 4017fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 4018fcf5ef2aSThomas Huth int nr; 4019fcf5ef2aSThomas Huth 4020fcf5ef2aSThomas Huth if (ctx->le_mode) { 4021fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4022fcf5ef2aSThomas Huth return; 4023fcf5ef2aSThomas Huth } 4024efe843d8SDavid Gibson if (nb == 0) { 4025fcf5ef2aSThomas Huth nb = 32; 4026efe843d8SDavid Gibson } 4027f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 4028fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 4029fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 4030fcf5ef2aSThomas Huth return; 4031fcf5ef2aSThomas Huth } 4032fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4033fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4034fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4035fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4036fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 4037fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 4038fcf5ef2aSThomas Huth tcg_temp_free(t0); 4039fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4040fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4041fcf5ef2aSThomas Huth } 4042fcf5ef2aSThomas Huth 4043fcf5ef2aSThomas Huth /* lswx */ 4044fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 4045fcf5ef2aSThomas Huth { 4046fcf5ef2aSThomas Huth TCGv t0; 4047fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 4048fcf5ef2aSThomas Huth 4049fcf5ef2aSThomas Huth if (ctx->le_mode) { 4050fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4051fcf5ef2aSThomas Huth return; 4052fcf5ef2aSThomas Huth } 4053fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4054fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4055fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4056fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 4057fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 4058fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 4059fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 4060fcf5ef2aSThomas Huth tcg_temp_free(t0); 4061fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4062fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4063fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4064fcf5ef2aSThomas Huth } 4065fcf5ef2aSThomas Huth 4066fcf5ef2aSThomas Huth /* stswi */ 4067fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 4068fcf5ef2aSThomas Huth { 4069fcf5ef2aSThomas Huth TCGv t0; 4070fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4071fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 4072fcf5ef2aSThomas Huth 4073fcf5ef2aSThomas Huth if (ctx->le_mode) { 4074fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4075fcf5ef2aSThomas Huth return; 4076fcf5ef2aSThomas Huth } 4077fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4078fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4079fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 4080efe843d8SDavid Gibson if (nb == 0) { 4081fcf5ef2aSThomas Huth nb = 32; 4082efe843d8SDavid Gibson } 4083fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 4084fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4085fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4086fcf5ef2aSThomas Huth tcg_temp_free(t0); 4087fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4088fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4089fcf5ef2aSThomas Huth } 4090fcf5ef2aSThomas Huth 4091fcf5ef2aSThomas Huth /* stswx */ 4092fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 4093fcf5ef2aSThomas Huth { 4094fcf5ef2aSThomas Huth TCGv t0; 4095fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 4096fcf5ef2aSThomas Huth 4097fcf5ef2aSThomas Huth if (ctx->le_mode) { 4098fcf5ef2aSThomas Huth gen_align_no_le(ctx); 4099fcf5ef2aSThomas Huth return; 4100fcf5ef2aSThomas Huth } 4101fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 4102fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4103fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4104fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4105fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 4106fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 4107fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 4108fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 4109fcf5ef2aSThomas Huth tcg_temp_free(t0); 4110fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4111fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4112fcf5ef2aSThomas Huth } 4113fcf5ef2aSThomas Huth 4114fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 4115fcf5ef2aSThomas Huth /* eieio */ 4116fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 4117fcf5ef2aSThomas Huth { 4118c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 4119c8fd8373SCédric Le Goater 4120c8fd8373SCédric Le Goater /* 4121c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 4122c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 4123c8fd8373SCédric Le Goater */ 4124c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 4125c8fd8373SCédric Le Goater /* 4126c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 4127c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 4128c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 4129c8fd8373SCédric Le Goater * complain to the user. 4130c8fd8373SCédric Le Goater */ 4131c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 4132c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 41332c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 4134c8fd8373SCédric Le Goater } else { 4135c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 4136c8fd8373SCédric Le Goater } 4137c8fd8373SCédric Le Goater } 4138c8fd8373SCédric Le Goater 4139c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 4140fcf5ef2aSThomas Huth } 4141fcf5ef2aSThomas Huth 4142fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4143fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 4144fcf5ef2aSThomas Huth { 4145fcf5ef2aSThomas Huth TCGv_i32 t; 4146fcf5ef2aSThomas Huth TCGLabel *l; 4147fcf5ef2aSThomas Huth 4148fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 4149fcf5ef2aSThomas Huth return; 4150fcf5ef2aSThomas Huth } 4151fcf5ef2aSThomas Huth l = gen_new_label(); 4152fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 4153fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4154fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 4155fcf5ef2aSThomas Huth if (global) { 4156fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 4157fcf5ef2aSThomas Huth } else { 4158fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 4159fcf5ef2aSThomas Huth } 4160fcf5ef2aSThomas Huth gen_set_label(l); 4161fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4162fcf5ef2aSThomas Huth } 4163fcf5ef2aSThomas Huth #else 4164fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 4165fcf5ef2aSThomas Huth #endif 4166fcf5ef2aSThomas Huth 4167fcf5ef2aSThomas Huth /* isync */ 4168fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 4169fcf5ef2aSThomas Huth { 4170fcf5ef2aSThomas Huth /* 4171fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 4172fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 4173fcf5ef2aSThomas Huth */ 4174fcf5ef2aSThomas Huth if (!ctx->pr) { 4175fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 4176fcf5ef2aSThomas Huth } 41774771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4178fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4179fcf5ef2aSThomas Huth } 4180fcf5ef2aSThomas Huth 4181fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 4182fcf5ef2aSThomas Huth 418314776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 41842a4e6c1bSRichard Henderson { 41852a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 41862a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 41872a4e6c1bSRichard Henderson 41882a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 41892a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 41902a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 41912a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 41922a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 41932a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 41942a4e6c1bSRichard Henderson tcg_temp_free(t0); 41952a4e6c1bSRichard Henderson } 41962a4e6c1bSRichard Henderson 4197fcf5ef2aSThomas Huth #define LARX(name, memop) \ 4198fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4199fcf5ef2aSThomas Huth { \ 42002a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 4201fcf5ef2aSThomas Huth } 4202fcf5ef2aSThomas Huth 4203fcf5ef2aSThomas Huth /* lwarx */ 4204fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 4205fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 4206fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 4207fcf5ef2aSThomas Huth 420814776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 420920923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 421020923c1dSRichard Henderson { 421120923c1dSRichard Henderson TCGv t = tcg_temp_new(); 421220923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 421320923c1dSRichard Henderson TCGv u = tcg_temp_new(); 421420923c1dSRichard Henderson 421520923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 421620923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 421720923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 421820923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 421920923c1dSRichard Henderson 422020923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 422120923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 422220923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 422320923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 422420923c1dSRichard Henderson 422520923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 422620923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 422720923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 422820923c1dSRichard Henderson 422920923c1dSRichard Henderson tcg_temp_free(t); 423020923c1dSRichard Henderson tcg_temp_free(t2); 423120923c1dSRichard Henderson tcg_temp_free(u); 423220923c1dSRichard Henderson } 423320923c1dSRichard Henderson 423414776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 423520ba8504SRichard Henderson { 423620ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 423720ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 423820923c1dSRichard Henderson int rt = rD(ctx->opcode); 423920923c1dSRichard Henderson bool need_serial; 424020ba8504SRichard Henderson TCGv src, dst; 424120ba8504SRichard Henderson 424220ba8504SRichard Henderson gen_addr_register(ctx, EA); 424320923c1dSRichard Henderson dst = cpu_gpr[rt]; 424420923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 424520ba8504SRichard Henderson 424620923c1dSRichard Henderson need_serial = false; 424720ba8504SRichard Henderson memop |= MO_ALIGN; 424820ba8504SRichard Henderson switch (gpr_FC) { 424920ba8504SRichard Henderson case 0: /* Fetch and add */ 425020ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 425120ba8504SRichard Henderson break; 425220ba8504SRichard Henderson case 1: /* Fetch and xor */ 425320ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 425420ba8504SRichard Henderson break; 425520ba8504SRichard Henderson case 2: /* Fetch and or */ 425620ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 425720ba8504SRichard Henderson break; 425820ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 425920ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 426020ba8504SRichard Henderson break; 4261b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 4262b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 4263b8ce0f86SRichard Henderson break; 4264b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 4265b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 4266b8ce0f86SRichard Henderson break; 4267b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 4268b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 4269b8ce0f86SRichard Henderson break; 4270b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 4271b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 4272b8ce0f86SRichard Henderson break; 427320ba8504SRichard Henderson case 8: /* Swap */ 427420ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 427520ba8504SRichard Henderson break; 427620923c1dSRichard Henderson 427720923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 427820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 427920923c1dSRichard Henderson need_serial = true; 428020923c1dSRichard Henderson } else { 428120923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 428220923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 428320923c1dSRichard Henderson 428420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 428520923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 428620923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 428720923c1dSRichard Henderson } else { 428820923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 428920923c1dSRichard Henderson } 429020923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 429120923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 429220923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 429320923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 429420923c1dSRichard Henderson 429520923c1dSRichard Henderson tcg_temp_free(t0); 429620923c1dSRichard Henderson tcg_temp_free(t1); 429720923c1dSRichard Henderson } 429820ba8504SRichard Henderson break; 429920923c1dSRichard Henderson 430020923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 430120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 430220923c1dSRichard Henderson need_serial = true; 430320923c1dSRichard Henderson } else { 430420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 430520923c1dSRichard Henderson } 430620923c1dSRichard Henderson break; 430720923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 430820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 430920923c1dSRichard Henderson need_serial = true; 431020923c1dSRichard Henderson } else { 431120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 431220923c1dSRichard Henderson } 431320923c1dSRichard Henderson break; 431420923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 431520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 431620923c1dSRichard Henderson need_serial = true; 431720923c1dSRichard Henderson } else { 431820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 431920923c1dSRichard Henderson } 432020923c1dSRichard Henderson break; 432120923c1dSRichard Henderson 432220ba8504SRichard Henderson default: 432320ba8504SRichard Henderson /* invoke data storage error handler */ 432420ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 432520ba8504SRichard Henderson } 432620ba8504SRichard Henderson tcg_temp_free(EA); 432720923c1dSRichard Henderson 432820923c1dSRichard Henderson if (need_serial) { 432920923c1dSRichard Henderson /* Restart with exclusive lock. */ 433020923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 433120923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 433220923c1dSRichard Henderson } 4333a68a6146SBalamuruhan S } 4334a68a6146SBalamuruhan S 433520ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 433620ba8504SRichard Henderson { 433720ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 433820ba8504SRichard Henderson } 433920ba8504SRichard Henderson 434020ba8504SRichard Henderson #ifdef TARGET_PPC64 434120ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 434220ba8504SRichard Henderson { 434320ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 434420ba8504SRichard Henderson } 4345a68a6146SBalamuruhan S #endif 4346a68a6146SBalamuruhan S 434714776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 43489deb041cSRichard Henderson { 43499deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 43509deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 43519deb041cSRichard Henderson TCGv src, discard; 43529deb041cSRichard Henderson 43539deb041cSRichard Henderson gen_addr_register(ctx, EA); 43549deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 43559deb041cSRichard Henderson discard = tcg_temp_new(); 43569deb041cSRichard Henderson 43579deb041cSRichard Henderson memop |= MO_ALIGN; 43589deb041cSRichard Henderson switch (gpr_FC) { 43599deb041cSRichard Henderson case 0: /* add and Store */ 43609deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43619deb041cSRichard Henderson break; 43629deb041cSRichard Henderson case 1: /* xor and Store */ 43639deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43649deb041cSRichard Henderson break; 43659deb041cSRichard Henderson case 2: /* Or and Store */ 43669deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43679deb041cSRichard Henderson break; 43689deb041cSRichard Henderson case 3: /* 'and' and Store */ 43699deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 43709deb041cSRichard Henderson break; 43719deb041cSRichard Henderson case 4: /* Store max unsigned */ 4372b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4373b8ce0f86SRichard Henderson break; 43749deb041cSRichard Henderson case 5: /* Store max signed */ 4375b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4376b8ce0f86SRichard Henderson break; 43779deb041cSRichard Henderson case 6: /* Store min unsigned */ 4378b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4379b8ce0f86SRichard Henderson break; 43809deb041cSRichard Henderson case 7: /* Store min signed */ 4381b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 4382b8ce0f86SRichard Henderson break; 43839deb041cSRichard Henderson case 24: /* Store twin */ 43847fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 43857fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 43867fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 43877fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 43887fbc2b20SRichard Henderson } else { 43897fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 43907fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 43917fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 43927fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 43937fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 43947fbc2b20SRichard Henderson 43957fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 43967fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 43977fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 43987fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 43997fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 44007fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 44017fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 44027fbc2b20SRichard Henderson 44037fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 44047fbc2b20SRichard Henderson tcg_temp_free(s2); 44057fbc2b20SRichard Henderson tcg_temp_free(s); 44067fbc2b20SRichard Henderson tcg_temp_free(t2); 44077fbc2b20SRichard Henderson tcg_temp_free(t); 44087fbc2b20SRichard Henderson } 44099deb041cSRichard Henderson break; 44109deb041cSRichard Henderson default: 44119deb041cSRichard Henderson /* invoke data storage error handler */ 44129deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 44139deb041cSRichard Henderson } 44149deb041cSRichard Henderson tcg_temp_free(discard); 44159deb041cSRichard Henderson tcg_temp_free(EA); 4416a3401188SBalamuruhan S } 4417a3401188SBalamuruhan S 44189deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 44199deb041cSRichard Henderson { 44209deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 44219deb041cSRichard Henderson } 44229deb041cSRichard Henderson 44239deb041cSRichard Henderson #ifdef TARGET_PPC64 44249deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 44259deb041cSRichard Henderson { 44269deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 44279deb041cSRichard Henderson } 4428a3401188SBalamuruhan S #endif 4429a3401188SBalamuruhan S 443014776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 4431fcf5ef2aSThomas Huth { 4432253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 4433253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 4434d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 4435d8b86898SRichard Henderson int reg = rS(ctx->opcode); 4436fcf5ef2aSThomas Huth 4437d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 4438d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 4439d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 4440d8b86898SRichard Henderson tcg_temp_free(t0); 4441253ce7b2SNikunj A Dadhania 4442253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 4443253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 4444253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 4445253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 4446253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 4447253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 4448253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 4449253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 4450253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 4451253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 4452253ce7b2SNikunj A Dadhania 4453fcf5ef2aSThomas Huth gen_set_label(l1); 44544771df23SNikunj A Dadhania 4455efe843d8SDavid Gibson /* 4456efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 4457efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 4458efe843d8SDavid Gibson */ 44594771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 4460253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4461253ce7b2SNikunj A Dadhania 4462253ce7b2SNikunj A Dadhania gen_set_label(l2); 4463fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 4464fcf5ef2aSThomas Huth } 4465fcf5ef2aSThomas Huth 4466fcf5ef2aSThomas Huth #define STCX(name, memop) \ 4467fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 4468fcf5ef2aSThomas Huth { \ 4469d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 4470fcf5ef2aSThomas Huth } 4471fcf5ef2aSThomas Huth 4472fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 4473fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 4474fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 4475fcf5ef2aSThomas Huth 4476fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4477fcf5ef2aSThomas Huth /* ldarx */ 4478fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 4479fcf5ef2aSThomas Huth /* stdcx. */ 4480fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 4481fcf5ef2aSThomas Huth 4482fcf5ef2aSThomas Huth /* lqarx */ 4483fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 4484fcf5ef2aSThomas Huth { 4485fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 448694bf2658SRichard Henderson TCGv EA, hi, lo; 4487fcf5ef2aSThomas Huth 4488fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 4489fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 4490fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4491fcf5ef2aSThomas Huth return; 4492fcf5ef2aSThomas Huth } 4493fcf5ef2aSThomas Huth 4494fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 449594bf2658SRichard Henderson EA = tcg_temp_new(); 4496fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 449794bf2658SRichard Henderson 449894bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 449994bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 450094bf2658SRichard Henderson hi = cpu_gpr[rd]; 450194bf2658SRichard Henderson 450294bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4503f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 450494bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 450594bf2658SRichard Henderson if (ctx->le_mode) { 450694bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 450794bf2658SRichard Henderson ctx->mem_idx)); 450894bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 4509fcf5ef2aSThomas Huth } else { 451094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 451194bf2658SRichard Henderson ctx->mem_idx)); 451294bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 4513fcf5ef2aSThomas Huth } 451494bf2658SRichard Henderson tcg_temp_free_i32(oi); 451594bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 4516f34ec0f6SRichard Henderson } else { 451794bf2658SRichard Henderson /* Restart with exclusive lock. */ 451894bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 451994bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 452094bf2658SRichard Henderson tcg_temp_free(EA); 452194bf2658SRichard Henderson return; 4522f34ec0f6SRichard Henderson } 452394bf2658SRichard Henderson } else if (ctx->le_mode) { 452494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 4525fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 4526fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 452794bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 452894bf2658SRichard Henderson } else { 452994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 453094bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 453194bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 453294bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 453394bf2658SRichard Henderson } 4534fcf5ef2aSThomas Huth tcg_temp_free(EA); 453594bf2658SRichard Henderson 453694bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 453794bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 4538fcf5ef2aSThomas Huth } 4539fcf5ef2aSThomas Huth 4540fcf5ef2aSThomas Huth /* stqcx. */ 4541fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 4542fcf5ef2aSThomas Huth { 45434a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 45444a9b3c5dSRichard Henderson TCGv EA, hi, lo; 4545fcf5ef2aSThomas Huth 45464a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 4547fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4548fcf5ef2aSThomas Huth return; 4549fcf5ef2aSThomas Huth } 45504a9b3c5dSRichard Henderson 4551fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 45524a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4553fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4554fcf5ef2aSThomas Huth 45554a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 45564a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 45574a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4558fcf5ef2aSThomas Huth 45594a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4560f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 45614a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 45624a9b3c5dSRichard Henderson if (ctx->le_mode) { 4563f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4564f34ec0f6SRichard Henderson EA, lo, hi, oi); 4565fcf5ef2aSThomas Huth } else { 4566f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4567f34ec0f6SRichard Henderson EA, lo, hi, oi); 4568fcf5ef2aSThomas Huth } 4569f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4570f34ec0f6SRichard Henderson } else { 45714a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 45724a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 45734a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4574f34ec0f6SRichard Henderson } 4575fcf5ef2aSThomas Huth tcg_temp_free(EA); 45764a9b3c5dSRichard Henderson } else { 45774a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 45784a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 45794a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 45804a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4581fcf5ef2aSThomas Huth 45824a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 45834a9b3c5dSRichard Henderson tcg_temp_free(EA); 45844a9b3c5dSRichard Henderson 45854a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 45864a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 45874a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 45884a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 45894a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 45904a9b3c5dSRichard Henderson 45914a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 45924a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 45934a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 45944a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 45954a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 45964a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 45974a9b3c5dSRichard Henderson 45984a9b3c5dSRichard Henderson /* Success */ 45994a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 46004a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 46014a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 46024a9b3c5dSRichard Henderson 46034a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46044a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 46054a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 46064a9b3c5dSRichard Henderson 46074a9b3c5dSRichard Henderson gen_set_label(lab_fail); 46084a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 46094a9b3c5dSRichard Henderson 46104a9b3c5dSRichard Henderson gen_set_label(lab_over); 46114a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 46124a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 46134a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 46144a9b3c5dSRichard Henderson } 46154a9b3c5dSRichard Henderson } 4616fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4617fcf5ef2aSThomas Huth 4618fcf5ef2aSThomas Huth /* sync */ 4619fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4620fcf5ef2aSThomas Huth { 4621fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4622fcf5ef2aSThomas Huth 4623fcf5ef2aSThomas Huth /* 4624fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4625fcf5ef2aSThomas Huth * 4626fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4627fcf5ef2aSThomas Huth * 4628fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4629fcf5ef2aSThomas Huth * check MSR_PR as well. 4630fcf5ef2aSThomas Huth */ 4631fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4632fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4633fcf5ef2aSThomas Huth } 46344771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4635fcf5ef2aSThomas Huth } 4636fcf5ef2aSThomas Huth 4637fcf5ef2aSThomas Huth /* wait */ 4638fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4639fcf5ef2aSThomas Huth { 4640fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4641fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4642fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4643fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4644fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4645b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4646fcf5ef2aSThomas Huth } 4647fcf5ef2aSThomas Huth 4648fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4649fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4650fcf5ef2aSThomas Huth { 4651fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4652fcf5ef2aSThomas Huth GEN_PRIV; 4653fcf5ef2aSThomas Huth #else 4654fcf5ef2aSThomas Huth TCGv_i32 t; 4655fcf5ef2aSThomas Huth 4656fcf5ef2aSThomas Huth CHK_HV; 4657fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4658fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4659fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4660154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4661154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4662fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4663fcf5ef2aSThomas Huth } 4664fcf5ef2aSThomas Huth 4665fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4666fcf5ef2aSThomas Huth { 4667fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4668fcf5ef2aSThomas Huth GEN_PRIV; 4669fcf5ef2aSThomas Huth #else 4670fcf5ef2aSThomas Huth TCGv_i32 t; 4671fcf5ef2aSThomas Huth 4672fcf5ef2aSThomas Huth CHK_HV; 4673fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4674fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4675fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4676154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4677154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4678fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4679fcf5ef2aSThomas Huth } 4680fcf5ef2aSThomas Huth 4681cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4682cdee0e72SNikunj A Dadhania { 468321c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 468421c0d66aSBenjamin Herrenschmidt GEN_PRIV; 468521c0d66aSBenjamin Herrenschmidt #else 468621c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 468721c0d66aSBenjamin Herrenschmidt 468821c0d66aSBenjamin Herrenschmidt CHK_HV; 468921c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 469021c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 469121c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 469221c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 469321c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 469421c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4695cdee0e72SNikunj A Dadhania } 4696cdee0e72SNikunj A Dadhania 4697fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4698fcf5ef2aSThomas Huth { 4699fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4700fcf5ef2aSThomas Huth GEN_PRIV; 4701fcf5ef2aSThomas Huth #else 4702fcf5ef2aSThomas Huth TCGv_i32 t; 4703fcf5ef2aSThomas Huth 4704fcf5ef2aSThomas Huth CHK_HV; 4705fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4706fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4707fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4708154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4709154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4710fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4711fcf5ef2aSThomas Huth } 4712fcf5ef2aSThomas Huth 4713fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4714fcf5ef2aSThomas Huth { 4715fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4716fcf5ef2aSThomas Huth GEN_PRIV; 4717fcf5ef2aSThomas Huth #else 4718fcf5ef2aSThomas Huth TCGv_i32 t; 4719fcf5ef2aSThomas Huth 4720fcf5ef2aSThomas Huth CHK_HV; 4721fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4722fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4723fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4724154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4725154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4726fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4727fcf5ef2aSThomas Huth } 4728fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4729fcf5ef2aSThomas Huth 4730fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4731fcf5ef2aSThomas Huth { 4732fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4733efe843d8SDavid Gibson if (ctx->has_cfar) { 4734fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4735efe843d8SDavid Gibson } 4736fcf5ef2aSThomas Huth #endif 4737fcf5ef2aSThomas Huth } 4738fcf5ef2aSThomas Huth 4739fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4740fcf5ef2aSThomas Huth { 4741fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 4742fcf5ef2aSThomas Huth return false; 4743fcf5ef2aSThomas Huth } 4744fcf5ef2aSThomas Huth 4745fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 4746b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 4747fcf5ef2aSThomas Huth #else 4748fcf5ef2aSThomas Huth return true; 4749fcf5ef2aSThomas Huth #endif 4750fcf5ef2aSThomas Huth } 4751fcf5ef2aSThomas Huth 47520e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 47530e3bf489SRoman Kapl { 47540e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 47550e3bf489SRoman Kapl if (unlikely(sse)) { 47560e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 47570e3bf489SRoman Kapl gen_debug_exception(ctx); 47580e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 4759e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 47600e3bf489SRoman Kapl gen_exception(ctx, excp); 47610e3bf489SRoman Kapl } 47620e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 47630e3bf489SRoman Kapl } else { 47640e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 47650e3bf489SRoman Kapl } 47660e3bf489SRoman Kapl } 47670e3bf489SRoman Kapl 4768fcf5ef2aSThomas Huth /*** Branch ***/ 4769c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4770fcf5ef2aSThomas Huth { 4771fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4772fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4773fcf5ef2aSThomas Huth } 4774fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 4775fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4776fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 477707ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4778fcf5ef2aSThomas Huth } else { 4779fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 47800e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4781fcf5ef2aSThomas Huth } 4782fcf5ef2aSThomas Huth } 4783fcf5ef2aSThomas Huth 4784fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4785fcf5ef2aSThomas Huth { 4786fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4787fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4788fcf5ef2aSThomas Huth } 4789fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4790fcf5ef2aSThomas Huth } 4791fcf5ef2aSThomas Huth 4792fcf5ef2aSThomas Huth /* b ba bl bla */ 4793fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4794fcf5ef2aSThomas Huth { 4795fcf5ef2aSThomas Huth target_ulong li, target; 4796fcf5ef2aSThomas Huth 4797fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 4798fcf5ef2aSThomas Huth /* sign extend LI */ 4799fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4800fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4801fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 48022c2bcb1bSRichard Henderson target = ctx->cia + li; 4803fcf5ef2aSThomas Huth } else { 4804fcf5ef2aSThomas Huth target = li; 4805fcf5ef2aSThomas Huth } 4806fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4807b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4808fcf5ef2aSThomas Huth } 48092c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4810fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 4811fcf5ef2aSThomas Huth } 4812fcf5ef2aSThomas Huth 4813fcf5ef2aSThomas Huth #define BCOND_IM 0 4814fcf5ef2aSThomas Huth #define BCOND_LR 1 4815fcf5ef2aSThomas Huth #define BCOND_CTR 2 4816fcf5ef2aSThomas Huth #define BCOND_TAR 3 4817fcf5ef2aSThomas Huth 4818c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4819fcf5ef2aSThomas Huth { 4820fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4821fcf5ef2aSThomas Huth TCGLabel *l1; 4822fcf5ef2aSThomas Huth TCGv target; 4823fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 48240e3bf489SRoman Kapl 4825fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4826fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4827efe843d8SDavid Gibson if (type == BCOND_CTR) { 4828fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4829efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4830fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4831efe843d8SDavid Gibson } else { 4832fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4833efe843d8SDavid Gibson } 4834fcf5ef2aSThomas Huth } else { 4835f764718dSRichard Henderson target = NULL; 4836fcf5ef2aSThomas Huth } 4837efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4838b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4839efe843d8SDavid Gibson } 4840fcf5ef2aSThomas Huth l1 = gen_new_label(); 4841fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4842fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4843fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4844fa200c95SGreg Kurz 4845fa200c95SGreg Kurz if (type == BCOND_CTR) { 4846fa200c95SGreg Kurz /* 4847fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4848fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4849fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 485015d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 485115d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 485215d68c5eSGreg Kurz * it basically useless and thus never used in real code. 485315d68c5eSGreg Kurz * 485415d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 485515d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 485615d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 485715d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 485815d68c5eSGreg Kurz * doing anything else harmful. 4859fa200c95SGreg Kurz */ 4860d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4861fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 48629acc95cdSGreg Kurz tcg_temp_free(temp); 48639acc95cdSGreg Kurz tcg_temp_free(target); 4864fcf5ef2aSThomas Huth return; 4865fcf5ef2aSThomas Huth } 4866fa200c95SGreg Kurz 4867fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4868fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4869fa200c95SGreg Kurz } else { 4870fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4871fa200c95SGreg Kurz } 4872fa200c95SGreg Kurz if (bo & 0x2) { 4873fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4874fa200c95SGreg Kurz } else { 4875fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4876fa200c95SGreg Kurz } 4877fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4878fa200c95SGreg Kurz } else { 4879fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4880fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4881fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4882fcf5ef2aSThomas Huth } else { 4883fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4884fcf5ef2aSThomas Huth } 4885fcf5ef2aSThomas Huth if (bo & 0x2) { 4886fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4887fcf5ef2aSThomas Huth } else { 4888fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4889fcf5ef2aSThomas Huth } 4890fa200c95SGreg Kurz } 4891fcf5ef2aSThomas Huth tcg_temp_free(temp); 4892fcf5ef2aSThomas Huth } 4893fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4894fcf5ef2aSThomas Huth /* Test CR */ 4895fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4896fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4897fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4898fcf5ef2aSThomas Huth 4899fcf5ef2aSThomas Huth if (bo & 0x8) { 4900fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4901fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4902fcf5ef2aSThomas Huth } else { 4903fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4904fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4905fcf5ef2aSThomas Huth } 4906fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4907fcf5ef2aSThomas Huth } 49082c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4909fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4910fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4911fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 49122c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4913fcf5ef2aSThomas Huth } else { 4914fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4915fcf5ef2aSThomas Huth } 4916fcf5ef2aSThomas Huth } else { 4917fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4918fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4919fcf5ef2aSThomas Huth } else { 4920fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4921fcf5ef2aSThomas Huth } 49220e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4923c4a2e3a9SRichard Henderson tcg_temp_free(target); 4924c4a2e3a9SRichard Henderson } 4925fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 49260e3bf489SRoman Kapl /* fallthrough case */ 4927fcf5ef2aSThomas Huth gen_set_label(l1); 4928b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4929fcf5ef2aSThomas Huth } 4930fcf5ef2aSThomas Huth } 4931fcf5ef2aSThomas Huth 4932fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4933fcf5ef2aSThomas Huth { 4934fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4935fcf5ef2aSThomas Huth } 4936fcf5ef2aSThomas Huth 4937fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4938fcf5ef2aSThomas Huth { 4939fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4940fcf5ef2aSThomas Huth } 4941fcf5ef2aSThomas Huth 4942fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4943fcf5ef2aSThomas Huth { 4944fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4945fcf5ef2aSThomas Huth } 4946fcf5ef2aSThomas Huth 4947fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4948fcf5ef2aSThomas Huth { 4949fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4950fcf5ef2aSThomas Huth } 4951fcf5ef2aSThomas Huth 4952fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4953fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4954fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4955fcf5ef2aSThomas Huth { \ 4956fcf5ef2aSThomas Huth uint8_t bitmask; \ 4957fcf5ef2aSThomas Huth int sh; \ 4958fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4959fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4960fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4961fcf5ef2aSThomas Huth if (sh > 0) \ 4962fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4963fcf5ef2aSThomas Huth else if (sh < 0) \ 4964fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4965fcf5ef2aSThomas Huth else \ 4966fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4967fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4968fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4969fcf5ef2aSThomas Huth if (sh > 0) \ 4970fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4971fcf5ef2aSThomas Huth else if (sh < 0) \ 4972fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4973fcf5ef2aSThomas Huth else \ 4974fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4975fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4976fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4977fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4978fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4979fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4980fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4981fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4982fcf5ef2aSThomas Huth } 4983fcf5ef2aSThomas Huth 4984fcf5ef2aSThomas Huth /* crand */ 4985fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4986fcf5ef2aSThomas Huth /* crandc */ 4987fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4988fcf5ef2aSThomas Huth /* creqv */ 4989fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4990fcf5ef2aSThomas Huth /* crnand */ 4991fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4992fcf5ef2aSThomas Huth /* crnor */ 4993fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4994fcf5ef2aSThomas Huth /* cror */ 4995fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4996fcf5ef2aSThomas Huth /* crorc */ 4997fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4998fcf5ef2aSThomas Huth /* crxor */ 4999fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 5000fcf5ef2aSThomas Huth 5001fcf5ef2aSThomas Huth /* mcrf */ 5002fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 5003fcf5ef2aSThomas Huth { 5004fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 5005fcf5ef2aSThomas Huth } 5006fcf5ef2aSThomas Huth 5007fcf5ef2aSThomas Huth /*** System linkage ***/ 5008fcf5ef2aSThomas Huth 5009fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 5010fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 5011fcf5ef2aSThomas Huth { 5012fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5013fcf5ef2aSThomas Huth GEN_PRIV; 5014fcf5ef2aSThomas Huth #else 5015efe843d8SDavid Gibson /* 5016efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 5017fcf5ef2aSThomas Huth * processors compliant with arch 2.x 5018fcf5ef2aSThomas Huth */ 5019d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 5020fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5021fcf5ef2aSThomas Huth return; 5022fcf5ef2aSThomas Huth } 5023fcf5ef2aSThomas Huth /* Restore CPU state */ 5024fcf5ef2aSThomas Huth CHK_SV; 5025a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5026a59d628fSMaria Klimushenkova gen_io_start(); 5027a59d628fSMaria Klimushenkova } 50282c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 5029fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 5030fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5031fcf5ef2aSThomas Huth #endif 5032fcf5ef2aSThomas Huth } 5033fcf5ef2aSThomas Huth 5034fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5035fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 5036fcf5ef2aSThomas Huth { 5037fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5038fcf5ef2aSThomas Huth GEN_PRIV; 5039fcf5ef2aSThomas Huth #else 5040fcf5ef2aSThomas Huth /* Restore CPU state */ 5041fcf5ef2aSThomas Huth CHK_SV; 5042a59d628fSMaria Klimushenkova if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 5043a59d628fSMaria Klimushenkova gen_io_start(); 5044a59d628fSMaria Klimushenkova } 50452c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 5046fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 5047fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5048fcf5ef2aSThomas Huth #endif 5049fcf5ef2aSThomas Huth } 5050fcf5ef2aSThomas Huth 50513c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 50523c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 50533c89b8d6SNicholas Piggin { 50543c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 50553c89b8d6SNicholas Piggin GEN_PRIV; 50563c89b8d6SNicholas Piggin #else 50573c89b8d6SNicholas Piggin /* Restore CPU state */ 50583c89b8d6SNicholas Piggin CHK_SV; 50593c89b8d6SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 50603c89b8d6SNicholas Piggin gen_io_start(); 50613c89b8d6SNicholas Piggin } 50622c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 50633c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 50643c89b8d6SNicholas Piggin gen_sync_exception(ctx); 50653c89b8d6SNicholas Piggin #endif 50663c89b8d6SNicholas Piggin } 50673c89b8d6SNicholas Piggin #endif 50683c89b8d6SNicholas Piggin 5069fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 5070fcf5ef2aSThomas Huth { 5071fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5072fcf5ef2aSThomas Huth GEN_PRIV; 5073fcf5ef2aSThomas Huth #else 5074fcf5ef2aSThomas Huth /* Restore CPU state */ 5075fcf5ef2aSThomas Huth CHK_HV; 5076fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 5077fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5078fcf5ef2aSThomas Huth #endif 5079fcf5ef2aSThomas Huth } 5080fcf5ef2aSThomas Huth #endif 5081fcf5ef2aSThomas Huth 5082fcf5ef2aSThomas Huth /* sc */ 5083fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5084fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 5085fcf5ef2aSThomas Huth #else 5086fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 50873c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 5088fcf5ef2aSThomas Huth #endif 5089fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 5090fcf5ef2aSThomas Huth { 5091fcf5ef2aSThomas Huth uint32_t lev; 5092fcf5ef2aSThomas Huth 5093fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 5094fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 5095fcf5ef2aSThomas Huth } 5096fcf5ef2aSThomas Huth 50973c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 50983c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 50993c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 51003c89b8d6SNicholas Piggin { 5101f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 51023c89b8d6SNicholas Piggin 5103f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 5104f43520e5SRichard Henderson if (ctx->exception == POWERPC_EXCP_NONE) { 51052c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 51063c89b8d6SNicholas Piggin } 5107f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 51083c89b8d6SNicholas Piggin 5109f43520e5SRichard Henderson /* This need not be exact, just not POWERPC_EXCP_NONE */ 5110f43520e5SRichard Henderson ctx->exception = POWERPC_SYSCALL_VECTORED; 51113c89b8d6SNicholas Piggin } 51123c89b8d6SNicholas Piggin #endif 51133c89b8d6SNicholas Piggin #endif 51143c89b8d6SNicholas Piggin 5115fcf5ef2aSThomas Huth /*** Trap ***/ 5116fcf5ef2aSThomas Huth 5117fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 5118fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 5119fcf5ef2aSThomas Huth { 5120fcf5ef2aSThomas Huth /* Trap never */ 5121fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 5122fcf5ef2aSThomas Huth return true; 5123fcf5ef2aSThomas Huth } 5124fcf5ef2aSThomas Huth /* Trap always */ 5125fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 5126fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 5127fcf5ef2aSThomas Huth return true; 5128fcf5ef2aSThomas Huth } 5129fcf5ef2aSThomas Huth return false; 5130fcf5ef2aSThomas Huth } 5131fcf5ef2aSThomas Huth 5132fcf5ef2aSThomas Huth /* tw */ 5133fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 5134fcf5ef2aSThomas Huth { 5135fcf5ef2aSThomas Huth TCGv_i32 t0; 5136fcf5ef2aSThomas Huth 5137fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5138fcf5ef2aSThomas Huth return; 5139fcf5ef2aSThomas Huth } 5140fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5141fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5142fcf5ef2aSThomas Huth t0); 5143fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5144fcf5ef2aSThomas Huth } 5145fcf5ef2aSThomas Huth 5146fcf5ef2aSThomas Huth /* twi */ 5147fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 5148fcf5ef2aSThomas Huth { 5149fcf5ef2aSThomas Huth TCGv t0; 5150fcf5ef2aSThomas Huth TCGv_i32 t1; 5151fcf5ef2aSThomas Huth 5152fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5153fcf5ef2aSThomas Huth return; 5154fcf5ef2aSThomas Huth } 5155fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5156fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5157fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5158fcf5ef2aSThomas Huth tcg_temp_free(t0); 5159fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5160fcf5ef2aSThomas Huth } 5161fcf5ef2aSThomas Huth 5162fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5163fcf5ef2aSThomas Huth /* td */ 5164fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 5165fcf5ef2aSThomas Huth { 5166fcf5ef2aSThomas Huth TCGv_i32 t0; 5167fcf5ef2aSThomas Huth 5168fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5169fcf5ef2aSThomas Huth return; 5170fcf5ef2aSThomas Huth } 5171fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 5172fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5173fcf5ef2aSThomas Huth t0); 5174fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5175fcf5ef2aSThomas Huth } 5176fcf5ef2aSThomas Huth 5177fcf5ef2aSThomas Huth /* tdi */ 5178fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 5179fcf5ef2aSThomas Huth { 5180fcf5ef2aSThomas Huth TCGv t0; 5181fcf5ef2aSThomas Huth TCGv_i32 t1; 5182fcf5ef2aSThomas Huth 5183fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 5184fcf5ef2aSThomas Huth return; 5185fcf5ef2aSThomas Huth } 5186fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 5187fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 5188fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 5189fcf5ef2aSThomas Huth tcg_temp_free(t0); 5190fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5191fcf5ef2aSThomas Huth } 5192fcf5ef2aSThomas Huth #endif 5193fcf5ef2aSThomas Huth 5194fcf5ef2aSThomas Huth /*** Processor control ***/ 5195fcf5ef2aSThomas Huth 5196fcf5ef2aSThomas Huth /* mcrxr */ 5197fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 5198fcf5ef2aSThomas Huth { 5199fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5200fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 5201fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5202fcf5ef2aSThomas Huth 5203fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 5204fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 5205fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 5206fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 5207fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 5208fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 5209fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 5210fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 5211fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5212fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5213fcf5ef2aSThomas Huth 5214fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 5215fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5216fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5217fcf5ef2aSThomas Huth } 5218fcf5ef2aSThomas Huth 5219b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 5220b63d0434SNikunj A Dadhania /* mcrxrx */ 5221b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 5222b63d0434SNikunj A Dadhania { 5223b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 5224b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 5225b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 5226b63d0434SNikunj A Dadhania 5227b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 5228b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 5229b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 5230b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 5231b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 5232b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 5233b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 5234b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 5235b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 5236b63d0434SNikunj A Dadhania tcg_temp_free(t0); 5237b63d0434SNikunj A Dadhania tcg_temp_free(t1); 5238b63d0434SNikunj A Dadhania } 5239b63d0434SNikunj A Dadhania #endif 5240b63d0434SNikunj A Dadhania 5241fcf5ef2aSThomas Huth /* mfcr mfocrf */ 5242fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 5243fcf5ef2aSThomas Huth { 5244fcf5ef2aSThomas Huth uint32_t crm, crn; 5245fcf5ef2aSThomas Huth 5246fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 5247fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5248fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 5249fcf5ef2aSThomas Huth crn = ctz32(crm); 5250fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 5251fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 5252fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 5253fcf5ef2aSThomas Huth } 5254fcf5ef2aSThomas Huth } else { 5255fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5256fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 5257fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5258fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 5259fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5260fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 5261fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5262fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 5263fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5264fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 5265fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5266fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 5267fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5268fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 5269fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 5270fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 5271fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5272fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5273fcf5ef2aSThomas Huth } 5274fcf5ef2aSThomas Huth } 5275fcf5ef2aSThomas Huth 5276fcf5ef2aSThomas Huth /* mfmsr */ 5277fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 5278fcf5ef2aSThomas Huth { 5279fcf5ef2aSThomas Huth CHK_SV; 5280fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 5281fcf5ef2aSThomas Huth } 5282fcf5ef2aSThomas Huth 5283fcf5ef2aSThomas Huth /* mfspr */ 5284fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 5285fcf5ef2aSThomas Huth { 5286fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 5287fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5288fcf5ef2aSThomas Huth 5289fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5290fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5291fcf5ef2aSThomas Huth #else 5292fcf5ef2aSThomas Huth if (ctx->pr) { 5293fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 5294fcf5ef2aSThomas Huth } else if (ctx->hv) { 5295fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 5296fcf5ef2aSThomas Huth } else { 5297fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 5298fcf5ef2aSThomas Huth } 5299fcf5ef2aSThomas Huth #endif 5300fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 5301fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 5302fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 5303fcf5ef2aSThomas Huth } else { 5304fcf5ef2aSThomas Huth /* Privilege exception */ 5305efe843d8SDavid Gibson /* 5306efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 5307fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 5308fcf5ef2aSThomas Huth * allowing userland application to read the PVR 5309fcf5ef2aSThomas Huth */ 5310fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 531131085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 531231085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 53132c2bcb1bSRichard Henderson ctx->cia); 5314fcf5ef2aSThomas Huth } 5315fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5316fcf5ef2aSThomas Huth } 5317fcf5ef2aSThomas Huth } else { 5318fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5319fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5320fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5321fcf5ef2aSThomas Huth /* This is a nop */ 5322fcf5ef2aSThomas Huth return; 5323fcf5ef2aSThomas Huth } 5324fcf5ef2aSThomas Huth /* Not defined */ 532531085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 532631085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 53272c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5328fcf5ef2aSThomas Huth 5329efe843d8SDavid Gibson /* 5330efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5331efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5332fcf5ef2aSThomas Huth */ 5333fcf5ef2aSThomas Huth if (sprn & 0x10) { 5334fcf5ef2aSThomas Huth if (ctx->pr) { 5335fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5336fcf5ef2aSThomas Huth } 5337fcf5ef2aSThomas Huth } else { 5338fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 5339fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5340fcf5ef2aSThomas Huth } 5341fcf5ef2aSThomas Huth } 5342fcf5ef2aSThomas Huth } 5343fcf5ef2aSThomas Huth } 5344fcf5ef2aSThomas Huth 5345fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 5346fcf5ef2aSThomas Huth { 5347fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5348fcf5ef2aSThomas Huth } 5349fcf5ef2aSThomas Huth 5350fcf5ef2aSThomas Huth /* mftb */ 5351fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 5352fcf5ef2aSThomas Huth { 5353fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 5354fcf5ef2aSThomas Huth } 5355fcf5ef2aSThomas Huth 5356fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 5357fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 5358fcf5ef2aSThomas Huth { 5359fcf5ef2aSThomas Huth uint32_t crm, crn; 5360fcf5ef2aSThomas Huth 5361fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 5362fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 5363fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 5364fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5365fcf5ef2aSThomas Huth crn = ctz32(crm); 5366fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5367fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 5368fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 5369fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5370fcf5ef2aSThomas Huth } 5371fcf5ef2aSThomas Huth } else { 5372fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 5373fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 5374fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 5375fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 5376fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 5377fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 5378fcf5ef2aSThomas Huth } 5379fcf5ef2aSThomas Huth } 5380fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 5381fcf5ef2aSThomas Huth } 5382fcf5ef2aSThomas Huth } 5383fcf5ef2aSThomas Huth 5384fcf5ef2aSThomas Huth /* mtmsr */ 5385fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5386fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 5387fcf5ef2aSThomas Huth { 5388fcf5ef2aSThomas Huth CHK_SV; 5389fcf5ef2aSThomas Huth 5390fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 53915ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 53925ed19506SNicholas Piggin gen_io_start(); 53935ed19506SNicholas Piggin } 5394fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 53955ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5396fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 53975ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5398efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5399efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54005ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5401efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54025ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54035ed19506SNicholas Piggin 54045ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5405fcf5ef2aSThomas Huth tcg_temp_free(t0); 54065ed19506SNicholas Piggin tcg_temp_free(t1); 54075ed19506SNicholas Piggin 5408fcf5ef2aSThomas Huth } else { 5409efe843d8SDavid Gibson /* 5410efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5411efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5412efe843d8SDavid Gibson * ppc_store_msr 5413fcf5ef2aSThomas Huth */ 5414b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5415fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 5416fcf5ef2aSThomas Huth } 54175ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54185ed19506SNicholas Piggin gen_stop_exception(ctx); 5419fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 5420fcf5ef2aSThomas Huth } 5421fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5422fcf5ef2aSThomas Huth 5423fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 5424fcf5ef2aSThomas Huth { 5425fcf5ef2aSThomas Huth CHK_SV; 5426fcf5ef2aSThomas Huth 5427fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 54285ed19506SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 54295ed19506SNicholas Piggin gen_io_start(); 54305ed19506SNicholas Piggin } 5431fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 54325ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 5433fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 54345ed19506SNicholas Piggin TCGv t1 = tcg_temp_new(); 5435efe843d8SDavid Gibson tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], 5436efe843d8SDavid Gibson (1 << MSR_RI) | (1 << MSR_EE)); 54375ed19506SNicholas Piggin tcg_gen_andi_tl(t1, cpu_msr, 5438efe843d8SDavid Gibson ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 54395ed19506SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 54405ed19506SNicholas Piggin 54415ed19506SNicholas Piggin gen_helper_store_msr(cpu_env, t1); 5442fcf5ef2aSThomas Huth tcg_temp_free(t0); 54435ed19506SNicholas Piggin tcg_temp_free(t1); 54445ed19506SNicholas Piggin 5445fcf5ef2aSThomas Huth } else { 5446fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 5447fcf5ef2aSThomas Huth 5448efe843d8SDavid Gibson /* 5449efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 5450efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 5451efe843d8SDavid Gibson * ppc_store_msr 5452fcf5ef2aSThomas Huth */ 5453b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 5454fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5455fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 5456fcf5ef2aSThomas Huth #else 5457fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 5458fcf5ef2aSThomas Huth #endif 5459fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 5460fcf5ef2aSThomas Huth tcg_temp_free(msr); 5461fcf5ef2aSThomas Huth } 54625ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 54635ed19506SNicholas Piggin gen_stop_exception(ctx); 5464fcf5ef2aSThomas Huth #endif 5465fcf5ef2aSThomas Huth } 5466fcf5ef2aSThomas Huth 5467fcf5ef2aSThomas Huth /* mtspr */ 5468fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 5469fcf5ef2aSThomas Huth { 5470fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 5471fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 5472fcf5ef2aSThomas Huth 5473fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5474fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5475fcf5ef2aSThomas Huth #else 5476fcf5ef2aSThomas Huth if (ctx->pr) { 5477fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 5478fcf5ef2aSThomas Huth } else if (ctx->hv) { 5479fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 5480fcf5ef2aSThomas Huth } else { 5481fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 5482fcf5ef2aSThomas Huth } 5483fcf5ef2aSThomas Huth #endif 5484fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 5485fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 5486fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 5487fcf5ef2aSThomas Huth } else { 5488fcf5ef2aSThomas Huth /* Privilege exception */ 548931085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 549031085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 54912c2bcb1bSRichard Henderson ctx->cia); 5492fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 5493fcf5ef2aSThomas Huth } 5494fcf5ef2aSThomas Huth } else { 5495fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 5496fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 5497fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 5498fcf5ef2aSThomas Huth /* This is a nop */ 5499fcf5ef2aSThomas Huth return; 5500fcf5ef2aSThomas Huth } 5501fcf5ef2aSThomas Huth 5502fcf5ef2aSThomas Huth /* Not defined */ 550331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 550431085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 55052c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 5506fcf5ef2aSThomas Huth 5507fcf5ef2aSThomas Huth 5508efe843d8SDavid Gibson /* 5509efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 5510efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 5511fcf5ef2aSThomas Huth */ 5512fcf5ef2aSThomas Huth if (sprn & 0x10) { 5513fcf5ef2aSThomas Huth if (ctx->pr) { 5514fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5515fcf5ef2aSThomas Huth } 5516fcf5ef2aSThomas Huth } else { 5517fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5518fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5519fcf5ef2aSThomas Huth } 5520fcf5ef2aSThomas Huth } 5521fcf5ef2aSThomas Huth } 5522fcf5ef2aSThomas Huth } 5523fcf5ef2aSThomas Huth 5524fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5525fcf5ef2aSThomas Huth /* setb */ 5526fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5527fcf5ef2aSThomas Huth { 5528fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 5529fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 5530fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 5531fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5532fcf5ef2aSThomas Huth 5533fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5534fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 5535fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 5536fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5537fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5538fcf5ef2aSThomas Huth 5539fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5540fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 5541fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 5542fcf5ef2aSThomas Huth } 5543fcf5ef2aSThomas Huth #endif 5544fcf5ef2aSThomas Huth 5545fcf5ef2aSThomas Huth /*** Cache management ***/ 5546fcf5ef2aSThomas Huth 5547fcf5ef2aSThomas Huth /* dcbf */ 5548fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5549fcf5ef2aSThomas Huth { 5550fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5551fcf5ef2aSThomas Huth TCGv t0; 5552fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5553fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5554fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5555fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5556fcf5ef2aSThomas Huth tcg_temp_free(t0); 5557fcf5ef2aSThomas Huth } 5558fcf5ef2aSThomas Huth 555950728199SRoman Kapl /* dcbfep (external PID dcbf) */ 556050728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 556150728199SRoman Kapl { 556250728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 556350728199SRoman Kapl TCGv t0; 556450728199SRoman Kapl CHK_SV; 556550728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 556650728199SRoman Kapl t0 = tcg_temp_new(); 556750728199SRoman Kapl gen_addr_reg_index(ctx, t0); 556850728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 556950728199SRoman Kapl tcg_temp_free(t0); 557050728199SRoman Kapl } 557150728199SRoman Kapl 5572fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5573fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5574fcf5ef2aSThomas Huth { 5575fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5576fcf5ef2aSThomas Huth GEN_PRIV; 5577fcf5ef2aSThomas Huth #else 5578fcf5ef2aSThomas Huth TCGv EA, val; 5579fcf5ef2aSThomas Huth 5580fcf5ef2aSThomas Huth CHK_SV; 5581fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5582fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5583fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5584fcf5ef2aSThomas Huth val = tcg_temp_new(); 5585fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5586fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5587fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5588fcf5ef2aSThomas Huth tcg_temp_free(val); 5589fcf5ef2aSThomas Huth tcg_temp_free(EA); 5590fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5591fcf5ef2aSThomas Huth } 5592fcf5ef2aSThomas Huth 5593fcf5ef2aSThomas Huth /* dcdst */ 5594fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5595fcf5ef2aSThomas Huth { 5596fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5597fcf5ef2aSThomas Huth TCGv t0; 5598fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5599fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5600fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5601fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5602fcf5ef2aSThomas Huth tcg_temp_free(t0); 5603fcf5ef2aSThomas Huth } 5604fcf5ef2aSThomas Huth 560550728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 560650728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 560750728199SRoman Kapl { 560850728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 560950728199SRoman Kapl TCGv t0; 561050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 561150728199SRoman Kapl t0 = tcg_temp_new(); 561250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 561350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 561450728199SRoman Kapl tcg_temp_free(t0); 561550728199SRoman Kapl } 561650728199SRoman Kapl 5617fcf5ef2aSThomas Huth /* dcbt */ 5618fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5619fcf5ef2aSThomas Huth { 5620efe843d8SDavid Gibson /* 5621efe843d8SDavid Gibson * interpreted as no-op 5622efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5623efe843d8SDavid Gibson * does not generate any exception 5624fcf5ef2aSThomas Huth */ 5625fcf5ef2aSThomas Huth } 5626fcf5ef2aSThomas Huth 562750728199SRoman Kapl /* dcbtep */ 562850728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 562950728199SRoman Kapl { 5630efe843d8SDavid Gibson /* 5631efe843d8SDavid Gibson * interpreted as no-op 5632efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5633efe843d8SDavid Gibson * does not generate any exception 563450728199SRoman Kapl */ 563550728199SRoman Kapl } 563650728199SRoman Kapl 5637fcf5ef2aSThomas Huth /* dcbtst */ 5638fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5639fcf5ef2aSThomas Huth { 5640efe843d8SDavid Gibson /* 5641efe843d8SDavid Gibson * interpreted as no-op 5642efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5643efe843d8SDavid Gibson * does not generate any exception 5644fcf5ef2aSThomas Huth */ 5645fcf5ef2aSThomas Huth } 5646fcf5ef2aSThomas Huth 564750728199SRoman Kapl /* dcbtstep */ 564850728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 564950728199SRoman Kapl { 5650efe843d8SDavid Gibson /* 5651efe843d8SDavid Gibson * interpreted as no-op 5652efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5653efe843d8SDavid Gibson * does not generate any exception 565450728199SRoman Kapl */ 565550728199SRoman Kapl } 565650728199SRoman Kapl 5657fcf5ef2aSThomas Huth /* dcbtls */ 5658fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5659fcf5ef2aSThomas Huth { 5660fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5661fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5662fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5663fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5664fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5665fcf5ef2aSThomas Huth tcg_temp_free(t0); 5666fcf5ef2aSThomas Huth } 5667fcf5ef2aSThomas Huth 5668fcf5ef2aSThomas Huth /* dcbz */ 5669fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5670fcf5ef2aSThomas Huth { 5671fcf5ef2aSThomas Huth TCGv tcgv_addr; 5672fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5673fcf5ef2aSThomas Huth 5674fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5675fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5676fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5677fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5678fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5679fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5680fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5681fcf5ef2aSThomas Huth } 5682fcf5ef2aSThomas Huth 568350728199SRoman Kapl /* dcbzep */ 568450728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 568550728199SRoman Kapl { 568650728199SRoman Kapl TCGv tcgv_addr; 568750728199SRoman Kapl TCGv_i32 tcgv_op; 568850728199SRoman Kapl 568950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 569050728199SRoman Kapl tcgv_addr = tcg_temp_new(); 569150728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 569250728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 569350728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 569450728199SRoman Kapl tcg_temp_free(tcgv_addr); 569550728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 569650728199SRoman Kapl } 569750728199SRoman Kapl 5698fcf5ef2aSThomas Huth /* dst / dstt */ 5699fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5700fcf5ef2aSThomas Huth { 5701fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5702fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5703fcf5ef2aSThomas Huth } else { 5704fcf5ef2aSThomas Huth /* interpreted as no-op */ 5705fcf5ef2aSThomas Huth } 5706fcf5ef2aSThomas Huth } 5707fcf5ef2aSThomas Huth 5708fcf5ef2aSThomas Huth /* dstst /dststt */ 5709fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5710fcf5ef2aSThomas Huth { 5711fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5712fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5713fcf5ef2aSThomas Huth } else { 5714fcf5ef2aSThomas Huth /* interpreted as no-op */ 5715fcf5ef2aSThomas Huth } 5716fcf5ef2aSThomas Huth 5717fcf5ef2aSThomas Huth } 5718fcf5ef2aSThomas Huth 5719fcf5ef2aSThomas Huth /* dss / dssall */ 5720fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5721fcf5ef2aSThomas Huth { 5722fcf5ef2aSThomas Huth /* interpreted as no-op */ 5723fcf5ef2aSThomas Huth } 5724fcf5ef2aSThomas Huth 5725fcf5ef2aSThomas Huth /* icbi */ 5726fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5727fcf5ef2aSThomas Huth { 5728fcf5ef2aSThomas Huth TCGv t0; 5729fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5730fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5731fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5732fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5733fcf5ef2aSThomas Huth tcg_temp_free(t0); 5734fcf5ef2aSThomas Huth } 5735fcf5ef2aSThomas Huth 573650728199SRoman Kapl /* icbiep */ 573750728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 573850728199SRoman Kapl { 573950728199SRoman Kapl TCGv t0; 574050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 574150728199SRoman Kapl t0 = tcg_temp_new(); 574250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 574350728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 574450728199SRoman Kapl tcg_temp_free(t0); 574550728199SRoman Kapl } 574650728199SRoman Kapl 5747fcf5ef2aSThomas Huth /* Optional: */ 5748fcf5ef2aSThomas Huth /* dcba */ 5749fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5750fcf5ef2aSThomas Huth { 5751efe843d8SDavid Gibson /* 5752efe843d8SDavid Gibson * interpreted as no-op 5753efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5754fcf5ef2aSThomas Huth * but does not generate any exception 5755fcf5ef2aSThomas Huth */ 5756fcf5ef2aSThomas Huth } 5757fcf5ef2aSThomas Huth 5758fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5759fcf5ef2aSThomas Huth /* Supervisor only: */ 5760fcf5ef2aSThomas Huth 5761fcf5ef2aSThomas Huth /* mfsr */ 5762fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5763fcf5ef2aSThomas Huth { 5764fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5765fcf5ef2aSThomas Huth GEN_PRIV; 5766fcf5ef2aSThomas Huth #else 5767fcf5ef2aSThomas Huth TCGv t0; 5768fcf5ef2aSThomas Huth 5769fcf5ef2aSThomas Huth CHK_SV; 5770fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5771fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5772fcf5ef2aSThomas Huth tcg_temp_free(t0); 5773fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5774fcf5ef2aSThomas Huth } 5775fcf5ef2aSThomas Huth 5776fcf5ef2aSThomas Huth /* mfsrin */ 5777fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5778fcf5ef2aSThomas Huth { 5779fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5780fcf5ef2aSThomas Huth GEN_PRIV; 5781fcf5ef2aSThomas Huth #else 5782fcf5ef2aSThomas Huth TCGv t0; 5783fcf5ef2aSThomas Huth 5784fcf5ef2aSThomas Huth CHK_SV; 5785fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5786e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5787fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5788fcf5ef2aSThomas Huth tcg_temp_free(t0); 5789fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5790fcf5ef2aSThomas Huth } 5791fcf5ef2aSThomas Huth 5792fcf5ef2aSThomas Huth /* mtsr */ 5793fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5794fcf5ef2aSThomas Huth { 5795fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5796fcf5ef2aSThomas Huth GEN_PRIV; 5797fcf5ef2aSThomas Huth #else 5798fcf5ef2aSThomas Huth TCGv t0; 5799fcf5ef2aSThomas Huth 5800fcf5ef2aSThomas Huth CHK_SV; 5801fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5802fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5803fcf5ef2aSThomas Huth tcg_temp_free(t0); 5804fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5805fcf5ef2aSThomas Huth } 5806fcf5ef2aSThomas Huth 5807fcf5ef2aSThomas Huth /* mtsrin */ 5808fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5809fcf5ef2aSThomas Huth { 5810fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5811fcf5ef2aSThomas Huth GEN_PRIV; 5812fcf5ef2aSThomas Huth #else 5813fcf5ef2aSThomas Huth TCGv t0; 5814fcf5ef2aSThomas Huth CHK_SV; 5815fcf5ef2aSThomas Huth 5816fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5817e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5818fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5819fcf5ef2aSThomas Huth tcg_temp_free(t0); 5820fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5821fcf5ef2aSThomas Huth } 5822fcf5ef2aSThomas Huth 5823fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5824fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5825fcf5ef2aSThomas Huth 5826fcf5ef2aSThomas Huth /* mfsr */ 5827fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5828fcf5ef2aSThomas Huth { 5829fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5830fcf5ef2aSThomas Huth GEN_PRIV; 5831fcf5ef2aSThomas Huth #else 5832fcf5ef2aSThomas Huth TCGv t0; 5833fcf5ef2aSThomas Huth 5834fcf5ef2aSThomas Huth CHK_SV; 5835fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5836fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5837fcf5ef2aSThomas Huth tcg_temp_free(t0); 5838fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5839fcf5ef2aSThomas Huth } 5840fcf5ef2aSThomas Huth 5841fcf5ef2aSThomas Huth /* mfsrin */ 5842fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5843fcf5ef2aSThomas Huth { 5844fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5845fcf5ef2aSThomas Huth GEN_PRIV; 5846fcf5ef2aSThomas Huth #else 5847fcf5ef2aSThomas Huth TCGv t0; 5848fcf5ef2aSThomas Huth 5849fcf5ef2aSThomas Huth CHK_SV; 5850fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5851e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5852fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5853fcf5ef2aSThomas Huth tcg_temp_free(t0); 5854fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5855fcf5ef2aSThomas Huth } 5856fcf5ef2aSThomas Huth 5857fcf5ef2aSThomas Huth /* mtsr */ 5858fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5859fcf5ef2aSThomas Huth { 5860fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5861fcf5ef2aSThomas Huth GEN_PRIV; 5862fcf5ef2aSThomas Huth #else 5863fcf5ef2aSThomas Huth TCGv t0; 5864fcf5ef2aSThomas Huth 5865fcf5ef2aSThomas Huth CHK_SV; 5866fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5867fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5868fcf5ef2aSThomas Huth tcg_temp_free(t0); 5869fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5870fcf5ef2aSThomas Huth } 5871fcf5ef2aSThomas Huth 5872fcf5ef2aSThomas Huth /* mtsrin */ 5873fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5874fcf5ef2aSThomas Huth { 5875fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5876fcf5ef2aSThomas Huth GEN_PRIV; 5877fcf5ef2aSThomas Huth #else 5878fcf5ef2aSThomas Huth TCGv t0; 5879fcf5ef2aSThomas Huth 5880fcf5ef2aSThomas Huth CHK_SV; 5881fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5882e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5883fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5884fcf5ef2aSThomas Huth tcg_temp_free(t0); 5885fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5886fcf5ef2aSThomas Huth } 5887fcf5ef2aSThomas Huth 5888fcf5ef2aSThomas Huth /* slbmte */ 5889fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5890fcf5ef2aSThomas Huth { 5891fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5892fcf5ef2aSThomas Huth GEN_PRIV; 5893fcf5ef2aSThomas Huth #else 5894fcf5ef2aSThomas Huth CHK_SV; 5895fcf5ef2aSThomas Huth 5896fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5897fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5898fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5899fcf5ef2aSThomas Huth } 5900fcf5ef2aSThomas Huth 5901fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5902fcf5ef2aSThomas Huth { 5903fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5904fcf5ef2aSThomas Huth GEN_PRIV; 5905fcf5ef2aSThomas Huth #else 5906fcf5ef2aSThomas Huth CHK_SV; 5907fcf5ef2aSThomas Huth 5908fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5909fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5910fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5911fcf5ef2aSThomas Huth } 5912fcf5ef2aSThomas Huth 5913fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5914fcf5ef2aSThomas Huth { 5915fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5916fcf5ef2aSThomas Huth GEN_PRIV; 5917fcf5ef2aSThomas Huth #else 5918fcf5ef2aSThomas Huth CHK_SV; 5919fcf5ef2aSThomas Huth 5920fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5921fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5922fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5923fcf5ef2aSThomas Huth } 5924fcf5ef2aSThomas Huth 5925fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5926fcf5ef2aSThomas Huth { 5927fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5928fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5929fcf5ef2aSThomas Huth #else 5930fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5931fcf5ef2aSThomas Huth 5932fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5933fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5934fcf5ef2aSThomas Huth return; 5935fcf5ef2aSThomas Huth } 5936fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5937fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5938fcf5ef2aSThomas Huth l1 = gen_new_label(); 5939fcf5ef2aSThomas Huth l2 = gen_new_label(); 5940fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5941fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5942efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5943fcf5ef2aSThomas Huth tcg_gen_br(l2); 5944fcf5ef2aSThomas Huth gen_set_label(l1); 5945fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5946fcf5ef2aSThomas Huth gen_set_label(l2); 5947fcf5ef2aSThomas Huth #endif 5948fcf5ef2aSThomas Huth } 5949fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5950fcf5ef2aSThomas Huth 5951fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5952fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5953fcf5ef2aSThomas Huth 5954fcf5ef2aSThomas Huth /* tlbia */ 5955fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5956fcf5ef2aSThomas Huth { 5957fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5958fcf5ef2aSThomas Huth GEN_PRIV; 5959fcf5ef2aSThomas Huth #else 5960fcf5ef2aSThomas Huth CHK_HV; 5961fcf5ef2aSThomas Huth 5962fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5963fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5964fcf5ef2aSThomas Huth } 5965fcf5ef2aSThomas Huth 5966fcf5ef2aSThomas Huth /* tlbiel */ 5967fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5968fcf5ef2aSThomas Huth { 5969fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5970fcf5ef2aSThomas Huth GEN_PRIV; 5971fcf5ef2aSThomas Huth #else 5972fcf5ef2aSThomas Huth CHK_SV; 5973fcf5ef2aSThomas Huth 5974fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5975fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5976fcf5ef2aSThomas Huth } 5977fcf5ef2aSThomas Huth 5978fcf5ef2aSThomas Huth /* tlbie */ 5979fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5980fcf5ef2aSThomas Huth { 5981fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5982fcf5ef2aSThomas Huth GEN_PRIV; 5983fcf5ef2aSThomas Huth #else 5984fcf5ef2aSThomas Huth TCGv_i32 t1; 5985c6fd28fdSSuraj Jitindar Singh 5986c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 598791c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 5988c6fd28fdSSuraj Jitindar Singh } else { 5989c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 5990c6fd28fdSSuraj Jitindar Singh } 5991fcf5ef2aSThomas Huth 5992fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5993fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5994fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5995fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5996fcf5ef2aSThomas Huth tcg_temp_free(t0); 5997fcf5ef2aSThomas Huth } else { 5998fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5999fcf5ef2aSThomas Huth } 6000fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 6001fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6002fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 6003fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 6004fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6005fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6006fcf5ef2aSThomas Huth } 6007fcf5ef2aSThomas Huth 6008fcf5ef2aSThomas Huth /* tlbsync */ 6009fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 6010fcf5ef2aSThomas Huth { 6011fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6012fcf5ef2aSThomas Huth GEN_PRIV; 6013fcf5ef2aSThomas Huth #else 601491c60f12SCédric Le Goater 601591c60f12SCédric Le Goater if (ctx->gtse) { 601691c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 601791c60f12SCédric Le Goater } else { 601891c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 601991c60f12SCédric Le Goater } 6020fcf5ef2aSThomas Huth 6021fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 6022fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 6023fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 6024fcf5ef2aSThomas Huth } 6025fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6026fcf5ef2aSThomas Huth } 6027fcf5ef2aSThomas Huth 6028fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6029fcf5ef2aSThomas Huth /* slbia */ 6030fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 6031fcf5ef2aSThomas Huth { 6032fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6033fcf5ef2aSThomas Huth GEN_PRIV; 6034fcf5ef2aSThomas Huth #else 60350418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 60360418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 60370418bf78SNicholas Piggin 6038fcf5ef2aSThomas Huth CHK_SV; 6039fcf5ef2aSThomas Huth 60400418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 60413119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 6042fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6043fcf5ef2aSThomas Huth } 6044fcf5ef2aSThomas Huth 6045fcf5ef2aSThomas Huth /* slbie */ 6046fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 6047fcf5ef2aSThomas Huth { 6048fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6049fcf5ef2aSThomas Huth GEN_PRIV; 6050fcf5ef2aSThomas Huth #else 6051fcf5ef2aSThomas Huth CHK_SV; 6052fcf5ef2aSThomas Huth 6053fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6054fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6055fcf5ef2aSThomas Huth } 6056a63f1dfcSNikunj A Dadhania 6057a63f1dfcSNikunj A Dadhania /* slbieg */ 6058a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 6059a63f1dfcSNikunj A Dadhania { 6060a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 6061a63f1dfcSNikunj A Dadhania GEN_PRIV; 6062a63f1dfcSNikunj A Dadhania #else 6063a63f1dfcSNikunj A Dadhania CHK_SV; 6064a63f1dfcSNikunj A Dadhania 6065a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6066a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 6067a63f1dfcSNikunj A Dadhania } 6068a63f1dfcSNikunj A Dadhania 606962d897caSNikunj A Dadhania /* slbsync */ 607062d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 607162d897caSNikunj A Dadhania { 607262d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 607362d897caSNikunj A Dadhania GEN_PRIV; 607462d897caSNikunj A Dadhania #else 607562d897caSNikunj A Dadhania CHK_SV; 607662d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 607762d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 607862d897caSNikunj A Dadhania } 607962d897caSNikunj A Dadhania 6080fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6081fcf5ef2aSThomas Huth 6082fcf5ef2aSThomas Huth /*** External control ***/ 6083fcf5ef2aSThomas Huth /* Optional: */ 6084fcf5ef2aSThomas Huth 6085fcf5ef2aSThomas Huth /* eciwx */ 6086fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 6087fcf5ef2aSThomas Huth { 6088fcf5ef2aSThomas Huth TCGv t0; 6089fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6090fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6091fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6092fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6093c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6094c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6095fcf5ef2aSThomas Huth tcg_temp_free(t0); 6096fcf5ef2aSThomas Huth } 6097fcf5ef2aSThomas Huth 6098fcf5ef2aSThomas Huth /* ecowx */ 6099fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 6100fcf5ef2aSThomas Huth { 6101fcf5ef2aSThomas Huth TCGv t0; 6102fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 6103fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 6104fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6105fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6106c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 6107c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 6108fcf5ef2aSThomas Huth tcg_temp_free(t0); 6109fcf5ef2aSThomas Huth } 6110fcf5ef2aSThomas Huth 6111fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 6112fcf5ef2aSThomas Huth 6113fcf5ef2aSThomas Huth /* abs - abs. */ 6114fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 6115fcf5ef2aSThomas Huth { 6116fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6117fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6118fe21b785SRichard Henderson 6119fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6120efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6121fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6122fcf5ef2aSThomas Huth } 6123efe843d8SDavid Gibson } 6124fcf5ef2aSThomas Huth 6125fcf5ef2aSThomas Huth /* abso - abso. */ 6126fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 6127fcf5ef2aSThomas Huth { 6128fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6129fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6130fe21b785SRichard Henderson 6131fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 6132fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6133fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 6134efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6135fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6136fcf5ef2aSThomas Huth } 6137efe843d8SDavid Gibson } 6138fcf5ef2aSThomas Huth 6139fcf5ef2aSThomas Huth /* clcs */ 6140fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 6141fcf5ef2aSThomas Huth { 6142fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 6143fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6144fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6145fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 6146fcf5ef2aSThomas Huth } 6147fcf5ef2aSThomas Huth 6148fcf5ef2aSThomas Huth /* div - div. */ 6149fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 6150fcf5ef2aSThomas Huth { 6151fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6152fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6153efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6154fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6155fcf5ef2aSThomas Huth } 6156efe843d8SDavid Gibson } 6157fcf5ef2aSThomas Huth 6158fcf5ef2aSThomas Huth /* divo - divo. */ 6159fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 6160fcf5ef2aSThomas Huth { 6161fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6162fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6163efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6164fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6165fcf5ef2aSThomas Huth } 6166efe843d8SDavid Gibson } 6167fcf5ef2aSThomas Huth 6168fcf5ef2aSThomas Huth /* divs - divs. */ 6169fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 6170fcf5ef2aSThomas Huth { 6171fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 6172fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6173efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6174fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6175fcf5ef2aSThomas Huth } 6176efe843d8SDavid Gibson } 6177fcf5ef2aSThomas Huth 6178fcf5ef2aSThomas Huth /* divso - divso. */ 6179fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 6180fcf5ef2aSThomas Huth { 6181fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 6182fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6183efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6184fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6185fcf5ef2aSThomas Huth } 6186efe843d8SDavid Gibson } 6187fcf5ef2aSThomas Huth 6188fcf5ef2aSThomas Huth /* doz - doz. */ 6189fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 6190fcf5ef2aSThomas Huth { 6191fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6192fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6193efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6194efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6195efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 6196efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 6197fcf5ef2aSThomas Huth tcg_gen_br(l2); 6198fcf5ef2aSThomas Huth gen_set_label(l1); 6199fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6200fcf5ef2aSThomas Huth gen_set_label(l2); 6201efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6202fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6203fcf5ef2aSThomas Huth } 6204efe843d8SDavid Gibson } 6205fcf5ef2aSThomas Huth 6206fcf5ef2aSThomas Huth /* dozo - dozo. */ 6207fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 6208fcf5ef2aSThomas Huth { 6209fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6210fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6211fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6212fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6213fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6214fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6215fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6216efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 6217efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 6218fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6219fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6220fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 6221fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6222fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 6223fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6224fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6225fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6226fcf5ef2aSThomas Huth tcg_gen_br(l2); 6227fcf5ef2aSThomas Huth gen_set_label(l1); 6228fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6229fcf5ef2aSThomas Huth gen_set_label(l2); 6230fcf5ef2aSThomas Huth tcg_temp_free(t0); 6231fcf5ef2aSThomas Huth tcg_temp_free(t1); 6232fcf5ef2aSThomas Huth tcg_temp_free(t2); 6233efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6234fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6235fcf5ef2aSThomas Huth } 6236efe843d8SDavid Gibson } 6237fcf5ef2aSThomas Huth 6238fcf5ef2aSThomas Huth /* dozi */ 6239fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 6240fcf5ef2aSThomas Huth { 6241fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 6242fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6243fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6244fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 6245fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 6246fcf5ef2aSThomas Huth tcg_gen_br(l2); 6247fcf5ef2aSThomas Huth gen_set_label(l1); 6248fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 6249fcf5ef2aSThomas Huth gen_set_label(l2); 6250efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6251fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6252fcf5ef2aSThomas Huth } 6253efe843d8SDavid Gibson } 6254fcf5ef2aSThomas Huth 6255fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 6256fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 6257fcf5ef2aSThomas Huth { 6258fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6259fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 6260fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 6261fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 6262fcf5ef2aSThomas Huth 6263fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6264fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 6265fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 6266fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 6267fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 6268fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 6269fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 6270efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6271fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 6272efe843d8SDavid Gibson } 6273fcf5ef2aSThomas Huth tcg_temp_free(t0); 6274fcf5ef2aSThomas Huth } 6275fcf5ef2aSThomas Huth 6276fcf5ef2aSThomas Huth /* maskg - maskg. */ 6277fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 6278fcf5ef2aSThomas Huth { 6279fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6280fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6281fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6282fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6283fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 6284fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 6285fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6286fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 6287fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 6288fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 6289fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 6290fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 6291fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 6292fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6293fcf5ef2aSThomas Huth gen_set_label(l1); 6294fcf5ef2aSThomas Huth tcg_temp_free(t0); 6295fcf5ef2aSThomas Huth tcg_temp_free(t1); 6296fcf5ef2aSThomas Huth tcg_temp_free(t2); 6297fcf5ef2aSThomas Huth tcg_temp_free(t3); 6298efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6299fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6300fcf5ef2aSThomas Huth } 6301efe843d8SDavid Gibson } 6302fcf5ef2aSThomas Huth 6303fcf5ef2aSThomas Huth /* maskir - maskir. */ 6304fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 6305fcf5ef2aSThomas Huth { 6306fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6307fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6308fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6309fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6310fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6311fcf5ef2aSThomas Huth tcg_temp_free(t0); 6312fcf5ef2aSThomas Huth tcg_temp_free(t1); 6313efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6314fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6315fcf5ef2aSThomas Huth } 6316efe843d8SDavid Gibson } 6317fcf5ef2aSThomas Huth 6318fcf5ef2aSThomas Huth /* mul - mul. */ 6319fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 6320fcf5ef2aSThomas Huth { 6321fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6322fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6323fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6324fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6325fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6326fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6327fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6328fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6329fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6330fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6331fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6332fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6333fcf5ef2aSThomas Huth tcg_temp_free(t2); 6334efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6335fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6336fcf5ef2aSThomas Huth } 6337efe843d8SDavid Gibson } 6338fcf5ef2aSThomas Huth 6339fcf5ef2aSThomas Huth /* mulo - mulo. */ 6340fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 6341fcf5ef2aSThomas Huth { 6342fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6343fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 6344fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6345fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6346fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6347fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6348fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 6349fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 6350fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 6351fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 6352fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 6353fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 6354fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 6355fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 6356fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 6357fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6358fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6359fcf5ef2aSThomas Huth gen_set_label(l1); 6360fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 6361fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6362fcf5ef2aSThomas Huth tcg_temp_free(t2); 6363efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6364fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 6365fcf5ef2aSThomas Huth } 6366efe843d8SDavid Gibson } 6367fcf5ef2aSThomas Huth 6368fcf5ef2aSThomas Huth /* nabs - nabs. */ 6369fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 6370fcf5ef2aSThomas Huth { 6371fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6372fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6373fe21b785SRichard Henderson 6374fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6375fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6376efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6377fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6378fcf5ef2aSThomas Huth } 6379efe843d8SDavid Gibson } 6380fcf5ef2aSThomas Huth 6381fcf5ef2aSThomas Huth /* nabso - nabso. */ 6382fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 6383fcf5ef2aSThomas Huth { 6384fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 6385fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 6386fe21b785SRichard Henderson 6387fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 6388fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 6389fcf5ef2aSThomas Huth /* nabs never overflows */ 6390fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6391efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6392fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 6393fcf5ef2aSThomas Huth } 6394efe843d8SDavid Gibson } 6395fcf5ef2aSThomas Huth 6396fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 6397fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 6398fcf5ef2aSThomas Huth { 6399fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 6400fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 6401fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6402fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6403fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6404fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 6405efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 6406efe843d8SDavid Gibson ~MASK(mb, me)); 6407fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 6408fcf5ef2aSThomas Huth tcg_temp_free(t0); 6409efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6410fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6411fcf5ef2aSThomas Huth } 6412efe843d8SDavid Gibson } 6413fcf5ef2aSThomas Huth 6414fcf5ef2aSThomas Huth /* rrib - rrib. */ 6415fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 6416fcf5ef2aSThomas Huth { 6417fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6418fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6419fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6420fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 6421fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6422fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6423fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6424fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 6425fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6426fcf5ef2aSThomas Huth tcg_temp_free(t0); 6427fcf5ef2aSThomas Huth tcg_temp_free(t1); 6428efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6429fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6430fcf5ef2aSThomas Huth } 6431efe843d8SDavid Gibson } 6432fcf5ef2aSThomas Huth 6433fcf5ef2aSThomas Huth /* sle - sle. */ 6434fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 6435fcf5ef2aSThomas Huth { 6436fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6437fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6438fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6439fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6440fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6441fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6442fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6443fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6444fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6445fcf5ef2aSThomas Huth tcg_temp_free(t0); 6446fcf5ef2aSThomas Huth tcg_temp_free(t1); 6447efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6448fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6449fcf5ef2aSThomas Huth } 6450efe843d8SDavid Gibson } 6451fcf5ef2aSThomas Huth 6452fcf5ef2aSThomas Huth /* sleq - sleq. */ 6453fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 6454fcf5ef2aSThomas Huth { 6455fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6456fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6457fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6458fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6459fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 6460fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 6461fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6462fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6463fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6464fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6465fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6466fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6467fcf5ef2aSThomas Huth tcg_temp_free(t0); 6468fcf5ef2aSThomas Huth tcg_temp_free(t1); 6469fcf5ef2aSThomas Huth tcg_temp_free(t2); 6470efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6471fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6472fcf5ef2aSThomas Huth } 6473efe843d8SDavid Gibson } 6474fcf5ef2aSThomas Huth 6475fcf5ef2aSThomas Huth /* sliq - sliq. */ 6476fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 6477fcf5ef2aSThomas Huth { 6478fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6479fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6480fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6481fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6482fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6483fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6484fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6485fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6486fcf5ef2aSThomas Huth tcg_temp_free(t0); 6487fcf5ef2aSThomas Huth tcg_temp_free(t1); 6488efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6489fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6490fcf5ef2aSThomas Huth } 6491efe843d8SDavid Gibson } 6492fcf5ef2aSThomas Huth 6493fcf5ef2aSThomas Huth /* slliq - slliq. */ 6494fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 6495fcf5ef2aSThomas Huth { 6496fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6497fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6498fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6499fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6500fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6501fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6502fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 6503fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 6504fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6505fcf5ef2aSThomas Huth tcg_temp_free(t0); 6506fcf5ef2aSThomas Huth tcg_temp_free(t1); 6507efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6508fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6509fcf5ef2aSThomas Huth } 6510efe843d8SDavid Gibson } 6511fcf5ef2aSThomas Huth 6512fcf5ef2aSThomas Huth /* sllq - sllq. */ 6513fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6514fcf5ef2aSThomas Huth { 6515fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6516fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6517fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6518fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6519fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6520fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6521fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6522fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6523fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6524fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6525fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6526fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6527fcf5ef2aSThomas Huth tcg_gen_br(l2); 6528fcf5ef2aSThomas Huth gen_set_label(l1); 6529fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6530fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6531fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6532fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6533fcf5ef2aSThomas Huth gen_set_label(l2); 6534fcf5ef2aSThomas Huth tcg_temp_free(t0); 6535fcf5ef2aSThomas Huth tcg_temp_free(t1); 6536fcf5ef2aSThomas Huth tcg_temp_free(t2); 6537efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6538fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6539fcf5ef2aSThomas Huth } 6540efe843d8SDavid Gibson } 6541fcf5ef2aSThomas Huth 6542fcf5ef2aSThomas Huth /* slq - slq. */ 6543fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6544fcf5ef2aSThomas Huth { 6545fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6546fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6547fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6548fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6549fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6550fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6551fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6552fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6553fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6554fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6555fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6556fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6557fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6558fcf5ef2aSThomas Huth gen_set_label(l1); 6559fcf5ef2aSThomas Huth tcg_temp_free(t0); 6560fcf5ef2aSThomas Huth tcg_temp_free(t1); 6561efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6562fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6563fcf5ef2aSThomas Huth } 6564efe843d8SDavid Gibson } 6565fcf5ef2aSThomas Huth 6566fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6567fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6568fcf5ef2aSThomas Huth { 6569fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6570fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6571fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6572fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6573fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6574fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6575fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6576fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6577fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6578fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6579fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6580fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6581fcf5ef2aSThomas Huth gen_set_label(l1); 6582fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6583fcf5ef2aSThomas Huth tcg_temp_free(t0); 6584fcf5ef2aSThomas Huth tcg_temp_free(t1); 6585efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6586fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6587fcf5ef2aSThomas Huth } 6588efe843d8SDavid Gibson } 6589fcf5ef2aSThomas Huth 6590fcf5ef2aSThomas Huth /* sraq - sraq. */ 6591fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6592fcf5ef2aSThomas Huth { 6593fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6594fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6595fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6596fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6597fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6598fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6599fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6600fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6601fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6602fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6603fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6604fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6605fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6606fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6607fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6608fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6609fcf5ef2aSThomas Huth gen_set_label(l1); 6610fcf5ef2aSThomas Huth tcg_temp_free(t0); 6611fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6612fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6613fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6614fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6615fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6616fcf5ef2aSThomas Huth gen_set_label(l2); 6617fcf5ef2aSThomas Huth tcg_temp_free(t1); 6618fcf5ef2aSThomas Huth tcg_temp_free(t2); 6619efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6620fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6621fcf5ef2aSThomas Huth } 6622efe843d8SDavid Gibson } 6623fcf5ef2aSThomas Huth 6624fcf5ef2aSThomas Huth /* sre - sre. */ 6625fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6626fcf5ef2aSThomas Huth { 6627fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6628fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6629fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6630fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6631fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6632fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6633fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6634fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6635fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6636fcf5ef2aSThomas Huth tcg_temp_free(t0); 6637fcf5ef2aSThomas Huth tcg_temp_free(t1); 6638efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6639fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6640fcf5ef2aSThomas Huth } 6641efe843d8SDavid Gibson } 6642fcf5ef2aSThomas Huth 6643fcf5ef2aSThomas Huth /* srea - srea. */ 6644fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6645fcf5ef2aSThomas Huth { 6646fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6647fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6648fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6649fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6650fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6651fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6652fcf5ef2aSThomas Huth tcg_temp_free(t0); 6653fcf5ef2aSThomas Huth tcg_temp_free(t1); 6654efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6655fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6656fcf5ef2aSThomas Huth } 6657efe843d8SDavid Gibson } 6658fcf5ef2aSThomas Huth 6659fcf5ef2aSThomas Huth /* sreq */ 6660fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6661fcf5ef2aSThomas Huth { 6662fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6663fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6664fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6665fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6666fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6667fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6668fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6669fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6670fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6671fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6672fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6673fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6674fcf5ef2aSThomas Huth tcg_temp_free(t0); 6675fcf5ef2aSThomas Huth tcg_temp_free(t1); 6676fcf5ef2aSThomas Huth tcg_temp_free(t2); 6677efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6678fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6679fcf5ef2aSThomas Huth } 6680efe843d8SDavid Gibson } 6681fcf5ef2aSThomas Huth 6682fcf5ef2aSThomas Huth /* sriq */ 6683fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6684fcf5ef2aSThomas Huth { 6685fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6686fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6687fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6688fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6689fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6690fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6691fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6692fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6693fcf5ef2aSThomas Huth tcg_temp_free(t0); 6694fcf5ef2aSThomas Huth tcg_temp_free(t1); 6695efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6696fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6697fcf5ef2aSThomas Huth } 6698efe843d8SDavid Gibson } 6699fcf5ef2aSThomas Huth 6700fcf5ef2aSThomas Huth /* srliq */ 6701fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6702fcf5ef2aSThomas Huth { 6703fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6704fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6705fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6706fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6707fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6708fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6709fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6710fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6711fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6712fcf5ef2aSThomas Huth tcg_temp_free(t0); 6713fcf5ef2aSThomas Huth tcg_temp_free(t1); 6714efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6715fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6716fcf5ef2aSThomas Huth } 6717efe843d8SDavid Gibson } 6718fcf5ef2aSThomas Huth 6719fcf5ef2aSThomas Huth /* srlq */ 6720fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6721fcf5ef2aSThomas Huth { 6722fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6723fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6724fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6725fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6726fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6727fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6728fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6729fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6730fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6731fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6732fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6733fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6734fcf5ef2aSThomas Huth tcg_gen_br(l2); 6735fcf5ef2aSThomas Huth gen_set_label(l1); 6736fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6737fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6738fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6739fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6740fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6741fcf5ef2aSThomas Huth gen_set_label(l2); 6742fcf5ef2aSThomas Huth tcg_temp_free(t0); 6743fcf5ef2aSThomas Huth tcg_temp_free(t1); 6744fcf5ef2aSThomas Huth tcg_temp_free(t2); 6745efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6746fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6747fcf5ef2aSThomas Huth } 6748efe843d8SDavid Gibson } 6749fcf5ef2aSThomas Huth 6750fcf5ef2aSThomas Huth /* srq */ 6751fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6752fcf5ef2aSThomas Huth { 6753fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6754fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6755fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6756fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6757fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6758fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6759fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6760fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6761fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6762fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6763fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6764fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6765fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6766fcf5ef2aSThomas Huth gen_set_label(l1); 6767fcf5ef2aSThomas Huth tcg_temp_free(t0); 6768fcf5ef2aSThomas Huth tcg_temp_free(t1); 6769efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6770fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6771fcf5ef2aSThomas Huth } 6772efe843d8SDavid Gibson } 6773fcf5ef2aSThomas Huth 6774fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6775fcf5ef2aSThomas Huth 6776fcf5ef2aSThomas Huth /* dsa */ 6777fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6778fcf5ef2aSThomas Huth { 6779fcf5ef2aSThomas Huth /* XXX: TODO */ 6780fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6781fcf5ef2aSThomas Huth } 6782fcf5ef2aSThomas Huth 6783fcf5ef2aSThomas Huth /* esa */ 6784fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6785fcf5ef2aSThomas Huth { 6786fcf5ef2aSThomas Huth /* XXX: TODO */ 6787fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6788fcf5ef2aSThomas Huth } 6789fcf5ef2aSThomas Huth 6790fcf5ef2aSThomas Huth /* mfrom */ 6791fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6792fcf5ef2aSThomas Huth { 6793fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6794fcf5ef2aSThomas Huth GEN_PRIV; 6795fcf5ef2aSThomas Huth #else 6796fcf5ef2aSThomas Huth CHK_SV; 6797fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6798fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6799fcf5ef2aSThomas Huth } 6800fcf5ef2aSThomas Huth 6801fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6802fcf5ef2aSThomas Huth 6803fcf5ef2aSThomas Huth /* tlbld */ 6804fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6805fcf5ef2aSThomas Huth { 6806fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6807fcf5ef2aSThomas Huth GEN_PRIV; 6808fcf5ef2aSThomas Huth #else 6809fcf5ef2aSThomas Huth CHK_SV; 6810fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6811fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6812fcf5ef2aSThomas Huth } 6813fcf5ef2aSThomas Huth 6814fcf5ef2aSThomas Huth /* tlbli */ 6815fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6816fcf5ef2aSThomas Huth { 6817fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6818fcf5ef2aSThomas Huth GEN_PRIV; 6819fcf5ef2aSThomas Huth #else 6820fcf5ef2aSThomas Huth CHK_SV; 6821fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6822fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6823fcf5ef2aSThomas Huth } 6824fcf5ef2aSThomas Huth 6825fcf5ef2aSThomas Huth /* 74xx TLB management */ 6826fcf5ef2aSThomas Huth 6827fcf5ef2aSThomas Huth /* tlbld */ 6828fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 6829fcf5ef2aSThomas Huth { 6830fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6831fcf5ef2aSThomas Huth GEN_PRIV; 6832fcf5ef2aSThomas Huth #else 6833fcf5ef2aSThomas Huth CHK_SV; 6834fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6835fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6836fcf5ef2aSThomas Huth } 6837fcf5ef2aSThomas Huth 6838fcf5ef2aSThomas Huth /* tlbli */ 6839fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 6840fcf5ef2aSThomas Huth { 6841fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6842fcf5ef2aSThomas Huth GEN_PRIV; 6843fcf5ef2aSThomas Huth #else 6844fcf5ef2aSThomas Huth CHK_SV; 6845fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6846fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6847fcf5ef2aSThomas Huth } 6848fcf5ef2aSThomas Huth 6849fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6850fcf5ef2aSThomas Huth 6851fcf5ef2aSThomas Huth /* clf */ 6852fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6853fcf5ef2aSThomas Huth { 6854fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6855fcf5ef2aSThomas Huth } 6856fcf5ef2aSThomas Huth 6857fcf5ef2aSThomas Huth /* cli */ 6858fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6859fcf5ef2aSThomas Huth { 6860fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6861fcf5ef2aSThomas Huth GEN_PRIV; 6862fcf5ef2aSThomas Huth #else 6863fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6864fcf5ef2aSThomas Huth CHK_SV; 6865fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6866fcf5ef2aSThomas Huth } 6867fcf5ef2aSThomas Huth 6868fcf5ef2aSThomas Huth /* dclst */ 6869fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6870fcf5ef2aSThomas Huth { 6871fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6872fcf5ef2aSThomas Huth } 6873fcf5ef2aSThomas Huth 6874fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6875fcf5ef2aSThomas Huth { 6876fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6877fcf5ef2aSThomas Huth GEN_PRIV; 6878fcf5ef2aSThomas Huth #else 6879fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6880fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6881fcf5ef2aSThomas Huth TCGv t0; 6882fcf5ef2aSThomas Huth 6883fcf5ef2aSThomas Huth CHK_SV; 6884fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6885fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6886e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6887fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6888fcf5ef2aSThomas Huth tcg_temp_free(t0); 6889efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6890fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6891efe843d8SDavid Gibson } 6892fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6893fcf5ef2aSThomas Huth } 6894fcf5ef2aSThomas Huth 6895fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6896fcf5ef2aSThomas Huth { 6897fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6898fcf5ef2aSThomas Huth GEN_PRIV; 6899fcf5ef2aSThomas Huth #else 6900fcf5ef2aSThomas Huth TCGv t0; 6901fcf5ef2aSThomas Huth 6902fcf5ef2aSThomas Huth CHK_SV; 6903fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6904fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6905fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6906fcf5ef2aSThomas Huth tcg_temp_free(t0); 6907fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6908fcf5ef2aSThomas Huth } 6909fcf5ef2aSThomas Huth 6910fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6911fcf5ef2aSThomas Huth { 6912fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6913fcf5ef2aSThomas Huth GEN_PRIV; 6914fcf5ef2aSThomas Huth #else 6915fcf5ef2aSThomas Huth CHK_SV; 6916fcf5ef2aSThomas Huth 6917fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 6918fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6919fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6920fcf5ef2aSThomas Huth } 6921fcf5ef2aSThomas Huth 6922fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6923fcf5ef2aSThomas Huth 6924fcf5ef2aSThomas Huth /* BookE specific instructions */ 6925fcf5ef2aSThomas Huth 6926fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6927fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6928fcf5ef2aSThomas Huth { 6929fcf5ef2aSThomas Huth /* XXX: TODO */ 6930fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6931fcf5ef2aSThomas Huth } 6932fcf5ef2aSThomas Huth 6933fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6934fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6935fcf5ef2aSThomas Huth { 6936fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6937fcf5ef2aSThomas Huth GEN_PRIV; 6938fcf5ef2aSThomas Huth #else 6939fcf5ef2aSThomas Huth TCGv t0; 6940fcf5ef2aSThomas Huth 6941fcf5ef2aSThomas Huth CHK_SV; 6942fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6943fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6944fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6945fcf5ef2aSThomas Huth tcg_temp_free(t0); 6946fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6947fcf5ef2aSThomas Huth } 6948fcf5ef2aSThomas Huth 6949fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6950fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6951fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6952fcf5ef2aSThomas Huth { 6953fcf5ef2aSThomas Huth TCGv t0, t1; 6954fcf5ef2aSThomas Huth 6955fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6956fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6957fcf5ef2aSThomas Huth 6958fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6959fcf5ef2aSThomas Huth case 0x05: 6960fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6961fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6962fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6963fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6964fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6965fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6966fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6967fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6968fcf5ef2aSThomas Huth break; 6969fcf5ef2aSThomas Huth case 0x04: 6970fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6971fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6972fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6973fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6974fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6975fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6976fcf5ef2aSThomas Huth break; 6977fcf5ef2aSThomas Huth case 0x01: 6978fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6979fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6980fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6981fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6982fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6983fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6984fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6985fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6986fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6987fcf5ef2aSThomas Huth break; 6988fcf5ef2aSThomas Huth case 0x00: 6989fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6990fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6991fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6992fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6993fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6994fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6995fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6996fcf5ef2aSThomas Huth break; 6997fcf5ef2aSThomas Huth case 0x0D: 6998fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6999fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 7000fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 7001fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 7002fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7003fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 7004fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 7005fcf5ef2aSThomas Huth break; 7006fcf5ef2aSThomas Huth case 0x0C: 7007fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 7008fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 7009fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7010fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 7011fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 7012fcf5ef2aSThomas Huth break; 7013fcf5ef2aSThomas Huth } 7014fcf5ef2aSThomas Huth if (opc2 & 0x04) { 7015fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 7016fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 7017fcf5ef2aSThomas Huth if (opc2 & 0x02) { 7018fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 7019fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 7020fcf5ef2aSThomas Huth } else { 7021fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 7022fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 7023fcf5ef2aSThomas Huth } 7024fcf5ef2aSThomas Huth 7025fcf5ef2aSThomas Huth if (opc3 & 0x12) { 7026fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 7027fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7028fcf5ef2aSThomas Huth 7029fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7030fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 7031fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 7032fcf5ef2aSThomas Huth } 7033fcf5ef2aSThomas Huth if (opc3 & 0x01) { 7034fcf5ef2aSThomas Huth /* Signed */ 7035fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 7036fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 7037fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 7038fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 7039fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7040fcf5ef2aSThomas Huth /* Saturate */ 7041fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 7042fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 7043fcf5ef2aSThomas Huth } 7044fcf5ef2aSThomas Huth } else { 7045fcf5ef2aSThomas Huth /* Unsigned */ 7046fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 7047fcf5ef2aSThomas Huth if (opc3 & 0x02) { 7048fcf5ef2aSThomas Huth /* Saturate */ 7049fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 7050fcf5ef2aSThomas Huth } 7051fcf5ef2aSThomas Huth } 7052fcf5ef2aSThomas Huth if (opc3 & 0x10) { 7053fcf5ef2aSThomas Huth /* Check overflow */ 7054fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 7055fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 7056fcf5ef2aSThomas Huth } 7057fcf5ef2aSThomas Huth gen_set_label(l1); 7058fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 7059fcf5ef2aSThomas Huth } 7060fcf5ef2aSThomas Huth } else { 7061fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 7062fcf5ef2aSThomas Huth } 7063fcf5ef2aSThomas Huth tcg_temp_free(t0); 7064fcf5ef2aSThomas Huth tcg_temp_free(t1); 7065fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 7066fcf5ef2aSThomas Huth /* Update Rc0 */ 7067fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 7068fcf5ef2aSThomas Huth } 7069fcf5ef2aSThomas Huth } 7070fcf5ef2aSThomas Huth 7071fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7072fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 7073fcf5ef2aSThomas Huth { \ 7074fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 7075fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 7076fcf5ef2aSThomas Huth } 7077fcf5ef2aSThomas Huth 7078fcf5ef2aSThomas Huth /* macchw - macchw. */ 7079fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 7080fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 7081fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 7082fcf5ef2aSThomas Huth /* macchws - macchws. */ 7083fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 7084fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 7085fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 7086fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 7087fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 7088fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 7089fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 7090fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 7091fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 7092fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 7093fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 7094fcf5ef2aSThomas Huth /* machhw - machhw. */ 7095fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 7096fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 7097fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 7098fcf5ef2aSThomas Huth /* machhws - machhws. */ 7099fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 7100fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 7101fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 7102fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 7103fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 7104fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 7105fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 7106fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 7107fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 7108fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 7109fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 7110fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 7111fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 7112fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 7113fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 7114fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 7115fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 7116fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 7117fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 7118fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 7119fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 7120fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 7121fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 7122fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 7123fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 7124fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 7125fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 7126fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 7127fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 7128fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 7129fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 7130fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 7131fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 7132fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 7133fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 7134fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 7135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 7136fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 7137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 7138fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 7139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 7140fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 7141fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 7142fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 7143fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 7144fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 7145fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 7146fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 7147fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 7148fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 7149fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 7150fcf5ef2aSThomas Huth 7151fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 7152fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 7153fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 7154fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 7155fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 7156fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 7157fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 7158fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 7159fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 7160fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 7161fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 7162fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 7163fcf5ef2aSThomas Huth 7164fcf5ef2aSThomas Huth /* mfdcr */ 7165fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 7166fcf5ef2aSThomas Huth { 7167fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7168fcf5ef2aSThomas Huth GEN_PRIV; 7169fcf5ef2aSThomas Huth #else 7170fcf5ef2aSThomas Huth TCGv dcrn; 7171fcf5ef2aSThomas Huth 7172fcf5ef2aSThomas Huth CHK_SV; 7173fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7174fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 7175fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7176fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7177fcf5ef2aSThomas Huth } 7178fcf5ef2aSThomas Huth 7179fcf5ef2aSThomas Huth /* mtdcr */ 7180fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 7181fcf5ef2aSThomas Huth { 7182fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7183fcf5ef2aSThomas Huth GEN_PRIV; 7184fcf5ef2aSThomas Huth #else 7185fcf5ef2aSThomas Huth TCGv dcrn; 7186fcf5ef2aSThomas Huth 7187fcf5ef2aSThomas Huth CHK_SV; 7188fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 7189fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 7190fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 7191fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7192fcf5ef2aSThomas Huth } 7193fcf5ef2aSThomas Huth 7194fcf5ef2aSThomas Huth /* mfdcrx */ 7195fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7196fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 7197fcf5ef2aSThomas Huth { 7198fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7199fcf5ef2aSThomas Huth GEN_PRIV; 7200fcf5ef2aSThomas Huth #else 7201fcf5ef2aSThomas Huth CHK_SV; 7202fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7203fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7204fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7205fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7206fcf5ef2aSThomas Huth } 7207fcf5ef2aSThomas Huth 7208fcf5ef2aSThomas Huth /* mtdcrx */ 7209fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7210fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 7211fcf5ef2aSThomas Huth { 7212fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7213fcf5ef2aSThomas Huth GEN_PRIV; 7214fcf5ef2aSThomas Huth #else 7215fcf5ef2aSThomas Huth CHK_SV; 7216fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7217fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7218fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7219fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7220fcf5ef2aSThomas Huth } 7221fcf5ef2aSThomas Huth 7222fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 7223fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 7224fcf5ef2aSThomas Huth { 7225fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 7226fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7227fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7228fcf5ef2aSThomas Huth } 7229fcf5ef2aSThomas Huth 7230fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 7231fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 7232fcf5ef2aSThomas Huth { 7233fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 7234fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7235fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 7236fcf5ef2aSThomas Huth } 7237fcf5ef2aSThomas Huth 7238fcf5ef2aSThomas Huth /* dccci */ 7239fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 7240fcf5ef2aSThomas Huth { 7241fcf5ef2aSThomas Huth CHK_SV; 7242fcf5ef2aSThomas Huth /* interpreted as no-op */ 7243fcf5ef2aSThomas Huth } 7244fcf5ef2aSThomas Huth 7245fcf5ef2aSThomas Huth /* dcread */ 7246fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 7247fcf5ef2aSThomas Huth { 7248fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7249fcf5ef2aSThomas Huth GEN_PRIV; 7250fcf5ef2aSThomas Huth #else 7251fcf5ef2aSThomas Huth TCGv EA, val; 7252fcf5ef2aSThomas Huth 7253fcf5ef2aSThomas Huth CHK_SV; 7254fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 7255fcf5ef2aSThomas Huth EA = tcg_temp_new(); 7256fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 7257fcf5ef2aSThomas Huth val = tcg_temp_new(); 7258fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 7259fcf5ef2aSThomas Huth tcg_temp_free(val); 7260fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 7261fcf5ef2aSThomas Huth tcg_temp_free(EA); 7262fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7263fcf5ef2aSThomas Huth } 7264fcf5ef2aSThomas Huth 7265fcf5ef2aSThomas Huth /* icbt */ 7266fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 7267fcf5ef2aSThomas Huth { 7268efe843d8SDavid Gibson /* 7269efe843d8SDavid Gibson * interpreted as no-op 7270efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7271efe843d8SDavid Gibson * does not generate any exception 7272fcf5ef2aSThomas Huth */ 7273fcf5ef2aSThomas Huth } 7274fcf5ef2aSThomas Huth 7275fcf5ef2aSThomas Huth /* iccci */ 7276fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 7277fcf5ef2aSThomas Huth { 7278fcf5ef2aSThomas Huth CHK_SV; 7279fcf5ef2aSThomas Huth /* interpreted as no-op */ 7280fcf5ef2aSThomas Huth } 7281fcf5ef2aSThomas Huth 7282fcf5ef2aSThomas Huth /* icread */ 7283fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 7284fcf5ef2aSThomas Huth { 7285fcf5ef2aSThomas Huth CHK_SV; 7286fcf5ef2aSThomas Huth /* interpreted as no-op */ 7287fcf5ef2aSThomas Huth } 7288fcf5ef2aSThomas Huth 7289fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 7290fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 7291fcf5ef2aSThomas Huth { 7292fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7293fcf5ef2aSThomas Huth GEN_PRIV; 7294fcf5ef2aSThomas Huth #else 7295fcf5ef2aSThomas Huth CHK_SV; 7296fcf5ef2aSThomas Huth /* Restore CPU state */ 7297fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 7298fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7299fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7300fcf5ef2aSThomas Huth } 7301fcf5ef2aSThomas Huth 7302fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 7303fcf5ef2aSThomas Huth { 7304fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7305fcf5ef2aSThomas Huth GEN_PRIV; 7306fcf5ef2aSThomas Huth #else 7307fcf5ef2aSThomas Huth CHK_SV; 7308fcf5ef2aSThomas Huth /* Restore CPU state */ 7309fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 7310fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7311fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7312fcf5ef2aSThomas Huth } 7313fcf5ef2aSThomas Huth 7314fcf5ef2aSThomas Huth /* BookE specific */ 7315fcf5ef2aSThomas Huth 7316fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7317fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 7318fcf5ef2aSThomas Huth { 7319fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7320fcf5ef2aSThomas Huth GEN_PRIV; 7321fcf5ef2aSThomas Huth #else 7322fcf5ef2aSThomas Huth CHK_SV; 7323fcf5ef2aSThomas Huth /* Restore CPU state */ 7324fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 7325fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7326fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7327fcf5ef2aSThomas Huth } 7328fcf5ef2aSThomas Huth 7329fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 7330fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 7331fcf5ef2aSThomas Huth { 7332fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7333fcf5ef2aSThomas Huth GEN_PRIV; 7334fcf5ef2aSThomas Huth #else 7335fcf5ef2aSThomas Huth CHK_SV; 7336fcf5ef2aSThomas Huth /* Restore CPU state */ 7337fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 7338fcf5ef2aSThomas Huth gen_sync_exception(ctx); 7339fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7340fcf5ef2aSThomas Huth } 7341fcf5ef2aSThomas Huth 7342fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 7343fcf5ef2aSThomas Huth 7344fcf5ef2aSThomas Huth /* tlbre */ 7345fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 7346fcf5ef2aSThomas Huth { 7347fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7348fcf5ef2aSThomas Huth GEN_PRIV; 7349fcf5ef2aSThomas Huth #else 7350fcf5ef2aSThomas Huth CHK_SV; 7351fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7352fcf5ef2aSThomas Huth case 0: 7353fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 7354fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7355fcf5ef2aSThomas Huth break; 7356fcf5ef2aSThomas Huth case 1: 7357fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 7358fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 7359fcf5ef2aSThomas Huth break; 7360fcf5ef2aSThomas Huth default: 7361fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7362fcf5ef2aSThomas Huth break; 7363fcf5ef2aSThomas Huth } 7364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7365fcf5ef2aSThomas Huth } 7366fcf5ef2aSThomas Huth 7367fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7368fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 7369fcf5ef2aSThomas Huth { 7370fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7371fcf5ef2aSThomas Huth GEN_PRIV; 7372fcf5ef2aSThomas Huth #else 7373fcf5ef2aSThomas Huth TCGv t0; 7374fcf5ef2aSThomas Huth 7375fcf5ef2aSThomas Huth CHK_SV; 7376fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7377fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7378fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7379fcf5ef2aSThomas Huth tcg_temp_free(t0); 7380fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7381fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7382fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7383fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7384fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7385fcf5ef2aSThomas Huth gen_set_label(l1); 7386fcf5ef2aSThomas Huth } 7387fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7388fcf5ef2aSThomas Huth } 7389fcf5ef2aSThomas Huth 7390fcf5ef2aSThomas Huth /* tlbwe */ 7391fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 7392fcf5ef2aSThomas Huth { 7393fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7394fcf5ef2aSThomas Huth GEN_PRIV; 7395fcf5ef2aSThomas Huth #else 7396fcf5ef2aSThomas Huth CHK_SV; 7397fcf5ef2aSThomas Huth 7398fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7399fcf5ef2aSThomas Huth case 0: 7400fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 7401fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7402fcf5ef2aSThomas Huth break; 7403fcf5ef2aSThomas Huth case 1: 7404fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 7405fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7406fcf5ef2aSThomas Huth break; 7407fcf5ef2aSThomas Huth default: 7408fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7409fcf5ef2aSThomas Huth break; 7410fcf5ef2aSThomas Huth } 7411fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7412fcf5ef2aSThomas Huth } 7413fcf5ef2aSThomas Huth 7414fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 7415fcf5ef2aSThomas Huth 7416fcf5ef2aSThomas Huth /* tlbre */ 7417fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 7418fcf5ef2aSThomas Huth { 7419fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7420fcf5ef2aSThomas Huth GEN_PRIV; 7421fcf5ef2aSThomas Huth #else 7422fcf5ef2aSThomas Huth CHK_SV; 7423fcf5ef2aSThomas Huth 7424fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7425fcf5ef2aSThomas Huth case 0: 7426fcf5ef2aSThomas Huth case 1: 7427fcf5ef2aSThomas Huth case 2: 7428fcf5ef2aSThomas Huth { 7429fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7430fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 7431fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 7432fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7433fcf5ef2aSThomas Huth } 7434fcf5ef2aSThomas Huth break; 7435fcf5ef2aSThomas Huth default: 7436fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7437fcf5ef2aSThomas Huth break; 7438fcf5ef2aSThomas Huth } 7439fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7440fcf5ef2aSThomas Huth } 7441fcf5ef2aSThomas Huth 7442fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7443fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 7444fcf5ef2aSThomas Huth { 7445fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7446fcf5ef2aSThomas Huth GEN_PRIV; 7447fcf5ef2aSThomas Huth #else 7448fcf5ef2aSThomas Huth TCGv t0; 7449fcf5ef2aSThomas Huth 7450fcf5ef2aSThomas Huth CHK_SV; 7451fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7452fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7453fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 7454fcf5ef2aSThomas Huth tcg_temp_free(t0); 7455fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7456fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 7457fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 7458fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 7459fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 7460fcf5ef2aSThomas Huth gen_set_label(l1); 7461fcf5ef2aSThomas Huth } 7462fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7463fcf5ef2aSThomas Huth } 7464fcf5ef2aSThomas Huth 7465fcf5ef2aSThomas Huth /* tlbwe */ 7466fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 7467fcf5ef2aSThomas Huth { 7468fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7469fcf5ef2aSThomas Huth GEN_PRIV; 7470fcf5ef2aSThomas Huth #else 7471fcf5ef2aSThomas Huth CHK_SV; 7472fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 7473fcf5ef2aSThomas Huth case 0: 7474fcf5ef2aSThomas Huth case 1: 7475fcf5ef2aSThomas Huth case 2: 7476fcf5ef2aSThomas Huth { 7477fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 7478fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 7479fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 7480fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7481fcf5ef2aSThomas Huth } 7482fcf5ef2aSThomas Huth break; 7483fcf5ef2aSThomas Huth default: 7484fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7485fcf5ef2aSThomas Huth break; 7486fcf5ef2aSThomas Huth } 7487fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7488fcf5ef2aSThomas Huth } 7489fcf5ef2aSThomas Huth 7490fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 7491fcf5ef2aSThomas Huth 7492fcf5ef2aSThomas Huth /* tlbre */ 7493fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 7494fcf5ef2aSThomas Huth { 7495fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7496fcf5ef2aSThomas Huth GEN_PRIV; 7497fcf5ef2aSThomas Huth #else 7498fcf5ef2aSThomas Huth CHK_SV; 7499fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 7500fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7501fcf5ef2aSThomas Huth } 7502fcf5ef2aSThomas Huth 7503fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 7504fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 7505fcf5ef2aSThomas Huth { 7506fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7507fcf5ef2aSThomas Huth GEN_PRIV; 7508fcf5ef2aSThomas Huth #else 7509fcf5ef2aSThomas Huth TCGv t0; 7510fcf5ef2aSThomas Huth 7511fcf5ef2aSThomas Huth CHK_SV; 7512fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 7513fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7514fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 7515fcf5ef2aSThomas Huth } else { 7516fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 7517fcf5ef2aSThomas Huth } 7518fcf5ef2aSThomas Huth 7519fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 7520fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 7521fcf5ef2aSThomas Huth tcg_temp_free(t0); 7522fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7523fcf5ef2aSThomas Huth } 7524fcf5ef2aSThomas Huth 7525fcf5ef2aSThomas Huth /* tlbwe */ 7526fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 7527fcf5ef2aSThomas Huth { 7528fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7529fcf5ef2aSThomas Huth GEN_PRIV; 7530fcf5ef2aSThomas Huth #else 7531fcf5ef2aSThomas Huth CHK_SV; 7532fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7533fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7534fcf5ef2aSThomas Huth } 7535fcf5ef2aSThomas Huth 7536fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7537fcf5ef2aSThomas Huth { 7538fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7539fcf5ef2aSThomas Huth GEN_PRIV; 7540fcf5ef2aSThomas Huth #else 7541fcf5ef2aSThomas Huth TCGv t0; 7542fcf5ef2aSThomas Huth 7543fcf5ef2aSThomas Huth CHK_SV; 7544fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7545fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7546fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7547fcf5ef2aSThomas Huth tcg_temp_free(t0); 7548fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7549fcf5ef2aSThomas Huth } 7550fcf5ef2aSThomas Huth 7551fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7552fcf5ef2aSThomas Huth { 7553fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7554fcf5ef2aSThomas Huth GEN_PRIV; 7555fcf5ef2aSThomas Huth #else 7556fcf5ef2aSThomas Huth TCGv t0; 7557fcf5ef2aSThomas Huth 7558fcf5ef2aSThomas Huth CHK_SV; 7559fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7560fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7561fcf5ef2aSThomas Huth 7562fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7563fcf5ef2aSThomas Huth case 0: 7564fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7565fcf5ef2aSThomas Huth break; 7566fcf5ef2aSThomas Huth case 1: 7567fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7568fcf5ef2aSThomas Huth break; 7569fcf5ef2aSThomas Huth case 3: 7570fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7571fcf5ef2aSThomas Huth break; 7572fcf5ef2aSThomas Huth default: 7573fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7574fcf5ef2aSThomas Huth break; 7575fcf5ef2aSThomas Huth } 7576fcf5ef2aSThomas Huth 7577fcf5ef2aSThomas Huth tcg_temp_free(t0); 7578fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7579fcf5ef2aSThomas Huth } 7580fcf5ef2aSThomas Huth 7581fcf5ef2aSThomas Huth 7582fcf5ef2aSThomas Huth /* wrtee */ 7583fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7584fcf5ef2aSThomas Huth { 7585fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7586fcf5ef2aSThomas Huth GEN_PRIV; 7587fcf5ef2aSThomas Huth #else 7588fcf5ef2aSThomas Huth TCGv t0; 7589fcf5ef2aSThomas Huth 7590fcf5ef2aSThomas Huth CHK_SV; 7591fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7592fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7593fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7594fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7595fcf5ef2aSThomas Huth tcg_temp_free(t0); 7596efe843d8SDavid Gibson /* 7597efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7598efe843d8SDavid Gibson * just set msr_ee to 1 7599fcf5ef2aSThomas Huth */ 7600fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7601fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7602fcf5ef2aSThomas Huth } 7603fcf5ef2aSThomas Huth 7604fcf5ef2aSThomas Huth /* wrteei */ 7605fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7606fcf5ef2aSThomas Huth { 7607fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7608fcf5ef2aSThomas Huth GEN_PRIV; 7609fcf5ef2aSThomas Huth #else 7610fcf5ef2aSThomas Huth CHK_SV; 7611fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7612fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7613fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7614fcf5ef2aSThomas Huth gen_stop_exception(ctx); 7615fcf5ef2aSThomas Huth } else { 7616fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7617fcf5ef2aSThomas Huth } 7618fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7619fcf5ef2aSThomas Huth } 7620fcf5ef2aSThomas Huth 7621fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7622fcf5ef2aSThomas Huth 7623fcf5ef2aSThomas Huth /* dlmzb */ 7624fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7625fcf5ef2aSThomas Huth { 7626fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7627fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7628fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7629fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7630fcf5ef2aSThomas Huth } 7631fcf5ef2aSThomas Huth 7632fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7633fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7634fcf5ef2aSThomas Huth { 7635fcf5ef2aSThomas Huth /* interpreted as no-op */ 7636fcf5ef2aSThomas Huth } 7637fcf5ef2aSThomas Huth 7638fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7639fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7640fcf5ef2aSThomas Huth { 764127a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 764227a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 764327a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 764427a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 764527a3ea7eSBALATON Zoltan } 764627a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7647fcf5ef2aSThomas Huth } 7648fcf5ef2aSThomas Huth 7649fcf5ef2aSThomas Huth /* icbt */ 7650fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7651fcf5ef2aSThomas Huth { 7652efe843d8SDavid Gibson /* 7653efe843d8SDavid Gibson * interpreted as no-op 7654efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7655efe843d8SDavid Gibson * does not generate any exception 7656fcf5ef2aSThomas Huth */ 7657fcf5ef2aSThomas Huth } 7658fcf5ef2aSThomas Huth 7659fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7660fcf5ef2aSThomas Huth 7661fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7662fcf5ef2aSThomas Huth { 7663fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7664fcf5ef2aSThomas Huth GEN_PRIV; 7665fcf5ef2aSThomas Huth #else 7666ebca5e6dSCédric Le Goater CHK_HV; 7667d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76687af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76697af1e7b0SCédric Le Goater } else { 7670fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76717af1e7b0SCédric Le Goater } 7672fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7673fcf5ef2aSThomas Huth } 7674fcf5ef2aSThomas Huth 7675fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7676fcf5ef2aSThomas Huth { 7677fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7678fcf5ef2aSThomas Huth GEN_PRIV; 7679fcf5ef2aSThomas Huth #else 7680ebca5e6dSCédric Le Goater CHK_HV; 7681d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 76827af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76837af1e7b0SCédric Le Goater } else { 7684fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 76857af1e7b0SCédric Le Goater } 7686fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7687fcf5ef2aSThomas Huth } 7688fcf5ef2aSThomas Huth 76895ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 76905ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 76915ba7ba1dSCédric Le Goater { 76925ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 76935ba7ba1dSCédric Le Goater GEN_PRIV; 76945ba7ba1dSCédric Le Goater #else 76955ba7ba1dSCédric Le Goater CHK_SV; 76965ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 76975ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 76985ba7ba1dSCédric Le Goater } 76995ba7ba1dSCédric Le Goater 77005ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 77015ba7ba1dSCédric Le Goater { 77025ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 77035ba7ba1dSCédric Le Goater GEN_PRIV; 77045ba7ba1dSCédric Le Goater #else 77055ba7ba1dSCédric Le Goater CHK_SV; 77065ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 77075ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77085ba7ba1dSCédric Le Goater } 77095ba7ba1dSCédric Le Goater #endif 77105ba7ba1dSCédric Le Goater 77117af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 77127af1e7b0SCédric Le Goater { 77137af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 77147af1e7b0SCédric Le Goater GEN_PRIV; 77157af1e7b0SCédric Le Goater #else 77167af1e7b0SCédric Le Goater CHK_HV; 77177af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 77187af1e7b0SCédric Le Goater /* interpreted as no-op */ 77197af1e7b0SCédric Le Goater } 7720fcf5ef2aSThomas Huth 7721fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7722fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7723fcf5ef2aSThomas Huth { 7724fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7725fcf5ef2aSThomas Huth 7726fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7727fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7728fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7729fcf5ef2aSThomas Huth } 7730fcf5ef2aSThomas Huth 7731fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7732fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7733fcf5ef2aSThomas Huth { 7734fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7735fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7736fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7737fcf5ef2aSThomas Huth 7738fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7739fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7740fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7741fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7742fcf5ef2aSThomas Huth } else { 7743fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7744fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7745fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7746fcf5ef2aSThomas Huth } 7747fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7748fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7749fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7750fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7751fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7752fcf5ef2aSThomas Huth } 7753fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7754fcf5ef2aSThomas Huth 7755fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7756fcf5ef2aSThomas Huth { 7757fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7758fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7759fcf5ef2aSThomas Huth return; 7760fcf5ef2aSThomas Huth } 7761fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7762fcf5ef2aSThomas Huth } 7763fcf5ef2aSThomas Huth 7764fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7765fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7766fcf5ef2aSThomas Huth { \ 7767fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7768fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7769fcf5ef2aSThomas Huth return; \ 7770fcf5ef2aSThomas Huth } \ 7771efe843d8SDavid Gibson /* \ 7772efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7773fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7774fcf5ef2aSThomas Huth * \ 7775fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7776fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7777fcf5ef2aSThomas Huth */ \ 7778fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7779fcf5ef2aSThomas Huth } 7780fcf5ef2aSThomas Huth 7781fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7782fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7783fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7784fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7785fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7786fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7787fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7788efe843d8SDavid Gibson 7789b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7790b8b4576eSSuraj Jitindar Singh { 7791efe843d8SDavid Gibson /* Do Nothing */ 7792b8b4576eSSuraj Jitindar Singh } 7793fcf5ef2aSThomas Huth 779480b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 779580b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 779680b8c1eeSNikunj A Dadhania { \ 7797efe843d8SDavid Gibson /* \ 7798efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7799efe843d8SDavid Gibson * implementation of the copy paste facility \ 780080b8c1eeSNikunj A Dadhania */ \ 780180b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 780280b8c1eeSNikunj A Dadhania } 780380b8c1eeSNikunj A Dadhania 780480b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 780580b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 780680b8c1eeSNikunj A Dadhania 7807fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7808fcf5ef2aSThomas Huth { 7809fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7810fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7811fcf5ef2aSThomas Huth return; 7812fcf5ef2aSThomas Huth } 7813efe843d8SDavid Gibson /* 7814efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7815efe843d8SDavid Gibson * simple: 7816fcf5ef2aSThomas Huth * 7817fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7818fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7819fcf5ef2aSThomas Huth */ 7820fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7821fcf5ef2aSThomas Huth } 7822fcf5ef2aSThomas Huth 7823fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7824fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7825fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7826fcf5ef2aSThomas Huth { \ 7827fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7828fcf5ef2aSThomas Huth } 7829fcf5ef2aSThomas Huth 7830fcf5ef2aSThomas Huth #else 7831fcf5ef2aSThomas Huth 7832fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7833fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7834fcf5ef2aSThomas Huth { \ 7835fcf5ef2aSThomas Huth CHK_SV; \ 7836fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7837fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7838fcf5ef2aSThomas Huth return; \ 7839fcf5ef2aSThomas Huth } \ 7840efe843d8SDavid Gibson /* \ 7841efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7842fcf5ef2aSThomas Huth * simple: \ 7843fcf5ef2aSThomas Huth * \ 7844fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7845fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7846fcf5ef2aSThomas Huth */ \ 7847fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7848fcf5ef2aSThomas Huth } 7849fcf5ef2aSThomas Huth 7850fcf5ef2aSThomas Huth #endif 7851fcf5ef2aSThomas Huth 7852fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7853fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7854fcf5ef2aSThomas Huth 78551a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 78561a404c91SMark Cave-Ayland { 7857e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 78581a404c91SMark Cave-Ayland } 78591a404c91SMark Cave-Ayland 78601a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 78611a404c91SMark Cave-Ayland { 7862e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 78631a404c91SMark Cave-Ayland } 78641a404c91SMark Cave-Ayland 7865c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7866c4a18dbfSMark Cave-Ayland { 786737da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7868c4a18dbfSMark Cave-Ayland } 7869c4a18dbfSMark Cave-Ayland 7870c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7871c4a18dbfSMark Cave-Ayland { 787237da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7873c4a18dbfSMark Cave-Ayland } 7874c4a18dbfSMark Cave-Ayland 7875139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7876fcf5ef2aSThomas Huth 7877139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7878fcf5ef2aSThomas Huth 7879139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7880fcf5ef2aSThomas Huth 7881139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7882fcf5ef2aSThomas Huth 7883139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7884fcf5ef2aSThomas Huth 78855cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 78865cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 78875cb091a4SNikunj A Dadhania { 78885cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 78895cb091a4SNikunj A Dadhania case 0: /* lfdp */ 78905cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 78915cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 78925cb091a4SNikunj A Dadhania } 78935cb091a4SNikunj A Dadhania break; 78945cb091a4SNikunj A Dadhania case 2: /* lxsd */ 78955cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 78965cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 78975cb091a4SNikunj A Dadhania } 78985cb091a4SNikunj A Dadhania break; 78995cb091a4SNikunj A Dadhania case 3: /* lxssp */ 79005cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 79015cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 79025cb091a4SNikunj A Dadhania } 79035cb091a4SNikunj A Dadhania break; 79045cb091a4SNikunj A Dadhania } 79055cb091a4SNikunj A Dadhania return gen_invalid(ctx); 79065cb091a4SNikunj A Dadhania } 79075cb091a4SNikunj A Dadhania 7908d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7909e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7910e3001664SNikunj A Dadhania { 7911e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 7912e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 7913e3001664SNikunj A Dadhania case 1: /* lxv */ 7914d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7915d59ba583SNikunj A Dadhania return gen_lxv(ctx); 7916d59ba583SNikunj A Dadhania } 7917e3001664SNikunj A Dadhania break; 7918e3001664SNikunj A Dadhania case 5: /* stxv */ 7919d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7920d59ba583SNikunj A Dadhania return gen_stxv(ctx); 7921d59ba583SNikunj A Dadhania } 7922e3001664SNikunj A Dadhania break; 7923e3001664SNikunj A Dadhania } 7924e3001664SNikunj A Dadhania } else { /* DS-FORM */ 7925e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7926e3001664SNikunj A Dadhania case 0: /* stfdp */ 7927e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7928e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7929e3001664SNikunj A Dadhania } 7930e3001664SNikunj A Dadhania break; 7931e3001664SNikunj A Dadhania case 2: /* stxsd */ 7932e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7933e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7934e3001664SNikunj A Dadhania } 7935e3001664SNikunj A Dadhania break; 7936e3001664SNikunj A Dadhania case 3: /* stxssp */ 7937e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7938e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7939e3001664SNikunj A Dadhania } 7940e3001664SNikunj A Dadhania break; 7941e3001664SNikunj A Dadhania } 7942e3001664SNikunj A Dadhania } 7943e3001664SNikunj A Dadhania return gen_invalid(ctx); 7944e3001664SNikunj A Dadhania } 7945e3001664SNikunj A Dadhania 79469d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79479d69cfa2SLijun Pan /* brd */ 79489d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 79499d69cfa2SLijun Pan { 79509d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79519d69cfa2SLijun Pan } 79529d69cfa2SLijun Pan 79539d69cfa2SLijun Pan /* brw */ 79549d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 79559d69cfa2SLijun Pan { 79569d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 79579d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 79589d69cfa2SLijun Pan 79599d69cfa2SLijun Pan } 79609d69cfa2SLijun Pan 79619d69cfa2SLijun Pan /* brh */ 79629d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 79639d69cfa2SLijun Pan { 79649d69cfa2SLijun Pan TCGv_i64 t0 = tcg_temp_new_i64(); 79659d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 79669d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 79679d69cfa2SLijun Pan 79689d69cfa2SLijun Pan tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); 79699d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 79709d69cfa2SLijun Pan tcg_gen_and_i64(t2, t1, t0); 79719d69cfa2SLijun Pan tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); 79729d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 79739d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 79749d69cfa2SLijun Pan 79759d69cfa2SLijun Pan tcg_temp_free_i64(t0); 79769d69cfa2SLijun Pan tcg_temp_free_i64(t1); 79779d69cfa2SLijun Pan tcg_temp_free_i64(t2); 79789d69cfa2SLijun Pan } 79799d69cfa2SLijun Pan #endif 79809d69cfa2SLijun Pan 7981fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 79829d69cfa2SLijun Pan #if defined(TARGET_PPC64) 79839d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 79849d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 79859d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 79869d69cfa2SLijun Pan #endif 7987fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7988fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 7989fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7990fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 7991fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 7992fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7993fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7994fcf5ef2aSThomas Huth #endif 7995fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7996fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7997fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7998fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7999fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8000fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8001fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8002fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 8003fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 8004fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 8005fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 8006fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 8007fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8008fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8009fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 8010fcf5ef2aSThomas Huth #endif 8011fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 8012fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 8013fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8014fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8015fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8016fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 8017fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 801880b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 8019b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 802080b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 8021fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 8022fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 8023fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8024fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8025fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8026fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8027fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 8028fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 8029fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 8030fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8031fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 8032fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 8033fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 8034fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 8035fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 8036fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 8037fcf5ef2aSThomas Huth #endif 8038fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8039fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8040fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8041fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 8042fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 8043fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 8044fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 8045fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8046fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 8047fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 8048fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 8049fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 8050fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 8051fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 8052fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8053fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 8054fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 8055fcf5ef2aSThomas Huth #endif 8056fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8057fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 8058fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 8059fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 8060fcf5ef2aSThomas Huth #endif 80615cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 80625cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8063d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 8064e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 8065fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8066fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 8067fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 8068fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 8069fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 8070fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 8071c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 8072fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 8073fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8074fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8075fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 8076a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 8077a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 8078fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8079fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 8080fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 8081fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8082a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 8083a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 8084fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 8085fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 8086fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 8087fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 8088fcf5ef2aSThomas Huth #endif 8089fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 8090fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 8091c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 8092fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8093fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8094fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 8095fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 8096fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 8097fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 8098fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 8099fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8100fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 81013c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 81023c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81033c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81043c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 81053c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 81063c89b8d6SNicholas Piggin #endif 8107cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8108fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8109fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8110fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8111fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 8112fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 8113fcf5ef2aSThomas Huth #endif 81143c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 81153c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 81163c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 8117fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 8118fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 8119fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8120fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 8121fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 8122fcf5ef2aSThomas Huth #endif 8123fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 8124fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 8125fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 8126fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 8127fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 8128fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 8129fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8130fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 8131fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 8132b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 8133fcf5ef2aSThomas Huth #endif 8134fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 8135fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 8136fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 813750728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8138fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 8139fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 814050728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8141fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 814250728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8143fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 814450728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 8145fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 8146fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 814750728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 8148fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 814999d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 8150fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 8151fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 815250728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 8153fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 8154fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 8155fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 8156fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 8157fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 8158fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8159fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 8160fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 8161fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8162fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 8163fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 8164fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 8165fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 8166fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 8167fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 8168fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 8169fcf5ef2aSThomas Huth #endif 8170fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 8171efe843d8SDavid Gibson /* 8172efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 8173efe843d8SDavid Gibson * different ISA versions 8174efe843d8SDavid Gibson */ 8175fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 8176fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 8177c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 8178c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 8179fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 8180fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8181fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 8182fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 8183a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 818462d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 8185fcf5ef2aSThomas Huth #endif 8186fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 8187fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 8188fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 8189fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 8190fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 8191fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 8192fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 8193fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 8194fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 8195fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 8196fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 8197fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8198fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 8199fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 8200fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 8201fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 8202fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 8203fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 8204fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 8205fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 8206fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 8207fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 8208fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 8209fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 8210fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 8211fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 8212fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 8213fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 8214fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 8215fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 8216fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 8217fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 8218fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 8219fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 8220fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 8221fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 8222fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 8223fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 8224fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 8225fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 8226fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 8227fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 8228fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 8229fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 8230fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 8231fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 8232fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 8233fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 8234fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 8235fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8236fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8237fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 8238fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 8239fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8240fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 8241fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 8242fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 8243fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 8244fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 8245fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 8246fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 8247fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 8248fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 8249fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 8250fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 8251fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 8252fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 8253fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 8254fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 8255fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 8256fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 8257fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 8258fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 8259fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 8260fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 8261fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 8262fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 8263fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 8264fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 8265fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 8266fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 8267fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8268fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 8269fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8270fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 8271fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8272fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 8273fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8274fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 8275fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 8276fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 8277fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 8278fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 8279fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 82807af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 82817af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 8282fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 8283fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 8284fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 8285fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 8286fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 828727a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 8288fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 8289fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 82900c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 82910c8d8c8bSBALATON Zoltan PPC_440_SPEC), 8292fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 8293fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 8294fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 8295fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 8296fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 8297fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8298fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 8299fcf5ef2aSThomas Huth PPC2_ISA300), 8300fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 83015ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 83025ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 83035ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 83045ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 8305fcf5ef2aSThomas Huth #endif 8306fcf5ef2aSThomas Huth 8307fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 8308fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 8309fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 8310fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 8311fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 8312fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8313fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 8314fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 8315fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 8316fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 8317fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 8318fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 8319fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 8320fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 8321fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 83224c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 8323fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 8324fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 8325fcf5ef2aSThomas Huth 8326fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 8327fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 8328fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 8329fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 8330fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 8331fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 8332fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 8333fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8334fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8335fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8336fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8337fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8338fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8339fcf5ef2aSThomas Huth 8340fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8341fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 8342fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 8343fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8344fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 8345fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 8346fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 8347fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 8348fcf5ef2aSThomas Huth 8349fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8350fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 8351fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8352fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 8353fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 8354fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 8355fcf5ef2aSThomas Huth 8356fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 8357fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 8358fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 8359fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 8360fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 8361fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 8362fcf5ef2aSThomas Huth #endif 8363fcf5ef2aSThomas Huth 8364fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 8365fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 8366fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 8367fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 8368fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 8369fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 8370fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 8371fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 8372fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 8373fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 8374fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 8375fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 8376fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 8377fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 8378fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 8379fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 8380fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 8381fcf5ef2aSThomas Huth 8382fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 8383fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 8384fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 8385fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 8386fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 8387fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 8388fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 8389fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 8390fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 8391fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 8392fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 8393fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 8394fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 8395fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 8396fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8397fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 8398fcf5ef2aSThomas Huth #endif 8399fcf5ef2aSThomas Huth 8400fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8401fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 8402fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 8403fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 8404fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8405fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8406fcf5ef2aSThomas Huth PPC_64B) 8407fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 8408fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 8409fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 8410fcf5ef2aSThomas Huth PPC_64B), \ 8411fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 8412fcf5ef2aSThomas Huth PPC_64B), \ 8413fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 8414fcf5ef2aSThomas Huth PPC_64B) 8415fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 8416fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 8417fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 8418fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 8419fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 8420fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 8421fcf5ef2aSThomas Huth #endif 8422fcf5ef2aSThomas Huth 8423fcf5ef2aSThomas Huth #undef GEN_LD 8424fcf5ef2aSThomas Huth #undef GEN_LDU 8425fcf5ef2aSThomas Huth #undef GEN_LDUX 8426fcf5ef2aSThomas Huth #undef GEN_LDX_E 8427fcf5ef2aSThomas Huth #undef GEN_LDS 8428fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 8429fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8430fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 8431fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 8432fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 8433fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8434fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 8435fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 8436fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 8437fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 8438fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 8439fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 8440fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 8441fcf5ef2aSThomas Huth 8442fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 8443fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 8444fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 8445fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 8446fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8447fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 8448fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 8449fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 8450fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 8451fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 8452fcf5ef2aSThomas Huth 8453fcf5ef2aSThomas Huth /* HV/P7 and later only */ 8454fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 8455fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 8456fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 8457fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 8458fcf5ef2aSThomas Huth #endif 8459fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 8460fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 8461fcf5ef2aSThomas Huth 846250728199SRoman Kapl /* External PID based load */ 846350728199SRoman Kapl #undef GEN_LDEPX 846450728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 846550728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 846650728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 846750728199SRoman Kapl 846850728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 846950728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 847050728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 847150728199SRoman Kapl #if defined(TARGET_PPC64) 847250728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 847350728199SRoman Kapl #endif 847450728199SRoman Kapl 8475fcf5ef2aSThomas Huth #undef GEN_ST 8476fcf5ef2aSThomas Huth #undef GEN_STU 8477fcf5ef2aSThomas Huth #undef GEN_STUX 8478fcf5ef2aSThomas Huth #undef GEN_STX_E 8479fcf5ef2aSThomas Huth #undef GEN_STS 8480fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 8481fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 8482fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 8483fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 8484fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 8485fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 8486fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 84870123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8488fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 8489fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 8490fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 8491fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 8492fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 8493fcf5ef2aSThomas Huth 8494fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 8495fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 8496fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 8497fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8498fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 8499fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 8500fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8501fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8502fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8503fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8504fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8505fcf5ef2aSThomas Huth #endif 8506fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8507fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8508fcf5ef2aSThomas Huth 850950728199SRoman Kapl #undef GEN_STEPX 851050728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 851150728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 851250728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 851350728199SRoman Kapl 851450728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 851550728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 851650728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 851750728199SRoman Kapl #if defined(TARGET_PPC64) 851850728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 851950728199SRoman Kapl #endif 852050728199SRoman Kapl 8521fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8522fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8523fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8524fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8525fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8526fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8527fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8528fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8529fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8530fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8531fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8532fcf5ef2aSThomas Huth 8533fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8534fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8535fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8536fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8537fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8538fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8539fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8540fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8541fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8542fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8543fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8544fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8545fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8546fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8547fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8549fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8551fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8553fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8555fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8557fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8559fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8561fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8563fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8565fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8567fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8569fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8571fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8573fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8575fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8577fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8578fcf5ef2aSThomas Huth 8579fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8580fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8581fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8582fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8583fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8584fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8585fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8586fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8587fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8588fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8589fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8590fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8591fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8592fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8593fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8594fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8595fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8596fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8597fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8598fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8599fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8600fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8601fcf5ef2aSThomas Huth 8602139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8603fcf5ef2aSThomas Huth 8604139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8605fcf5ef2aSThomas Huth 8606139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8607fcf5ef2aSThomas Huth 8608139c1837SPaolo Bonzini #include "translate/dfp-ops.c.inc" 8609fcf5ef2aSThomas Huth 8610139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8611fcf5ef2aSThomas Huth }; 8612fcf5ef2aSThomas Huth 86137468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 86147468e2c8SBruno Larsen (billionai) /* Opcode types */ 86157468e2c8SBruno Larsen (billionai) enum { 86167468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 86177468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 86187468e2c8SBruno Larsen (billionai) }; 86197468e2c8SBruno Larsen (billionai) 86207468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 86217468e2c8SBruno Larsen (billionai) 86227468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 86237468e2c8SBruno Larsen (billionai) { 86247468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 86257468e2c8SBruno Larsen (billionai) } 86267468e2c8SBruno Larsen (billionai) 86277468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 86287468e2c8SBruno Larsen (billionai) { 86297468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 86307468e2c8SBruno Larsen (billionai) } 86317468e2c8SBruno Larsen (billionai) 86327468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 86337468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 86347468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 86357468e2c8SBruno Larsen (billionai) { 86367468e2c8SBruno Larsen (billionai) int i; 86377468e2c8SBruno Larsen (billionai) 86387468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 86397468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 86407468e2c8SBruno Larsen (billionai) } 86417468e2c8SBruno Larsen (billionai) } 86427468e2c8SBruno Larsen (billionai) 86437468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 86447468e2c8SBruno Larsen (billionai) { 86457468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 86467468e2c8SBruno Larsen (billionai) 86477468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 86487468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 86497468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 86507468e2c8SBruno Larsen (billionai) 86517468e2c8SBruno Larsen (billionai) return 0; 86527468e2c8SBruno Larsen (billionai) } 86537468e2c8SBruno Larsen (billionai) 86547468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 86557468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86567468e2c8SBruno Larsen (billionai) { 86577468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 86587468e2c8SBruno Larsen (billionai) return -1; 86597468e2c8SBruno Larsen (billionai) } 86607468e2c8SBruno Larsen (billionai) table[idx] = handler; 86617468e2c8SBruno Larsen (billionai) 86627468e2c8SBruno Larsen (billionai) return 0; 86637468e2c8SBruno Larsen (billionai) } 86647468e2c8SBruno Larsen (billionai) 86657468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 86667468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 86677468e2c8SBruno Larsen (billionai) { 86687468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 86697468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 86707468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 86717468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 86727468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 86737468e2c8SBruno Larsen (billionai) ppc_opcodes[idx]->oname, handler->oname); 86747468e2c8SBruno Larsen (billionai) #endif 86757468e2c8SBruno Larsen (billionai) return -1; 86767468e2c8SBruno Larsen (billionai) } 86777468e2c8SBruno Larsen (billionai) 86787468e2c8SBruno Larsen (billionai) return 0; 86797468e2c8SBruno Larsen (billionai) } 86807468e2c8SBruno Larsen (billionai) 86817468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 86827468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 86837468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 86847468e2c8SBruno Larsen (billionai) { 86857468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 86867468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 86877468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 86887468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 86897468e2c8SBruno Larsen (billionai) return -1; 86907468e2c8SBruno Larsen (billionai) } 86917468e2c8SBruno Larsen (billionai) } else { 86927468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 86937468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 86947468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 86957468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 86967468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 86977468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 86987468e2c8SBruno Larsen (billionai) #endif 86997468e2c8SBruno Larsen (billionai) return -1; 87007468e2c8SBruno Larsen (billionai) } 87017468e2c8SBruno Larsen (billionai) } 87027468e2c8SBruno Larsen (billionai) if (handler != NULL && 87037468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 87047468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 87057468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 87067468e2c8SBruno Larsen (billionai) #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 87077468e2c8SBruno Larsen (billionai) printf(" Registered handler '%s' - new handler '%s'\n", 87087468e2c8SBruno Larsen (billionai) ind_table(table[idx1])[idx2]->oname, handler->oname); 87097468e2c8SBruno Larsen (billionai) #endif 87107468e2c8SBruno Larsen (billionai) return -1; 87117468e2c8SBruno Larsen (billionai) } 87127468e2c8SBruno Larsen (billionai) 87137468e2c8SBruno Larsen (billionai) return 0; 87147468e2c8SBruno Larsen (billionai) } 87157468e2c8SBruno Larsen (billionai) 87167468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 87177468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87187468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 87197468e2c8SBruno Larsen (billionai) { 87207468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 87217468e2c8SBruno Larsen (billionai) } 87227468e2c8SBruno Larsen (billionai) 87237468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 87247468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87257468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 87267468e2c8SBruno Larsen (billionai) { 87277468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 87287468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 87297468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 87307468e2c8SBruno Larsen (billionai) return -1; 87317468e2c8SBruno Larsen (billionai) } 87327468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 87337468e2c8SBruno Larsen (billionai) handler) < 0) { 87347468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 87357468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 87367468e2c8SBruno Larsen (billionai) return -1; 87377468e2c8SBruno Larsen (billionai) } 87387468e2c8SBruno Larsen (billionai) 87397468e2c8SBruno Larsen (billionai) return 0; 87407468e2c8SBruno Larsen (billionai) } 87417468e2c8SBruno Larsen (billionai) 87427468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 87437468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 87447468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 87457468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 87467468e2c8SBruno Larsen (billionai) { 87477468e2c8SBruno Larsen (billionai) opc_handler_t **table; 87487468e2c8SBruno Larsen (billionai) 87497468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 87507468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 87517468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 87527468e2c8SBruno Larsen (billionai) return -1; 87537468e2c8SBruno Larsen (billionai) } 87547468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 87557468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 87567468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 87577468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 87587468e2c8SBruno Larsen (billionai) return -1; 87597468e2c8SBruno Larsen (billionai) } 87607468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 87617468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 87627468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 87637468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 87647468e2c8SBruno Larsen (billionai) return -1; 87657468e2c8SBruno Larsen (billionai) } 87667468e2c8SBruno Larsen (billionai) return 0; 87677468e2c8SBruno Larsen (billionai) } 87687468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 87697468e2c8SBruno Larsen (billionai) { 87707468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 87717468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 87727468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 87737468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 87747468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 87757468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 87767468e2c8SBruno Larsen (billionai) return -1; 87777468e2c8SBruno Larsen (billionai) } 87787468e2c8SBruno Larsen (billionai) } else { 87797468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 87807468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 87817468e2c8SBruno Larsen (billionai) return -1; 87827468e2c8SBruno Larsen (billionai) } 87837468e2c8SBruno Larsen (billionai) } 87847468e2c8SBruno Larsen (billionai) } else { 87857468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 87867468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 87877468e2c8SBruno Larsen (billionai) return -1; 87887468e2c8SBruno Larsen (billionai) } 87897468e2c8SBruno Larsen (billionai) } 87907468e2c8SBruno Larsen (billionai) } else { 87917468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 87927468e2c8SBruno Larsen (billionai) return -1; 87937468e2c8SBruno Larsen (billionai) } 87947468e2c8SBruno Larsen (billionai) } 87957468e2c8SBruno Larsen (billionai) 87967468e2c8SBruno Larsen (billionai) return 0; 87977468e2c8SBruno Larsen (billionai) } 87987468e2c8SBruno Larsen (billionai) 87997468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 88007468e2c8SBruno Larsen (billionai) { 88017468e2c8SBruno Larsen (billionai) int i, count, tmp; 88027468e2c8SBruno Larsen (billionai) 88037468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 88047468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 88057468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 88067468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88077468e2c8SBruno Larsen (billionai) } 88087468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 88097468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 88107468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 88117468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 88127468e2c8SBruno Larsen (billionai) if (tmp == 0) { 88137468e2c8SBruno Larsen (billionai) free(table[i]); 88147468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 88157468e2c8SBruno Larsen (billionai) } else { 88167468e2c8SBruno Larsen (billionai) count++; 88177468e2c8SBruno Larsen (billionai) } 88187468e2c8SBruno Larsen (billionai) } else { 88197468e2c8SBruno Larsen (billionai) count++; 88207468e2c8SBruno Larsen (billionai) } 88217468e2c8SBruno Larsen (billionai) } 88227468e2c8SBruno Larsen (billionai) } 88237468e2c8SBruno Larsen (billionai) 88247468e2c8SBruno Larsen (billionai) return count; 88257468e2c8SBruno Larsen (billionai) } 88267468e2c8SBruno Larsen (billionai) 88277468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 88287468e2c8SBruno Larsen (billionai) { 88297468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 88307468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 88317468e2c8SBruno Larsen (billionai) } 88327468e2c8SBruno Larsen (billionai) } 88337468e2c8SBruno Larsen (billionai) 88347468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 88357468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 88367468e2c8SBruno Larsen (billionai) { 88377468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 88387468e2c8SBruno Larsen (billionai) opcode_t *opc; 88397468e2c8SBruno Larsen (billionai) 88407468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 88417468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 88427468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 88437468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 88447468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 88457468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 88467468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 88477468e2c8SBruno Larsen (billionai) opc->opc3); 88487468e2c8SBruno Larsen (billionai) return; 88497468e2c8SBruno Larsen (billionai) } 88507468e2c8SBruno Larsen (billionai) } 88517468e2c8SBruno Larsen (billionai) } 88527468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 88537468e2c8SBruno Larsen (billionai) fflush(stdout); 88547468e2c8SBruno Larsen (billionai) fflush(stderr); 88557468e2c8SBruno Larsen (billionai) } 88567468e2c8SBruno Larsen (billionai) 88577468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 88587468e2c8SBruno Larsen (billionai) { 88597468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 88607468e2c8SBruno Larsen (billionai) int i, j, k; 88617468e2c8SBruno Larsen (billionai) 88627468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 88637468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 88647468e2c8SBruno Larsen (billionai) continue; 88657468e2c8SBruno Larsen (billionai) } 88667468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 88677468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 88687468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 88697468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 88707468e2c8SBruno Larsen (billionai) continue; 88717468e2c8SBruno Larsen (billionai) } 88727468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 88737468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 88747468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 88757468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 88767468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 88777468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 88787468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88797468e2c8SBruno Larsen (billionai) } 88807468e2c8SBruno Larsen (billionai) } 88817468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 88827468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88837468e2c8SBruno Larsen (billionai) } 88847468e2c8SBruno Larsen (billionai) } 88857468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 88867468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 88877468e2c8SBruno Larsen (billionai) } 88887468e2c8SBruno Larsen (billionai) } 88897468e2c8SBruno Larsen (billionai) } 88907468e2c8SBruno Larsen (billionai) 88917468e2c8SBruno Larsen (billionai) #if defined(PPC_DUMP_CPU) 88927468e2c8SBruno Larsen (billionai) static void dump_ppc_insns(CPUPPCState *env) 88937468e2c8SBruno Larsen (billionai) { 88947468e2c8SBruno Larsen (billionai) opc_handler_t **table, *handler; 88957468e2c8SBruno Larsen (billionai) const char *p, *q; 88967468e2c8SBruno Larsen (billionai) uint8_t opc1, opc2, opc3, opc4; 88977468e2c8SBruno Larsen (billionai) 88987468e2c8SBruno Larsen (billionai) printf("Instructions set:\n"); 88997468e2c8SBruno Larsen (billionai) /* opc1 is 6 bits long */ 89007468e2c8SBruno Larsen (billionai) for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 89017468e2c8SBruno Larsen (billionai) table = env->opcodes; 89027468e2c8SBruno Larsen (billionai) handler = table[opc1]; 89037468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89047468e2c8SBruno Larsen (billionai) /* opc2 is 5 bits long */ 89057468e2c8SBruno Larsen (billionai) for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 89067468e2c8SBruno Larsen (billionai) table = env->opcodes; 89077468e2c8SBruno Larsen (billionai) handler = env->opcodes[opc1]; 89087468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89097468e2c8SBruno Larsen (billionai) handler = table[opc2]; 89107468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89117468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89127468e2c8SBruno Larsen (billionai) /* opc3 is 5 bits long */ 89137468e2c8SBruno Larsen (billionai) for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 89147468e2c8SBruno Larsen (billionai) opc3++) { 89157468e2c8SBruno Larsen (billionai) handler = table[opc3]; 89167468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(handler)) { 89177468e2c8SBruno Larsen (billionai) table = ind_table(handler); 89187468e2c8SBruno Larsen (billionai) /* opc4 is 5 bits long */ 89197468e2c8SBruno Larsen (billionai) for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 89207468e2c8SBruno Larsen (billionai) opc4++) { 89217468e2c8SBruno Larsen (billionai) handler = table[opc4]; 89227468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89237468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x %02x -- " 89247468e2c8SBruno Larsen (billionai) "(%02d %04d %02d) : %s\n", 89257468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc4, 89267468e2c8SBruno Larsen (billionai) opc1, (opc3 << 5) | opc2, opc4, 89277468e2c8SBruno Larsen (billionai) handler->oname); 89287468e2c8SBruno Larsen (billionai) } 89297468e2c8SBruno Larsen (billionai) } 89307468e2c8SBruno Larsen (billionai) } else { 89317468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89327468e2c8SBruno Larsen (billionai) /* Special hack to properly dump SPE insns */ 89337468e2c8SBruno Larsen (billionai) p = strchr(handler->oname, '_'); 89347468e2c8SBruno Larsen (billionai) if (p == NULL) { 89357468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x (%02d %04d) : " 89367468e2c8SBruno Larsen (billionai) "%s\n", 89377468e2c8SBruno Larsen (billionai) opc1, opc2, opc3, opc1, 89387468e2c8SBruno Larsen (billionai) (opc3 << 5) | opc2, 89397468e2c8SBruno Larsen (billionai) handler->oname); 89407468e2c8SBruno Larsen (billionai) } else { 89417468e2c8SBruno Larsen (billionai) q = "speundef"; 89427468e2c8SBruno Larsen (billionai) if ((p - handler->oname) != strlen(q) 89437468e2c8SBruno Larsen (billionai) || (memcmp(handler->oname, q, strlen(q)) 89447468e2c8SBruno Larsen (billionai) != 0)) { 89457468e2c8SBruno Larsen (billionai) /* First instruction */ 89467468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x" 89477468e2c8SBruno Larsen (billionai) "(%02d %04d) : %.*s\n", 89487468e2c8SBruno Larsen (billionai) opc1, opc2 << 1, opc3, opc1, 89497468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1), 89507468e2c8SBruno Larsen (billionai) (int)(p - handler->oname), 89517468e2c8SBruno Larsen (billionai) handler->oname); 89527468e2c8SBruno Larsen (billionai) } 89537468e2c8SBruno Larsen (billionai) if (strcmp(p + 1, q) != 0) { 89547468e2c8SBruno Larsen (billionai) /* Second instruction */ 89557468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x %02x " 89567468e2c8SBruno Larsen (billionai) "(%02d %04d) : %s\n", opc1, 89577468e2c8SBruno Larsen (billionai) (opc2 << 1) | 1, opc3, opc1, 89587468e2c8SBruno Larsen (billionai) (opc3 << 6) | (opc2 << 1) | 1, 89597468e2c8SBruno Larsen (billionai) p + 1); 89607468e2c8SBruno Larsen (billionai) } 89617468e2c8SBruno Larsen (billionai) } 89627468e2c8SBruno Larsen (billionai) } 89637468e2c8SBruno Larsen (billionai) } 89647468e2c8SBruno Larsen (billionai) } 89657468e2c8SBruno Larsen (billionai) } else { 89667468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89677468e2c8SBruno Larsen (billionai) printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 89687468e2c8SBruno Larsen (billionai) opc1, opc2, opc1, opc2, handler->oname); 89697468e2c8SBruno Larsen (billionai) } 89707468e2c8SBruno Larsen (billionai) } 89717468e2c8SBruno Larsen (billionai) } 89727468e2c8SBruno Larsen (billionai) } else { 89737468e2c8SBruno Larsen (billionai) if (handler->handler != &gen_invalid) { 89747468e2c8SBruno Larsen (billionai) printf("INSN: %02x -- -- (%02d ----) : %s\n", 89757468e2c8SBruno Larsen (billionai) opc1, opc1, handler->oname); 89767468e2c8SBruno Larsen (billionai) } 89777468e2c8SBruno Larsen (billionai) } 89787468e2c8SBruno Larsen (billionai) } 89797468e2c8SBruno Larsen (billionai) } 89807468e2c8SBruno Larsen (billionai) #endif 89817468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 89827468e2c8SBruno Larsen (billionai) { 89837468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 89847468e2c8SBruno Larsen (billionai) 89857468e2c8SBruno Larsen (billionai) /* 89867468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 89877468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 89887468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 89897468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 89907468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 89917468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 89927468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 89937468e2c8SBruno Larsen (billionai) */ 89947468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 89957468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 89967468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 89977468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 89987468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 89997468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 90007468e2c8SBruno Larsen (billionai) } 90017468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 90027468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 90037468e2c8SBruno Larsen (billionai) return 0; 90047468e2c8SBruno Larsen (billionai) } 90057468e2c8SBruno Larsen (billionai) 90067468e2c8SBruno Larsen (billionai) 900711cb6c15SMarkus Armbruster void ppc_cpu_dump_statistics(CPUState *cs, int flags) 9008fcf5ef2aSThomas Huth { 9009fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9010fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 9011fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 9012fcf5ef2aSThomas Huth int op1, op2, op3; 9013fcf5ef2aSThomas Huth 9014fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 9015fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 9016fcf5ef2aSThomas Huth handler = t1[op1]; 9017fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9018fcf5ef2aSThomas Huth t2 = ind_table(handler); 9019fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 9020fcf5ef2aSThomas Huth handler = t2[op2]; 9021fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 9022fcf5ef2aSThomas Huth t3 = ind_table(handler); 9023fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 9024fcf5ef2aSThomas Huth handler = t3[op3]; 9025efe843d8SDavid Gibson if (handler->count == 0) { 9026fcf5ef2aSThomas Huth continue; 9027efe843d8SDavid Gibson } 902811cb6c15SMarkus Armbruster qemu_printf("%02x %02x %02x (%02x %04d) %16s: " 9029fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9030fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 9031fcf5ef2aSThomas Huth handler->oname, 9032fcf5ef2aSThomas Huth handler->count, handler->count); 9033fcf5ef2aSThomas Huth } 9034fcf5ef2aSThomas Huth } else { 9035efe843d8SDavid Gibson if (handler->count == 0) { 9036fcf5ef2aSThomas Huth continue; 9037efe843d8SDavid Gibson } 903811cb6c15SMarkus Armbruster qemu_printf("%02x %02x (%02x %04d) %16s: " 9039fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 9040fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 9041fcf5ef2aSThomas Huth handler->count, handler->count); 9042fcf5ef2aSThomas Huth } 9043fcf5ef2aSThomas Huth } 9044fcf5ef2aSThomas Huth } else { 9045efe843d8SDavid Gibson if (handler->count == 0) { 9046fcf5ef2aSThomas Huth continue; 9047efe843d8SDavid Gibson } 904811cb6c15SMarkus Armbruster qemu_printf("%02x (%02x ) %16s: %016" PRIx64 9049fcf5ef2aSThomas Huth " %" PRId64 "\n", 9050fcf5ef2aSThomas Huth op1, op1, handler->oname, 9051fcf5ef2aSThomas Huth handler->count, handler->count); 9052fcf5ef2aSThomas Huth } 9053fcf5ef2aSThomas Huth } 9054fcf5ef2aSThomas Huth #endif 9055fcf5ef2aSThomas Huth } 9056fcf5ef2aSThomas Huth 9057624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 9058624cb07fSRichard Henderson { 9059624cb07fSRichard Henderson opc_handler_t **table, *handler; 9060624cb07fSRichard Henderson uint32_t inval; 9061624cb07fSRichard Henderson 9062624cb07fSRichard Henderson ctx->opcode = insn; 9063624cb07fSRichard Henderson 9064624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 9065624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9066624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 9067624cb07fSRichard Henderson 9068624cb07fSRichard Henderson table = cpu->opcodes; 9069624cb07fSRichard Henderson handler = table[opc1(insn)]; 9070624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9071624cb07fSRichard Henderson table = ind_table(handler); 9072624cb07fSRichard Henderson handler = table[opc2(insn)]; 9073624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9074624cb07fSRichard Henderson table = ind_table(handler); 9075624cb07fSRichard Henderson handler = table[opc3(insn)]; 9076624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 9077624cb07fSRichard Henderson table = ind_table(handler); 9078624cb07fSRichard Henderson handler = table[opc4(insn)]; 9079624cb07fSRichard Henderson } 9080624cb07fSRichard Henderson } 9081624cb07fSRichard Henderson } 9082624cb07fSRichard Henderson 9083624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 9084624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 9085624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 9086624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 9087624cb07fSRichard Henderson TARGET_FMT_lx "\n", 9088624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9089624cb07fSRichard Henderson insn, ctx->cia); 9090624cb07fSRichard Henderson return false; 9091624cb07fSRichard Henderson } 9092624cb07fSRichard Henderson 9093624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 9094624cb07fSRichard Henderson && Rc(insn))) { 9095624cb07fSRichard Henderson inval = handler->inval2; 9096624cb07fSRichard Henderson } else { 9097624cb07fSRichard Henderson inval = handler->inval1; 9098624cb07fSRichard Henderson } 9099624cb07fSRichard Henderson 9100624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 9101624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 9102624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 9103624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 9104624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 9105624cb07fSRichard Henderson insn, ctx->cia); 9106624cb07fSRichard Henderson return false; 9107624cb07fSRichard Henderson } 9108624cb07fSRichard Henderson 9109624cb07fSRichard Henderson handler->handler(ctx); 9110624cb07fSRichard Henderson return true; 9111624cb07fSRichard Henderson } 9112624cb07fSRichard Henderson 9113b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 9114fcf5ef2aSThomas Huth { 9115b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 91169c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 91172df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 9118b0c2d521SEmilio G. Cota int bound; 9119fcf5ef2aSThomas Huth 9120b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 9121b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 91222df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 9123d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 91242df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 91252df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 9126b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 9127b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 9128b0c2d521SEmilio G. Cota ctx->access_type = -1; 9129d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 91302df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 9131b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 91320e3bf489SRoman Kapl ctx->flags = env->flags; 9133fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 91342df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 9135b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 9136fcf5ef2aSThomas Huth #endif 9137e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 9138e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 9139d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 9140fcf5ef2aSThomas Huth 91412df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 91422df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 91432df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 91442df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 91452df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 9146f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 91472df4fe7aSRichard Henderson 9148b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 91492df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 91502df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 9151efe843d8SDavid Gibson } 91522df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 9153b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 9154efe843d8SDavid Gibson } 9155b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9156b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 9157fcf5ef2aSThomas Huth } 9158b0c2d521SEmilio G. Cota 9159b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 9160b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 9161fcf5ef2aSThomas Huth } 9162fcf5ef2aSThomas Huth 9163b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 9164b0c2d521SEmilio G. Cota { 9165b0c2d521SEmilio G. Cota } 9166fcf5ef2aSThomas Huth 9167b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 9168b0c2d521SEmilio G. Cota { 9169b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 9170b0c2d521SEmilio G. Cota } 9171b0c2d521SEmilio G. Cota 9172b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 9173b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 9174b0c2d521SEmilio G. Cota { 9175b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9176b0c2d521SEmilio G. Cota 9177*2736fc61SRichard Henderson gen_update_nip(ctx, ctx->base.pc_next); 9178b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9179efe843d8SDavid Gibson /* 9180efe843d8SDavid Gibson * The address covered by the breakpoint must be included in 9181efe843d8SDavid Gibson * [tb->pc, tb->pc + tb->size) in order to for it to be properly 9182efe843d8SDavid Gibson * cleared -- thus we increment the PC here so that the logic 9183efe843d8SDavid Gibson * setting tb->size below does the right thing. 9184efe843d8SDavid Gibson */ 9185b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9186b0c2d521SEmilio G. Cota return true; 9187fcf5ef2aSThomas Huth } 9188fcf5ef2aSThomas Huth 9189b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 9190b0c2d521SEmilio G. Cota { 9191b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 919228876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 9193b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 9194624cb07fSRichard Henderson uint32_t insn; 9195624cb07fSRichard Henderson bool ok; 9196b0c2d521SEmilio G. Cota 9197fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 9198fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 9199b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 9200b0c2d521SEmilio G. Cota 92012c2bcb1bSRichard Henderson ctx->cia = ctx->base.pc_next; 9202624cb07fSRichard Henderson insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); 9203b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 9204fcf5ef2aSThomas Huth 9205624cb07fSRichard Henderson ok = decode_legacy(cpu, ctx, insn); 9206624cb07fSRichard Henderson if (!ok) { 9207624cb07fSRichard Henderson gen_invalid(ctx); 9208fcf5ef2aSThomas Huth } 9209624cb07fSRichard Henderson 9210fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 9211fcf5ef2aSThomas Huth handler->count++; 9212fcf5ef2aSThomas Huth #endif 92133d8a5b69SRichard Henderson 9214fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 9215b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 9216b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 92173d8a5b69SRichard Henderson ctx->exception != POWERPC_EXCP_BRANCH && 92183d8a5b69SRichard Henderson ctx->base.is_jmp != DISAS_NORETURN)) { 9219e150ac89SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx); 92200e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 9221fcf5ef2aSThomas Huth } 9222b0c2d521SEmilio G. Cota 9223fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 9224b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 9225b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 9226b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 9227fcf5ef2aSThomas Huth } 9228b0c2d521SEmilio G. Cota 92293d8a5b69SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT 92303d8a5b69SRichard Henderson && ctx->exception != POWERPC_EXCP_NONE) { 92313d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 92323d8a5b69SRichard Henderson } 9233fcf5ef2aSThomas Huth } 9234b0c2d521SEmilio G. Cota 9235b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 9236b0c2d521SEmilio G. Cota { 9237b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 9238b0c2d521SEmilio G. Cota 92393d8a5b69SRichard Henderson if (ctx->base.is_jmp == DISAS_NORETURN) { 92403d8a5b69SRichard Henderson return; 92413d8a5b69SRichard Henderson } 92423d8a5b69SRichard Henderson 9243b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 9244b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 9245b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 9246b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 9247b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 9248fcf5ef2aSThomas Huth } 9249fcf5ef2aSThomas Huth /* Generate the return instruction */ 925007ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 9251fcf5ef2aSThomas Huth } 9252fcf5ef2aSThomas Huth } 9253b0c2d521SEmilio G. Cota 9254b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 9255b0c2d521SEmilio G. Cota { 9256b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 9257b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 9258b0c2d521SEmilio G. Cota } 9259b0c2d521SEmilio G. Cota 9260b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 9261b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 9262b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 9263b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 9264b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 9265b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 9266b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 9267b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 9268b0c2d521SEmilio G. Cota }; 9269b0c2d521SEmilio G. Cota 92708b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 9271b0c2d521SEmilio G. Cota { 9272b0c2d521SEmilio G. Cota DisasContext ctx; 9273b0c2d521SEmilio G. Cota 92748b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 9275fcf5ef2aSThomas Huth } 9276fcf5ef2aSThomas Huth 9277fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 9278fcf5ef2aSThomas Huth target_ulong *data) 9279fcf5ef2aSThomas Huth { 9280fcf5ef2aSThomas Huth env->nip = data[0]; 9281fcf5ef2aSThomas Huth } 9282