1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29db725815SMarkus Armbruster #include "qemu/main-loop.h" 30fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 31fcf5ef2aSThomas Huth 32fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 33fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 34fcf5ef2aSThomas Huth 35b6bac4bcSEmilio G. Cota #include "exec/translator.h" 36fcf5ef2aSThomas Huth #include "exec/log.h" 37f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 38a829cec3SBruno Larsen (billionai) #include "spr_tcg.h" 39fcf5ef2aSThomas Huth 403e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 413e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 42fcf5ef2aSThomas Huth 43fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 44fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 47efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 50fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 51fcf5ef2aSThomas Huth #else 52fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 53fcf5ef2aSThomas Huth #endif 54fcf5ef2aSThomas Huth /*****************************************************************************/ 55fcf5ef2aSThomas Huth /* Code translation helpers */ 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth /* global register indexes */ 58fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 59fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 60fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 64fcf5ef2aSThomas Huth static TCGv cpu_nip; 65fcf5ef2aSThomas Huth static TCGv cpu_msr; 66fcf5ef2aSThomas Huth static TCGv cpu_ctr; 67fcf5ef2aSThomas Huth static TCGv cpu_lr; 68fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 69fcf5ef2aSThomas Huth static TCGv cpu_cfar; 70fcf5ef2aSThomas Huth #endif 71dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 72fcf5ef2aSThomas Huth static TCGv cpu_reserve; 73253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 74fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 75fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 76fcf5ef2aSThomas Huth 77fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 78fcf5ef2aSThomas Huth 79fcf5ef2aSThomas Huth void ppc_translate_init(void) 80fcf5ef2aSThomas Huth { 81fcf5ef2aSThomas Huth int i; 82fcf5ef2aSThomas Huth char *p; 83fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 84fcf5ef2aSThomas Huth 85fcf5ef2aSThomas Huth p = cpu_reg_names; 86fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 89fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 90fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 91fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 92fcf5ef2aSThomas Huth p += 5; 93fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 94fcf5ef2aSThomas Huth } 95fcf5ef2aSThomas Huth 96fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 97fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 98fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 99fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 100fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 101fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 102fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 103fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 104fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 105fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 106fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 107fcf5ef2aSThomas Huth } 108fcf5ef2aSThomas Huth 109fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 110fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 122fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth 126fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 128fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 129fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 130fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 132fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 133fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 134dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 135dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 136dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 137dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 138fcf5ef2aSThomas Huth 139fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 141fcf5ef2aSThomas Huth "reserve_addr"); 142253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 143253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 144253ce7b2SNikunj A Dadhania "reserve_val"); 145fcf5ef2aSThomas Huth 146fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 148fcf5ef2aSThomas Huth 149fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 150efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 151efe843d8SDavid Gibson "access_type"); 152fcf5ef2aSThomas Huth } 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth /* internal defines */ 155fcf5ef2aSThomas Huth struct DisasContext { 156b6bac4bcSEmilio G. Cota DisasContextBase base; 1572c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 158fcf5ef2aSThomas Huth uint32_t opcode; 159fcf5ef2aSThomas Huth /* Routine used to access memory */ 160fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 161fcf5ef2aSThomas Huth bool lazy_tlb_flush; 162fcf5ef2aSThomas Huth bool need_access_type; 163fcf5ef2aSThomas Huth int mem_idx; 164fcf5ef2aSThomas Huth int access_type; 165fcf5ef2aSThomas Huth /* Translation flags */ 16614776ab5STony Nguyen MemOp default_tcg_memop_mask; 167fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 168fcf5ef2aSThomas Huth bool sf_mode; 169fcf5ef2aSThomas Huth bool has_cfar; 170fcf5ef2aSThomas Huth #endif 171fcf5ef2aSThomas Huth bool fpu_enabled; 172fcf5ef2aSThomas Huth bool altivec_enabled; 173fcf5ef2aSThomas Huth bool vsx_enabled; 174fcf5ef2aSThomas Huth bool spe_enabled; 175fcf5ef2aSThomas Huth bool tm_enabled; 176c6fd28fdSSuraj Jitindar Singh bool gtse; 1771db3632aSMatheus Ferst bool hr; 178f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 179f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 18046d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 181fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 182fcf5ef2aSThomas Huth int singlestep_enabled; 1830e3bf489SRoman Kapl uint32_t flags; 184fcf5ef2aSThomas Huth uint64_t insns_flags; 185fcf5ef2aSThomas Huth uint64_t insns_flags2; 186fcf5ef2aSThomas Huth }; 187fcf5ef2aSThomas Huth 188a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 189a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 190a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 191a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 192a9b5b3d0SRichard Henderson 193fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 194fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 195fcf5ef2aSThomas Huth { 196fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 197fcf5ef2aSThomas Huth return ctx->le_mode; 198fcf5ef2aSThomas Huth #else 199fcf5ef2aSThomas Huth return !ctx->le_mode; 200fcf5ef2aSThomas Huth #endif 201fcf5ef2aSThomas Huth } 202fcf5ef2aSThomas Huth 203fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 204fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 205fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 206fcf5ef2aSThomas Huth #else 207fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 208fcf5ef2aSThomas Huth #endif 209fcf5ef2aSThomas Huth 210fcf5ef2aSThomas Huth struct opc_handler_t { 211fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 212fcf5ef2aSThomas Huth uint32_t inval1; 213fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 214fcf5ef2aSThomas Huth uint32_t inval2; 215fcf5ef2aSThomas Huth /* instruction type */ 216fcf5ef2aSThomas Huth uint64_t type; 217fcf5ef2aSThomas Huth /* extended instruction type */ 218fcf5ef2aSThomas Huth uint64_t type2; 219fcf5ef2aSThomas Huth /* handler */ 220fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 221fcf5ef2aSThomas Huth }; 222fcf5ef2aSThomas Huth 2230e3bf489SRoman Kapl /* SPR load/store helpers */ 2240e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2250e3bf489SRoman Kapl { 2260e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2270e3bf489SRoman Kapl } 2280e3bf489SRoman Kapl 2290e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2300e3bf489SRoman Kapl { 2310e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2320e3bf489SRoman Kapl } 2330e3bf489SRoman Kapl 234fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 235fcf5ef2aSThomas Huth { 236fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 237fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 238fcf5ef2aSThomas Huth ctx->access_type = access_type; 239fcf5ef2aSThomas Huth } 240fcf5ef2aSThomas Huth } 241fcf5ef2aSThomas Huth 242fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 243fcf5ef2aSThomas Huth { 244fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 245fcf5ef2aSThomas Huth nip = (uint32_t)nip; 246fcf5ef2aSThomas Huth } 247fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 248fcf5ef2aSThomas Huth } 249fcf5ef2aSThomas Huth 250fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 251fcf5ef2aSThomas Huth { 252fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 253fcf5ef2aSThomas Huth 254efe843d8SDavid Gibson /* 255efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 256efe843d8SDavid Gibson * faulting instruction 257fcf5ef2aSThomas Huth */ 2582c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 259fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 260fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 261fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 262fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 263fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2643d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 265fcf5ef2aSThomas Huth } 266fcf5ef2aSThomas Huth 267fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 268fcf5ef2aSThomas Huth { 269fcf5ef2aSThomas Huth TCGv_i32 t0; 270fcf5ef2aSThomas Huth 271efe843d8SDavid Gibson /* 272efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 273efe843d8SDavid Gibson * faulting instruction 274fcf5ef2aSThomas Huth */ 2752c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 276fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 277fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 278fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2793d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth 282fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 283fcf5ef2aSThomas Huth target_ulong nip) 284fcf5ef2aSThomas Huth { 285fcf5ef2aSThomas Huth TCGv_i32 t0; 286fcf5ef2aSThomas Huth 287fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 288fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 289fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 290fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2913d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 292fcf5ef2aSThomas Huth } 293fcf5ef2aSThomas Huth 294f5b6daacSRichard Henderson static void gen_icount_io_start(DisasContext *ctx) 295f5b6daacSRichard Henderson { 296f5b6daacSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 297f5b6daacSRichard Henderson gen_io_start(); 298f5b6daacSRichard Henderson /* 299f5b6daacSRichard Henderson * An I/O instruction must be last in the TB. 300f5b6daacSRichard Henderson * Chain to the next TB, and let the code from gen_tb_start 301f5b6daacSRichard Henderson * decide if we need to return to the main loop. 302f5b6daacSRichard Henderson * Doing this first also allows this value to be overridden. 303f5b6daacSRichard Henderson */ 304f5b6daacSRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 305f5b6daacSRichard Henderson } 306f5b6daacSRichard Henderson } 307f5b6daacSRichard Henderson 308e150ac89SRoman Kapl /* 309e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 310e150ac89SRoman Kapl * SPR registers for this exception. 311e150ac89SRoman Kapl * 312e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 313e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3140e3bf489SRoman Kapl */ 315e150ac89SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx) 3160e3bf489SRoman Kapl { 3170e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3180e3bf489SRoman Kapl target_ulong dbsr = 0; 319e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3200e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 321e150ac89SRoman Kapl } else { 322e150ac89SRoman Kapl /* Must have been branch */ 3230e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3240e3bf489SRoman Kapl } 3250e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3260e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3270e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3280e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 3290e3bf489SRoman Kapl tcg_temp_free(t0); 3300e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 3310e3bf489SRoman Kapl } else { 332e150ac89SRoman Kapl return POWERPC_EXCP_TRACE; 3330e3bf489SRoman Kapl } 3340e3bf489SRoman Kapl } 3350e3bf489SRoman Kapl 336fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 337fcf5ef2aSThomas Huth { 3389498d103SRichard Henderson gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); 3393d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 340fcf5ef2aSThomas Huth } 341fcf5ef2aSThomas Huth 342fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 343fcf5ef2aSThomas Huth { 344fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 345fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 346fcf5ef2aSThomas Huth } 347fcf5ef2aSThomas Huth 348fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 353fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 354fcf5ef2aSThomas Huth { 355fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 356fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 357fcf5ef2aSThomas Huth } 358fcf5ef2aSThomas Huth 35937f219c8SBruno Larsen (billionai) /*****************************************************************************/ 36037f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 36137f219c8SBruno Larsen (billionai) 362a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 36337f219c8SBruno Larsen (billionai) { 36437f219c8SBruno Larsen (billionai) #if 0 36537f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 36637f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 36737f219c8SBruno Larsen (billionai) #endif 36837f219c8SBruno Larsen (billionai) } 36937f219c8SBruno Larsen (billionai) 37037f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 37137f219c8SBruno Larsen (billionai) 37237f219c8SBruno Larsen (billionai) /* 37337f219c8SBruno Larsen (billionai) * Generic callbacks: 37437f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 37537f219c8SBruno Larsen (billionai) */ 37637f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 37737f219c8SBruno Larsen (billionai) { 37837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 37937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 38037f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 38137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 38237f219c8SBruno Larsen (billionai) #endif 38337f219c8SBruno Larsen (billionai) } 38437f219c8SBruno Larsen (billionai) 385a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 38637f219c8SBruno Larsen (billionai) { 38737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 38837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 38937f219c8SBruno Larsen (billionai) } 39037f219c8SBruno Larsen (billionai) 39137f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 39237f219c8SBruno Larsen (billionai) { 39337f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 39437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 39537f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 39637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 39737f219c8SBruno Larsen (billionai) #endif 39837f219c8SBruno Larsen (billionai) } 39937f219c8SBruno Larsen (billionai) 400a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 40137f219c8SBruno Larsen (billionai) { 40237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 40337f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 40437f219c8SBruno Larsen (billionai) } 40537f219c8SBruno Larsen (billionai) 4067aeac354SDaniel Henrique Barboza void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 4077aeac354SDaniel Henrique Barboza { 4087aeac354SDaniel Henrique Barboza spr_write_generic(ctx, sprn, gprn); 4097aeac354SDaniel Henrique Barboza 4107aeac354SDaniel Henrique Barboza /* 4117aeac354SDaniel Henrique Barboza * SPR_CTRL writes must force a new translation block, 4127aeac354SDaniel Henrique Barboza * allowing the PMU to calculate the run latch events with 4137aeac354SDaniel Henrique Barboza * more accuracy. 4147aeac354SDaniel Henrique Barboza */ 4157aeac354SDaniel Henrique Barboza ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4167aeac354SDaniel Henrique Barboza } 4177aeac354SDaniel Henrique Barboza 41837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 419a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 42037f219c8SBruno Larsen (billionai) { 42137f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 42237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 42337f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 42437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 42537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 42637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42737f219c8SBruno Larsen (billionai) #else 42837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 42937f219c8SBruno Larsen (billionai) #endif 43037f219c8SBruno Larsen (billionai) } 43137f219c8SBruno Larsen (billionai) 432a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 43337f219c8SBruno Larsen (billionai) { 43437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 43637f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 43737f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 43837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 43937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 44037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 44137f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 44237f219c8SBruno Larsen (billionai) } 44337f219c8SBruno Larsen (billionai) 444a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 44537f219c8SBruno Larsen (billionai) { 44637f219c8SBruno Larsen (billionai) } 44737f219c8SBruno Larsen (billionai) 44837f219c8SBruno Larsen (billionai) #endif 44937f219c8SBruno Larsen (billionai) 45037f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 45137f219c8SBruno Larsen (billionai) /* XER */ 452a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 45337f219c8SBruno Larsen (billionai) { 45437f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 45537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 45637f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 45737f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 45837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 45937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 46037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 46137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 46237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 46337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 46437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46537f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 46637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 46737f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 46837f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 46937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 47037f219c8SBruno Larsen (billionai) } 47137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 47237f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 47337f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 47437f219c8SBruno Larsen (billionai) } 47537f219c8SBruno Larsen (billionai) 476a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 47737f219c8SBruno Larsen (billionai) { 47837f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 47937f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 48037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 48137f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 48237f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 48337f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 48437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 48537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 48637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 48737f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 48837f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 48937f219c8SBruno Larsen (billionai) } 49037f219c8SBruno Larsen (billionai) 49137f219c8SBruno Larsen (billionai) /* LR */ 492a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 49337f219c8SBruno Larsen (billionai) { 49437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 49537f219c8SBruno Larsen (billionai) } 49637f219c8SBruno Larsen (billionai) 497a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 49837f219c8SBruno Larsen (billionai) { 49937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 50037f219c8SBruno Larsen (billionai) } 50137f219c8SBruno Larsen (billionai) 50237f219c8SBruno Larsen (billionai) /* CFAR */ 50337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 504a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 50537f219c8SBruno Larsen (billionai) { 50637f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 50737f219c8SBruno Larsen (billionai) } 50837f219c8SBruno Larsen (billionai) 509a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 51037f219c8SBruno Larsen (billionai) { 51137f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 51237f219c8SBruno Larsen (billionai) } 51337f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 51437f219c8SBruno Larsen (billionai) 51537f219c8SBruno Larsen (billionai) /* CTR */ 516a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 51737f219c8SBruno Larsen (billionai) { 51837f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 51937f219c8SBruno Larsen (billionai) } 52037f219c8SBruno Larsen (billionai) 521a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 52237f219c8SBruno Larsen (billionai) { 52337f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 52437f219c8SBruno Larsen (billionai) } 52537f219c8SBruno Larsen (billionai) 52637f219c8SBruno Larsen (billionai) /* User read access to SPR */ 52737f219c8SBruno Larsen (billionai) /* USPRx */ 52837f219c8SBruno Larsen (billionai) /* UMMCRx */ 52937f219c8SBruno Larsen (billionai) /* UPMCx */ 53037f219c8SBruno Larsen (billionai) /* USIA */ 53137f219c8SBruno Larsen (billionai) /* UDECR */ 532a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 53337f219c8SBruno Larsen (billionai) { 53437f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 53537f219c8SBruno Larsen (billionai) } 53637f219c8SBruno Larsen (billionai) 53737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 538a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 53937f219c8SBruno Larsen (billionai) { 54037f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 54137f219c8SBruno Larsen (billionai) } 54237f219c8SBruno Larsen (billionai) #endif 54337f219c8SBruno Larsen (billionai) 54437f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 54537f219c8SBruno Larsen (billionai) /* DECR */ 54637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 547a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 54837f219c8SBruno Larsen (billionai) { 549f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55037f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 55137f219c8SBruno Larsen (billionai) } 55237f219c8SBruno Larsen (billionai) 553a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 55437f219c8SBruno Larsen (billionai) { 555f5b6daacSRichard Henderson gen_icount_io_start(ctx); 55637f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 55737f219c8SBruno Larsen (billionai) } 55837f219c8SBruno Larsen (billionai) #endif 55937f219c8SBruno Larsen (billionai) 56037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 56137f219c8SBruno Larsen (billionai) /* Time base */ 562a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 56337f219c8SBruno Larsen (billionai) { 564f5b6daacSRichard Henderson gen_icount_io_start(ctx); 56537f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 56637f219c8SBruno Larsen (billionai) } 56737f219c8SBruno Larsen (billionai) 568a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 56937f219c8SBruno Larsen (billionai) { 570f5b6daacSRichard Henderson gen_icount_io_start(ctx); 57137f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 57237f219c8SBruno Larsen (billionai) } 57337f219c8SBruno Larsen (billionai) 574a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 57537f219c8SBruno Larsen (billionai) { 57637f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 57737f219c8SBruno Larsen (billionai) } 57837f219c8SBruno Larsen (billionai) 579a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 58037f219c8SBruno Larsen (billionai) { 58137f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 58237f219c8SBruno Larsen (billionai) } 58337f219c8SBruno Larsen (billionai) 58437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 585a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 58637f219c8SBruno Larsen (billionai) { 587f5b6daacSRichard Henderson gen_icount_io_start(ctx); 58837f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 58937f219c8SBruno Larsen (billionai) } 59037f219c8SBruno Larsen (billionai) 591a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 59237f219c8SBruno Larsen (billionai) { 593f5b6daacSRichard Henderson gen_icount_io_start(ctx); 59437f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 59537f219c8SBruno Larsen (billionai) } 59637f219c8SBruno Larsen (billionai) 597a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 59837f219c8SBruno Larsen (billionai) { 59937f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 60037f219c8SBruno Larsen (billionai) } 60137f219c8SBruno Larsen (billionai) 602a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 60337f219c8SBruno Larsen (billionai) { 60437f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 60537f219c8SBruno Larsen (billionai) } 60637f219c8SBruno Larsen (billionai) 60737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 608a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 60937f219c8SBruno Larsen (billionai) { 610f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61137f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 61237f219c8SBruno Larsen (billionai) } 61337f219c8SBruno Larsen (billionai) 614a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 61537f219c8SBruno Larsen (billionai) { 616f5b6daacSRichard Henderson gen_icount_io_start(ctx); 61737f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 61837f219c8SBruno Larsen (billionai) } 61937f219c8SBruno Larsen (billionai) 62037f219c8SBruno Larsen (billionai) /* HDECR */ 621a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 62237f219c8SBruno Larsen (billionai) { 623f5b6daacSRichard Henderson gen_icount_io_start(ctx); 62437f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 62537f219c8SBruno Larsen (billionai) } 62637f219c8SBruno Larsen (billionai) 627a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 62837f219c8SBruno Larsen (billionai) { 629f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63037f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 63137f219c8SBruno Larsen (billionai) } 63237f219c8SBruno Larsen (billionai) 633a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 63437f219c8SBruno Larsen (billionai) { 635f5b6daacSRichard Henderson gen_icount_io_start(ctx); 63637f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 63737f219c8SBruno Larsen (billionai) } 63837f219c8SBruno Larsen (billionai) 639a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 64037f219c8SBruno Larsen (billionai) { 641f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64237f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 64337f219c8SBruno Larsen (billionai) } 64437f219c8SBruno Larsen (billionai) 645a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 64637f219c8SBruno Larsen (billionai) { 647f5b6daacSRichard Henderson gen_icount_io_start(ctx); 64837f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 64937f219c8SBruno Larsen (billionai) } 65037f219c8SBruno Larsen (billionai) 65137f219c8SBruno Larsen (billionai) #endif 65237f219c8SBruno Larsen (billionai) #endif 65337f219c8SBruno Larsen (billionai) 65437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 65537f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 65637f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 657a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 65837f219c8SBruno Larsen (billionai) { 65937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66137f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 66237f219c8SBruno Larsen (billionai) } 66337f219c8SBruno Larsen (billionai) 664a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 66537f219c8SBruno Larsen (billionai) { 66637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 66737f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 66837f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 66937f219c8SBruno Larsen (billionai) } 67037f219c8SBruno Larsen (billionai) 671a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 67237f219c8SBruno Larsen (billionai) { 67337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 67437f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 67537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 67637f219c8SBruno Larsen (billionai) } 67737f219c8SBruno Larsen (billionai) 678a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 67937f219c8SBruno Larsen (billionai) { 68037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 68137f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 68237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 68337f219c8SBruno Larsen (billionai) } 68437f219c8SBruno Larsen (billionai) 685a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 68637f219c8SBruno Larsen (billionai) { 68737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 68837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 68937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69037f219c8SBruno Larsen (billionai) } 69137f219c8SBruno Larsen (billionai) 692a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 69337f219c8SBruno Larsen (billionai) { 69437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 69537f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 69637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 69737f219c8SBruno Larsen (billionai) } 69837f219c8SBruno Larsen (billionai) 69937f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 70037f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 701a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 70237f219c8SBruno Larsen (billionai) { 70337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 70437f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 70537f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 70637f219c8SBruno Larsen (billionai) } 70737f219c8SBruno Larsen (billionai) 708a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 70937f219c8SBruno Larsen (billionai) { 71037f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 71137f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 71237f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 71337f219c8SBruno Larsen (billionai) } 71437f219c8SBruno Larsen (billionai) 715a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 71637f219c8SBruno Larsen (billionai) { 71737f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 71837f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 71937f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72037f219c8SBruno Larsen (billionai) } 72137f219c8SBruno Larsen (billionai) 722a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 72337f219c8SBruno Larsen (billionai) { 72437f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 72537f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 72637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 72737f219c8SBruno Larsen (billionai) } 72837f219c8SBruno Larsen (billionai) 729a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 73037f219c8SBruno Larsen (billionai) { 73137f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 73237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 73337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 73437f219c8SBruno Larsen (billionai) } 73537f219c8SBruno Larsen (billionai) 736a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 73737f219c8SBruno Larsen (billionai) { 73837f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 73937f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 74037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 74137f219c8SBruno Larsen (billionai) } 74237f219c8SBruno Larsen (billionai) 74337f219c8SBruno Larsen (billionai) /* SDR1 */ 744a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 74537f219c8SBruno Larsen (billionai) { 74637f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 74737f219c8SBruno Larsen (billionai) } 74837f219c8SBruno Larsen (billionai) 74937f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 75037f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 75137f219c8SBruno Larsen (billionai) /* PIDR */ 752a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 75337f219c8SBruno Larsen (billionai) { 75437f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 75537f219c8SBruno Larsen (billionai) } 75637f219c8SBruno Larsen (billionai) 757a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 75837f219c8SBruno Larsen (billionai) { 75937f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 76037f219c8SBruno Larsen (billionai) } 76137f219c8SBruno Larsen (billionai) 762a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 76337f219c8SBruno Larsen (billionai) { 76437f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 76537f219c8SBruno Larsen (billionai) } 76637f219c8SBruno Larsen (billionai) 767a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 76837f219c8SBruno Larsen (billionai) { 76937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 77037f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 77137f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 77237f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 77337f219c8SBruno Larsen (billionai) } 774a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 77537f219c8SBruno Larsen (billionai) { 77637f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 77737f219c8SBruno Larsen (billionai) } 77837f219c8SBruno Larsen (billionai) 779a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 78037f219c8SBruno Larsen (billionai) { 78137f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 78237f219c8SBruno Larsen (billionai) } 78337f219c8SBruno Larsen (billionai) 78437f219c8SBruno Larsen (billionai) /* DPDES */ 785a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 78637f219c8SBruno Larsen (billionai) { 78737f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 78837f219c8SBruno Larsen (billionai) } 78937f219c8SBruno Larsen (billionai) 790a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 79137f219c8SBruno Larsen (billionai) { 79237f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) #endif 79537f219c8SBruno Larsen (billionai) #endif 79637f219c8SBruno Larsen (billionai) 79737f219c8SBruno Larsen (billionai) /* PowerPC 601 specific registers */ 79837f219c8SBruno Larsen (billionai) /* RTC */ 799a829cec3SBruno Larsen (billionai) void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 80037f219c8SBruno Larsen (billionai) { 80137f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 80237f219c8SBruno Larsen (billionai) } 80337f219c8SBruno Larsen (billionai) 804a829cec3SBruno Larsen (billionai) void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 80537f219c8SBruno Larsen (billionai) { 80637f219c8SBruno Larsen (billionai) gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 80737f219c8SBruno Larsen (billionai) } 80837f219c8SBruno Larsen (billionai) 80937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 810a829cec3SBruno Larsen (billionai) void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 81137f219c8SBruno Larsen (billionai) { 81237f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 81337f219c8SBruno Larsen (billionai) } 81437f219c8SBruno Larsen (billionai) 815a829cec3SBruno Larsen (billionai) void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 81637f219c8SBruno Larsen (billionai) { 81737f219c8SBruno Larsen (billionai) gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 81837f219c8SBruno Larsen (billionai) } 81937f219c8SBruno Larsen (billionai) 820a829cec3SBruno Larsen (billionai) void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 82137f219c8SBruno Larsen (billionai) { 82237f219c8SBruno Larsen (billionai) gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 82337f219c8SBruno Larsen (billionai) /* Must stop the translation as endianness may have changed */ 824d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 82537f219c8SBruno Larsen (billionai) } 82637f219c8SBruno Larsen (billionai) #endif 82737f219c8SBruno Larsen (billionai) 82837f219c8SBruno Larsen (billionai) /* Unified bats */ 82937f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 830a829cec3SBruno Larsen (billionai) void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 83137f219c8SBruno Larsen (billionai) { 83237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 83337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 83437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 83537f219c8SBruno Larsen (billionai) } 83637f219c8SBruno Larsen (billionai) 837a829cec3SBruno Larsen (billionai) void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 83837f219c8SBruno Larsen (billionai) { 83937f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 84037f219c8SBruno Larsen (billionai) gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 84137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 84237f219c8SBruno Larsen (billionai) } 84337f219c8SBruno Larsen (billionai) 844a829cec3SBruno Larsen (billionai) void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 84537f219c8SBruno Larsen (billionai) { 84637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 84737f219c8SBruno Larsen (billionai) gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 84837f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 84937f219c8SBruno Larsen (billionai) } 85037f219c8SBruno Larsen (billionai) #endif 85137f219c8SBruno Larsen (billionai) 85237f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 85337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 854a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 85537f219c8SBruno Larsen (billionai) { 856f5b6daacSRichard Henderson gen_icount_io_start(ctx); 85737f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 85837f219c8SBruno Larsen (billionai) } 85937f219c8SBruno Larsen (billionai) 860a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 86137f219c8SBruno Larsen (billionai) { 862f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86337f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 86437f219c8SBruno Larsen (billionai) } 86537f219c8SBruno Larsen (billionai) 866a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 86737f219c8SBruno Larsen (billionai) { 868f5b6daacSRichard Henderson gen_icount_io_start(ctx); 86937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 87037f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 87137f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 872d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 87337f219c8SBruno Larsen (billionai) } 87437f219c8SBruno Larsen (billionai) 875a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 87637f219c8SBruno Larsen (billionai) { 877f5b6daacSRichard Henderson gen_icount_io_start(ctx); 87837f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 87937f219c8SBruno Larsen (billionai) } 88037f219c8SBruno Larsen (billionai) 881a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 88237f219c8SBruno Larsen (billionai) { 883f5b6daacSRichard Henderson gen_icount_io_start(ctx); 88437f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 88537f219c8SBruno Larsen (billionai) } 88637f219c8SBruno Larsen (billionai) 887a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 88837f219c8SBruno Larsen (billionai) { 889f5b6daacSRichard Henderson gen_icount_io_start(ctx); 89037f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 89137f219c8SBruno Larsen (billionai) } 89237f219c8SBruno Larsen (billionai) #endif 89337f219c8SBruno Larsen (billionai) 89437f219c8SBruno Larsen (billionai) /* PowerPC 403 specific registers */ 89537f219c8SBruno Larsen (billionai) /* PBL1 / PBU1 / PBL2 / PBU2 */ 89637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 897a829cec3SBruno Larsen (billionai) void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 89837f219c8SBruno Larsen (billionai) { 89937f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 90037f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 90137f219c8SBruno Larsen (billionai) } 90237f219c8SBruno Larsen (billionai) 903a829cec3SBruno Larsen (billionai) void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 90437f219c8SBruno Larsen (billionai) { 90537f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 90637f219c8SBruno Larsen (billionai) gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 90737f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 90837f219c8SBruno Larsen (billionai) } 90937f219c8SBruno Larsen (billionai) 910a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 91137f219c8SBruno Larsen (billionai) { 91237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 91337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 91437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 91537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 91637f219c8SBruno Larsen (billionai) } 91737f219c8SBruno Larsen (billionai) #endif 91837f219c8SBruno Larsen (billionai) 91937f219c8SBruno Larsen (billionai) /* SPE specific registers */ 920a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 92137f219c8SBruno Larsen (billionai) { 92237f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 92337f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 92437f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 92537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 92637f219c8SBruno Larsen (billionai) } 92737f219c8SBruno Larsen (billionai) 928a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 92937f219c8SBruno Larsen (billionai) { 93037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 93137f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 93237f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 93337f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 93437f219c8SBruno Larsen (billionai) } 93537f219c8SBruno Larsen (billionai) 93637f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 93737f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 938a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 93937f219c8SBruno Larsen (billionai) { 94037f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 94137f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 94237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 94337f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 94437f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 94537f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 94637f219c8SBruno Larsen (billionai) } 94737f219c8SBruno Larsen (billionai) 948a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 94937f219c8SBruno Larsen (billionai) { 95037f219c8SBruno Larsen (billionai) int sprn_offs; 95137f219c8SBruno Larsen (billionai) 95237f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 95337f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 95437f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 95537f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 95637f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 95737f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 95837f219c8SBruno Larsen (billionai) } else { 95937f219c8SBruno Larsen (billionai) printf("Trying to write an unknown exception vector %d %03x\n", 96037f219c8SBruno Larsen (billionai) sprn, sprn); 96137f219c8SBruno Larsen (billionai) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 96237f219c8SBruno Larsen (billionai) return; 96337f219c8SBruno Larsen (billionai) } 96437f219c8SBruno Larsen (billionai) 96537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 96637f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 96737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 96837f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 96937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 97037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 97137f219c8SBruno Larsen (billionai) } 97237f219c8SBruno Larsen (billionai) #endif 97337f219c8SBruno Larsen (billionai) 97437f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 97537f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 976a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 97737f219c8SBruno Larsen (billionai) { 97837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 98037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 98137f219c8SBruno Larsen (billionai) 98237f219c8SBruno Larsen (billionai) /* 98337f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 98437f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 98537f219c8SBruno Larsen (billionai) */ 98637f219c8SBruno Larsen (billionai) 98737f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 98837f219c8SBruno Larsen (billionai) if (ctx->pr) { 98937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 99037f219c8SBruno Larsen (billionai) } else { 99137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 99237f219c8SBruno Larsen (billionai) } 99337f219c8SBruno Larsen (billionai) 99437f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 99537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 99637f219c8SBruno Larsen (billionai) 99737f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 99837f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 99937f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 100037f219c8SBruno Larsen (billionai) 100137f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 100237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 100337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 100437f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 100537f219c8SBruno Larsen (billionai) 100637f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 100737f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 100837f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 100937f219c8SBruno Larsen (billionai) } 101037f219c8SBruno Larsen (billionai) 1011a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 101237f219c8SBruno Larsen (billionai) { 101337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 101437f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 101537f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 101637f219c8SBruno Larsen (billionai) 101737f219c8SBruno Larsen (billionai) /* 101837f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 101937f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 102037f219c8SBruno Larsen (billionai) */ 102137f219c8SBruno Larsen (billionai) 102237f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 102337f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 102437f219c8SBruno Larsen (billionai) 102537f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 102637f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 102737f219c8SBruno Larsen (billionai) 102837f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 102937f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 103037f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 103137f219c8SBruno Larsen (billionai) 103237f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 103337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 103437f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 103537f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 103637f219c8SBruno Larsen (billionai) 103737f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 103837f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 103937f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 104037f219c8SBruno Larsen (billionai) } 104137f219c8SBruno Larsen (billionai) 1042a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 104337f219c8SBruno Larsen (billionai) { 104437f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 104537f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 104637f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 104737f219c8SBruno Larsen (billionai) 104837f219c8SBruno Larsen (billionai) /* 104937f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 105037f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 105137f219c8SBruno Larsen (billionai) */ 105237f219c8SBruno Larsen (billionai) 105337f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 105437f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 105537f219c8SBruno Larsen (billionai) 105637f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 105737f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 105837f219c8SBruno Larsen (billionai) 105937f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 106037f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 106137f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 106237f219c8SBruno Larsen (billionai) 106337f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 106437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 106537f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 106637f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 106737f219c8SBruno Larsen (billionai) 106837f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 106937f219c8SBruno Larsen (billionai) tcg_temp_free(t1); 107037f219c8SBruno Larsen (billionai) tcg_temp_free(t2); 107137f219c8SBruno Larsen (billionai) } 107237f219c8SBruno Larsen (billionai) #endif 107337f219c8SBruno Larsen (billionai) #endif 107437f219c8SBruno Larsen (billionai) 107537f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1076a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 107737f219c8SBruno Larsen (billionai) { 107837f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 107937f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 108037f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 108137f219c8SBruno Larsen (billionai) } 108237f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 108337f219c8SBruno Larsen (billionai) 108437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1085a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 108637f219c8SBruno Larsen (billionai) { 108737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108837f219c8SBruno Larsen (billionai) 108937f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 109037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109137f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 109237f219c8SBruno Larsen (billionai) } 109337f219c8SBruno Larsen (billionai) 1094a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 109537f219c8SBruno Larsen (billionai) { 109637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109737f219c8SBruno Larsen (billionai) 109837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 109937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 110037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 110137f219c8SBruno Larsen (billionai) } 110237f219c8SBruno Larsen (billionai) 1103a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 110437f219c8SBruno Larsen (billionai) { 110537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 110637f219c8SBruno Larsen (billionai) 110737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 110837f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 110937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 111037f219c8SBruno Larsen (billionai) tcg_temp_free(t0); 111137f219c8SBruno Larsen (billionai) } 111237f219c8SBruno Larsen (billionai) 1113a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 111437f219c8SBruno Larsen (billionai) { 111537f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 111637f219c8SBruno Larsen (billionai) } 111737f219c8SBruno Larsen (billionai) 1118a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 111937f219c8SBruno Larsen (billionai) { 112037f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_const_i32(sprn); 112137f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 112237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t0); 112337f219c8SBruno Larsen (billionai) } 1124a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 112537f219c8SBruno Larsen (billionai) { 112637f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 112737f219c8SBruno Larsen (billionai) } 1128a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 112937f219c8SBruno Larsen (billionai) { 113037f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 113137f219c8SBruno Larsen (billionai) } 113237f219c8SBruno Larsen (billionai) 113337f219c8SBruno Larsen (billionai) #endif 113437f219c8SBruno Larsen (billionai) 113537f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1136a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 113737f219c8SBruno Larsen (billionai) { 113837f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 113937f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 114037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 114137f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 114237f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 114337f219c8SBruno Larsen (billionai) tcg_temp_free(val); 114437f219c8SBruno Larsen (billionai) } 114537f219c8SBruno Larsen (billionai) 1146a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 114737f219c8SBruno Larsen (billionai) { 114837f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 114937f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 115037f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 115137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 115237f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 115337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 115437f219c8SBruno Larsen (billionai) tcg_temp_free(mas3); 115537f219c8SBruno Larsen (billionai) tcg_temp_free(mas7); 115637f219c8SBruno Larsen (billionai) } 115737f219c8SBruno Larsen (billionai) 115837f219c8SBruno Larsen (billionai) #endif 115937f219c8SBruno Larsen (billionai) 116037f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 116137f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 116237f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116337f219c8SBruno Larsen (billionai) { 116437f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 116537f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 116637f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 116737f219c8SBruno Larsen (billionai) 116837f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 116937f219c8SBruno Larsen (billionai) 117037f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 117137f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 117237f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 117337f219c8SBruno Larsen (billionai) } 117437f219c8SBruno Larsen (billionai) 117537f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 117637f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 117737f219c8SBruno Larsen (billionai) { 117837f219c8SBruno Larsen (billionai) TCGv_i32 t1 = tcg_const_i32(bit); 117937f219c8SBruno Larsen (billionai) TCGv_i32 t2 = tcg_const_i32(sprn); 118037f219c8SBruno Larsen (billionai) TCGv_i32 t3 = tcg_const_i32(cause); 118137f219c8SBruno Larsen (billionai) 118237f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 118337f219c8SBruno Larsen (billionai) 118437f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t3); 118537f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t2); 118637f219c8SBruno Larsen (billionai) tcg_temp_free_i32(t1); 118737f219c8SBruno Larsen (billionai) } 118837f219c8SBruno Larsen (billionai) 1189a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 119037f219c8SBruno Larsen (billionai) { 119137f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 119237f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 119337f219c8SBruno Larsen (billionai) 119437f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 119537f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 119637f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 119737f219c8SBruno Larsen (billionai) 119837f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 119937f219c8SBruno Larsen (billionai) tcg_temp_free(spr_up); 120037f219c8SBruno Larsen (billionai) } 120137f219c8SBruno Larsen (billionai) 1202a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 120337f219c8SBruno Larsen (billionai) { 120437f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 120537f219c8SBruno Larsen (billionai) 120637f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 120737f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 120837f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 120937f219c8SBruno Larsen (billionai) 121037f219c8SBruno Larsen (billionai) tcg_temp_free(spr); 121137f219c8SBruno Larsen (billionai) } 121237f219c8SBruno Larsen (billionai) 121337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1214a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 121537f219c8SBruno Larsen (billionai) { 121637f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 121737f219c8SBruno Larsen (billionai) 121837f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 121937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 122037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 122137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 122237f219c8SBruno Larsen (billionai) tcg_temp_free(hmer); 122337f219c8SBruno Larsen (billionai) } 122437f219c8SBruno Larsen (billionai) 1225a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 122637f219c8SBruno Larsen (billionai) { 122737f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 122837f219c8SBruno Larsen (billionai) } 122937f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 123037f219c8SBruno Larsen (billionai) 1231a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 123237f219c8SBruno Larsen (billionai) { 123337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 123437f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123537f219c8SBruno Larsen (billionai) } 123637f219c8SBruno Larsen (billionai) 1237a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 123837f219c8SBruno Larsen (billionai) { 123937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 124037f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124137f219c8SBruno Larsen (billionai) } 124237f219c8SBruno Larsen (billionai) 1243a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 124437f219c8SBruno Larsen (billionai) { 124537f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 124737f219c8SBruno Larsen (billionai) } 124837f219c8SBruno Larsen (billionai) 1249a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 125037f219c8SBruno Larsen (billionai) { 125137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 125337f219c8SBruno Larsen (billionai) } 125437f219c8SBruno Larsen (billionai) 1255a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 125637f219c8SBruno Larsen (billionai) { 125737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 125937f219c8SBruno Larsen (billionai) } 126037f219c8SBruno Larsen (billionai) 1261a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 126237f219c8SBruno Larsen (billionai) { 126337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 126437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 126537f219c8SBruno Larsen (billionai) } 126637f219c8SBruno Larsen (billionai) 1267a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 126837f219c8SBruno Larsen (billionai) { 126937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 127137f219c8SBruno Larsen (billionai) } 127237f219c8SBruno Larsen (billionai) 1273a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 127437f219c8SBruno Larsen (billionai) { 127537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 127737f219c8SBruno Larsen (billionai) } 127837f219c8SBruno Larsen (billionai) 1279a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 128037f219c8SBruno Larsen (billionai) { 128137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 128237f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 128337f219c8SBruno Larsen (billionai) } 128437f219c8SBruno Larsen (billionai) 1285a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 128637f219c8SBruno Larsen (billionai) { 128737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 128837f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 128937f219c8SBruno Larsen (billionai) } 129037f219c8SBruno Larsen (billionai) #endif 129137f219c8SBruno Larsen (billionai) 1292fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1293fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1294fcf5ef2aSThomas Huth 1295fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1296fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1297fcf5ef2aSThomas Huth 1298fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1299fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1300fcf5ef2aSThomas Huth 1301fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1302fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1303fcf5ef2aSThomas Huth 1304fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1305fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1306fcf5ef2aSThomas Huth 1307fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1308fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1309fcf5ef2aSThomas Huth 1310fcf5ef2aSThomas Huth typedef struct opcode_t { 1311fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1312fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1313fcf5ef2aSThomas Huth unsigned char pad[4]; 1314fcf5ef2aSThomas Huth #endif 1315fcf5ef2aSThomas Huth opc_handler_t handler; 1316fcf5ef2aSThomas Huth const char *oname; 1317fcf5ef2aSThomas Huth } opcode_t; 1318fcf5ef2aSThomas Huth 1319fcf5ef2aSThomas Huth /* Helpers for priv. check */ 1320fcf5ef2aSThomas Huth #define GEN_PRIV \ 1321fcf5ef2aSThomas Huth do { \ 1322fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 1323fcf5ef2aSThomas Huth } while (0) 1324fcf5ef2aSThomas Huth 1325fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 1326fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 1327fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 1328fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 1329fcf5ef2aSThomas Huth #else 1330fcf5ef2aSThomas Huth #define CHK_HV \ 1331fcf5ef2aSThomas Huth do { \ 1332fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 1333fcf5ef2aSThomas Huth GEN_PRIV; \ 1334fcf5ef2aSThomas Huth } \ 1335fcf5ef2aSThomas Huth } while (0) 1336fcf5ef2aSThomas Huth #define CHK_SV \ 1337fcf5ef2aSThomas Huth do { \ 1338fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 1339fcf5ef2aSThomas Huth GEN_PRIV; \ 1340fcf5ef2aSThomas Huth } \ 1341fcf5ef2aSThomas Huth } while (0) 1342fcf5ef2aSThomas Huth #define CHK_HVRM \ 1343fcf5ef2aSThomas Huth do { \ 1344fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 1345fcf5ef2aSThomas Huth GEN_PRIV; \ 1346fcf5ef2aSThomas Huth } \ 1347fcf5ef2aSThomas Huth } while (0) 1348fcf5ef2aSThomas Huth #endif 1349fcf5ef2aSThomas Huth 1350fcf5ef2aSThomas Huth #define CHK_NONE 1351fcf5ef2aSThomas Huth 1352fcf5ef2aSThomas Huth /*****************************************************************************/ 1353fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1354fcf5ef2aSThomas Huth 1355fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1356fcf5ef2aSThomas Huth { \ 1357fcf5ef2aSThomas Huth .opc1 = op1, \ 1358fcf5ef2aSThomas Huth .opc2 = op2, \ 1359fcf5ef2aSThomas Huth .opc3 = op3, \ 1360fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1361fcf5ef2aSThomas Huth .handler = { \ 1362fcf5ef2aSThomas Huth .inval1 = invl, \ 1363fcf5ef2aSThomas Huth .type = _typ, \ 1364fcf5ef2aSThomas Huth .type2 = _typ2, \ 1365fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1366fcf5ef2aSThomas Huth }, \ 1367fcf5ef2aSThomas Huth .oname = stringify(name), \ 1368fcf5ef2aSThomas Huth } 1369fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1370fcf5ef2aSThomas Huth { \ 1371fcf5ef2aSThomas Huth .opc1 = op1, \ 1372fcf5ef2aSThomas Huth .opc2 = op2, \ 1373fcf5ef2aSThomas Huth .opc3 = op3, \ 1374fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1375fcf5ef2aSThomas Huth .handler = { \ 1376fcf5ef2aSThomas Huth .inval1 = invl1, \ 1377fcf5ef2aSThomas Huth .inval2 = invl2, \ 1378fcf5ef2aSThomas Huth .type = _typ, \ 1379fcf5ef2aSThomas Huth .type2 = _typ2, \ 1380fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1381fcf5ef2aSThomas Huth }, \ 1382fcf5ef2aSThomas Huth .oname = stringify(name), \ 1383fcf5ef2aSThomas Huth } 1384fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1385fcf5ef2aSThomas Huth { \ 1386fcf5ef2aSThomas Huth .opc1 = op1, \ 1387fcf5ef2aSThomas Huth .opc2 = op2, \ 1388fcf5ef2aSThomas Huth .opc3 = op3, \ 1389fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1390fcf5ef2aSThomas Huth .handler = { \ 1391fcf5ef2aSThomas Huth .inval1 = invl, \ 1392fcf5ef2aSThomas Huth .type = _typ, \ 1393fcf5ef2aSThomas Huth .type2 = _typ2, \ 1394fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1395fcf5ef2aSThomas Huth }, \ 1396fcf5ef2aSThomas Huth .oname = onam, \ 1397fcf5ef2aSThomas Huth } 1398fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1399fcf5ef2aSThomas Huth { \ 1400fcf5ef2aSThomas Huth .opc1 = op1, \ 1401fcf5ef2aSThomas Huth .opc2 = op2, \ 1402fcf5ef2aSThomas Huth .opc3 = op3, \ 1403fcf5ef2aSThomas Huth .opc4 = op4, \ 1404fcf5ef2aSThomas Huth .handler = { \ 1405fcf5ef2aSThomas Huth .inval1 = invl, \ 1406fcf5ef2aSThomas Huth .type = _typ, \ 1407fcf5ef2aSThomas Huth .type2 = _typ2, \ 1408fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1409fcf5ef2aSThomas Huth }, \ 1410fcf5ef2aSThomas Huth .oname = stringify(name), \ 1411fcf5ef2aSThomas Huth } 1412fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1413fcf5ef2aSThomas Huth { \ 1414fcf5ef2aSThomas Huth .opc1 = op1, \ 1415fcf5ef2aSThomas Huth .opc2 = op2, \ 1416fcf5ef2aSThomas Huth .opc3 = op3, \ 1417fcf5ef2aSThomas Huth .opc4 = op4, \ 1418fcf5ef2aSThomas Huth .handler = { \ 1419fcf5ef2aSThomas Huth .inval1 = invl, \ 1420fcf5ef2aSThomas Huth .type = _typ, \ 1421fcf5ef2aSThomas Huth .type2 = _typ2, \ 1422fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1423fcf5ef2aSThomas Huth }, \ 1424fcf5ef2aSThomas Huth .oname = onam, \ 1425fcf5ef2aSThomas Huth } 1426fcf5ef2aSThomas Huth 1427fcf5ef2aSThomas Huth /* Invalid instruction */ 1428fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1429fcf5ef2aSThomas Huth { 1430fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1431fcf5ef2aSThomas Huth } 1432fcf5ef2aSThomas Huth 1433fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1434fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1435fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1436fcf5ef2aSThomas Huth .type = PPC_NONE, 1437fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1438fcf5ef2aSThomas Huth .handler = gen_invalid, 1439fcf5ef2aSThomas Huth }; 1440fcf5ef2aSThomas Huth 1441fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1442fcf5ef2aSThomas Huth 1443fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1444fcf5ef2aSThomas Huth { 1445fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1446b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1447b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1448fcf5ef2aSThomas Huth 1449b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1450b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1451efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1452efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1453b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1454efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1455efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1456b62b3686Spbonzini@redhat.com 1457b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1458fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1459b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1460fcf5ef2aSThomas Huth 1461fcf5ef2aSThomas Huth tcg_temp_free(t0); 1462b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 1463b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 1464fcf5ef2aSThomas Huth } 1465fcf5ef2aSThomas Huth 1466fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1467fcf5ef2aSThomas Huth { 1468fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1469fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1470fcf5ef2aSThomas Huth tcg_temp_free(t0); 1471fcf5ef2aSThomas Huth } 1472fcf5ef2aSThomas Huth 1473fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1474fcf5ef2aSThomas Huth { 1475fcf5ef2aSThomas Huth TCGv t0, t1; 1476fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1477fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1478fcf5ef2aSThomas Huth if (s) { 1479fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1480fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1481fcf5ef2aSThomas Huth } else { 1482fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1483fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1484fcf5ef2aSThomas Huth } 1485fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1486fcf5ef2aSThomas Huth tcg_temp_free(t1); 1487fcf5ef2aSThomas Huth tcg_temp_free(t0); 1488fcf5ef2aSThomas Huth } 1489fcf5ef2aSThomas Huth 1490fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1491fcf5ef2aSThomas Huth { 1492fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 1493fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1494fcf5ef2aSThomas Huth tcg_temp_free(t0); 1495fcf5ef2aSThomas Huth } 1496fcf5ef2aSThomas Huth 1497fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1498fcf5ef2aSThomas Huth { 1499fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1500fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1501fcf5ef2aSThomas Huth } else { 1502fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1503fcf5ef2aSThomas Huth } 1504fcf5ef2aSThomas Huth } 1505fcf5ef2aSThomas Huth 1506fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1507fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1508fcf5ef2aSThomas Huth { 1509fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1510fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1511fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1512fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1513fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1514fcf5ef2aSThomas Huth 1515fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1516fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1517fcf5ef2aSThomas Huth 1518fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1519fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1520fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1521fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1522fcf5ef2aSThomas Huth 1523fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1524fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1525fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1526fcf5ef2aSThomas Huth 1527fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1528fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1529fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1530fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1531fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1532fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1533fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1534fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1535fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1536fcf5ef2aSThomas Huth } 1537efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1538fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 1539fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 1540fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 1541fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 1542fcf5ef2aSThomas Huth } 1543fcf5ef2aSThomas Huth 1544fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1545fcf5ef2aSThomas Huth /* cmpeqb */ 1546fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1547fcf5ef2aSThomas Huth { 1548fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1549fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1550fcf5ef2aSThomas Huth } 1551fcf5ef2aSThomas Huth #endif 1552fcf5ef2aSThomas Huth 1553fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1554fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1555fcf5ef2aSThomas Huth { 1556fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1557fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1558fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1559fcf5ef2aSThomas Huth TCGv zr; 1560fcf5ef2aSThomas Huth 1561fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1562fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1563fcf5ef2aSThomas Huth 1564fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 1565fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1566fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1567fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1568fcf5ef2aSThomas Huth tcg_temp_free(zr); 1569fcf5ef2aSThomas Huth tcg_temp_free(t0); 1570fcf5ef2aSThomas Huth } 1571fcf5ef2aSThomas Huth 1572fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1573fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1574fcf5ef2aSThomas Huth { 1575fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1576fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1577fcf5ef2aSThomas Huth } 1578fcf5ef2aSThomas Huth 1579fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1580fcf5ef2aSThomas Huth 1581fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1582fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1583fcf5ef2aSThomas Huth { 1584fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1585fcf5ef2aSThomas Huth 1586fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1587fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1588fcf5ef2aSThomas Huth if (sub) { 1589fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1590fcf5ef2aSThomas Huth } else { 1591fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1592fcf5ef2aSThomas Huth } 1593fcf5ef2aSThomas Huth tcg_temp_free(t0); 1594fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1595dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1596dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1597dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1598fcf5ef2aSThomas Huth } 1599dc0ad844SNikunj A Dadhania } else { 1600dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1601dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1602dc0ad844SNikunj A Dadhania } 160338a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1604dc0ad844SNikunj A Dadhania } 1605fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1606fcf5ef2aSThomas Huth } 1607fcf5ef2aSThomas Huth 16086b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 16096b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 16104c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 16116b10d008SNikunj A Dadhania { 16126b10d008SNikunj A Dadhania TCGv t0; 16136b10d008SNikunj A Dadhania 16146b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16156b10d008SNikunj A Dadhania return; 16166b10d008SNikunj A Dadhania } 16176b10d008SNikunj A Dadhania 16186b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 161933903d0aSNikunj A Dadhania if (sub) { 162033903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 162133903d0aSNikunj A Dadhania } else { 16226b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 162333903d0aSNikunj A Dadhania } 16246b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16254c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16266b10d008SNikunj A Dadhania tcg_temp_free(t0); 16276b10d008SNikunj A Dadhania } 16286b10d008SNikunj A Dadhania 1629fcf5ef2aSThomas Huth /* Common add function */ 1630fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16314c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16324c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1633fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1634fcf5ef2aSThomas Huth { 1635fcf5ef2aSThomas Huth TCGv t0 = ret; 1636fcf5ef2aSThomas Huth 1637fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1638fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1639fcf5ef2aSThomas Huth } 1640fcf5ef2aSThomas Huth 1641fcf5ef2aSThomas Huth if (compute_ca) { 1642fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1643efe843d8SDavid Gibson /* 1644efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1645efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1646efe843d8SDavid Gibson * produce the carry into bit 32. 1647efe843d8SDavid Gibson */ 1648fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1649fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1650fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1651fcf5ef2aSThomas Huth if (add_ca) { 16524c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1653fcf5ef2aSThomas Huth } 16544c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 1655fcf5ef2aSThomas Huth tcg_temp_free(t1); 16564c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16576b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16584c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16596b10d008SNikunj A Dadhania } 1660fcf5ef2aSThomas Huth } else { 1661fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1662fcf5ef2aSThomas Huth if (add_ca) { 16634c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16644c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1665fcf5ef2aSThomas Huth } else { 16664c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1667fcf5ef2aSThomas Huth } 16684c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1669fcf5ef2aSThomas Huth tcg_temp_free(zero); 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth } else { 1672fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1673fcf5ef2aSThomas Huth if (add_ca) { 16744c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1675fcf5ef2aSThomas Huth } 1676fcf5ef2aSThomas Huth } 1677fcf5ef2aSThomas Huth 1678fcf5ef2aSThomas Huth if (compute_ov) { 1679fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1680fcf5ef2aSThomas Huth } 1681fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1682fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1683fcf5ef2aSThomas Huth } 1684fcf5ef2aSThomas Huth 168511f4e8f8SRichard Henderson if (t0 != ret) { 1686fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1687fcf5ef2aSThomas Huth tcg_temp_free(t0); 1688fcf5ef2aSThomas Huth } 1689fcf5ef2aSThomas Huth } 1690fcf5ef2aSThomas Huth /* Add functions with two operands */ 16914c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1692fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1693fcf5ef2aSThomas Huth { \ 1694fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1695fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16964c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1697fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1698fcf5ef2aSThomas Huth } 1699fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 17004c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1701fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1702fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1703fcf5ef2aSThomas Huth { \ 1704fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1705fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1706fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 17074c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1708fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1709fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1710fcf5ef2aSThomas Huth } 1711fcf5ef2aSThomas Huth 1712fcf5ef2aSThomas Huth /* add add. addo addo. */ 17134c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17144c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1715fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17164c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17174c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1718fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17194c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17204c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1721fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17224c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17234c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17244c5920afSSuraj Jitindar Singh /* addex */ 17254c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1726fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17274c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17284c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1729fcf5ef2aSThomas Huth /* addic addic.*/ 1730fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1731fcf5ef2aSThomas Huth { 1732fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1733fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17344c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1735fcf5ef2aSThomas Huth tcg_temp_free(c); 1736fcf5ef2aSThomas Huth } 1737fcf5ef2aSThomas Huth 1738fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1739fcf5ef2aSThomas Huth { 1740fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1741fcf5ef2aSThomas Huth } 1742fcf5ef2aSThomas Huth 1743fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1744fcf5ef2aSThomas Huth { 1745fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1746fcf5ef2aSThomas Huth } 1747fcf5ef2aSThomas Huth 1748fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1749fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1750fcf5ef2aSThomas Huth { 1751fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1752fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1753fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1754fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1755fcf5ef2aSThomas Huth 1756fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1757fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1758fcf5ef2aSThomas Huth if (sign) { 1759fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1760fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1761fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1762fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1763fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1764fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1765fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1766fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1767fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1768fcf5ef2aSThomas Huth } else { 1769fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1770fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1771fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1772fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1773fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1774fcf5ef2aSThomas Huth } 1775fcf5ef2aSThomas Huth if (compute_ov) { 1776fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1777c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1778c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1779c44027ffSNikunj A Dadhania } 1780fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1781fcf5ef2aSThomas Huth } 1782fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1783fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1784fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1785fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1786fcf5ef2aSThomas Huth 1787efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1788fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1789fcf5ef2aSThomas Huth } 1790efe843d8SDavid Gibson } 1791fcf5ef2aSThomas Huth /* Div functions */ 1792fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1793fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1794fcf5ef2aSThomas Huth { \ 1795fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1796fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1797fcf5ef2aSThomas Huth sign, compute_ov); \ 1798fcf5ef2aSThomas Huth } 1799fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1800fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1801fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1802fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1803fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1804fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1805fcf5ef2aSThomas Huth 1806fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1807fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1808fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1809fcf5ef2aSThomas Huth { \ 1810fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1811fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1812fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1813fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1814fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1815fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1816fcf5ef2aSThomas Huth } \ 1817fcf5ef2aSThomas Huth } 1818fcf5ef2aSThomas Huth 1819fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1820fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1821fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1822fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1823fcf5ef2aSThomas Huth 1824fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1825fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1826fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1827fcf5ef2aSThomas Huth { 1828fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1829fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1830fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1831fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1832fcf5ef2aSThomas Huth 1833fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1834fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1835fcf5ef2aSThomas Huth if (sign) { 1836fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1837fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1838fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1839fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1840fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1841fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1842fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1843fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1844fcf5ef2aSThomas Huth } else { 1845fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1846fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1847fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1848fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1849fcf5ef2aSThomas Huth } 1850fcf5ef2aSThomas Huth if (compute_ov) { 1851fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1852c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1853c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1854c44027ffSNikunj A Dadhania } 1855fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1856fcf5ef2aSThomas Huth } 1857fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1858fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1859fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1860fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1861fcf5ef2aSThomas Huth 1862efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1863fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1864fcf5ef2aSThomas Huth } 1865efe843d8SDavid Gibson } 1866fcf5ef2aSThomas Huth 1867fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1868fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1869fcf5ef2aSThomas Huth { \ 1870fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1871fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1872fcf5ef2aSThomas Huth sign, compute_ov); \ 1873fcf5ef2aSThomas Huth } 1874c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1875fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1876fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1877c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1878fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1879fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1880fcf5ef2aSThomas Huth 1881fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1882fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1883fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1884fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1885fcf5ef2aSThomas Huth #endif 1886fcf5ef2aSThomas Huth 1887fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1888fcf5ef2aSThomas Huth TCGv arg2, int sign) 1889fcf5ef2aSThomas Huth { 1890fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1891fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1892fcf5ef2aSThomas Huth 1893fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1894fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1895fcf5ef2aSThomas Huth if (sign) { 1896fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1897fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1898fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1899fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1900fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1901fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1902fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1903fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1904fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1905fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1906fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1907fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1908fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1909fcf5ef2aSThomas Huth } else { 1910fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1911fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1912fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1913fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1914fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1915fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1916fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1917fcf5ef2aSThomas Huth } 1918fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1919fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1920fcf5ef2aSThomas Huth } 1921fcf5ef2aSThomas Huth 1922fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1923fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1924fcf5ef2aSThomas Huth { \ 1925fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1926fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1927fcf5ef2aSThomas Huth sign); \ 1928fcf5ef2aSThomas Huth } 1929fcf5ef2aSThomas Huth 1930fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1931fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1932fcf5ef2aSThomas Huth 1933fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1934fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1935fcf5ef2aSThomas Huth TCGv arg2, int sign) 1936fcf5ef2aSThomas Huth { 1937fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1938fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1939fcf5ef2aSThomas Huth 1940fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1941fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1942fcf5ef2aSThomas Huth if (sign) { 1943fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1944fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1945fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1946fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1947fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1948fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1949fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1950fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1951fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1952fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1953fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1954fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1955fcf5ef2aSThomas Huth } else { 1956fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1957fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1958fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1959fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1960fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1961fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1962fcf5ef2aSThomas Huth } 1963fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1964fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1965fcf5ef2aSThomas Huth } 1966fcf5ef2aSThomas Huth 1967fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1968fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1969fcf5ef2aSThomas Huth { \ 1970fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1971fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1972fcf5ef2aSThomas Huth sign); \ 1973fcf5ef2aSThomas Huth } 1974fcf5ef2aSThomas Huth 1975fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1976fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1977fcf5ef2aSThomas Huth #endif 1978fcf5ef2aSThomas Huth 1979fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1980fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1981fcf5ef2aSThomas Huth { 1982fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1983fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1984fcf5ef2aSThomas Huth 1985fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1986fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1987fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1988fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1989fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1990fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1991efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1992fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1993fcf5ef2aSThomas Huth } 1994efe843d8SDavid Gibson } 1995fcf5ef2aSThomas Huth 1996fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1997fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1998fcf5ef2aSThomas Huth { 1999fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2000fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2001fcf5ef2aSThomas Huth 2002fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2003fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2004fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 2005fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 2006fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2007fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2008efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2009fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2010fcf5ef2aSThomas Huth } 2011efe843d8SDavid Gibson } 2012fcf5ef2aSThomas Huth 2013fcf5ef2aSThomas Huth /* mullw mullw. */ 2014fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 2015fcf5ef2aSThomas Huth { 2016fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2017fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 2018fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 2019fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 2020fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 2021fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 2022fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2023fcf5ef2aSThomas Huth tcg_temp_free(t0); 2024fcf5ef2aSThomas Huth tcg_temp_free(t1); 2025fcf5ef2aSThomas Huth #else 2026fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2027fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2028fcf5ef2aSThomas Huth #endif 2029efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2030fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2031fcf5ef2aSThomas Huth } 2032efe843d8SDavid Gibson } 2033fcf5ef2aSThomas Huth 2034fcf5ef2aSThomas Huth /* mullwo mullwo. */ 2035fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2036fcf5ef2aSThomas Huth { 2037fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2038fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2039fcf5ef2aSThomas Huth 2040fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2041fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2042fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2043fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2044fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2045fcf5ef2aSThomas Huth #else 2046fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2047fcf5ef2aSThomas Huth #endif 2048fcf5ef2aSThomas Huth 2049fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2050fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2051fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 205261aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 205361aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 205461aa9a69SNikunj A Dadhania } 2055fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2056fcf5ef2aSThomas Huth 2057fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2058fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2059efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2060fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2061fcf5ef2aSThomas Huth } 2062efe843d8SDavid Gibson } 2063fcf5ef2aSThomas Huth 2064fcf5ef2aSThomas Huth /* mulli */ 2065fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2066fcf5ef2aSThomas Huth { 2067fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2068fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2069fcf5ef2aSThomas Huth } 2070fcf5ef2aSThomas Huth 2071fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2072fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2073fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2074fcf5ef2aSThomas Huth { 2075fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2076fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2077fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2078fcf5ef2aSThomas Huth tcg_temp_free(lo); 2079fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2080fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2081fcf5ef2aSThomas Huth } 2082fcf5ef2aSThomas Huth } 2083fcf5ef2aSThomas Huth 2084fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2085fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2086fcf5ef2aSThomas Huth { 2087fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2088fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2089fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2090fcf5ef2aSThomas Huth tcg_temp_free(lo); 2091fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2092fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2093fcf5ef2aSThomas Huth } 2094fcf5ef2aSThomas Huth } 2095fcf5ef2aSThomas Huth 2096fcf5ef2aSThomas Huth /* mulld mulld. */ 2097fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2098fcf5ef2aSThomas Huth { 2099fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2100fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2101efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2102fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2103fcf5ef2aSThomas Huth } 2104efe843d8SDavid Gibson } 2105fcf5ef2aSThomas Huth 2106fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2107fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2108fcf5ef2aSThomas Huth { 2109fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2110fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2111fcf5ef2aSThomas Huth 2112fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2113fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2114fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2115fcf5ef2aSThomas Huth 2116fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2117fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 211861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 211961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 212061aa9a69SNikunj A Dadhania } 2121fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2122fcf5ef2aSThomas Huth 2123fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2124fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 2125fcf5ef2aSThomas Huth 2126fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2127fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2128fcf5ef2aSThomas Huth } 2129fcf5ef2aSThomas Huth } 2130fcf5ef2aSThomas Huth #endif 2131fcf5ef2aSThomas Huth 2132fcf5ef2aSThomas Huth /* Common subf function */ 2133fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2134fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2135fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2136fcf5ef2aSThomas Huth { 2137fcf5ef2aSThomas Huth TCGv t0 = ret; 2138fcf5ef2aSThomas Huth 2139fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2140fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2141fcf5ef2aSThomas Huth } 2142fcf5ef2aSThomas Huth 2143fcf5ef2aSThomas Huth if (compute_ca) { 2144fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2145fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2146efe843d8SDavid Gibson /* 2147efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2148efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2149efe843d8SDavid Gibson * produce the carry into bit 32. 2150efe843d8SDavid Gibson */ 2151fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2152fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2153fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2154fcf5ef2aSThomas Huth if (add_ca) { 2155fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2156fcf5ef2aSThomas Huth } else { 2157fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2158fcf5ef2aSThomas Huth } 2159fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2160fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2161fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2162fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2163fcf5ef2aSThomas Huth tcg_temp_free(t1); 2164e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 216533903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 216633903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 216733903d0aSNikunj A Dadhania } 2168fcf5ef2aSThomas Huth } else if (add_ca) { 2169fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2170fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2171fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 2172fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2173fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21744c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2175fcf5ef2aSThomas Huth tcg_temp_free(zero); 2176fcf5ef2aSThomas Huth tcg_temp_free(inv1); 2177fcf5ef2aSThomas Huth } else { 2178fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2179fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21804c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2181fcf5ef2aSThomas Huth } 2182fcf5ef2aSThomas Huth } else if (add_ca) { 2183efe843d8SDavid Gibson /* 2184efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2185efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2186efe843d8SDavid Gibson */ 2187fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2188fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2189fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2190fcf5ef2aSThomas Huth } else { 2191fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2192fcf5ef2aSThomas Huth } 2193fcf5ef2aSThomas Huth 2194fcf5ef2aSThomas Huth if (compute_ov) { 2195fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2196fcf5ef2aSThomas Huth } 2197fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2198fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2199fcf5ef2aSThomas Huth } 2200fcf5ef2aSThomas Huth 220111f4e8f8SRichard Henderson if (t0 != ret) { 2202fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2203fcf5ef2aSThomas Huth tcg_temp_free(t0); 2204fcf5ef2aSThomas Huth } 2205fcf5ef2aSThomas Huth } 2206fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2207fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2208fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2209fcf5ef2aSThomas Huth { \ 2210fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2211fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2212fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2213fcf5ef2aSThomas Huth } 2214fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2215fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2216fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2217fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2218fcf5ef2aSThomas Huth { \ 2219fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 2220fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2221fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2222fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2223fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 2224fcf5ef2aSThomas Huth } 2225fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2226fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2227fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2228fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2229fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2230fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2231fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2232fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2233fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2234fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2235fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2236fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2237fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2238fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2239fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2240fcf5ef2aSThomas Huth 2241fcf5ef2aSThomas Huth /* subfic */ 2242fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2243fcf5ef2aSThomas Huth { 2244fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 2245fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2246fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2247fcf5ef2aSThomas Huth tcg_temp_free(c); 2248fcf5ef2aSThomas Huth } 2249fcf5ef2aSThomas Huth 2250fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2251fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2252fcf5ef2aSThomas Huth { 2253fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 2254fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2255fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2256fcf5ef2aSThomas Huth tcg_temp_free(zero); 2257fcf5ef2aSThomas Huth } 2258fcf5ef2aSThomas Huth 2259fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2260fcf5ef2aSThomas Huth { 22611480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22621480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22631480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22641480d71cSNikunj A Dadhania } 2265fcf5ef2aSThomas Huth } 2266fcf5ef2aSThomas Huth 2267fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2268fcf5ef2aSThomas Huth { 2269fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2270fcf5ef2aSThomas Huth } 2271fcf5ef2aSThomas Huth 2272fcf5ef2aSThomas Huth /*** Integer logical ***/ 2273fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2274fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2275fcf5ef2aSThomas Huth { \ 2276fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2277fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2278fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2279fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2280fcf5ef2aSThomas Huth } 2281fcf5ef2aSThomas Huth 2282fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2283fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2284fcf5ef2aSThomas Huth { \ 2285fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2286fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2287fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2288fcf5ef2aSThomas Huth } 2289fcf5ef2aSThomas Huth 2290fcf5ef2aSThomas Huth /* and & and. */ 2291fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2292fcf5ef2aSThomas Huth /* andc & andc. */ 2293fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2294fcf5ef2aSThomas Huth 2295fcf5ef2aSThomas Huth /* andi. */ 2296fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2297fcf5ef2aSThomas Huth { 2298efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2299efe843d8SDavid Gibson UIMM(ctx->opcode)); 2300fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2301fcf5ef2aSThomas Huth } 2302fcf5ef2aSThomas Huth 2303fcf5ef2aSThomas Huth /* andis. */ 2304fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2305fcf5ef2aSThomas Huth { 2306efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2307efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2308fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2309fcf5ef2aSThomas Huth } 2310fcf5ef2aSThomas Huth 2311fcf5ef2aSThomas Huth /* cntlzw */ 2312fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2313fcf5ef2aSThomas Huth { 23149b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23159b8514e5SRichard Henderson 23169b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23179b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 23189b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23199b8514e5SRichard Henderson tcg_temp_free_i32(t); 23209b8514e5SRichard Henderson 2321efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2322fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2323fcf5ef2aSThomas Huth } 2324efe843d8SDavid Gibson } 2325fcf5ef2aSThomas Huth 2326fcf5ef2aSThomas Huth /* cnttzw */ 2327fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2328fcf5ef2aSThomas Huth { 23299b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 23309b8514e5SRichard Henderson 23319b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 23329b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 23339b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 23349b8514e5SRichard Henderson tcg_temp_free_i32(t); 23359b8514e5SRichard Henderson 2336fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2337fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2338fcf5ef2aSThomas Huth } 2339fcf5ef2aSThomas Huth } 2340fcf5ef2aSThomas Huth 2341fcf5ef2aSThomas Huth /* eqv & eqv. */ 2342fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2343fcf5ef2aSThomas Huth /* extsb & extsb. */ 2344fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2345fcf5ef2aSThomas Huth /* extsh & extsh. */ 2346fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2347fcf5ef2aSThomas Huth /* nand & nand. */ 2348fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2349fcf5ef2aSThomas Huth /* nor & nor. */ 2350fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2351fcf5ef2aSThomas Huth 2352fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2353fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2354fcf5ef2aSThomas Huth { 2355fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 2356fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2357fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2358fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2359fcf5ef2aSThomas Huth 2360fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2361b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2362fcf5ef2aSThomas Huth } 2363fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2364fcf5ef2aSThomas Huth 2365fcf5ef2aSThomas Huth /* or & or. */ 2366fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2367fcf5ef2aSThomas Huth { 2368fcf5ef2aSThomas Huth int rs, ra, rb; 2369fcf5ef2aSThomas Huth 2370fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2371fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2372fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2373fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2374fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2375efe843d8SDavid Gibson if (rs != rb) { 2376fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2377efe843d8SDavid Gibson } else { 2378fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2379efe843d8SDavid Gibson } 2380efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2381fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2382efe843d8SDavid Gibson } 2383fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2384fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2385fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2386fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2387fcf5ef2aSThomas Huth int prio = 0; 2388fcf5ef2aSThomas Huth 2389fcf5ef2aSThomas Huth switch (rs) { 2390fcf5ef2aSThomas Huth case 1: 2391fcf5ef2aSThomas Huth /* Set process priority to low */ 2392fcf5ef2aSThomas Huth prio = 2; 2393fcf5ef2aSThomas Huth break; 2394fcf5ef2aSThomas Huth case 6: 2395fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2396fcf5ef2aSThomas Huth prio = 3; 2397fcf5ef2aSThomas Huth break; 2398fcf5ef2aSThomas Huth case 2: 2399fcf5ef2aSThomas Huth /* Set process priority to normal */ 2400fcf5ef2aSThomas Huth prio = 4; 2401fcf5ef2aSThomas Huth break; 2402fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2403fcf5ef2aSThomas Huth case 31: 2404fcf5ef2aSThomas Huth if (!ctx->pr) { 2405fcf5ef2aSThomas Huth /* Set process priority to very low */ 2406fcf5ef2aSThomas Huth prio = 1; 2407fcf5ef2aSThomas Huth } 2408fcf5ef2aSThomas Huth break; 2409fcf5ef2aSThomas Huth case 5: 2410fcf5ef2aSThomas Huth if (!ctx->pr) { 2411fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2412fcf5ef2aSThomas Huth prio = 5; 2413fcf5ef2aSThomas Huth } 2414fcf5ef2aSThomas Huth break; 2415fcf5ef2aSThomas Huth case 3: 2416fcf5ef2aSThomas Huth if (!ctx->pr) { 2417fcf5ef2aSThomas Huth /* Set process priority to high */ 2418fcf5ef2aSThomas Huth prio = 6; 2419fcf5ef2aSThomas Huth } 2420fcf5ef2aSThomas Huth break; 2421fcf5ef2aSThomas Huth case 7: 2422fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2423fcf5ef2aSThomas Huth /* Set process priority to very high */ 2424fcf5ef2aSThomas Huth prio = 7; 2425fcf5ef2aSThomas Huth } 2426fcf5ef2aSThomas Huth break; 2427fcf5ef2aSThomas Huth #endif 2428fcf5ef2aSThomas Huth default: 2429fcf5ef2aSThomas Huth break; 2430fcf5ef2aSThomas Huth } 2431fcf5ef2aSThomas Huth if (prio) { 2432fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2433fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2434fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2435fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2436fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2437fcf5ef2aSThomas Huth tcg_temp_free(t0); 2438fcf5ef2aSThomas Huth } 2439fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2440efe843d8SDavid Gibson /* 2441efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2442efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2443efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2444efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2445fcf5ef2aSThomas Huth */ 2446fcf5ef2aSThomas Huth gen_pause(ctx); 2447fcf5ef2aSThomas Huth #endif 2448fcf5ef2aSThomas Huth #endif 2449fcf5ef2aSThomas Huth } 2450fcf5ef2aSThomas Huth } 2451fcf5ef2aSThomas Huth /* orc & orc. */ 2452fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2453fcf5ef2aSThomas Huth 2454fcf5ef2aSThomas Huth /* xor & xor. */ 2455fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2456fcf5ef2aSThomas Huth { 2457fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2458efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2459efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2460efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2461efe843d8SDavid Gibson } else { 2462fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2463efe843d8SDavid Gibson } 2464efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2465fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2466fcf5ef2aSThomas Huth } 2467efe843d8SDavid Gibson } 2468fcf5ef2aSThomas Huth 2469fcf5ef2aSThomas Huth /* ori */ 2470fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2471fcf5ef2aSThomas Huth { 2472fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2473fcf5ef2aSThomas Huth 2474fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2475fcf5ef2aSThomas Huth return; 2476fcf5ef2aSThomas Huth } 2477fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2478fcf5ef2aSThomas Huth } 2479fcf5ef2aSThomas Huth 2480fcf5ef2aSThomas Huth /* oris */ 2481fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2482fcf5ef2aSThomas Huth { 2483fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2484fcf5ef2aSThomas Huth 2485fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2486fcf5ef2aSThomas Huth /* NOP */ 2487fcf5ef2aSThomas Huth return; 2488fcf5ef2aSThomas Huth } 2489efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2490efe843d8SDavid Gibson uimm << 16); 2491fcf5ef2aSThomas Huth } 2492fcf5ef2aSThomas Huth 2493fcf5ef2aSThomas Huth /* xori */ 2494fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2495fcf5ef2aSThomas Huth { 2496fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2497fcf5ef2aSThomas Huth 2498fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2499fcf5ef2aSThomas Huth /* NOP */ 2500fcf5ef2aSThomas Huth return; 2501fcf5ef2aSThomas Huth } 2502fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2503fcf5ef2aSThomas Huth } 2504fcf5ef2aSThomas Huth 2505fcf5ef2aSThomas Huth /* xoris */ 2506fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2507fcf5ef2aSThomas Huth { 2508fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2509fcf5ef2aSThomas Huth 2510fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2511fcf5ef2aSThomas Huth /* NOP */ 2512fcf5ef2aSThomas Huth return; 2513fcf5ef2aSThomas Huth } 2514efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2515efe843d8SDavid Gibson uimm << 16); 2516fcf5ef2aSThomas Huth } 2517fcf5ef2aSThomas Huth 2518fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2519fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2520fcf5ef2aSThomas Huth { 2521fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2522fcf5ef2aSThomas Huth } 2523fcf5ef2aSThomas Huth 2524fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2525fcf5ef2aSThomas Huth { 252679770002SRichard Henderson #if defined(TARGET_PPC64) 2527fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 252879770002SRichard Henderson #else 252979770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 253079770002SRichard Henderson #endif 2531fcf5ef2aSThomas Huth } 2532fcf5ef2aSThomas Huth 2533fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2534fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2535fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2536fcf5ef2aSThomas Huth { 253779770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2538fcf5ef2aSThomas Huth } 2539fcf5ef2aSThomas Huth #endif 2540fcf5ef2aSThomas Huth 2541fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2542fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2543fcf5ef2aSThomas Huth { 2544fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2545fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2546fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2547fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2548fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2549fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2550fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2551fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2552fcf5ef2aSThomas Huth tcg_temp_free(t0); 2553fcf5ef2aSThomas Huth } 2554fcf5ef2aSThomas Huth 2555fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2556fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2557fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2558fcf5ef2aSThomas Huth { 2559fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2560fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2561fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2562fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2563fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2564fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2565fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2566fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2567fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2568fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2569fcf5ef2aSThomas Huth tcg_temp_free(t0); 2570fcf5ef2aSThomas Huth } 2571fcf5ef2aSThomas Huth #endif 2572fcf5ef2aSThomas Huth 2573fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2574fcf5ef2aSThomas Huth /* bpermd */ 2575fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2576fcf5ef2aSThomas Huth { 2577fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2578fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2579fcf5ef2aSThomas Huth } 2580fcf5ef2aSThomas Huth #endif 2581fcf5ef2aSThomas Huth 2582fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2583fcf5ef2aSThomas Huth /* extsw & extsw. */ 2584fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2585fcf5ef2aSThomas Huth 2586fcf5ef2aSThomas Huth /* cntlzd */ 2587fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2588fcf5ef2aSThomas Huth { 25899b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2590efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2591fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2592fcf5ef2aSThomas Huth } 2593efe843d8SDavid Gibson } 2594fcf5ef2aSThomas Huth 2595fcf5ef2aSThomas Huth /* cnttzd */ 2596fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2597fcf5ef2aSThomas Huth { 25989b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2599fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2600fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2601fcf5ef2aSThomas Huth } 2602fcf5ef2aSThomas Huth } 2603fcf5ef2aSThomas Huth 2604fcf5ef2aSThomas Huth /* darn */ 2605fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2606fcf5ef2aSThomas Huth { 2607fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2608fcf5ef2aSThomas Huth 26097e4357f6SRichard Henderson if (l > 2) { 26107e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 26117e4357f6SRichard Henderson } else { 2612f5b6daacSRichard Henderson gen_icount_io_start(ctx); 2613fcf5ef2aSThomas Huth if (l == 0) { 2614fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 26157e4357f6SRichard Henderson } else { 2616fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2617fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 26187e4357f6SRichard Henderson } 2619fcf5ef2aSThomas Huth } 2620fcf5ef2aSThomas Huth } 2621fcf5ef2aSThomas Huth #endif 2622fcf5ef2aSThomas Huth 2623fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2624fcf5ef2aSThomas Huth 2625fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2626fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2627fcf5ef2aSThomas Huth { 2628fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2629fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2630fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2631fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2632fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2633fcf5ef2aSThomas Huth 2634fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2635fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2636fcf5ef2aSThomas Huth } else { 2637fcf5ef2aSThomas Huth target_ulong mask; 2638c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2639fcf5ef2aSThomas Huth TCGv t1; 2640fcf5ef2aSThomas Huth 2641fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2642fcf5ef2aSThomas Huth mb += 32; 2643fcf5ef2aSThomas Huth me += 32; 2644fcf5ef2aSThomas Huth #endif 2645fcf5ef2aSThomas Huth mask = MASK(mb, me); 2646fcf5ef2aSThomas Huth 2647c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2648c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2649c4f6a4a3SDaniele Buono mask_in_32b = false; 2650c4f6a4a3SDaniele Buono } 2651c4f6a4a3SDaniele Buono #endif 2652fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2653c4f6a4a3SDaniele Buono if (mask_in_32b) { 2654fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2655fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2656fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2657fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2658fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2659fcf5ef2aSThomas Huth } else { 2660fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2661fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2662fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2663fcf5ef2aSThomas Huth #else 2664fcf5ef2aSThomas Huth g_assert_not_reached(); 2665fcf5ef2aSThomas Huth #endif 2666fcf5ef2aSThomas Huth } 2667fcf5ef2aSThomas Huth 2668fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2669fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2670fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2671fcf5ef2aSThomas Huth tcg_temp_free(t1); 2672fcf5ef2aSThomas Huth } 2673fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2674fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2675fcf5ef2aSThomas Huth } 2676fcf5ef2aSThomas Huth } 2677fcf5ef2aSThomas Huth 2678fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2679fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2680fcf5ef2aSThomas Huth { 2681fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2682fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26837b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26847b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26857b4d326fSRichard Henderson int me = ME(ctx->opcode); 26867b4d326fSRichard Henderson int len = me - mb + 1; 26877b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2688fcf5ef2aSThomas Huth 26897b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26907b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26917b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26927b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2693fcf5ef2aSThomas Huth } else { 2694fcf5ef2aSThomas Huth target_ulong mask; 2695c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2696fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2697fcf5ef2aSThomas Huth mb += 32; 2698fcf5ef2aSThomas Huth me += 32; 2699fcf5ef2aSThomas Huth #endif 2700fcf5ef2aSThomas Huth mask = MASK(mb, me); 2701c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2702c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2703c4f6a4a3SDaniele Buono mask_in_32b = false; 2704c4f6a4a3SDaniele Buono } 2705c4f6a4a3SDaniele Buono #endif 2706c4f6a4a3SDaniele Buono if (mask_in_32b) { 27077b4d326fSRichard Henderson if (sh == 0) { 27087b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 270994f040aaSVitaly Chikunov } else { 2710fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2711fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2712fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2713fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2714fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 2715fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 271694f040aaSVitaly Chikunov } 2717fcf5ef2aSThomas Huth } else { 2718fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2719fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2720fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2721fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2722fcf5ef2aSThomas Huth #else 2723fcf5ef2aSThomas Huth g_assert_not_reached(); 2724fcf5ef2aSThomas Huth #endif 2725fcf5ef2aSThomas Huth } 2726fcf5ef2aSThomas Huth } 2727fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2728fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2729fcf5ef2aSThomas Huth } 2730fcf5ef2aSThomas Huth } 2731fcf5ef2aSThomas Huth 2732fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2733fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2734fcf5ef2aSThomas Huth { 2735fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2736fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2737fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2738fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2739fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2740fcf5ef2aSThomas Huth target_ulong mask; 2741c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2742fcf5ef2aSThomas Huth 2743fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2744fcf5ef2aSThomas Huth mb += 32; 2745fcf5ef2aSThomas Huth me += 32; 2746fcf5ef2aSThomas Huth #endif 2747fcf5ef2aSThomas Huth mask = MASK(mb, me); 2748fcf5ef2aSThomas Huth 2749c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2750c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2751c4f6a4a3SDaniele Buono mask_in_32b = false; 2752c4f6a4a3SDaniele Buono } 2753c4f6a4a3SDaniele Buono #endif 2754c4f6a4a3SDaniele Buono if (mask_in_32b) { 2755fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2756fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2757fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2758fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2759fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2760fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2761fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2762fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 2763fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2764fcf5ef2aSThomas Huth } else { 2765fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2766fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2767fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2768fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2769fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2770fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 2771fcf5ef2aSThomas Huth #else 2772fcf5ef2aSThomas Huth g_assert_not_reached(); 2773fcf5ef2aSThomas Huth #endif 2774fcf5ef2aSThomas Huth } 2775fcf5ef2aSThomas Huth 2776fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2777fcf5ef2aSThomas Huth 2778fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2779fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2780fcf5ef2aSThomas Huth } 2781fcf5ef2aSThomas Huth } 2782fcf5ef2aSThomas Huth 2783fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2784fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2785fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2786fcf5ef2aSThomas Huth { \ 2787fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2788fcf5ef2aSThomas Huth } \ 2789fcf5ef2aSThomas Huth \ 2790fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2791fcf5ef2aSThomas Huth { \ 2792fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2793fcf5ef2aSThomas Huth } 2794fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2795fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2796fcf5ef2aSThomas Huth { \ 2797fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2798fcf5ef2aSThomas Huth } \ 2799fcf5ef2aSThomas Huth \ 2800fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2801fcf5ef2aSThomas Huth { \ 2802fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2803fcf5ef2aSThomas Huth } \ 2804fcf5ef2aSThomas Huth \ 2805fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2806fcf5ef2aSThomas Huth { \ 2807fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2808fcf5ef2aSThomas Huth } \ 2809fcf5ef2aSThomas Huth \ 2810fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2811fcf5ef2aSThomas Huth { \ 2812fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2813fcf5ef2aSThomas Huth } 2814fcf5ef2aSThomas Huth 2815fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2816fcf5ef2aSThomas Huth { 2817fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2818fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 28197b4d326fSRichard Henderson int len = me - mb + 1; 28207b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2821fcf5ef2aSThomas Huth 28227b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 28237b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 28247b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 28257b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2826fcf5ef2aSThomas Huth } else { 2827fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2828fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2829fcf5ef2aSThomas Huth } 2830fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2831fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2832fcf5ef2aSThomas Huth } 2833fcf5ef2aSThomas Huth } 2834fcf5ef2aSThomas Huth 2835fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2836fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2837fcf5ef2aSThomas Huth { 2838fcf5ef2aSThomas Huth uint32_t sh, mb; 2839fcf5ef2aSThomas Huth 2840fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2841fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2842fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2843fcf5ef2aSThomas Huth } 2844fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2845fcf5ef2aSThomas Huth 2846fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2847fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2848fcf5ef2aSThomas Huth { 2849fcf5ef2aSThomas Huth uint32_t sh, me; 2850fcf5ef2aSThomas Huth 2851fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2852fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2853fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2854fcf5ef2aSThomas Huth } 2855fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2856fcf5ef2aSThomas Huth 2857fcf5ef2aSThomas Huth /* rldic - rldic. */ 2858fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2859fcf5ef2aSThomas Huth { 2860fcf5ef2aSThomas Huth uint32_t sh, mb; 2861fcf5ef2aSThomas Huth 2862fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2863fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2864fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2865fcf5ef2aSThomas Huth } 2866fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2867fcf5ef2aSThomas Huth 2868fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2869fcf5ef2aSThomas Huth { 2870fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2871fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2872fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2873fcf5ef2aSThomas Huth TCGv t0; 2874fcf5ef2aSThomas Huth 2875fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2876fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2877fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2878fcf5ef2aSThomas Huth tcg_temp_free(t0); 2879fcf5ef2aSThomas Huth 2880fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2881fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2882fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2883fcf5ef2aSThomas Huth } 2884fcf5ef2aSThomas Huth } 2885fcf5ef2aSThomas Huth 2886fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2887fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2888fcf5ef2aSThomas Huth { 2889fcf5ef2aSThomas Huth uint32_t mb; 2890fcf5ef2aSThomas Huth 2891fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2892fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2893fcf5ef2aSThomas Huth } 2894fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2895fcf5ef2aSThomas Huth 2896fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2897fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2898fcf5ef2aSThomas Huth { 2899fcf5ef2aSThomas Huth uint32_t me; 2900fcf5ef2aSThomas Huth 2901fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2902fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2903fcf5ef2aSThomas Huth } 2904fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2905fcf5ef2aSThomas Huth 2906fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2907fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2908fcf5ef2aSThomas Huth { 2909fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2910fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2911fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2912fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2913fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2914fcf5ef2aSThomas Huth 2915fcf5ef2aSThomas Huth if (mb <= me) { 2916fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2917fcf5ef2aSThomas Huth } else { 2918fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2919fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2920fcf5ef2aSThomas Huth 2921fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2922fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2923fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2924fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2925fcf5ef2aSThomas Huth tcg_temp_free(t1); 2926fcf5ef2aSThomas Huth } 2927fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2928fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2929fcf5ef2aSThomas Huth } 2930fcf5ef2aSThomas Huth } 2931fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2932fcf5ef2aSThomas Huth #endif 2933fcf5ef2aSThomas Huth 2934fcf5ef2aSThomas Huth /*** Integer shift ***/ 2935fcf5ef2aSThomas Huth 2936fcf5ef2aSThomas Huth /* slw & slw. */ 2937fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2938fcf5ef2aSThomas Huth { 2939fcf5ef2aSThomas Huth TCGv t0, t1; 2940fcf5ef2aSThomas Huth 2941fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2942fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2943fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2944fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2945fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2946fcf5ef2aSThomas Huth #else 2947fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2948fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2949fcf5ef2aSThomas Huth #endif 2950fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2951fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2952fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2953fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2954fcf5ef2aSThomas Huth tcg_temp_free(t1); 2955fcf5ef2aSThomas Huth tcg_temp_free(t0); 2956fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2957efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2958fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2959fcf5ef2aSThomas Huth } 2960efe843d8SDavid Gibson } 2961fcf5ef2aSThomas Huth 2962fcf5ef2aSThomas Huth /* sraw & sraw. */ 2963fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2964fcf5ef2aSThomas Huth { 2965fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2966fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2967efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2968fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2969fcf5ef2aSThomas Huth } 2970efe843d8SDavid Gibson } 2971fcf5ef2aSThomas Huth 2972fcf5ef2aSThomas Huth /* srawi & srawi. */ 2973fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2974fcf5ef2aSThomas Huth { 2975fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2976fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2977fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2978fcf5ef2aSThomas Huth if (sh == 0) { 2979fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2980fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2981af1c259fSSandipan Das if (is_isa300(ctx)) { 2982af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2983af1c259fSSandipan Das } 2984fcf5ef2aSThomas Huth } else { 2985fcf5ef2aSThomas Huth TCGv t0; 2986fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2987fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2988fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2989fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2990fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2991fcf5ef2aSThomas Huth tcg_temp_free(t0); 2992fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2993af1c259fSSandipan Das if (is_isa300(ctx)) { 2994af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2995af1c259fSSandipan Das } 2996fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2997fcf5ef2aSThomas Huth } 2998fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2999fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3000fcf5ef2aSThomas Huth } 3001fcf5ef2aSThomas Huth } 3002fcf5ef2aSThomas Huth 3003fcf5ef2aSThomas Huth /* srw & srw. */ 3004fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 3005fcf5ef2aSThomas Huth { 3006fcf5ef2aSThomas Huth TCGv t0, t1; 3007fcf5ef2aSThomas Huth 3008fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3009fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 3010fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3011fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 3012fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3013fcf5ef2aSThomas Huth #else 3014fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 3015fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 3016fcf5ef2aSThomas Huth #endif 3017fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3018fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 3019fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3020fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 3021fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3022fcf5ef2aSThomas Huth tcg_temp_free(t1); 3023fcf5ef2aSThomas Huth tcg_temp_free(t0); 3024efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3025fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3026fcf5ef2aSThomas Huth } 3027efe843d8SDavid Gibson } 3028fcf5ef2aSThomas Huth 3029fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3030fcf5ef2aSThomas Huth /* sld & sld. */ 3031fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 3032fcf5ef2aSThomas Huth { 3033fcf5ef2aSThomas Huth TCGv t0, t1; 3034fcf5ef2aSThomas Huth 3035fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3036fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3037fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3038fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3039fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3040fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3041fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3042fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3043fcf5ef2aSThomas Huth tcg_temp_free(t1); 3044fcf5ef2aSThomas Huth tcg_temp_free(t0); 3045efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3046fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3047fcf5ef2aSThomas Huth } 3048efe843d8SDavid Gibson } 3049fcf5ef2aSThomas Huth 3050fcf5ef2aSThomas Huth /* srad & srad. */ 3051fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 3052fcf5ef2aSThomas Huth { 3053fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 3054fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3055efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3056fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3057fcf5ef2aSThomas Huth } 3058efe843d8SDavid Gibson } 3059fcf5ef2aSThomas Huth /* sradi & sradi. */ 3060fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 3061fcf5ef2aSThomas Huth { 3062fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3063fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3064fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3065fcf5ef2aSThomas Huth if (sh == 0) { 3066fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 3067fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3068af1c259fSSandipan Das if (is_isa300(ctx)) { 3069af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 3070af1c259fSSandipan Das } 3071fcf5ef2aSThomas Huth } else { 3072fcf5ef2aSThomas Huth TCGv t0; 3073fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3074fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3075fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3076fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3077fcf5ef2aSThomas Huth tcg_temp_free(t0); 3078fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3079af1c259fSSandipan Das if (is_isa300(ctx)) { 3080af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3081af1c259fSSandipan Das } 3082fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3083fcf5ef2aSThomas Huth } 3084fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3085fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3086fcf5ef2aSThomas Huth } 3087fcf5ef2aSThomas Huth } 3088fcf5ef2aSThomas Huth 3089fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3090fcf5ef2aSThomas Huth { 3091fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3092fcf5ef2aSThomas Huth } 3093fcf5ef2aSThomas Huth 3094fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3095fcf5ef2aSThomas Huth { 3096fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3097fcf5ef2aSThomas Huth } 3098fcf5ef2aSThomas Huth 3099fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3100fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3101fcf5ef2aSThomas Huth { 3102fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3103fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3104fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3105fcf5ef2aSThomas Huth 3106fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3107fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3108fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3109fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3110fcf5ef2aSThomas Huth } 3111fcf5ef2aSThomas Huth } 3112fcf5ef2aSThomas Huth 3113fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3114fcf5ef2aSThomas Huth { 3115fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3116fcf5ef2aSThomas Huth } 3117fcf5ef2aSThomas Huth 3118fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3119fcf5ef2aSThomas Huth { 3120fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3121fcf5ef2aSThomas Huth } 3122fcf5ef2aSThomas Huth 3123fcf5ef2aSThomas Huth /* srd & srd. */ 3124fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3125fcf5ef2aSThomas Huth { 3126fcf5ef2aSThomas Huth TCGv t0, t1; 3127fcf5ef2aSThomas Huth 3128fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3129fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3130fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3131fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3132fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3133fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3134fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3135fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3136fcf5ef2aSThomas Huth tcg_temp_free(t1); 3137fcf5ef2aSThomas Huth tcg_temp_free(t0); 3138efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3139fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3140fcf5ef2aSThomas Huth } 3141efe843d8SDavid Gibson } 3142fcf5ef2aSThomas Huth #endif 3143fcf5ef2aSThomas Huth 3144fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3145fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3146fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3147fcf5ef2aSThomas Huth target_long maskl) 3148fcf5ef2aSThomas Huth { 3149fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3150fcf5ef2aSThomas Huth 3151fcf5ef2aSThomas Huth simm &= ~maskl; 3152fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3153fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3154fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3155fcf5ef2aSThomas Huth } 3156fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3157fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3158fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3159fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3160fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3161fcf5ef2aSThomas Huth } 3162fcf5ef2aSThomas Huth } else { 3163fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3164fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3165fcf5ef2aSThomas Huth } else { 3166fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3167fcf5ef2aSThomas Huth } 3168fcf5ef2aSThomas Huth } 3169fcf5ef2aSThomas Huth } 3170fcf5ef2aSThomas Huth 3171fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3172fcf5ef2aSThomas Huth { 3173fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3174fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3175fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3176fcf5ef2aSThomas Huth } else { 3177fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3178fcf5ef2aSThomas Huth } 3179fcf5ef2aSThomas Huth } else { 3180fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3181fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3182fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3183fcf5ef2aSThomas Huth } 3184fcf5ef2aSThomas Huth } 3185fcf5ef2aSThomas Huth } 3186fcf5ef2aSThomas Huth 3187fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3188fcf5ef2aSThomas Huth { 3189fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3190fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3191fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3192fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3193fcf5ef2aSThomas Huth } else { 3194fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3195fcf5ef2aSThomas Huth } 3196fcf5ef2aSThomas Huth } 3197fcf5ef2aSThomas Huth 3198fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3199fcf5ef2aSThomas Huth target_long val) 3200fcf5ef2aSThomas Huth { 3201fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3202fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3203fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3204fcf5ef2aSThomas Huth } 3205fcf5ef2aSThomas Huth } 3206fcf5ef2aSThomas Huth 3207fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3208fcf5ef2aSThomas Huth { 3209fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3210fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3211fcf5ef2aSThomas Huth } 3212fcf5ef2aSThomas Huth 3213eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3214eb63efd9SFernando Eckhardt Valle { 3215eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3216eb63efd9SFernando Eckhardt Valle if (ra) { 3217eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3218eb63efd9SFernando Eckhardt Valle } else { 3219eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3220eb63efd9SFernando Eckhardt Valle } 3221eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3222eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3223eb63efd9SFernando Eckhardt Valle } 3224eb63efd9SFernando Eckhardt Valle return ea; 3225eb63efd9SFernando Eckhardt Valle } 3226eb63efd9SFernando Eckhardt Valle 3227fcf5ef2aSThomas Huth /*** Integer load ***/ 3228fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3229fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3230fcf5ef2aSThomas Huth 3231fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3232fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3233fcf5ef2aSThomas Huth TCGv val, \ 3234fcf5ef2aSThomas Huth TCGv addr) \ 3235fcf5ef2aSThomas Huth { \ 3236fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3237fcf5ef2aSThomas Huth } 3238fcf5ef2aSThomas Huth 3239fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3240fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3241fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3242fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3243fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3244fcf5ef2aSThomas Huth 3245fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3246fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3247fcf5ef2aSThomas Huth 3248fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3249fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3250fcf5ef2aSThomas Huth TCGv_i64 val, \ 3251fcf5ef2aSThomas Huth TCGv addr) \ 3252fcf5ef2aSThomas Huth { \ 3253fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3254fcf5ef2aSThomas Huth } 3255fcf5ef2aSThomas Huth 3256fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3257fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3258fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3259fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3260fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 3261fcf5ef2aSThomas Huth 3262fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3263fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 3264fcf5ef2aSThomas Huth #endif 3265fcf5ef2aSThomas Huth 3266fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3267fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3268fcf5ef2aSThomas Huth TCGv val, \ 3269fcf5ef2aSThomas Huth TCGv addr) \ 3270fcf5ef2aSThomas Huth { \ 3271fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3272fcf5ef2aSThomas Huth } 3273fcf5ef2aSThomas Huth 3274e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3275fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3276e8f4c8d6SRichard Henderson #endif 3277fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3278fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3279fcf5ef2aSThomas Huth 3280fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3281fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3282fcf5ef2aSThomas Huth 3283fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3284fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3285fcf5ef2aSThomas Huth TCGv_i64 val, \ 3286fcf5ef2aSThomas Huth TCGv addr) \ 3287fcf5ef2aSThomas Huth { \ 3288fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3289fcf5ef2aSThomas Huth } 3290fcf5ef2aSThomas Huth 3291fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3292fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3293fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3294fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 3295fcf5ef2aSThomas Huth 3296fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3297fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 3298fcf5ef2aSThomas Huth #endif 3299fcf5ef2aSThomas Huth 3300fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3301fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3302fcf5ef2aSThomas Huth { \ 3303fcf5ef2aSThomas Huth TCGv EA; \ 3304fcf5ef2aSThomas Huth chk; \ 3305fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3306fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3307fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3308fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3309fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3310fcf5ef2aSThomas Huth } 3311fcf5ef2aSThomas Huth 3312fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3313fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3314fcf5ef2aSThomas Huth 3315fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3316fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3317fcf5ef2aSThomas Huth 331850728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 331950728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 332050728199SRoman Kapl { \ 332150728199SRoman Kapl TCGv EA; \ 332250728199SRoman Kapl CHK_SV; \ 332350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 332450728199SRoman Kapl EA = tcg_temp_new(); \ 332550728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 332650728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 332750728199SRoman Kapl tcg_temp_free(EA); \ 332850728199SRoman Kapl } 332950728199SRoman Kapl 333050728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 333150728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 333250728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 333350728199SRoman Kapl #if defined(TARGET_PPC64) 333450728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 333550728199SRoman Kapl #endif 333650728199SRoman Kapl 3337fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3338fcf5ef2aSThomas Huth /* CI load/store variants */ 3339fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3340fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3341fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3342fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3343fcf5ef2aSThomas Huth #endif 3344fcf5ef2aSThomas Huth 3345fcf5ef2aSThomas Huth /*** Integer store ***/ 3346fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3347fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3348fcf5ef2aSThomas Huth { \ 3349fcf5ef2aSThomas Huth TCGv EA; \ 3350fcf5ef2aSThomas Huth chk; \ 3351fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3352fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3353fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3354fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3355fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 3356fcf5ef2aSThomas Huth } 3357fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3358fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3359fcf5ef2aSThomas Huth 3360fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3361fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3362fcf5ef2aSThomas Huth 336350728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 336450728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 336550728199SRoman Kapl { \ 336650728199SRoman Kapl TCGv EA; \ 336750728199SRoman Kapl CHK_SV; \ 336850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 336950728199SRoman Kapl EA = tcg_temp_new(); \ 337050728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 337150728199SRoman Kapl tcg_gen_qemu_st_tl( \ 337250728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 337350728199SRoman Kapl tcg_temp_free(EA); \ 337450728199SRoman Kapl } 337550728199SRoman Kapl 337650728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 337750728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 337850728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 337950728199SRoman Kapl #if defined(TARGET_PPC64) 338050728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) 338150728199SRoman Kapl #endif 338250728199SRoman Kapl 3383fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3384fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3385fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3386fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3387fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3388fcf5ef2aSThomas Huth #endif 3389fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3390fcf5ef2aSThomas Huth 3391fcf5ef2aSThomas Huth /* lhbrx */ 3392fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3393fcf5ef2aSThomas Huth 3394fcf5ef2aSThomas Huth /* lwbrx */ 3395fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3396fcf5ef2aSThomas Huth 3397fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3398fcf5ef2aSThomas Huth /* ldbrx */ 3399fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3400fcf5ef2aSThomas Huth /* stdbrx */ 3401fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3402fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3403fcf5ef2aSThomas Huth 3404fcf5ef2aSThomas Huth /* sthbrx */ 3405fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3406fcf5ef2aSThomas Huth /* stwbrx */ 3407fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3408fcf5ef2aSThomas Huth 3409fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3410fcf5ef2aSThomas Huth 3411fcf5ef2aSThomas Huth /* lmw */ 3412fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3413fcf5ef2aSThomas Huth { 3414fcf5ef2aSThomas Huth TCGv t0; 3415fcf5ef2aSThomas Huth TCGv_i32 t1; 3416fcf5ef2aSThomas Huth 3417fcf5ef2aSThomas Huth if (ctx->le_mode) { 3418fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3419fcf5ef2aSThomas Huth return; 3420fcf5ef2aSThomas Huth } 3421fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3422fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3423fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3424fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3425fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3426fcf5ef2aSThomas Huth tcg_temp_free(t0); 3427fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3428fcf5ef2aSThomas Huth } 3429fcf5ef2aSThomas Huth 3430fcf5ef2aSThomas Huth /* stmw */ 3431fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3432fcf5ef2aSThomas Huth { 3433fcf5ef2aSThomas Huth TCGv t0; 3434fcf5ef2aSThomas Huth TCGv_i32 t1; 3435fcf5ef2aSThomas Huth 3436fcf5ef2aSThomas Huth if (ctx->le_mode) { 3437fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3438fcf5ef2aSThomas Huth return; 3439fcf5ef2aSThomas Huth } 3440fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3441fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3442fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 3443fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3444fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3445fcf5ef2aSThomas Huth tcg_temp_free(t0); 3446fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3447fcf5ef2aSThomas Huth } 3448fcf5ef2aSThomas Huth 3449fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3450fcf5ef2aSThomas Huth 3451fcf5ef2aSThomas Huth /* lswi */ 3452efe843d8SDavid Gibson /* 3453efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3454efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3455efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3456efe843d8SDavid Gibson * spec... 3457fcf5ef2aSThomas Huth */ 3458fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3459fcf5ef2aSThomas Huth { 3460fcf5ef2aSThomas Huth TCGv t0; 3461fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3462fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3463fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3464fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3465fcf5ef2aSThomas Huth int nr; 3466fcf5ef2aSThomas Huth 3467fcf5ef2aSThomas Huth if (ctx->le_mode) { 3468fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3469fcf5ef2aSThomas Huth return; 3470fcf5ef2aSThomas Huth } 3471efe843d8SDavid Gibson if (nb == 0) { 3472fcf5ef2aSThomas Huth nb = 32; 3473efe843d8SDavid Gibson } 3474f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3475fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3476fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3477fcf5ef2aSThomas Huth return; 3478fcf5ef2aSThomas Huth } 3479fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3480fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3481fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3482fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3483fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 3484fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3485fcf5ef2aSThomas Huth tcg_temp_free(t0); 3486fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3487fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3488fcf5ef2aSThomas Huth } 3489fcf5ef2aSThomas Huth 3490fcf5ef2aSThomas Huth /* lswx */ 3491fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3492fcf5ef2aSThomas Huth { 3493fcf5ef2aSThomas Huth TCGv t0; 3494fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3495fcf5ef2aSThomas Huth 3496fcf5ef2aSThomas Huth if (ctx->le_mode) { 3497fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3498fcf5ef2aSThomas Huth return; 3499fcf5ef2aSThomas Huth } 3500fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3501fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3502fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3503fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 3504fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 3505fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 3506fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3507fcf5ef2aSThomas Huth tcg_temp_free(t0); 3508fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3509fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3510fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 3511fcf5ef2aSThomas Huth } 3512fcf5ef2aSThomas Huth 3513fcf5ef2aSThomas Huth /* stswi */ 3514fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3515fcf5ef2aSThomas Huth { 3516fcf5ef2aSThomas Huth TCGv t0; 3517fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3518fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3519fcf5ef2aSThomas Huth 3520fcf5ef2aSThomas Huth if (ctx->le_mode) { 3521fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3522fcf5ef2aSThomas Huth return; 3523fcf5ef2aSThomas Huth } 3524fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3525fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3526fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3527efe843d8SDavid Gibson if (nb == 0) { 3528fcf5ef2aSThomas Huth nb = 32; 3529efe843d8SDavid Gibson } 3530fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 3531fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3532fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3533fcf5ef2aSThomas Huth tcg_temp_free(t0); 3534fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3535fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3536fcf5ef2aSThomas Huth } 3537fcf5ef2aSThomas Huth 3538fcf5ef2aSThomas Huth /* stswx */ 3539fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3540fcf5ef2aSThomas Huth { 3541fcf5ef2aSThomas Huth TCGv t0; 3542fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3543fcf5ef2aSThomas Huth 3544fcf5ef2aSThomas Huth if (ctx->le_mode) { 3545fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3546fcf5ef2aSThomas Huth return; 3547fcf5ef2aSThomas Huth } 3548fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3549fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3550fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3551fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3552fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3553fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3554fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3555fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3556fcf5ef2aSThomas Huth tcg_temp_free(t0); 3557fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3558fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3559fcf5ef2aSThomas Huth } 3560fcf5ef2aSThomas Huth 3561fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3562fcf5ef2aSThomas Huth /* eieio */ 3563fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3564fcf5ef2aSThomas Huth { 3565c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3566c8fd8373SCédric Le Goater 3567c8fd8373SCédric Le Goater /* 3568c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3569c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3570c8fd8373SCédric Le Goater */ 3571c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3572c8fd8373SCédric Le Goater /* 3573c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3574c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3575c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3576c8fd8373SCédric Le Goater * complain to the user. 3577c8fd8373SCédric Le Goater */ 3578c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3579c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 35802c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3581c8fd8373SCédric Le Goater } else { 3582c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3583c8fd8373SCédric Le Goater } 3584c8fd8373SCédric Le Goater } 3585c8fd8373SCédric Le Goater 3586c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3587fcf5ef2aSThomas Huth } 3588fcf5ef2aSThomas Huth 3589fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3590fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3591fcf5ef2aSThomas Huth { 3592fcf5ef2aSThomas Huth TCGv_i32 t; 3593fcf5ef2aSThomas Huth TCGLabel *l; 3594fcf5ef2aSThomas Huth 3595fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3596fcf5ef2aSThomas Huth return; 3597fcf5ef2aSThomas Huth } 3598fcf5ef2aSThomas Huth l = gen_new_label(); 3599fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3600fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3601fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3602fcf5ef2aSThomas Huth if (global) { 3603fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3604fcf5ef2aSThomas Huth } else { 3605fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3606fcf5ef2aSThomas Huth } 3607fcf5ef2aSThomas Huth gen_set_label(l); 3608fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3609fcf5ef2aSThomas Huth } 3610fcf5ef2aSThomas Huth #else 3611fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3612fcf5ef2aSThomas Huth #endif 3613fcf5ef2aSThomas Huth 3614fcf5ef2aSThomas Huth /* isync */ 3615fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3616fcf5ef2aSThomas Huth { 3617fcf5ef2aSThomas Huth /* 3618fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3619fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3620fcf5ef2aSThomas Huth */ 3621fcf5ef2aSThomas Huth if (!ctx->pr) { 3622fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3623fcf5ef2aSThomas Huth } 36244771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3625d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3626fcf5ef2aSThomas Huth } 3627fcf5ef2aSThomas Huth 3628fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3629fcf5ef2aSThomas Huth 363014776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 36312a4e6c1bSRichard Henderson { 36322a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 36332a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 36342a4e6c1bSRichard Henderson 36352a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 36362a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 36372a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 36382a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 36392a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 36402a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 36412a4e6c1bSRichard Henderson tcg_temp_free(t0); 36422a4e6c1bSRichard Henderson } 36432a4e6c1bSRichard Henderson 3644fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3645fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3646fcf5ef2aSThomas Huth { \ 36472a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3648fcf5ef2aSThomas Huth } 3649fcf5ef2aSThomas Huth 3650fcf5ef2aSThomas Huth /* lwarx */ 3651fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3652fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3653fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3654fcf5ef2aSThomas Huth 365514776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 365620923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 365720923c1dSRichard Henderson { 365820923c1dSRichard Henderson TCGv t = tcg_temp_new(); 365920923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 366020923c1dSRichard Henderson TCGv u = tcg_temp_new(); 366120923c1dSRichard Henderson 366220923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 366320923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 366420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 366520923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 366620923c1dSRichard Henderson 366720923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 366820923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 366920923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 367020923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 367120923c1dSRichard Henderson 367220923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 367320923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 367420923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 367520923c1dSRichard Henderson 367620923c1dSRichard Henderson tcg_temp_free(t); 367720923c1dSRichard Henderson tcg_temp_free(t2); 367820923c1dSRichard Henderson tcg_temp_free(u); 367920923c1dSRichard Henderson } 368020923c1dSRichard Henderson 368114776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 368220ba8504SRichard Henderson { 368320ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 368420ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 368520923c1dSRichard Henderson int rt = rD(ctx->opcode); 368620923c1dSRichard Henderson bool need_serial; 368720ba8504SRichard Henderson TCGv src, dst; 368820ba8504SRichard Henderson 368920ba8504SRichard Henderson gen_addr_register(ctx, EA); 369020923c1dSRichard Henderson dst = cpu_gpr[rt]; 369120923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 369220ba8504SRichard Henderson 369320923c1dSRichard Henderson need_serial = false; 369420ba8504SRichard Henderson memop |= MO_ALIGN; 369520ba8504SRichard Henderson switch (gpr_FC) { 369620ba8504SRichard Henderson case 0: /* Fetch and add */ 369720ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 369820ba8504SRichard Henderson break; 369920ba8504SRichard Henderson case 1: /* Fetch and xor */ 370020ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 370120ba8504SRichard Henderson break; 370220ba8504SRichard Henderson case 2: /* Fetch and or */ 370320ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 370420ba8504SRichard Henderson break; 370520ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 370620ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 370720ba8504SRichard Henderson break; 3708b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3709b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3710b8ce0f86SRichard Henderson break; 3711b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3712b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3713b8ce0f86SRichard Henderson break; 3714b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3715b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3716b8ce0f86SRichard Henderson break; 3717b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3718b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3719b8ce0f86SRichard Henderson break; 372020ba8504SRichard Henderson case 8: /* Swap */ 372120ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 372220ba8504SRichard Henderson break; 372320923c1dSRichard Henderson 372420923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 372520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 372620923c1dSRichard Henderson need_serial = true; 372720923c1dSRichard Henderson } else { 372820923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 372920923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 373020923c1dSRichard Henderson 373120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 373220923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 373320923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 373420923c1dSRichard Henderson } else { 373520923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 373620923c1dSRichard Henderson } 373720923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 373820923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 373920923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 374020923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 374120923c1dSRichard Henderson 374220923c1dSRichard Henderson tcg_temp_free(t0); 374320923c1dSRichard Henderson tcg_temp_free(t1); 374420923c1dSRichard Henderson } 374520ba8504SRichard Henderson break; 374620923c1dSRichard Henderson 374720923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 374820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 374920923c1dSRichard Henderson need_serial = true; 375020923c1dSRichard Henderson } else { 375120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 375220923c1dSRichard Henderson } 375320923c1dSRichard Henderson break; 375420923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 375520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 375620923c1dSRichard Henderson need_serial = true; 375720923c1dSRichard Henderson } else { 375820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 375920923c1dSRichard Henderson } 376020923c1dSRichard Henderson break; 376120923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 376220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 376320923c1dSRichard Henderson need_serial = true; 376420923c1dSRichard Henderson } else { 376520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 376620923c1dSRichard Henderson } 376720923c1dSRichard Henderson break; 376820923c1dSRichard Henderson 376920ba8504SRichard Henderson default: 377020ba8504SRichard Henderson /* invoke data storage error handler */ 377120ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 377220ba8504SRichard Henderson } 377320ba8504SRichard Henderson tcg_temp_free(EA); 377420923c1dSRichard Henderson 377520923c1dSRichard Henderson if (need_serial) { 377620923c1dSRichard Henderson /* Restart with exclusive lock. */ 377720923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 377820923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 377920923c1dSRichard Henderson } 3780a68a6146SBalamuruhan S } 3781a68a6146SBalamuruhan S 378220ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 378320ba8504SRichard Henderson { 378420ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 378520ba8504SRichard Henderson } 378620ba8504SRichard Henderson 378720ba8504SRichard Henderson #ifdef TARGET_PPC64 378820ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 378920ba8504SRichard Henderson { 379020ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 379120ba8504SRichard Henderson } 3792a68a6146SBalamuruhan S #endif 3793a68a6146SBalamuruhan S 379414776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 37959deb041cSRichard Henderson { 37969deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 37979deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 37989deb041cSRichard Henderson TCGv src, discard; 37999deb041cSRichard Henderson 38009deb041cSRichard Henderson gen_addr_register(ctx, EA); 38019deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 38029deb041cSRichard Henderson discard = tcg_temp_new(); 38039deb041cSRichard Henderson 38049deb041cSRichard Henderson memop |= MO_ALIGN; 38059deb041cSRichard Henderson switch (gpr_FC) { 38069deb041cSRichard Henderson case 0: /* add and Store */ 38079deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38089deb041cSRichard Henderson break; 38099deb041cSRichard Henderson case 1: /* xor and Store */ 38109deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38119deb041cSRichard Henderson break; 38129deb041cSRichard Henderson case 2: /* Or and Store */ 38139deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38149deb041cSRichard Henderson break; 38159deb041cSRichard Henderson case 3: /* 'and' and Store */ 38169deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 38179deb041cSRichard Henderson break; 38189deb041cSRichard Henderson case 4: /* Store max unsigned */ 3819b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3820b8ce0f86SRichard Henderson break; 38219deb041cSRichard Henderson case 5: /* Store max signed */ 3822b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3823b8ce0f86SRichard Henderson break; 38249deb041cSRichard Henderson case 6: /* Store min unsigned */ 3825b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3826b8ce0f86SRichard Henderson break; 38279deb041cSRichard Henderson case 7: /* Store min signed */ 3828b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3829b8ce0f86SRichard Henderson break; 38309deb041cSRichard Henderson case 24: /* Store twin */ 38317fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 38327fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 38337fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 38347fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 38357fbc2b20SRichard Henderson } else { 38367fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 38377fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 38387fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 38397fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 38407fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 38417fbc2b20SRichard Henderson 38427fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 38437fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 38447fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 38457fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 38467fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 38477fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 38487fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 38497fbc2b20SRichard Henderson 38507fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 38517fbc2b20SRichard Henderson tcg_temp_free(s2); 38527fbc2b20SRichard Henderson tcg_temp_free(s); 38537fbc2b20SRichard Henderson tcg_temp_free(t2); 38547fbc2b20SRichard Henderson tcg_temp_free(t); 38557fbc2b20SRichard Henderson } 38569deb041cSRichard Henderson break; 38579deb041cSRichard Henderson default: 38589deb041cSRichard Henderson /* invoke data storage error handler */ 38599deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 38609deb041cSRichard Henderson } 38619deb041cSRichard Henderson tcg_temp_free(discard); 38629deb041cSRichard Henderson tcg_temp_free(EA); 3863a3401188SBalamuruhan S } 3864a3401188SBalamuruhan S 38659deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 38669deb041cSRichard Henderson { 38679deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 38689deb041cSRichard Henderson } 38699deb041cSRichard Henderson 38709deb041cSRichard Henderson #ifdef TARGET_PPC64 38719deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 38729deb041cSRichard Henderson { 38739deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 38749deb041cSRichard Henderson } 3875a3401188SBalamuruhan S #endif 3876a3401188SBalamuruhan S 387714776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3878fcf5ef2aSThomas Huth { 3879253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3880253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3881d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3882d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3883fcf5ef2aSThomas Huth 3884d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3885d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3886d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3887d8b86898SRichard Henderson tcg_temp_free(t0); 3888253ce7b2SNikunj A Dadhania 3889253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3890253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3891253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3892253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3893253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3894253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3895253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3896253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3897253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3898253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3899253ce7b2SNikunj A Dadhania 3900fcf5ef2aSThomas Huth gen_set_label(l1); 39014771df23SNikunj A Dadhania 3902efe843d8SDavid Gibson /* 3903efe843d8SDavid Gibson * Address mismatch implies failure. But we still need to provide 3904efe843d8SDavid Gibson * the memory barrier semantics of the instruction. 3905efe843d8SDavid Gibson */ 39064771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3907253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3908253ce7b2SNikunj A Dadhania 3909253ce7b2SNikunj A Dadhania gen_set_label(l2); 3910fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3911fcf5ef2aSThomas Huth } 3912fcf5ef2aSThomas Huth 3913fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3914fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3915fcf5ef2aSThomas Huth { \ 3916d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3917fcf5ef2aSThomas Huth } 3918fcf5ef2aSThomas Huth 3919fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3920fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3921fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3922fcf5ef2aSThomas Huth 3923fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3924fcf5ef2aSThomas Huth /* ldarx */ 3925fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3926fcf5ef2aSThomas Huth /* stdcx. */ 3927fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3928fcf5ef2aSThomas Huth 3929fcf5ef2aSThomas Huth /* lqarx */ 3930fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3931fcf5ef2aSThomas Huth { 3932fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 393394bf2658SRichard Henderson TCGv EA, hi, lo; 3934fcf5ef2aSThomas Huth 3935fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3936fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3937fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3938fcf5ef2aSThomas Huth return; 3939fcf5ef2aSThomas Huth } 3940fcf5ef2aSThomas Huth 3941fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 394294bf2658SRichard Henderson EA = tcg_temp_new(); 3943fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 394494bf2658SRichard Henderson 394594bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 394694bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 394794bf2658SRichard Henderson hi = cpu_gpr[rd]; 394894bf2658SRichard Henderson 394994bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 3950f34ec0f6SRichard Henderson if (HAVE_ATOMIC128) { 395194bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 395294bf2658SRichard Henderson if (ctx->le_mode) { 395368e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN, 395494bf2658SRichard Henderson ctx->mem_idx)); 395594bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3956fcf5ef2aSThomas Huth } else { 395768e33d86SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN, 395894bf2658SRichard Henderson ctx->mem_idx)); 395994bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3960fcf5ef2aSThomas Huth } 396194bf2658SRichard Henderson tcg_temp_free_i32(oi); 396294bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 3963f34ec0f6SRichard Henderson } else { 396494bf2658SRichard Henderson /* Restart with exclusive lock. */ 396594bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 396694bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 396794bf2658SRichard Henderson tcg_temp_free(EA); 396894bf2658SRichard Henderson return; 3969f34ec0f6SRichard Henderson } 397094bf2658SRichard Henderson } else if (ctx->le_mode) { 397194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3972fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3973fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 397494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 397594bf2658SRichard Henderson } else { 397694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 397794bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 397894bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 397994bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 398094bf2658SRichard Henderson } 3981fcf5ef2aSThomas Huth tcg_temp_free(EA); 398294bf2658SRichard Henderson 398394bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 398494bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3985fcf5ef2aSThomas Huth } 3986fcf5ef2aSThomas Huth 3987fcf5ef2aSThomas Huth /* stqcx. */ 3988fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3989fcf5ef2aSThomas Huth { 39904a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 39914a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3992fcf5ef2aSThomas Huth 39934a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3994fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3995fcf5ef2aSThomas Huth return; 3996fcf5ef2aSThomas Huth } 39974a9b3c5dSRichard Henderson 3998fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 39994a9b3c5dSRichard Henderson EA = tcg_temp_new(); 4000fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4001fcf5ef2aSThomas Huth 40024a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 40034a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 40044a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 4005fcf5ef2aSThomas Huth 40064a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 4007f34ec0f6SRichard Henderson if (HAVE_CMPXCHG128) { 400868e33d86SRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); 40094a9b3c5dSRichard Henderson if (ctx->le_mode) { 4010f34ec0f6SRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, 4011f34ec0f6SRichard Henderson EA, lo, hi, oi); 4012fcf5ef2aSThomas Huth } else { 4013f34ec0f6SRichard Henderson gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, 4014f34ec0f6SRichard Henderson EA, lo, hi, oi); 4015fcf5ef2aSThomas Huth } 4016f34ec0f6SRichard Henderson tcg_temp_free_i32(oi); 4017f34ec0f6SRichard Henderson } else { 40184a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 40194a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 40204a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4021f34ec0f6SRichard Henderson } 4022fcf5ef2aSThomas Huth tcg_temp_free(EA); 40234a9b3c5dSRichard Henderson } else { 40244a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 40254a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 40264a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 40274a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 4028fcf5ef2aSThomas Huth 40294a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 40304a9b3c5dSRichard Henderson tcg_temp_free(EA); 40314a9b3c5dSRichard Henderson 40324a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 40334a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40344a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 40354a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 40364a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40374a9b3c5dSRichard Henderson 40384a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40394a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 40404a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 40414a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 40424a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 40434a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 40444a9b3c5dSRichard Henderson 40454a9b3c5dSRichard Henderson /* Success */ 40464a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 40474a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 40484a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 40494a9b3c5dSRichard Henderson 40504a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40514a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 40524a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 40534a9b3c5dSRichard Henderson 40544a9b3c5dSRichard Henderson gen_set_label(lab_fail); 40554a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 40564a9b3c5dSRichard Henderson 40574a9b3c5dSRichard Henderson gen_set_label(lab_over); 40584a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 40594a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 40604a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 40614a9b3c5dSRichard Henderson } 40624a9b3c5dSRichard Henderson } 4063fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4064fcf5ef2aSThomas Huth 4065fcf5ef2aSThomas Huth /* sync */ 4066fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 4067fcf5ef2aSThomas Huth { 4068fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 4069fcf5ef2aSThomas Huth 4070fcf5ef2aSThomas Huth /* 4071fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 4072fcf5ef2aSThomas Huth * 4073fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 4074fcf5ef2aSThomas Huth * 4075fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 4076fcf5ef2aSThomas Huth * check MSR_PR as well. 4077fcf5ef2aSThomas Huth */ 4078fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 4079fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4080fcf5ef2aSThomas Huth } 40814771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 4082fcf5ef2aSThomas Huth } 4083fcf5ef2aSThomas Huth 4084fcf5ef2aSThomas Huth /* wait */ 4085fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 4086fcf5ef2aSThomas Huth { 4087fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 4088fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 4089fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 4090fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4091fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4092b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4093fcf5ef2aSThomas Huth } 4094fcf5ef2aSThomas Huth 4095fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4096fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4097fcf5ef2aSThomas Huth { 4098fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4099fcf5ef2aSThomas Huth GEN_PRIV; 4100fcf5ef2aSThomas Huth #else 4101fcf5ef2aSThomas Huth TCGv_i32 t; 4102fcf5ef2aSThomas Huth 4103fcf5ef2aSThomas Huth CHK_HV; 4104fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 4105fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4106fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4107154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4108154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4109fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4110fcf5ef2aSThomas Huth } 4111fcf5ef2aSThomas Huth 4112fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4113fcf5ef2aSThomas Huth { 4114fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4115fcf5ef2aSThomas Huth GEN_PRIV; 4116fcf5ef2aSThomas Huth #else 4117fcf5ef2aSThomas Huth TCGv_i32 t; 4118fcf5ef2aSThomas Huth 4119fcf5ef2aSThomas Huth CHK_HV; 4120fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 4121fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4122fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4123154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4124154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4125fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4126fcf5ef2aSThomas Huth } 4127fcf5ef2aSThomas Huth 4128cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4129cdee0e72SNikunj A Dadhania { 413021c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 413121c0d66aSBenjamin Herrenschmidt GEN_PRIV; 413221c0d66aSBenjamin Herrenschmidt #else 413321c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 413421c0d66aSBenjamin Herrenschmidt 413521c0d66aSBenjamin Herrenschmidt CHK_HV; 413621c0d66aSBenjamin Herrenschmidt t = tcg_const_i32(PPC_PM_STOP); 413721c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 413821c0d66aSBenjamin Herrenschmidt tcg_temp_free_i32(t); 413921c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 414021c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 414121c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4142cdee0e72SNikunj A Dadhania } 4143cdee0e72SNikunj A Dadhania 4144fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4145fcf5ef2aSThomas Huth { 4146fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4147fcf5ef2aSThomas Huth GEN_PRIV; 4148fcf5ef2aSThomas Huth #else 4149fcf5ef2aSThomas Huth TCGv_i32 t; 4150fcf5ef2aSThomas Huth 4151fcf5ef2aSThomas Huth CHK_HV; 4152fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 4153fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4154fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4155154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4156154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4157fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4158fcf5ef2aSThomas Huth } 4159fcf5ef2aSThomas Huth 4160fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4161fcf5ef2aSThomas Huth { 4162fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4163fcf5ef2aSThomas Huth GEN_PRIV; 4164fcf5ef2aSThomas Huth #else 4165fcf5ef2aSThomas Huth TCGv_i32 t; 4166fcf5ef2aSThomas Huth 4167fcf5ef2aSThomas Huth CHK_HV; 4168fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 4169fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4170fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 4171154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4172154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4173fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4174fcf5ef2aSThomas Huth } 4175fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4176fcf5ef2aSThomas Huth 4177fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4178fcf5ef2aSThomas Huth { 4179fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4180efe843d8SDavid Gibson if (ctx->has_cfar) { 4181fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4182efe843d8SDavid Gibson } 4183fcf5ef2aSThomas Huth #endif 4184fcf5ef2aSThomas Huth } 4185fcf5ef2aSThomas Huth 418646d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 418746d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 418846d396bdSDaniel Henrique Barboza { 418946d396bdSDaniel Henrique Barboza /* 419046d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 419146d396bdSDaniel Henrique Barboza * instructions. 419246d396bdSDaniel Henrique Barboza */ 419346d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 419446d396bdSDaniel Henrique Barboza return; 419546d396bdSDaniel Henrique Barboza } 419646d396bdSDaniel Henrique Barboza 419746d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 419846d396bdSDaniel Henrique Barboza /* 419946d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 420046d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 420146d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 420246d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 420346d396bdSDaniel Henrique Barboza */ 420446d396bdSDaniel Henrique Barboza gen_icount_io_start(ctx); 420546d396bdSDaniel Henrique Barboza 420646d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 420746d396bdSDaniel Henrique Barboza #else 420846d396bdSDaniel Henrique Barboza /* 420946d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 421046d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 421146d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 421246d396bdSDaniel Henrique Barboza */ 421346d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 421446d396bdSDaniel Henrique Barboza 421546d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 421646d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 421746d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 421846d396bdSDaniel Henrique Barboza 421946d396bdSDaniel Henrique Barboza tcg_temp_free(t0); 422046d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 422146d396bdSDaniel Henrique Barboza } 422246d396bdSDaniel Henrique Barboza #else 422346d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 422446d396bdSDaniel Henrique Barboza { 422546d396bdSDaniel Henrique Barboza return; 422646d396bdSDaniel Henrique Barboza } 422746d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 422846d396bdSDaniel Henrique Barboza 4229fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4230fcf5ef2aSThomas Huth { 42316e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4232fcf5ef2aSThomas Huth } 4233fcf5ef2aSThomas Huth 42340e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 42350e3bf489SRoman Kapl { 42369498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 42370e3bf489SRoman Kapl gen_debug_exception(ctx); 42380e3bf489SRoman Kapl } else { 423946d396bdSDaniel Henrique Barboza /* 424046d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 424146d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 424246d396bdSDaniel Henrique Barboza */ 424346d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 424446d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 424546d396bdSDaniel Henrique Barboza } 424646d396bdSDaniel Henrique Barboza 42470e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 42480e3bf489SRoman Kapl } 42490e3bf489SRoman Kapl } 42500e3bf489SRoman Kapl 4251fcf5ef2aSThomas Huth /*** Branch ***/ 4252c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4253fcf5ef2aSThomas Huth { 4254fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4255fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4256fcf5ef2aSThomas Huth } 4257fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 425846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4259fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4260fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 426107ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4262fcf5ef2aSThomas Huth } else { 4263fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 42640e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4265fcf5ef2aSThomas Huth } 4266fcf5ef2aSThomas Huth } 4267fcf5ef2aSThomas Huth 4268fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4269fcf5ef2aSThomas Huth { 4270fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4271fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4272fcf5ef2aSThomas Huth } 4273fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4274fcf5ef2aSThomas Huth } 4275fcf5ef2aSThomas Huth 4276fcf5ef2aSThomas Huth /* b ba bl bla */ 4277fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4278fcf5ef2aSThomas Huth { 4279fcf5ef2aSThomas Huth target_ulong li, target; 4280fcf5ef2aSThomas Huth 4281fcf5ef2aSThomas Huth /* sign extend LI */ 4282fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4283fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4284fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42852c2bcb1bSRichard Henderson target = ctx->cia + li; 4286fcf5ef2aSThomas Huth } else { 4287fcf5ef2aSThomas Huth target = li; 4288fcf5ef2aSThomas Huth } 4289fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4290b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4291fcf5ef2aSThomas Huth } 42922c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4293fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 42946086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4295fcf5ef2aSThomas Huth } 4296fcf5ef2aSThomas Huth 4297fcf5ef2aSThomas Huth #define BCOND_IM 0 4298fcf5ef2aSThomas Huth #define BCOND_LR 1 4299fcf5ef2aSThomas Huth #define BCOND_CTR 2 4300fcf5ef2aSThomas Huth #define BCOND_TAR 3 4301fcf5ef2aSThomas Huth 4302c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4303fcf5ef2aSThomas Huth { 4304fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4305fcf5ef2aSThomas Huth TCGLabel *l1; 4306fcf5ef2aSThomas Huth TCGv target; 43070e3bf489SRoman Kapl 4308fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 4309fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 4310efe843d8SDavid Gibson if (type == BCOND_CTR) { 4311fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4312efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4313fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4314efe843d8SDavid Gibson } else { 4315fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4316efe843d8SDavid Gibson } 4317fcf5ef2aSThomas Huth } else { 4318f764718dSRichard Henderson target = NULL; 4319fcf5ef2aSThomas Huth } 4320efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4321b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4322efe843d8SDavid Gibson } 4323fcf5ef2aSThomas Huth l1 = gen_new_label(); 4324fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4325fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4326fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4327fa200c95SGreg Kurz 4328fa200c95SGreg Kurz if (type == BCOND_CTR) { 4329fa200c95SGreg Kurz /* 4330fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4331fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4332fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 433315d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 433415d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 433515d68c5eSGreg Kurz * it basically useless and thus never used in real code. 433615d68c5eSGreg Kurz * 433715d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 433815d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 433915d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 434015d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 434115d68c5eSGreg Kurz * doing anything else harmful. 4342fa200c95SGreg Kurz */ 4343d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4344fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 43459acc95cdSGreg Kurz tcg_temp_free(temp); 43469acc95cdSGreg Kurz tcg_temp_free(target); 4347fcf5ef2aSThomas Huth return; 4348fcf5ef2aSThomas Huth } 4349fa200c95SGreg Kurz 4350fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4351fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4352fa200c95SGreg Kurz } else { 4353fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4354fa200c95SGreg Kurz } 4355fa200c95SGreg Kurz if (bo & 0x2) { 4356fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4357fa200c95SGreg Kurz } else { 4358fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4359fa200c95SGreg Kurz } 4360fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4361fa200c95SGreg Kurz } else { 4362fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4363fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4364fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4365fcf5ef2aSThomas Huth } else { 4366fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4367fcf5ef2aSThomas Huth } 4368fcf5ef2aSThomas Huth if (bo & 0x2) { 4369fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4370fcf5ef2aSThomas Huth } else { 4371fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4372fcf5ef2aSThomas Huth } 4373fa200c95SGreg Kurz } 4374fcf5ef2aSThomas Huth tcg_temp_free(temp); 4375fcf5ef2aSThomas Huth } 4376fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4377fcf5ef2aSThomas Huth /* Test CR */ 4378fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4379fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4380fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4381fcf5ef2aSThomas Huth 4382fcf5ef2aSThomas Huth if (bo & 0x8) { 4383fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4384fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4385fcf5ef2aSThomas Huth } else { 4386fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4387fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4388fcf5ef2aSThomas Huth } 4389fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4390fcf5ef2aSThomas Huth } 43912c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4392fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4393fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4394fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43952c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4396fcf5ef2aSThomas Huth } else { 4397fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4398fcf5ef2aSThomas Huth } 4399fcf5ef2aSThomas Huth } else { 4400fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4401fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4402fcf5ef2aSThomas Huth } else { 4403fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4404fcf5ef2aSThomas Huth } 44050e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4406c4a2e3a9SRichard Henderson tcg_temp_free(target); 4407c4a2e3a9SRichard Henderson } 4408fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 44090e3bf489SRoman Kapl /* fallthrough case */ 4410fcf5ef2aSThomas Huth gen_set_label(l1); 4411b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4412fcf5ef2aSThomas Huth } 44136086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4414fcf5ef2aSThomas Huth } 4415fcf5ef2aSThomas Huth 4416fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4417fcf5ef2aSThomas Huth { 4418fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4419fcf5ef2aSThomas Huth } 4420fcf5ef2aSThomas Huth 4421fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4422fcf5ef2aSThomas Huth { 4423fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4424fcf5ef2aSThomas Huth } 4425fcf5ef2aSThomas Huth 4426fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4427fcf5ef2aSThomas Huth { 4428fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4429fcf5ef2aSThomas Huth } 4430fcf5ef2aSThomas Huth 4431fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4432fcf5ef2aSThomas Huth { 4433fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4434fcf5ef2aSThomas Huth } 4435fcf5ef2aSThomas Huth 4436fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4437fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4438fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4439fcf5ef2aSThomas Huth { \ 4440fcf5ef2aSThomas Huth uint8_t bitmask; \ 4441fcf5ef2aSThomas Huth int sh; \ 4442fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4443fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4444fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4445fcf5ef2aSThomas Huth if (sh > 0) \ 4446fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4447fcf5ef2aSThomas Huth else if (sh < 0) \ 4448fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4449fcf5ef2aSThomas Huth else \ 4450fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4451fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4452fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4453fcf5ef2aSThomas Huth if (sh > 0) \ 4454fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4455fcf5ef2aSThomas Huth else if (sh < 0) \ 4456fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4457fcf5ef2aSThomas Huth else \ 4458fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4459fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4460fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4461fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4462fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4463fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4464fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 4465fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 4466fcf5ef2aSThomas Huth } 4467fcf5ef2aSThomas Huth 4468fcf5ef2aSThomas Huth /* crand */ 4469fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4470fcf5ef2aSThomas Huth /* crandc */ 4471fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4472fcf5ef2aSThomas Huth /* creqv */ 4473fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4474fcf5ef2aSThomas Huth /* crnand */ 4475fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4476fcf5ef2aSThomas Huth /* crnor */ 4477fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4478fcf5ef2aSThomas Huth /* cror */ 4479fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4480fcf5ef2aSThomas Huth /* crorc */ 4481fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4482fcf5ef2aSThomas Huth /* crxor */ 4483fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4484fcf5ef2aSThomas Huth 4485fcf5ef2aSThomas Huth /* mcrf */ 4486fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4487fcf5ef2aSThomas Huth { 4488fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4489fcf5ef2aSThomas Huth } 4490fcf5ef2aSThomas Huth 4491fcf5ef2aSThomas Huth /*** System linkage ***/ 4492fcf5ef2aSThomas Huth 4493fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4494fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4495fcf5ef2aSThomas Huth { 4496fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4497fcf5ef2aSThomas Huth GEN_PRIV; 4498fcf5ef2aSThomas Huth #else 4499efe843d8SDavid Gibson /* 4500efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4501fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4502fcf5ef2aSThomas Huth */ 4503d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4504fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4505fcf5ef2aSThomas Huth return; 4506fcf5ef2aSThomas Huth } 4507fcf5ef2aSThomas Huth /* Restore CPU state */ 4508fcf5ef2aSThomas Huth CHK_SV; 4509f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45102c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4511fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 451259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4513fcf5ef2aSThomas Huth #endif 4514fcf5ef2aSThomas Huth } 4515fcf5ef2aSThomas Huth 4516fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4517fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4518fcf5ef2aSThomas Huth { 4519fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4520fcf5ef2aSThomas Huth GEN_PRIV; 4521fcf5ef2aSThomas Huth #else 4522fcf5ef2aSThomas Huth /* Restore CPU state */ 4523fcf5ef2aSThomas Huth CHK_SV; 4524f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45252c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4526fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 452759bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4528fcf5ef2aSThomas Huth #endif 4529fcf5ef2aSThomas Huth } 4530fcf5ef2aSThomas Huth 45313c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45323c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 45333c89b8d6SNicholas Piggin { 45343c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 45353c89b8d6SNicholas Piggin GEN_PRIV; 45363c89b8d6SNicholas Piggin #else 45373c89b8d6SNicholas Piggin /* Restore CPU state */ 45383c89b8d6SNicholas Piggin CHK_SV; 4539f5b6daacSRichard Henderson gen_icount_io_start(ctx); 45402c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 45413c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 454259bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 45433c89b8d6SNicholas Piggin #endif 45443c89b8d6SNicholas Piggin } 45453c89b8d6SNicholas Piggin #endif 45463c89b8d6SNicholas Piggin 4547fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4548fcf5ef2aSThomas Huth { 4549fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4550fcf5ef2aSThomas Huth GEN_PRIV; 4551fcf5ef2aSThomas Huth #else 4552fcf5ef2aSThomas Huth /* Restore CPU state */ 4553fcf5ef2aSThomas Huth CHK_HV; 4554fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 455559bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4556fcf5ef2aSThomas Huth #endif 4557fcf5ef2aSThomas Huth } 4558fcf5ef2aSThomas Huth #endif 4559fcf5ef2aSThomas Huth 4560fcf5ef2aSThomas Huth /* sc */ 4561fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4562fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4563fcf5ef2aSThomas Huth #else 4564fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 45653c89b8d6SNicholas Piggin #define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED 4566fcf5ef2aSThomas Huth #endif 4567fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4568fcf5ef2aSThomas Huth { 4569fcf5ef2aSThomas Huth uint32_t lev; 4570fcf5ef2aSThomas Huth 4571fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 4572fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4573fcf5ef2aSThomas Huth } 4574fcf5ef2aSThomas Huth 45753c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 45763c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45773c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 45783c89b8d6SNicholas Piggin { 4579f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 45803c89b8d6SNicholas Piggin 4581f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 45822c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4583f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 45843c89b8d6SNicholas Piggin 45857a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 45863c89b8d6SNicholas Piggin } 45873c89b8d6SNicholas Piggin #endif 45883c89b8d6SNicholas Piggin #endif 45893c89b8d6SNicholas Piggin 4590fcf5ef2aSThomas Huth /*** Trap ***/ 4591fcf5ef2aSThomas Huth 4592fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4593fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4594fcf5ef2aSThomas Huth { 4595fcf5ef2aSThomas Huth /* Trap never */ 4596fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4597fcf5ef2aSThomas Huth return true; 4598fcf5ef2aSThomas Huth } 4599fcf5ef2aSThomas Huth /* Trap always */ 4600fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4601fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4602fcf5ef2aSThomas Huth return true; 4603fcf5ef2aSThomas Huth } 4604fcf5ef2aSThomas Huth return false; 4605fcf5ef2aSThomas Huth } 4606fcf5ef2aSThomas Huth 4607fcf5ef2aSThomas Huth /* tw */ 4608fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4609fcf5ef2aSThomas Huth { 4610fcf5ef2aSThomas Huth TCGv_i32 t0; 4611fcf5ef2aSThomas Huth 4612fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4613fcf5ef2aSThomas Huth return; 4614fcf5ef2aSThomas Huth } 4615fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4616fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4617fcf5ef2aSThomas Huth t0); 4618fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4619fcf5ef2aSThomas Huth } 4620fcf5ef2aSThomas Huth 4621fcf5ef2aSThomas Huth /* twi */ 4622fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4623fcf5ef2aSThomas Huth { 4624fcf5ef2aSThomas Huth TCGv t0; 4625fcf5ef2aSThomas Huth TCGv_i32 t1; 4626fcf5ef2aSThomas Huth 4627fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4628fcf5ef2aSThomas Huth return; 4629fcf5ef2aSThomas Huth } 4630fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4631fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4632fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4633fcf5ef2aSThomas Huth tcg_temp_free(t0); 4634fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4635fcf5ef2aSThomas Huth } 4636fcf5ef2aSThomas Huth 4637fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4638fcf5ef2aSThomas Huth /* td */ 4639fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4640fcf5ef2aSThomas Huth { 4641fcf5ef2aSThomas Huth TCGv_i32 t0; 4642fcf5ef2aSThomas Huth 4643fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4644fcf5ef2aSThomas Huth return; 4645fcf5ef2aSThomas Huth } 4646fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 4647fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4648fcf5ef2aSThomas Huth t0); 4649fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4650fcf5ef2aSThomas Huth } 4651fcf5ef2aSThomas Huth 4652fcf5ef2aSThomas Huth /* tdi */ 4653fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4654fcf5ef2aSThomas Huth { 4655fcf5ef2aSThomas Huth TCGv t0; 4656fcf5ef2aSThomas Huth TCGv_i32 t1; 4657fcf5ef2aSThomas Huth 4658fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4659fcf5ef2aSThomas Huth return; 4660fcf5ef2aSThomas Huth } 4661fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 4662fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 4663fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4664fcf5ef2aSThomas Huth tcg_temp_free(t0); 4665fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4666fcf5ef2aSThomas Huth } 4667fcf5ef2aSThomas Huth #endif 4668fcf5ef2aSThomas Huth 4669fcf5ef2aSThomas Huth /*** Processor control ***/ 4670fcf5ef2aSThomas Huth 4671fcf5ef2aSThomas Huth /* mcrxr */ 4672fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4673fcf5ef2aSThomas Huth { 4674fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4675fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4676fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4677fcf5ef2aSThomas Huth 4678fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4679fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4680fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4681fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4682fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4683fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4684fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4685fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4686fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4687fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4688fcf5ef2aSThomas Huth 4689fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4690fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4691fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4692fcf5ef2aSThomas Huth } 4693fcf5ef2aSThomas Huth 4694b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4695b63d0434SNikunj A Dadhania /* mcrxrx */ 4696b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4697b63d0434SNikunj A Dadhania { 4698b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4699b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4700b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4701b63d0434SNikunj A Dadhania 4702b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4703b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4704b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4705b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4706b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4707b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4708b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4709b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4710b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4711b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4712b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4713b63d0434SNikunj A Dadhania } 4714b63d0434SNikunj A Dadhania #endif 4715b63d0434SNikunj A Dadhania 4716fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4717fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4718fcf5ef2aSThomas Huth { 4719fcf5ef2aSThomas Huth uint32_t crm, crn; 4720fcf5ef2aSThomas Huth 4721fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4722fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4723fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4724fcf5ef2aSThomas Huth crn = ctz32(crm); 4725fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4726fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4727fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4728fcf5ef2aSThomas Huth } 4729fcf5ef2aSThomas Huth } else { 4730fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4731fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4732fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4733fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4734fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4735fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4736fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4737fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4738fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4739fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4740fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4741fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4742fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4743fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4744fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4745fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4746fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4747fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4748fcf5ef2aSThomas Huth } 4749fcf5ef2aSThomas Huth } 4750fcf5ef2aSThomas Huth 4751fcf5ef2aSThomas Huth /* mfmsr */ 4752fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4753fcf5ef2aSThomas Huth { 4754fcf5ef2aSThomas Huth CHK_SV; 4755fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4756fcf5ef2aSThomas Huth } 4757fcf5ef2aSThomas Huth 4758fcf5ef2aSThomas Huth /* mfspr */ 4759fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4760fcf5ef2aSThomas Huth { 4761fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4762fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4763fcf5ef2aSThomas Huth 4764fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4765fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4766fcf5ef2aSThomas Huth #else 4767fcf5ef2aSThomas Huth if (ctx->pr) { 4768fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4769fcf5ef2aSThomas Huth } else if (ctx->hv) { 4770fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4771fcf5ef2aSThomas Huth } else { 4772fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4773fcf5ef2aSThomas Huth } 4774fcf5ef2aSThomas Huth #endif 4775fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4776fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4777fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4778fcf5ef2aSThomas Huth } else { 4779fcf5ef2aSThomas Huth /* Privilege exception */ 4780efe843d8SDavid Gibson /* 4781efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4782fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4783fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4784fcf5ef2aSThomas Huth */ 4785fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 478631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 478731085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 47882c2bcb1bSRichard Henderson ctx->cia); 4789fcf5ef2aSThomas Huth } 4790fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4791fcf5ef2aSThomas Huth } 4792fcf5ef2aSThomas Huth } else { 4793fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4794fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4795fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4796fcf5ef2aSThomas Huth /* This is a nop */ 4797fcf5ef2aSThomas Huth return; 4798fcf5ef2aSThomas Huth } 4799fcf5ef2aSThomas Huth /* Not defined */ 480031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 480131085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 48022c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4803fcf5ef2aSThomas Huth 4804efe843d8SDavid Gibson /* 4805efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4806efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4807fcf5ef2aSThomas Huth */ 4808fcf5ef2aSThomas Huth if (sprn & 0x10) { 4809fcf5ef2aSThomas Huth if (ctx->pr) { 4810fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4811fcf5ef2aSThomas Huth } 4812fcf5ef2aSThomas Huth } else { 4813fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4814fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4815fcf5ef2aSThomas Huth } 4816fcf5ef2aSThomas Huth } 4817fcf5ef2aSThomas Huth } 4818fcf5ef2aSThomas Huth } 4819fcf5ef2aSThomas Huth 4820fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4821fcf5ef2aSThomas Huth { 4822fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4823fcf5ef2aSThomas Huth } 4824fcf5ef2aSThomas Huth 4825fcf5ef2aSThomas Huth /* mftb */ 4826fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4827fcf5ef2aSThomas Huth { 4828fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4829fcf5ef2aSThomas Huth } 4830fcf5ef2aSThomas Huth 4831fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4832fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4833fcf5ef2aSThomas Huth { 4834fcf5ef2aSThomas Huth uint32_t crm, crn; 4835fcf5ef2aSThomas Huth 4836fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4837fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4838fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4839fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4840fcf5ef2aSThomas Huth crn = ctz32(crm); 4841fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4842fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4843fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4844fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4845fcf5ef2aSThomas Huth } 4846fcf5ef2aSThomas Huth } else { 4847fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4848fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4849fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4850fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4851fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4852fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4853fcf5ef2aSThomas Huth } 4854fcf5ef2aSThomas Huth } 4855fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4856fcf5ef2aSThomas Huth } 4857fcf5ef2aSThomas Huth } 4858fcf5ef2aSThomas Huth 4859fcf5ef2aSThomas Huth /* mtmsr */ 4860fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4861fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4862fcf5ef2aSThomas Huth { 4863caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4864caf590ddSNicholas Piggin gen_invalid(ctx); 4865caf590ddSNicholas Piggin return; 4866caf590ddSNicholas Piggin } 4867caf590ddSNicholas Piggin 4868fcf5ef2aSThomas Huth CHK_SV; 4869fcf5ef2aSThomas Huth 4870fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48716fa5726bSMatheus Ferst TCGv t0, t1; 48726fa5726bSMatheus Ferst target_ulong mask; 48736fa5726bSMatheus Ferst 48746fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48756fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48766fa5726bSMatheus Ferst 4877f5b6daacSRichard Henderson gen_icount_io_start(ctx); 48786fa5726bSMatheus Ferst 4879fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48805ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48816fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4882fcf5ef2aSThomas Huth } else { 48836fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 48846fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 48856fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4886efe843d8SDavid Gibson /* 4887efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4888efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4889efe843d8SDavid Gibson * ppc_store_msr 4890fcf5ef2aSThomas Huth */ 4891b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4892fcf5ef2aSThomas Huth } 48936fa5726bSMatheus Ferst 48946fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48956fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48966fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48976fa5726bSMatheus Ferst 48986fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48996fa5726bSMatheus Ferst 49005ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4901d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 49026fa5726bSMatheus Ferst 49036fa5726bSMatheus Ferst tcg_temp_free(t0); 49046fa5726bSMatheus Ferst tcg_temp_free(t1); 4905fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4906fcf5ef2aSThomas Huth } 4907fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4908fcf5ef2aSThomas Huth 4909fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4910fcf5ef2aSThomas Huth { 4911fcf5ef2aSThomas Huth CHK_SV; 4912fcf5ef2aSThomas Huth 4913fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 49146fa5726bSMatheus Ferst TCGv t0, t1; 49156fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 49166fa5726bSMatheus Ferst 49176fa5726bSMatheus Ferst t0 = tcg_temp_new(); 49186fa5726bSMatheus Ferst t1 = tcg_temp_new(); 49196fa5726bSMatheus Ferst 4920f5b6daacSRichard Henderson gen_icount_io_start(ctx); 4921fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 49225ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 49236fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4924fcf5ef2aSThomas Huth } else { 49256fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 49266fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4927fcf5ef2aSThomas Huth 4928efe843d8SDavid Gibson /* 4929efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4930efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4931efe843d8SDavid Gibson * ppc_store_msr 4932fcf5ef2aSThomas Huth */ 4933b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4934fcf5ef2aSThomas Huth } 49356fa5726bSMatheus Ferst 49366fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 49376fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 49386fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 49396fa5726bSMatheus Ferst 49406fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 49416fa5726bSMatheus Ferst 49425ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4943d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 49446fa5726bSMatheus Ferst 49456fa5726bSMatheus Ferst tcg_temp_free(t0); 49466fa5726bSMatheus Ferst tcg_temp_free(t1); 4947fcf5ef2aSThomas Huth #endif 4948fcf5ef2aSThomas Huth } 4949fcf5ef2aSThomas Huth 4950fcf5ef2aSThomas Huth /* mtspr */ 4951fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4952fcf5ef2aSThomas Huth { 4953fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4954fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4955fcf5ef2aSThomas Huth 4956fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4957fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4958fcf5ef2aSThomas Huth #else 4959fcf5ef2aSThomas Huth if (ctx->pr) { 4960fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4961fcf5ef2aSThomas Huth } else if (ctx->hv) { 4962fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4963fcf5ef2aSThomas Huth } else { 4964fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4965fcf5ef2aSThomas Huth } 4966fcf5ef2aSThomas Huth #endif 4967fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4968fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4969fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4970fcf5ef2aSThomas Huth } else { 4971fcf5ef2aSThomas Huth /* Privilege exception */ 497231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 497331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 49742c2bcb1bSRichard Henderson ctx->cia); 4975fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4976fcf5ef2aSThomas Huth } 4977fcf5ef2aSThomas Huth } else { 4978fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4979fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4980fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4981fcf5ef2aSThomas Huth /* This is a nop */ 4982fcf5ef2aSThomas Huth return; 4983fcf5ef2aSThomas Huth } 4984fcf5ef2aSThomas Huth 4985fcf5ef2aSThomas Huth /* Not defined */ 498631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 498731085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 49882c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4989fcf5ef2aSThomas Huth 4990fcf5ef2aSThomas Huth 4991efe843d8SDavid Gibson /* 4992efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4993efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4994fcf5ef2aSThomas Huth */ 4995fcf5ef2aSThomas Huth if (sprn & 0x10) { 4996fcf5ef2aSThomas Huth if (ctx->pr) { 4997fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4998fcf5ef2aSThomas Huth } 4999fcf5ef2aSThomas Huth } else { 5000fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 5001fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 5002fcf5ef2aSThomas Huth } 5003fcf5ef2aSThomas Huth } 5004fcf5ef2aSThomas Huth } 5005fcf5ef2aSThomas Huth } 5006fcf5ef2aSThomas Huth 5007fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5008fcf5ef2aSThomas Huth /* setb */ 5009fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 5010fcf5ef2aSThomas Huth { 5011fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 50126f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 50136f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 5014fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 5015fcf5ef2aSThomas Huth 5016fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 5017fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 5018fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 5019fcf5ef2aSThomas Huth 5020fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5021fcf5ef2aSThomas Huth } 5022fcf5ef2aSThomas Huth #endif 5023fcf5ef2aSThomas Huth 5024fcf5ef2aSThomas Huth /*** Cache management ***/ 5025fcf5ef2aSThomas Huth 5026fcf5ef2aSThomas Huth /* dcbf */ 5027fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 5028fcf5ef2aSThomas Huth { 5029fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 5030fcf5ef2aSThomas Huth TCGv t0; 5031fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5032fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5033fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5034fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5035fcf5ef2aSThomas Huth tcg_temp_free(t0); 5036fcf5ef2aSThomas Huth } 5037fcf5ef2aSThomas Huth 503850728199SRoman Kapl /* dcbfep (external PID dcbf) */ 503950728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 504050728199SRoman Kapl { 504150728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 504250728199SRoman Kapl TCGv t0; 504350728199SRoman Kapl CHK_SV; 504450728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 504550728199SRoman Kapl t0 = tcg_temp_new(); 504650728199SRoman Kapl gen_addr_reg_index(ctx, t0); 504750728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 504850728199SRoman Kapl tcg_temp_free(t0); 504950728199SRoman Kapl } 505050728199SRoman Kapl 5051fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 5052fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 5053fcf5ef2aSThomas Huth { 5054fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5055fcf5ef2aSThomas Huth GEN_PRIV; 5056fcf5ef2aSThomas Huth #else 5057fcf5ef2aSThomas Huth TCGv EA, val; 5058fcf5ef2aSThomas Huth 5059fcf5ef2aSThomas Huth CHK_SV; 5060fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5061fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5062fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5063fcf5ef2aSThomas Huth val = tcg_temp_new(); 5064fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 5065fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5066fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5067fcf5ef2aSThomas Huth tcg_temp_free(val); 5068fcf5ef2aSThomas Huth tcg_temp_free(EA); 5069fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5070fcf5ef2aSThomas Huth } 5071fcf5ef2aSThomas Huth 5072fcf5ef2aSThomas Huth /* dcdst */ 5073fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5074fcf5ef2aSThomas Huth { 5075fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5076fcf5ef2aSThomas Huth TCGv t0; 5077fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5078fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5079fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5080fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5081fcf5ef2aSThomas Huth tcg_temp_free(t0); 5082fcf5ef2aSThomas Huth } 5083fcf5ef2aSThomas Huth 508450728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 508550728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 508650728199SRoman Kapl { 508750728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 508850728199SRoman Kapl TCGv t0; 508950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 509050728199SRoman Kapl t0 = tcg_temp_new(); 509150728199SRoman Kapl gen_addr_reg_index(ctx, t0); 509250728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 509350728199SRoman Kapl tcg_temp_free(t0); 509450728199SRoman Kapl } 509550728199SRoman Kapl 5096fcf5ef2aSThomas Huth /* dcbt */ 5097fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5098fcf5ef2aSThomas Huth { 5099efe843d8SDavid Gibson /* 5100efe843d8SDavid Gibson * interpreted as no-op 5101efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5102efe843d8SDavid Gibson * does not generate any exception 5103fcf5ef2aSThomas Huth */ 5104fcf5ef2aSThomas Huth } 5105fcf5ef2aSThomas Huth 510650728199SRoman Kapl /* dcbtep */ 510750728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 510850728199SRoman Kapl { 5109efe843d8SDavid Gibson /* 5110efe843d8SDavid Gibson * interpreted as no-op 5111efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5112efe843d8SDavid Gibson * does not generate any exception 511350728199SRoman Kapl */ 511450728199SRoman Kapl } 511550728199SRoman Kapl 5116fcf5ef2aSThomas Huth /* dcbtst */ 5117fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5118fcf5ef2aSThomas Huth { 5119efe843d8SDavid Gibson /* 5120efe843d8SDavid Gibson * interpreted as no-op 5121efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5122efe843d8SDavid Gibson * does not generate any exception 5123fcf5ef2aSThomas Huth */ 5124fcf5ef2aSThomas Huth } 5125fcf5ef2aSThomas Huth 512650728199SRoman Kapl /* dcbtstep */ 512750728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 512850728199SRoman Kapl { 5129efe843d8SDavid Gibson /* 5130efe843d8SDavid Gibson * interpreted as no-op 5131efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5132efe843d8SDavid Gibson * does not generate any exception 513350728199SRoman Kapl */ 513450728199SRoman Kapl } 513550728199SRoman Kapl 5136fcf5ef2aSThomas Huth /* dcbtls */ 5137fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5138fcf5ef2aSThomas Huth { 5139fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5140fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5141fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5142fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5143fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5144fcf5ef2aSThomas Huth tcg_temp_free(t0); 5145fcf5ef2aSThomas Huth } 5146fcf5ef2aSThomas Huth 5147fcf5ef2aSThomas Huth /* dcbz */ 5148fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5149fcf5ef2aSThomas Huth { 5150fcf5ef2aSThomas Huth TCGv tcgv_addr; 5151fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5152fcf5ef2aSThomas Huth 5153fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5154fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 5155fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 5156fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5157fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5158fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 5159fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 5160fcf5ef2aSThomas Huth } 5161fcf5ef2aSThomas Huth 516250728199SRoman Kapl /* dcbzep */ 516350728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 516450728199SRoman Kapl { 516550728199SRoman Kapl TCGv tcgv_addr; 516650728199SRoman Kapl TCGv_i32 tcgv_op; 516750728199SRoman Kapl 516850728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 516950728199SRoman Kapl tcgv_addr = tcg_temp_new(); 517050728199SRoman Kapl tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 517150728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 517250728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 517350728199SRoman Kapl tcg_temp_free(tcgv_addr); 517450728199SRoman Kapl tcg_temp_free_i32(tcgv_op); 517550728199SRoman Kapl } 517650728199SRoman Kapl 5177fcf5ef2aSThomas Huth /* dst / dstt */ 5178fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5179fcf5ef2aSThomas Huth { 5180fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5181fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5182fcf5ef2aSThomas Huth } else { 5183fcf5ef2aSThomas Huth /* interpreted as no-op */ 5184fcf5ef2aSThomas Huth } 5185fcf5ef2aSThomas Huth } 5186fcf5ef2aSThomas Huth 5187fcf5ef2aSThomas Huth /* dstst /dststt */ 5188fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5189fcf5ef2aSThomas Huth { 5190fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5191fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5192fcf5ef2aSThomas Huth } else { 5193fcf5ef2aSThomas Huth /* interpreted as no-op */ 5194fcf5ef2aSThomas Huth } 5195fcf5ef2aSThomas Huth 5196fcf5ef2aSThomas Huth } 5197fcf5ef2aSThomas Huth 5198fcf5ef2aSThomas Huth /* dss / dssall */ 5199fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5200fcf5ef2aSThomas Huth { 5201fcf5ef2aSThomas Huth /* interpreted as no-op */ 5202fcf5ef2aSThomas Huth } 5203fcf5ef2aSThomas Huth 5204fcf5ef2aSThomas Huth /* icbi */ 5205fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5206fcf5ef2aSThomas Huth { 5207fcf5ef2aSThomas Huth TCGv t0; 5208fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5209fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5210fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5211fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5212fcf5ef2aSThomas Huth tcg_temp_free(t0); 5213fcf5ef2aSThomas Huth } 5214fcf5ef2aSThomas Huth 521550728199SRoman Kapl /* icbiep */ 521650728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 521750728199SRoman Kapl { 521850728199SRoman Kapl TCGv t0; 521950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 522050728199SRoman Kapl t0 = tcg_temp_new(); 522150728199SRoman Kapl gen_addr_reg_index(ctx, t0); 522250728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 522350728199SRoman Kapl tcg_temp_free(t0); 522450728199SRoman Kapl } 522550728199SRoman Kapl 5226fcf5ef2aSThomas Huth /* Optional: */ 5227fcf5ef2aSThomas Huth /* dcba */ 5228fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5229fcf5ef2aSThomas Huth { 5230efe843d8SDavid Gibson /* 5231efe843d8SDavid Gibson * interpreted as no-op 5232efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5233fcf5ef2aSThomas Huth * but does not generate any exception 5234fcf5ef2aSThomas Huth */ 5235fcf5ef2aSThomas Huth } 5236fcf5ef2aSThomas Huth 5237fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5238fcf5ef2aSThomas Huth /* Supervisor only: */ 5239fcf5ef2aSThomas Huth 5240fcf5ef2aSThomas Huth /* mfsr */ 5241fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5242fcf5ef2aSThomas Huth { 5243fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5244fcf5ef2aSThomas Huth GEN_PRIV; 5245fcf5ef2aSThomas Huth #else 5246fcf5ef2aSThomas Huth TCGv t0; 5247fcf5ef2aSThomas Huth 5248fcf5ef2aSThomas Huth CHK_SV; 5249fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5250fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5251fcf5ef2aSThomas Huth tcg_temp_free(t0); 5252fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5253fcf5ef2aSThomas Huth } 5254fcf5ef2aSThomas Huth 5255fcf5ef2aSThomas Huth /* mfsrin */ 5256fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5257fcf5ef2aSThomas Huth { 5258fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5259fcf5ef2aSThomas Huth GEN_PRIV; 5260fcf5ef2aSThomas Huth #else 5261fcf5ef2aSThomas Huth TCGv t0; 5262fcf5ef2aSThomas Huth 5263fcf5ef2aSThomas Huth CHK_SV; 5264fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5265e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5266fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5267fcf5ef2aSThomas Huth tcg_temp_free(t0); 5268fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5269fcf5ef2aSThomas Huth } 5270fcf5ef2aSThomas Huth 5271fcf5ef2aSThomas Huth /* mtsr */ 5272fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5273fcf5ef2aSThomas Huth { 5274fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5275fcf5ef2aSThomas Huth GEN_PRIV; 5276fcf5ef2aSThomas Huth #else 5277fcf5ef2aSThomas Huth TCGv t0; 5278fcf5ef2aSThomas Huth 5279fcf5ef2aSThomas Huth CHK_SV; 5280fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5281fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5282fcf5ef2aSThomas Huth tcg_temp_free(t0); 5283fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5284fcf5ef2aSThomas Huth } 5285fcf5ef2aSThomas Huth 5286fcf5ef2aSThomas Huth /* mtsrin */ 5287fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5288fcf5ef2aSThomas Huth { 5289fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5290fcf5ef2aSThomas Huth GEN_PRIV; 5291fcf5ef2aSThomas Huth #else 5292fcf5ef2aSThomas Huth TCGv t0; 5293fcf5ef2aSThomas Huth CHK_SV; 5294fcf5ef2aSThomas Huth 5295fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5296e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5297fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5298fcf5ef2aSThomas Huth tcg_temp_free(t0); 5299fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5300fcf5ef2aSThomas Huth } 5301fcf5ef2aSThomas Huth 5302fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5303fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5304fcf5ef2aSThomas Huth 5305fcf5ef2aSThomas Huth /* mfsr */ 5306fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5307fcf5ef2aSThomas Huth { 5308fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5309fcf5ef2aSThomas Huth GEN_PRIV; 5310fcf5ef2aSThomas Huth #else 5311fcf5ef2aSThomas Huth TCGv t0; 5312fcf5ef2aSThomas Huth 5313fcf5ef2aSThomas Huth CHK_SV; 5314fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5315fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5316fcf5ef2aSThomas Huth tcg_temp_free(t0); 5317fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5318fcf5ef2aSThomas Huth } 5319fcf5ef2aSThomas Huth 5320fcf5ef2aSThomas Huth /* mfsrin */ 5321fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5322fcf5ef2aSThomas Huth { 5323fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5324fcf5ef2aSThomas Huth GEN_PRIV; 5325fcf5ef2aSThomas Huth #else 5326fcf5ef2aSThomas Huth TCGv t0; 5327fcf5ef2aSThomas Huth 5328fcf5ef2aSThomas Huth CHK_SV; 5329fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5330e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5331fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5332fcf5ef2aSThomas Huth tcg_temp_free(t0); 5333fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5334fcf5ef2aSThomas Huth } 5335fcf5ef2aSThomas Huth 5336fcf5ef2aSThomas Huth /* mtsr */ 5337fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5338fcf5ef2aSThomas Huth { 5339fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5340fcf5ef2aSThomas Huth GEN_PRIV; 5341fcf5ef2aSThomas Huth #else 5342fcf5ef2aSThomas Huth TCGv t0; 5343fcf5ef2aSThomas Huth 5344fcf5ef2aSThomas Huth CHK_SV; 5345fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 5346fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5347fcf5ef2aSThomas Huth tcg_temp_free(t0); 5348fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5349fcf5ef2aSThomas Huth } 5350fcf5ef2aSThomas Huth 5351fcf5ef2aSThomas Huth /* mtsrin */ 5352fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5353fcf5ef2aSThomas Huth { 5354fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5355fcf5ef2aSThomas Huth GEN_PRIV; 5356fcf5ef2aSThomas Huth #else 5357fcf5ef2aSThomas Huth TCGv t0; 5358fcf5ef2aSThomas Huth 5359fcf5ef2aSThomas Huth CHK_SV; 5360fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5361e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5362fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5363fcf5ef2aSThomas Huth tcg_temp_free(t0); 5364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5365fcf5ef2aSThomas Huth } 5366fcf5ef2aSThomas Huth 5367fcf5ef2aSThomas Huth /* slbmte */ 5368fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 5369fcf5ef2aSThomas Huth { 5370fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5371fcf5ef2aSThomas Huth GEN_PRIV; 5372fcf5ef2aSThomas Huth #else 5373fcf5ef2aSThomas Huth CHK_SV; 5374fcf5ef2aSThomas Huth 5375fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 5376fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5377fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5378fcf5ef2aSThomas Huth } 5379fcf5ef2aSThomas Huth 5380fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 5381fcf5ef2aSThomas Huth { 5382fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5383fcf5ef2aSThomas Huth GEN_PRIV; 5384fcf5ef2aSThomas Huth #else 5385fcf5ef2aSThomas Huth CHK_SV; 5386fcf5ef2aSThomas Huth 5387fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5388fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5389fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5390fcf5ef2aSThomas Huth } 5391fcf5ef2aSThomas Huth 5392fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 5393fcf5ef2aSThomas Huth { 5394fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5395fcf5ef2aSThomas Huth GEN_PRIV; 5396fcf5ef2aSThomas Huth #else 5397fcf5ef2aSThomas Huth CHK_SV; 5398fcf5ef2aSThomas Huth 5399fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5400fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5401fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5402fcf5ef2aSThomas Huth } 5403fcf5ef2aSThomas Huth 5404fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 5405fcf5ef2aSThomas Huth { 5406fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5407fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5408fcf5ef2aSThomas Huth #else 5409fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 5410fcf5ef2aSThomas Huth 5411fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 5412fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 5413fcf5ef2aSThomas Huth return; 5414fcf5ef2aSThomas Huth } 5415fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 5416fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5417fcf5ef2aSThomas Huth l1 = gen_new_label(); 5418fcf5ef2aSThomas Huth l2 = gen_new_label(); 5419fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5420fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 5421efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 5422fcf5ef2aSThomas Huth tcg_gen_br(l2); 5423fcf5ef2aSThomas Huth gen_set_label(l1); 5424fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 5425fcf5ef2aSThomas Huth gen_set_label(l2); 5426fcf5ef2aSThomas Huth #endif 5427fcf5ef2aSThomas Huth } 5428fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5429fcf5ef2aSThomas Huth 5430fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5431fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5432fcf5ef2aSThomas Huth 5433fcf5ef2aSThomas Huth /* tlbia */ 5434fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5435fcf5ef2aSThomas Huth { 5436fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5437fcf5ef2aSThomas Huth GEN_PRIV; 5438fcf5ef2aSThomas Huth #else 5439fcf5ef2aSThomas Huth CHK_HV; 5440fcf5ef2aSThomas Huth 5441fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5442fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5443fcf5ef2aSThomas Huth } 5444fcf5ef2aSThomas Huth 5445fcf5ef2aSThomas Huth /* tlbiel */ 5446fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 5447fcf5ef2aSThomas Huth { 5448fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5449fcf5ef2aSThomas Huth GEN_PRIV; 5450fcf5ef2aSThomas Huth #else 545192fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 545292fb92d3SMatheus Ferst 545392fb92d3SMatheus Ferst if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) { 545492fb92d3SMatheus Ferst /* 545592fb92d3SMatheus Ferst * tlbiel is privileged except when PSR=0 and HR=1, making it 545692fb92d3SMatheus Ferst * hypervisor privileged. 545792fb92d3SMatheus Ferst */ 545892fb92d3SMatheus Ferst GEN_PRIV; 545992fb92d3SMatheus Ferst } 5460fcf5ef2aSThomas Huth 5461fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5462fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5463fcf5ef2aSThomas Huth } 5464fcf5ef2aSThomas Huth 5465fcf5ef2aSThomas Huth /* tlbie */ 5466fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 5467fcf5ef2aSThomas Huth { 5468fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5469fcf5ef2aSThomas Huth GEN_PRIV; 5470fcf5ef2aSThomas Huth #else 547192fb92d3SMatheus Ferst bool psr = (ctx->opcode >> 17) & 0x1; 5472fcf5ef2aSThomas Huth TCGv_i32 t1; 5473c6fd28fdSSuraj Jitindar Singh 547492fb92d3SMatheus Ferst if (ctx->pr) { 547592fb92d3SMatheus Ferst /* tlbie is privileged... */ 547692fb92d3SMatheus Ferst GEN_PRIV; 547792fb92d3SMatheus Ferst } else if (!ctx->hv) { 547892fb92d3SMatheus Ferst if (!ctx->gtse || (!psr && ctx->hr)) { 547992fb92d3SMatheus Ferst /* 548092fb92d3SMatheus Ferst * ... except when GTSE=0 or when PSR=0 and HR=1, making it 548192fb92d3SMatheus Ferst * hypervisor privileged. 548292fb92d3SMatheus Ferst */ 548392fb92d3SMatheus Ferst GEN_PRIV; 548492fb92d3SMatheus Ferst } 5485c6fd28fdSSuraj Jitindar Singh } 5486fcf5ef2aSThomas Huth 5487fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 5488fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5489fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 5490fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 5491fcf5ef2aSThomas Huth tcg_temp_free(t0); 5492fcf5ef2aSThomas Huth } else { 5493fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5494fcf5ef2aSThomas Huth } 5495fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 5496fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5497fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 5498fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 5499fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5500fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5501fcf5ef2aSThomas Huth } 5502fcf5ef2aSThomas Huth 5503fcf5ef2aSThomas Huth /* tlbsync */ 5504fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5505fcf5ef2aSThomas Huth { 5506fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5507fcf5ef2aSThomas Huth GEN_PRIV; 5508fcf5ef2aSThomas Huth #else 550991c60f12SCédric Le Goater 551091c60f12SCédric Le Goater if (ctx->gtse) { 551191c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 551291c60f12SCédric Le Goater } else { 551391c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 551491c60f12SCédric Le Goater } 5515fcf5ef2aSThomas Huth 5516fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5517fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5518fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5519fcf5ef2aSThomas Huth } 5520fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5521fcf5ef2aSThomas Huth } 5522fcf5ef2aSThomas Huth 5523fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5524fcf5ef2aSThomas Huth /* slbia */ 5525fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 5526fcf5ef2aSThomas Huth { 5527fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5528fcf5ef2aSThomas Huth GEN_PRIV; 5529fcf5ef2aSThomas Huth #else 55300418bf78SNicholas Piggin uint32_t ih = (ctx->opcode >> 21) & 0x7; 55310418bf78SNicholas Piggin TCGv_i32 t0 = tcg_const_i32(ih); 55320418bf78SNicholas Piggin 5533fcf5ef2aSThomas Huth CHK_SV; 5534fcf5ef2aSThomas Huth 55350418bf78SNicholas Piggin gen_helper_slbia(cpu_env, t0); 55363119154dSPhilippe Mathieu-Daudé tcg_temp_free_i32(t0); 5537fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5538fcf5ef2aSThomas Huth } 5539fcf5ef2aSThomas Huth 5540fcf5ef2aSThomas Huth /* slbie */ 5541fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 5542fcf5ef2aSThomas Huth { 5543fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5544fcf5ef2aSThomas Huth GEN_PRIV; 5545fcf5ef2aSThomas Huth #else 5546fcf5ef2aSThomas Huth CHK_SV; 5547fcf5ef2aSThomas Huth 5548fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5549fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5550fcf5ef2aSThomas Huth } 5551a63f1dfcSNikunj A Dadhania 5552a63f1dfcSNikunj A Dadhania /* slbieg */ 5553a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 5554a63f1dfcSNikunj A Dadhania { 5555a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 5556a63f1dfcSNikunj A Dadhania GEN_PRIV; 5557a63f1dfcSNikunj A Dadhania #else 5558a63f1dfcSNikunj A Dadhania CHK_SV; 5559a63f1dfcSNikunj A Dadhania 5560a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5561a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 5562a63f1dfcSNikunj A Dadhania } 5563a63f1dfcSNikunj A Dadhania 556462d897caSNikunj A Dadhania /* slbsync */ 556562d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 556662d897caSNikunj A Dadhania { 556762d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 556862d897caSNikunj A Dadhania GEN_PRIV; 556962d897caSNikunj A Dadhania #else 557062d897caSNikunj A Dadhania CHK_SV; 557162d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 557262d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 557362d897caSNikunj A Dadhania } 557462d897caSNikunj A Dadhania 5575fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5576fcf5ef2aSThomas Huth 5577fcf5ef2aSThomas Huth /*** External control ***/ 5578fcf5ef2aSThomas Huth /* Optional: */ 5579fcf5ef2aSThomas Huth 5580fcf5ef2aSThomas Huth /* eciwx */ 5581fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5582fcf5ef2aSThomas Huth { 5583fcf5ef2aSThomas Huth TCGv t0; 5584fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5585fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5586fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5587fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5588c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5589c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5590fcf5ef2aSThomas Huth tcg_temp_free(t0); 5591fcf5ef2aSThomas Huth } 5592fcf5ef2aSThomas Huth 5593fcf5ef2aSThomas Huth /* ecowx */ 5594fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5595fcf5ef2aSThomas Huth { 5596fcf5ef2aSThomas Huth TCGv t0; 5597fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5598fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5599fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5600fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5601c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5602c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5603fcf5ef2aSThomas Huth tcg_temp_free(t0); 5604fcf5ef2aSThomas Huth } 5605fcf5ef2aSThomas Huth 5606fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 5607fcf5ef2aSThomas Huth 5608fcf5ef2aSThomas Huth /* abs - abs. */ 5609fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 5610fcf5ef2aSThomas Huth { 5611fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5612fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5613fe21b785SRichard Henderson 5614fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5615efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5616fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5617fcf5ef2aSThomas Huth } 5618efe843d8SDavid Gibson } 5619fcf5ef2aSThomas Huth 5620fcf5ef2aSThomas Huth /* abso - abso. */ 5621fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 5622fcf5ef2aSThomas Huth { 5623fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5624fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5625fe21b785SRichard Henderson 5626fe21b785SRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); 5627fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5628fe21b785SRichard Henderson tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 5629efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5630fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5631fcf5ef2aSThomas Huth } 5632efe843d8SDavid Gibson } 5633fcf5ef2aSThomas Huth 5634fcf5ef2aSThomas Huth /* clcs */ 5635fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 5636fcf5ef2aSThomas Huth { 5637fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 5638fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5639fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5640fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 5641fcf5ef2aSThomas Huth } 5642fcf5ef2aSThomas Huth 5643fcf5ef2aSThomas Huth /* div - div. */ 5644fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 5645fcf5ef2aSThomas Huth { 5646fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5647fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5648efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5649fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5650fcf5ef2aSThomas Huth } 5651efe843d8SDavid Gibson } 5652fcf5ef2aSThomas Huth 5653fcf5ef2aSThomas Huth /* divo - divo. */ 5654fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 5655fcf5ef2aSThomas Huth { 5656fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5657fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5658efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5659fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5660fcf5ef2aSThomas Huth } 5661efe843d8SDavid Gibson } 5662fcf5ef2aSThomas Huth 5663fcf5ef2aSThomas Huth /* divs - divs. */ 5664fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 5665fcf5ef2aSThomas Huth { 5666fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 5667fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 5668efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5669fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5670fcf5ef2aSThomas Huth } 5671efe843d8SDavid Gibson } 5672fcf5ef2aSThomas Huth 5673fcf5ef2aSThomas Huth /* divso - divso. */ 5674fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 5675fcf5ef2aSThomas Huth { 5676fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 5677fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5678efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5679fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5680fcf5ef2aSThomas Huth } 5681efe843d8SDavid Gibson } 5682fcf5ef2aSThomas Huth 5683fcf5ef2aSThomas Huth /* doz - doz. */ 5684fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 5685fcf5ef2aSThomas Huth { 5686fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5687fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5688efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5689efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5690efe843d8SDavid Gibson tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 5691efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)]); 5692fcf5ef2aSThomas Huth tcg_gen_br(l2); 5693fcf5ef2aSThomas Huth gen_set_label(l1); 5694fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5695fcf5ef2aSThomas Huth gen_set_label(l2); 5696efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5697fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5698fcf5ef2aSThomas Huth } 5699efe843d8SDavid Gibson } 5700fcf5ef2aSThomas Huth 5701fcf5ef2aSThomas Huth /* dozo - dozo. */ 5702fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 5703fcf5ef2aSThomas Huth { 5704fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5705fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5706fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5707fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5708fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5709fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5710fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5711efe843d8SDavid Gibson tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], 5712efe843d8SDavid Gibson cpu_gpr[rA(ctx->opcode)], l1); 5713fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5714fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5715fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 5716fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5717fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 5718fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5719fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5720fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5721fcf5ef2aSThomas Huth tcg_gen_br(l2); 5722fcf5ef2aSThomas Huth gen_set_label(l1); 5723fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5724fcf5ef2aSThomas Huth gen_set_label(l2); 5725fcf5ef2aSThomas Huth tcg_temp_free(t0); 5726fcf5ef2aSThomas Huth tcg_temp_free(t1); 5727fcf5ef2aSThomas Huth tcg_temp_free(t2); 5728efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5729fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5730fcf5ef2aSThomas Huth } 5731efe843d8SDavid Gibson } 5732fcf5ef2aSThomas Huth 5733fcf5ef2aSThomas Huth /* dozi */ 5734fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 5735fcf5ef2aSThomas Huth { 5736fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5737fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5738fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5739fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5740fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5741fcf5ef2aSThomas Huth tcg_gen_br(l2); 5742fcf5ef2aSThomas Huth gen_set_label(l1); 5743fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5744fcf5ef2aSThomas Huth gen_set_label(l2); 5745efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5746fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5747fcf5ef2aSThomas Huth } 5748efe843d8SDavid Gibson } 5749fcf5ef2aSThomas Huth 5750fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5751fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5752fcf5ef2aSThomas Huth { 5753fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5754fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5755fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5756fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5757fcf5ef2aSThomas Huth 5758fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5759fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5760fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5761fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5762fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5763fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5764fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5765efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5766fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5767efe843d8SDavid Gibson } 5768fcf5ef2aSThomas Huth tcg_temp_free(t0); 5769fcf5ef2aSThomas Huth } 5770fcf5ef2aSThomas Huth 5771fcf5ef2aSThomas Huth /* maskg - maskg. */ 5772fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5773fcf5ef2aSThomas Huth { 5774fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5775fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5776fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5777fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5778fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5779fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5780fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5781fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5782fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5783fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5784fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5785fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5786fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5787fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5788fcf5ef2aSThomas Huth gen_set_label(l1); 5789fcf5ef2aSThomas Huth tcg_temp_free(t0); 5790fcf5ef2aSThomas Huth tcg_temp_free(t1); 5791fcf5ef2aSThomas Huth tcg_temp_free(t2); 5792fcf5ef2aSThomas Huth tcg_temp_free(t3); 5793efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5794fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5795fcf5ef2aSThomas Huth } 5796efe843d8SDavid Gibson } 5797fcf5ef2aSThomas Huth 5798fcf5ef2aSThomas Huth /* maskir - maskir. */ 5799fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5800fcf5ef2aSThomas Huth { 5801fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5802fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5803fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5804fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5805fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5806fcf5ef2aSThomas Huth tcg_temp_free(t0); 5807fcf5ef2aSThomas Huth tcg_temp_free(t1); 5808efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5809fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5810fcf5ef2aSThomas Huth } 5811efe843d8SDavid Gibson } 5812fcf5ef2aSThomas Huth 5813fcf5ef2aSThomas Huth /* mul - mul. */ 5814fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5815fcf5ef2aSThomas Huth { 5816fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5817fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5818fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5819fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5820fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5821fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5822fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5823fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5824fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5825fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5826fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5827fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5828fcf5ef2aSThomas Huth tcg_temp_free(t2); 5829efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5830fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5831fcf5ef2aSThomas Huth } 5832efe843d8SDavid Gibson } 5833fcf5ef2aSThomas Huth 5834fcf5ef2aSThomas Huth /* mulo - mulo. */ 5835fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5836fcf5ef2aSThomas Huth { 5837fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5838fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5839fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5840fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5841fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5842fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5843fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5844fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5845fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5846fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5847fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5848fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5849fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5850fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5851fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5852fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5853fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5854fcf5ef2aSThomas Huth gen_set_label(l1); 5855fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5856fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5857fcf5ef2aSThomas Huth tcg_temp_free(t2); 5858efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5859fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5860fcf5ef2aSThomas Huth } 5861efe843d8SDavid Gibson } 5862fcf5ef2aSThomas Huth 5863fcf5ef2aSThomas Huth /* nabs - nabs. */ 5864fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5865fcf5ef2aSThomas Huth { 5866fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5867fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5868fe21b785SRichard Henderson 5869fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5870fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5871efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5872fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5873fcf5ef2aSThomas Huth } 5874efe843d8SDavid Gibson } 5875fcf5ef2aSThomas Huth 5876fcf5ef2aSThomas Huth /* nabso - nabso. */ 5877fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5878fcf5ef2aSThomas Huth { 5879fe21b785SRichard Henderson TCGv d = cpu_gpr[rD(ctx->opcode)]; 5880fe21b785SRichard Henderson TCGv a = cpu_gpr[rA(ctx->opcode)]; 5881fe21b785SRichard Henderson 5882fe21b785SRichard Henderson tcg_gen_abs_tl(d, a); 5883fe21b785SRichard Henderson tcg_gen_neg_tl(d, d); 5884fcf5ef2aSThomas Huth /* nabs never overflows */ 5885fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5886efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5887fe21b785SRichard Henderson gen_set_Rc0(ctx, d); 5888fcf5ef2aSThomas Huth } 5889efe843d8SDavid Gibson } 5890fcf5ef2aSThomas Huth 5891fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5892fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5893fcf5ef2aSThomas Huth { 5894fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5895fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5896fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5897fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5898fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5899fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5900efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 5901efe843d8SDavid Gibson ~MASK(mb, me)); 5902fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5903fcf5ef2aSThomas Huth tcg_temp_free(t0); 5904efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5905fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5906fcf5ef2aSThomas Huth } 5907efe843d8SDavid Gibson } 5908fcf5ef2aSThomas Huth 5909fcf5ef2aSThomas Huth /* rrib - rrib. */ 5910fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5911fcf5ef2aSThomas Huth { 5912fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5913fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5914fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5915fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5916fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5917fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5918fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5919fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5920fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5921fcf5ef2aSThomas Huth tcg_temp_free(t0); 5922fcf5ef2aSThomas Huth tcg_temp_free(t1); 5923efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5924fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5925fcf5ef2aSThomas Huth } 5926efe843d8SDavid Gibson } 5927fcf5ef2aSThomas Huth 5928fcf5ef2aSThomas Huth /* sle - sle. */ 5929fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5930fcf5ef2aSThomas Huth { 5931fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5932fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5933fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5934fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5935fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5936fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5937fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5938fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5939fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5940fcf5ef2aSThomas Huth tcg_temp_free(t0); 5941fcf5ef2aSThomas Huth tcg_temp_free(t1); 5942efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5943fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5944fcf5ef2aSThomas Huth } 5945efe843d8SDavid Gibson } 5946fcf5ef2aSThomas Huth 5947fcf5ef2aSThomas Huth /* sleq - sleq. */ 5948fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5949fcf5ef2aSThomas Huth { 5950fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5951fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5952fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5953fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5954fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5955fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5956fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5957fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5958fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5959fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5960fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5961fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5962fcf5ef2aSThomas Huth tcg_temp_free(t0); 5963fcf5ef2aSThomas Huth tcg_temp_free(t1); 5964fcf5ef2aSThomas Huth tcg_temp_free(t2); 5965efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5966fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5967fcf5ef2aSThomas Huth } 5968efe843d8SDavid Gibson } 5969fcf5ef2aSThomas Huth 5970fcf5ef2aSThomas Huth /* sliq - sliq. */ 5971fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5972fcf5ef2aSThomas Huth { 5973fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5974fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5975fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5976fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5977fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5978fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5979fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5980fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5981fcf5ef2aSThomas Huth tcg_temp_free(t0); 5982fcf5ef2aSThomas Huth tcg_temp_free(t1); 5983efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 5984fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5985fcf5ef2aSThomas Huth } 5986efe843d8SDavid Gibson } 5987fcf5ef2aSThomas Huth 5988fcf5ef2aSThomas Huth /* slliq - slliq. */ 5989fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5990fcf5ef2aSThomas Huth { 5991fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5992fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5993fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5994fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5995fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5996fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5997fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5998fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5999fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6000fcf5ef2aSThomas Huth tcg_temp_free(t0); 6001fcf5ef2aSThomas Huth tcg_temp_free(t1); 6002efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6003fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6004fcf5ef2aSThomas Huth } 6005efe843d8SDavid Gibson } 6006fcf5ef2aSThomas Huth 6007fcf5ef2aSThomas Huth /* sllq - sllq. */ 6008fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 6009fcf5ef2aSThomas Huth { 6010fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6011fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6012fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6013fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6014fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6015fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6016fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6017fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 6018fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6019fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6020fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6021fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6022fcf5ef2aSThomas Huth tcg_gen_br(l2); 6023fcf5ef2aSThomas Huth gen_set_label(l1); 6024fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6025fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6026fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 6027fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6028fcf5ef2aSThomas Huth gen_set_label(l2); 6029fcf5ef2aSThomas Huth tcg_temp_free(t0); 6030fcf5ef2aSThomas Huth tcg_temp_free(t1); 6031fcf5ef2aSThomas Huth tcg_temp_free(t2); 6032efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6033fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6034fcf5ef2aSThomas Huth } 6035efe843d8SDavid Gibson } 6036fcf5ef2aSThomas Huth 6037fcf5ef2aSThomas Huth /* slq - slq. */ 6038fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 6039fcf5ef2aSThomas Huth { 6040fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6041fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6042fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6043fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6044fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6045fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6046fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6047fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6048fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6049fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6050fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6051fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6052fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6053fcf5ef2aSThomas Huth gen_set_label(l1); 6054fcf5ef2aSThomas Huth tcg_temp_free(t0); 6055fcf5ef2aSThomas Huth tcg_temp_free(t1); 6056efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6057fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6058fcf5ef2aSThomas Huth } 6059efe843d8SDavid Gibson } 6060fcf5ef2aSThomas Huth 6061fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 6062fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 6063fcf5ef2aSThomas Huth { 6064fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6065fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6066fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6067fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6068fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6069fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6070fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 6071fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6072fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6073fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 6074fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 6075fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6076fcf5ef2aSThomas Huth gen_set_label(l1); 6077fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 6078fcf5ef2aSThomas Huth tcg_temp_free(t0); 6079fcf5ef2aSThomas Huth tcg_temp_free(t1); 6080efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6081fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6082fcf5ef2aSThomas Huth } 6083efe843d8SDavid Gibson } 6084fcf5ef2aSThomas Huth 6085fcf5ef2aSThomas Huth /* sraq - sraq. */ 6086fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 6087fcf5ef2aSThomas Huth { 6088fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6089fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6090fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6091fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6092fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6093fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6094fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6095fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 6096fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 6097fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 6098fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 6099fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6100fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6101fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 6102fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 6103fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 6104fcf5ef2aSThomas Huth gen_set_label(l1); 6105fcf5ef2aSThomas Huth tcg_temp_free(t0); 6106fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 6107fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 6108fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 6109fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 6110fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 6111fcf5ef2aSThomas Huth gen_set_label(l2); 6112fcf5ef2aSThomas Huth tcg_temp_free(t1); 6113fcf5ef2aSThomas Huth tcg_temp_free(t2); 6114efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6115fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6116fcf5ef2aSThomas Huth } 6117efe843d8SDavid Gibson } 6118fcf5ef2aSThomas Huth 6119fcf5ef2aSThomas Huth /* sre - sre. */ 6120fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 6121fcf5ef2aSThomas Huth { 6122fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6123fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6124fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6125fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6126fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6127fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6128fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6129fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6130fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6131fcf5ef2aSThomas Huth tcg_temp_free(t0); 6132fcf5ef2aSThomas Huth tcg_temp_free(t1); 6133efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6134fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6135fcf5ef2aSThomas Huth } 6136efe843d8SDavid Gibson } 6137fcf5ef2aSThomas Huth 6138fcf5ef2aSThomas Huth /* srea - srea. */ 6139fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 6140fcf5ef2aSThomas Huth { 6141fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6142fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6143fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6144fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6145fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6146fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 6147fcf5ef2aSThomas Huth tcg_temp_free(t0); 6148fcf5ef2aSThomas Huth tcg_temp_free(t1); 6149efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6150fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6151fcf5ef2aSThomas Huth } 6152efe843d8SDavid Gibson } 6153fcf5ef2aSThomas Huth 6154fcf5ef2aSThomas Huth /* sreq */ 6155fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 6156fcf5ef2aSThomas Huth { 6157fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6158fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6159fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 6160fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 6161fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6162fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 6163fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 6164fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 6165fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6166fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 6167fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 6168fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6169fcf5ef2aSThomas Huth tcg_temp_free(t0); 6170fcf5ef2aSThomas Huth tcg_temp_free(t1); 6171fcf5ef2aSThomas Huth tcg_temp_free(t2); 6172efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6173fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6174fcf5ef2aSThomas Huth } 6175efe843d8SDavid Gibson } 6176fcf5ef2aSThomas Huth 6177fcf5ef2aSThomas Huth /* sriq */ 6178fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 6179fcf5ef2aSThomas Huth { 6180fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6181fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6182fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6183fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6184fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 6185fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6186fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6187fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6188fcf5ef2aSThomas Huth tcg_temp_free(t0); 6189fcf5ef2aSThomas Huth tcg_temp_free(t1); 6190efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6191fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6192fcf5ef2aSThomas Huth } 6193efe843d8SDavid Gibson } 6194fcf5ef2aSThomas Huth 6195fcf5ef2aSThomas Huth /* srliq */ 6196fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 6197fcf5ef2aSThomas Huth { 6198fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 6199fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6200fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6201fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 6202fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6203fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 6204fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 6205fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 6206fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6207fcf5ef2aSThomas Huth tcg_temp_free(t0); 6208fcf5ef2aSThomas Huth tcg_temp_free(t1); 6209efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6210fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6211fcf5ef2aSThomas Huth } 6212efe843d8SDavid Gibson } 6213fcf5ef2aSThomas Huth 6214fcf5ef2aSThomas Huth /* srlq */ 6215fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 6216fcf5ef2aSThomas Huth { 6217fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6218fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 6219fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 6220fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 6221fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 6222fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 6223fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 6224fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 6225fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 6226fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6227fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 6228fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 6229fcf5ef2aSThomas Huth tcg_gen_br(l2); 6230fcf5ef2aSThomas Huth gen_set_label(l1); 6231fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 6232fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 6233fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 6234fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 6235fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 6236fcf5ef2aSThomas Huth gen_set_label(l2); 6237fcf5ef2aSThomas Huth tcg_temp_free(t0); 6238fcf5ef2aSThomas Huth tcg_temp_free(t1); 6239fcf5ef2aSThomas Huth tcg_temp_free(t2); 6240efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6241fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6242fcf5ef2aSThomas Huth } 6243efe843d8SDavid Gibson } 6244fcf5ef2aSThomas Huth 6245fcf5ef2aSThomas Huth /* srq */ 6246fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 6247fcf5ef2aSThomas Huth { 6248fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6249fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 6250fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 6251fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 6252fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 6253fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 6254fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 6255fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 6256fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 6257fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 6258fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 6259fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 6260fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 6261fcf5ef2aSThomas Huth gen_set_label(l1); 6262fcf5ef2aSThomas Huth tcg_temp_free(t0); 6263fcf5ef2aSThomas Huth tcg_temp_free(t1); 6264efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 6265fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 6266fcf5ef2aSThomas Huth } 6267efe843d8SDavid Gibson } 6268fcf5ef2aSThomas Huth 6269fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 6270fcf5ef2aSThomas Huth 6271fcf5ef2aSThomas Huth /* dsa */ 6272fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 6273fcf5ef2aSThomas Huth { 6274fcf5ef2aSThomas Huth /* XXX: TODO */ 6275fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6276fcf5ef2aSThomas Huth } 6277fcf5ef2aSThomas Huth 6278fcf5ef2aSThomas Huth /* esa */ 6279fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 6280fcf5ef2aSThomas Huth { 6281fcf5ef2aSThomas Huth /* XXX: TODO */ 6282fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6283fcf5ef2aSThomas Huth } 6284fcf5ef2aSThomas Huth 6285fcf5ef2aSThomas Huth /* mfrom */ 6286fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 6287fcf5ef2aSThomas Huth { 6288fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6289fcf5ef2aSThomas Huth GEN_PRIV; 6290fcf5ef2aSThomas Huth #else 6291fcf5ef2aSThomas Huth CHK_SV; 6292fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 6293fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6294fcf5ef2aSThomas Huth } 6295fcf5ef2aSThomas Huth 6296fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 6297fcf5ef2aSThomas Huth 6298fcf5ef2aSThomas Huth /* tlbld */ 6299fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 6300fcf5ef2aSThomas Huth { 6301fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6302fcf5ef2aSThomas Huth GEN_PRIV; 6303fcf5ef2aSThomas Huth #else 6304fcf5ef2aSThomas Huth CHK_SV; 6305fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6306fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6307fcf5ef2aSThomas Huth } 6308fcf5ef2aSThomas Huth 6309fcf5ef2aSThomas Huth /* tlbli */ 6310fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 6311fcf5ef2aSThomas Huth { 6312fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6313fcf5ef2aSThomas Huth GEN_PRIV; 6314fcf5ef2aSThomas Huth #else 6315fcf5ef2aSThomas Huth CHK_SV; 6316fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6317fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6318fcf5ef2aSThomas Huth } 6319fcf5ef2aSThomas Huth 6320fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 6321fcf5ef2aSThomas Huth 6322fcf5ef2aSThomas Huth /* clf */ 6323fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 6324fcf5ef2aSThomas Huth { 6325fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 6326fcf5ef2aSThomas Huth } 6327fcf5ef2aSThomas Huth 6328fcf5ef2aSThomas Huth /* cli */ 6329fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 6330fcf5ef2aSThomas Huth { 6331fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6332fcf5ef2aSThomas Huth GEN_PRIV; 6333fcf5ef2aSThomas Huth #else 6334fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 6335fcf5ef2aSThomas Huth CHK_SV; 6336fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6337fcf5ef2aSThomas Huth } 6338fcf5ef2aSThomas Huth 6339fcf5ef2aSThomas Huth /* dclst */ 6340fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 6341fcf5ef2aSThomas Huth { 6342fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 6343fcf5ef2aSThomas Huth } 6344fcf5ef2aSThomas Huth 6345fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 6346fcf5ef2aSThomas Huth { 6347fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6348fcf5ef2aSThomas Huth GEN_PRIV; 6349fcf5ef2aSThomas Huth #else 6350fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 6351fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 6352fcf5ef2aSThomas Huth TCGv t0; 6353fcf5ef2aSThomas Huth 6354fcf5ef2aSThomas Huth CHK_SV; 6355fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6356fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6357e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 6358fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 6359fcf5ef2aSThomas Huth tcg_temp_free(t0); 6360efe843d8SDavid Gibson if (ra != 0 && ra != rd) { 6361fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 6362efe843d8SDavid Gibson } 6363fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6364fcf5ef2aSThomas Huth } 6365fcf5ef2aSThomas Huth 6366fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 6367fcf5ef2aSThomas Huth { 6368fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6369fcf5ef2aSThomas Huth GEN_PRIV; 6370fcf5ef2aSThomas Huth #else 6371fcf5ef2aSThomas Huth TCGv t0; 6372fcf5ef2aSThomas Huth 6373fcf5ef2aSThomas Huth CHK_SV; 6374fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6375fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6376fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6377fcf5ef2aSThomas Huth tcg_temp_free(t0); 6378fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6379fcf5ef2aSThomas Huth } 6380fcf5ef2aSThomas Huth 6381fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 6382fcf5ef2aSThomas Huth { 6383fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6384fcf5ef2aSThomas Huth GEN_PRIV; 6385fcf5ef2aSThomas Huth #else 6386fcf5ef2aSThomas Huth CHK_SV; 6387fcf5ef2aSThomas Huth 6388fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 638959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6390fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6391fcf5ef2aSThomas Huth } 6392fcf5ef2aSThomas Huth 6393fcf5ef2aSThomas Huth /* svc is not implemented for now */ 6394fcf5ef2aSThomas Huth 6395fcf5ef2aSThomas Huth /* BookE specific instructions */ 6396fcf5ef2aSThomas Huth 6397fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6398fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 6399fcf5ef2aSThomas Huth { 6400fcf5ef2aSThomas Huth /* XXX: TODO */ 6401fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6402fcf5ef2aSThomas Huth } 6403fcf5ef2aSThomas Huth 6404fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6405fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 6406fcf5ef2aSThomas Huth { 6407fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6408fcf5ef2aSThomas Huth GEN_PRIV; 6409fcf5ef2aSThomas Huth #else 6410fcf5ef2aSThomas Huth TCGv t0; 6411fcf5ef2aSThomas Huth 6412fcf5ef2aSThomas Huth CHK_SV; 6413fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6414fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6415fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6416fcf5ef2aSThomas Huth tcg_temp_free(t0); 6417fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6418fcf5ef2aSThomas Huth } 6419fcf5ef2aSThomas Huth 6420fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 6421fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 6422fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 6423fcf5ef2aSThomas Huth { 6424fcf5ef2aSThomas Huth TCGv t0, t1; 6425fcf5ef2aSThomas Huth 6426fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 6427fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 6428fcf5ef2aSThomas Huth 6429fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 6430fcf5ef2aSThomas Huth case 0x05: 6431fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 6432fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 6433fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 6434fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 6435fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6436fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6437fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6438fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6439fcf5ef2aSThomas Huth break; 6440fcf5ef2aSThomas Huth case 0x04: 6441fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 6442fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 6443fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6444fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6445fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6446fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6447fcf5ef2aSThomas Huth break; 6448fcf5ef2aSThomas Huth case 0x01: 6449fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 6450fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 6451fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 6452fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 6453fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6454fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 6455fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 6456fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 6457fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 6458fcf5ef2aSThomas Huth break; 6459fcf5ef2aSThomas Huth case 0x00: 6460fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 6461fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 6462fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6463fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 6464fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 6465fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 6466fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 6467fcf5ef2aSThomas Huth break; 6468fcf5ef2aSThomas Huth case 0x0D: 6469fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 6470fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 6471fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 6472fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 6473fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6474fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 6475fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 6476fcf5ef2aSThomas Huth break; 6477fcf5ef2aSThomas Huth case 0x0C: 6478fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 6479fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 6480fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6481fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 6482fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 6483fcf5ef2aSThomas Huth break; 6484fcf5ef2aSThomas Huth } 6485fcf5ef2aSThomas Huth if (opc2 & 0x04) { 6486fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 6487fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 6488fcf5ef2aSThomas Huth if (opc2 & 0x02) { 6489fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 6490fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 6491fcf5ef2aSThomas Huth } else { 6492fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 6493fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 6494fcf5ef2aSThomas Huth } 6495fcf5ef2aSThomas Huth 6496fcf5ef2aSThomas Huth if (opc3 & 0x12) { 6497fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 6498fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6499fcf5ef2aSThomas Huth 6500fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6501fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 6502fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 6503fcf5ef2aSThomas Huth } 6504fcf5ef2aSThomas Huth if (opc3 & 0x01) { 6505fcf5ef2aSThomas Huth /* Signed */ 6506fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 6507fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 6508fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 6509fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 6510fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6511fcf5ef2aSThomas Huth /* Saturate */ 6512fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 6513fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 6514fcf5ef2aSThomas Huth } 6515fcf5ef2aSThomas Huth } else { 6516fcf5ef2aSThomas Huth /* Unsigned */ 6517fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 6518fcf5ef2aSThomas Huth if (opc3 & 0x02) { 6519fcf5ef2aSThomas Huth /* Saturate */ 6520fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 6521fcf5ef2aSThomas Huth } 6522fcf5ef2aSThomas Huth } 6523fcf5ef2aSThomas Huth if (opc3 & 0x10) { 6524fcf5ef2aSThomas Huth /* Check overflow */ 6525fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 6526fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 6527fcf5ef2aSThomas Huth } 6528fcf5ef2aSThomas Huth gen_set_label(l1); 6529fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 6530fcf5ef2aSThomas Huth } 6531fcf5ef2aSThomas Huth } else { 6532fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 6533fcf5ef2aSThomas Huth } 6534fcf5ef2aSThomas Huth tcg_temp_free(t0); 6535fcf5ef2aSThomas Huth tcg_temp_free(t1); 6536fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 6537fcf5ef2aSThomas Huth /* Update Rc0 */ 6538fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 6539fcf5ef2aSThomas Huth } 6540fcf5ef2aSThomas Huth } 6541fcf5ef2aSThomas Huth 6542fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6543fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 6544fcf5ef2aSThomas Huth { \ 6545fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 6546fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 6547fcf5ef2aSThomas Huth } 6548fcf5ef2aSThomas Huth 6549fcf5ef2aSThomas Huth /* macchw - macchw. */ 6550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 6551fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 6552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 6553fcf5ef2aSThomas Huth /* macchws - macchws. */ 6554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 6555fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 6556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 6557fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 6558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 6559fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 6560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 6561fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 6562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 6563fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 6564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 6565fcf5ef2aSThomas Huth /* machhw - machhw. */ 6566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 6567fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 6568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 6569fcf5ef2aSThomas Huth /* machhws - machhws. */ 6570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 6571fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 6572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 6573fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 6574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 6575fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 6576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 6577fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 6578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 6579fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 6580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 6581fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 6582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 6583fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 6584fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 6585fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 6586fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 6587fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 6588fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 6589fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 6590fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 6591fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 6592fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 6593fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 6594fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 6595fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 6596fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 6597fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 6598fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 6599fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 6600fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 6601fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 6602fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 6603fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 6604fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 6605fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 6606fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 6607fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 6608fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 6609fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 6610fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 6611fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 6612fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 6613fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 6614fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 6615fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 6616fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 6617fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 6618fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 6619fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 6620fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 6621fcf5ef2aSThomas Huth 6622fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 6623fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 6624fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 6625fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 6626fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 6627fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 6628fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 6629fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 6630fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 6631fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 6632fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 6633fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 6634fcf5ef2aSThomas Huth 6635fcf5ef2aSThomas Huth /* mfdcr */ 6636fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 6637fcf5ef2aSThomas Huth { 6638fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6639fcf5ef2aSThomas Huth GEN_PRIV; 6640fcf5ef2aSThomas Huth #else 6641fcf5ef2aSThomas Huth TCGv dcrn; 6642fcf5ef2aSThomas Huth 6643fcf5ef2aSThomas Huth CHK_SV; 6644fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6645fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 6646fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6647fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6648fcf5ef2aSThomas Huth } 6649fcf5ef2aSThomas Huth 6650fcf5ef2aSThomas Huth /* mtdcr */ 6651fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 6652fcf5ef2aSThomas Huth { 6653fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6654fcf5ef2aSThomas Huth GEN_PRIV; 6655fcf5ef2aSThomas Huth #else 6656fcf5ef2aSThomas Huth TCGv dcrn; 6657fcf5ef2aSThomas Huth 6658fcf5ef2aSThomas Huth CHK_SV; 6659fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 6660fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 6661fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 6662fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6663fcf5ef2aSThomas Huth } 6664fcf5ef2aSThomas Huth 6665fcf5ef2aSThomas Huth /* mfdcrx */ 6666fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6667fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 6668fcf5ef2aSThomas Huth { 6669fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6670fcf5ef2aSThomas Huth GEN_PRIV; 6671fcf5ef2aSThomas Huth #else 6672fcf5ef2aSThomas Huth CHK_SV; 6673fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6674fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6675fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6676fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6677fcf5ef2aSThomas Huth } 6678fcf5ef2aSThomas Huth 6679fcf5ef2aSThomas Huth /* mtdcrx */ 6680fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6681fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 6682fcf5ef2aSThomas Huth { 6683fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6684fcf5ef2aSThomas Huth GEN_PRIV; 6685fcf5ef2aSThomas Huth #else 6686fcf5ef2aSThomas Huth CHK_SV; 6687fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6688fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6689fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6690fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6691fcf5ef2aSThomas Huth } 6692fcf5ef2aSThomas Huth 6693fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 6694fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 6695fcf5ef2aSThomas Huth { 6696fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 6697fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6698fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6699fcf5ef2aSThomas Huth } 6700fcf5ef2aSThomas Huth 6701fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 6702fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 6703fcf5ef2aSThomas Huth { 6704fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 6705fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6706fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 6707fcf5ef2aSThomas Huth } 6708fcf5ef2aSThomas Huth 6709fcf5ef2aSThomas Huth /* dccci */ 6710fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 6711fcf5ef2aSThomas Huth { 6712fcf5ef2aSThomas Huth CHK_SV; 6713fcf5ef2aSThomas Huth /* interpreted as no-op */ 6714fcf5ef2aSThomas Huth } 6715fcf5ef2aSThomas Huth 6716fcf5ef2aSThomas Huth /* dcread */ 6717fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 6718fcf5ef2aSThomas Huth { 6719fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6720fcf5ef2aSThomas Huth GEN_PRIV; 6721fcf5ef2aSThomas Huth #else 6722fcf5ef2aSThomas Huth TCGv EA, val; 6723fcf5ef2aSThomas Huth 6724fcf5ef2aSThomas Huth CHK_SV; 6725fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 6726fcf5ef2aSThomas Huth EA = tcg_temp_new(); 6727fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 6728fcf5ef2aSThomas Huth val = tcg_temp_new(); 6729fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 6730fcf5ef2aSThomas Huth tcg_temp_free(val); 6731fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 6732fcf5ef2aSThomas Huth tcg_temp_free(EA); 6733fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6734fcf5ef2aSThomas Huth } 6735fcf5ef2aSThomas Huth 6736fcf5ef2aSThomas Huth /* icbt */ 6737fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6738fcf5ef2aSThomas Huth { 6739efe843d8SDavid Gibson /* 6740efe843d8SDavid Gibson * interpreted as no-op 6741efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6742efe843d8SDavid Gibson * does not generate any exception 6743fcf5ef2aSThomas Huth */ 6744fcf5ef2aSThomas Huth } 6745fcf5ef2aSThomas Huth 6746fcf5ef2aSThomas Huth /* iccci */ 6747fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6748fcf5ef2aSThomas Huth { 6749fcf5ef2aSThomas Huth CHK_SV; 6750fcf5ef2aSThomas Huth /* interpreted as no-op */ 6751fcf5ef2aSThomas Huth } 6752fcf5ef2aSThomas Huth 6753fcf5ef2aSThomas Huth /* icread */ 6754fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6755fcf5ef2aSThomas Huth { 6756fcf5ef2aSThomas Huth CHK_SV; 6757fcf5ef2aSThomas Huth /* interpreted as no-op */ 6758fcf5ef2aSThomas Huth } 6759fcf5ef2aSThomas Huth 6760fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6761fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6762fcf5ef2aSThomas Huth { 6763fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6764fcf5ef2aSThomas Huth GEN_PRIV; 6765fcf5ef2aSThomas Huth #else 6766fcf5ef2aSThomas Huth CHK_SV; 6767fcf5ef2aSThomas Huth /* Restore CPU state */ 6768fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 676959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6770fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6771fcf5ef2aSThomas Huth } 6772fcf5ef2aSThomas Huth 6773fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6774fcf5ef2aSThomas Huth { 6775fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6776fcf5ef2aSThomas Huth GEN_PRIV; 6777fcf5ef2aSThomas Huth #else 6778fcf5ef2aSThomas Huth CHK_SV; 6779fcf5ef2aSThomas Huth /* Restore CPU state */ 6780fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 678159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6782fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6783fcf5ef2aSThomas Huth } 6784fcf5ef2aSThomas Huth 6785fcf5ef2aSThomas Huth /* BookE specific */ 6786fcf5ef2aSThomas Huth 6787fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6788fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6789fcf5ef2aSThomas Huth { 6790fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6791fcf5ef2aSThomas Huth GEN_PRIV; 6792fcf5ef2aSThomas Huth #else 6793fcf5ef2aSThomas Huth CHK_SV; 6794fcf5ef2aSThomas Huth /* Restore CPU state */ 6795fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 679659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6797fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6798fcf5ef2aSThomas Huth } 6799fcf5ef2aSThomas Huth 6800fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6801fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6802fcf5ef2aSThomas Huth { 6803fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6804fcf5ef2aSThomas Huth GEN_PRIV; 6805fcf5ef2aSThomas Huth #else 6806fcf5ef2aSThomas Huth CHK_SV; 6807fcf5ef2aSThomas Huth /* Restore CPU state */ 6808fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 680959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 6810fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6811fcf5ef2aSThomas Huth } 6812fcf5ef2aSThomas Huth 6813fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6814fcf5ef2aSThomas Huth 6815fcf5ef2aSThomas Huth /* tlbre */ 6816fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6817fcf5ef2aSThomas Huth { 6818fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6819fcf5ef2aSThomas Huth GEN_PRIV; 6820fcf5ef2aSThomas Huth #else 6821fcf5ef2aSThomas Huth CHK_SV; 6822fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6823fcf5ef2aSThomas Huth case 0: 6824fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6825fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6826fcf5ef2aSThomas Huth break; 6827fcf5ef2aSThomas Huth case 1: 6828fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6829fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6830fcf5ef2aSThomas Huth break; 6831fcf5ef2aSThomas Huth default: 6832fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6833fcf5ef2aSThomas Huth break; 6834fcf5ef2aSThomas Huth } 6835fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6836fcf5ef2aSThomas Huth } 6837fcf5ef2aSThomas Huth 6838fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6839fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6840fcf5ef2aSThomas Huth { 6841fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6842fcf5ef2aSThomas Huth GEN_PRIV; 6843fcf5ef2aSThomas Huth #else 6844fcf5ef2aSThomas Huth TCGv t0; 6845fcf5ef2aSThomas Huth 6846fcf5ef2aSThomas Huth CHK_SV; 6847fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6848fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6849fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6850fcf5ef2aSThomas Huth tcg_temp_free(t0); 6851fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6852fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6853fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6854fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6855fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6856fcf5ef2aSThomas Huth gen_set_label(l1); 6857fcf5ef2aSThomas Huth } 6858fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6859fcf5ef2aSThomas Huth } 6860fcf5ef2aSThomas Huth 6861fcf5ef2aSThomas Huth /* tlbwe */ 6862fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6863fcf5ef2aSThomas Huth { 6864fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6865fcf5ef2aSThomas Huth GEN_PRIV; 6866fcf5ef2aSThomas Huth #else 6867fcf5ef2aSThomas Huth CHK_SV; 6868fcf5ef2aSThomas Huth 6869fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6870fcf5ef2aSThomas Huth case 0: 6871fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6872fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6873fcf5ef2aSThomas Huth break; 6874fcf5ef2aSThomas Huth case 1: 6875fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6876fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6877fcf5ef2aSThomas Huth break; 6878fcf5ef2aSThomas Huth default: 6879fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6880fcf5ef2aSThomas Huth break; 6881fcf5ef2aSThomas Huth } 6882fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6883fcf5ef2aSThomas Huth } 6884fcf5ef2aSThomas Huth 6885fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6886fcf5ef2aSThomas Huth 6887fcf5ef2aSThomas Huth /* tlbre */ 6888fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6889fcf5ef2aSThomas Huth { 6890fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6891fcf5ef2aSThomas Huth GEN_PRIV; 6892fcf5ef2aSThomas Huth #else 6893fcf5ef2aSThomas Huth CHK_SV; 6894fcf5ef2aSThomas Huth 6895fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6896fcf5ef2aSThomas Huth case 0: 6897fcf5ef2aSThomas Huth case 1: 6898fcf5ef2aSThomas Huth case 2: 6899fcf5ef2aSThomas Huth { 6900fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6901fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6902fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6903fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6904fcf5ef2aSThomas Huth } 6905fcf5ef2aSThomas Huth break; 6906fcf5ef2aSThomas Huth default: 6907fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6908fcf5ef2aSThomas Huth break; 6909fcf5ef2aSThomas Huth } 6910fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6911fcf5ef2aSThomas Huth } 6912fcf5ef2aSThomas Huth 6913fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6914fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6915fcf5ef2aSThomas Huth { 6916fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6917fcf5ef2aSThomas Huth GEN_PRIV; 6918fcf5ef2aSThomas Huth #else 6919fcf5ef2aSThomas Huth TCGv t0; 6920fcf5ef2aSThomas Huth 6921fcf5ef2aSThomas Huth CHK_SV; 6922fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6923fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6924fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6925fcf5ef2aSThomas Huth tcg_temp_free(t0); 6926fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6927fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6928fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6929fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6930fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6931fcf5ef2aSThomas Huth gen_set_label(l1); 6932fcf5ef2aSThomas Huth } 6933fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6934fcf5ef2aSThomas Huth } 6935fcf5ef2aSThomas Huth 6936fcf5ef2aSThomas Huth /* tlbwe */ 6937fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6938fcf5ef2aSThomas Huth { 6939fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6940fcf5ef2aSThomas Huth GEN_PRIV; 6941fcf5ef2aSThomas Huth #else 6942fcf5ef2aSThomas Huth CHK_SV; 6943fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6944fcf5ef2aSThomas Huth case 0: 6945fcf5ef2aSThomas Huth case 1: 6946fcf5ef2aSThomas Huth case 2: 6947fcf5ef2aSThomas Huth { 6948fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6949fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6950fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6951fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6952fcf5ef2aSThomas Huth } 6953fcf5ef2aSThomas Huth break; 6954fcf5ef2aSThomas Huth default: 6955fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6956fcf5ef2aSThomas Huth break; 6957fcf5ef2aSThomas Huth } 6958fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6959fcf5ef2aSThomas Huth } 6960fcf5ef2aSThomas Huth 6961fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6962fcf5ef2aSThomas Huth 6963fcf5ef2aSThomas Huth /* tlbre */ 6964fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6965fcf5ef2aSThomas Huth { 6966fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6967fcf5ef2aSThomas Huth GEN_PRIV; 6968fcf5ef2aSThomas Huth #else 6969fcf5ef2aSThomas Huth CHK_SV; 6970fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6971fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6972fcf5ef2aSThomas Huth } 6973fcf5ef2aSThomas Huth 6974fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6975fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6976fcf5ef2aSThomas Huth { 6977fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6978fcf5ef2aSThomas Huth GEN_PRIV; 6979fcf5ef2aSThomas Huth #else 6980fcf5ef2aSThomas Huth TCGv t0; 6981fcf5ef2aSThomas Huth 6982fcf5ef2aSThomas Huth CHK_SV; 6983fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6984fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6985fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6986fcf5ef2aSThomas Huth } else { 6987fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6988fcf5ef2aSThomas Huth } 6989fcf5ef2aSThomas Huth 6990fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6991fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6992fcf5ef2aSThomas Huth tcg_temp_free(t0); 6993fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6994fcf5ef2aSThomas Huth } 6995fcf5ef2aSThomas Huth 6996fcf5ef2aSThomas Huth /* tlbwe */ 6997fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6998fcf5ef2aSThomas Huth { 6999fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7000fcf5ef2aSThomas Huth GEN_PRIV; 7001fcf5ef2aSThomas Huth #else 7002fcf5ef2aSThomas Huth CHK_SV; 7003fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 7004fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7005fcf5ef2aSThomas Huth } 7006fcf5ef2aSThomas Huth 7007fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 7008fcf5ef2aSThomas Huth { 7009fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7010fcf5ef2aSThomas Huth GEN_PRIV; 7011fcf5ef2aSThomas Huth #else 7012fcf5ef2aSThomas Huth TCGv t0; 7013fcf5ef2aSThomas Huth 7014fcf5ef2aSThomas Huth CHK_SV; 7015fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7016fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7017fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 7018fcf5ef2aSThomas Huth tcg_temp_free(t0); 7019fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7020fcf5ef2aSThomas Huth } 7021fcf5ef2aSThomas Huth 7022fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 7023fcf5ef2aSThomas Huth { 7024fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7025fcf5ef2aSThomas Huth GEN_PRIV; 7026fcf5ef2aSThomas Huth #else 7027fcf5ef2aSThomas Huth TCGv t0; 7028fcf5ef2aSThomas Huth 7029fcf5ef2aSThomas Huth CHK_SV; 7030fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7031fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 7032fcf5ef2aSThomas Huth 7033fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 7034fcf5ef2aSThomas Huth case 0: 7035fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 7036fcf5ef2aSThomas Huth break; 7037fcf5ef2aSThomas Huth case 1: 7038fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 7039fcf5ef2aSThomas Huth break; 7040fcf5ef2aSThomas Huth case 3: 7041fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 7042fcf5ef2aSThomas Huth break; 7043fcf5ef2aSThomas Huth default: 7044fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7045fcf5ef2aSThomas Huth break; 7046fcf5ef2aSThomas Huth } 7047fcf5ef2aSThomas Huth 7048fcf5ef2aSThomas Huth tcg_temp_free(t0); 7049fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7050fcf5ef2aSThomas Huth } 7051fcf5ef2aSThomas Huth 7052fcf5ef2aSThomas Huth 7053fcf5ef2aSThomas Huth /* wrtee */ 7054fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 7055fcf5ef2aSThomas Huth { 7056fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7057fcf5ef2aSThomas Huth GEN_PRIV; 7058fcf5ef2aSThomas Huth #else 7059fcf5ef2aSThomas Huth TCGv t0; 7060fcf5ef2aSThomas Huth 7061fcf5ef2aSThomas Huth CHK_SV; 7062fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 7063fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 7064fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7065fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 7066fcf5ef2aSThomas Huth tcg_temp_free(t0); 7067efe843d8SDavid Gibson /* 7068efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 7069efe843d8SDavid Gibson * just set msr_ee to 1 7070fcf5ef2aSThomas Huth */ 7071d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7072fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7073fcf5ef2aSThomas Huth } 7074fcf5ef2aSThomas Huth 7075fcf5ef2aSThomas Huth /* wrteei */ 7076fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 7077fcf5ef2aSThomas Huth { 7078fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7079fcf5ef2aSThomas Huth GEN_PRIV; 7080fcf5ef2aSThomas Huth #else 7081fcf5ef2aSThomas Huth CHK_SV; 7082fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 7083fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 7084fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 7085d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 7086fcf5ef2aSThomas Huth } else { 7087fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 7088fcf5ef2aSThomas Huth } 7089fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7090fcf5ef2aSThomas Huth } 7091fcf5ef2aSThomas Huth 7092fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 7093fcf5ef2aSThomas Huth 7094fcf5ef2aSThomas Huth /* dlmzb */ 7095fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 7096fcf5ef2aSThomas Huth { 7097fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 7098fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 7099fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 7100fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 7101fcf5ef2aSThomas Huth } 7102fcf5ef2aSThomas Huth 7103fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 7104fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 7105fcf5ef2aSThomas Huth { 7106fcf5ef2aSThomas Huth /* interpreted as no-op */ 7107fcf5ef2aSThomas Huth } 7108fcf5ef2aSThomas Huth 7109fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 7110fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 7111fcf5ef2aSThomas Huth { 711227a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 711327a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 711427a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 711527a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 711627a3ea7eSBALATON Zoltan } 711727a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 7118fcf5ef2aSThomas Huth } 7119fcf5ef2aSThomas Huth 7120fcf5ef2aSThomas Huth /* icbt */ 7121fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 7122fcf5ef2aSThomas Huth { 7123efe843d8SDavid Gibson /* 7124efe843d8SDavid Gibson * interpreted as no-op 7125efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 7126efe843d8SDavid Gibson * does not generate any exception 7127fcf5ef2aSThomas Huth */ 7128fcf5ef2aSThomas Huth } 7129fcf5ef2aSThomas Huth 7130fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 7131fcf5ef2aSThomas Huth 7132fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 7133fcf5ef2aSThomas Huth { 7134fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7135fcf5ef2aSThomas Huth GEN_PRIV; 7136fcf5ef2aSThomas Huth #else 7137ebca5e6dSCédric Le Goater CHK_HV; 7138d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 71397af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71407af1e7b0SCédric Le Goater } else { 7141fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71427af1e7b0SCédric Le Goater } 7143fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7144fcf5ef2aSThomas Huth } 7145fcf5ef2aSThomas Huth 7146fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 7147fcf5ef2aSThomas Huth { 7148fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7149fcf5ef2aSThomas Huth GEN_PRIV; 7150fcf5ef2aSThomas Huth #else 7151ebca5e6dSCédric Le Goater CHK_HV; 7152d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 71537af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 71547af1e7b0SCédric Le Goater } else { 7155fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 71567af1e7b0SCédric Le Goater } 7157fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 7158fcf5ef2aSThomas Huth } 7159fcf5ef2aSThomas Huth 71605ba7ba1dSCédric Le Goater #if defined(TARGET_PPC64) 71615ba7ba1dSCédric Le Goater static void gen_msgclrp(DisasContext *ctx) 71625ba7ba1dSCédric Le Goater { 71635ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 71645ba7ba1dSCédric Le Goater GEN_PRIV; 71655ba7ba1dSCédric Le Goater #else 71665ba7ba1dSCédric Le Goater CHK_SV; 71675ba7ba1dSCédric Le Goater gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71685ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 71695ba7ba1dSCédric Le Goater } 71705ba7ba1dSCédric Le Goater 71715ba7ba1dSCédric Le Goater static void gen_msgsndp(DisasContext *ctx) 71725ba7ba1dSCédric Le Goater { 71735ba7ba1dSCédric Le Goater #if defined(CONFIG_USER_ONLY) 71745ba7ba1dSCédric Le Goater GEN_PRIV; 71755ba7ba1dSCédric Le Goater #else 71765ba7ba1dSCédric Le Goater CHK_SV; 71775ba7ba1dSCédric Le Goater gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]); 71785ba7ba1dSCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 71795ba7ba1dSCédric Le Goater } 71805ba7ba1dSCédric Le Goater #endif 71815ba7ba1dSCédric Le Goater 71827af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 71837af1e7b0SCédric Le Goater { 71847af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 71857af1e7b0SCédric Le Goater GEN_PRIV; 71867af1e7b0SCédric Le Goater #else 71877af1e7b0SCédric Le Goater CHK_HV; 71887af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 71897af1e7b0SCédric Le Goater /* interpreted as no-op */ 71907af1e7b0SCédric Le Goater } 7191fcf5ef2aSThomas Huth 7192fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7193fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 7194fcf5ef2aSThomas Huth { 7195fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7196fcf5ef2aSThomas Huth 7197fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 7198fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 7199fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7200fcf5ef2aSThomas Huth } 7201fcf5ef2aSThomas Huth 7202fcf5ef2aSThomas Huth /* maddhd maddhdu */ 7203fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 7204fcf5ef2aSThomas Huth { 7205fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 7206fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 7207fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 7208fcf5ef2aSThomas Huth 7209fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 7210fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7211fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7212fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 7213fcf5ef2aSThomas Huth } else { 7214fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 7215fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 7216fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 7217fcf5ef2aSThomas Huth } 7218fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 7219fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 7220fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 7221fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 7222fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 7223fcf5ef2aSThomas Huth } 7224fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 7225fcf5ef2aSThomas Huth 7226fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 7227fcf5ef2aSThomas Huth { 7228fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7229fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7230fcf5ef2aSThomas Huth return; 7231fcf5ef2aSThomas Huth } 7232fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 7233fcf5ef2aSThomas Huth } 7234fcf5ef2aSThomas Huth 7235fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 7236fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7237fcf5ef2aSThomas Huth { \ 7238fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7239fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7240fcf5ef2aSThomas Huth return; \ 7241fcf5ef2aSThomas Huth } \ 7242efe843d8SDavid Gibson /* \ 7243efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 7244fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 7245fcf5ef2aSThomas Huth * \ 7246fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7247fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 7248fcf5ef2aSThomas Huth */ \ 7249fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7250fcf5ef2aSThomas Huth } 7251fcf5ef2aSThomas Huth 7252fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 7253fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 7254fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 7255fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 7256fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 7257fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 7258fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 7259efe843d8SDavid Gibson 7260b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 7261b8b4576eSSuraj Jitindar Singh { 7262efe843d8SDavid Gibson /* Do Nothing */ 7263b8b4576eSSuraj Jitindar Singh } 7264fcf5ef2aSThomas Huth 726580b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 726680b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 726780b8c1eeSNikunj A Dadhania { \ 7268efe843d8SDavid Gibson /* \ 7269efe843d8SDavid Gibson * Generate invalid exception until we have an \ 7270efe843d8SDavid Gibson * implementation of the copy paste facility \ 727180b8c1eeSNikunj A Dadhania */ \ 727280b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 727380b8c1eeSNikunj A Dadhania } 727480b8c1eeSNikunj A Dadhania 727580b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 727680b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 727780b8c1eeSNikunj A Dadhania 7278fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 7279fcf5ef2aSThomas Huth { 7280fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 7281fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 7282fcf5ef2aSThomas Huth return; 7283fcf5ef2aSThomas Huth } 7284efe843d8SDavid Gibson /* 7285efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 7286efe843d8SDavid Gibson * simple: 7287fcf5ef2aSThomas Huth * 7288fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 7289fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 7290fcf5ef2aSThomas Huth */ 7291fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 7292fcf5ef2aSThomas Huth } 7293fcf5ef2aSThomas Huth 7294fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 7295fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7296fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7297fcf5ef2aSThomas Huth { \ 7298fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 7299fcf5ef2aSThomas Huth } 7300fcf5ef2aSThomas Huth 7301fcf5ef2aSThomas Huth #else 7302fcf5ef2aSThomas Huth 7303fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 7304fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 7305fcf5ef2aSThomas Huth { \ 7306fcf5ef2aSThomas Huth CHK_SV; \ 7307fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 7308fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 7309fcf5ef2aSThomas Huth return; \ 7310fcf5ef2aSThomas Huth } \ 7311efe843d8SDavid Gibson /* \ 7312efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 7313fcf5ef2aSThomas Huth * simple: \ 7314fcf5ef2aSThomas Huth * \ 7315fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 7316fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 7317fcf5ef2aSThomas Huth */ \ 7318fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 7319fcf5ef2aSThomas Huth } 7320fcf5ef2aSThomas Huth 7321fcf5ef2aSThomas Huth #endif 7322fcf5ef2aSThomas Huth 7323fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 7324fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 7325fcf5ef2aSThomas Huth 73261a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 73271a404c91SMark Cave-Ayland { 7328e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 73291a404c91SMark Cave-Ayland } 73301a404c91SMark Cave-Ayland 73311a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 73321a404c91SMark Cave-Ayland { 7333e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 73341a404c91SMark Cave-Ayland } 73351a404c91SMark Cave-Ayland 7336c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 7337c4a18dbfSMark Cave-Ayland { 733837da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 7339c4a18dbfSMark Cave-Ayland } 7340c4a18dbfSMark Cave-Ayland 7341c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 7342c4a18dbfSMark Cave-Ayland { 734337da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 7344c4a18dbfSMark Cave-Ayland } 7345c4a18dbfSMark Cave-Ayland 7346c9826ae9SRichard Henderson /* 7347f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 7348f2aabda8SRichard Henderson */ 7349d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 7350d39b2cc7SLuis Pires { 7351d39b2cc7SLuis Pires return x * 2; 7352d39b2cc7SLuis Pires } 7353d39b2cc7SLuis Pires 7354f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 7355f2aabda8SRichard Henderson { 7356f2aabda8SRichard Henderson return x * 4; 7357f2aabda8SRichard Henderson } 7358f2aabda8SRichard Henderson 7359e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 7360e10271e1SMatheus Ferst { 7361e10271e1SMatheus Ferst return x * 16; 7362e10271e1SMatheus Ferst } 7363e10271e1SMatheus Ferst 7364f2aabda8SRichard Henderson /* 7365c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 7366c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 7367c9826ae9SRichard Henderson * proper variable. 7368c9826ae9SRichard Henderson */ 7369c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 7370c9826ae9SRichard Henderson do { \ 7371c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 7372c9826ae9SRichard Henderson return false; \ 7373c9826ae9SRichard Henderson } \ 7374c9826ae9SRichard Henderson } while (0) 7375c9826ae9SRichard Henderson 7376c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 7377c9826ae9SRichard Henderson do { \ 7378c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 7379c9826ae9SRichard Henderson return false; \ 7380c9826ae9SRichard Henderson } \ 7381c9826ae9SRichard Henderson } while (0) 7382c9826ae9SRichard Henderson 7383c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 7384c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 7385c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 7386c9826ae9SRichard Henderson #else 7387c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 7388c9826ae9SRichard Henderson #endif 7389c9826ae9SRichard Henderson 7390e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 7391e2205a46SBruno Larsen do { \ 7392e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 7393e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 7394e2205a46SBruno Larsen return true; \ 7395e2205a46SBruno Larsen } \ 7396e2205a46SBruno Larsen } while (0) 7397e2205a46SBruno Larsen 73988226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 73998226cb2dSBruno Larsen (billionai) do { \ 74008226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 74018226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 74028226cb2dSBruno Larsen (billionai) return true; \ 74038226cb2dSBruno Larsen (billionai) } \ 74048226cb2dSBruno Larsen (billionai) } while (0) 74058226cb2dSBruno Larsen (billionai) 740686057426SFernando Valle #define REQUIRE_FPU(ctx) \ 740786057426SFernando Valle do { \ 740886057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 740986057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 741086057426SFernando Valle return true; \ 741186057426SFernando Valle } \ 741286057426SFernando Valle } while (0) 741386057426SFernando Valle 7414f2aabda8SRichard Henderson /* 7415f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 7416f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 7417f2aabda8SRichard Henderson */ 7418f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 7419f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7420f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 7421f2aabda8SRichard Henderson 7422f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 7423f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 7424f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 7425f2aabda8SRichard Henderson 7426f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 7427f2aabda8SRichard Henderson 7428f2aabda8SRichard Henderson 742999082815SRichard Henderson #include "decode-insn32.c.inc" 743099082815SRichard Henderson #include "decode-insn64.c.inc" 7431565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 7432565cb109SGustavo Romero 7433725b2d4dSFernando Eckhardt Valle /* 7434725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 7435725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 7436725b2d4dSFernando Eckhardt Valle */ 7437725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 7438725b2d4dSFernando Eckhardt Valle { 7439725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 7440725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 7441725b2d4dSFernando Eckhardt Valle d->si = a->si; 7442725b2d4dSFernando Eckhardt Valle if (a->r) { 7443725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 7444725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 7445725b2d4dSFernando Eckhardt Valle return false; 7446725b2d4dSFernando Eckhardt Valle } 7447725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 7448725b2d4dSFernando Eckhardt Valle } 7449725b2d4dSFernando Eckhardt Valle return true; 7450725b2d4dSFernando Eckhardt Valle } 7451725b2d4dSFernando Eckhardt Valle 745299082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 745399082815SRichard Henderson 7454139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 7455fcf5ef2aSThomas Huth 7456139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 7457fcf5ef2aSThomas Huth 7458139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 7459fcf5ef2aSThomas Huth 7460139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 7461fcf5ef2aSThomas Huth 7462139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 7463fcf5ef2aSThomas Huth 7464*1f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 7465*1f26c751SDaniel Henrique Barboza 74665cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 74675cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 74685cb091a4SNikunj A Dadhania { 74695cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 74705cb091a4SNikunj A Dadhania case 0: /* lfdp */ 74715cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 74725cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 74735cb091a4SNikunj A Dadhania } 74745cb091a4SNikunj A Dadhania break; 74755cb091a4SNikunj A Dadhania case 2: /* lxsd */ 74765cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 74775cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 74785cb091a4SNikunj A Dadhania } 74795cb091a4SNikunj A Dadhania break; 74805cb091a4SNikunj A Dadhania case 3: /* lxssp */ 74815cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 74825cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 74835cb091a4SNikunj A Dadhania } 74845cb091a4SNikunj A Dadhania break; 74855cb091a4SNikunj A Dadhania } 74865cb091a4SNikunj A Dadhania return gen_invalid(ctx); 74875cb091a4SNikunj A Dadhania } 74885cb091a4SNikunj A Dadhania 7489d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 7490e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 7491e3001664SNikunj A Dadhania { 749272b70d5cSLucas Mateus Castro (alqotel) if ((ctx->opcode & 3) != 1) { /* DS-FORM */ 7493e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 7494e3001664SNikunj A Dadhania case 0: /* stfdp */ 7495e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 7496e3001664SNikunj A Dadhania return gen_stfdp(ctx); 7497e3001664SNikunj A Dadhania } 7498e3001664SNikunj A Dadhania break; 7499e3001664SNikunj A Dadhania case 2: /* stxsd */ 7500e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7501e3001664SNikunj A Dadhania return gen_stxsd(ctx); 7502e3001664SNikunj A Dadhania } 7503e3001664SNikunj A Dadhania break; 7504e3001664SNikunj A Dadhania case 3: /* stxssp */ 7505e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 7506e3001664SNikunj A Dadhania return gen_stxssp(ctx); 7507e3001664SNikunj A Dadhania } 7508e3001664SNikunj A Dadhania break; 7509e3001664SNikunj A Dadhania } 7510e3001664SNikunj A Dadhania } 7511e3001664SNikunj A Dadhania return gen_invalid(ctx); 7512e3001664SNikunj A Dadhania } 7513e3001664SNikunj A Dadhania 75149d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75159d69cfa2SLijun Pan /* brd */ 75169d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 75179d69cfa2SLijun Pan { 75189d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75199d69cfa2SLijun Pan } 75209d69cfa2SLijun Pan 75219d69cfa2SLijun Pan /* brw */ 75229d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 75239d69cfa2SLijun Pan { 75249d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 75259d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 75269d69cfa2SLijun Pan 75279d69cfa2SLijun Pan } 75289d69cfa2SLijun Pan 75299d69cfa2SLijun Pan /* brh */ 75309d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 75319d69cfa2SLijun Pan { 7532491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 75339d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 75349d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 75359d69cfa2SLijun Pan 75369d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 7537491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 7538491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 75399d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 75409d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 75419d69cfa2SLijun Pan 75429d69cfa2SLijun Pan tcg_temp_free_i64(t1); 75439d69cfa2SLijun Pan tcg_temp_free_i64(t2); 75449d69cfa2SLijun Pan } 75459d69cfa2SLijun Pan #endif 75469d69cfa2SLijun Pan 7547fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 75489d69cfa2SLijun Pan #if defined(TARGET_PPC64) 75499d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 75509d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 75519d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 75529d69cfa2SLijun Pan #endif 7553fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 7554fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7555fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 7556fcf5ef2aSThomas Huth #endif 7557fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 7558fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 7559fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 7560fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7561fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7562fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 7563fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 7564fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 7565fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 7566fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7567fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7568fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 7569fcf5ef2aSThomas Huth #endif 7570fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 7571fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 7572fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7573fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7574fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7575fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 7576fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 757780b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 7578b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 757980b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 7580fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 7581fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 7582fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7583fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7584fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7585fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7586fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 7587fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 7588fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 7589fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7590fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 7591fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 7592fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 7593fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 7594fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 7595fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 7596fcf5ef2aSThomas Huth #endif 7597fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7598fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7599fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7600fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 7601fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 7602fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 7603fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 7604fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7605fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 7606fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 7607fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 7608fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 7609fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 7610fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 7611fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7612fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 7613fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 7614fcf5ef2aSThomas Huth #endif 76155cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 76165cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 761772b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 7618e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 7619fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7620fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 7621fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 7622fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 7623fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 7624fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 7625c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 7626fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 7627fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7628fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7629fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 7630a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 7631a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 7632fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7633fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 7634fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 7635fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7636a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 7637a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 7638fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 7639fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 7640fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 7641fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 7642fcf5ef2aSThomas Huth #endif 7643fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 7644fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 7645c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 7646fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7647fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7648fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 7649fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 7650fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 7651fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 7652fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 7653fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7654fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 76553c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 76563c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 76573c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 76583c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 76593c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 76603c89b8d6SNicholas Piggin #endif 7661cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7662fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7663fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7664fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7665fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 7666fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 7667fcf5ef2aSThomas Huth #endif 76683c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 76693c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 76703c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 7671fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 7672fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 7673fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7674fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 7675fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 7676fcf5ef2aSThomas Huth #endif 7677fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 7678fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 7679fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 7680fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 7681fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 7682fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 7683fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7684fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 7685fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 7686b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 7687fcf5ef2aSThomas Huth #endif 7688fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 7689fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 7690fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 769150728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7692fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 7693fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 769450728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7695fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 769650728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7697fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 769850728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 7699fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 7700fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 770150728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 7702fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 770399d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 7704fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 7705fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 770650728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 7707fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 7708fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 7709fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 7710fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 7711fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 7712fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7713fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 7714fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 7715fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7716fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 7717fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 7718fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 7719fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 7720fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 7721fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 7722fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 7723fcf5ef2aSThomas Huth #endif 7724fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 7725efe843d8SDavid Gibson /* 7726efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 7727efe843d8SDavid Gibson * different ISA versions 7728efe843d8SDavid Gibson */ 7729fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 7730fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 7731c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 7732c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 7733fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 7734fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7735fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 7736fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 7737a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 773862d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 7739fcf5ef2aSThomas Huth #endif 7740fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 7741fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 7742fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 7743fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 7744fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 7745fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 7746fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 7747fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 7748fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 7749fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 7750fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 7751fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7752fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 7753fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 7754fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 7755fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 7756fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 7757fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 7758fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 7759fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 7760fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 7761fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 7762fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 7763fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 7764fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 7765fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 7766fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 7767fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 7768fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 7769fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 7770fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 7771fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 7772fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 7773fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 7774fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 7775fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 7776fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 7777fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 7778fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 7779fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 7780fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 7781fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 7782fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 7783fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 7784fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 7785fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 7786fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 7787fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7788fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7789fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 7790fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 7791fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7792fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 7793fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 7794fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 7795fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 7796fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 7797fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 7798fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 7799fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 7800fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 7801fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 7802fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 7803fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 7804fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 7805fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 7806fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 7807fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 7808fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 7809fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 7810fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 7811fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 7812fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 7813fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 7814fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 7815fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 7816fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 7817fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 7818fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 7819fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7820fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 7821fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7822fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 7823fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7824fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 7825fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7826fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 7827fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 7828fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 7829fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 7830fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 7831fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 78327af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 78337af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 7834fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 7835fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 7836fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 7837fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 7838fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 783927a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 7840fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 7841fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 78420c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 78430c8d8c8bSBALATON Zoltan PPC_440_SPEC), 7844fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 7845fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 7846fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 7847fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 7848fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 7849fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7850fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 7851fcf5ef2aSThomas Huth PPC2_ISA300), 7852fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 78535ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001, 78545ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 78555ba7ba1dSCédric Le Goater GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001, 78565ba7ba1dSCédric Le Goater PPC_NONE, PPC2_ISA207S), 7857fcf5ef2aSThomas Huth #endif 7858fcf5ef2aSThomas Huth 7859fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 7860fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 7861fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 7862fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 7863fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 7864fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7865fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 7866fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 7867fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 7868fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 7869fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 7870fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 7871fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 7872fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 7873fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 78744c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 7875fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 7876fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 7877fcf5ef2aSThomas Huth 7878fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 7879fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 7880fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 7881fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 7882fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 7883fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 7884fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 7885fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7886fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7887fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7888fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7889fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7890fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7891fcf5ef2aSThomas Huth 7892fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7893fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 7894fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 7895fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7896fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 7897fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 7898fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 7899fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 7900fcf5ef2aSThomas Huth 7901fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7902fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 7903fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7904fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 7905fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 7906fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 7907fcf5ef2aSThomas Huth 7908fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 7909fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 7910fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 7911fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 7912fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 7913fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 7914fcf5ef2aSThomas Huth #endif 7915fcf5ef2aSThomas Huth 7916fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 7917fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 7918fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 7919fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 7920fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 7921fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 7922fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 7923fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 7924fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 7925fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 7926fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 7927fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7928fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7929fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7930fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7931fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7932fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7933fcf5ef2aSThomas Huth 7934fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7935fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7936fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7937fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7938fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7939fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7940fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7941fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7942fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7943fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7944fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7945fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7946fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7947fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7948fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7949fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7950fcf5ef2aSThomas Huth #endif 7951fcf5ef2aSThomas Huth 7952fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7953fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7954fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7955fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7956fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7957fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7958fcf5ef2aSThomas Huth PPC_64B) 7959fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7960fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7961fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7962fcf5ef2aSThomas Huth PPC_64B), \ 7963fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7964fcf5ef2aSThomas Huth PPC_64B), \ 7965fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7966fcf5ef2aSThomas Huth PPC_64B) 7967fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7968fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7969fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7970fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7971fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7972fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7973fcf5ef2aSThomas Huth #endif 7974fcf5ef2aSThomas Huth 7975fcf5ef2aSThomas Huth #undef GEN_LDX_E 7976fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7977fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7978fcf5ef2aSThomas Huth 7979fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7980fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7981fcf5ef2aSThomas Huth 7982fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7983fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7984fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7985fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7986fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7987fcf5ef2aSThomas Huth #endif 7988fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7989fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7990fcf5ef2aSThomas Huth 799150728199SRoman Kapl /* External PID based load */ 799250728199SRoman Kapl #undef GEN_LDEPX 799350728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 799450728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 799550728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 799650728199SRoman Kapl 799750728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 799850728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 799950728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 800050728199SRoman Kapl #if defined(TARGET_PPC64) 800150728199SRoman Kapl GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) 800250728199SRoman Kapl #endif 800350728199SRoman Kapl 8004fcf5ef2aSThomas Huth #undef GEN_STX_E 8005fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 80060123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 8007fcf5ef2aSThomas Huth 8008fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 8009fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 8010fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 8011fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 8012fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 8013fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 8014fcf5ef2aSThomas Huth #endif 8015fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 8016fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 8017fcf5ef2aSThomas Huth 801850728199SRoman Kapl #undef GEN_STEPX 801950728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 802050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 802150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 802250728199SRoman Kapl 802350728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 802450728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 802550728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 802650728199SRoman Kapl #if defined(TARGET_PPC64) 802750728199SRoman Kapl GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) 802850728199SRoman Kapl #endif 802950728199SRoman Kapl 8030fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 8031fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 8032fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 8033fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 8034fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 8035fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 8036fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 8037fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 8038fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 8039fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 8040fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 8041fcf5ef2aSThomas Huth 8042fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 8043fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 8044fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 8045fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 8046fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 8047fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 8048fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 8049fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 8050fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 8051fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 8052fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 8053fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 8054fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 8055fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 8056fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 8057fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 8058fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 8059fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 8060fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 8061fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 8062fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 8063fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 8064fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 8065fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 8066fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 8067fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 8068fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 8069fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 8070fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 8071fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 8072fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 8073fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 8074fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 8075fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 8076fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 8077fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 8078fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 8079fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 8080fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 8081fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 8082fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 8083fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 8084fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 8085fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 8086fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 8087fcf5ef2aSThomas Huth 8088fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 8089fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8090fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 8091fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8092fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 8093fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8094fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 8095fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8096fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 8097fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8098fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 8099fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8100fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 8101fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8102fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 8103fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8104fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 8105fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8106fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 8107fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8108fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 8109fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 8110fcf5ef2aSThomas Huth 8111139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 8112fcf5ef2aSThomas Huth 8113139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 8114fcf5ef2aSThomas Huth 8115139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 8116fcf5ef2aSThomas Huth 8117139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 8118fcf5ef2aSThomas Huth }; 8119fcf5ef2aSThomas Huth 81207468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 81217468e2c8SBruno Larsen (billionai) /* Opcode types */ 81227468e2c8SBruno Larsen (billionai) enum { 81237468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 81247468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 81257468e2c8SBruno Larsen (billionai) }; 81267468e2c8SBruno Larsen (billionai) 81277468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 81287468e2c8SBruno Larsen (billionai) 81297468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 81307468e2c8SBruno Larsen (billionai) { 81317468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 81327468e2c8SBruno Larsen (billionai) } 81337468e2c8SBruno Larsen (billionai) 81347468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 81357468e2c8SBruno Larsen (billionai) { 81367468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 81377468e2c8SBruno Larsen (billionai) } 81387468e2c8SBruno Larsen (billionai) 81397468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 81407468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 81417468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 81427468e2c8SBruno Larsen (billionai) { 81437468e2c8SBruno Larsen (billionai) int i; 81447468e2c8SBruno Larsen (billionai) 81457468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 81467468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 81477468e2c8SBruno Larsen (billionai) } 81487468e2c8SBruno Larsen (billionai) } 81497468e2c8SBruno Larsen (billionai) 81507468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 81517468e2c8SBruno Larsen (billionai) { 81527468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 81537468e2c8SBruno Larsen (billionai) 81547468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 81557468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 81567468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 81577468e2c8SBruno Larsen (billionai) 81587468e2c8SBruno Larsen (billionai) return 0; 81597468e2c8SBruno Larsen (billionai) } 81607468e2c8SBruno Larsen (billionai) 81617468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 81627468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 81637468e2c8SBruno Larsen (billionai) { 81647468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 81657468e2c8SBruno Larsen (billionai) return -1; 81667468e2c8SBruno Larsen (billionai) } 81677468e2c8SBruno Larsen (billionai) table[idx] = handler; 81687468e2c8SBruno Larsen (billionai) 81697468e2c8SBruno Larsen (billionai) return 0; 81707468e2c8SBruno Larsen (billionai) } 81717468e2c8SBruno Larsen (billionai) 81727468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 81737468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 81747468e2c8SBruno Larsen (billionai) { 81757468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 81767468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 81777468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 81787468e2c8SBruno Larsen (billionai) return -1; 81797468e2c8SBruno Larsen (billionai) } 81807468e2c8SBruno Larsen (billionai) 81817468e2c8SBruno Larsen (billionai) return 0; 81827468e2c8SBruno Larsen (billionai) } 81837468e2c8SBruno Larsen (billionai) 81847468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 81857468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 81867468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 81877468e2c8SBruno Larsen (billionai) { 81887468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 81897468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 81907468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 81917468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 81927468e2c8SBruno Larsen (billionai) return -1; 81937468e2c8SBruno Larsen (billionai) } 81947468e2c8SBruno Larsen (billionai) } else { 81957468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 81967468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 81977468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 81987468e2c8SBruno Larsen (billionai) return -1; 81997468e2c8SBruno Larsen (billionai) } 82007468e2c8SBruno Larsen (billionai) } 82017468e2c8SBruno Larsen (billionai) if (handler != NULL && 82027468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 82037468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 82047468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 82057468e2c8SBruno Larsen (billionai) return -1; 82067468e2c8SBruno Larsen (billionai) } 82077468e2c8SBruno Larsen (billionai) 82087468e2c8SBruno Larsen (billionai) return 0; 82097468e2c8SBruno Larsen (billionai) } 82107468e2c8SBruno Larsen (billionai) 82117468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 82127468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82137468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82147468e2c8SBruno Larsen (billionai) { 82157468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 82167468e2c8SBruno Larsen (billionai) } 82177468e2c8SBruno Larsen (billionai) 82187468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 82197468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82207468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 82217468e2c8SBruno Larsen (billionai) { 82227468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82237468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82247468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82257468e2c8SBruno Larsen (billionai) return -1; 82267468e2c8SBruno Larsen (billionai) } 82277468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 82287468e2c8SBruno Larsen (billionai) handler) < 0) { 82297468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 82307468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 82317468e2c8SBruno Larsen (billionai) return -1; 82327468e2c8SBruno Larsen (billionai) } 82337468e2c8SBruno Larsen (billionai) 82347468e2c8SBruno Larsen (billionai) return 0; 82357468e2c8SBruno Larsen (billionai) } 82367468e2c8SBruno Larsen (billionai) 82377468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 82387468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 82397468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 82407468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 82417468e2c8SBruno Larsen (billionai) { 82427468e2c8SBruno Larsen (billionai) opc_handler_t **table; 82437468e2c8SBruno Larsen (billionai) 82447468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 82457468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 82467468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 82477468e2c8SBruno Larsen (billionai) return -1; 82487468e2c8SBruno Larsen (billionai) } 82497468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 82507468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 82517468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 82527468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 82537468e2c8SBruno Larsen (billionai) return -1; 82547468e2c8SBruno Larsen (billionai) } 82557468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 82567468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 82577468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 82587468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 82597468e2c8SBruno Larsen (billionai) return -1; 82607468e2c8SBruno Larsen (billionai) } 82617468e2c8SBruno Larsen (billionai) return 0; 82627468e2c8SBruno Larsen (billionai) } 82637468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 82647468e2c8SBruno Larsen (billionai) { 82657468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 82667468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 82677468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 82687468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 82697468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 82707468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 82717468e2c8SBruno Larsen (billionai) return -1; 82727468e2c8SBruno Larsen (billionai) } 82737468e2c8SBruno Larsen (billionai) } else { 82747468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 82757468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 82767468e2c8SBruno Larsen (billionai) return -1; 82777468e2c8SBruno Larsen (billionai) } 82787468e2c8SBruno Larsen (billionai) } 82797468e2c8SBruno Larsen (billionai) } else { 82807468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 82817468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 82827468e2c8SBruno Larsen (billionai) return -1; 82837468e2c8SBruno Larsen (billionai) } 82847468e2c8SBruno Larsen (billionai) } 82857468e2c8SBruno Larsen (billionai) } else { 82867468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 82877468e2c8SBruno Larsen (billionai) return -1; 82887468e2c8SBruno Larsen (billionai) } 82897468e2c8SBruno Larsen (billionai) } 82907468e2c8SBruno Larsen (billionai) 82917468e2c8SBruno Larsen (billionai) return 0; 82927468e2c8SBruno Larsen (billionai) } 82937468e2c8SBruno Larsen (billionai) 82947468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 82957468e2c8SBruno Larsen (billionai) { 82967468e2c8SBruno Larsen (billionai) int i, count, tmp; 82977468e2c8SBruno Larsen (billionai) 82987468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 82997468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 83007468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 83017468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83027468e2c8SBruno Larsen (billionai) } 83037468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 83047468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 83057468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 83067468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 83077468e2c8SBruno Larsen (billionai) if (tmp == 0) { 83087468e2c8SBruno Larsen (billionai) free(table[i]); 83097468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 83107468e2c8SBruno Larsen (billionai) } else { 83117468e2c8SBruno Larsen (billionai) count++; 83127468e2c8SBruno Larsen (billionai) } 83137468e2c8SBruno Larsen (billionai) } else { 83147468e2c8SBruno Larsen (billionai) count++; 83157468e2c8SBruno Larsen (billionai) } 83167468e2c8SBruno Larsen (billionai) } 83177468e2c8SBruno Larsen (billionai) } 83187468e2c8SBruno Larsen (billionai) 83197468e2c8SBruno Larsen (billionai) return count; 83207468e2c8SBruno Larsen (billionai) } 83217468e2c8SBruno Larsen (billionai) 83227468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 83237468e2c8SBruno Larsen (billionai) { 83247468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 83257468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 83267468e2c8SBruno Larsen (billionai) } 83277468e2c8SBruno Larsen (billionai) } 83287468e2c8SBruno Larsen (billionai) 83297468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 83307468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 83317468e2c8SBruno Larsen (billionai) { 83327468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 83337468e2c8SBruno Larsen (billionai) opcode_t *opc; 83347468e2c8SBruno Larsen (billionai) 83357468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 83367468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 83377468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 83387468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 83397468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 83407468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 83417468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 83427468e2c8SBruno Larsen (billionai) opc->opc3); 83437468e2c8SBruno Larsen (billionai) return; 83447468e2c8SBruno Larsen (billionai) } 83457468e2c8SBruno Larsen (billionai) } 83467468e2c8SBruno Larsen (billionai) } 83477468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 83487468e2c8SBruno Larsen (billionai) fflush(stdout); 83497468e2c8SBruno Larsen (billionai) fflush(stderr); 83507468e2c8SBruno Larsen (billionai) } 83517468e2c8SBruno Larsen (billionai) 83527468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 83537468e2c8SBruno Larsen (billionai) { 83547468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 83557468e2c8SBruno Larsen (billionai) int i, j, k; 83567468e2c8SBruno Larsen (billionai) 83577468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 83587468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 83597468e2c8SBruno Larsen (billionai) continue; 83607468e2c8SBruno Larsen (billionai) } 83617468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 83627468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 83637468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 83647468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 83657468e2c8SBruno Larsen (billionai) continue; 83667468e2c8SBruno Larsen (billionai) } 83677468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 83687468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 83697468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 83707468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 83717468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 83727468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 83737468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 83747468e2c8SBruno Larsen (billionai) } 83757468e2c8SBruno Larsen (billionai) } 83767468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 83777468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 83787468e2c8SBruno Larsen (billionai) } 83797468e2c8SBruno Larsen (billionai) } 83807468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 83817468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 83827468e2c8SBruno Larsen (billionai) } 83837468e2c8SBruno Larsen (billionai) } 83847468e2c8SBruno Larsen (billionai) } 83857468e2c8SBruno Larsen (billionai) 83867468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 83877468e2c8SBruno Larsen (billionai) { 83887468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 83897468e2c8SBruno Larsen (billionai) 83907468e2c8SBruno Larsen (billionai) /* 83917468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 83927468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 83937468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 83947468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 83957468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 83967468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 83977468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 83987468e2c8SBruno Larsen (billionai) */ 83997468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 84007468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 84017468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 84027468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 84037468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 84047468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 84057468e2c8SBruno Larsen (billionai) } 84067468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 84077468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 84087468e2c8SBruno Larsen (billionai) return 0; 84097468e2c8SBruno Larsen (billionai) } 84107468e2c8SBruno Larsen (billionai) 8411624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 8412624cb07fSRichard Henderson { 8413624cb07fSRichard Henderson opc_handler_t **table, *handler; 8414624cb07fSRichard Henderson uint32_t inval; 8415624cb07fSRichard Henderson 8416624cb07fSRichard Henderson ctx->opcode = insn; 8417624cb07fSRichard Henderson 8418624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 8419624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8420624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 8421624cb07fSRichard Henderson 8422624cb07fSRichard Henderson table = cpu->opcodes; 8423624cb07fSRichard Henderson handler = table[opc1(insn)]; 8424624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8425624cb07fSRichard Henderson table = ind_table(handler); 8426624cb07fSRichard Henderson handler = table[opc2(insn)]; 8427624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8428624cb07fSRichard Henderson table = ind_table(handler); 8429624cb07fSRichard Henderson handler = table[opc3(insn)]; 8430624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 8431624cb07fSRichard Henderson table = ind_table(handler); 8432624cb07fSRichard Henderson handler = table[opc4(insn)]; 8433624cb07fSRichard Henderson } 8434624cb07fSRichard Henderson } 8435624cb07fSRichard Henderson } 8436624cb07fSRichard Henderson 8437624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 8438624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 8439624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 8440624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8441624cb07fSRichard Henderson TARGET_FMT_lx "\n", 8442624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8443624cb07fSRichard Henderson insn, ctx->cia); 8444624cb07fSRichard Henderson return false; 8445624cb07fSRichard Henderson } 8446624cb07fSRichard Henderson 8447624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 8448624cb07fSRichard Henderson && Rc(insn))) { 8449624cb07fSRichard Henderson inval = handler->inval2; 8450624cb07fSRichard Henderson } else { 8451624cb07fSRichard Henderson inval = handler->inval1; 8452624cb07fSRichard Henderson } 8453624cb07fSRichard Henderson 8454624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 8455624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 8456624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 8457624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 8458624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 8459624cb07fSRichard Henderson insn, ctx->cia); 8460624cb07fSRichard Henderson return false; 8461624cb07fSRichard Henderson } 8462624cb07fSRichard Henderson 8463624cb07fSRichard Henderson handler->handler(ctx); 8464624cb07fSRichard Henderson return true; 8465624cb07fSRichard Henderson } 8466624cb07fSRichard Henderson 8467b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 8468fcf5ef2aSThomas Huth { 8469b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 84709c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 84712df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 8472fcf5ef2aSThomas Huth 8473b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 84742df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 8475d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 84762df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 84772df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 8478b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 8479b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 8480b0c2d521SEmilio G. Cota ctx->access_type = -1; 8481d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 84822df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 8483b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 84840e3bf489SRoman Kapl ctx->flags = env->flags; 8485fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 84862df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 8487b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 8488fcf5ef2aSThomas Huth #endif 8489e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 8490e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 8491d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 8492fcf5ef2aSThomas Huth 84932df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 84942df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 84952df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 84962df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 84972df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 8498f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 84991db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 8500f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 8501f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 850246d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 85032df4fe7aSRichard Henderson 8504b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 85052df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 85062df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 85079498d103SRichard Henderson ctx->base.max_insns = 1; 8508efe843d8SDavid Gibson } 85092df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 8510b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 8511efe843d8SDavid Gibson } 851213b45575SRichard Henderson } 8513fcf5ef2aSThomas Huth 8514b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 8515b0c2d521SEmilio G. Cota { 8516b0c2d521SEmilio G. Cota } 8517fcf5ef2aSThomas Huth 8518b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 8519b0c2d521SEmilio G. Cota { 8520b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 8521b0c2d521SEmilio G. Cota } 8522b0c2d521SEmilio G. Cota 852399082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 852499082815SRichard Henderson { 852599082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 852699082815SRichard Henderson return opc1(insn) == 1; 852799082815SRichard Henderson } 852899082815SRichard Henderson 8529b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 8530b0c2d521SEmilio G. Cota { 8531b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 853228876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 8533b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 853499082815SRichard Henderson target_ulong pc; 8535624cb07fSRichard Henderson uint32_t insn; 8536624cb07fSRichard Henderson bool ok; 8537b0c2d521SEmilio G. Cota 8538fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 8539fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 8540b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 8541b0c2d521SEmilio G. Cota 854299082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 85434e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 854499082815SRichard Henderson ctx->base.pc_next = pc += 4; 8545fcf5ef2aSThomas Huth 854699082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 854799082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 854899082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 854999082815SRichard Henderson } else if ((pc & 63) == 0) { 855099082815SRichard Henderson /* 855199082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 855299082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 855399082815SRichard Henderson * 64-byte address boundary (system alignment error). 855499082815SRichard Henderson */ 855599082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 855699082815SRichard Henderson ok = true; 855799082815SRichard Henderson } else { 85584e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 85594e116893SIlya Leoshkevich need_byteswap(ctx)); 856099082815SRichard Henderson ctx->base.pc_next = pc += 4; 856199082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 856299082815SRichard Henderson } 8563624cb07fSRichard Henderson if (!ok) { 8564624cb07fSRichard Henderson gen_invalid(ctx); 8565fcf5ef2aSThomas Huth } 8566624cb07fSRichard Henderson 856764a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 856899082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 856964a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 857064a0f644SRichard Henderson } 857164a0f644SRichard Henderson 857251eb7b1dSRichard Henderson translator_loop_temp_check(&ctx->base); 8573fcf5ef2aSThomas Huth } 8574b0c2d521SEmilio G. Cota 8575b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 8576b0c2d521SEmilio G. Cota { 8577b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 8578a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 8579a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 8580b0c2d521SEmilio G. Cota 8581a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 8582a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 85833d8a5b69SRichard Henderson return; 85843d8a5b69SRichard Henderson } 85853d8a5b69SRichard Henderson 8586a9b5b3d0SRichard Henderson /* Honor single stepping. */ 85879498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) 85889498d103SRichard Henderson && (nip <= 0x100 || nip > 0xf00)) { 8589a9b5b3d0SRichard Henderson switch (is_jmp) { 8590a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8591a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8592a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8593a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8594a9b5b3d0SRichard Henderson break; 8595a9b5b3d0SRichard Henderson case DISAS_EXIT: 8596a9b5b3d0SRichard Henderson case DISAS_CHAIN: 8597a9b5b3d0SRichard Henderson break; 8598a9b5b3d0SRichard Henderson default: 8599a9b5b3d0SRichard Henderson g_assert_not_reached(); 8600fcf5ef2aSThomas Huth } 860113b45575SRichard Henderson 8602a9b5b3d0SRichard Henderson gen_debug_exception(ctx); 8603a9b5b3d0SRichard Henderson return; 8604a9b5b3d0SRichard Henderson } 8605a9b5b3d0SRichard Henderson 8606a9b5b3d0SRichard Henderson switch (is_jmp) { 8607a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 8608a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 860946d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 8610a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 8611a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8612a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 8613a9b5b3d0SRichard Henderson break; 8614a9b5b3d0SRichard Henderson } 8615a9b5b3d0SRichard Henderson /* fall through */ 8616a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 8617a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8618a9b5b3d0SRichard Henderson /* fall through */ 8619a9b5b3d0SRichard Henderson case DISAS_CHAIN: 862046d396bdSDaniel Henrique Barboza /* 862146d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 862246d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 862346d396bdSDaniel Henrique Barboza */ 862446d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 862546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 862646d396bdSDaniel Henrique Barboza } 862746d396bdSDaniel Henrique Barboza 8628a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 8629a9b5b3d0SRichard Henderson break; 8630a9b5b3d0SRichard Henderson 8631a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 8632a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 8633a9b5b3d0SRichard Henderson /* fall through */ 8634a9b5b3d0SRichard Henderson case DISAS_EXIT: 863546d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 863607ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 8637a9b5b3d0SRichard Henderson break; 8638a9b5b3d0SRichard Henderson 8639a9b5b3d0SRichard Henderson default: 8640a9b5b3d0SRichard Henderson g_assert_not_reached(); 8641fcf5ef2aSThomas Huth } 8642fcf5ef2aSThomas Huth } 8643b0c2d521SEmilio G. Cota 8644b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 8645b0c2d521SEmilio G. Cota { 8646b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 8647b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 8648b0c2d521SEmilio G. Cota } 8649b0c2d521SEmilio G. Cota 8650b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 8651b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 8652b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 8653b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 8654b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 8655b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 8656b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 8657b0c2d521SEmilio G. Cota }; 8658b0c2d521SEmilio G. Cota 86598b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8660b0c2d521SEmilio G. Cota { 8661b0c2d521SEmilio G. Cota DisasContext ctx; 8662b0c2d521SEmilio G. Cota 86638b86d6d2SRichard Henderson translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); 8664fcf5ef2aSThomas Huth } 8665fcf5ef2aSThomas Huth 8666fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 8667fcf5ef2aSThomas Huth target_ulong *data) 8668fcf5ef2aSThomas Huth { 8669fcf5ef2aSThomas Huth env->nip = data[0]; 8670fcf5ef2aSThomas Huth } 8671