1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 106bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 27dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 28fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33b6bac4bcSEmilio G. Cota #include "exec/translator.h" 34fcf5ef2aSThomas Huth #include "exec/log.h" 35f34ec0f6SRichard Henderson #include "qemu/atomic128.h" 3699e964efSFabiano Rosas #include "spr_common.h" 37eeaaefe9SLeandro Lupori #include "power8-pmu.h" 38fcf5ef2aSThomas Huth 393e770bf7SBruno Larsen (billionai) #include "qemu/qemu-print.h" 403e770bf7SBruno Larsen (billionai) #include "qapi/error.h" 41fcf5ef2aSThomas Huth 42d53106c9SRichard Henderson #define HELPER_H "helper.h" 43d53106c9SRichard Henderson #include "exec/helper-info.c.inc" 44d53106c9SRichard Henderson #undef HELPER_H 45d53106c9SRichard Henderson 46fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 47fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 50efe843d8SDavid Gibson /* #define PPC_DEBUG_DISAS */ 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 53fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 54fcf5ef2aSThomas Huth #else 55fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 56fcf5ef2aSThomas Huth #endif 57fcf5ef2aSThomas Huth /*****************************************************************************/ 58fcf5ef2aSThomas Huth /* Code translation helpers */ 59fcf5ef2aSThomas Huth 60fcf5ef2aSThomas Huth /* global register indexes */ 61fcf5ef2aSThomas Huth static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ 62fcf5ef2aSThomas Huth + 10 * 4 + 22 * 5 /* SPE GPRh */ 63fcf5ef2aSThomas Huth + 8 * 5 /* CRF */]; 64fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 65fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76392d328aSNicholas Piggin static TCGv cpu_reserve_length; 77253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 78894448aeSRichard Henderson static TCGv cpu_reserve_val2; 79fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 80fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char *p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth } 111fcf5ef2aSThomas Huth 112fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 114fcf5ef2aSThomas Huth 115fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 116fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 119fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 120fcf5ef2aSThomas Huth 121fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 122fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 125fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 126fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 127fcf5ef2aSThomas Huth #endif 128fcf5ef2aSThomas Huth 129fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 131fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 132fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 133fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 135fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 136fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 137dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 138dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 139dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 140dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 141fcf5ef2aSThomas Huth 142fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 143fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 144fcf5ef2aSThomas Huth "reserve_addr"); 145392d328aSNicholas Piggin cpu_reserve_length = tcg_global_mem_new(cpu_env, 146392d328aSNicholas Piggin offsetof(CPUPPCState, 147392d328aSNicholas Piggin reserve_length), 148392d328aSNicholas Piggin "reserve_length"); 149253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 150253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 151253ce7b2SNikunj A Dadhania "reserve_val"); 152894448aeSRichard Henderson cpu_reserve_val2 = tcg_global_mem_new(cpu_env, 153894448aeSRichard Henderson offsetof(CPUPPCState, reserve_val2), 154894448aeSRichard Henderson "reserve_val2"); 155fcf5ef2aSThomas Huth 156fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 157fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 158fcf5ef2aSThomas Huth 159fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 160efe843d8SDavid Gibson offsetof(CPUPPCState, access_type), 161efe843d8SDavid Gibson "access_type"); 162fcf5ef2aSThomas Huth } 163fcf5ef2aSThomas Huth 164fcf5ef2aSThomas Huth /* internal defines */ 165fcf5ef2aSThomas Huth struct DisasContext { 166b6bac4bcSEmilio G. Cota DisasContextBase base; 1672c2bcb1bSRichard Henderson target_ulong cia; /* current instruction address */ 168fcf5ef2aSThomas Huth uint32_t opcode; 169fcf5ef2aSThomas Huth /* Routine used to access memory */ 170fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 171fcf5ef2aSThomas Huth bool lazy_tlb_flush; 172fcf5ef2aSThomas Huth bool need_access_type; 173fcf5ef2aSThomas Huth int mem_idx; 174fcf5ef2aSThomas Huth int access_type; 175fcf5ef2aSThomas Huth /* Translation flags */ 17614776ab5STony Nguyen MemOp default_tcg_memop_mask; 177fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 178fcf5ef2aSThomas Huth bool sf_mode; 179fcf5ef2aSThomas Huth bool has_cfar; 180fcf5ef2aSThomas Huth #endif 181fcf5ef2aSThomas Huth bool fpu_enabled; 182fcf5ef2aSThomas Huth bool altivec_enabled; 183fcf5ef2aSThomas Huth bool vsx_enabled; 184fcf5ef2aSThomas Huth bool spe_enabled; 185fcf5ef2aSThomas Huth bool tm_enabled; 186c6fd28fdSSuraj Jitindar Singh bool gtse; 1871db3632aSMatheus Ferst bool hr; 188f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc0; 189f7460df2SDaniel Henrique Barboza bool mmcr0_pmcc1; 1908b3d1c49SLeandro Lupori bool mmcr0_pmcjce; 1918b3d1c49SLeandro Lupori bool pmc_other; 19246d396bdSDaniel Henrique Barboza bool pmu_insn_cnt; 193fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 194fcf5ef2aSThomas Huth int singlestep_enabled; 1950e3bf489SRoman Kapl uint32_t flags; 196fcf5ef2aSThomas Huth uint64_t insns_flags; 197fcf5ef2aSThomas Huth uint64_t insns_flags2; 198fcf5ef2aSThomas Huth }; 199fcf5ef2aSThomas Huth 200a9b5b3d0SRichard Henderson #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ 201a9b5b3d0SRichard Henderson #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ 202a9b5b3d0SRichard Henderson #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ 203a9b5b3d0SRichard Henderson #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ 204a9b5b3d0SRichard Henderson 205fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 206fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 207fcf5ef2aSThomas Huth { 208ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 209fcf5ef2aSThomas Huth return ctx->le_mode; 210fcf5ef2aSThomas Huth #else 211fcf5ef2aSThomas Huth return !ctx->le_mode; 212fcf5ef2aSThomas Huth #endif 213fcf5ef2aSThomas Huth } 214fcf5ef2aSThomas Huth 215fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 216fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 217fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 218fcf5ef2aSThomas Huth #else 219fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 220fcf5ef2aSThomas Huth #endif 221fcf5ef2aSThomas Huth 222fcf5ef2aSThomas Huth struct opc_handler_t { 223fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 224fcf5ef2aSThomas Huth uint32_t inval1; 225fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 226fcf5ef2aSThomas Huth uint32_t inval2; 227fcf5ef2aSThomas Huth /* instruction type */ 228fcf5ef2aSThomas Huth uint64_t type; 229fcf5ef2aSThomas Huth /* extended instruction type */ 230fcf5ef2aSThomas Huth uint64_t type2; 231fcf5ef2aSThomas Huth /* handler */ 232fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 233fcf5ef2aSThomas Huth }; 234fcf5ef2aSThomas Huth 235b769d4c8SNicholas Piggin static inline bool gen_serialize(DisasContext *ctx) 236b769d4c8SNicholas Piggin { 237b769d4c8SNicholas Piggin if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 238b769d4c8SNicholas Piggin /* Restart with exclusive lock. */ 239b769d4c8SNicholas Piggin gen_helper_exit_atomic(cpu_env); 240b769d4c8SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 241b769d4c8SNicholas Piggin return false; 242b769d4c8SNicholas Piggin } 243b769d4c8SNicholas Piggin return true; 244b769d4c8SNicholas Piggin } 245b769d4c8SNicholas Piggin 246b769d4c8SNicholas Piggin #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2473401ea3cSNicholas Piggin static inline bool gen_serialize_core_lpar(DisasContext *ctx) 248b769d4c8SNicholas Piggin { 2493401ea3cSNicholas Piggin if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { 250b769d4c8SNicholas Piggin return gen_serialize(ctx); 251b769d4c8SNicholas Piggin } 252b769d4c8SNicholas Piggin 253b769d4c8SNicholas Piggin return true; 254b769d4c8SNicholas Piggin } 255b769d4c8SNicholas Piggin #endif 256b769d4c8SNicholas Piggin 2570e3bf489SRoman Kapl /* SPR load/store helpers */ 2580e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 2590e3bf489SRoman Kapl { 2600e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2610e3bf489SRoman Kapl } 2620e3bf489SRoman Kapl 2630e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 2640e3bf489SRoman Kapl { 2650e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 2660e3bf489SRoman Kapl } 2670e3bf489SRoman Kapl 268fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 269fcf5ef2aSThomas Huth { 270fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 271fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 272fcf5ef2aSThomas Huth ctx->access_type = access_type; 273fcf5ef2aSThomas Huth } 274fcf5ef2aSThomas Huth } 275fcf5ef2aSThomas Huth 276fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 277fcf5ef2aSThomas Huth { 278fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 279fcf5ef2aSThomas Huth nip = (uint32_t)nip; 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 282fcf5ef2aSThomas Huth } 283fcf5ef2aSThomas Huth 284fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 285fcf5ef2aSThomas Huth { 286fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 287fcf5ef2aSThomas Huth 288efe843d8SDavid Gibson /* 289efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 290efe843d8SDavid Gibson * faulting instruction 291fcf5ef2aSThomas Huth */ 2922c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 2937058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 2947058ff52SRichard Henderson t1 = tcg_constant_i32(error); 295fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 2963d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 297fcf5ef2aSThomas Huth } 298fcf5ef2aSThomas Huth 299fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 300fcf5ef2aSThomas Huth { 301fcf5ef2aSThomas Huth TCGv_i32 t0; 302fcf5ef2aSThomas Huth 303efe843d8SDavid Gibson /* 304efe843d8SDavid Gibson * These are all synchronous exceptions, we set the PC back to the 305efe843d8SDavid Gibson * faulting instruction 306fcf5ef2aSThomas Huth */ 3072c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 3087058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 309fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3103d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 311fcf5ef2aSThomas Huth } 312fcf5ef2aSThomas Huth 313fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 314fcf5ef2aSThomas Huth target_ulong nip) 315fcf5ef2aSThomas Huth { 316fcf5ef2aSThomas Huth TCGv_i32 t0; 317fcf5ef2aSThomas Huth 318fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 3197058ff52SRichard Henderson t0 = tcg_constant_i32(excp); 320fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 3213d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 322fcf5ef2aSThomas Huth } 323fcf5ef2aSThomas Huth 3242fdedcbcSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 3252fdedcbcSMatheus Ferst static void gen_ppc_maybe_interrupt(DisasContext *ctx) 3262fdedcbcSMatheus Ferst { 327283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 3282fdedcbcSMatheus Ferst gen_helper_ppc_maybe_interrupt(cpu_env); 3292fdedcbcSMatheus Ferst } 3302fdedcbcSMatheus Ferst #endif 3312fdedcbcSMatheus Ferst 332e150ac89SRoman Kapl /* 333e150ac89SRoman Kapl * Tells the caller what is the appropriate exception to generate and prepares 334e150ac89SRoman Kapl * SPR registers for this exception. 335e150ac89SRoman Kapl * 336e150ac89SRoman Kapl * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or 337e150ac89SRoman Kapl * POWERPC_EXCP_DEBUG (on BookE). 3380e3bf489SRoman Kapl */ 339a11e3a15SNicholas Piggin static void gen_debug_exception(DisasContext *ctx, bool rfi_type) 3400e3bf489SRoman Kapl { 34114895384SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 3420e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 3430e3bf489SRoman Kapl target_ulong dbsr = 0; 344e150ac89SRoman Kapl if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { 3450e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 346e150ac89SRoman Kapl } else { 347e150ac89SRoman Kapl /* Must have been branch */ 3480e3bf489SRoman Kapl dbsr = DBCR0_BRT; 3490e3bf489SRoman Kapl } 3500e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 3510e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 3520e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 3530e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 35414895384SNicholas Piggin gen_helper_raise_exception(cpu_env, 35514895384SNicholas Piggin tcg_constant_i32(POWERPC_EXCP_DEBUG)); 3563d8a5b69SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 35714895384SNicholas Piggin } else { 358a11e3a15SNicholas Piggin if (!rfi_type) { /* BookS does not single step rfi type instructions */ 35914895384SNicholas Piggin TCGv t0 = tcg_temp_new(); 36014895384SNicholas Piggin tcg_gen_movi_tl(t0, ctx->cia); 36114895384SNicholas Piggin gen_helper_book3s_trace(cpu_env, t0); 36214895384SNicholas Piggin ctx->base.is_jmp = DISAS_NORETURN; 36314895384SNicholas Piggin } 364a11e3a15SNicholas Piggin } 36514895384SNicholas Piggin #endif 366fcf5ef2aSThomas Huth } 367fcf5ef2aSThomas Huth 368fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 369fcf5ef2aSThomas Huth { 370fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 371fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 372fcf5ef2aSThomas Huth } 373fcf5ef2aSThomas Huth 374fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 375fcf5ef2aSThomas Huth { 376fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 377fcf5ef2aSThomas Huth } 378fcf5ef2aSThomas Huth 379fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 380fcf5ef2aSThomas Huth { 381fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 382fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 383fcf5ef2aSThomas Huth } 384fcf5ef2aSThomas Huth 38537f219c8SBruno Larsen (billionai) /*****************************************************************************/ 38637f219c8SBruno Larsen (billionai) /* SPR READ/WRITE CALLBACKS */ 38737f219c8SBruno Larsen (billionai) 388a829cec3SBruno Larsen (billionai) void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 38937f219c8SBruno Larsen (billionai) { 39037f219c8SBruno Larsen (billionai) #if 0 39137f219c8SBruno Larsen (billionai) sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 39237f219c8SBruno Larsen (billionai) printf("ERROR: try to access SPR %d !\n", sprn); 39337f219c8SBruno Larsen (billionai) #endif 39437f219c8SBruno Larsen (billionai) } 39537f219c8SBruno Larsen (billionai) 39637f219c8SBruno Larsen (billionai) /* #define PPC_DUMP_SPR_ACCESSES */ 39737f219c8SBruno Larsen (billionai) 39837f219c8SBruno Larsen (billionai) /* 39937f219c8SBruno Larsen (billionai) * Generic callbacks: 40037f219c8SBruno Larsen (billionai) * do nothing but store/retrieve spr value 40137f219c8SBruno Larsen (billionai) */ 40237f219c8SBruno Larsen (billionai) static void spr_load_dump_spr(int sprn) 40337f219c8SBruno Larsen (billionai) { 40437f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4057058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 40637f219c8SBruno Larsen (billionai) gen_helper_load_dump_spr(cpu_env, t0); 40737f219c8SBruno Larsen (billionai) #endif 40837f219c8SBruno Larsen (billionai) } 40937f219c8SBruno Larsen (billionai) 410a829cec3SBruno Larsen (billionai) void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 41137f219c8SBruno Larsen (billionai) { 41237f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 41337f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 41437f219c8SBruno Larsen (billionai) } 41537f219c8SBruno Larsen (billionai) 41637f219c8SBruno Larsen (billionai) static void spr_store_dump_spr(int sprn) 41737f219c8SBruno Larsen (billionai) { 41837f219c8SBruno Larsen (billionai) #ifdef PPC_DUMP_SPR_ACCESSES 4197058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 42037f219c8SBruno Larsen (billionai) gen_helper_store_dump_spr(cpu_env, t0); 42137f219c8SBruno Larsen (billionai) #endif 42237f219c8SBruno Larsen (billionai) } 42337f219c8SBruno Larsen (billionai) 424a829cec3SBruno Larsen (billionai) void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 42537f219c8SBruno Larsen (billionai) { 42637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 42737f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 42837f219c8SBruno Larsen (billionai) } 42937f219c8SBruno Larsen (billionai) 430a829cec3SBruno Larsen (billionai) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 43137f219c8SBruno Larsen (billionai) { 43237f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 43337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 43437f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 43537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 43637f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 43737f219c8SBruno Larsen (billionai) #else 43837f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 43937f219c8SBruno Larsen (billionai) #endif 44037f219c8SBruno Larsen (billionai) } 44137f219c8SBruno Larsen (billionai) 4429cdfd1b9SNicholas Piggin void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) 4439cdfd1b9SNicholas Piggin { 4449cdfd1b9SNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT)) { 4459cdfd1b9SNicholas Piggin spr_write_generic(ctx, sprn, gprn); 4469cdfd1b9SNicholas Piggin return; 4479cdfd1b9SNicholas Piggin } 4489cdfd1b9SNicholas Piggin 4499cdfd1b9SNicholas Piggin if (!gen_serialize(ctx)) { 4509cdfd1b9SNicholas Piggin return; 4519cdfd1b9SNicholas Piggin } 4529cdfd1b9SNicholas Piggin 4539cdfd1b9SNicholas Piggin gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn), 4549cdfd1b9SNicholas Piggin cpu_gpr[gprn]); 4559cdfd1b9SNicholas Piggin spr_store_dump_spr(sprn); 4569cdfd1b9SNicholas Piggin } 4579cdfd1b9SNicholas Piggin 458c5d98a7bSNicholas Piggin static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) 459fbda88f7SNicholas Piggin { 460488aad11SNicholas Piggin /* This does not implement >1 thread */ 461488aad11SNicholas Piggin TCGv t0 = tcg_temp_new(); 462488aad11SNicholas Piggin TCGv t1 = tcg_temp_new(); 463488aad11SNicholas Piggin tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ 464488aad11SNicholas Piggin tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ 465488aad11SNicholas Piggin tcg_gen_or_tl(t1, t1, t0); 466488aad11SNicholas Piggin gen_store_spr(sprn, t1); 467c5d98a7bSNicholas Piggin } 468c5d98a7bSNicholas Piggin 469c5d98a7bSNicholas Piggin void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) 470c5d98a7bSNicholas Piggin { 4713401ea3cSNicholas Piggin if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { 4723401ea3cSNicholas Piggin /* CTRL behaves as 1-thread in LPAR-per-thread mode */ 473c5d98a7bSNicholas Piggin spr_write_CTRL_ST(ctx, sprn, gprn); 474c5d98a7bSNicholas Piggin goto out; 475c5d98a7bSNicholas Piggin } 476c5d98a7bSNicholas Piggin 477c5d98a7bSNicholas Piggin if (!gen_serialize(ctx)) { 478c5d98a7bSNicholas Piggin return; 479c5d98a7bSNicholas Piggin } 480c5d98a7bSNicholas Piggin 481c5d98a7bSNicholas Piggin gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), 482c5d98a7bSNicholas Piggin cpu_gpr[gprn]); 483c5d98a7bSNicholas Piggin out: 484488aad11SNicholas Piggin spr_store_dump_spr(sprn); 485fbda88f7SNicholas Piggin 486fbda88f7SNicholas Piggin /* 487fbda88f7SNicholas Piggin * SPR_CTRL writes must force a new translation block, 488fbda88f7SNicholas Piggin * allowing the PMU to calculate the run latch events with 489fbda88f7SNicholas Piggin * more accuracy. 490fbda88f7SNicholas Piggin */ 491fbda88f7SNicholas Piggin ctx->base.is_jmp = DISAS_EXIT_UPDATE; 492fbda88f7SNicholas Piggin } 493fbda88f7SNicholas Piggin 494fbda88f7SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 495a829cec3SBruno Larsen (billionai) void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 49637f219c8SBruno Larsen (billionai) { 49737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 49837f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 49937f219c8SBruno Larsen (billionai) gen_load_spr(t0, sprn); 50037f219c8SBruno Larsen (billionai) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 50137f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, t1); 50237f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 50337f219c8SBruno Larsen (billionai) } 50437f219c8SBruno Larsen (billionai) 505a829cec3SBruno Larsen (billionai) void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 50637f219c8SBruno Larsen (billionai) { 50737f219c8SBruno Larsen (billionai) } 50837f219c8SBruno Larsen (billionai) 50937f219c8SBruno Larsen (billionai) #endif 51037f219c8SBruno Larsen (billionai) 51137f219c8SBruno Larsen (billionai) /* SPR common to all PowerPC */ 51237f219c8SBruno Larsen (billionai) /* XER */ 513a829cec3SBruno Larsen (billionai) void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 51437f219c8SBruno Larsen (billionai) { 51537f219c8SBruno Larsen (billionai) TCGv dst = cpu_gpr[gprn]; 51637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 51737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 51837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 51937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(dst, cpu_xer); 52037f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_so, XER_SO); 52137f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 52237f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 52337f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t1); 52437f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t2); 52537f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 52637f219c8SBruno Larsen (billionai) if (is_isa300(ctx)) { 52737f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 52837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 52937f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 53037f219c8SBruno Larsen (billionai) tcg_gen_or_tl(dst, dst, t0); 53137f219c8SBruno Larsen (billionai) } 53237f219c8SBruno Larsen (billionai) } 53337f219c8SBruno Larsen (billionai) 534a829cec3SBruno Larsen (billionai) void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 53537f219c8SBruno Larsen (billionai) { 53637f219c8SBruno Larsen (billionai) TCGv src = cpu_gpr[gprn]; 53737f219c8SBruno Larsen (billionai) /* Write all flags, while reading back check for isa300 */ 53837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(cpu_xer, src, 53937f219c8SBruno Larsen (billionai) ~((1u << XER_SO) | 54037f219c8SBruno Larsen (billionai) (1u << XER_OV) | (1u << XER_OV32) | 54137f219c8SBruno Larsen (billionai) (1u << XER_CA) | (1u << XER_CA32))); 54237f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 54337f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 54437f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 54537f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 54637f219c8SBruno Larsen (billionai) tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 54737f219c8SBruno Larsen (billionai) } 54837f219c8SBruno Larsen (billionai) 54937f219c8SBruno Larsen (billionai) /* LR */ 550a829cec3SBruno Larsen (billionai) void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 55137f219c8SBruno Larsen (billionai) { 55237f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 55337f219c8SBruno Larsen (billionai) } 55437f219c8SBruno Larsen (billionai) 555a829cec3SBruno Larsen (billionai) void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 55637f219c8SBruno Larsen (billionai) { 55737f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 55837f219c8SBruno Larsen (billionai) } 55937f219c8SBruno Larsen (billionai) 56037f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 561*14192307SNicholas Piggin /* Debug facilities */ 562*14192307SNicholas Piggin /* CFAR */ 563a829cec3SBruno Larsen (billionai) void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 56437f219c8SBruno Larsen (billionai) { 56537f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 56637f219c8SBruno Larsen (billionai) } 56737f219c8SBruno Larsen (billionai) 568a829cec3SBruno Larsen (billionai) void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 56937f219c8SBruno Larsen (billionai) { 57037f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 57137f219c8SBruno Larsen (billionai) } 572*14192307SNicholas Piggin 573*14192307SNicholas Piggin /* Breakpoint */ 574*14192307SNicholas Piggin void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) 575*14192307SNicholas Piggin { 576*14192307SNicholas Piggin translator_io_start(&ctx->base); 577*14192307SNicholas Piggin gen_helper_store_ciabr(cpu_env, cpu_gpr[gprn]); 578*14192307SNicholas Piggin } 57937f219c8SBruno Larsen (billionai) #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 58037f219c8SBruno Larsen (billionai) 58137f219c8SBruno Larsen (billionai) /* CTR */ 582a829cec3SBruno Larsen (billionai) void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 58337f219c8SBruno Larsen (billionai) { 58437f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 58537f219c8SBruno Larsen (billionai) } 58637f219c8SBruno Larsen (billionai) 587a829cec3SBruno Larsen (billionai) void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 58837f219c8SBruno Larsen (billionai) { 58937f219c8SBruno Larsen (billionai) tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 59037f219c8SBruno Larsen (billionai) } 59137f219c8SBruno Larsen (billionai) 59237f219c8SBruno Larsen (billionai) /* User read access to SPR */ 59337f219c8SBruno Larsen (billionai) /* USPRx */ 59437f219c8SBruno Larsen (billionai) /* UMMCRx */ 59537f219c8SBruno Larsen (billionai) /* UPMCx */ 59637f219c8SBruno Larsen (billionai) /* USIA */ 59737f219c8SBruno Larsen (billionai) /* UDECR */ 598a829cec3SBruno Larsen (billionai) void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 59937f219c8SBruno Larsen (billionai) { 60037f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 60137f219c8SBruno Larsen (billionai) } 60237f219c8SBruno Larsen (billionai) 60337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 604a829cec3SBruno Larsen (billionai) void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 60537f219c8SBruno Larsen (billionai) { 60637f219c8SBruno Larsen (billionai) gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 60737f219c8SBruno Larsen (billionai) } 60837f219c8SBruno Larsen (billionai) #endif 60937f219c8SBruno Larsen (billionai) 61037f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC */ 61137f219c8SBruno Larsen (billionai) /* DECR */ 61237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 613a829cec3SBruno Larsen (billionai) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 61437f219c8SBruno Larsen (billionai) { 615283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 61637f219c8SBruno Larsen (billionai) gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 61737f219c8SBruno Larsen (billionai) } 61837f219c8SBruno Larsen (billionai) 619a829cec3SBruno Larsen (billionai) void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 62037f219c8SBruno Larsen (billionai) { 621283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 62237f219c8SBruno Larsen (billionai) gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 62337f219c8SBruno Larsen (billionai) } 62437f219c8SBruno Larsen (billionai) #endif 62537f219c8SBruno Larsen (billionai) 62637f219c8SBruno Larsen (billionai) /* SPR common to all non-embedded PowerPC, except 601 */ 62737f219c8SBruno Larsen (billionai) /* Time base */ 628a829cec3SBruno Larsen (billionai) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 62937f219c8SBruno Larsen (billionai) { 630283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 63137f219c8SBruno Larsen (billionai) gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 63237f219c8SBruno Larsen (billionai) } 63337f219c8SBruno Larsen (billionai) 634a829cec3SBruno Larsen (billionai) void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 63537f219c8SBruno Larsen (billionai) { 636283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 63737f219c8SBruno Larsen (billionai) gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 63837f219c8SBruno Larsen (billionai) } 63937f219c8SBruno Larsen (billionai) 640a829cec3SBruno Larsen (billionai) void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 64137f219c8SBruno Larsen (billionai) { 64237f219c8SBruno Larsen (billionai) gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 64337f219c8SBruno Larsen (billionai) } 64437f219c8SBruno Larsen (billionai) 645a829cec3SBruno Larsen (billionai) void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 64637f219c8SBruno Larsen (billionai) { 64737f219c8SBruno Larsen (billionai) gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 64837f219c8SBruno Larsen (billionai) } 64937f219c8SBruno Larsen (billionai) 65037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 651a829cec3SBruno Larsen (billionai) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 65237f219c8SBruno Larsen (billionai) { 653283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 65437f219c8SBruno Larsen (billionai) gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 65537f219c8SBruno Larsen (billionai) } 65637f219c8SBruno Larsen (billionai) 657a829cec3SBruno Larsen (billionai) void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 65837f219c8SBruno Larsen (billionai) { 659283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 66037f219c8SBruno Larsen (billionai) gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 66137f219c8SBruno Larsen (billionai) } 66237f219c8SBruno Larsen (billionai) 663a829cec3SBruno Larsen (billionai) void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 66437f219c8SBruno Larsen (billionai) { 66537f219c8SBruno Larsen (billionai) gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 66637f219c8SBruno Larsen (billionai) } 66737f219c8SBruno Larsen (billionai) 668a829cec3SBruno Larsen (billionai) void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 66937f219c8SBruno Larsen (billionai) { 67037f219c8SBruno Larsen (billionai) gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 67137f219c8SBruno Larsen (billionai) } 67237f219c8SBruno Larsen (billionai) 67337f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 674a829cec3SBruno Larsen (billionai) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 67537f219c8SBruno Larsen (billionai) { 676283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 67737f219c8SBruno Larsen (billionai) gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 67837f219c8SBruno Larsen (billionai) } 67937f219c8SBruno Larsen (billionai) 680a829cec3SBruno Larsen (billionai) void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 68137f219c8SBruno Larsen (billionai) { 682283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 68337f219c8SBruno Larsen (billionai) gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 68437f219c8SBruno Larsen (billionai) } 68537f219c8SBruno Larsen (billionai) 68637f219c8SBruno Larsen (billionai) /* HDECR */ 687a829cec3SBruno Larsen (billionai) void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 68837f219c8SBruno Larsen (billionai) { 689283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 69037f219c8SBruno Larsen (billionai) gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 69137f219c8SBruno Larsen (billionai) } 69237f219c8SBruno Larsen (billionai) 693a829cec3SBruno Larsen (billionai) void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 69437f219c8SBruno Larsen (billionai) { 695283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 69637f219c8SBruno Larsen (billionai) gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 69737f219c8SBruno Larsen (billionai) } 69837f219c8SBruno Larsen (billionai) 699a829cec3SBruno Larsen (billionai) void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 70037f219c8SBruno Larsen (billionai) { 701283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 70237f219c8SBruno Larsen (billionai) gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 70337f219c8SBruno Larsen (billionai) } 70437f219c8SBruno Larsen (billionai) 705a829cec3SBruno Larsen (billionai) void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 70637f219c8SBruno Larsen (billionai) { 707283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 70837f219c8SBruno Larsen (billionai) gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 70937f219c8SBruno Larsen (billionai) } 71037f219c8SBruno Larsen (billionai) 711a829cec3SBruno Larsen (billionai) void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 71237f219c8SBruno Larsen (billionai) { 713283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 71437f219c8SBruno Larsen (billionai) gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 71537f219c8SBruno Larsen (billionai) } 71637f219c8SBruno Larsen (billionai) 71737f219c8SBruno Larsen (billionai) #endif 71837f219c8SBruno Larsen (billionai) #endif 71937f219c8SBruno Larsen (billionai) 72037f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 72137f219c8SBruno Larsen (billionai) /* IBAT0U...IBAT0U */ 72237f219c8SBruno Larsen (billionai) /* IBAT0L...IBAT7L */ 723a829cec3SBruno Larsen (billionai) void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 72437f219c8SBruno Larsen (billionai) { 72537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 72637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 72737f219c8SBruno Larsen (billionai) IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 72837f219c8SBruno Larsen (billionai) } 72937f219c8SBruno Larsen (billionai) 730a829cec3SBruno Larsen (billionai) void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 73137f219c8SBruno Larsen (billionai) { 73237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 73337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 73437f219c8SBruno Larsen (billionai) IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 73537f219c8SBruno Larsen (billionai) } 73637f219c8SBruno Larsen (billionai) 737a829cec3SBruno Larsen (billionai) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 73837f219c8SBruno Larsen (billionai) { 7397058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); 74037f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 74137f219c8SBruno Larsen (billionai) } 74237f219c8SBruno Larsen (billionai) 743a829cec3SBruno Larsen (billionai) void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 74437f219c8SBruno Larsen (billionai) { 7457058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); 74637f219c8SBruno Larsen (billionai) gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 74737f219c8SBruno Larsen (billionai) } 74837f219c8SBruno Larsen (billionai) 749a829cec3SBruno Larsen (billionai) void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 75037f219c8SBruno Larsen (billionai) { 7517058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); 75237f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 75337f219c8SBruno Larsen (billionai) } 75437f219c8SBruno Larsen (billionai) 755a829cec3SBruno Larsen (billionai) void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 75637f219c8SBruno Larsen (billionai) { 7577058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); 75837f219c8SBruno Larsen (billionai) gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 75937f219c8SBruno Larsen (billionai) } 76037f219c8SBruno Larsen (billionai) 76137f219c8SBruno Larsen (billionai) /* DBAT0U...DBAT7U */ 76237f219c8SBruno Larsen (billionai) /* DBAT0L...DBAT7L */ 763a829cec3SBruno Larsen (billionai) void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 76437f219c8SBruno Larsen (billionai) { 76537f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 76637f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 76737f219c8SBruno Larsen (billionai) DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 76837f219c8SBruno Larsen (billionai) } 76937f219c8SBruno Larsen (billionai) 770a829cec3SBruno Larsen (billionai) void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 77137f219c8SBruno Larsen (billionai) { 77237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 77337f219c8SBruno Larsen (billionai) offsetof(CPUPPCState, 77437f219c8SBruno Larsen (billionai) DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 77537f219c8SBruno Larsen (billionai) } 77637f219c8SBruno Larsen (billionai) 777a829cec3SBruno Larsen (billionai) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 77837f219c8SBruno Larsen (billionai) { 7797058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); 78037f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 78137f219c8SBruno Larsen (billionai) } 78237f219c8SBruno Larsen (billionai) 783a829cec3SBruno Larsen (billionai) void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 78437f219c8SBruno Larsen (billionai) { 7857058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); 78637f219c8SBruno Larsen (billionai) gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 78737f219c8SBruno Larsen (billionai) } 78837f219c8SBruno Larsen (billionai) 789a829cec3SBruno Larsen (billionai) void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 79037f219c8SBruno Larsen (billionai) { 7917058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); 79237f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 79337f219c8SBruno Larsen (billionai) } 79437f219c8SBruno Larsen (billionai) 795a829cec3SBruno Larsen (billionai) void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 79637f219c8SBruno Larsen (billionai) { 7977058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); 79837f219c8SBruno Larsen (billionai) gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 79937f219c8SBruno Larsen (billionai) } 80037f219c8SBruno Larsen (billionai) 80137f219c8SBruno Larsen (billionai) /* SDR1 */ 802a829cec3SBruno Larsen (billionai) void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 80337f219c8SBruno Larsen (billionai) { 80437f219c8SBruno Larsen (billionai) gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 80537f219c8SBruno Larsen (billionai) } 80637f219c8SBruno Larsen (billionai) 80737f219c8SBruno Larsen (billionai) #if defined(TARGET_PPC64) 80837f219c8SBruno Larsen (billionai) /* 64 bits PowerPC specific SPRs */ 80937f219c8SBruno Larsen (billionai) /* PIDR */ 810a829cec3SBruno Larsen (billionai) void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 81137f219c8SBruno Larsen (billionai) { 81237f219c8SBruno Larsen (billionai) gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 81337f219c8SBruno Larsen (billionai) } 81437f219c8SBruno Larsen (billionai) 815a829cec3SBruno Larsen (billionai) void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 81637f219c8SBruno Larsen (billionai) { 81737f219c8SBruno Larsen (billionai) gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 81837f219c8SBruno Larsen (billionai) } 81937f219c8SBruno Larsen (billionai) 820a829cec3SBruno Larsen (billionai) void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 82137f219c8SBruno Larsen (billionai) { 82237f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 82337f219c8SBruno Larsen (billionai) } 82437f219c8SBruno Larsen (billionai) 825a829cec3SBruno Larsen (billionai) void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 82637f219c8SBruno Larsen (billionai) { 82737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 82837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 82937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 83037f219c8SBruno Larsen (billionai) } 831a829cec3SBruno Larsen (billionai) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 83237f219c8SBruno Larsen (billionai) { 83337f219c8SBruno Larsen (billionai) gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 83437f219c8SBruno Larsen (billionai) } 83537f219c8SBruno Larsen (billionai) 836a829cec3SBruno Larsen (billionai) void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 83737f219c8SBruno Larsen (billionai) { 83837f219c8SBruno Larsen (billionai) gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 83937f219c8SBruno Larsen (billionai) } 84037f219c8SBruno Larsen (billionai) 84137f219c8SBruno Larsen (billionai) /* DPDES */ 842a829cec3SBruno Larsen (billionai) void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 84337f219c8SBruno Larsen (billionai) { 8443401ea3cSNicholas Piggin if (!gen_serialize_core_lpar(ctx)) { 845d24e80b2SNicholas Piggin return; 846d24e80b2SNicholas Piggin } 847d24e80b2SNicholas Piggin 84837f219c8SBruno Larsen (billionai) gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 84937f219c8SBruno Larsen (billionai) } 85037f219c8SBruno Larsen (billionai) 851a829cec3SBruno Larsen (billionai) void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 85237f219c8SBruno Larsen (billionai) { 8533401ea3cSNicholas Piggin if (!gen_serialize_core_lpar(ctx)) { 854d24e80b2SNicholas Piggin return; 855d24e80b2SNicholas Piggin } 856d24e80b2SNicholas Piggin 85737f219c8SBruno Larsen (billionai) gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 85837f219c8SBruno Larsen (billionai) } 85937f219c8SBruno Larsen (billionai) #endif 86037f219c8SBruno Larsen (billionai) #endif 86137f219c8SBruno Larsen (billionai) 86237f219c8SBruno Larsen (billionai) /* PowerPC 40x specific registers */ 86337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 864a829cec3SBruno Larsen (billionai) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 86537f219c8SBruno Larsen (billionai) { 866283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 86737f219c8SBruno Larsen (billionai) gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 86837f219c8SBruno Larsen (billionai) } 86937f219c8SBruno Larsen (billionai) 870a829cec3SBruno Larsen (billionai) void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 87137f219c8SBruno Larsen (billionai) { 872283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 87337f219c8SBruno Larsen (billionai) gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 87437f219c8SBruno Larsen (billionai) } 87537f219c8SBruno Larsen (billionai) 876a829cec3SBruno Larsen (billionai) void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 87737f219c8SBruno Larsen (billionai) { 878283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 87937f219c8SBruno Larsen (billionai) gen_store_spr(sprn, cpu_gpr[gprn]); 88037f219c8SBruno Larsen (billionai) gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 88137f219c8SBruno Larsen (billionai) /* We must stop translation as we may have rebooted */ 882d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 88337f219c8SBruno Larsen (billionai) } 88437f219c8SBruno Larsen (billionai) 885a829cec3SBruno Larsen (billionai) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 88637f219c8SBruno Larsen (billionai) { 887283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 88837f219c8SBruno Larsen (billionai) gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 88937f219c8SBruno Larsen (billionai) } 89037f219c8SBruno Larsen (billionai) 891cbd8f17dSCédric Le Goater void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) 892cbd8f17dSCédric Le Goater { 893283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 894cbd8f17dSCédric Le Goater gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); 895cbd8f17dSCédric Le Goater } 896cbd8f17dSCédric Le Goater 897cbd8f17dSCédric Le Goater void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) 898cbd8f17dSCédric Le Goater { 899283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 900cbd8f17dSCédric Le Goater gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); 901cbd8f17dSCédric Le Goater } 902cbd8f17dSCédric Le Goater 903dd69d140SCédric Le Goater void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) 904dd69d140SCédric Le Goater { 905dd69d140SCédric Le Goater TCGv t0 = tcg_temp_new(); 906dd69d140SCédric Le Goater tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); 90747822486SCédric Le Goater gen_helper_store_40x_pid(cpu_env, t0); 908dd69d140SCédric Le Goater } 909dd69d140SCédric Le Goater 910a829cec3SBruno Larsen (billionai) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 91137f219c8SBruno Larsen (billionai) { 912283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 91337f219c8SBruno Larsen (billionai) gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 91437f219c8SBruno Larsen (billionai) } 91537f219c8SBruno Larsen (billionai) 916a829cec3SBruno Larsen (billionai) void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 91737f219c8SBruno Larsen (billionai) { 918283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 91937f219c8SBruno Larsen (billionai) gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 92037f219c8SBruno Larsen (billionai) } 92137f219c8SBruno Larsen (billionai) #endif 92237f219c8SBruno Larsen (billionai) 923328c95fcSCédric Le Goater /* PIR */ 92437f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 925a829cec3SBruno Larsen (billionai) void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 92637f219c8SBruno Larsen (billionai) { 92737f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 92837f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 92937f219c8SBruno Larsen (billionai) gen_store_spr(SPR_PIR, t0); 93037f219c8SBruno Larsen (billionai) } 93137f219c8SBruno Larsen (billionai) #endif 93237f219c8SBruno Larsen (billionai) 93337f219c8SBruno Larsen (billionai) /* SPE specific registers */ 934a829cec3SBruno Larsen (billionai) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 93537f219c8SBruno Larsen (billionai) { 93637f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 93737f219c8SBruno Larsen (billionai) tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 93837f219c8SBruno Larsen (billionai) tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 93937f219c8SBruno Larsen (billionai) } 94037f219c8SBruno Larsen (billionai) 941a829cec3SBruno Larsen (billionai) void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 94237f219c8SBruno Larsen (billionai) { 94337f219c8SBruno Larsen (billionai) TCGv_i32 t0 = tcg_temp_new_i32(); 94437f219c8SBruno Larsen (billionai) tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 94537f219c8SBruno Larsen (billionai) tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 94637f219c8SBruno Larsen (billionai) } 94737f219c8SBruno Larsen (billionai) 94837f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 94937f219c8SBruno Larsen (billionai) /* Callback used to write the exception vector base */ 950a829cec3SBruno Larsen (billionai) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 95137f219c8SBruno Larsen (billionai) { 95237f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 95337f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 95437f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 95537f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 95637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 95737f219c8SBruno Larsen (billionai) } 95837f219c8SBruno Larsen (billionai) 959a829cec3SBruno Larsen (billionai) void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 96037f219c8SBruno Larsen (billionai) { 96137f219c8SBruno Larsen (billionai) int sprn_offs; 96237f219c8SBruno Larsen (billionai) 96337f219c8SBruno Larsen (billionai) if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 96437f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR0; 96537f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 96637f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 96737f219c8SBruno Larsen (billionai) } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 96837f219c8SBruno Larsen (billionai) sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 96937f219c8SBruno Larsen (billionai) } else { 9708e1fedf8SMatheus Ferst qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" 9718e1fedf8SMatheus Ferst " vector 0x%03x\n", sprn); 9728e1fedf8SMatheus Ferst gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 97337f219c8SBruno Larsen (billionai) return; 97437f219c8SBruno Larsen (billionai) } 97537f219c8SBruno Larsen (billionai) 97637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 97737f219c8SBruno Larsen (billionai) tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 97837f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 97937f219c8SBruno Larsen (billionai) tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 98037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 98137f219c8SBruno Larsen (billionai) } 98237f219c8SBruno Larsen (billionai) #endif 98337f219c8SBruno Larsen (billionai) 98437f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 98537f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 986a829cec3SBruno Larsen (billionai) void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 98737f219c8SBruno Larsen (billionai) { 98837f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 98937f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 99037f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 99137f219c8SBruno Larsen (billionai) 99237f219c8SBruno Larsen (billionai) /* 99337f219c8SBruno Larsen (billionai) * Note, the HV=1 PR=0 case is handled earlier by simply using 99437f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 99537f219c8SBruno Larsen (billionai) */ 99637f219c8SBruno Larsen (billionai) 99737f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 99837f219c8SBruno Larsen (billionai) if (ctx->pr) { 99937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_UAMOR); 100037f219c8SBruno Larsen (billionai) } else { 100137f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 100237f219c8SBruno Larsen (billionai) } 100337f219c8SBruno Larsen (billionai) 100437f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 100537f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 100637f219c8SBruno Larsen (billionai) 100737f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 100837f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_AMR); 100937f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 101037f219c8SBruno Larsen (billionai) 101137f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 101237f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 101337f219c8SBruno Larsen (billionai) gen_store_spr(SPR_AMR, t0); 101437f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_AMR); 101537f219c8SBruno Larsen (billionai) } 101637f219c8SBruno Larsen (billionai) 1017a829cec3SBruno Larsen (billionai) void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 101837f219c8SBruno Larsen (billionai) { 101937f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 102037f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 102137f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 102237f219c8SBruno Larsen (billionai) 102337f219c8SBruno Larsen (billionai) /* 102437f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 102537f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 102637f219c8SBruno Larsen (billionai) */ 102737f219c8SBruno Larsen (billionai) 102837f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 102937f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 103037f219c8SBruno Larsen (billionai) 103137f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 103237f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 103337f219c8SBruno Larsen (billionai) 103437f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 103537f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_UAMOR); 103637f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 103737f219c8SBruno Larsen (billionai) 103837f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 103937f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 104037f219c8SBruno Larsen (billionai) gen_store_spr(SPR_UAMOR, t0); 104137f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_UAMOR); 104237f219c8SBruno Larsen (billionai) } 104337f219c8SBruno Larsen (billionai) 1044a829cec3SBruno Larsen (billionai) void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 104537f219c8SBruno Larsen (billionai) { 104637f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 104737f219c8SBruno Larsen (billionai) TCGv t1 = tcg_temp_new(); 104837f219c8SBruno Larsen (billionai) TCGv t2 = tcg_temp_new(); 104937f219c8SBruno Larsen (billionai) 105037f219c8SBruno Larsen (billionai) /* 105137f219c8SBruno Larsen (billionai) * Note, the HV=1 case is handled earlier by simply using 105237f219c8SBruno Larsen (billionai) * spr_write_generic for HV mode in the SPR table 105337f219c8SBruno Larsen (billionai) */ 105437f219c8SBruno Larsen (billionai) 105537f219c8SBruno Larsen (billionai) /* Build insertion mask into t1 based on context */ 105637f219c8SBruno Larsen (billionai) gen_load_spr(t1, SPR_AMOR); 105737f219c8SBruno Larsen (billionai) 105837f219c8SBruno Larsen (billionai) /* Mask new bits into t2 */ 105937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 106037f219c8SBruno Larsen (billionai) 106137f219c8SBruno Larsen (billionai) /* Load AMR and clear new bits in t0 */ 106237f219c8SBruno Larsen (billionai) gen_load_spr(t0, SPR_IAMR); 106337f219c8SBruno Larsen (billionai) tcg_gen_andc_tl(t0, t0, t1); 106437f219c8SBruno Larsen (billionai) 106537f219c8SBruno Larsen (billionai) /* Or'in new bits and write it out */ 106637f219c8SBruno Larsen (billionai) tcg_gen_or_tl(t0, t0, t2); 106737f219c8SBruno Larsen (billionai) gen_store_spr(SPR_IAMR, t0); 106837f219c8SBruno Larsen (billionai) spr_store_dump_spr(SPR_IAMR); 106937f219c8SBruno Larsen (billionai) } 107037f219c8SBruno Larsen (billionai) #endif 107137f219c8SBruno Larsen (billionai) #endif 107237f219c8SBruno Larsen (billionai) 107337f219c8SBruno Larsen (billionai) #ifndef CONFIG_USER_ONLY 1074a829cec3SBruno Larsen (billionai) void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 107537f219c8SBruno Larsen (billionai) { 107637f219c8SBruno Larsen (billionai) gen_helper_fixup_thrm(cpu_env); 107737f219c8SBruno Larsen (billionai) gen_load_spr(cpu_gpr[gprn], sprn); 107837f219c8SBruno Larsen (billionai) spr_load_dump_spr(sprn); 107937f219c8SBruno Larsen (billionai) } 108037f219c8SBruno Larsen (billionai) #endif /* !CONFIG_USER_ONLY */ 108137f219c8SBruno Larsen (billionai) 108237f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1083a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 108437f219c8SBruno Larsen (billionai) { 108537f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 108637f219c8SBruno Larsen (billionai) 108737f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 108837f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 108937f219c8SBruno Larsen (billionai) } 109037f219c8SBruno Larsen (billionai) 1091a829cec3SBruno Larsen (billionai) void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 109237f219c8SBruno Larsen (billionai) { 109337f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 109437f219c8SBruno Larsen (billionai) 109537f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 109637f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 109737f219c8SBruno Larsen (billionai) } 109837f219c8SBruno Larsen (billionai) 1099a829cec3SBruno Larsen (billionai) void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 110037f219c8SBruno Larsen (billionai) { 110137f219c8SBruno Larsen (billionai) TCGv t0 = tcg_temp_new(); 110237f219c8SBruno Larsen (billionai) 110337f219c8SBruno Larsen (billionai) tcg_gen_andi_tl(t0, cpu_gpr[gprn], 110437f219c8SBruno Larsen (billionai) ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 110537f219c8SBruno Larsen (billionai) gen_store_spr(sprn, t0); 110637f219c8SBruno Larsen (billionai) } 110737f219c8SBruno Larsen (billionai) 1108a829cec3SBruno Larsen (billionai) void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 110937f219c8SBruno Larsen (billionai) { 111037f219c8SBruno Larsen (billionai) gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 111137f219c8SBruno Larsen (billionai) } 111237f219c8SBruno Larsen (billionai) 1113a829cec3SBruno Larsen (billionai) void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 111437f219c8SBruno Larsen (billionai) { 11157058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(sprn); 111637f219c8SBruno Larsen (billionai) gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 111737f219c8SBruno Larsen (billionai) } 11187058ff52SRichard Henderson 1119a829cec3SBruno Larsen (billionai) void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 112037f219c8SBruno Larsen (billionai) { 112137f219c8SBruno Larsen (billionai) gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 112237f219c8SBruno Larsen (billionai) } 11237058ff52SRichard Henderson 1124a829cec3SBruno Larsen (billionai) void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 112537f219c8SBruno Larsen (billionai) { 112637f219c8SBruno Larsen (billionai) gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 112737f219c8SBruno Larsen (billionai) } 112837f219c8SBruno Larsen (billionai) 112937f219c8SBruno Larsen (billionai) #endif 113037f219c8SBruno Larsen (billionai) 113137f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1132a829cec3SBruno Larsen (billionai) void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 113337f219c8SBruno Larsen (billionai) { 113437f219c8SBruno Larsen (billionai) TCGv val = tcg_temp_new(); 113537f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 113637f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS3, val); 113737f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 113837f219c8SBruno Larsen (billionai) gen_store_spr(SPR_BOOKE_MAS7, val); 113937f219c8SBruno Larsen (billionai) } 114037f219c8SBruno Larsen (billionai) 1141a829cec3SBruno Larsen (billionai) void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 114237f219c8SBruno Larsen (billionai) { 114337f219c8SBruno Larsen (billionai) TCGv mas7 = tcg_temp_new(); 114437f219c8SBruno Larsen (billionai) TCGv mas3 = tcg_temp_new(); 114537f219c8SBruno Larsen (billionai) gen_load_spr(mas7, SPR_BOOKE_MAS7); 114637f219c8SBruno Larsen (billionai) tcg_gen_shli_tl(mas7, mas7, 32); 114737f219c8SBruno Larsen (billionai) gen_load_spr(mas3, SPR_BOOKE_MAS3); 114837f219c8SBruno Larsen (billionai) tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 114937f219c8SBruno Larsen (billionai) } 115037f219c8SBruno Larsen (billionai) 115137f219c8SBruno Larsen (billionai) #endif 115237f219c8SBruno Larsen (billionai) 115337f219c8SBruno Larsen (billionai) #ifdef TARGET_PPC64 115437f219c8SBruno Larsen (billionai) static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 115537f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 115637f219c8SBruno Larsen (billionai) { 11577058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11587058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11597058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 116037f219c8SBruno Larsen (billionai) 116137f219c8SBruno Larsen (billionai) gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 116237f219c8SBruno Larsen (billionai) } 116337f219c8SBruno Larsen (billionai) 116437f219c8SBruno Larsen (billionai) static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 116537f219c8SBruno Larsen (billionai) int bit, int sprn, int cause) 116637f219c8SBruno Larsen (billionai) { 11677058ff52SRichard Henderson TCGv_i32 t1 = tcg_constant_i32(bit); 11687058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(sprn); 11697058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(cause); 117037f219c8SBruno Larsen (billionai) 117137f219c8SBruno Larsen (billionai) gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 117237f219c8SBruno Larsen (billionai) } 117337f219c8SBruno Larsen (billionai) 1174a829cec3SBruno Larsen (billionai) void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 117537f219c8SBruno Larsen (billionai) { 117637f219c8SBruno Larsen (billionai) TCGv spr_up = tcg_temp_new(); 117737f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 117837f219c8SBruno Larsen (billionai) 117937f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118037f219c8SBruno Larsen (billionai) tcg_gen_shri_tl(spr_up, spr, 32); 118137f219c8SBruno Larsen (billionai) tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 118237f219c8SBruno Larsen (billionai) } 118337f219c8SBruno Larsen (billionai) 1184a829cec3SBruno Larsen (billionai) void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 118537f219c8SBruno Larsen (billionai) { 118637f219c8SBruno Larsen (billionai) TCGv spr = tcg_temp_new(); 118737f219c8SBruno Larsen (billionai) 118837f219c8SBruno Larsen (billionai) gen_load_spr(spr, sprn - 1); 118937f219c8SBruno Larsen (billionai) tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 119037f219c8SBruno Larsen (billionai) gen_store_spr(sprn - 1, spr); 119137f219c8SBruno Larsen (billionai) } 119237f219c8SBruno Larsen (billionai) 119337f219c8SBruno Larsen (billionai) #if !defined(CONFIG_USER_ONLY) 1194a829cec3SBruno Larsen (billionai) void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 119537f219c8SBruno Larsen (billionai) { 119637f219c8SBruno Larsen (billionai) TCGv hmer = tcg_temp_new(); 119737f219c8SBruno Larsen (billionai) 119837f219c8SBruno Larsen (billionai) gen_load_spr(hmer, sprn); 119937f219c8SBruno Larsen (billionai) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 120037f219c8SBruno Larsen (billionai) gen_store_spr(sprn, hmer); 120137f219c8SBruno Larsen (billionai) spr_store_dump_spr(sprn); 120237f219c8SBruno Larsen (billionai) } 120337f219c8SBruno Larsen (billionai) 1204b25f2ffaSNicholas Piggin void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) 1205b25f2ffaSNicholas Piggin { 1206b25f2ffaSNicholas Piggin gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); 1207b25f2ffaSNicholas Piggin } 1208b25f2ffaSNicholas Piggin 1209b25f2ffaSNicholas Piggin void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) 1210b25f2ffaSNicholas Piggin { 1211b25f2ffaSNicholas Piggin gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); 1212b25f2ffaSNicholas Piggin } 1213b25f2ffaSNicholas Piggin 1214a829cec3SBruno Larsen (billionai) void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 121537f219c8SBruno Larsen (billionai) { 1216c32654afSNicholas Piggin translator_io_start(&ctx->base); 121737f219c8SBruno Larsen (billionai) gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 121837f219c8SBruno Larsen (billionai) } 121937f219c8SBruno Larsen (billionai) #endif /* !defined(CONFIG_USER_ONLY) */ 122037f219c8SBruno Larsen (billionai) 1221a829cec3SBruno Larsen (billionai) void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 122237f219c8SBruno Larsen (billionai) { 122337f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 122437f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 122537f219c8SBruno Larsen (billionai) } 122637f219c8SBruno Larsen (billionai) 1227a829cec3SBruno Larsen (billionai) void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 122837f219c8SBruno Larsen (billionai) { 122937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 123037f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 123137f219c8SBruno Larsen (billionai) } 123237f219c8SBruno Larsen (billionai) 1233a829cec3SBruno Larsen (billionai) void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 123437f219c8SBruno Larsen (billionai) { 123537f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 123637f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 123737f219c8SBruno Larsen (billionai) } 123837f219c8SBruno Larsen (billionai) 1239a829cec3SBruno Larsen (billionai) void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 124037f219c8SBruno Larsen (billionai) { 124137f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124237f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 124337f219c8SBruno Larsen (billionai) } 124437f219c8SBruno Larsen (billionai) 1245a829cec3SBruno Larsen (billionai) void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 124637f219c8SBruno Larsen (billionai) { 124737f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 124837f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 124937f219c8SBruno Larsen (billionai) } 125037f219c8SBruno Larsen (billionai) 1251a829cec3SBruno Larsen (billionai) void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 125237f219c8SBruno Larsen (billionai) { 125337f219c8SBruno Larsen (billionai) gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 125437f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 125537f219c8SBruno Larsen (billionai) } 125637f219c8SBruno Larsen (billionai) 1257a829cec3SBruno Larsen (billionai) void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 125837f219c8SBruno Larsen (billionai) { 125937f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126037f219c8SBruno Larsen (billionai) spr_read_generic(ctx, gprn, sprn); 126137f219c8SBruno Larsen (billionai) } 126237f219c8SBruno Larsen (billionai) 1263a829cec3SBruno Larsen (billionai) void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 126437f219c8SBruno Larsen (billionai) { 126537f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 126637f219c8SBruno Larsen (billionai) spr_write_generic(ctx, sprn, gprn); 126737f219c8SBruno Larsen (billionai) } 126837f219c8SBruno Larsen (billionai) 1269a829cec3SBruno Larsen (billionai) void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 127037f219c8SBruno Larsen (billionai) { 127137f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127237f219c8SBruno Larsen (billionai) spr_read_prev_upper32(ctx, gprn, sprn); 127337f219c8SBruno Larsen (billionai) } 127437f219c8SBruno Larsen (billionai) 1275a829cec3SBruno Larsen (billionai) void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 127637f219c8SBruno Larsen (billionai) { 127737f219c8SBruno Larsen (billionai) gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 127837f219c8SBruno Larsen (billionai) spr_write_prev_upper32(ctx, sprn, gprn); 127937f219c8SBruno Larsen (billionai) } 1280395b5d5bSNicholas Miehlbradt 1281395b5d5bSNicholas Miehlbradt void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) 1282395b5d5bSNicholas Miehlbradt { 1283395b5d5bSNicholas Miehlbradt TCGv t0 = tcg_temp_new(); 1284395b5d5bSNicholas Miehlbradt 1285395b5d5bSNicholas Miehlbradt /* 1286395b5d5bSNicholas Miehlbradt * Access to the (H)DEXCR in problem state is done using separated 1287395b5d5bSNicholas Miehlbradt * SPR indexes which are 16 below the SPR indexes which have full 1288395b5d5bSNicholas Miehlbradt * access to the (H)DEXCR in privileged state. Problem state can 1289395b5d5bSNicholas Miehlbradt * only read bits 32:63, bits 0:31 return 0. 1290395b5d5bSNicholas Miehlbradt * 1291395b5d5bSNicholas Miehlbradt * See section 9.3.1-9.3.2 of PowerISA v3.1B 1292395b5d5bSNicholas Miehlbradt */ 1293395b5d5bSNicholas Miehlbradt 1294395b5d5bSNicholas Miehlbradt gen_load_spr(t0, sprn + 16); 1295395b5d5bSNicholas Miehlbradt tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); 1296395b5d5bSNicholas Miehlbradt } 129737f219c8SBruno Larsen (billionai) #endif 129837f219c8SBruno Larsen (billionai) 1299fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 1300fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 1301fcf5ef2aSThomas Huth 1302fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 1303fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 1304fcf5ef2aSThomas Huth 1305fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 1306fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 1307fcf5ef2aSThomas Huth 1308fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 1309fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 1310fcf5ef2aSThomas Huth 1311fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 1312fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 1313fcf5ef2aSThomas Huth 1314fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 1315fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 1316fcf5ef2aSThomas Huth 1317fcf5ef2aSThomas Huth typedef struct opcode_t { 1318fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 1319fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 1320fcf5ef2aSThomas Huth unsigned char pad[4]; 1321fcf5ef2aSThomas Huth #endif 1322fcf5ef2aSThomas Huth opc_handler_t handler; 1323fcf5ef2aSThomas Huth const char *oname; 1324fcf5ef2aSThomas Huth } opcode_t; 1325fcf5ef2aSThomas Huth 13269f0cf041SMatheus Ferst static void gen_priv_opc(DisasContext *ctx) 13279f0cf041SMatheus Ferst { 13289f0cf041SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 13299f0cf041SMatheus Ferst } 13309f0cf041SMatheus Ferst 1331fcf5ef2aSThomas Huth /* Helpers for priv. check */ 13329f0cf041SMatheus Ferst #define GEN_PRIV(CTX) \ 1333fcf5ef2aSThomas Huth do { \ 13349f0cf041SMatheus Ferst gen_priv_opc(CTX); return; \ 1335fcf5ef2aSThomas Huth } while (0) 1336fcf5ef2aSThomas Huth 1337fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 13389f0cf041SMatheus Ferst #define CHK_HV(CTX) GEN_PRIV(CTX) 13399f0cf041SMatheus Ferst #define CHK_SV(CTX) GEN_PRIV(CTX) 13409f0cf041SMatheus Ferst #define CHK_HVRM(CTX) GEN_PRIV(CTX) 1341fcf5ef2aSThomas Huth #else 13429f0cf041SMatheus Ferst #define CHK_HV(CTX) \ 1343fcf5ef2aSThomas Huth do { \ 1344fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) {\ 13459f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1346fcf5ef2aSThomas Huth } \ 1347fcf5ef2aSThomas Huth } while (0) 13489f0cf041SMatheus Ferst #define CHK_SV(CTX) \ 1349fcf5ef2aSThomas Huth do { \ 1350fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 13519f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1352fcf5ef2aSThomas Huth } \ 1353fcf5ef2aSThomas Huth } while (0) 13549f0cf041SMatheus Ferst #define CHK_HVRM(CTX) \ 1355fcf5ef2aSThomas Huth do { \ 1356fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 13579f0cf041SMatheus Ferst GEN_PRIV(CTX); \ 1358fcf5ef2aSThomas Huth } \ 1359fcf5ef2aSThomas Huth } while (0) 1360fcf5ef2aSThomas Huth #endif 1361fcf5ef2aSThomas Huth 13629f0cf041SMatheus Ferst #define CHK_NONE(CTX) 1363fcf5ef2aSThomas Huth 1364fcf5ef2aSThomas Huth /*****************************************************************************/ 1365fcf5ef2aSThomas Huth /* PowerPC instructions table */ 1366fcf5ef2aSThomas Huth 1367fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 1368fcf5ef2aSThomas Huth { \ 1369fcf5ef2aSThomas Huth .opc1 = op1, \ 1370fcf5ef2aSThomas Huth .opc2 = op2, \ 1371fcf5ef2aSThomas Huth .opc3 = op3, \ 1372fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1373fcf5ef2aSThomas Huth .handler = { \ 1374fcf5ef2aSThomas Huth .inval1 = invl, \ 1375fcf5ef2aSThomas Huth .type = _typ, \ 1376fcf5ef2aSThomas Huth .type2 = _typ2, \ 1377fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1378fcf5ef2aSThomas Huth }, \ 1379fcf5ef2aSThomas Huth .oname = stringify(name), \ 1380fcf5ef2aSThomas Huth } 1381fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 1382fcf5ef2aSThomas Huth { \ 1383fcf5ef2aSThomas Huth .opc1 = op1, \ 1384fcf5ef2aSThomas Huth .opc2 = op2, \ 1385fcf5ef2aSThomas Huth .opc3 = op3, \ 1386fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1387fcf5ef2aSThomas Huth .handler = { \ 1388fcf5ef2aSThomas Huth .inval1 = invl1, \ 1389fcf5ef2aSThomas Huth .inval2 = invl2, \ 1390fcf5ef2aSThomas Huth .type = _typ, \ 1391fcf5ef2aSThomas Huth .type2 = _typ2, \ 1392fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1393fcf5ef2aSThomas Huth }, \ 1394fcf5ef2aSThomas Huth .oname = stringify(name), \ 1395fcf5ef2aSThomas Huth } 1396fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 1397fcf5ef2aSThomas Huth { \ 1398fcf5ef2aSThomas Huth .opc1 = op1, \ 1399fcf5ef2aSThomas Huth .opc2 = op2, \ 1400fcf5ef2aSThomas Huth .opc3 = op3, \ 1401fcf5ef2aSThomas Huth .opc4 = 0xff, \ 1402fcf5ef2aSThomas Huth .handler = { \ 1403fcf5ef2aSThomas Huth .inval1 = invl, \ 1404fcf5ef2aSThomas Huth .type = _typ, \ 1405fcf5ef2aSThomas Huth .type2 = _typ2, \ 1406fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1407fcf5ef2aSThomas Huth }, \ 1408fcf5ef2aSThomas Huth .oname = onam, \ 1409fcf5ef2aSThomas Huth } 1410fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 1411fcf5ef2aSThomas Huth { \ 1412fcf5ef2aSThomas Huth .opc1 = op1, \ 1413fcf5ef2aSThomas Huth .opc2 = op2, \ 1414fcf5ef2aSThomas Huth .opc3 = op3, \ 1415fcf5ef2aSThomas Huth .opc4 = op4, \ 1416fcf5ef2aSThomas Huth .handler = { \ 1417fcf5ef2aSThomas Huth .inval1 = invl, \ 1418fcf5ef2aSThomas Huth .type = _typ, \ 1419fcf5ef2aSThomas Huth .type2 = _typ2, \ 1420fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1421fcf5ef2aSThomas Huth }, \ 1422fcf5ef2aSThomas Huth .oname = stringify(name), \ 1423fcf5ef2aSThomas Huth } 1424fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 1425fcf5ef2aSThomas Huth { \ 1426fcf5ef2aSThomas Huth .opc1 = op1, \ 1427fcf5ef2aSThomas Huth .opc2 = op2, \ 1428fcf5ef2aSThomas Huth .opc3 = op3, \ 1429fcf5ef2aSThomas Huth .opc4 = op4, \ 1430fcf5ef2aSThomas Huth .handler = { \ 1431fcf5ef2aSThomas Huth .inval1 = invl, \ 1432fcf5ef2aSThomas Huth .type = _typ, \ 1433fcf5ef2aSThomas Huth .type2 = _typ2, \ 1434fcf5ef2aSThomas Huth .handler = &gen_##name, \ 1435fcf5ef2aSThomas Huth }, \ 1436fcf5ef2aSThomas Huth .oname = onam, \ 1437fcf5ef2aSThomas Huth } 1438fcf5ef2aSThomas Huth 1439fcf5ef2aSThomas Huth /* Invalid instruction */ 1440fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 1441fcf5ef2aSThomas Huth { 1442fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 1443fcf5ef2aSThomas Huth } 1444fcf5ef2aSThomas Huth 1445fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 1446fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 1447fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 1448fcf5ef2aSThomas Huth .type = PPC_NONE, 1449fcf5ef2aSThomas Huth .type2 = PPC_NONE, 1450fcf5ef2aSThomas Huth .handler = gen_invalid, 1451fcf5ef2aSThomas Huth }; 1452fcf5ef2aSThomas Huth 1453fcf5ef2aSThomas Huth /*** Integer comparison ***/ 1454fcf5ef2aSThomas Huth 1455fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 1456fcf5ef2aSThomas Huth { 1457fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1458b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 1459b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 1460fcf5ef2aSThomas Huth 1461b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 1462b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 1463efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), 1464efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1465b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 1466efe843d8SDavid Gibson tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), 1467efe843d8SDavid Gibson t0, arg0, arg1, t1, t0); 1468b62b3686Spbonzini@redhat.com 1469b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 1470fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 1471b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 1472fcf5ef2aSThomas Huth } 1473fcf5ef2aSThomas Huth 1474fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 1475fcf5ef2aSThomas Huth { 14767058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1477fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 1478fcf5ef2aSThomas Huth } 1479fcf5ef2aSThomas Huth 1480fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 1481fcf5ef2aSThomas Huth { 1482fcf5ef2aSThomas Huth TCGv t0, t1; 1483fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1484fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1485fcf5ef2aSThomas Huth if (s) { 1486fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 1487fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 1488fcf5ef2aSThomas Huth } else { 1489fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 1490fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 1491fcf5ef2aSThomas Huth } 1492fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 1493fcf5ef2aSThomas Huth } 1494fcf5ef2aSThomas Huth 1495fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 1496fcf5ef2aSThomas Huth { 14977058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(arg1); 1498fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 1499fcf5ef2aSThomas Huth } 1500fcf5ef2aSThomas Huth 1501fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 1502fcf5ef2aSThomas Huth { 1503fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1504fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 1505fcf5ef2aSThomas Huth } else { 1506fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 1507fcf5ef2aSThomas Huth } 1508fcf5ef2aSThomas Huth } 1509fcf5ef2aSThomas Huth 1510fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 1511fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 1512fcf5ef2aSThomas Huth { 1513fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 1514fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 1515fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 1516fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 1517fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 1518fcf5ef2aSThomas Huth 1519fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 1520fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 1521fcf5ef2aSThomas Huth 1522fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 1523fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1524fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1525fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1526fcf5ef2aSThomas Huth 1527fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1528fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1529fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 1530fcf5ef2aSThomas Huth 1531fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 1532fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1533fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 1534fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 1535fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 1536fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 1537fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 1538fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 1539fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 1540fcf5ef2aSThomas Huth } 1541efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 1542fcf5ef2aSThomas Huth } 1543fcf5ef2aSThomas Huth 1544fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1545fcf5ef2aSThomas Huth /* cmpeqb */ 1546fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 1547fcf5ef2aSThomas Huth { 1548fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1549fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1550fcf5ef2aSThomas Huth } 1551fcf5ef2aSThomas Huth #endif 1552fcf5ef2aSThomas Huth 1553fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 1554fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 1555fcf5ef2aSThomas Huth { 1556fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 1557fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 1558fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1559fcf5ef2aSThomas Huth TCGv zr; 1560fcf5ef2aSThomas Huth 1561fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 1562fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 1563fcf5ef2aSThomas Huth 15647058ff52SRichard Henderson zr = tcg_constant_tl(0); 1565fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 1566fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 1567fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1568fcf5ef2aSThomas Huth } 1569fcf5ef2aSThomas Huth 1570fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 1571fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 1572fcf5ef2aSThomas Huth { 1573fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 1574fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1575fcf5ef2aSThomas Huth } 1576fcf5ef2aSThomas Huth 1577fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 1578fcf5ef2aSThomas Huth 1579fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 1580fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 1581fcf5ef2aSThomas Huth { 1582fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1583fcf5ef2aSThomas Huth 1584fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 1585fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 1586fcf5ef2aSThomas Huth if (sub) { 1587fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 1588fcf5ef2aSThomas Huth } else { 1589fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 1590fcf5ef2aSThomas Huth } 1591fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1592dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 1593dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1594dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 1595fcf5ef2aSThomas Huth } 1596dc0ad844SNikunj A Dadhania } else { 1597dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 1598dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 1599dc0ad844SNikunj A Dadhania } 160038a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 1601dc0ad844SNikunj A Dadhania } 1602fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1603fcf5ef2aSThomas Huth } 1604fcf5ef2aSThomas Huth 16056b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 16066b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 16074c5920afSSuraj Jitindar Singh TCGv ca32, int sub) 16086b10d008SNikunj A Dadhania { 16096b10d008SNikunj A Dadhania TCGv t0; 16106b10d008SNikunj A Dadhania 16116b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 16126b10d008SNikunj A Dadhania return; 16136b10d008SNikunj A Dadhania } 16146b10d008SNikunj A Dadhania 16156b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 161633903d0aSNikunj A Dadhania if (sub) { 161733903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 161833903d0aSNikunj A Dadhania } else { 16196b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 162033903d0aSNikunj A Dadhania } 16216b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 16224c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca32, t0, 32, 1); 16236b10d008SNikunj A Dadhania } 16246b10d008SNikunj A Dadhania 1625fcf5ef2aSThomas Huth /* Common add function */ 1626fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 16274c5920afSSuraj Jitindar Singh TCGv arg2, TCGv ca, TCGv ca32, 16284c5920afSSuraj Jitindar Singh bool add_ca, bool compute_ca, 1629fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1630fcf5ef2aSThomas Huth { 1631fcf5ef2aSThomas Huth TCGv t0 = ret; 1632fcf5ef2aSThomas Huth 1633fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1634fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1635fcf5ef2aSThomas Huth } 1636fcf5ef2aSThomas Huth 1637fcf5ef2aSThomas Huth if (compute_ca) { 1638fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1639efe843d8SDavid Gibson /* 1640efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 1641efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 1642efe843d8SDavid Gibson * produce the carry into bit 32. 1643efe843d8SDavid Gibson */ 1644fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1645fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 1646fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1647fcf5ef2aSThomas Huth if (add_ca) { 16484c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1649fcf5ef2aSThomas Huth } 16504c5920afSSuraj Jitindar Singh tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ 16514c5920afSSuraj Jitindar Singh tcg_gen_extract_tl(ca, ca, 32, 1); 16526b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 16534c5920afSSuraj Jitindar Singh tcg_gen_mov_tl(ca32, ca); 16546b10d008SNikunj A Dadhania } 1655fcf5ef2aSThomas Huth } else { 16567058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 1657fcf5ef2aSThomas Huth if (add_ca) { 16584c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); 16594c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); 1660fcf5ef2aSThomas Huth } else { 16614c5920afSSuraj Jitindar Singh tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); 1662fcf5ef2aSThomas Huth } 16634c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); 1664fcf5ef2aSThomas Huth } 1665fcf5ef2aSThomas Huth } else { 1666fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 1667fcf5ef2aSThomas Huth if (add_ca) { 16684c5920afSSuraj Jitindar Singh tcg_gen_add_tl(t0, t0, ca); 1669fcf5ef2aSThomas Huth } 1670fcf5ef2aSThomas Huth } 1671fcf5ef2aSThomas Huth 1672fcf5ef2aSThomas Huth if (compute_ov) { 1673fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 1674fcf5ef2aSThomas Huth } 1675fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1676fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1677fcf5ef2aSThomas Huth } 1678fcf5ef2aSThomas Huth 167911f4e8f8SRichard Henderson if (t0 != ret) { 1680fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1681fcf5ef2aSThomas Huth } 1682fcf5ef2aSThomas Huth } 1683fcf5ef2aSThomas Huth /* Add functions with two operands */ 16844c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ 1685fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1686fcf5ef2aSThomas Huth { \ 1687fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1688fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 16894c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1690fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1691fcf5ef2aSThomas Huth } 1692fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 16934c5920afSSuraj Jitindar Singh #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ 1694fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1695fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1696fcf5ef2aSThomas Huth { \ 16977058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 1698fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 1699fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 17004c5920afSSuraj Jitindar Singh ca, glue(ca, 32), \ 1701fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1702fcf5ef2aSThomas Huth } 1703fcf5ef2aSThomas Huth 1704fcf5ef2aSThomas Huth /* add add. addo addo. */ 17054c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) 17064c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) 1707fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 17084c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) 17094c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) 1710fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 17114c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) 17124c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) 1713fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 17144c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) 17154c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) 17164c5920afSSuraj Jitindar Singh /* addex */ 17174c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); 1718fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 17194c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) 17204c5920afSSuraj Jitindar Singh GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) 1721fcf5ef2aSThomas Huth /* addic addic.*/ 1722fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 1723fcf5ef2aSThomas Huth { 17247058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 1725fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 17264c5920afSSuraj Jitindar Singh c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); 1727fcf5ef2aSThomas Huth } 1728fcf5ef2aSThomas Huth 1729fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 1730fcf5ef2aSThomas Huth { 1731fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 1732fcf5ef2aSThomas Huth } 1733fcf5ef2aSThomas Huth 1734fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 1735fcf5ef2aSThomas Huth { 1736fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 1737fcf5ef2aSThomas Huth } 1738fcf5ef2aSThomas Huth 1739fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1740fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1741fcf5ef2aSThomas Huth { 1742fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1743fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1744fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1745fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1746fcf5ef2aSThomas Huth 1747fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1748fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1749fcf5ef2aSThomas Huth if (sign) { 1750fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1751fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1752fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1753fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1754fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1755fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1756fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1757fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1758fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1759fcf5ef2aSThomas Huth } else { 1760fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1761fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1762fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1763fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1764fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1765fcf5ef2aSThomas Huth } 1766fcf5ef2aSThomas Huth if (compute_ov) { 1767fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1768c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1769c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1770c44027ffSNikunj A Dadhania } 1771fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1772fcf5ef2aSThomas Huth } 1773fcf5ef2aSThomas Huth 1774efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1775fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1776fcf5ef2aSThomas Huth } 1777efe843d8SDavid Gibson } 1778fcf5ef2aSThomas Huth /* Div functions */ 1779fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1780fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1781fcf5ef2aSThomas Huth { \ 1782fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1783fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1784fcf5ef2aSThomas Huth sign, compute_ov); \ 1785fcf5ef2aSThomas Huth } 1786fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1787fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1788fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1789fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1790fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1791fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1792fcf5ef2aSThomas Huth 1793fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1794fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1795fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1796fcf5ef2aSThomas Huth { \ 17977058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ 1798fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1799fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1800fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1801fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1802fcf5ef2aSThomas Huth } \ 1803fcf5ef2aSThomas Huth } 1804fcf5ef2aSThomas Huth 1805fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1806fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1807fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1808fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1809fcf5ef2aSThomas Huth 1810fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1811fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1812fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1813fcf5ef2aSThomas Huth { 1814fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1815fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1816fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1817fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1818fcf5ef2aSThomas Huth 1819fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1820fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1821fcf5ef2aSThomas Huth if (sign) { 1822fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1823fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1824fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1825fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1826fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1827fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1828fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1829fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1830fcf5ef2aSThomas Huth } else { 1831fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1832fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1833fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1834fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1835fcf5ef2aSThomas Huth } 1836fcf5ef2aSThomas Huth if (compute_ov) { 1837fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1838c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1839c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1840c44027ffSNikunj A Dadhania } 1841fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1842fcf5ef2aSThomas Huth } 1843fcf5ef2aSThomas Huth 1844efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1845fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1846fcf5ef2aSThomas Huth } 1847efe843d8SDavid Gibson } 1848fcf5ef2aSThomas Huth 1849fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1850fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1851fcf5ef2aSThomas Huth { \ 1852fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1853fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1854fcf5ef2aSThomas Huth sign, compute_ov); \ 1855fcf5ef2aSThomas Huth } 1856c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1857fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1858fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1859c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1860fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1861fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1862fcf5ef2aSThomas Huth 1863fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1864fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1865fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1866fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1867fcf5ef2aSThomas Huth #endif 1868fcf5ef2aSThomas Huth 1869fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1870fcf5ef2aSThomas Huth TCGv arg2, int sign) 1871fcf5ef2aSThomas Huth { 1872fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1873fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1874fcf5ef2aSThomas Huth 1875fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1876fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1877fcf5ef2aSThomas Huth if (sign) { 1878fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1879fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1880fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1881fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1882fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1883fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1884fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1885fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1886fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1887fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1888fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1889fcf5ef2aSThomas Huth } else { 18907058ff52SRichard Henderson TCGv_i32 t2 = tcg_constant_i32(1); 18917058ff52SRichard Henderson TCGv_i32 t3 = tcg_constant_i32(0); 1892fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1893a253231fSRichard Henderson tcg_gen_remu_i32(t0, t0, t1); 1894a253231fSRichard Henderson tcg_gen_extu_i32_tl(ret, t0); 1895fcf5ef2aSThomas Huth } 1896fcf5ef2aSThomas Huth } 1897fcf5ef2aSThomas Huth 1898fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1899fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1900fcf5ef2aSThomas Huth { \ 1901fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1902fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1903fcf5ef2aSThomas Huth sign); \ 1904fcf5ef2aSThomas Huth } 1905fcf5ef2aSThomas Huth 1906fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1907fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1908fcf5ef2aSThomas Huth 1909fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1910fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1911fcf5ef2aSThomas Huth TCGv arg2, int sign) 1912fcf5ef2aSThomas Huth { 1913fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1914fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1915fcf5ef2aSThomas Huth 1916fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1917fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1918fcf5ef2aSThomas Huth if (sign) { 1919fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1920fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1921fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1922fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1923fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1924fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1925fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1926fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1927fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1928fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1929fcf5ef2aSThomas Huth } else { 19307058ff52SRichard Henderson TCGv_i64 t2 = tcg_constant_i64(1); 19317058ff52SRichard Henderson TCGv_i64 t3 = tcg_constant_i64(0); 1932fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1933fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1934fcf5ef2aSThomas Huth } 1935fcf5ef2aSThomas Huth } 1936fcf5ef2aSThomas Huth 1937fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1938fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1939fcf5ef2aSThomas Huth { \ 1940fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1941fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1942fcf5ef2aSThomas Huth sign); \ 1943fcf5ef2aSThomas Huth } 1944fcf5ef2aSThomas Huth 1945fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1946fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1947fcf5ef2aSThomas Huth #endif 1948fcf5ef2aSThomas Huth 1949fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1950fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1951fcf5ef2aSThomas Huth { 1952fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1953fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1954fcf5ef2aSThomas Huth 1955fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1956fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1957fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1958fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1959efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1960fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1961fcf5ef2aSThomas Huth } 1962efe843d8SDavid Gibson } 1963fcf5ef2aSThomas Huth 1964fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1965fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1966fcf5ef2aSThomas Huth { 1967fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1968fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1969fcf5ef2aSThomas Huth 1970fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1971fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1972fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1973fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1974efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1975fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1976fcf5ef2aSThomas Huth } 1977efe843d8SDavid Gibson } 1978fcf5ef2aSThomas Huth 1979fcf5ef2aSThomas Huth /* mullw mullw. */ 1980fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1981fcf5ef2aSThomas Huth { 1982fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1983fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1984fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1985fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1986fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1987fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1988fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1989fcf5ef2aSThomas Huth #else 1990fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1991fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1992fcf5ef2aSThomas Huth #endif 1993efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 1994fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1995fcf5ef2aSThomas Huth } 1996efe843d8SDavid Gibson } 1997fcf5ef2aSThomas Huth 1998fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1999fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 2000fcf5ef2aSThomas Huth { 2001fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2002fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2003fcf5ef2aSThomas Huth 2004fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 2005fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 2006fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 2007fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2008fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 2009fcf5ef2aSThomas Huth #else 2010fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 2011fcf5ef2aSThomas Huth #endif 2012fcf5ef2aSThomas Huth 2013fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 2014fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 2015fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 201661aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 201761aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 201861aa9a69SNikunj A Dadhania } 2019fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2020fcf5ef2aSThomas Huth 2021efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2022fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2023fcf5ef2aSThomas Huth } 2024efe843d8SDavid Gibson } 2025fcf5ef2aSThomas Huth 2026fcf5ef2aSThomas Huth /* mulli */ 2027fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 2028fcf5ef2aSThomas Huth { 2029fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2030fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 2031fcf5ef2aSThomas Huth } 2032fcf5ef2aSThomas Huth 2033fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2034fcf5ef2aSThomas Huth /* mulhd mulhd. */ 2035fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 2036fcf5ef2aSThomas Huth { 2037fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2038fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2039fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2040fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2041fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2042fcf5ef2aSThomas Huth } 2043fcf5ef2aSThomas Huth } 2044fcf5ef2aSThomas Huth 2045fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 2046fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 2047fcf5ef2aSThomas Huth { 2048fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 2049fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 2050fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2051fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2052fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2053fcf5ef2aSThomas Huth } 2054fcf5ef2aSThomas Huth } 2055fcf5ef2aSThomas Huth 2056fcf5ef2aSThomas Huth /* mulld mulld. */ 2057fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 2058fcf5ef2aSThomas Huth { 2059fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2060fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2061efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2062fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2063fcf5ef2aSThomas Huth } 2064efe843d8SDavid Gibson } 2065fcf5ef2aSThomas Huth 2066fcf5ef2aSThomas Huth /* mulldo mulldo. */ 2067fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 2068fcf5ef2aSThomas Huth { 2069fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2070fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 2071fcf5ef2aSThomas Huth 2072fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 2073fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 2074fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 2075fcf5ef2aSThomas Huth 2076fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 2077fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 207861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 207961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 208061aa9a69SNikunj A Dadhania } 2081fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 2082fcf5ef2aSThomas Huth 2083fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2084fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 2085fcf5ef2aSThomas Huth } 2086fcf5ef2aSThomas Huth } 2087fcf5ef2aSThomas Huth #endif 2088fcf5ef2aSThomas Huth 2089fcf5ef2aSThomas Huth /* Common subf function */ 2090fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 2091fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 2092fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 2093fcf5ef2aSThomas Huth { 2094fcf5ef2aSThomas Huth TCGv t0 = ret; 2095fcf5ef2aSThomas Huth 2096fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 2097fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2098fcf5ef2aSThomas Huth } 2099fcf5ef2aSThomas Huth 2100fcf5ef2aSThomas Huth if (compute_ca) { 2101fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 2102fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2103efe843d8SDavid Gibson /* 2104efe843d8SDavid Gibson * Caution: a non-obvious corner case of the spec is that 2105efe843d8SDavid Gibson * we must produce the *entire* 64-bit addition, but 2106efe843d8SDavid Gibson * produce the carry into bit 32. 2107efe843d8SDavid Gibson */ 2108fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 2109fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2110fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 2111fcf5ef2aSThomas Huth if (add_ca) { 2112fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 2113fcf5ef2aSThomas Huth } else { 2114fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 2115fcf5ef2aSThomas Huth } 2116fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 2117fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 2118fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 2119e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 212033903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 212133903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 212233903d0aSNikunj A Dadhania } 2123fcf5ef2aSThomas Huth } else if (add_ca) { 2124fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 2125fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 21267058ff52SRichard Henderson zero = tcg_constant_tl(0); 2127fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 2128fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 21294c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); 2130fcf5ef2aSThomas Huth } else { 2131fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 2132fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 21334c5920afSSuraj Jitindar Singh gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); 2134fcf5ef2aSThomas Huth } 2135fcf5ef2aSThomas Huth } else if (add_ca) { 2136efe843d8SDavid Gibson /* 2137efe843d8SDavid Gibson * Since we're ignoring carry-out, we can simplify the 2138efe843d8SDavid Gibson * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. 2139efe843d8SDavid Gibson */ 2140fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2141fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 2142fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 2143fcf5ef2aSThomas Huth } else { 2144fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 2145fcf5ef2aSThomas Huth } 2146fcf5ef2aSThomas Huth 2147fcf5ef2aSThomas Huth if (compute_ov) { 2148fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 2149fcf5ef2aSThomas Huth } 2150fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 2151fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 2152fcf5ef2aSThomas Huth } 2153fcf5ef2aSThomas Huth 215411f4e8f8SRichard Henderson if (t0 != ret) { 2155fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 2156fcf5ef2aSThomas Huth } 2157fcf5ef2aSThomas Huth } 2158fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 2159fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 2160fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2161fcf5ef2aSThomas Huth { \ 2162fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2163fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 2164fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2165fcf5ef2aSThomas Huth } 2166fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 2167fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 2168fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 2169fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2170fcf5ef2aSThomas Huth { \ 21717058ff52SRichard Henderson TCGv t0 = tcg_constant_tl(const_val); \ 2172fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 2173fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 2174fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 2175fcf5ef2aSThomas Huth } 2176fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 2177fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 2178fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 2179fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 2180fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 2181fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 2182fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 2183fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 2184fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 2185fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 2186fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 2187fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 2188fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 2189fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 2190fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 2191fcf5ef2aSThomas Huth 2192fcf5ef2aSThomas Huth /* subfic */ 2193fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 2194fcf5ef2aSThomas Huth { 21957058ff52SRichard Henderson TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); 2196fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2197fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 2198fcf5ef2aSThomas Huth } 2199fcf5ef2aSThomas Huth 2200fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 2201fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 2202fcf5ef2aSThomas Huth { 22037058ff52SRichard Henderson TCGv zero = tcg_constant_tl(0); 2204fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 2205fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 2206fcf5ef2aSThomas Huth } 2207fcf5ef2aSThomas Huth 2208fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 2209fcf5ef2aSThomas Huth { 22101480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 22111480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 22121480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 22131480d71cSNikunj A Dadhania } 2214fcf5ef2aSThomas Huth } 2215fcf5ef2aSThomas Huth 2216fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 2217fcf5ef2aSThomas Huth { 2218fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 2219fcf5ef2aSThomas Huth } 2220fcf5ef2aSThomas Huth 2221fcf5ef2aSThomas Huth /*** Integer logical ***/ 2222fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 2223fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2224fcf5ef2aSThomas Huth { \ 2225fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 2226fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 2227fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2228fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2229fcf5ef2aSThomas Huth } 2230fcf5ef2aSThomas Huth 2231fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 2232fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2233fcf5ef2aSThomas Huth { \ 2234fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 2235fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 2236fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 2237fcf5ef2aSThomas Huth } 2238fcf5ef2aSThomas Huth 2239fcf5ef2aSThomas Huth /* and & and. */ 2240fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 2241fcf5ef2aSThomas Huth /* andc & andc. */ 2242fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 2243fcf5ef2aSThomas Huth 2244fcf5ef2aSThomas Huth /* andi. */ 2245fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 2246fcf5ef2aSThomas Huth { 2247efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2248efe843d8SDavid Gibson UIMM(ctx->opcode)); 2249fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2250fcf5ef2aSThomas Huth } 2251fcf5ef2aSThomas Huth 2252fcf5ef2aSThomas Huth /* andis. */ 2253fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 2254fcf5ef2aSThomas Huth { 2255efe843d8SDavid Gibson tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2256efe843d8SDavid Gibson UIMM(ctx->opcode) << 16); 2257fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2258fcf5ef2aSThomas Huth } 2259fcf5ef2aSThomas Huth 2260fcf5ef2aSThomas Huth /* cntlzw */ 2261fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 2262fcf5ef2aSThomas Huth { 22639b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22649b8514e5SRichard Henderson 22659b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22669b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 22679b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22689b8514e5SRichard Henderson 2269efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2270fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2271fcf5ef2aSThomas Huth } 2272efe843d8SDavid Gibson } 2273fcf5ef2aSThomas Huth 2274fcf5ef2aSThomas Huth /* cnttzw */ 2275fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 2276fcf5ef2aSThomas Huth { 22779b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 22789b8514e5SRichard Henderson 22799b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 22809b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 22819b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 22829b8514e5SRichard Henderson 2283fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2284fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2285fcf5ef2aSThomas Huth } 2286fcf5ef2aSThomas Huth } 2287fcf5ef2aSThomas Huth 2288fcf5ef2aSThomas Huth /* eqv & eqv. */ 2289fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 2290fcf5ef2aSThomas Huth /* extsb & extsb. */ 2291fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 2292fcf5ef2aSThomas Huth /* extsh & extsh. */ 2293fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 2294fcf5ef2aSThomas Huth /* nand & nand. */ 2295fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 2296fcf5ef2aSThomas Huth /* nor & nor. */ 2297fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 2298fcf5ef2aSThomas Huth 2299fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 2300fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 2301fcf5ef2aSThomas Huth { 23027058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(0); 2303fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 2304fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 2305fcf5ef2aSThomas Huth 2306fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 2307b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 2308fcf5ef2aSThomas Huth } 2309fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 2310fcf5ef2aSThomas Huth 2311fcf5ef2aSThomas Huth /* or & or. */ 2312fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 2313fcf5ef2aSThomas Huth { 2314fcf5ef2aSThomas Huth int rs, ra, rb; 2315fcf5ef2aSThomas Huth 2316fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2317fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2318fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 2319fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 2320fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 2321efe843d8SDavid Gibson if (rs != rb) { 2322fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 2323efe843d8SDavid Gibson } else { 2324fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 2325efe843d8SDavid Gibson } 2326efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2327fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 2328efe843d8SDavid Gibson } 2329fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 2330fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 2331fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2332fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 2333fcf5ef2aSThomas Huth int prio = 0; 2334fcf5ef2aSThomas Huth 2335fcf5ef2aSThomas Huth switch (rs) { 2336fcf5ef2aSThomas Huth case 1: 2337fcf5ef2aSThomas Huth /* Set process priority to low */ 2338fcf5ef2aSThomas Huth prio = 2; 2339fcf5ef2aSThomas Huth break; 2340fcf5ef2aSThomas Huth case 6: 2341fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 2342fcf5ef2aSThomas Huth prio = 3; 2343fcf5ef2aSThomas Huth break; 2344fcf5ef2aSThomas Huth case 2: 2345fcf5ef2aSThomas Huth /* Set process priority to normal */ 2346fcf5ef2aSThomas Huth prio = 4; 2347fcf5ef2aSThomas Huth break; 2348fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2349fcf5ef2aSThomas Huth case 31: 2350fcf5ef2aSThomas Huth if (!ctx->pr) { 2351fcf5ef2aSThomas Huth /* Set process priority to very low */ 2352fcf5ef2aSThomas Huth prio = 1; 2353fcf5ef2aSThomas Huth } 2354fcf5ef2aSThomas Huth break; 2355fcf5ef2aSThomas Huth case 5: 2356fcf5ef2aSThomas Huth if (!ctx->pr) { 2357fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 2358fcf5ef2aSThomas Huth prio = 5; 2359fcf5ef2aSThomas Huth } 2360fcf5ef2aSThomas Huth break; 2361fcf5ef2aSThomas Huth case 3: 2362fcf5ef2aSThomas Huth if (!ctx->pr) { 2363fcf5ef2aSThomas Huth /* Set process priority to high */ 2364fcf5ef2aSThomas Huth prio = 6; 2365fcf5ef2aSThomas Huth } 2366fcf5ef2aSThomas Huth break; 2367fcf5ef2aSThomas Huth case 7: 2368fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 2369fcf5ef2aSThomas Huth /* Set process priority to very high */ 2370fcf5ef2aSThomas Huth prio = 7; 2371fcf5ef2aSThomas Huth } 2372fcf5ef2aSThomas Huth break; 2373fcf5ef2aSThomas Huth #endif 2374fcf5ef2aSThomas Huth default: 2375fcf5ef2aSThomas Huth break; 2376fcf5ef2aSThomas Huth } 2377fcf5ef2aSThomas Huth if (prio) { 2378fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2379fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 2380fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 2381fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 2382fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 2383fcf5ef2aSThomas Huth } 2384fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2385efe843d8SDavid Gibson /* 2386efe843d8SDavid Gibson * Pause out of TCG otherwise spin loops with smt_low eat too 2387efe843d8SDavid Gibson * much CPU and the kernel hangs. This applies to all 2388efe843d8SDavid Gibson * encodings other than no-op, e.g., miso(rs=26), yield(27), 2389efe843d8SDavid Gibson * mdoio(29), mdoom(30), and all currently undefined. 2390fcf5ef2aSThomas Huth */ 2391fcf5ef2aSThomas Huth gen_pause(ctx); 2392fcf5ef2aSThomas Huth #endif 2393fcf5ef2aSThomas Huth #endif 2394fcf5ef2aSThomas Huth } 2395fcf5ef2aSThomas Huth } 2396fcf5ef2aSThomas Huth /* orc & orc. */ 2397fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 2398fcf5ef2aSThomas Huth 2399fcf5ef2aSThomas Huth /* xor & xor. */ 2400fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 2401fcf5ef2aSThomas Huth { 2402fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 2403efe843d8SDavid Gibson if (rS(ctx->opcode) != rB(ctx->opcode)) { 2404efe843d8SDavid Gibson tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2405efe843d8SDavid Gibson cpu_gpr[rB(ctx->opcode)]); 2406efe843d8SDavid Gibson } else { 2407fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 2408efe843d8SDavid Gibson } 2409efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2410fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2411fcf5ef2aSThomas Huth } 2412efe843d8SDavid Gibson } 2413fcf5ef2aSThomas Huth 2414fcf5ef2aSThomas Huth /* ori */ 2415fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 2416fcf5ef2aSThomas Huth { 2417fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2418fcf5ef2aSThomas Huth 2419fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2420fcf5ef2aSThomas Huth return; 2421fcf5ef2aSThomas Huth } 2422fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2423fcf5ef2aSThomas Huth } 2424fcf5ef2aSThomas Huth 2425fcf5ef2aSThomas Huth /* oris */ 2426fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 2427fcf5ef2aSThomas Huth { 2428fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2429fcf5ef2aSThomas Huth 2430fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2431fcf5ef2aSThomas Huth /* NOP */ 2432fcf5ef2aSThomas Huth return; 2433fcf5ef2aSThomas Huth } 2434efe843d8SDavid Gibson tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2435efe843d8SDavid Gibson uimm << 16); 2436fcf5ef2aSThomas Huth } 2437fcf5ef2aSThomas Huth 2438fcf5ef2aSThomas Huth /* xori */ 2439fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 2440fcf5ef2aSThomas Huth { 2441fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2442fcf5ef2aSThomas Huth 2443fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2444fcf5ef2aSThomas Huth /* NOP */ 2445fcf5ef2aSThomas Huth return; 2446fcf5ef2aSThomas Huth } 2447fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 2448fcf5ef2aSThomas Huth } 2449fcf5ef2aSThomas Huth 2450fcf5ef2aSThomas Huth /* xoris */ 2451fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 2452fcf5ef2aSThomas Huth { 2453fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 2454fcf5ef2aSThomas Huth 2455fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 2456fcf5ef2aSThomas Huth /* NOP */ 2457fcf5ef2aSThomas Huth return; 2458fcf5ef2aSThomas Huth } 2459efe843d8SDavid Gibson tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 2460efe843d8SDavid Gibson uimm << 16); 2461fcf5ef2aSThomas Huth } 2462fcf5ef2aSThomas Huth 2463fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 2464fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 2465fcf5ef2aSThomas Huth { 2466fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2467fcf5ef2aSThomas Huth } 2468fcf5ef2aSThomas Huth 2469fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 2470fcf5ef2aSThomas Huth { 247179770002SRichard Henderson #if defined(TARGET_PPC64) 2472fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 247379770002SRichard Henderson #else 247479770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 247579770002SRichard Henderson #endif 2476fcf5ef2aSThomas Huth } 2477fcf5ef2aSThomas Huth 2478fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2479fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 2480fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 2481fcf5ef2aSThomas Huth { 248279770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 2483fcf5ef2aSThomas Huth } 2484fcf5ef2aSThomas Huth #endif 2485fcf5ef2aSThomas Huth 2486fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 2487fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 2488fcf5ef2aSThomas Huth { 2489fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2490fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2491fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2492fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 2493fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2494fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2495fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2496fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 2497fcf5ef2aSThomas Huth } 2498fcf5ef2aSThomas Huth 2499fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2500fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 2501fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 2502fcf5ef2aSThomas Huth { 2503fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 2504fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 2505fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2506fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 2507fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 2508fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 2509fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2510fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 2511fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 2512fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 2513fcf5ef2aSThomas Huth } 2514fcf5ef2aSThomas Huth #endif 2515fcf5ef2aSThomas Huth 2516fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2517fcf5ef2aSThomas Huth /* bpermd */ 2518fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 2519fcf5ef2aSThomas Huth { 2520fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 2521fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2522fcf5ef2aSThomas Huth } 2523fcf5ef2aSThomas Huth #endif 2524fcf5ef2aSThomas Huth 2525fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2526fcf5ef2aSThomas Huth /* extsw & extsw. */ 2527fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 2528fcf5ef2aSThomas Huth 2529fcf5ef2aSThomas Huth /* cntlzd */ 2530fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 2531fcf5ef2aSThomas Huth { 25329b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2533efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2534fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2535fcf5ef2aSThomas Huth } 2536efe843d8SDavid Gibson } 2537fcf5ef2aSThomas Huth 2538fcf5ef2aSThomas Huth /* cnttzd */ 2539fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 2540fcf5ef2aSThomas Huth { 25419b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 2542fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2543fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2544fcf5ef2aSThomas Huth } 2545fcf5ef2aSThomas Huth } 2546fcf5ef2aSThomas Huth 2547fcf5ef2aSThomas Huth /* darn */ 2548fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 2549fcf5ef2aSThomas Huth { 2550fcf5ef2aSThomas Huth int l = L(ctx->opcode); 2551fcf5ef2aSThomas Huth 25527e4357f6SRichard Henderson if (l > 2) { 25537e4357f6SRichard Henderson tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 25547e4357f6SRichard Henderson } else { 2555283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 2556fcf5ef2aSThomas Huth if (l == 0) { 2557fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 25587e4357f6SRichard Henderson } else { 2559fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 2560fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 25617e4357f6SRichard Henderson } 2562fcf5ef2aSThomas Huth } 2563fcf5ef2aSThomas Huth } 2564fcf5ef2aSThomas Huth #endif 2565fcf5ef2aSThomas Huth 2566fcf5ef2aSThomas Huth /*** Integer rotate ***/ 2567fcf5ef2aSThomas Huth 2568fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 2569fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 2570fcf5ef2aSThomas Huth { 2571fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2572fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2573fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 2574fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2575fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2576fcf5ef2aSThomas Huth 2577fcf5ef2aSThomas Huth if (sh == (31 - me) && mb <= me) { 2578fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2579fcf5ef2aSThomas Huth } else { 2580fcf5ef2aSThomas Huth target_ulong mask; 2581c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2582fcf5ef2aSThomas Huth TCGv t1; 2583fcf5ef2aSThomas Huth 2584fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2585fcf5ef2aSThomas Huth mb += 32; 2586fcf5ef2aSThomas Huth me += 32; 2587fcf5ef2aSThomas Huth #endif 2588fcf5ef2aSThomas Huth mask = MASK(mb, me); 2589fcf5ef2aSThomas Huth 2590c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2591c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2592c4f6a4a3SDaniele Buono mask_in_32b = false; 2593c4f6a4a3SDaniele Buono } 2594c4f6a4a3SDaniele Buono #endif 2595fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2596c4f6a4a3SDaniele Buono if (mask_in_32b) { 2597fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2598fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2599fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2600fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 2601fcf5ef2aSThomas Huth } else { 2602fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2603fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 2604fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 2605fcf5ef2aSThomas Huth #else 2606fcf5ef2aSThomas Huth g_assert_not_reached(); 2607fcf5ef2aSThomas Huth #endif 2608fcf5ef2aSThomas Huth } 2609fcf5ef2aSThomas Huth 2610fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2611fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2612fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2613fcf5ef2aSThomas Huth } 2614fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2615fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2616fcf5ef2aSThomas Huth } 2617fcf5ef2aSThomas Huth } 2618fcf5ef2aSThomas Huth 2619fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 2620fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 2621fcf5ef2aSThomas Huth { 2622fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2623fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 26247b4d326fSRichard Henderson int sh = SH(ctx->opcode); 26257b4d326fSRichard Henderson int mb = MB(ctx->opcode); 26267b4d326fSRichard Henderson int me = ME(ctx->opcode); 26277b4d326fSRichard Henderson int len = me - mb + 1; 26287b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 2629fcf5ef2aSThomas Huth 26307b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 26317b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 26327b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 26337b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2634fcf5ef2aSThomas Huth } else { 2635fcf5ef2aSThomas Huth target_ulong mask; 2636c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2637fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2638fcf5ef2aSThomas Huth mb += 32; 2639fcf5ef2aSThomas Huth me += 32; 2640fcf5ef2aSThomas Huth #endif 2641fcf5ef2aSThomas Huth mask = MASK(mb, me); 2642c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2643c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2644c4f6a4a3SDaniele Buono mask_in_32b = false; 2645c4f6a4a3SDaniele Buono } 2646c4f6a4a3SDaniele Buono #endif 2647c4f6a4a3SDaniele Buono if (mask_in_32b) { 26487b4d326fSRichard Henderson if (sh == 0) { 26497b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 265094f040aaSVitaly Chikunov } else { 2651fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2652fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 2653fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 2654fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 2655fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 265694f040aaSVitaly Chikunov } 2657fcf5ef2aSThomas Huth } else { 2658fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2659fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2660fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 2661fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 2662fcf5ef2aSThomas Huth #else 2663fcf5ef2aSThomas Huth g_assert_not_reached(); 2664fcf5ef2aSThomas Huth #endif 2665fcf5ef2aSThomas Huth } 2666fcf5ef2aSThomas Huth } 2667fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2668fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2669fcf5ef2aSThomas Huth } 2670fcf5ef2aSThomas Huth } 2671fcf5ef2aSThomas Huth 2672fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 2673fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 2674fcf5ef2aSThomas Huth { 2675fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2676fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2677fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2678fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 2679fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 2680fcf5ef2aSThomas Huth target_ulong mask; 2681c4f6a4a3SDaniele Buono bool mask_in_32b = true; 2682fcf5ef2aSThomas Huth 2683fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2684fcf5ef2aSThomas Huth mb += 32; 2685fcf5ef2aSThomas Huth me += 32; 2686fcf5ef2aSThomas Huth #endif 2687fcf5ef2aSThomas Huth mask = MASK(mb, me); 2688fcf5ef2aSThomas Huth 2689c4f6a4a3SDaniele Buono #if defined(TARGET_PPC64) 2690c4f6a4a3SDaniele Buono if (mask > 0xffffffffu) { 2691c4f6a4a3SDaniele Buono mask_in_32b = false; 2692c4f6a4a3SDaniele Buono } 2693c4f6a4a3SDaniele Buono #endif 2694c4f6a4a3SDaniele Buono if (mask_in_32b) { 2695fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 2696fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 2697fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 2698fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 2699fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 2700fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 2701fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 2702fcf5ef2aSThomas Huth } else { 2703fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2704fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 2705fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 2706fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 2707fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 2708fcf5ef2aSThomas Huth #else 2709fcf5ef2aSThomas Huth g_assert_not_reached(); 2710fcf5ef2aSThomas Huth #endif 2711fcf5ef2aSThomas Huth } 2712fcf5ef2aSThomas Huth 2713fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2714fcf5ef2aSThomas Huth 2715fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2716fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2717fcf5ef2aSThomas Huth } 2718fcf5ef2aSThomas Huth } 2719fcf5ef2aSThomas Huth 2720fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2721fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2722fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2723fcf5ef2aSThomas Huth { \ 2724fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2725fcf5ef2aSThomas Huth } \ 2726fcf5ef2aSThomas Huth \ 2727fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2728fcf5ef2aSThomas Huth { \ 2729fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2730fcf5ef2aSThomas Huth } 2731fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2732fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2733fcf5ef2aSThomas Huth { \ 2734fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2735fcf5ef2aSThomas Huth } \ 2736fcf5ef2aSThomas Huth \ 2737fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2738fcf5ef2aSThomas Huth { \ 2739fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2740fcf5ef2aSThomas Huth } \ 2741fcf5ef2aSThomas Huth \ 2742fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2743fcf5ef2aSThomas Huth { \ 2744fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2745fcf5ef2aSThomas Huth } \ 2746fcf5ef2aSThomas Huth \ 2747fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2748fcf5ef2aSThomas Huth { \ 2749fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2750fcf5ef2aSThomas Huth } 2751fcf5ef2aSThomas Huth 2752fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2753fcf5ef2aSThomas Huth { 2754fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2755fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 27567b4d326fSRichard Henderson int len = me - mb + 1; 27577b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2758fcf5ef2aSThomas Huth 27597b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 27607b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 27617b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 27627b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2763fcf5ef2aSThomas Huth } else { 2764fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2765fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2766fcf5ef2aSThomas Huth } 2767fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2768fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2769fcf5ef2aSThomas Huth } 2770fcf5ef2aSThomas Huth } 2771fcf5ef2aSThomas Huth 2772fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2773fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2774fcf5ef2aSThomas Huth { 2775fcf5ef2aSThomas Huth uint32_t sh, mb; 2776fcf5ef2aSThomas Huth 2777fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2778fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2779fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2780fcf5ef2aSThomas Huth } 2781fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2782fcf5ef2aSThomas Huth 2783fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2784fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2785fcf5ef2aSThomas Huth { 2786fcf5ef2aSThomas Huth uint32_t sh, me; 2787fcf5ef2aSThomas Huth 2788fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2789fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2790fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2791fcf5ef2aSThomas Huth } 2792fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2793fcf5ef2aSThomas Huth 2794fcf5ef2aSThomas Huth /* rldic - rldic. */ 2795fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2796fcf5ef2aSThomas Huth { 2797fcf5ef2aSThomas Huth uint32_t sh, mb; 2798fcf5ef2aSThomas Huth 2799fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2800fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2801fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2802fcf5ef2aSThomas Huth } 2803fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2804fcf5ef2aSThomas Huth 2805fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2806fcf5ef2aSThomas Huth { 2807fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2808fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2809fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2810fcf5ef2aSThomas Huth TCGv t0; 2811fcf5ef2aSThomas Huth 2812fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2813fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2814fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2815fcf5ef2aSThomas Huth 2816fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2817fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2818fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2819fcf5ef2aSThomas Huth } 2820fcf5ef2aSThomas Huth } 2821fcf5ef2aSThomas Huth 2822fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2823fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2824fcf5ef2aSThomas Huth { 2825fcf5ef2aSThomas Huth uint32_t mb; 2826fcf5ef2aSThomas Huth 2827fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2828fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2829fcf5ef2aSThomas Huth } 2830fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2831fcf5ef2aSThomas Huth 2832fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2833fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2834fcf5ef2aSThomas Huth { 2835fcf5ef2aSThomas Huth uint32_t me; 2836fcf5ef2aSThomas Huth 2837fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2838fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2839fcf5ef2aSThomas Huth } 2840fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2841fcf5ef2aSThomas Huth 2842fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2843fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2844fcf5ef2aSThomas Huth { 2845fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2846fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2847fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2848fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2849fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2850fcf5ef2aSThomas Huth 2851fcf5ef2aSThomas Huth if (mb <= me) { 2852fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2853fcf5ef2aSThomas Huth } else { 2854fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2855fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2856fcf5ef2aSThomas Huth 2857fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2858fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2859fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2860fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2861fcf5ef2aSThomas Huth } 2862fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2863fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2864fcf5ef2aSThomas Huth } 2865fcf5ef2aSThomas Huth } 2866fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2867fcf5ef2aSThomas Huth #endif 2868fcf5ef2aSThomas Huth 2869fcf5ef2aSThomas Huth /*** Integer shift ***/ 2870fcf5ef2aSThomas Huth 2871fcf5ef2aSThomas Huth /* slw & slw. */ 2872fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2873fcf5ef2aSThomas Huth { 2874fcf5ef2aSThomas Huth TCGv t0, t1; 2875fcf5ef2aSThomas Huth 2876fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2877fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2878fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2879fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2880fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2881fcf5ef2aSThomas Huth #else 2882fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2883fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2884fcf5ef2aSThomas Huth #endif 2885fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2886fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2887fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2888fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2889fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2890efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2891fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2892fcf5ef2aSThomas Huth } 2893efe843d8SDavid Gibson } 2894fcf5ef2aSThomas Huth 2895fcf5ef2aSThomas Huth /* sraw & sraw. */ 2896fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2897fcf5ef2aSThomas Huth { 2898fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2899fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2900efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2901fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2902fcf5ef2aSThomas Huth } 2903efe843d8SDavid Gibson } 2904fcf5ef2aSThomas Huth 2905fcf5ef2aSThomas Huth /* srawi & srawi. */ 2906fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2907fcf5ef2aSThomas Huth { 2908fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2909fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2910fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2911fcf5ef2aSThomas Huth if (sh == 0) { 2912fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2913fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2914af1c259fSSandipan Das if (is_isa300(ctx)) { 2915af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2916af1c259fSSandipan Das } 2917fcf5ef2aSThomas Huth } else { 2918fcf5ef2aSThomas Huth TCGv t0; 2919fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2920fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2921fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2922fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2923fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2924fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2925af1c259fSSandipan Das if (is_isa300(ctx)) { 2926af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2927af1c259fSSandipan Das } 2928fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2929fcf5ef2aSThomas Huth } 2930fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2931fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2932fcf5ef2aSThomas Huth } 2933fcf5ef2aSThomas Huth } 2934fcf5ef2aSThomas Huth 2935fcf5ef2aSThomas Huth /* srw & srw. */ 2936fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2937fcf5ef2aSThomas Huth { 2938fcf5ef2aSThomas Huth TCGv t0, t1; 2939fcf5ef2aSThomas Huth 2940fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2941fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2942fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2943fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2944fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2945fcf5ef2aSThomas Huth #else 2946fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2947fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2948fcf5ef2aSThomas Huth #endif 2949fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2950fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2951fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2952fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2953fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2954efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2955fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2956fcf5ef2aSThomas Huth } 2957efe843d8SDavid Gibson } 2958fcf5ef2aSThomas Huth 2959fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2960fcf5ef2aSThomas Huth /* sld & sld. */ 2961fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2962fcf5ef2aSThomas Huth { 2963fcf5ef2aSThomas Huth TCGv t0, t1; 2964fcf5ef2aSThomas Huth 2965fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2966fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2967fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2968fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2969fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2970fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2971fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2972fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2973efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2974fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2975fcf5ef2aSThomas Huth } 2976efe843d8SDavid Gibson } 2977fcf5ef2aSThomas Huth 2978fcf5ef2aSThomas Huth /* srad & srad. */ 2979fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2980fcf5ef2aSThomas Huth { 2981fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2982fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2983efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 2984fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2985fcf5ef2aSThomas Huth } 2986efe843d8SDavid Gibson } 2987fcf5ef2aSThomas Huth /* sradi & sradi. */ 2988fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2989fcf5ef2aSThomas Huth { 2990fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2991fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2992fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2993fcf5ef2aSThomas Huth if (sh == 0) { 2994fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2995fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2996af1c259fSSandipan Das if (is_isa300(ctx)) { 2997af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2998af1c259fSSandipan Das } 2999fcf5ef2aSThomas Huth } else { 3000fcf5ef2aSThomas Huth TCGv t0; 3001fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 3002fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3003fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 3004fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 3005fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 3006af1c259fSSandipan Das if (is_isa300(ctx)) { 3007af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 3008af1c259fSSandipan Das } 3009fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 3010fcf5ef2aSThomas Huth } 3011fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3012fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3013fcf5ef2aSThomas Huth } 3014fcf5ef2aSThomas Huth } 3015fcf5ef2aSThomas Huth 3016fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 3017fcf5ef2aSThomas Huth { 3018fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 3019fcf5ef2aSThomas Huth } 3020fcf5ef2aSThomas Huth 3021fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 3022fcf5ef2aSThomas Huth { 3023fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 3024fcf5ef2aSThomas Huth } 3025fcf5ef2aSThomas Huth 3026fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 3027fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 3028fcf5ef2aSThomas Huth { 3029fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 3030fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 3031fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 3032fcf5ef2aSThomas Huth 3033fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 3034fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 3035fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 3036fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 3037fcf5ef2aSThomas Huth } 3038fcf5ef2aSThomas Huth } 3039fcf5ef2aSThomas Huth 3040fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 3041fcf5ef2aSThomas Huth { 3042fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 3043fcf5ef2aSThomas Huth } 3044fcf5ef2aSThomas Huth 3045fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 3046fcf5ef2aSThomas Huth { 3047fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 3048fcf5ef2aSThomas Huth } 3049fcf5ef2aSThomas Huth 3050fcf5ef2aSThomas Huth /* srd & srd. */ 3051fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 3052fcf5ef2aSThomas Huth { 3053fcf5ef2aSThomas Huth TCGv t0, t1; 3054fcf5ef2aSThomas Huth 3055fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3056fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 3057fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 3058fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 3059fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 3060fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 3061fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 3062fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 3063efe843d8SDavid Gibson if (unlikely(Rc(ctx->opcode) != 0)) { 3064fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 3065fcf5ef2aSThomas Huth } 3066efe843d8SDavid Gibson } 3067fcf5ef2aSThomas Huth #endif 3068fcf5ef2aSThomas Huth 3069fcf5ef2aSThomas Huth /*** Addressing modes ***/ 3070fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 3071fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 3072fcf5ef2aSThomas Huth target_long maskl) 3073fcf5ef2aSThomas Huth { 3074fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 3075fcf5ef2aSThomas Huth 3076fcf5ef2aSThomas Huth simm &= ~maskl; 3077fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3078fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3079fcf5ef2aSThomas Huth simm = (uint32_t)simm; 3080fcf5ef2aSThomas Huth } 3081fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 3082fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 3083fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 3084fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3085fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3086fcf5ef2aSThomas Huth } 3087fcf5ef2aSThomas Huth } else { 3088fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3089fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3090fcf5ef2aSThomas Huth } else { 3091fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3092fcf5ef2aSThomas Huth } 3093fcf5ef2aSThomas Huth } 3094fcf5ef2aSThomas Huth } 3095fcf5ef2aSThomas Huth 3096fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 3097fcf5ef2aSThomas Huth { 3098fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3099fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3100fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3101fcf5ef2aSThomas Huth } else { 3102fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 3103fcf5ef2aSThomas Huth } 3104fcf5ef2aSThomas Huth } else { 3105fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 3106fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3107fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 3108fcf5ef2aSThomas Huth } 3109fcf5ef2aSThomas Huth } 3110fcf5ef2aSThomas Huth } 3111fcf5ef2aSThomas Huth 3112fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 3113fcf5ef2aSThomas Huth { 3114fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 3115fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 3116fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 3117fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3118fcf5ef2aSThomas Huth } else { 3119fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 3120fcf5ef2aSThomas Huth } 3121fcf5ef2aSThomas Huth } 3122fcf5ef2aSThomas Huth 3123fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 3124fcf5ef2aSThomas Huth target_long val) 3125fcf5ef2aSThomas Huth { 3126fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 3127fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3128fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 3129fcf5ef2aSThomas Huth } 3130fcf5ef2aSThomas Huth } 3131fcf5ef2aSThomas Huth 3132fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 3133fcf5ef2aSThomas Huth { 3134fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 3135fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 3136fcf5ef2aSThomas Huth } 3137fcf5ef2aSThomas Huth 3138eb63efd9SFernando Eckhardt Valle static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) 3139eb63efd9SFernando Eckhardt Valle { 3140eb63efd9SFernando Eckhardt Valle TCGv ea = tcg_temp_new(); 3141eb63efd9SFernando Eckhardt Valle if (ra) { 3142eb63efd9SFernando Eckhardt Valle tcg_gen_add_tl(ea, cpu_gpr[ra], displ); 3143eb63efd9SFernando Eckhardt Valle } else { 3144eb63efd9SFernando Eckhardt Valle tcg_gen_mov_tl(ea, displ); 3145eb63efd9SFernando Eckhardt Valle } 3146eb63efd9SFernando Eckhardt Valle if (NARROW_MODE(ctx)) { 3147eb63efd9SFernando Eckhardt Valle tcg_gen_ext32u_tl(ea, ea); 3148eb63efd9SFernando Eckhardt Valle } 3149eb63efd9SFernando Eckhardt Valle return ea; 3150eb63efd9SFernando Eckhardt Valle } 3151eb63efd9SFernando Eckhardt Valle 3152fcf5ef2aSThomas Huth /*** Integer load ***/ 3153fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 3154fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 3155fcf5ef2aSThomas Huth 3156fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 3157fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 3158fcf5ef2aSThomas Huth TCGv val, \ 3159fcf5ef2aSThomas Huth TCGv addr) \ 3160fcf5ef2aSThomas Huth { \ 3161fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 3162fcf5ef2aSThomas Huth } 3163fcf5ef2aSThomas Huth 3164fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 3165fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 3166fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 3167fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 3168fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 3169fcf5ef2aSThomas Huth 3170fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 3171fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 3172fcf5ef2aSThomas Huth 3173fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 3174fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 3175fcf5ef2aSThomas Huth TCGv_i64 val, \ 3176fcf5ef2aSThomas Huth TCGv addr) \ 3177fcf5ef2aSThomas Huth { \ 3178fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 3179fcf5ef2aSThomas Huth } 3180fcf5ef2aSThomas Huth 3181fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 3182fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 3183fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 3184fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 3185fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) 3186fcf5ef2aSThomas Huth 3187fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3188fc313c64SFrédéric Pétrot GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) 3189fcf5ef2aSThomas Huth #endif 3190fcf5ef2aSThomas Huth 3191fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 3192fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 3193fcf5ef2aSThomas Huth TCGv val, \ 3194fcf5ef2aSThomas Huth TCGv addr) \ 3195fcf5ef2aSThomas Huth { \ 3196fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 3197fcf5ef2aSThomas Huth } 3198fcf5ef2aSThomas Huth 3199e8f4c8d6SRichard Henderson #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) 3200fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 3201e8f4c8d6SRichard Henderson #endif 3202fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 3203fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 3204fcf5ef2aSThomas Huth 3205fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 3206fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 3207fcf5ef2aSThomas Huth 3208fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 3209fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 3210fcf5ef2aSThomas Huth TCGv_i64 val, \ 3211fcf5ef2aSThomas Huth TCGv addr) \ 3212fcf5ef2aSThomas Huth { \ 3213fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 3214fcf5ef2aSThomas Huth } 3215fcf5ef2aSThomas Huth 3216fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 3217fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 3218fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 3219fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) 3220fcf5ef2aSThomas Huth 3221fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3222fc313c64SFrédéric Pétrot GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) 3223fcf5ef2aSThomas Huth #endif 3224fcf5ef2aSThomas Huth 3225fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 3226fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3227fcf5ef2aSThomas Huth { \ 3228fcf5ef2aSThomas Huth TCGv EA; \ 32299f0cf041SMatheus Ferst chk(ctx); \ 3230fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3231fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3232fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3233fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 3234fcf5ef2aSThomas Huth } 3235fcf5ef2aSThomas Huth 3236fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 3237fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3238fcf5ef2aSThomas Huth 3239fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 3240fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3241fcf5ef2aSThomas Huth 324250728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 324350728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 324450728199SRoman Kapl { \ 324550728199SRoman Kapl TCGv EA; \ 32469f0cf041SMatheus Ferst CHK_SV(ctx); \ 324750728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 324850728199SRoman Kapl EA = tcg_temp_new(); \ 324950728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 325050728199SRoman Kapl tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 325150728199SRoman Kapl } 325250728199SRoman Kapl 325350728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 325450728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 325550728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 325650728199SRoman Kapl #if defined(TARGET_PPC64) 3257fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 325850728199SRoman Kapl #endif 325950728199SRoman Kapl 3260fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3261fcf5ef2aSThomas Huth /* CI load/store variants */ 3262fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 3263fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 3264fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 3265fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 3266fcf5ef2aSThomas Huth #endif 3267fcf5ef2aSThomas Huth 3268fcf5ef2aSThomas Huth /*** Integer store ***/ 3269fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 3270fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 3271fcf5ef2aSThomas Huth { \ 3272fcf5ef2aSThomas Huth TCGv EA; \ 32739f0cf041SMatheus Ferst chk(ctx); \ 3274fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 3275fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 3276fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 3277fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 3278fcf5ef2aSThomas Huth } 3279fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 3280fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 3281fcf5ef2aSThomas Huth 3282fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 3283fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 3284fcf5ef2aSThomas Huth 328550728199SRoman Kapl #define GEN_STEPX(name, stop, opc2, opc3) \ 328650728199SRoman Kapl static void glue(gen_, name##epx)(DisasContext *ctx) \ 328750728199SRoman Kapl { \ 328850728199SRoman Kapl TCGv EA; \ 32899f0cf041SMatheus Ferst CHK_SV(ctx); \ 329050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_INT); \ 329150728199SRoman Kapl EA = tcg_temp_new(); \ 329250728199SRoman Kapl gen_addr_reg_index(ctx, EA); \ 329350728199SRoman Kapl tcg_gen_qemu_st_tl( \ 329450728199SRoman Kapl cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 329550728199SRoman Kapl } 329650728199SRoman Kapl 329750728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 329850728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 329950728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 330050728199SRoman Kapl #if defined(TARGET_PPC64) 3301fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) 330250728199SRoman Kapl #endif 330350728199SRoman Kapl 3304fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3305fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 3306fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 3307fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 3308fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 3309fcf5ef2aSThomas Huth #endif 3310fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 3311fcf5ef2aSThomas Huth 3312fcf5ef2aSThomas Huth /* lhbrx */ 3313fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 3314fcf5ef2aSThomas Huth 3315fcf5ef2aSThomas Huth /* lwbrx */ 3316fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 3317fcf5ef2aSThomas Huth 3318fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3319fcf5ef2aSThomas Huth /* ldbrx */ 3320fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 3321fcf5ef2aSThomas Huth /* stdbrx */ 3322fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 3323fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 3324fcf5ef2aSThomas Huth 3325fcf5ef2aSThomas Huth /* sthbrx */ 3326fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 3327fcf5ef2aSThomas Huth /* stwbrx */ 3328fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 3329fcf5ef2aSThomas Huth 3330fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 3331fcf5ef2aSThomas Huth 3332fcf5ef2aSThomas Huth /* lmw */ 3333fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 3334fcf5ef2aSThomas Huth { 3335fcf5ef2aSThomas Huth TCGv t0; 3336fcf5ef2aSThomas Huth TCGv_i32 t1; 3337fcf5ef2aSThomas Huth 3338fcf5ef2aSThomas Huth if (ctx->le_mode) { 3339fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3340fcf5ef2aSThomas Huth return; 3341fcf5ef2aSThomas Huth } 3342fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3343fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33447058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 3345fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3346fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 3347fcf5ef2aSThomas Huth } 3348fcf5ef2aSThomas Huth 3349fcf5ef2aSThomas Huth /* stmw */ 3350fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 3351fcf5ef2aSThomas Huth { 3352fcf5ef2aSThomas Huth TCGv t0; 3353fcf5ef2aSThomas Huth TCGv_i32 t1; 3354fcf5ef2aSThomas Huth 3355fcf5ef2aSThomas Huth if (ctx->le_mode) { 3356fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3357fcf5ef2aSThomas Huth return; 3358fcf5ef2aSThomas Huth } 3359fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3360fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 33617058ff52SRichard Henderson t1 = tcg_constant_i32(rS(ctx->opcode)); 3362fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 3363fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 3364fcf5ef2aSThomas Huth } 3365fcf5ef2aSThomas Huth 3366fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 3367fcf5ef2aSThomas Huth 3368fcf5ef2aSThomas Huth /* lswi */ 3369efe843d8SDavid Gibson /* 3370efe843d8SDavid Gibson * PowerPC32 specification says we must generate an exception if rA is 3371efe843d8SDavid Gibson * in the range of registers to be loaded. In an other hand, IBM says 3372efe843d8SDavid Gibson * this is valid, but rA won't be loaded. For now, I'll follow the 3373efe843d8SDavid Gibson * spec... 3374fcf5ef2aSThomas Huth */ 3375fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 3376fcf5ef2aSThomas Huth { 3377fcf5ef2aSThomas Huth TCGv t0; 3378fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3379fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3380fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 3381fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 3382fcf5ef2aSThomas Huth int nr; 3383fcf5ef2aSThomas Huth 3384fcf5ef2aSThomas Huth if (ctx->le_mode) { 3385fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3386fcf5ef2aSThomas Huth return; 3387fcf5ef2aSThomas Huth } 3388efe843d8SDavid Gibson if (nb == 0) { 3389fcf5ef2aSThomas Huth nb = 32; 3390efe843d8SDavid Gibson } 3391f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 3392fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 3393fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 3394fcf5ef2aSThomas Huth return; 3395fcf5ef2aSThomas Huth } 3396fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3397fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3398fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 33997058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 34007058ff52SRichard Henderson t2 = tcg_constant_i32(start); 3401fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 3402fcf5ef2aSThomas Huth } 3403fcf5ef2aSThomas Huth 3404fcf5ef2aSThomas Huth /* lswx */ 3405fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 3406fcf5ef2aSThomas Huth { 3407fcf5ef2aSThomas Huth TCGv t0; 3408fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 3409fcf5ef2aSThomas Huth 3410fcf5ef2aSThomas Huth if (ctx->le_mode) { 3411fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3412fcf5ef2aSThomas Huth return; 3413fcf5ef2aSThomas Huth } 3414fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3415fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3416fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 34177058ff52SRichard Henderson t1 = tcg_constant_i32(rD(ctx->opcode)); 34187058ff52SRichard Henderson t2 = tcg_constant_i32(rA(ctx->opcode)); 34197058ff52SRichard Henderson t3 = tcg_constant_i32(rB(ctx->opcode)); 3420fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 3421fcf5ef2aSThomas Huth } 3422fcf5ef2aSThomas Huth 3423fcf5ef2aSThomas Huth /* stswi */ 3424fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 3425fcf5ef2aSThomas Huth { 3426fcf5ef2aSThomas Huth TCGv t0; 3427fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3428fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 3429fcf5ef2aSThomas Huth 3430fcf5ef2aSThomas Huth if (ctx->le_mode) { 3431fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3432fcf5ef2aSThomas Huth return; 3433fcf5ef2aSThomas Huth } 3434fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3435fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3436fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 3437efe843d8SDavid Gibson if (nb == 0) { 3438fcf5ef2aSThomas Huth nb = 32; 3439efe843d8SDavid Gibson } 34407058ff52SRichard Henderson t1 = tcg_constant_i32(nb); 34417058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3442fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3443fcf5ef2aSThomas Huth } 3444fcf5ef2aSThomas Huth 3445fcf5ef2aSThomas Huth /* stswx */ 3446fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 3447fcf5ef2aSThomas Huth { 3448fcf5ef2aSThomas Huth TCGv t0; 3449fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3450fcf5ef2aSThomas Huth 3451fcf5ef2aSThomas Huth if (ctx->le_mode) { 3452fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3453fcf5ef2aSThomas Huth return; 3454fcf5ef2aSThomas Huth } 3455fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3456fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3457fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3458fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3459fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3460fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 34617058ff52SRichard Henderson t2 = tcg_constant_i32(rS(ctx->opcode)); 3462fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3463fcf5ef2aSThomas Huth } 3464fcf5ef2aSThomas Huth 3465fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3466fcf5ef2aSThomas Huth /* eieio */ 3467fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3468fcf5ef2aSThomas Huth { 3469fcb830afSNicholas Piggin TCGBar bar = TCG_MO_ALL; 3470fcb830afSNicholas Piggin 3471fcb830afSNicholas Piggin /* 3472fcb830afSNicholas Piggin * eieio has complex semanitcs. It provides memory ordering between 3473fcb830afSNicholas Piggin * operations in the set: 3474fcb830afSNicholas Piggin * - loads from CI memory. 3475fcb830afSNicholas Piggin * - stores to CI memory. 3476fcb830afSNicholas Piggin * - stores to WT memory. 3477fcb830afSNicholas Piggin * 3478fcb830afSNicholas Piggin * It separately also orders memory for operations in the set: 3479fcb830afSNicholas Piggin * - stores to cacheble memory. 3480fcb830afSNicholas Piggin * 3481fcb830afSNicholas Piggin * It also serializes instructions: 3482fcb830afSNicholas Piggin * - dcbt and dcbst. 3483fcb830afSNicholas Piggin * 3484fcb830afSNicholas Piggin * It separately serializes: 3485fcb830afSNicholas Piggin * - tlbie and tlbsync. 3486fcb830afSNicholas Piggin * 3487fcb830afSNicholas Piggin * And separately serializes: 3488fcb830afSNicholas Piggin * - slbieg, slbiag, and slbsync. 3489fcb830afSNicholas Piggin * 3490fcb830afSNicholas Piggin * The end result is that CI memory ordering requires TCG_MO_ALL 3491fcb830afSNicholas Piggin * and it is not possible to special-case more relaxed ordering for 3492fcb830afSNicholas Piggin * cacheable accesses. TCG_BAR_SC is required to provide this 3493fcb830afSNicholas Piggin * serialization. 3494fcb830afSNicholas Piggin */ 3495c8fd8373SCédric Le Goater 3496c8fd8373SCédric Le Goater /* 3497c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3498c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3499c8fd8373SCédric Le Goater */ 3500c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3501c8fd8373SCédric Le Goater /* 3502c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3503c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3504c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3505c8fd8373SCédric Le Goater * complain to the user. 3506c8fd8373SCédric Le Goater */ 3507c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3508c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 35092c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", ctx->cia); 3510c8fd8373SCédric Le Goater } else { 3511c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3512c8fd8373SCédric Le Goater } 3513c8fd8373SCédric Le Goater } 3514c8fd8373SCédric Le Goater 3515c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3516fcf5ef2aSThomas Huth } 3517fcf5ef2aSThomas Huth 3518fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3519fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3520fcf5ef2aSThomas Huth { 3521fcf5ef2aSThomas Huth TCGv_i32 t; 3522fcf5ef2aSThomas Huth TCGLabel *l; 3523fcf5ef2aSThomas Huth 3524fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3525fcf5ef2aSThomas Huth return; 3526fcf5ef2aSThomas Huth } 3527fcf5ef2aSThomas Huth l = gen_new_label(); 3528fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3529fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3530fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3531fcf5ef2aSThomas Huth if (global) { 3532fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3533fcf5ef2aSThomas Huth } else { 3534fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3535fcf5ef2aSThomas Huth } 3536fcf5ef2aSThomas Huth gen_set_label(l); 3537fcf5ef2aSThomas Huth } 3538fcf5ef2aSThomas Huth #else 3539fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3540fcf5ef2aSThomas Huth #endif 3541fcf5ef2aSThomas Huth 3542fcf5ef2aSThomas Huth /* isync */ 3543fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3544fcf5ef2aSThomas Huth { 3545fcf5ef2aSThomas Huth /* 3546fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3547fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3548fcf5ef2aSThomas Huth */ 3549fcf5ef2aSThomas Huth if (!ctx->pr) { 3550fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3551fcf5ef2aSThomas Huth } 35524771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3553d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 3554fcf5ef2aSThomas Huth } 3555fcf5ef2aSThomas Huth 3556fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3557fcf5ef2aSThomas Huth 355814776ab5STony Nguyen static void gen_load_locked(DisasContext *ctx, MemOp memop) 35592a4e6c1bSRichard Henderson { 35602a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 35612a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 35622a4e6c1bSRichard Henderson 35632a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 35642a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 35652a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 35662a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 3567392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); 35682a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 35692a4e6c1bSRichard Henderson } 35702a4e6c1bSRichard Henderson 3571fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3572fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3573fcf5ef2aSThomas Huth { \ 35742a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3575fcf5ef2aSThomas Huth } 3576fcf5ef2aSThomas Huth 3577fcf5ef2aSThomas Huth /* lwarx */ 3578fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3579fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3580fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3581fcf5ef2aSThomas Huth 358214776ab5STony Nguyen static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, 358320923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 358420923c1dSRichard Henderson { 358520923c1dSRichard Henderson TCGv t = tcg_temp_new(); 358620923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 358720923c1dSRichard Henderson TCGv u = tcg_temp_new(); 358820923c1dSRichard Henderson 358920923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 359020923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 359120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 359220923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 359320923c1dSRichard Henderson 359420923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 359520923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 359620923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 359720923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 359820923c1dSRichard Henderson 359920923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 360020923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 360120923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 360220923c1dSRichard Henderson } 360320923c1dSRichard Henderson 360414776ab5STony Nguyen static void gen_ld_atomic(DisasContext *ctx, MemOp memop) 360520ba8504SRichard Henderson { 360620ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 360720ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 360820923c1dSRichard Henderson int rt = rD(ctx->opcode); 360920923c1dSRichard Henderson bool need_serial; 361020ba8504SRichard Henderson TCGv src, dst; 361120ba8504SRichard Henderson 361220ba8504SRichard Henderson gen_addr_register(ctx, EA); 361320923c1dSRichard Henderson dst = cpu_gpr[rt]; 361420923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 361520ba8504SRichard Henderson 361620923c1dSRichard Henderson need_serial = false; 361720ba8504SRichard Henderson memop |= MO_ALIGN; 361820ba8504SRichard Henderson switch (gpr_FC) { 361920ba8504SRichard Henderson case 0: /* Fetch and add */ 362020ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 362120ba8504SRichard Henderson break; 362220ba8504SRichard Henderson case 1: /* Fetch and xor */ 362320ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 362420ba8504SRichard Henderson break; 362520ba8504SRichard Henderson case 2: /* Fetch and or */ 362620ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 362720ba8504SRichard Henderson break; 362820ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 362920ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 363020ba8504SRichard Henderson break; 3631b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3632b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3633b8ce0f86SRichard Henderson break; 3634b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3635b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3636b8ce0f86SRichard Henderson break; 3637b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3638b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3639b8ce0f86SRichard Henderson break; 3640b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3641b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3642b8ce0f86SRichard Henderson break; 364320ba8504SRichard Henderson case 8: /* Swap */ 364420ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 364520ba8504SRichard Henderson break; 364620923c1dSRichard Henderson 364720923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 364820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 364920923c1dSRichard Henderson need_serial = true; 365020923c1dSRichard Henderson } else { 365120923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 365220923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 365320923c1dSRichard Henderson 365420923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 365520923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 365620923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 365720923c1dSRichard Henderson } else { 365820923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 365920923c1dSRichard Henderson } 366020923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 366120923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 366220923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 366320923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 366420923c1dSRichard Henderson } 366520ba8504SRichard Henderson break; 366620923c1dSRichard Henderson 366720923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 366820923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 366920923c1dSRichard Henderson need_serial = true; 367020923c1dSRichard Henderson } else { 367120923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 367220923c1dSRichard Henderson } 367320923c1dSRichard Henderson break; 367420923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 367520923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 367620923c1dSRichard Henderson need_serial = true; 367720923c1dSRichard Henderson } else { 367820923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 367920923c1dSRichard Henderson } 368020923c1dSRichard Henderson break; 368120923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 368220923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 368320923c1dSRichard Henderson need_serial = true; 368420923c1dSRichard Henderson } else { 368520923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 368620923c1dSRichard Henderson } 368720923c1dSRichard Henderson break; 368820923c1dSRichard Henderson 368920ba8504SRichard Henderson default: 369020ba8504SRichard Henderson /* invoke data storage error handler */ 369120ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 369220ba8504SRichard Henderson } 369320923c1dSRichard Henderson 369420923c1dSRichard Henderson if (need_serial) { 369520923c1dSRichard Henderson /* Restart with exclusive lock. */ 369620923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 369720923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 369820923c1dSRichard Henderson } 3699a68a6146SBalamuruhan S } 3700a68a6146SBalamuruhan S 370120ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 370220ba8504SRichard Henderson { 370320ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 370420ba8504SRichard Henderson } 370520ba8504SRichard Henderson 370620ba8504SRichard Henderson #ifdef TARGET_PPC64 370720ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 370820ba8504SRichard Henderson { 3709fc313c64SFrédéric Pétrot gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); 371020ba8504SRichard Henderson } 3711a68a6146SBalamuruhan S #endif 3712a68a6146SBalamuruhan S 371314776ab5STony Nguyen static void gen_st_atomic(DisasContext *ctx, MemOp memop) 37149deb041cSRichard Henderson { 37159deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 37169deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 37179deb041cSRichard Henderson TCGv src, discard; 37189deb041cSRichard Henderson 37199deb041cSRichard Henderson gen_addr_register(ctx, EA); 37209deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 37219deb041cSRichard Henderson discard = tcg_temp_new(); 37229deb041cSRichard Henderson 37239deb041cSRichard Henderson memop |= MO_ALIGN; 37249deb041cSRichard Henderson switch (gpr_FC) { 37259deb041cSRichard Henderson case 0: /* add and Store */ 37269deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37279deb041cSRichard Henderson break; 37289deb041cSRichard Henderson case 1: /* xor and Store */ 37299deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37309deb041cSRichard Henderson break; 37319deb041cSRichard Henderson case 2: /* Or and Store */ 37329deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37339deb041cSRichard Henderson break; 37349deb041cSRichard Henderson case 3: /* 'and' and Store */ 37359deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 37369deb041cSRichard Henderson break; 37379deb041cSRichard Henderson case 4: /* Store max unsigned */ 3738b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3739b8ce0f86SRichard Henderson break; 37409deb041cSRichard Henderson case 5: /* Store max signed */ 3741b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3742b8ce0f86SRichard Henderson break; 37439deb041cSRichard Henderson case 6: /* Store min unsigned */ 3744b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3745b8ce0f86SRichard Henderson break; 37469deb041cSRichard Henderson case 7: /* Store min signed */ 3747b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3748b8ce0f86SRichard Henderson break; 37499deb041cSRichard Henderson case 24: /* Store twin */ 37507fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 37517fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 37527fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 37537fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 37547fbc2b20SRichard Henderson } else { 37557fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 37567fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 37577fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 37587fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 37597fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 37607fbc2b20SRichard Henderson 37617fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 37627fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 37637fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 37647fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 37657fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 37667fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 37677fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 37687fbc2b20SRichard Henderson } 37699deb041cSRichard Henderson break; 37709deb041cSRichard Henderson default: 37719deb041cSRichard Henderson /* invoke data storage error handler */ 37729deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 37739deb041cSRichard Henderson } 3774a3401188SBalamuruhan S } 3775a3401188SBalamuruhan S 37769deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 37779deb041cSRichard Henderson { 37789deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 37799deb041cSRichard Henderson } 37809deb041cSRichard Henderson 37819deb041cSRichard Henderson #ifdef TARGET_PPC64 37829deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 37839deb041cSRichard Henderson { 3784fc313c64SFrédéric Pétrot gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); 37859deb041cSRichard Henderson } 3786a3401188SBalamuruhan S #endif 3787a3401188SBalamuruhan S 378814776ab5STony Nguyen static void gen_conditional_store(DisasContext *ctx, MemOp memop) 3789fcf5ef2aSThomas Huth { 379021ee07e7SNicholas Piggin TCGLabel *lfail; 379121ee07e7SNicholas Piggin TCGv EA; 379221ee07e7SNicholas Piggin TCGv cr0; 379321ee07e7SNicholas Piggin TCGv t0; 379421ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3795fcf5ef2aSThomas Huth 379621ee07e7SNicholas Piggin lfail = gen_new_label(); 379721ee07e7SNicholas Piggin EA = tcg_temp_new(); 379821ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3799253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 380021ee07e7SNicholas Piggin 380121ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 380221ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 380321ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 380421ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 380521ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); 380621ee07e7SNicholas Piggin 3807253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 380821ee07e7SNicholas Piggin cpu_gpr[rs], ctx->mem_idx, 3809253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3810253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3811253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 381221ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3813253ce7b2SNikunj A Dadhania 381421ee07e7SNicholas Piggin gen_set_label(lfail); 381521ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 3816fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3817fcf5ef2aSThomas Huth } 3818fcf5ef2aSThomas Huth 3819fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3820fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3821fcf5ef2aSThomas Huth { \ 3822d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3823fcf5ef2aSThomas Huth } 3824fcf5ef2aSThomas Huth 3825fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3826fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3827fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3828fcf5ef2aSThomas Huth 3829fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3830fcf5ef2aSThomas Huth /* ldarx */ 3831fc313c64SFrédéric Pétrot LARX(ldarx, DEF_MEMOP(MO_UQ)) 3832fcf5ef2aSThomas Huth /* stdcx. */ 3833fc313c64SFrédéric Pétrot STCX(stdcx_, DEF_MEMOP(MO_UQ)) 3834fcf5ef2aSThomas Huth 3835fcf5ef2aSThomas Huth /* lqarx */ 3836fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3837fcf5ef2aSThomas Huth { 3838fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 383994bf2658SRichard Henderson TCGv EA, hi, lo; 384057b38ffdSRichard Henderson TCGv_i128 t16; 3841fcf5ef2aSThomas Huth 3842fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3843fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3844fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3845fcf5ef2aSThomas Huth return; 3846fcf5ef2aSThomas Huth } 3847fcf5ef2aSThomas Huth 3848fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 384994bf2658SRichard Henderson EA = tcg_temp_new(); 3850fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 385194bf2658SRichard Henderson 385294bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 385394bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 385494bf2658SRichard Henderson hi = cpu_gpr[rd]; 385594bf2658SRichard Henderson 385657b38ffdSRichard Henderson t16 = tcg_temp_new_i128(); 385757b38ffdSRichard Henderson tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); 385857b38ffdSRichard Henderson tcg_gen_extr_i128_i64(lo, hi, t16); 385994bf2658SRichard Henderson 3860e025e8f5SNicholas Piggin tcg_gen_mov_tl(cpu_reserve, EA); 3861392d328aSNicholas Piggin tcg_gen_movi_tl(cpu_reserve_length, 16); 386294bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 386394bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3864fcf5ef2aSThomas Huth } 3865fcf5ef2aSThomas Huth 3866fcf5ef2aSThomas Huth /* stqcx. */ 3867fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3868fcf5ef2aSThomas Huth { 386921ee07e7SNicholas Piggin TCGLabel *lfail; 3870894448aeSRichard Henderson TCGv EA, t0, t1; 387121ee07e7SNicholas Piggin TCGv cr0; 3872894448aeSRichard Henderson TCGv_i128 cmp, val; 387321ee07e7SNicholas Piggin int rs = rS(ctx->opcode); 3874fcf5ef2aSThomas Huth 38754a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3876fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3877fcf5ef2aSThomas Huth return; 3878fcf5ef2aSThomas Huth } 38794a9b3c5dSRichard Henderson 388021ee07e7SNicholas Piggin lfail = gen_new_label(); 38814a9b3c5dSRichard Henderson EA = tcg_temp_new(); 388221ee07e7SNicholas Piggin cr0 = tcg_temp_new(); 3883fcf5ef2aSThomas Huth 388421ee07e7SNicholas Piggin tcg_gen_mov_tl(cr0, cpu_so); 388521ee07e7SNicholas Piggin gen_set_access_type(ctx, ACCESS_RES); 388621ee07e7SNicholas Piggin gen_addr_reg_index(ctx, EA); 388721ee07e7SNicholas Piggin tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); 388821ee07e7SNicholas Piggin tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); 38894a9b3c5dSRichard Henderson 3890894448aeSRichard Henderson cmp = tcg_temp_new_i128(); 3891894448aeSRichard Henderson val = tcg_temp_new_i128(); 38924a9b3c5dSRichard Henderson 3893894448aeSRichard Henderson tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); 38944a9b3c5dSRichard Henderson 3895894448aeSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 3896894448aeSRichard Henderson tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); 38974a9b3c5dSRichard Henderson 3898894448aeSRichard Henderson tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, 3899894448aeSRichard Henderson DEF_MEMOP(MO_128 | MO_ALIGN)); 3900894448aeSRichard Henderson 3901894448aeSRichard Henderson t0 = tcg_temp_new(); 3902894448aeSRichard Henderson t1 = tcg_temp_new(); 3903894448aeSRichard Henderson tcg_gen_extr_i128_i64(t1, t0, val); 3904894448aeSRichard Henderson 3905894448aeSRichard Henderson tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); 3906894448aeSRichard Henderson tcg_gen_xor_tl(t0, t0, cpu_reserve_val); 3907894448aeSRichard Henderson tcg_gen_or_tl(t0, t0, t1); 3908894448aeSRichard Henderson 3909894448aeSRichard Henderson tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); 3910894448aeSRichard Henderson tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 391121ee07e7SNicholas Piggin tcg_gen_or_tl(cr0, cr0, t0); 3912894448aeSRichard Henderson 391321ee07e7SNicholas Piggin gen_set_label(lfail); 391421ee07e7SNicholas Piggin tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); 39154a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 39164a9b3c5dSRichard Henderson } 3917fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3918fcf5ef2aSThomas Huth 3919fcf5ef2aSThomas Huth /* sync */ 3920fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3921fcf5ef2aSThomas Huth { 392203abfd90SNicholas Piggin TCGBar bar = TCG_MO_ALL; 3923fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3924fcf5ef2aSThomas Huth 392503abfd90SNicholas Piggin if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { 392603abfd90SNicholas Piggin bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; 392703abfd90SNicholas Piggin } 392803abfd90SNicholas Piggin 3929fcf5ef2aSThomas Huth /* 3930fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3931fcf5ef2aSThomas Huth * 3932fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3933fcf5ef2aSThomas Huth * 3934fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3935fcf5ef2aSThomas Huth * check MSR_PR as well. 3936fcf5ef2aSThomas Huth */ 3937fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3938fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3939fcf5ef2aSThomas Huth } 394003abfd90SNicholas Piggin 394103abfd90SNicholas Piggin tcg_gen_mb(bar | TCG_BAR_SC); 3942fcf5ef2aSThomas Huth } 3943fcf5ef2aSThomas Huth 3944fcf5ef2aSThomas Huth /* wait */ 3945fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3946fcf5ef2aSThomas Huth { 39470c9717ffSNicholas Piggin uint32_t wc; 39480c9717ffSNicholas Piggin 39490c9717ffSNicholas Piggin if (ctx->insns_flags & PPC_WAIT) { 39500c9717ffSNicholas Piggin /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ 39510c9717ffSNicholas Piggin 39520c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_PM_ISA206) { 39530c9717ffSNicholas Piggin /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ 39540c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39550c9717ffSNicholas Piggin } else { 39560c9717ffSNicholas Piggin wc = 0; 39570c9717ffSNicholas Piggin } 39580c9717ffSNicholas Piggin 39590c9717ffSNicholas Piggin } else if (ctx->insns_flags2 & PPC2_ISA300) { 39600c9717ffSNicholas Piggin /* v3.0 defines a new 'wait' encoding. */ 39610c9717ffSNicholas Piggin wc = WC(ctx->opcode); 39620c9717ffSNicholas Piggin if (ctx->insns_flags2 & PPC2_ISA310) { 39630c9717ffSNicholas Piggin uint32_t pl = PL(ctx->opcode); 39640c9717ffSNicholas Piggin 39650c9717ffSNicholas Piggin /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ 39660c9717ffSNicholas Piggin if (wc == 3) { 39670c9717ffSNicholas Piggin gen_invalid(ctx); 39680c9717ffSNicholas Piggin return; 39690c9717ffSNicholas Piggin } 39700c9717ffSNicholas Piggin 39710c9717ffSNicholas Piggin /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ 39720c9717ffSNicholas Piggin if (pl > 0 && wc != 2) { 39730c9717ffSNicholas Piggin gen_invalid(ctx); 39740c9717ffSNicholas Piggin return; 39750c9717ffSNicholas Piggin } 39760c9717ffSNicholas Piggin 39770c9717ffSNicholas Piggin } else { /* ISA300 */ 39780c9717ffSNicholas Piggin /* WC 1-3 are reserved */ 39790c9717ffSNicholas Piggin if (wc > 0) { 39800c9717ffSNicholas Piggin gen_invalid(ctx); 39810c9717ffSNicholas Piggin return; 39820c9717ffSNicholas Piggin } 39830c9717ffSNicholas Piggin } 39840c9717ffSNicholas Piggin 39850c9717ffSNicholas Piggin } else { 39860c9717ffSNicholas Piggin warn_report("wait instruction decoded with wrong ISA flags."); 39870c9717ffSNicholas Piggin gen_invalid(ctx); 39880c9717ffSNicholas Piggin return; 39890c9717ffSNicholas Piggin } 39900c9717ffSNicholas Piggin 39910c9717ffSNicholas Piggin /* 39920c9717ffSNicholas Piggin * wait without WC field or with WC=0 waits for an exception / interrupt 39930c9717ffSNicholas Piggin * to occur. 39940c9717ffSNicholas Piggin */ 39950c9717ffSNicholas Piggin if (wc == 0) { 39967058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(1); 3997fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3998fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3999fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 4000b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4001fcf5ef2aSThomas Huth } 4002fcf5ef2aSThomas Huth 40030c9717ffSNicholas Piggin /* 40040c9717ffSNicholas Piggin * Other wait types must not just wait until an exception occurs because 40050c9717ffSNicholas Piggin * ignoring their other wake-up conditions could cause a hang. 40060c9717ffSNicholas Piggin * 40070c9717ffSNicholas Piggin * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as 40080c9717ffSNicholas Piggin * no-ops. 40090c9717ffSNicholas Piggin * 40100c9717ffSNicholas Piggin * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. 40110c9717ffSNicholas Piggin * 40120c9717ffSNicholas Piggin * wc=2 waits for an implementation-specific condition, such could be 40130c9717ffSNicholas Piggin * always true, so it can be implemented as a no-op. 40140c9717ffSNicholas Piggin * 40150c9717ffSNicholas Piggin * For v3.1, wc=1,2 are architected but may be implemented as no-ops. 40160c9717ffSNicholas Piggin * 40170c9717ffSNicholas Piggin * wc=1 (waitrsv) waits for an exception or a reservation to be lost. 40180c9717ffSNicholas Piggin * Reservation-loss may have implementation-specific conditions, so it 40190c9717ffSNicholas Piggin * can be implemented as a no-op. 40200c9717ffSNicholas Piggin * 40210c9717ffSNicholas Piggin * wc=2 waits for an exception or an amount of time to pass. This 40220c9717ffSNicholas Piggin * amount is implementation-specific so it can be implemented as a 40230c9717ffSNicholas Piggin * no-op. 40240c9717ffSNicholas Piggin * 40250c9717ffSNicholas Piggin * ISA v3.1 allows for execution to resume "in the rare case of 40260c9717ffSNicholas Piggin * an implementation-dependent event", so in any case software must 40270c9717ffSNicholas Piggin * not depend on the architected resumption condition to become 40280c9717ffSNicholas Piggin * true, so no-op implementations should be architecturally correct 40290c9717ffSNicholas Piggin * (if suboptimal). 40300c9717ffSNicholas Piggin */ 40310c9717ffSNicholas Piggin } 40320c9717ffSNicholas Piggin 4033fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4034fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 4035fcf5ef2aSThomas Huth { 4036fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40379f0cf041SMatheus Ferst GEN_PRIV(ctx); 4038fcf5ef2aSThomas Huth #else 4039fcf5ef2aSThomas Huth TCGv_i32 t; 4040fcf5ef2aSThomas Huth 40419f0cf041SMatheus Ferst CHK_HV(ctx); 4042c32654afSNicholas Piggin translator_io_start(&ctx->base); 40437058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_DOZE); 4044fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4045154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4046154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4047fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4048fcf5ef2aSThomas Huth } 4049fcf5ef2aSThomas Huth 4050fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 4051fcf5ef2aSThomas Huth { 4052fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40539f0cf041SMatheus Ferst GEN_PRIV(ctx); 4054fcf5ef2aSThomas Huth #else 4055fcf5ef2aSThomas Huth TCGv_i32 t; 4056fcf5ef2aSThomas Huth 40579f0cf041SMatheus Ferst CHK_HV(ctx); 4058c32654afSNicholas Piggin translator_io_start(&ctx->base); 40597058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_NAP); 4060fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4061154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4062154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4063fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4064fcf5ef2aSThomas Huth } 4065fcf5ef2aSThomas Huth 4066cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 4067cdee0e72SNikunj A Dadhania { 406821c0d66aSBenjamin Herrenschmidt #if defined(CONFIG_USER_ONLY) 40699f0cf041SMatheus Ferst GEN_PRIV(ctx); 407021c0d66aSBenjamin Herrenschmidt #else 407121c0d66aSBenjamin Herrenschmidt TCGv_i32 t; 407221c0d66aSBenjamin Herrenschmidt 40739f0cf041SMatheus Ferst CHK_HV(ctx); 4074c32654afSNicholas Piggin translator_io_start(&ctx->base); 40757058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_STOP); 407621c0d66aSBenjamin Herrenschmidt gen_helper_pminsn(cpu_env, t); 407721c0d66aSBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 407821c0d66aSBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 407921c0d66aSBenjamin Herrenschmidt #endif /* defined(CONFIG_USER_ONLY) */ 4080cdee0e72SNikunj A Dadhania } 4081cdee0e72SNikunj A Dadhania 4082fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 4083fcf5ef2aSThomas Huth { 4084fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 40859f0cf041SMatheus Ferst GEN_PRIV(ctx); 4086fcf5ef2aSThomas Huth #else 4087fcf5ef2aSThomas Huth TCGv_i32 t; 4088fcf5ef2aSThomas Huth 40899f0cf041SMatheus Ferst CHK_HV(ctx); 4090c32654afSNicholas Piggin translator_io_start(&ctx->base); 40917058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_SLEEP); 4092fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4093154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4094154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4095fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4096fcf5ef2aSThomas Huth } 4097fcf5ef2aSThomas Huth 4098fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 4099fcf5ef2aSThomas Huth { 4100fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 41019f0cf041SMatheus Ferst GEN_PRIV(ctx); 4102fcf5ef2aSThomas Huth #else 4103fcf5ef2aSThomas Huth TCGv_i32 t; 4104fcf5ef2aSThomas Huth 41059f0cf041SMatheus Ferst CHK_HV(ctx); 4106c32654afSNicholas Piggin translator_io_start(&ctx->base); 41077058ff52SRichard Henderson t = tcg_constant_i32(PPC_PM_RVWINKLE); 4108fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 4109154c69f2SBenjamin Herrenschmidt /* Stop translation, as the CPU is supposed to sleep from now */ 4110154c69f2SBenjamin Herrenschmidt gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 4111fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4112fcf5ef2aSThomas Huth } 4113fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 4114fcf5ef2aSThomas Huth 4115fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 4116fcf5ef2aSThomas Huth { 4117fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4118efe843d8SDavid Gibson if (ctx->has_cfar) { 4119fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 4120efe843d8SDavid Gibson } 4121fcf5ef2aSThomas Huth #endif 4122fcf5ef2aSThomas Huth } 4123fcf5ef2aSThomas Huth 412446d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 412546d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 412646d396bdSDaniel Henrique Barboza { 412746d396bdSDaniel Henrique Barboza /* 412846d396bdSDaniel Henrique Barboza * Do not bother calling the helper if the PMU isn't counting 412946d396bdSDaniel Henrique Barboza * instructions. 413046d396bdSDaniel Henrique Barboza */ 413146d396bdSDaniel Henrique Barboza if (!ctx->pmu_insn_cnt) { 413246d396bdSDaniel Henrique Barboza return; 413346d396bdSDaniel Henrique Barboza } 413446d396bdSDaniel Henrique Barboza 413546d396bdSDaniel Henrique Barboza #if !defined(CONFIG_USER_ONLY) 4136eeaaefe9SLeandro Lupori TCGLabel *l; 4137eeaaefe9SLeandro Lupori TCGv t0; 4138eeaaefe9SLeandro Lupori 413946d396bdSDaniel Henrique Barboza /* 414046d396bdSDaniel Henrique Barboza * The PMU insns_inc() helper stops the internal PMU timer if a 414146d396bdSDaniel Henrique Barboza * counter overflows happens. In that case, if the guest is 414246d396bdSDaniel Henrique Barboza * running with icount and we do not handle it beforehand, 414346d396bdSDaniel Henrique Barboza * the helper can trigger a 'bad icount read'. 414446d396bdSDaniel Henrique Barboza */ 4145283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 414646d396bdSDaniel Henrique Barboza 4147eeaaefe9SLeandro Lupori /* Avoid helper calls when only PMC5-6 are enabled. */ 4148eeaaefe9SLeandro Lupori if (!ctx->pmc_other) { 4149eeaaefe9SLeandro Lupori l = gen_new_label(); 4150eeaaefe9SLeandro Lupori t0 = tcg_temp_new(); 4151eeaaefe9SLeandro Lupori 4152eeaaefe9SLeandro Lupori gen_load_spr(t0, SPR_POWER_PMC5); 4153eeaaefe9SLeandro Lupori tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 4154eeaaefe9SLeandro Lupori gen_store_spr(SPR_POWER_PMC5, t0); 4155eeaaefe9SLeandro Lupori /* Check for overflow, if it's enabled */ 4156eeaaefe9SLeandro Lupori if (ctx->mmcr0_pmcjce) { 4157eeaaefe9SLeandro Lupori tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); 4158eeaaefe9SLeandro Lupori gen_helper_handle_pmc5_overflow(cpu_env); 4159eeaaefe9SLeandro Lupori } 4160eeaaefe9SLeandro Lupori 4161eeaaefe9SLeandro Lupori gen_set_label(l); 4162eeaaefe9SLeandro Lupori } else { 416346d396bdSDaniel Henrique Barboza gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); 4164eeaaefe9SLeandro Lupori } 416546d396bdSDaniel Henrique Barboza #else 416646d396bdSDaniel Henrique Barboza /* 416746d396bdSDaniel Henrique Barboza * User mode can read (but not write) PMC5 and start/stop 416846d396bdSDaniel Henrique Barboza * the PMU via MMCR0_FC. In this case just increment 416946d396bdSDaniel Henrique Barboza * PMC5 with base.num_insns. 417046d396bdSDaniel Henrique Barboza */ 417146d396bdSDaniel Henrique Barboza TCGv t0 = tcg_temp_new(); 417246d396bdSDaniel Henrique Barboza 417346d396bdSDaniel Henrique Barboza gen_load_spr(t0, SPR_POWER_PMC5); 417446d396bdSDaniel Henrique Barboza tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); 417546d396bdSDaniel Henrique Barboza gen_store_spr(SPR_POWER_PMC5, t0); 417646d396bdSDaniel Henrique Barboza #endif /* #if !defined(CONFIG_USER_ONLY) */ 417746d396bdSDaniel Henrique Barboza } 417846d396bdSDaniel Henrique Barboza #else 417946d396bdSDaniel Henrique Barboza static void pmu_count_insns(DisasContext *ctx) 418046d396bdSDaniel Henrique Barboza { 418146d396bdSDaniel Henrique Barboza return; 418246d396bdSDaniel Henrique Barboza } 418346d396bdSDaniel Henrique Barboza #endif /* #if defined(TARGET_PPC64) */ 418446d396bdSDaniel Henrique Barboza 4185fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 4186fcf5ef2aSThomas Huth { 41872e718e66SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 41882e718e66SRichard Henderson return false; 41892e718e66SRichard Henderson } 41906e9cc373SRichard Henderson return translator_use_goto_tb(&ctx->base, dest); 4191fcf5ef2aSThomas Huth } 4192fcf5ef2aSThomas Huth 41930e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 41940e3bf489SRoman Kapl { 41959498d103SRichard Henderson if (unlikely(ctx->singlestep_enabled)) { 419614895384SNicholas Piggin gen_debug_exception(ctx, false); 41970e3bf489SRoman Kapl } else { 419846d396bdSDaniel Henrique Barboza /* 419946d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 420046d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 420146d396bdSDaniel Henrique Barboza */ 420246d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 420346d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 420446d396bdSDaniel Henrique Barboza } 420546d396bdSDaniel Henrique Barboza 42060e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 42070e3bf489SRoman Kapl } 42080e3bf489SRoman Kapl } 42090e3bf489SRoman Kapl 4210fcf5ef2aSThomas Huth /*** Branch ***/ 4211c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 4212fcf5ef2aSThomas Huth { 4213fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4214fcf5ef2aSThomas Huth dest = (uint32_t) dest; 4215fcf5ef2aSThomas Huth } 4216fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 421746d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 4218fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 4219fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 422007ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 4221fcf5ef2aSThomas Huth } else { 4222fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 42230e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4224fcf5ef2aSThomas Huth } 4225fcf5ef2aSThomas Huth } 4226fcf5ef2aSThomas Huth 4227fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 4228fcf5ef2aSThomas Huth { 4229fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4230fcf5ef2aSThomas Huth nip = (uint32_t)nip; 4231fcf5ef2aSThomas Huth } 4232fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 4233fcf5ef2aSThomas Huth } 4234fcf5ef2aSThomas Huth 4235fcf5ef2aSThomas Huth /* b ba bl bla */ 4236fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 4237fcf5ef2aSThomas Huth { 4238fcf5ef2aSThomas Huth target_ulong li, target; 4239fcf5ef2aSThomas Huth 4240fcf5ef2aSThomas Huth /* sign extend LI */ 4241fcf5ef2aSThomas Huth li = LI(ctx->opcode); 4242fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 4243fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 42442c2bcb1bSRichard Henderson target = ctx->cia + li; 4245fcf5ef2aSThomas Huth } else { 4246fcf5ef2aSThomas Huth target = li; 4247fcf5ef2aSThomas Huth } 4248fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 4249b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4250fcf5ef2aSThomas Huth } 42512c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4252fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 42536086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4254fcf5ef2aSThomas Huth } 4255fcf5ef2aSThomas Huth 4256fcf5ef2aSThomas Huth #define BCOND_IM 0 4257fcf5ef2aSThomas Huth #define BCOND_LR 1 4258fcf5ef2aSThomas Huth #define BCOND_CTR 2 4259fcf5ef2aSThomas Huth #define BCOND_TAR 3 4260fcf5ef2aSThomas Huth 4261c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 4262fcf5ef2aSThomas Huth { 4263fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 4264fcf5ef2aSThomas Huth TCGLabel *l1; 4265fcf5ef2aSThomas Huth TCGv target; 42660e3bf489SRoman Kapl 4267fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 42689723281fSRichard Henderson target = tcg_temp_new(); 4269efe843d8SDavid Gibson if (type == BCOND_CTR) { 4270fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 4271efe843d8SDavid Gibson } else if (type == BCOND_TAR) { 4272fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 4273efe843d8SDavid Gibson } else { 4274fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 4275efe843d8SDavid Gibson } 4276fcf5ef2aSThomas Huth } else { 4277f764718dSRichard Henderson target = NULL; 4278fcf5ef2aSThomas Huth } 4279efe843d8SDavid Gibson if (LK(ctx->opcode)) { 4280b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 4281efe843d8SDavid Gibson } 4282fcf5ef2aSThomas Huth l1 = gen_new_label(); 4283fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 4284fcf5ef2aSThomas Huth /* Decrement and test CTR */ 4285fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 4286fa200c95SGreg Kurz 4287fa200c95SGreg Kurz if (type == BCOND_CTR) { 4288fa200c95SGreg Kurz /* 4289fa200c95SGreg Kurz * All ISAs up to v3 describe this form of bcctr as invalid but 4290fa200c95SGreg Kurz * some processors, ie. 64-bit server processors compliant with 4291fa200c95SGreg Kurz * arch 2.x, do implement a "test and decrement" logic instead, 429215d68c5eSGreg Kurz * as described in their respective UMs. This logic involves CTR 429315d68c5eSGreg Kurz * to act as both the branch target and a counter, which makes 429415d68c5eSGreg Kurz * it basically useless and thus never used in real code. 429515d68c5eSGreg Kurz * 429615d68c5eSGreg Kurz * This form was hence chosen to trigger extra micro-architectural 429715d68c5eSGreg Kurz * side-effect on real HW needed for the Spectre v2 workaround. 429815d68c5eSGreg Kurz * It is up to guests that implement such workaround, ie. linux, to 429915d68c5eSGreg Kurz * use this form in a way it just triggers the side-effect without 430015d68c5eSGreg Kurz * doing anything else harmful. 4301fa200c95SGreg Kurz */ 4302d0db7cadSGreg Kurz if (unlikely(!is_book3s_arch2x(ctx))) { 4303fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4304fcf5ef2aSThomas Huth return; 4305fcf5ef2aSThomas Huth } 4306fa200c95SGreg Kurz 4307fa200c95SGreg Kurz if (NARROW_MODE(ctx)) { 4308fa200c95SGreg Kurz tcg_gen_ext32u_tl(temp, cpu_ctr); 4309fa200c95SGreg Kurz } else { 4310fa200c95SGreg Kurz tcg_gen_mov_tl(temp, cpu_ctr); 4311fa200c95SGreg Kurz } 4312fa200c95SGreg Kurz if (bo & 0x2) { 4313fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4314fa200c95SGreg Kurz } else { 4315fa200c95SGreg Kurz tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4316fa200c95SGreg Kurz } 4317fa200c95SGreg Kurz tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4318fa200c95SGreg Kurz } else { 4319fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 4320fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4321fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 4322fcf5ef2aSThomas Huth } else { 4323fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 4324fcf5ef2aSThomas Huth } 4325fcf5ef2aSThomas Huth if (bo & 0x2) { 4326fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 4327fcf5ef2aSThomas Huth } else { 4328fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 4329fcf5ef2aSThomas Huth } 4330fa200c95SGreg Kurz } 4331fcf5ef2aSThomas Huth } 4332fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 4333fcf5ef2aSThomas Huth /* Test CR */ 4334fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 4335fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 4336fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4337fcf5ef2aSThomas Huth 4338fcf5ef2aSThomas Huth if (bo & 0x8) { 4339fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4340fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 4341fcf5ef2aSThomas Huth } else { 4342fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 4343fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 4344fcf5ef2aSThomas Huth } 4345fcf5ef2aSThomas Huth } 43462c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4347fcf5ef2aSThomas Huth if (type == BCOND_IM) { 4348fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 4349fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 43502c2bcb1bSRichard Henderson gen_goto_tb(ctx, 0, ctx->cia + li); 4351fcf5ef2aSThomas Huth } else { 4352fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 4353fcf5ef2aSThomas Huth } 4354fcf5ef2aSThomas Huth } else { 4355fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4356fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 4357fcf5ef2aSThomas Huth } else { 4358fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 4359fcf5ef2aSThomas Huth } 43600e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 4361c4a2e3a9SRichard Henderson } 4362fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 43630e3bf489SRoman Kapl /* fallthrough case */ 4364fcf5ef2aSThomas Huth gen_set_label(l1); 4365b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 4366fcf5ef2aSThomas Huth } 43676086c751SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 4368fcf5ef2aSThomas Huth } 4369fcf5ef2aSThomas Huth 4370fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 4371fcf5ef2aSThomas Huth { 4372fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 4373fcf5ef2aSThomas Huth } 4374fcf5ef2aSThomas Huth 4375fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 4376fcf5ef2aSThomas Huth { 4377fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 4378fcf5ef2aSThomas Huth } 4379fcf5ef2aSThomas Huth 4380fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 4381fcf5ef2aSThomas Huth { 4382fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 4383fcf5ef2aSThomas Huth } 4384fcf5ef2aSThomas Huth 4385fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 4386fcf5ef2aSThomas Huth { 4387fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 4388fcf5ef2aSThomas Huth } 4389fcf5ef2aSThomas Huth 4390fcf5ef2aSThomas Huth /*** Condition register logical ***/ 4391fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 4392fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 4393fcf5ef2aSThomas Huth { \ 4394fcf5ef2aSThomas Huth uint8_t bitmask; \ 4395fcf5ef2aSThomas Huth int sh; \ 4396fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 4397fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 4398fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 4399fcf5ef2aSThomas Huth if (sh > 0) \ 4400fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 4401fcf5ef2aSThomas Huth else if (sh < 0) \ 4402fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 4403fcf5ef2aSThomas Huth else \ 4404fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 4405fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 4406fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 4407fcf5ef2aSThomas Huth if (sh > 0) \ 4408fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 4409fcf5ef2aSThomas Huth else if (sh < 0) \ 4410fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 4411fcf5ef2aSThomas Huth else \ 4412fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 4413fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 4414fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 4415fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 4416fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4417fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 4418fcf5ef2aSThomas Huth } 4419fcf5ef2aSThomas Huth 4420fcf5ef2aSThomas Huth /* crand */ 4421fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 4422fcf5ef2aSThomas Huth /* crandc */ 4423fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 4424fcf5ef2aSThomas Huth /* creqv */ 4425fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 4426fcf5ef2aSThomas Huth /* crnand */ 4427fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 4428fcf5ef2aSThomas Huth /* crnor */ 4429fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 4430fcf5ef2aSThomas Huth /* cror */ 4431fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 4432fcf5ef2aSThomas Huth /* crorc */ 4433fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 4434fcf5ef2aSThomas Huth /* crxor */ 4435fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 4436fcf5ef2aSThomas Huth 4437fcf5ef2aSThomas Huth /* mcrf */ 4438fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 4439fcf5ef2aSThomas Huth { 4440fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 4441fcf5ef2aSThomas Huth } 4442fcf5ef2aSThomas Huth 4443fcf5ef2aSThomas Huth /*** System linkage ***/ 4444fcf5ef2aSThomas Huth 4445fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 4446fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 4447fcf5ef2aSThomas Huth { 4448fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44499f0cf041SMatheus Ferst GEN_PRIV(ctx); 4450fcf5ef2aSThomas Huth #else 4451efe843d8SDavid Gibson /* 4452efe843d8SDavid Gibson * This instruction doesn't exist anymore on 64-bit server 4453fcf5ef2aSThomas Huth * processors compliant with arch 2.x 4454fcf5ef2aSThomas Huth */ 4455d0db7cadSGreg Kurz if (is_book3s_arch2x(ctx)) { 4456fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4457fcf5ef2aSThomas Huth return; 4458fcf5ef2aSThomas Huth } 4459fcf5ef2aSThomas Huth /* Restore CPU state */ 44609f0cf041SMatheus Ferst CHK_SV(ctx); 4461283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44622c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4463fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 446459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4465fcf5ef2aSThomas Huth #endif 4466fcf5ef2aSThomas Huth } 4467fcf5ef2aSThomas Huth 4468fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4469fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 4470fcf5ef2aSThomas Huth { 4471fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 44729f0cf041SMatheus Ferst GEN_PRIV(ctx); 4473fcf5ef2aSThomas Huth #else 4474fcf5ef2aSThomas Huth /* Restore CPU state */ 44759f0cf041SMatheus Ferst CHK_SV(ctx); 4476283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44772c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 4478fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 447959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4480fcf5ef2aSThomas Huth #endif 4481fcf5ef2aSThomas Huth } 4482fcf5ef2aSThomas Huth 44833c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 44843c89b8d6SNicholas Piggin static void gen_rfscv(DisasContext *ctx) 44853c89b8d6SNicholas Piggin { 44863c89b8d6SNicholas Piggin #if defined(CONFIG_USER_ONLY) 44879f0cf041SMatheus Ferst GEN_PRIV(ctx); 44883c89b8d6SNicholas Piggin #else 44893c89b8d6SNicholas Piggin /* Restore CPU state */ 44909f0cf041SMatheus Ferst CHK_SV(ctx); 4491283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 44922c2bcb1bSRichard Henderson gen_update_cfar(ctx, ctx->cia); 44933c89b8d6SNicholas Piggin gen_helper_rfscv(cpu_env); 449459bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 44953c89b8d6SNicholas Piggin #endif 44963c89b8d6SNicholas Piggin } 44973c89b8d6SNicholas Piggin #endif 44983c89b8d6SNicholas Piggin 4499fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 4500fcf5ef2aSThomas Huth { 4501fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 45029f0cf041SMatheus Ferst GEN_PRIV(ctx); 4503fcf5ef2aSThomas Huth #else 4504fcf5ef2aSThomas Huth /* Restore CPU state */ 45059f0cf041SMatheus Ferst CHK_HV(ctx); 4506c32654afSNicholas Piggin translator_io_start(&ctx->base); 4507fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 450859bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 4509fcf5ef2aSThomas Huth #endif 4510fcf5ef2aSThomas Huth } 4511fcf5ef2aSThomas Huth #endif 4512fcf5ef2aSThomas Huth 4513fcf5ef2aSThomas Huth /* sc */ 4514fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4515fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 4516fcf5ef2aSThomas Huth #else 4517fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 4518fcf5ef2aSThomas Huth #endif 4519fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 4520fcf5ef2aSThomas Huth { 4521fcf5ef2aSThomas Huth uint32_t lev; 4522fcf5ef2aSThomas Huth 4523984eda58SNicholas Piggin /* 4524984eda58SNicholas Piggin * LEV is a 7-bit field, but the top 6 bits are treated as a reserved 4525984eda58SNicholas Piggin * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is 4526984eda58SNicholas Piggin * for Ultravisor which TCG does not support, so just ignore the top 6. 4527984eda58SNicholas Piggin */ 4528984eda58SNicholas Piggin lev = (ctx->opcode >> 5) & 0x1; 4529fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 4530fcf5ef2aSThomas Huth } 4531fcf5ef2aSThomas Huth 45323c89b8d6SNicholas Piggin #if defined(TARGET_PPC64) 45333c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 45343c89b8d6SNicholas Piggin static void gen_scv(DisasContext *ctx) 45353c89b8d6SNicholas Piggin { 4536f43520e5SRichard Henderson uint32_t lev = (ctx->opcode >> 5) & 0x7F; 45373c89b8d6SNicholas Piggin 4538f43520e5SRichard Henderson /* Set the PC back to the faulting instruction. */ 45392c2bcb1bSRichard Henderson gen_update_nip(ctx, ctx->cia); 4540f43520e5SRichard Henderson gen_helper_scv(cpu_env, tcg_constant_i32(lev)); 45413c89b8d6SNicholas Piggin 45427a3fe174SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 45433c89b8d6SNicholas Piggin } 45443c89b8d6SNicholas Piggin #endif 45453c89b8d6SNicholas Piggin #endif 45463c89b8d6SNicholas Piggin 4547fcf5ef2aSThomas Huth /*** Trap ***/ 4548fcf5ef2aSThomas Huth 4549fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 4550fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 4551fcf5ef2aSThomas Huth { 4552fcf5ef2aSThomas Huth /* Trap never */ 4553fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 4554fcf5ef2aSThomas Huth return true; 4555fcf5ef2aSThomas Huth } 4556fcf5ef2aSThomas Huth /* Trap always */ 4557fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 4558fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 4559fcf5ef2aSThomas Huth return true; 4560fcf5ef2aSThomas Huth } 4561fcf5ef2aSThomas Huth return false; 4562fcf5ef2aSThomas Huth } 4563fcf5ef2aSThomas Huth 4564fcf5ef2aSThomas Huth /* tw */ 4565fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 4566fcf5ef2aSThomas Huth { 4567fcf5ef2aSThomas Huth TCGv_i32 t0; 4568fcf5ef2aSThomas Huth 4569fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4570fcf5ef2aSThomas Huth return; 4571fcf5ef2aSThomas Huth } 45727058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4573fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4574fcf5ef2aSThomas Huth t0); 4575fcf5ef2aSThomas Huth } 4576fcf5ef2aSThomas Huth 4577fcf5ef2aSThomas Huth /* twi */ 4578fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 4579fcf5ef2aSThomas Huth { 4580fcf5ef2aSThomas Huth TCGv t0; 4581fcf5ef2aSThomas Huth TCGv_i32 t1; 4582fcf5ef2aSThomas Huth 4583fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4584fcf5ef2aSThomas Huth return; 4585fcf5ef2aSThomas Huth } 45867058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 45877058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4588fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4589fcf5ef2aSThomas Huth } 4590fcf5ef2aSThomas Huth 4591fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4592fcf5ef2aSThomas Huth /* td */ 4593fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 4594fcf5ef2aSThomas Huth { 4595fcf5ef2aSThomas Huth TCGv_i32 t0; 4596fcf5ef2aSThomas Huth 4597fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4598fcf5ef2aSThomas Huth return; 4599fcf5ef2aSThomas Huth } 46007058ff52SRichard Henderson t0 = tcg_constant_i32(TO(ctx->opcode)); 4601fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 4602fcf5ef2aSThomas Huth t0); 4603fcf5ef2aSThomas Huth } 4604fcf5ef2aSThomas Huth 4605fcf5ef2aSThomas Huth /* tdi */ 4606fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 4607fcf5ef2aSThomas Huth { 4608fcf5ef2aSThomas Huth TCGv t0; 4609fcf5ef2aSThomas Huth TCGv_i32 t1; 4610fcf5ef2aSThomas Huth 4611fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 4612fcf5ef2aSThomas Huth return; 4613fcf5ef2aSThomas Huth } 46147058ff52SRichard Henderson t0 = tcg_constant_tl(SIMM(ctx->opcode)); 46157058ff52SRichard Henderson t1 = tcg_constant_i32(TO(ctx->opcode)); 4616fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 4617fcf5ef2aSThomas Huth } 4618fcf5ef2aSThomas Huth #endif 4619fcf5ef2aSThomas Huth 4620fcf5ef2aSThomas Huth /*** Processor control ***/ 4621fcf5ef2aSThomas Huth 4622fcf5ef2aSThomas Huth /* mcrxr */ 4623fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4624fcf5ef2aSThomas Huth { 4625fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4626fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4627fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4628fcf5ef2aSThomas Huth 4629fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4630fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4631fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4632fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4633fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4634fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4635fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4636fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4637fcf5ef2aSThomas Huth 4638fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4639fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4640fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4641fcf5ef2aSThomas Huth } 4642fcf5ef2aSThomas Huth 4643b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4644b63d0434SNikunj A Dadhania /* mcrxrx */ 4645b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4646b63d0434SNikunj A Dadhania { 4647b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4648b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4649b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4650b63d0434SNikunj A Dadhania 4651b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4652b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4653b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4654b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4655b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4656b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4657b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4658b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4659b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4660b63d0434SNikunj A Dadhania } 4661b63d0434SNikunj A Dadhania #endif 4662b63d0434SNikunj A Dadhania 4663fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4664fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4665fcf5ef2aSThomas Huth { 4666fcf5ef2aSThomas Huth uint32_t crm, crn; 4667fcf5ef2aSThomas Huth 4668fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4669fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4670fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4671fcf5ef2aSThomas Huth crn = ctz32(crm); 4672fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4673fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4674fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4675fcf5ef2aSThomas Huth } 4676fcf5ef2aSThomas Huth } else { 4677fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4678fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4679fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4680fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4681fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4682fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4683fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4684fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4685fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4686fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4687fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4688fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4689fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4690fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4691fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4692fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4693fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4694fcf5ef2aSThomas Huth } 4695fcf5ef2aSThomas Huth } 4696fcf5ef2aSThomas Huth 4697fcf5ef2aSThomas Huth /* mfmsr */ 4698fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4699fcf5ef2aSThomas Huth { 47009f0cf041SMatheus Ferst CHK_SV(ctx); 4701fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4702fcf5ef2aSThomas Huth } 4703fcf5ef2aSThomas Huth 4704fcf5ef2aSThomas Huth /* mfspr */ 4705fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4706fcf5ef2aSThomas Huth { 4707fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4708fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4709fcf5ef2aSThomas Huth 4710fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4711fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4712fcf5ef2aSThomas Huth #else 4713fcf5ef2aSThomas Huth if (ctx->pr) { 4714fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4715fcf5ef2aSThomas Huth } else if (ctx->hv) { 4716fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4717fcf5ef2aSThomas Huth } else { 4718fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4719fcf5ef2aSThomas Huth } 4720fcf5ef2aSThomas Huth #endif 4721fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4722fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4723fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4724fcf5ef2aSThomas Huth } else { 4725fcf5ef2aSThomas Huth /* Privilege exception */ 4726efe843d8SDavid Gibson /* 4727efe843d8SDavid Gibson * This is a hack to avoid warnings when running Linux: 4728fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4729fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4730fcf5ef2aSThomas Huth */ 4731fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 473231085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 473331085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 47342c2bcb1bSRichard Henderson ctx->cia); 4735fcf5ef2aSThomas Huth } 4736fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4737fcf5ef2aSThomas Huth } 4738fcf5ef2aSThomas Huth } else { 4739fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4740fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4741fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4742fcf5ef2aSThomas Huth /* This is a nop */ 4743fcf5ef2aSThomas Huth return; 4744fcf5ef2aSThomas Huth } 4745fcf5ef2aSThomas Huth /* Not defined */ 474631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 474731085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 47482c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4749fcf5ef2aSThomas Huth 4750efe843d8SDavid Gibson /* 4751efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4752efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4753fcf5ef2aSThomas Huth */ 4754fcf5ef2aSThomas Huth if (sprn & 0x10) { 4755fcf5ef2aSThomas Huth if (ctx->pr) { 47561315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4757fcf5ef2aSThomas Huth } 4758fcf5ef2aSThomas Huth } else { 4759fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 47601315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4761fcf5ef2aSThomas Huth } 4762fcf5ef2aSThomas Huth } 4763fcf5ef2aSThomas Huth } 4764fcf5ef2aSThomas Huth } 4765fcf5ef2aSThomas Huth 4766fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4767fcf5ef2aSThomas Huth { 4768fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4769fcf5ef2aSThomas Huth } 4770fcf5ef2aSThomas Huth 4771fcf5ef2aSThomas Huth /* mftb */ 4772fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4773fcf5ef2aSThomas Huth { 4774fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4775fcf5ef2aSThomas Huth } 4776fcf5ef2aSThomas Huth 4777fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4778fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4779fcf5ef2aSThomas Huth { 4780fcf5ef2aSThomas Huth uint32_t crm, crn; 4781fcf5ef2aSThomas Huth 4782fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4783fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4784fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4785fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4786fcf5ef2aSThomas Huth crn = ctz32(crm); 4787fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4788fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4789fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4790fcf5ef2aSThomas Huth } 4791fcf5ef2aSThomas Huth } else { 4792fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4793fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4794fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4795fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4796fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4797fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4798fcf5ef2aSThomas Huth } 4799fcf5ef2aSThomas Huth } 4800fcf5ef2aSThomas Huth } 4801fcf5ef2aSThomas Huth } 4802fcf5ef2aSThomas Huth 4803fcf5ef2aSThomas Huth /* mtmsr */ 4804fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4805fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4806fcf5ef2aSThomas Huth { 4807caf590ddSNicholas Piggin if (unlikely(!is_book3s_arch2x(ctx))) { 4808caf590ddSNicholas Piggin gen_invalid(ctx); 4809caf590ddSNicholas Piggin return; 4810caf590ddSNicholas Piggin } 4811caf590ddSNicholas Piggin 48129f0cf041SMatheus Ferst CHK_SV(ctx); 4813fcf5ef2aSThomas Huth 4814fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48156fa5726bSMatheus Ferst TCGv t0, t1; 48166fa5726bSMatheus Ferst target_ulong mask; 48176fa5726bSMatheus Ferst 48186fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48196fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48206fa5726bSMatheus Ferst 4821283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 48226fa5726bSMatheus Ferst 4823fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48245ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48256fa5726bSMatheus Ferst mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); 4826fcf5ef2aSThomas Huth } else { 48276fa5726bSMatheus Ferst /* mtmsrd does not alter HV, S, ME, or LE */ 48286fa5726bSMatheus Ferst mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | 48296fa5726bSMatheus Ferst (1ULL << MSR_HV)); 4830efe843d8SDavid Gibson /* 4831efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4832efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4833efe843d8SDavid Gibson * ppc_store_msr 4834fcf5ef2aSThomas Huth */ 4835b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4836fcf5ef2aSThomas Huth } 48376fa5726bSMatheus Ferst 48386fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48396fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48406fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48416fa5726bSMatheus Ferst 48426fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48436fa5726bSMatheus Ferst 48445ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4845d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4846fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4847fcf5ef2aSThomas Huth } 4848fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4849fcf5ef2aSThomas Huth 4850fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4851fcf5ef2aSThomas Huth { 48529f0cf041SMatheus Ferst CHK_SV(ctx); 4853fcf5ef2aSThomas Huth 4854fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 48556fa5726bSMatheus Ferst TCGv t0, t1; 48566fa5726bSMatheus Ferst target_ulong mask = 0xFFFFFFFF; 48576fa5726bSMatheus Ferst 48586fa5726bSMatheus Ferst t0 = tcg_temp_new(); 48596fa5726bSMatheus Ferst t1 = tcg_temp_new(); 48606fa5726bSMatheus Ferst 4861283a9177SPhilippe Mathieu-Daudé translator_io_start(&ctx->base); 4862fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 48635ed19506SNicholas Piggin /* L=1 form only updates EE and RI */ 48646fa5726bSMatheus Ferst mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); 4865fcf5ef2aSThomas Huth } else { 48666fa5726bSMatheus Ferst /* mtmsr does not alter S, ME, or LE */ 48676fa5726bSMatheus Ferst mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); 4868fcf5ef2aSThomas Huth 4869efe843d8SDavid Gibson /* 4870efe843d8SDavid Gibson * XXX: we need to update nip before the store if we enter 4871efe843d8SDavid Gibson * power saving mode, we will exit the loop directly from 4872efe843d8SDavid Gibson * ppc_store_msr 4873fcf5ef2aSThomas Huth */ 4874b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4875fcf5ef2aSThomas Huth } 48766fa5726bSMatheus Ferst 48776fa5726bSMatheus Ferst tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); 48786fa5726bSMatheus Ferst tcg_gen_andi_tl(t1, cpu_msr, ~mask); 48796fa5726bSMatheus Ferst tcg_gen_or_tl(t0, t0, t1); 48806fa5726bSMatheus Ferst 48816fa5726bSMatheus Ferst gen_helper_store_msr(cpu_env, t0); 48826fa5726bSMatheus Ferst 48835ed19506SNicholas Piggin /* Must stop the translation as machine state (may have) changed */ 4884d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 4885fcf5ef2aSThomas Huth #endif 4886fcf5ef2aSThomas Huth } 4887fcf5ef2aSThomas Huth 4888fcf5ef2aSThomas Huth /* mtspr */ 4889fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4890fcf5ef2aSThomas Huth { 4891fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4892fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4893fcf5ef2aSThomas Huth 4894fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4895fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4896fcf5ef2aSThomas Huth #else 4897fcf5ef2aSThomas Huth if (ctx->pr) { 4898fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4899fcf5ef2aSThomas Huth } else if (ctx->hv) { 4900fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4901fcf5ef2aSThomas Huth } else { 4902fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4903fcf5ef2aSThomas Huth } 4904fcf5ef2aSThomas Huth #endif 4905fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4906fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4907fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4908fcf5ef2aSThomas Huth } else { 4909fcf5ef2aSThomas Huth /* Privilege exception */ 491031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 491131085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 49122c2bcb1bSRichard Henderson ctx->cia); 4913fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4914fcf5ef2aSThomas Huth } 4915fcf5ef2aSThomas Huth } else { 4916fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4917fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4918fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4919fcf5ef2aSThomas Huth /* This is a nop */ 4920fcf5ef2aSThomas Huth return; 4921fcf5ef2aSThomas Huth } 4922fcf5ef2aSThomas Huth 4923fcf5ef2aSThomas Huth /* Not defined */ 492431085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 492531085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 49262c2bcb1bSRichard Henderson TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); 4927fcf5ef2aSThomas Huth 4928fcf5ef2aSThomas Huth 4929efe843d8SDavid Gibson /* 4930efe843d8SDavid Gibson * The behaviour depends on MSR:PR and SPR# bit 0x10, it can 4931efe843d8SDavid Gibson * generate a priv, a hv emu or a no-op 4932fcf5ef2aSThomas Huth */ 4933fcf5ef2aSThomas Huth if (sprn & 0x10) { 4934fcf5ef2aSThomas Huth if (ctx->pr) { 49351315eed6SMatheus Ferst gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4936fcf5ef2aSThomas Huth } 4937fcf5ef2aSThomas Huth } else { 4938fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 49391315eed6SMatheus Ferst gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4940fcf5ef2aSThomas Huth } 4941fcf5ef2aSThomas Huth } 4942fcf5ef2aSThomas Huth } 4943fcf5ef2aSThomas Huth } 4944fcf5ef2aSThomas Huth 4945fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4946fcf5ef2aSThomas Huth /* setb */ 4947fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4948fcf5ef2aSThomas Huth { 4949fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 49506f4912a4SPhilippe Mathieu-Daudé TCGv_i32 t8 = tcg_constant_i32(8); 49516f4912a4SPhilippe Mathieu-Daudé TCGv_i32 tm1 = tcg_constant_i32(-1); 4952fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4953fcf5ef2aSThomas Huth 4954fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4955fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4956fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4957fcf5ef2aSThomas Huth } 4958fcf5ef2aSThomas Huth #endif 4959fcf5ef2aSThomas Huth 4960fcf5ef2aSThomas Huth /*** Cache management ***/ 4961fcf5ef2aSThomas Huth 4962fcf5ef2aSThomas Huth /* dcbf */ 4963fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4964fcf5ef2aSThomas Huth { 4965fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4966fcf5ef2aSThomas Huth TCGv t0; 4967fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4968fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4969fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4970fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4971fcf5ef2aSThomas Huth } 4972fcf5ef2aSThomas Huth 497350728199SRoman Kapl /* dcbfep (external PID dcbf) */ 497450728199SRoman Kapl static void gen_dcbfep(DisasContext *ctx) 497550728199SRoman Kapl { 497650728199SRoman Kapl /* XXX: specification says this is treated as a load by the MMU */ 497750728199SRoman Kapl TCGv t0; 49789f0cf041SMatheus Ferst CHK_SV(ctx); 497950728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 498050728199SRoman Kapl t0 = tcg_temp_new(); 498150728199SRoman Kapl gen_addr_reg_index(ctx, t0); 498250728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 498350728199SRoman Kapl } 498450728199SRoman Kapl 4985fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4986fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4987fcf5ef2aSThomas Huth { 4988fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 49899f0cf041SMatheus Ferst GEN_PRIV(ctx); 4990fcf5ef2aSThomas Huth #else 4991fcf5ef2aSThomas Huth TCGv EA, val; 4992fcf5ef2aSThomas Huth 49939f0cf041SMatheus Ferst CHK_SV(ctx); 4994fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4995fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4996fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4997fcf5ef2aSThomas Huth val = tcg_temp_new(); 4998fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4999fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 5000fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 5001fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5002fcf5ef2aSThomas Huth } 5003fcf5ef2aSThomas Huth 5004fcf5ef2aSThomas Huth /* dcdst */ 5005fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 5006fcf5ef2aSThomas Huth { 5007fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 5008fcf5ef2aSThomas Huth TCGv t0; 5009fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5010fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5011fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5012fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 5013fcf5ef2aSThomas Huth } 5014fcf5ef2aSThomas Huth 501550728199SRoman Kapl /* dcbstep (dcbstep External PID version) */ 501650728199SRoman Kapl static void gen_dcbstep(DisasContext *ctx) 501750728199SRoman Kapl { 501850728199SRoman Kapl /* XXX: specification say this is treated as a load by the MMU */ 501950728199SRoman Kapl TCGv t0; 502050728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 502150728199SRoman Kapl t0 = tcg_temp_new(); 502250728199SRoman Kapl gen_addr_reg_index(ctx, t0); 502350728199SRoman Kapl tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); 502450728199SRoman Kapl } 502550728199SRoman Kapl 5026fcf5ef2aSThomas Huth /* dcbt */ 5027fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 5028fcf5ef2aSThomas Huth { 5029efe843d8SDavid Gibson /* 5030efe843d8SDavid Gibson * interpreted as no-op 5031efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5032efe843d8SDavid Gibson * does not generate any exception 5033fcf5ef2aSThomas Huth */ 5034fcf5ef2aSThomas Huth } 5035fcf5ef2aSThomas Huth 503650728199SRoman Kapl /* dcbtep */ 503750728199SRoman Kapl static void gen_dcbtep(DisasContext *ctx) 503850728199SRoman Kapl { 5039efe843d8SDavid Gibson /* 5040efe843d8SDavid Gibson * interpreted as no-op 5041efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5042efe843d8SDavid Gibson * does not generate any exception 504350728199SRoman Kapl */ 504450728199SRoman Kapl } 504550728199SRoman Kapl 5046fcf5ef2aSThomas Huth /* dcbtst */ 5047fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 5048fcf5ef2aSThomas Huth { 5049efe843d8SDavid Gibson /* 5050efe843d8SDavid Gibson * interpreted as no-op 5051efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5052efe843d8SDavid Gibson * does not generate any exception 5053fcf5ef2aSThomas Huth */ 5054fcf5ef2aSThomas Huth } 5055fcf5ef2aSThomas Huth 505650728199SRoman Kapl /* dcbtstep */ 505750728199SRoman Kapl static void gen_dcbtstep(DisasContext *ctx) 505850728199SRoman Kapl { 5059efe843d8SDavid Gibson /* 5060efe843d8SDavid Gibson * interpreted as no-op 5061efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5062efe843d8SDavid Gibson * does not generate any exception 506350728199SRoman Kapl */ 506450728199SRoman Kapl } 506550728199SRoman Kapl 5066fcf5ef2aSThomas Huth /* dcbtls */ 5067fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 5068fcf5ef2aSThomas Huth { 5069fcf5ef2aSThomas Huth /* Always fails locking the cache */ 5070fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5071fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 5072fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 5073fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 5074fcf5ef2aSThomas Huth } 5075fcf5ef2aSThomas Huth 5076e64645baSBernhard Beschow /* dcblc */ 5077e64645baSBernhard Beschow static void gen_dcblc(DisasContext *ctx) 5078e64645baSBernhard Beschow { 5079e64645baSBernhard Beschow /* 5080e64645baSBernhard Beschow * interpreted as no-op 5081e64645baSBernhard Beschow */ 5082e64645baSBernhard Beschow } 5083e64645baSBernhard Beschow 5084fcf5ef2aSThomas Huth /* dcbz */ 5085fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 5086fcf5ef2aSThomas Huth { 5087fcf5ef2aSThomas Huth TCGv tcgv_addr; 5088fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 5089fcf5ef2aSThomas Huth 5090fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5091fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 50927058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 5093fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 5094fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 5095fcf5ef2aSThomas Huth } 5096fcf5ef2aSThomas Huth 509750728199SRoman Kapl /* dcbzep */ 509850728199SRoman Kapl static void gen_dcbzep(DisasContext *ctx) 509950728199SRoman Kapl { 510050728199SRoman Kapl TCGv tcgv_addr; 510150728199SRoman Kapl TCGv_i32 tcgv_op; 510250728199SRoman Kapl 510350728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 510450728199SRoman Kapl tcgv_addr = tcg_temp_new(); 51057058ff52SRichard Henderson tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); 510650728199SRoman Kapl gen_addr_reg_index(ctx, tcgv_addr); 510750728199SRoman Kapl gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); 510850728199SRoman Kapl } 510950728199SRoman Kapl 5110fcf5ef2aSThomas Huth /* dst / dstt */ 5111fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 5112fcf5ef2aSThomas Huth { 5113fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5114fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5115fcf5ef2aSThomas Huth } else { 5116fcf5ef2aSThomas Huth /* interpreted as no-op */ 5117fcf5ef2aSThomas Huth } 5118fcf5ef2aSThomas Huth } 5119fcf5ef2aSThomas Huth 5120fcf5ef2aSThomas Huth /* dstst /dststt */ 5121fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 5122fcf5ef2aSThomas Huth { 5123fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 5124fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5125fcf5ef2aSThomas Huth } else { 5126fcf5ef2aSThomas Huth /* interpreted as no-op */ 5127fcf5ef2aSThomas Huth } 5128fcf5ef2aSThomas Huth 5129fcf5ef2aSThomas Huth } 5130fcf5ef2aSThomas Huth 5131fcf5ef2aSThomas Huth /* dss / dssall */ 5132fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 5133fcf5ef2aSThomas Huth { 5134fcf5ef2aSThomas Huth /* interpreted as no-op */ 5135fcf5ef2aSThomas Huth } 5136fcf5ef2aSThomas Huth 5137fcf5ef2aSThomas Huth /* icbi */ 5138fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 5139fcf5ef2aSThomas Huth { 5140fcf5ef2aSThomas Huth TCGv t0; 5141fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5142fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5143fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5144fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 5145fcf5ef2aSThomas Huth } 5146fcf5ef2aSThomas Huth 514750728199SRoman Kapl /* icbiep */ 514850728199SRoman Kapl static void gen_icbiep(DisasContext *ctx) 514950728199SRoman Kapl { 515050728199SRoman Kapl TCGv t0; 515150728199SRoman Kapl gen_set_access_type(ctx, ACCESS_CACHE); 515250728199SRoman Kapl t0 = tcg_temp_new(); 515350728199SRoman Kapl gen_addr_reg_index(ctx, t0); 515450728199SRoman Kapl gen_helper_icbiep(cpu_env, t0); 515550728199SRoman Kapl } 515650728199SRoman Kapl 5157fcf5ef2aSThomas Huth /* Optional: */ 5158fcf5ef2aSThomas Huth /* dcba */ 5159fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 5160fcf5ef2aSThomas Huth { 5161efe843d8SDavid Gibson /* 5162efe843d8SDavid Gibson * interpreted as no-op 5163efe843d8SDavid Gibson * XXX: specification say this is treated as a store by the MMU 5164fcf5ef2aSThomas Huth * but does not generate any exception 5165fcf5ef2aSThomas Huth */ 5166fcf5ef2aSThomas Huth } 5167fcf5ef2aSThomas Huth 5168fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 5169fcf5ef2aSThomas Huth /* Supervisor only: */ 5170fcf5ef2aSThomas Huth 5171fcf5ef2aSThomas Huth /* mfsr */ 5172fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 5173fcf5ef2aSThomas Huth { 5174fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51759f0cf041SMatheus Ferst GEN_PRIV(ctx); 5176fcf5ef2aSThomas Huth #else 5177fcf5ef2aSThomas Huth TCGv t0; 5178fcf5ef2aSThomas Huth 51799f0cf041SMatheus Ferst CHK_SV(ctx); 51807058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5181fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5182fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5183fcf5ef2aSThomas Huth } 5184fcf5ef2aSThomas Huth 5185fcf5ef2aSThomas Huth /* mfsrin */ 5186fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 5187fcf5ef2aSThomas Huth { 5188fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 51899f0cf041SMatheus Ferst GEN_PRIV(ctx); 5190fcf5ef2aSThomas Huth #else 5191fcf5ef2aSThomas Huth TCGv t0; 5192fcf5ef2aSThomas Huth 51939f0cf041SMatheus Ferst CHK_SV(ctx); 5194fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5195e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5196fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5197fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5198fcf5ef2aSThomas Huth } 5199fcf5ef2aSThomas Huth 5200fcf5ef2aSThomas Huth /* mtsr */ 5201fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 5202fcf5ef2aSThomas Huth { 5203fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52049f0cf041SMatheus Ferst GEN_PRIV(ctx); 5205fcf5ef2aSThomas Huth #else 5206fcf5ef2aSThomas Huth TCGv t0; 5207fcf5ef2aSThomas Huth 52089f0cf041SMatheus Ferst CHK_SV(ctx); 52097058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5210fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5211fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5212fcf5ef2aSThomas Huth } 5213fcf5ef2aSThomas Huth 5214fcf5ef2aSThomas Huth /* mtsrin */ 5215fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 5216fcf5ef2aSThomas Huth { 5217fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52189f0cf041SMatheus Ferst GEN_PRIV(ctx); 5219fcf5ef2aSThomas Huth #else 5220fcf5ef2aSThomas Huth TCGv t0; 52219f0cf041SMatheus Ferst CHK_SV(ctx); 5222fcf5ef2aSThomas Huth 5223fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5224e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5225fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 5226fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5227fcf5ef2aSThomas Huth } 5228fcf5ef2aSThomas Huth 5229fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 5230fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 5231fcf5ef2aSThomas Huth 5232fcf5ef2aSThomas Huth /* mfsr */ 5233fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 5234fcf5ef2aSThomas Huth { 5235fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52369f0cf041SMatheus Ferst GEN_PRIV(ctx); 5237fcf5ef2aSThomas Huth #else 5238fcf5ef2aSThomas Huth TCGv t0; 5239fcf5ef2aSThomas Huth 52409f0cf041SMatheus Ferst CHK_SV(ctx); 52417058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5242fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5243fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5244fcf5ef2aSThomas Huth } 5245fcf5ef2aSThomas Huth 5246fcf5ef2aSThomas Huth /* mfsrin */ 5247fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 5248fcf5ef2aSThomas Huth { 5249fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52509f0cf041SMatheus Ferst GEN_PRIV(ctx); 5251fcf5ef2aSThomas Huth #else 5252fcf5ef2aSThomas Huth TCGv t0; 5253fcf5ef2aSThomas Huth 52549f0cf041SMatheus Ferst CHK_SV(ctx); 5255fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5256e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5257fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5258fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5259fcf5ef2aSThomas Huth } 5260fcf5ef2aSThomas Huth 5261fcf5ef2aSThomas Huth /* mtsr */ 5262fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 5263fcf5ef2aSThomas Huth { 5264fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52659f0cf041SMatheus Ferst GEN_PRIV(ctx); 5266fcf5ef2aSThomas Huth #else 5267fcf5ef2aSThomas Huth TCGv t0; 5268fcf5ef2aSThomas Huth 52699f0cf041SMatheus Ferst CHK_SV(ctx); 52707058ff52SRichard Henderson t0 = tcg_constant_tl(SR(ctx->opcode)); 5271fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5272fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5273fcf5ef2aSThomas Huth } 5274fcf5ef2aSThomas Huth 5275fcf5ef2aSThomas Huth /* mtsrin */ 5276fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 5277fcf5ef2aSThomas Huth { 5278fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52799f0cf041SMatheus Ferst GEN_PRIV(ctx); 5280fcf5ef2aSThomas Huth #else 5281fcf5ef2aSThomas Huth TCGv t0; 5282fcf5ef2aSThomas Huth 52839f0cf041SMatheus Ferst CHK_SV(ctx); 5284fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5285e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 5286fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 5287fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5288fcf5ef2aSThomas Huth } 5289fcf5ef2aSThomas Huth 5290fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 5291fcf5ef2aSThomas Huth 5292fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 5293fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 5294fcf5ef2aSThomas Huth 5295fcf5ef2aSThomas Huth /* tlbia */ 5296fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 5297fcf5ef2aSThomas Huth { 5298fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 52999f0cf041SMatheus Ferst GEN_PRIV(ctx); 5300fcf5ef2aSThomas Huth #else 53019f0cf041SMatheus Ferst CHK_HV(ctx); 5302fcf5ef2aSThomas Huth 5303fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 5304fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5305fcf5ef2aSThomas Huth } 5306fcf5ef2aSThomas Huth 5307fcf5ef2aSThomas Huth /* tlbsync */ 5308fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 5309fcf5ef2aSThomas Huth { 5310fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53119f0cf041SMatheus Ferst GEN_PRIV(ctx); 5312fcf5ef2aSThomas Huth #else 531391c60f12SCédric Le Goater 531491c60f12SCédric Le Goater if (ctx->gtse) { 53159f0cf041SMatheus Ferst CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ 531691c60f12SCédric Le Goater } else { 53179f0cf041SMatheus Ferst CHK_HV(ctx); /* Else hypervisor privileged */ 531891c60f12SCédric Le Goater } 5319fcf5ef2aSThomas Huth 5320fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 5321fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 5322fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 5323fcf5ef2aSThomas Huth } 5324fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5325fcf5ef2aSThomas Huth } 5326fcf5ef2aSThomas Huth 5327fcf5ef2aSThomas Huth /*** External control ***/ 5328fcf5ef2aSThomas Huth /* Optional: */ 5329fcf5ef2aSThomas Huth 5330fcf5ef2aSThomas Huth /* eciwx */ 5331fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 5332fcf5ef2aSThomas Huth { 5333fcf5ef2aSThomas Huth TCGv t0; 5334fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5335fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5336fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5337fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5338c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5339c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5340fcf5ef2aSThomas Huth } 5341fcf5ef2aSThomas Huth 5342fcf5ef2aSThomas Huth /* ecowx */ 5343fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 5344fcf5ef2aSThomas Huth { 5345fcf5ef2aSThomas Huth TCGv t0; 5346fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 5347fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 5348fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5349fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5350c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 5351c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 5352fcf5ef2aSThomas Huth } 5353fcf5ef2aSThomas Huth 5354fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5355fcf5ef2aSThomas Huth 5356fcf5ef2aSThomas Huth /* tlbld */ 5357fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5358fcf5ef2aSThomas Huth { 5359fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53609f0cf041SMatheus Ferst GEN_PRIV(ctx); 5361fcf5ef2aSThomas Huth #else 53629f0cf041SMatheus Ferst CHK_SV(ctx); 5363fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5364fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5365fcf5ef2aSThomas Huth } 5366fcf5ef2aSThomas Huth 5367fcf5ef2aSThomas Huth /* tlbli */ 5368fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5369fcf5ef2aSThomas Huth { 5370fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53719f0cf041SMatheus Ferst GEN_PRIV(ctx); 5372fcf5ef2aSThomas Huth #else 53739f0cf041SMatheus Ferst CHK_SV(ctx); 5374fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5375fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5376fcf5ef2aSThomas Huth } 5377fcf5ef2aSThomas Huth 5378fcf5ef2aSThomas Huth /* BookE specific instructions */ 5379fcf5ef2aSThomas Huth 5380fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5381fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5382fcf5ef2aSThomas Huth { 5383fcf5ef2aSThomas Huth /* XXX: TODO */ 5384fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5385fcf5ef2aSThomas Huth } 5386fcf5ef2aSThomas Huth 5387fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5388fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5389fcf5ef2aSThomas Huth { 5390fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 53919f0cf041SMatheus Ferst GEN_PRIV(ctx); 5392fcf5ef2aSThomas Huth #else 5393fcf5ef2aSThomas Huth TCGv t0; 5394fcf5ef2aSThomas Huth 53959f0cf041SMatheus Ferst CHK_SV(ctx); 5396fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5397fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5398fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5399fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5400fcf5ef2aSThomas Huth } 5401fcf5ef2aSThomas Huth 5402fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5403fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5404fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5405fcf5ef2aSThomas Huth { 5406fcf5ef2aSThomas Huth TCGv t0, t1; 5407fcf5ef2aSThomas Huth 54089723281fSRichard Henderson t0 = tcg_temp_new(); 54099723281fSRichard Henderson t1 = tcg_temp_new(); 5410fcf5ef2aSThomas Huth 5411fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5412fcf5ef2aSThomas Huth case 0x05: 5413fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5414fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5415fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5416fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5417fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5418fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5419fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5420fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5421fcf5ef2aSThomas Huth break; 5422fcf5ef2aSThomas Huth case 0x04: 5423fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5424fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5425fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5426fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5427fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5428fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5429fcf5ef2aSThomas Huth break; 5430fcf5ef2aSThomas Huth case 0x01: 5431fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5432fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5433fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5434fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5435fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5436fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5437fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5438fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5439fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5440fcf5ef2aSThomas Huth break; 5441fcf5ef2aSThomas Huth case 0x00: 5442fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5443fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5444fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5445fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5446fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5447fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5448fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5449fcf5ef2aSThomas Huth break; 5450fcf5ef2aSThomas Huth case 0x0D: 5451fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5452fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5453fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5454fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5455fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5456fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5457fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5458fcf5ef2aSThomas Huth break; 5459fcf5ef2aSThomas Huth case 0x0C: 5460fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5461fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5462fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5463fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5464fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5465fcf5ef2aSThomas Huth break; 5466fcf5ef2aSThomas Huth } 5467fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5468fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5469fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5470fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5471fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5472fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5473fcf5ef2aSThomas Huth } else { 5474fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5475fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5476fcf5ef2aSThomas Huth } 5477fcf5ef2aSThomas Huth 5478fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5479fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5480fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5481fcf5ef2aSThomas Huth 5482fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5483fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5484fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5485fcf5ef2aSThomas Huth } 5486fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5487fcf5ef2aSThomas Huth /* Signed */ 5488fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5489fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5490fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5491fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5492fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5493fcf5ef2aSThomas Huth /* Saturate */ 5494fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5495fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5496fcf5ef2aSThomas Huth } 5497fcf5ef2aSThomas Huth } else { 5498fcf5ef2aSThomas Huth /* Unsigned */ 5499fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5500fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5501fcf5ef2aSThomas Huth /* Saturate */ 5502fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5503fcf5ef2aSThomas Huth } 5504fcf5ef2aSThomas Huth } 5505fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5506fcf5ef2aSThomas Huth /* Check overflow */ 5507fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5508fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5509fcf5ef2aSThomas Huth } 5510fcf5ef2aSThomas Huth gen_set_label(l1); 5511fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5512fcf5ef2aSThomas Huth } 5513fcf5ef2aSThomas Huth } else { 5514fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5515fcf5ef2aSThomas Huth } 5516fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5517fcf5ef2aSThomas Huth /* Update Rc0 */ 5518fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5519fcf5ef2aSThomas Huth } 5520fcf5ef2aSThomas Huth } 5521fcf5ef2aSThomas Huth 5522fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5523fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5524fcf5ef2aSThomas Huth { \ 5525fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5526fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5527fcf5ef2aSThomas Huth } 5528fcf5ef2aSThomas Huth 5529fcf5ef2aSThomas Huth /* macchw - macchw. */ 5530fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5531fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5532fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5533fcf5ef2aSThomas Huth /* macchws - macchws. */ 5534fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5535fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5536fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5537fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5538fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5539fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5540fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5541fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5542fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5543fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5544fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5545fcf5ef2aSThomas Huth /* machhw - machhw. */ 5546fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5547fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5548fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5549fcf5ef2aSThomas Huth /* machhws - machhws. */ 5550fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5551fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5552fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5553fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5554fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5555fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5556fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5557fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5558fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5559fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5560fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5561fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5562fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5563fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5564fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5565fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5566fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5567fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5568fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5569fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5570fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5571fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5572fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5573fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5574fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5575fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5576fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5577fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5578fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5579fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5580fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5581fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5582fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5583fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5584fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5585fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5586fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5587fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5588fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5589fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5590fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5591fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5592fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5593fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5594fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5595fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5596fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5597fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5598fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5599fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5600fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5601fcf5ef2aSThomas Huth 5602fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5603fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5604fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5605fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5606fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5607fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5608fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5609fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5610fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5611fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5612fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5613fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5614fcf5ef2aSThomas Huth 5615fcf5ef2aSThomas Huth /* mfdcr */ 5616fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5617fcf5ef2aSThomas Huth { 5618fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56199f0cf041SMatheus Ferst GEN_PRIV(ctx); 5620fcf5ef2aSThomas Huth #else 5621fcf5ef2aSThomas Huth TCGv dcrn; 5622fcf5ef2aSThomas Huth 56239f0cf041SMatheus Ferst CHK_SV(ctx); 56247058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5625fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5626fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5627fcf5ef2aSThomas Huth } 5628fcf5ef2aSThomas Huth 5629fcf5ef2aSThomas Huth /* mtdcr */ 5630fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5631fcf5ef2aSThomas Huth { 5632fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56339f0cf041SMatheus Ferst GEN_PRIV(ctx); 5634fcf5ef2aSThomas Huth #else 5635fcf5ef2aSThomas Huth TCGv dcrn; 5636fcf5ef2aSThomas Huth 56379f0cf041SMatheus Ferst CHK_SV(ctx); 56387058ff52SRichard Henderson dcrn = tcg_constant_tl(SPR(ctx->opcode)); 5639fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5640fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5641fcf5ef2aSThomas Huth } 5642fcf5ef2aSThomas Huth 5643fcf5ef2aSThomas Huth /* mfdcrx */ 5644fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5645fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5646fcf5ef2aSThomas Huth { 5647fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56489f0cf041SMatheus Ferst GEN_PRIV(ctx); 5649fcf5ef2aSThomas Huth #else 56509f0cf041SMatheus Ferst CHK_SV(ctx); 5651fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5652fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5653fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5654fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5655fcf5ef2aSThomas Huth } 5656fcf5ef2aSThomas Huth 5657fcf5ef2aSThomas Huth /* mtdcrx */ 5658fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5659fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5660fcf5ef2aSThomas Huth { 5661fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56629f0cf041SMatheus Ferst GEN_PRIV(ctx); 5663fcf5ef2aSThomas Huth #else 56649f0cf041SMatheus Ferst CHK_SV(ctx); 5665fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5666fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5667fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5668fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5669fcf5ef2aSThomas Huth } 5670fcf5ef2aSThomas Huth 5671fcf5ef2aSThomas Huth /* dccci */ 5672fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5673fcf5ef2aSThomas Huth { 56749f0cf041SMatheus Ferst CHK_SV(ctx); 5675fcf5ef2aSThomas Huth /* interpreted as no-op */ 5676fcf5ef2aSThomas Huth } 5677fcf5ef2aSThomas Huth 5678fcf5ef2aSThomas Huth /* dcread */ 5679fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5680fcf5ef2aSThomas Huth { 5681fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 56829f0cf041SMatheus Ferst GEN_PRIV(ctx); 5683fcf5ef2aSThomas Huth #else 5684fcf5ef2aSThomas Huth TCGv EA, val; 5685fcf5ef2aSThomas Huth 56869f0cf041SMatheus Ferst CHK_SV(ctx); 5687fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5688fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5689fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5690fcf5ef2aSThomas Huth val = tcg_temp_new(); 5691fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5692fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5693fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5694fcf5ef2aSThomas Huth } 5695fcf5ef2aSThomas Huth 5696fcf5ef2aSThomas Huth /* icbt */ 5697fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5698fcf5ef2aSThomas Huth { 5699efe843d8SDavid Gibson /* 5700efe843d8SDavid Gibson * interpreted as no-op 5701efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 5702efe843d8SDavid Gibson * does not generate any exception 5703fcf5ef2aSThomas Huth */ 5704fcf5ef2aSThomas Huth } 5705fcf5ef2aSThomas Huth 5706fcf5ef2aSThomas Huth /* iccci */ 5707fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5708fcf5ef2aSThomas Huth { 57099f0cf041SMatheus Ferst CHK_SV(ctx); 5710fcf5ef2aSThomas Huth /* interpreted as no-op */ 5711fcf5ef2aSThomas Huth } 5712fcf5ef2aSThomas Huth 5713fcf5ef2aSThomas Huth /* icread */ 5714fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5715fcf5ef2aSThomas Huth { 57169f0cf041SMatheus Ferst CHK_SV(ctx); 5717fcf5ef2aSThomas Huth /* interpreted as no-op */ 5718fcf5ef2aSThomas Huth } 5719fcf5ef2aSThomas Huth 5720fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5721fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5722fcf5ef2aSThomas Huth { 5723fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57249f0cf041SMatheus Ferst GEN_PRIV(ctx); 5725fcf5ef2aSThomas Huth #else 57269f0cf041SMatheus Ferst CHK_SV(ctx); 5727fcf5ef2aSThomas Huth /* Restore CPU state */ 5728fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 572959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5730fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5731fcf5ef2aSThomas Huth } 5732fcf5ef2aSThomas Huth 5733fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5734fcf5ef2aSThomas Huth { 5735fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57369f0cf041SMatheus Ferst GEN_PRIV(ctx); 5737fcf5ef2aSThomas Huth #else 57389f0cf041SMatheus Ferst CHK_SV(ctx); 5739fcf5ef2aSThomas Huth /* Restore CPU state */ 5740fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 574159bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5742fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5743fcf5ef2aSThomas Huth } 5744fcf5ef2aSThomas Huth 5745fcf5ef2aSThomas Huth /* BookE specific */ 5746fcf5ef2aSThomas Huth 5747fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5748fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5749fcf5ef2aSThomas Huth { 5750fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57519f0cf041SMatheus Ferst GEN_PRIV(ctx); 5752fcf5ef2aSThomas Huth #else 57539f0cf041SMatheus Ferst CHK_SV(ctx); 5754fcf5ef2aSThomas Huth /* Restore CPU state */ 5755fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 575659bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5757fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5758fcf5ef2aSThomas Huth } 5759fcf5ef2aSThomas Huth 5760fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5761fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5762fcf5ef2aSThomas Huth { 5763fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57649f0cf041SMatheus Ferst GEN_PRIV(ctx); 5765fcf5ef2aSThomas Huth #else 57669f0cf041SMatheus Ferst CHK_SV(ctx); 5767fcf5ef2aSThomas Huth /* Restore CPU state */ 5768fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 576959bf23faSRichard Henderson ctx->base.is_jmp = DISAS_EXIT; 5770fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5771fcf5ef2aSThomas Huth } 5772fcf5ef2aSThomas Huth 5773fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5774fcf5ef2aSThomas Huth 5775fcf5ef2aSThomas Huth /* tlbre */ 5776fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5777fcf5ef2aSThomas Huth { 5778fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 57799f0cf041SMatheus Ferst GEN_PRIV(ctx); 5780fcf5ef2aSThomas Huth #else 57819f0cf041SMatheus Ferst CHK_SV(ctx); 5782fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5783fcf5ef2aSThomas Huth case 0: 5784fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5785fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5786fcf5ef2aSThomas Huth break; 5787fcf5ef2aSThomas Huth case 1: 5788fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5789fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5790fcf5ef2aSThomas Huth break; 5791fcf5ef2aSThomas Huth default: 5792fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5793fcf5ef2aSThomas Huth break; 5794fcf5ef2aSThomas Huth } 5795fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5796fcf5ef2aSThomas Huth } 5797fcf5ef2aSThomas Huth 5798fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5799fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5800fcf5ef2aSThomas Huth { 5801fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58029f0cf041SMatheus Ferst GEN_PRIV(ctx); 5803fcf5ef2aSThomas Huth #else 5804fcf5ef2aSThomas Huth TCGv t0; 5805fcf5ef2aSThomas Huth 58069f0cf041SMatheus Ferst CHK_SV(ctx); 5807fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5808fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5809fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5810fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5811fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5812fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5813fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5814fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5815fcf5ef2aSThomas Huth gen_set_label(l1); 5816fcf5ef2aSThomas Huth } 5817fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5818fcf5ef2aSThomas Huth } 5819fcf5ef2aSThomas Huth 5820fcf5ef2aSThomas Huth /* tlbwe */ 5821fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5822fcf5ef2aSThomas Huth { 5823fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58249f0cf041SMatheus Ferst GEN_PRIV(ctx); 5825fcf5ef2aSThomas Huth #else 58269f0cf041SMatheus Ferst CHK_SV(ctx); 5827fcf5ef2aSThomas Huth 5828fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5829fcf5ef2aSThomas Huth case 0: 5830fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5831fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5832fcf5ef2aSThomas Huth break; 5833fcf5ef2aSThomas Huth case 1: 5834fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5835fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5836fcf5ef2aSThomas Huth break; 5837fcf5ef2aSThomas Huth default: 5838fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5839fcf5ef2aSThomas Huth break; 5840fcf5ef2aSThomas Huth } 5841fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5842fcf5ef2aSThomas Huth } 5843fcf5ef2aSThomas Huth 5844fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5845fcf5ef2aSThomas Huth 5846fcf5ef2aSThomas Huth /* tlbre */ 5847fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5848fcf5ef2aSThomas Huth { 5849fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58509f0cf041SMatheus Ferst GEN_PRIV(ctx); 5851fcf5ef2aSThomas Huth #else 58529f0cf041SMatheus Ferst CHK_SV(ctx); 5853fcf5ef2aSThomas Huth 5854fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5855fcf5ef2aSThomas Huth case 0: 5856fcf5ef2aSThomas Huth case 1: 5857fcf5ef2aSThomas Huth case 2: 5858fcf5ef2aSThomas Huth { 58597058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5860fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5861fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5862fcf5ef2aSThomas Huth } 5863fcf5ef2aSThomas Huth break; 5864fcf5ef2aSThomas Huth default: 5865fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5866fcf5ef2aSThomas Huth break; 5867fcf5ef2aSThomas Huth } 5868fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5869fcf5ef2aSThomas Huth } 5870fcf5ef2aSThomas Huth 5871fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5872fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5873fcf5ef2aSThomas Huth { 5874fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58759f0cf041SMatheus Ferst GEN_PRIV(ctx); 5876fcf5ef2aSThomas Huth #else 5877fcf5ef2aSThomas Huth TCGv t0; 5878fcf5ef2aSThomas Huth 58799f0cf041SMatheus Ferst CHK_SV(ctx); 5880fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5881fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5882fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5883fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5884fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5885fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5886fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5887fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5888fcf5ef2aSThomas Huth gen_set_label(l1); 5889fcf5ef2aSThomas Huth } 5890fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5891fcf5ef2aSThomas Huth } 5892fcf5ef2aSThomas Huth 5893fcf5ef2aSThomas Huth /* tlbwe */ 5894fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 5895fcf5ef2aSThomas Huth { 5896fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 58979f0cf041SMatheus Ferst GEN_PRIV(ctx); 5898fcf5ef2aSThomas Huth #else 58999f0cf041SMatheus Ferst CHK_SV(ctx); 5900fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5901fcf5ef2aSThomas Huth case 0: 5902fcf5ef2aSThomas Huth case 1: 5903fcf5ef2aSThomas Huth case 2: 5904fcf5ef2aSThomas Huth { 59057058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); 5906fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 5907fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5908fcf5ef2aSThomas Huth } 5909fcf5ef2aSThomas Huth break; 5910fcf5ef2aSThomas Huth default: 5911fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5912fcf5ef2aSThomas Huth break; 5913fcf5ef2aSThomas Huth } 5914fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5915fcf5ef2aSThomas Huth } 5916fcf5ef2aSThomas Huth 5917fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 5918fcf5ef2aSThomas Huth 5919fcf5ef2aSThomas Huth /* tlbre */ 5920fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 5921fcf5ef2aSThomas Huth { 5922fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59239f0cf041SMatheus Ferst GEN_PRIV(ctx); 5924fcf5ef2aSThomas Huth #else 59259f0cf041SMatheus Ferst CHK_SV(ctx); 5926fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 5927fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5928fcf5ef2aSThomas Huth } 5929fcf5ef2aSThomas Huth 5930fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5931fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 5932fcf5ef2aSThomas Huth { 5933fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59349f0cf041SMatheus Ferst GEN_PRIV(ctx); 5935fcf5ef2aSThomas Huth #else 5936fcf5ef2aSThomas Huth TCGv t0; 5937fcf5ef2aSThomas Huth 59389f0cf041SMatheus Ferst CHK_SV(ctx); 5939fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 5940fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 59419d15d8e1SRichard Henderson tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5942fcf5ef2aSThomas Huth } else { 59439d15d8e1SRichard Henderson t0 = cpu_gpr[rB(ctx->opcode)]; 5944fcf5ef2aSThomas Huth } 5945fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 5946fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5947fcf5ef2aSThomas Huth } 5948fcf5ef2aSThomas Huth 5949fcf5ef2aSThomas Huth /* tlbwe */ 5950fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 5951fcf5ef2aSThomas Huth { 5952fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59539f0cf041SMatheus Ferst GEN_PRIV(ctx); 5954fcf5ef2aSThomas Huth #else 59559f0cf041SMatheus Ferst CHK_SV(ctx); 5956fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 5957fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5958fcf5ef2aSThomas Huth } 5959fcf5ef2aSThomas Huth 5960fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 5961fcf5ef2aSThomas Huth { 5962fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59639f0cf041SMatheus Ferst GEN_PRIV(ctx); 5964fcf5ef2aSThomas Huth #else 5965fcf5ef2aSThomas Huth TCGv t0; 5966fcf5ef2aSThomas Huth 59679f0cf041SMatheus Ferst CHK_SV(ctx); 5968fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5969fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5970fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 5971fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5972fcf5ef2aSThomas Huth } 5973fcf5ef2aSThomas Huth 5974fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 5975fcf5ef2aSThomas Huth { 5976fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 59779f0cf041SMatheus Ferst GEN_PRIV(ctx); 5978fcf5ef2aSThomas Huth #else 5979fcf5ef2aSThomas Huth TCGv t0; 5980fcf5ef2aSThomas Huth 59819f0cf041SMatheus Ferst CHK_SV(ctx); 5982fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5983fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5984fcf5ef2aSThomas Huth 5985fcf5ef2aSThomas Huth switch ((ctx->opcode >> 21) & 0x3) { 5986fcf5ef2aSThomas Huth case 0: 5987fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 5988fcf5ef2aSThomas Huth break; 5989fcf5ef2aSThomas Huth case 1: 5990fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 5991fcf5ef2aSThomas Huth break; 5992fcf5ef2aSThomas Huth case 3: 5993fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 5994fcf5ef2aSThomas Huth break; 5995fcf5ef2aSThomas Huth default: 5996fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5997fcf5ef2aSThomas Huth break; 5998fcf5ef2aSThomas Huth } 5999fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6000fcf5ef2aSThomas Huth } 6001fcf5ef2aSThomas Huth 6002fcf5ef2aSThomas Huth /* wrtee */ 6003fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6004fcf5ef2aSThomas Huth { 6005fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60069f0cf041SMatheus Ferst GEN_PRIV(ctx); 6007fcf5ef2aSThomas Huth #else 6008fcf5ef2aSThomas Huth TCGv t0; 6009fcf5ef2aSThomas Huth 60109f0cf041SMatheus Ferst CHK_SV(ctx); 6011fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6012fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6013fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6014fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 60152fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6016efe843d8SDavid Gibson /* 6017efe843d8SDavid Gibson * Stop translation to have a chance to raise an exception if we 6018efe843d8SDavid Gibson * just set msr_ee to 1 6019fcf5ef2aSThomas Huth */ 6020d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6021fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6022fcf5ef2aSThomas Huth } 6023fcf5ef2aSThomas Huth 6024fcf5ef2aSThomas Huth /* wrteei */ 6025fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6026fcf5ef2aSThomas Huth { 6027fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 60289f0cf041SMatheus Ferst GEN_PRIV(ctx); 6029fcf5ef2aSThomas Huth #else 60309f0cf041SMatheus Ferst CHK_SV(ctx); 6031fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6032fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 60332fdedcbcSMatheus Ferst gen_ppc_maybe_interrupt(ctx); 6034fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6035d736de8fSRichard Henderson ctx->base.is_jmp = DISAS_EXIT_UPDATE; 6036fcf5ef2aSThomas Huth } else { 6037fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6038fcf5ef2aSThomas Huth } 6039fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6040fcf5ef2aSThomas Huth } 6041fcf5ef2aSThomas Huth 6042fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6043fcf5ef2aSThomas Huth 6044fcf5ef2aSThomas Huth /* dlmzb */ 6045fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6046fcf5ef2aSThomas Huth { 60477058ff52SRichard Henderson TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); 6048fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6049fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6050fcf5ef2aSThomas Huth } 6051fcf5ef2aSThomas Huth 6052fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6053fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6054fcf5ef2aSThomas Huth { 6055fcf5ef2aSThomas Huth /* interpreted as no-op */ 6056fcf5ef2aSThomas Huth } 6057fcf5ef2aSThomas Huth 6058fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6059fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6060fcf5ef2aSThomas Huth { 606127a3ea7eSBALATON Zoltan /* Only e500 seems to treat reserved bits as invalid */ 606227a3ea7eSBALATON Zoltan if ((ctx->insns_flags2 & PPC2_BOOKE206) && 606327a3ea7eSBALATON Zoltan (ctx->opcode & 0x03FFF801)) { 606427a3ea7eSBALATON Zoltan gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 606527a3ea7eSBALATON Zoltan } 606627a3ea7eSBALATON Zoltan /* otherwise interpreted as no-op */ 6067fcf5ef2aSThomas Huth } 6068fcf5ef2aSThomas Huth 6069fcf5ef2aSThomas Huth /* icbt */ 6070fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6071fcf5ef2aSThomas Huth { 6072efe843d8SDavid Gibson /* 6073efe843d8SDavid Gibson * interpreted as no-op 6074efe843d8SDavid Gibson * XXX: specification say this is treated as a load by the MMU but 6075efe843d8SDavid Gibson * does not generate any exception 6076fcf5ef2aSThomas Huth */ 6077fcf5ef2aSThomas Huth } 6078fcf5ef2aSThomas Huth 6079fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6080fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6081fcf5ef2aSThomas Huth { 6082fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6083fcf5ef2aSThomas Huth 6084fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6085fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6086fcf5ef2aSThomas Huth } 6087fcf5ef2aSThomas Huth 6088fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6089fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6090fcf5ef2aSThomas Huth { 6091fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6092fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6093fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6094fcf5ef2aSThomas Huth 6095fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6096fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6097fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6098fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6099fcf5ef2aSThomas Huth } else { 6100fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6101fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6102fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6103fcf5ef2aSThomas Huth } 6104fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6105fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6106fcf5ef2aSThomas Huth } 6107fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6108fcf5ef2aSThomas Huth 6109fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6110fcf5ef2aSThomas Huth { 6111fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6112fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6113fcf5ef2aSThomas Huth return; 6114fcf5ef2aSThomas Huth } 6115fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6116fcf5ef2aSThomas Huth } 6117fcf5ef2aSThomas Huth 6118fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6119fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6120fcf5ef2aSThomas Huth { \ 6121fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6122fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6123fcf5ef2aSThomas Huth return; \ 6124fcf5ef2aSThomas Huth } \ 6125efe843d8SDavid Gibson /* \ 6126efe843d8SDavid Gibson * Because tbegin always fails in QEMU, these user \ 6127fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6128fcf5ef2aSThomas Huth * \ 6129fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6130fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6131fcf5ef2aSThomas Huth */ \ 6132fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6133fcf5ef2aSThomas Huth } 6134fcf5ef2aSThomas Huth 6135fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6136fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6137fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6138fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6139fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6140fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6141fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6142efe843d8SDavid Gibson 6143b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6144b8b4576eSSuraj Jitindar Singh { 6145efe843d8SDavid Gibson /* Do Nothing */ 6146b8b4576eSSuraj Jitindar Singh } 6147fcf5ef2aSThomas Huth 614880b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 614980b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 615080b8c1eeSNikunj A Dadhania { \ 6151efe843d8SDavid Gibson /* \ 6152efe843d8SDavid Gibson * Generate invalid exception until we have an \ 6153efe843d8SDavid Gibson * implementation of the copy paste facility \ 615480b8c1eeSNikunj A Dadhania */ \ 615580b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 615680b8c1eeSNikunj A Dadhania } 615780b8c1eeSNikunj A Dadhania 615880b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 615980b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 616080b8c1eeSNikunj A Dadhania 6161fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6162fcf5ef2aSThomas Huth { 6163fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6164fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6165fcf5ef2aSThomas Huth return; 6166fcf5ef2aSThomas Huth } 6167efe843d8SDavid Gibson /* 6168efe843d8SDavid Gibson * Because tbegin always fails, the tcheck implementation is 6169efe843d8SDavid Gibson * simple: 6170fcf5ef2aSThomas Huth * 6171fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6172fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6173fcf5ef2aSThomas Huth */ 6174fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6175fcf5ef2aSThomas Huth } 6176fcf5ef2aSThomas Huth 6177fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6178fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6179fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6180fcf5ef2aSThomas Huth { \ 61819f0cf041SMatheus Ferst gen_priv_opc(ctx); \ 6182fcf5ef2aSThomas Huth } 6183fcf5ef2aSThomas Huth 6184fcf5ef2aSThomas Huth #else 6185fcf5ef2aSThomas Huth 6186fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6187fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6188fcf5ef2aSThomas Huth { \ 61899f0cf041SMatheus Ferst CHK_SV(ctx); \ 6190fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6191fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6192fcf5ef2aSThomas Huth return; \ 6193fcf5ef2aSThomas Huth } \ 6194efe843d8SDavid Gibson /* \ 6195efe843d8SDavid Gibson * Because tbegin always fails, the implementation is \ 6196fcf5ef2aSThomas Huth * simple: \ 6197fcf5ef2aSThomas Huth * \ 6198fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6199fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6200fcf5ef2aSThomas Huth */ \ 6201fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6202fcf5ef2aSThomas Huth } 6203fcf5ef2aSThomas Huth 6204fcf5ef2aSThomas Huth #endif 6205fcf5ef2aSThomas Huth 6206fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6207fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6208fcf5ef2aSThomas Huth 62091a404c91SMark Cave-Ayland static inline void get_fpr(TCGv_i64 dst, int regno) 62101a404c91SMark Cave-Ayland { 6211e7d3b272SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); 62121a404c91SMark Cave-Ayland } 62131a404c91SMark Cave-Ayland 62141a404c91SMark Cave-Ayland static inline void set_fpr(int regno, TCGv_i64 src) 62151a404c91SMark Cave-Ayland { 6216e7d3b272SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); 62174b65b6e7SVíctor Colombo /* 62184b65b6e7SVíctor Colombo * Before PowerISA v3.1 the result of doubleword 1 of the VSR 62194b65b6e7SVíctor Colombo * corresponding to the target FPR was undefined. However, 62204b65b6e7SVíctor Colombo * most (if not all) real hardware were setting the result to 0. 62214b65b6e7SVíctor Colombo * Starting at ISA v3.1, the result for doubleword 1 is now defined 62224b65b6e7SVíctor Colombo * to be 0. 62234b65b6e7SVíctor Colombo */ 62244b65b6e7SVíctor Colombo tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); 62251a404c91SMark Cave-Ayland } 62261a404c91SMark Cave-Ayland 6227c4a18dbfSMark Cave-Ayland static inline void get_avr64(TCGv_i64 dst, int regno, bool high) 6228c4a18dbfSMark Cave-Ayland { 622937da91f1SMark Cave-Ayland tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); 6230c4a18dbfSMark Cave-Ayland } 6231c4a18dbfSMark Cave-Ayland 6232c4a18dbfSMark Cave-Ayland static inline void set_avr64(int regno, TCGv_i64 src, bool high) 6233c4a18dbfSMark Cave-Ayland { 623437da91f1SMark Cave-Ayland tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); 6235c4a18dbfSMark Cave-Ayland } 6236c4a18dbfSMark Cave-Ayland 6237c9826ae9SRichard Henderson /* 6238f2aabda8SRichard Henderson * Helpers for decodetree used by !function for decoding arguments. 6239f2aabda8SRichard Henderson */ 6240d39b2cc7SLuis Pires static int times_2(DisasContext *ctx, int x) 6241d39b2cc7SLuis Pires { 6242d39b2cc7SLuis Pires return x * 2; 6243d39b2cc7SLuis Pires } 6244d39b2cc7SLuis Pires 6245f2aabda8SRichard Henderson static int times_4(DisasContext *ctx, int x) 6246f2aabda8SRichard Henderson { 6247f2aabda8SRichard Henderson return x * 4; 6248f2aabda8SRichard Henderson } 6249f2aabda8SRichard Henderson 6250e10271e1SMatheus Ferst static int times_16(DisasContext *ctx, int x) 6251e10271e1SMatheus Ferst { 6252e10271e1SMatheus Ferst return x * 16; 6253e10271e1SMatheus Ferst } 6254e10271e1SMatheus Ferst 6255670f1da3SVíctor Colombo static int64_t dw_compose_ea(DisasContext *ctx, int x) 6256670f1da3SVíctor Colombo { 6257670f1da3SVíctor Colombo return deposit64(0xfffffffffffffe00, 3, 6, x); 6258670f1da3SVíctor Colombo } 6259670f1da3SVíctor Colombo 6260f2aabda8SRichard Henderson /* 6261c9826ae9SRichard Henderson * Helpers for trans_* functions to check for specific insns flags. 6262c9826ae9SRichard Henderson * Use token pasting to ensure that we use the proper flag with the 6263c9826ae9SRichard Henderson * proper variable. 6264c9826ae9SRichard Henderson */ 6265c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ 6266c9826ae9SRichard Henderson do { \ 6267c9826ae9SRichard Henderson if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ 6268c9826ae9SRichard Henderson return false; \ 6269c9826ae9SRichard Henderson } \ 6270c9826ae9SRichard Henderson } while (0) 6271c9826ae9SRichard Henderson 6272c9826ae9SRichard Henderson #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ 6273c9826ae9SRichard Henderson do { \ 6274c9826ae9SRichard Henderson if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ 6275c9826ae9SRichard Henderson return false; \ 6276c9826ae9SRichard Henderson } \ 6277c9826ae9SRichard Henderson } while (0) 6278c9826ae9SRichard Henderson 6279c9826ae9SRichard Henderson /* Then special-case the check for 64-bit so that we elide code for ppc32. */ 6280c9826ae9SRichard Henderson #if TARGET_LONG_BITS == 32 6281c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) return false 6282c9826ae9SRichard Henderson #else 6283c9826ae9SRichard Henderson # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) 6284c9826ae9SRichard Henderson #endif 6285c9826ae9SRichard Henderson 6286e2205a46SBruno Larsen #define REQUIRE_VECTOR(CTX) \ 6287e2205a46SBruno Larsen do { \ 6288e2205a46SBruno Larsen if (unlikely(!(CTX)->altivec_enabled)) { \ 6289e2205a46SBruno Larsen gen_exception((CTX), POWERPC_EXCP_VPU); \ 6290e2205a46SBruno Larsen return true; \ 6291e2205a46SBruno Larsen } \ 6292e2205a46SBruno Larsen } while (0) 6293e2205a46SBruno Larsen 62948226cb2dSBruno Larsen (billionai) #define REQUIRE_VSX(CTX) \ 62958226cb2dSBruno Larsen (billionai) do { \ 62968226cb2dSBruno Larsen (billionai) if (unlikely(!(CTX)->vsx_enabled)) { \ 62978226cb2dSBruno Larsen (billionai) gen_exception((CTX), POWERPC_EXCP_VSXU); \ 62988226cb2dSBruno Larsen (billionai) return true; \ 62998226cb2dSBruno Larsen (billionai) } \ 63008226cb2dSBruno Larsen (billionai) } while (0) 63018226cb2dSBruno Larsen (billionai) 630286057426SFernando Valle #define REQUIRE_FPU(ctx) \ 630386057426SFernando Valle do { \ 630486057426SFernando Valle if (unlikely(!(ctx)->fpu_enabled)) { \ 630586057426SFernando Valle gen_exception((ctx), POWERPC_EXCP_FPU); \ 630686057426SFernando Valle return true; \ 630786057426SFernando Valle } \ 630886057426SFernando Valle } while (0) 630986057426SFernando Valle 6310fc34e81aSMatheus Ferst #if !defined(CONFIG_USER_ONLY) 6311fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) \ 6312fc34e81aSMatheus Ferst do { \ 6313fc34e81aSMatheus Ferst if (unlikely((CTX)->pr)) { \ 6314fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6315fc34e81aSMatheus Ferst return true; \ 6316fc34e81aSMatheus Ferst } \ 6317fc34e81aSMatheus Ferst } while (0) 6318fc34e81aSMatheus Ferst 6319fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) \ 6320fc34e81aSMatheus Ferst do { \ 6321e8db3cc7SMatheus Ferst if (unlikely((CTX)->pr || !(CTX)->hv)) { \ 6322fc34e81aSMatheus Ferst gen_priv_opc(CTX); \ 6323fc34e81aSMatheus Ferst return true; \ 6324fc34e81aSMatheus Ferst } \ 6325fc34e81aSMatheus Ferst } while (0) 6326fc34e81aSMatheus Ferst #else 6327fc34e81aSMatheus Ferst #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6328fc34e81aSMatheus Ferst #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) 6329fc34e81aSMatheus Ferst #endif 6330fc34e81aSMatheus Ferst 6331f2aabda8SRichard Henderson /* 6332f2aabda8SRichard Henderson * Helpers for implementing sets of trans_* functions. 6333f2aabda8SRichard Henderson * Defer the implementation of NAME to FUNC, with optional extra arguments. 6334f2aabda8SRichard Henderson */ 6335f2aabda8SRichard Henderson #define TRANS(NAME, FUNC, ...) \ 6336f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6337f2aabda8SRichard Henderson { return FUNC(ctx, a, __VA_ARGS__); } 633819f0862dSLuis Pires #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ 633919f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 634019f0862dSLuis Pires { \ 634119f0862dSLuis Pires REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ 634219f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 634319f0862dSLuis Pires } 634419f0862dSLuis Pires #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 634519f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 634619f0862dSLuis Pires { \ 634719f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 634819f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 634919f0862dSLuis Pires } 6350f2aabda8SRichard Henderson 6351f2aabda8SRichard Henderson #define TRANS64(NAME, FUNC, ...) \ 6352f2aabda8SRichard Henderson static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 6353f2aabda8SRichard Henderson { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } 635419f0862dSLuis Pires #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ 635519f0862dSLuis Pires static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 635619f0862dSLuis Pires { \ 635719f0862dSLuis Pires REQUIRE_64BIT(ctx); \ 635819f0862dSLuis Pires REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ 635919f0862dSLuis Pires return FUNC(ctx, a, __VA_ARGS__); \ 636019f0862dSLuis Pires } 6361f2aabda8SRichard Henderson 6362f2aabda8SRichard Henderson /* TODO: More TRANS* helpers for extra insn_flags checks. */ 6363f2aabda8SRichard Henderson 6364f2aabda8SRichard Henderson 636599082815SRichard Henderson #include "decode-insn32.c.inc" 636699082815SRichard Henderson #include "decode-insn64.c.inc" 6367565cb109SGustavo Romero #include "power8-pmu-regs.c.inc" 6368565cb109SGustavo Romero 6369725b2d4dSFernando Eckhardt Valle /* 6370725b2d4dSFernando Eckhardt Valle * Incorporate CIA into the constant when R=1. 6371725b2d4dSFernando Eckhardt Valle * Validate that when R=1, RA=0. 6372725b2d4dSFernando Eckhardt Valle */ 6373725b2d4dSFernando Eckhardt Valle static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) 6374725b2d4dSFernando Eckhardt Valle { 6375725b2d4dSFernando Eckhardt Valle d->rt = a->rt; 6376725b2d4dSFernando Eckhardt Valle d->ra = a->ra; 6377725b2d4dSFernando Eckhardt Valle d->si = a->si; 6378725b2d4dSFernando Eckhardt Valle if (a->r) { 6379725b2d4dSFernando Eckhardt Valle if (unlikely(a->ra != 0)) { 6380725b2d4dSFernando Eckhardt Valle gen_invalid(ctx); 6381725b2d4dSFernando Eckhardt Valle return false; 6382725b2d4dSFernando Eckhardt Valle } 6383725b2d4dSFernando Eckhardt Valle d->si += ctx->cia; 6384725b2d4dSFernando Eckhardt Valle } 6385725b2d4dSFernando Eckhardt Valle return true; 6386725b2d4dSFernando Eckhardt Valle } 6387725b2d4dSFernando Eckhardt Valle 638899082815SRichard Henderson #include "translate/fixedpoint-impl.c.inc" 638999082815SRichard Henderson 6390139c1837SPaolo Bonzini #include "translate/fp-impl.c.inc" 6391fcf5ef2aSThomas Huth 6392139c1837SPaolo Bonzini #include "translate/vmx-impl.c.inc" 6393fcf5ef2aSThomas Huth 6394139c1837SPaolo Bonzini #include "translate/vsx-impl.c.inc" 6395fcf5ef2aSThomas Huth 6396139c1837SPaolo Bonzini #include "translate/dfp-impl.c.inc" 6397fcf5ef2aSThomas Huth 6398139c1837SPaolo Bonzini #include "translate/spe-impl.c.inc" 6399fcf5ef2aSThomas Huth 64001f26c751SDaniel Henrique Barboza #include "translate/branch-impl.c.inc" 64011f26c751SDaniel Henrique Barboza 640298f43417SMatheus Ferst #include "translate/processor-ctrl-impl.c.inc" 640398f43417SMatheus Ferst 6404016b6e1dSLeandro Lupori #include "translate/storage-ctrl-impl.c.inc" 6405016b6e1dSLeandro Lupori 640620e2d04eSLeandro Lupori /* Handles lfdp */ 64075cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 64085cb091a4SNikunj A Dadhania { 640920e2d04eSLeandro Lupori if ((ctx->opcode & 0x3) == 0) { 64105cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 64115cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 64125cb091a4SNikunj A Dadhania } 64135cb091a4SNikunj A Dadhania } 64145cb091a4SNikunj A Dadhania return gen_invalid(ctx); 64155cb091a4SNikunj A Dadhania } 64165cb091a4SNikunj A Dadhania 641720e2d04eSLeandro Lupori /* Handles stfdp */ 6418e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6419e3001664SNikunj A Dadhania { 642020e2d04eSLeandro Lupori if ((ctx->opcode & 3) == 0) { /* DS-FORM */ 642120e2d04eSLeandro Lupori /* stfdp */ 6422e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6423e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6424e3001664SNikunj A Dadhania } 6425e3001664SNikunj A Dadhania } 6426e3001664SNikunj A Dadhania return gen_invalid(ctx); 6427e3001664SNikunj A Dadhania } 6428e3001664SNikunj A Dadhania 64299d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64309d69cfa2SLijun Pan /* brd */ 64319d69cfa2SLijun Pan static void gen_brd(DisasContext *ctx) 64329d69cfa2SLijun Pan { 64339d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64349d69cfa2SLijun Pan } 64359d69cfa2SLijun Pan 64369d69cfa2SLijun Pan /* brw */ 64379d69cfa2SLijun Pan static void gen_brw(DisasContext *ctx) 64389d69cfa2SLijun Pan { 64399d69cfa2SLijun Pan tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 64409d69cfa2SLijun Pan tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); 64419d69cfa2SLijun Pan 64429d69cfa2SLijun Pan } 64439d69cfa2SLijun Pan 64449d69cfa2SLijun Pan /* brh */ 64459d69cfa2SLijun Pan static void gen_brh(DisasContext *ctx) 64469d69cfa2SLijun Pan { 6447491b3ccaSPhilippe Mathieu-Daudé TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); 64489d69cfa2SLijun Pan TCGv_i64 t1 = tcg_temp_new_i64(); 64499d69cfa2SLijun Pan TCGv_i64 t2 = tcg_temp_new_i64(); 64509d69cfa2SLijun Pan 64519d69cfa2SLijun Pan tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); 6452491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t2, t1, mask); 6453491b3ccaSPhilippe Mathieu-Daudé tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); 64549d69cfa2SLijun Pan tcg_gen_shli_i64(t1, t1, 8); 64559d69cfa2SLijun Pan tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); 64569d69cfa2SLijun Pan } 64579d69cfa2SLijun Pan #endif 64589d69cfa2SLijun Pan 6459fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 64609d69cfa2SLijun Pan #if defined(TARGET_PPC64) 64619d69cfa2SLijun Pan GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), 64629d69cfa2SLijun Pan GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), 64639d69cfa2SLijun Pan GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), 64649d69cfa2SLijun Pan #endif 6465fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6466fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6467fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6468fcf5ef2aSThomas Huth #endif 6469fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6470fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6471fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6472fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6473fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6474fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6475fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6476fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6477fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6478fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6479fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6480fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6481fcf5ef2aSThomas Huth #endif 6482fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6483fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6484fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6485fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6486fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6487fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6488fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 648980b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6490b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 649180b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6492fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6493fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6494fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6495fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6496fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6497fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6498fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6499fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6500fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6501fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6502fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6503fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6504fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6505fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6506fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6507fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6508fcf5ef2aSThomas Huth #endif 6509fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6510fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6511fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6512fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6513fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6514fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6515fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6516fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6517fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6518fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6519fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6520fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6521fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6522fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6523fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6524fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6525fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6526fcf5ef2aSThomas Huth #endif 65275cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 65285cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 652972b70d5cSLucas Mateus Castro (alqotel) /* handles stfdp, stxsd, stxssp */ 6530e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6531fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6532fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6533fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6534fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6535fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6536fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6537c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6538fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6539fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6540fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6541fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6542a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6543a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6544fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6545fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6546fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6547fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6548a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6549a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6550fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6551fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6552fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6553fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6554fcf5ef2aSThomas Huth #endif 6555fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 65560c9717ffSNicholas Piggin /* ISA v3.0 changed the extended opcode from 62 to 30 */ 65570c9717ffSNicholas Piggin GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), 65580c9717ffSNicholas Piggin GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), 6559fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6560fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6561fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6562fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6563fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6564fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6565fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6566fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6567fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 65683c89b8d6SNicholas Piggin #if !defined(CONFIG_USER_ONLY) 65693c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65703c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65713c89b8d6SNicholas Piggin GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), 65723c89b8d6SNicholas Piggin GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), 65733c89b8d6SNicholas Piggin #endif 6574cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6575fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6576fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6577fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6578fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6579fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6580fcf5ef2aSThomas Huth #endif 65813c89b8d6SNicholas Piggin /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ 65823c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), 65833c89b8d6SNicholas Piggin GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), 6584fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6585fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6586fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6587fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6588fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6589fcf5ef2aSThomas Huth #endif 6590fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6591fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6592fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6593fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6594fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6595fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6596fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6597fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6598fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6599b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6600fcf5ef2aSThomas Huth #endif 6601fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6602fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6603fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 660450728199SRoman Kapl GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6605fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6606fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 660750728199SRoman Kapl GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6608fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 660950728199SRoman Kapl GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6610fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 661150728199SRoman Kapl GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), 6612fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6613e64645baSBernhard Beschow GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6614fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 661550728199SRoman Kapl GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), 6616fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 661799d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6618fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6619fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 662050728199SRoman Kapl GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), 6621fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6622fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6623fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6624fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6625fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6626fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6627fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6628fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6629fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6630fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6631fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6632fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6633fcf5ef2aSThomas Huth #endif 6634fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6635efe843d8SDavid Gibson /* 6636efe843d8SDavid Gibson * XXX Those instructions will need to be handled differently for 6637efe843d8SDavid Gibson * different ISA versions 6638efe843d8SDavid Gibson */ 6639fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6640fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6641fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6642fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6643fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6644fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6645fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6646fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6647fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6648fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6649fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6650fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6651fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6652fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6653fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6654fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6655fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6656fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6657fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6658fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6659fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6660fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6661fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6662fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6663fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6664fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6665fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6666fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6667fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6668fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6669fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6670fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6671fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6672fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6673fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6674fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6675fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6676fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6677fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6678fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6679fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 668027a3ea7eSBALATON Zoltan GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), 6681fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6682fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 66830c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 66840c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6685fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6686fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6687fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6688fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6689fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6690fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6691fcf5ef2aSThomas Huth PPC2_ISA300), 6692fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6693fcf5ef2aSThomas Huth #endif 6694fcf5ef2aSThomas Huth 6695fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6696fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6697fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6698fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6699fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6700fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6701fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6702fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6703fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6704fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6705fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6706fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6707fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6708fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6709fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 67104c5920afSSuraj Jitindar Singh GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), 6711fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6712fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6713fcf5ef2aSThomas Huth 6714fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6715fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6716fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6717fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6718fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6719fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6720fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6721fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6722fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6723fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6724fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6725fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6726fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6727fcf5ef2aSThomas Huth 6728fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6729fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6730fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6731fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6732fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6733fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6734fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6735fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6736fcf5ef2aSThomas Huth 6737fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6738fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6739fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6740fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6741fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6742fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6743fcf5ef2aSThomas Huth 6744fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6745fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6746fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6747fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6748fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6749fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6750fcf5ef2aSThomas Huth #endif 6751fcf5ef2aSThomas Huth 6752fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6753fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6754fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6755fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6756fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6757fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6758fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6759fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6760fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6761fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6762fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6763fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6764fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6765fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6766fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6767fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6768fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6769fcf5ef2aSThomas Huth 6770fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6771fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6772fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6773fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6774fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6775fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6776fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6777fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6778fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6779fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6780fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6781fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6782fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6783fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6784fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6785fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6786fcf5ef2aSThomas Huth #endif 6787fcf5ef2aSThomas Huth 6788fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6789fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6790fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6791fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6792fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6793fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6794fcf5ef2aSThomas Huth PPC_64B) 6795fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6796fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6797fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6798fcf5ef2aSThomas Huth PPC_64B), \ 6799fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6800fcf5ef2aSThomas Huth PPC_64B), \ 6801fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6802fcf5ef2aSThomas Huth PPC_64B) 6803fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6804fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6805fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6806fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6807fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6808fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6809fcf5ef2aSThomas Huth #endif 6810fcf5ef2aSThomas Huth 6811fcf5ef2aSThomas Huth #undef GEN_LDX_E 6812fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6813fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6814fcf5ef2aSThomas Huth 6815fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6816fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6817fcf5ef2aSThomas Huth 6818fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6819fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6820fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6821fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6822fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6823fcf5ef2aSThomas Huth #endif 6824fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6825fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6826fcf5ef2aSThomas Huth 682750728199SRoman Kapl /* External PID based load */ 682850728199SRoman Kapl #undef GEN_LDEPX 682950728199SRoman Kapl #define GEN_LDEPX(name, ldop, opc2, opc3) \ 683050728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 683150728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 683250728199SRoman Kapl 683350728199SRoman Kapl GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) 683450728199SRoman Kapl GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) 683550728199SRoman Kapl GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) 683650728199SRoman Kapl #if defined(TARGET_PPC64) 6837fc313c64SFrédéric Pétrot GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) 683850728199SRoman Kapl #endif 683950728199SRoman Kapl 6840fcf5ef2aSThomas Huth #undef GEN_STX_E 6841fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 68420123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 6843fcf5ef2aSThomas Huth 6844fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6845fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6846fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6847fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6848fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6849fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6850fcf5ef2aSThomas Huth #endif 6851fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6852fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6853fcf5ef2aSThomas Huth 685450728199SRoman Kapl #undef GEN_STEPX 685550728199SRoman Kapl #define GEN_STEPX(name, ldop, opc2, opc3) \ 685650728199SRoman Kapl GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ 685750728199SRoman Kapl 0x00000001, PPC_NONE, PPC2_BOOKE206), 685850728199SRoman Kapl 685950728199SRoman Kapl GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) 686050728199SRoman Kapl GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) 686150728199SRoman Kapl GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) 686250728199SRoman Kapl #if defined(TARGET_PPC64) 6863fc313c64SFrédéric Pétrot GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) 686450728199SRoman Kapl #endif 686550728199SRoman Kapl 6866fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6867fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6868fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6869fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6870fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6871fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6872fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6873fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6874fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6875fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6876fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6877fcf5ef2aSThomas Huth 6878fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6879fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6880fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6881fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6882fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6883fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6884fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6885fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6886fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6887fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6888fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6889fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6890fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6891fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6892fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6893fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6894fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6895fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6896fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6897fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6898fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6899fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6900fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6901fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6902fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6903fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6904fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6905fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6906fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6907fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6908fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6909fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6910fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6911fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6912fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6913fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6914fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6915fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6916fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6917fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6918fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6919fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6920fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6921fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6922fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6923fcf5ef2aSThomas Huth 6924fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6925fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6926fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6927fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6928fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6929fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6930fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6931fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6932fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6933fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6934fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6935fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6936fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6937fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6938fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6939fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6940fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6941fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6942fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6943fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6944fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6945fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6946fcf5ef2aSThomas Huth 6947139c1837SPaolo Bonzini #include "translate/fp-ops.c.inc" 6948fcf5ef2aSThomas Huth 6949139c1837SPaolo Bonzini #include "translate/vmx-ops.c.inc" 6950fcf5ef2aSThomas Huth 6951139c1837SPaolo Bonzini #include "translate/vsx-ops.c.inc" 6952fcf5ef2aSThomas Huth 6953139c1837SPaolo Bonzini #include "translate/spe-ops.c.inc" 6954fcf5ef2aSThomas Huth }; 6955fcf5ef2aSThomas Huth 69567468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 69577468e2c8SBruno Larsen (billionai) /* Opcode types */ 69587468e2c8SBruno Larsen (billionai) enum { 69597468e2c8SBruno Larsen (billionai) PPC_DIRECT = 0, /* Opcode routine */ 69607468e2c8SBruno Larsen (billionai) PPC_INDIRECT = 1, /* Indirect opcode table */ 69617468e2c8SBruno Larsen (billionai) }; 69627468e2c8SBruno Larsen (billionai) 69637468e2c8SBruno Larsen (billionai) #define PPC_OPCODE_MASK 0x3 69647468e2c8SBruno Larsen (billionai) 69657468e2c8SBruno Larsen (billionai) static inline int is_indirect_opcode(void *handler) 69667468e2c8SBruno Larsen (billionai) { 69677468e2c8SBruno Larsen (billionai) return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 69687468e2c8SBruno Larsen (billionai) } 69697468e2c8SBruno Larsen (billionai) 69707468e2c8SBruno Larsen (billionai) static inline opc_handler_t **ind_table(void *handler) 69717468e2c8SBruno Larsen (billionai) { 69727468e2c8SBruno Larsen (billionai) return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 69737468e2c8SBruno Larsen (billionai) } 69747468e2c8SBruno Larsen (billionai) 69757468e2c8SBruno Larsen (billionai) /* Instruction table creation */ 69767468e2c8SBruno Larsen (billionai) /* Opcodes tables creation */ 69777468e2c8SBruno Larsen (billionai) static void fill_new_table(opc_handler_t **table, int len) 69787468e2c8SBruno Larsen (billionai) { 69797468e2c8SBruno Larsen (billionai) int i; 69807468e2c8SBruno Larsen (billionai) 69817468e2c8SBruno Larsen (billionai) for (i = 0; i < len; i++) { 69827468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 69837468e2c8SBruno Larsen (billionai) } 69847468e2c8SBruno Larsen (billionai) } 69857468e2c8SBruno Larsen (billionai) 69867468e2c8SBruno Larsen (billionai) static int create_new_table(opc_handler_t **table, unsigned char idx) 69877468e2c8SBruno Larsen (billionai) { 69887468e2c8SBruno Larsen (billionai) opc_handler_t **tmp; 69897468e2c8SBruno Larsen (billionai) 69907468e2c8SBruno Larsen (billionai) tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 69917468e2c8SBruno Larsen (billionai) fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 69927468e2c8SBruno Larsen (billionai) table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 69937468e2c8SBruno Larsen (billionai) 69947468e2c8SBruno Larsen (billionai) return 0; 69957468e2c8SBruno Larsen (billionai) } 69967468e2c8SBruno Larsen (billionai) 69977468e2c8SBruno Larsen (billionai) static int insert_in_table(opc_handler_t **table, unsigned char idx, 69987468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 69997468e2c8SBruno Larsen (billionai) { 70007468e2c8SBruno Larsen (billionai) if (table[idx] != &invalid_handler) { 70017468e2c8SBruno Larsen (billionai) return -1; 70027468e2c8SBruno Larsen (billionai) } 70037468e2c8SBruno Larsen (billionai) table[idx] = handler; 70047468e2c8SBruno Larsen (billionai) 70057468e2c8SBruno Larsen (billionai) return 0; 70067468e2c8SBruno Larsen (billionai) } 70077468e2c8SBruno Larsen (billionai) 70087468e2c8SBruno Larsen (billionai) static int register_direct_insn(opc_handler_t **ppc_opcodes, 70097468e2c8SBruno Larsen (billionai) unsigned char idx, opc_handler_t *handler) 70107468e2c8SBruno Larsen (billionai) { 70117468e2c8SBruno Larsen (billionai) if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 70127468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in main " 70137468e2c8SBruno Larsen (billionai) "opcode table\n", idx); 70147468e2c8SBruno Larsen (billionai) return -1; 70157468e2c8SBruno Larsen (billionai) } 70167468e2c8SBruno Larsen (billionai) 70177468e2c8SBruno Larsen (billionai) return 0; 70187468e2c8SBruno Larsen (billionai) } 70197468e2c8SBruno Larsen (billionai) 70207468e2c8SBruno Larsen (billionai) static int register_ind_in_table(opc_handler_t **table, 70217468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70227468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70237468e2c8SBruno Larsen (billionai) { 70247468e2c8SBruno Larsen (billionai) if (table[idx1] == &invalid_handler) { 70257468e2c8SBruno Larsen (billionai) if (create_new_table(table, idx1) < 0) { 70267468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to create indirect table " 70277468e2c8SBruno Larsen (billionai) "idx=%02x\n", idx1); 70287468e2c8SBruno Larsen (billionai) return -1; 70297468e2c8SBruno Larsen (billionai) } 70307468e2c8SBruno Larsen (billionai) } else { 70317468e2c8SBruno Larsen (billionai) if (!is_indirect_opcode(table[idx1])) { 70327468e2c8SBruno Larsen (billionai) printf("*** ERROR: idx %02x already assigned to a direct " 70337468e2c8SBruno Larsen (billionai) "opcode\n", idx1); 70347468e2c8SBruno Larsen (billionai) return -1; 70357468e2c8SBruno Larsen (billionai) } 70367468e2c8SBruno Larsen (billionai) } 70377468e2c8SBruno Larsen (billionai) if (handler != NULL && 70387468e2c8SBruno Larsen (billionai) insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 70397468e2c8SBruno Larsen (billionai) printf("*** ERROR: opcode %02x already assigned in " 70407468e2c8SBruno Larsen (billionai) "opcode table %02x\n", idx2, idx1); 70417468e2c8SBruno Larsen (billionai) return -1; 70427468e2c8SBruno Larsen (billionai) } 70437468e2c8SBruno Larsen (billionai) 70447468e2c8SBruno Larsen (billionai) return 0; 70457468e2c8SBruno Larsen (billionai) } 70467468e2c8SBruno Larsen (billionai) 70477468e2c8SBruno Larsen (billionai) static int register_ind_insn(opc_handler_t **ppc_opcodes, 70487468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70497468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70507468e2c8SBruno Larsen (billionai) { 70517468e2c8SBruno Larsen (billionai) return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 70527468e2c8SBruno Larsen (billionai) } 70537468e2c8SBruno Larsen (billionai) 70547468e2c8SBruno Larsen (billionai) static int register_dblind_insn(opc_handler_t **ppc_opcodes, 70557468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70567468e2c8SBruno Larsen (billionai) unsigned char idx3, opc_handler_t *handler) 70577468e2c8SBruno Larsen (billionai) { 70587468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70597468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70607468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70617468e2c8SBruno Larsen (billionai) return -1; 70627468e2c8SBruno Larsen (billionai) } 70637468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 70647468e2c8SBruno Larsen (billionai) handler) < 0) { 70657468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70667468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70677468e2c8SBruno Larsen (billionai) return -1; 70687468e2c8SBruno Larsen (billionai) } 70697468e2c8SBruno Larsen (billionai) 70707468e2c8SBruno Larsen (billionai) return 0; 70717468e2c8SBruno Larsen (billionai) } 70727468e2c8SBruno Larsen (billionai) 70737468e2c8SBruno Larsen (billionai) static int register_trplind_insn(opc_handler_t **ppc_opcodes, 70747468e2c8SBruno Larsen (billionai) unsigned char idx1, unsigned char idx2, 70757468e2c8SBruno Larsen (billionai) unsigned char idx3, unsigned char idx4, 70767468e2c8SBruno Larsen (billionai) opc_handler_t *handler) 70777468e2c8SBruno Larsen (billionai) { 70787468e2c8SBruno Larsen (billionai) opc_handler_t **table; 70797468e2c8SBruno Larsen (billionai) 70807468e2c8SBruno Larsen (billionai) if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 70817468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join indirect table idx " 70827468e2c8SBruno Larsen (billionai) "[%02x-%02x]\n", idx1, idx2); 70837468e2c8SBruno Larsen (billionai) return -1; 70847468e2c8SBruno Larsen (billionai) } 70857468e2c8SBruno Larsen (billionai) table = ind_table(ppc_opcodes[idx1]); 70867468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 70877468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to join 2nd-level indirect table idx " 70887468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 70897468e2c8SBruno Larsen (billionai) return -1; 70907468e2c8SBruno Larsen (billionai) } 70917468e2c8SBruno Larsen (billionai) table = ind_table(table[idx2]); 70927468e2c8SBruno Larsen (billionai) if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 70937468e2c8SBruno Larsen (billionai) printf("*** ERROR: unable to insert opcode " 70947468e2c8SBruno Larsen (billionai) "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 70957468e2c8SBruno Larsen (billionai) return -1; 70967468e2c8SBruno Larsen (billionai) } 70977468e2c8SBruno Larsen (billionai) return 0; 70987468e2c8SBruno Larsen (billionai) } 70997468e2c8SBruno Larsen (billionai) static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 71007468e2c8SBruno Larsen (billionai) { 71017468e2c8SBruno Larsen (billionai) if (insn->opc2 != 0xFF) { 71027468e2c8SBruno Larsen (billionai) if (insn->opc3 != 0xFF) { 71037468e2c8SBruno Larsen (billionai) if (insn->opc4 != 0xFF) { 71047468e2c8SBruno Larsen (billionai) if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 71057468e2c8SBruno Larsen (billionai) insn->opc3, insn->opc4, 71067468e2c8SBruno Larsen (billionai) &insn->handler) < 0) { 71077468e2c8SBruno Larsen (billionai) return -1; 71087468e2c8SBruno Larsen (billionai) } 71097468e2c8SBruno Larsen (billionai) } else { 71107468e2c8SBruno Larsen (billionai) if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 71117468e2c8SBruno Larsen (billionai) insn->opc3, &insn->handler) < 0) { 71127468e2c8SBruno Larsen (billionai) return -1; 71137468e2c8SBruno Larsen (billionai) } 71147468e2c8SBruno Larsen (billionai) } 71157468e2c8SBruno Larsen (billionai) } else { 71167468e2c8SBruno Larsen (billionai) if (register_ind_insn(ppc_opcodes, insn->opc1, 71177468e2c8SBruno Larsen (billionai) insn->opc2, &insn->handler) < 0) { 71187468e2c8SBruno Larsen (billionai) return -1; 71197468e2c8SBruno Larsen (billionai) } 71207468e2c8SBruno Larsen (billionai) } 71217468e2c8SBruno Larsen (billionai) } else { 71227468e2c8SBruno Larsen (billionai) if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 71237468e2c8SBruno Larsen (billionai) return -1; 71247468e2c8SBruno Larsen (billionai) } 71257468e2c8SBruno Larsen (billionai) } 71267468e2c8SBruno Larsen (billionai) 71277468e2c8SBruno Larsen (billionai) return 0; 71287468e2c8SBruno Larsen (billionai) } 71297468e2c8SBruno Larsen (billionai) 71307468e2c8SBruno Larsen (billionai) static int test_opcode_table(opc_handler_t **table, int len) 71317468e2c8SBruno Larsen (billionai) { 71327468e2c8SBruno Larsen (billionai) int i, count, tmp; 71337468e2c8SBruno Larsen (billionai) 71347468e2c8SBruno Larsen (billionai) for (i = 0, count = 0; i < len; i++) { 71357468e2c8SBruno Larsen (billionai) /* Consistency fixup */ 71367468e2c8SBruno Larsen (billionai) if (table[i] == NULL) { 71377468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71387468e2c8SBruno Larsen (billionai) } 71397468e2c8SBruno Larsen (billionai) if (table[i] != &invalid_handler) { 71407468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[i])) { 71417468e2c8SBruno Larsen (billionai) tmp = test_opcode_table(ind_table(table[i]), 71427468e2c8SBruno Larsen (billionai) PPC_CPU_INDIRECT_OPCODES_LEN); 71437468e2c8SBruno Larsen (billionai) if (tmp == 0) { 71447468e2c8SBruno Larsen (billionai) free(table[i]); 71457468e2c8SBruno Larsen (billionai) table[i] = &invalid_handler; 71467468e2c8SBruno Larsen (billionai) } else { 71477468e2c8SBruno Larsen (billionai) count++; 71487468e2c8SBruno Larsen (billionai) } 71497468e2c8SBruno Larsen (billionai) } else { 71507468e2c8SBruno Larsen (billionai) count++; 71517468e2c8SBruno Larsen (billionai) } 71527468e2c8SBruno Larsen (billionai) } 71537468e2c8SBruno Larsen (billionai) } 71547468e2c8SBruno Larsen (billionai) 71557468e2c8SBruno Larsen (billionai) return count; 71567468e2c8SBruno Larsen (billionai) } 71577468e2c8SBruno Larsen (billionai) 71587468e2c8SBruno Larsen (billionai) static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 71597468e2c8SBruno Larsen (billionai) { 71607468e2c8SBruno Larsen (billionai) if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 71617468e2c8SBruno Larsen (billionai) printf("*** WARNING: no opcode defined !\n"); 71627468e2c8SBruno Larsen (billionai) } 71637468e2c8SBruno Larsen (billionai) } 71647468e2c8SBruno Larsen (billionai) 71657468e2c8SBruno Larsen (billionai) /*****************************************************************************/ 71667468e2c8SBruno Larsen (billionai) void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 71677468e2c8SBruno Larsen (billionai) { 71687468e2c8SBruno Larsen (billionai) PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 71697468e2c8SBruno Larsen (billionai) opcode_t *opc; 71707468e2c8SBruno Larsen (billionai) 71717468e2c8SBruno Larsen (billionai) fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 71727468e2c8SBruno Larsen (billionai) for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 71737468e2c8SBruno Larsen (billionai) if (((opc->handler.type & pcc->insns_flags) != 0) || 71747468e2c8SBruno Larsen (billionai) ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 71757468e2c8SBruno Larsen (billionai) if (register_insn(cpu->opcodes, opc) < 0) { 71767468e2c8SBruno Larsen (billionai) error_setg(errp, "ERROR initializing PowerPC instruction " 71777468e2c8SBruno Larsen (billionai) "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 71787468e2c8SBruno Larsen (billionai) opc->opc3); 71797468e2c8SBruno Larsen (billionai) return; 71807468e2c8SBruno Larsen (billionai) } 71817468e2c8SBruno Larsen (billionai) } 71827468e2c8SBruno Larsen (billionai) } 71837468e2c8SBruno Larsen (billionai) fix_opcode_tables(cpu->opcodes); 71847468e2c8SBruno Larsen (billionai) fflush(stdout); 71857468e2c8SBruno Larsen (billionai) fflush(stderr); 71867468e2c8SBruno Larsen (billionai) } 71877468e2c8SBruno Larsen (billionai) 71887468e2c8SBruno Larsen (billionai) void destroy_ppc_opcodes(PowerPCCPU *cpu) 71897468e2c8SBruno Larsen (billionai) { 71907468e2c8SBruno Larsen (billionai) opc_handler_t **table, **table_2; 71917468e2c8SBruno Larsen (billionai) int i, j, k; 71927468e2c8SBruno Larsen (billionai) 71937468e2c8SBruno Larsen (billionai) for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 71947468e2c8SBruno Larsen (billionai) if (cpu->opcodes[i] == &invalid_handler) { 71957468e2c8SBruno Larsen (billionai) continue; 71967468e2c8SBruno Larsen (billionai) } 71977468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(cpu->opcodes[i])) { 71987468e2c8SBruno Larsen (billionai) table = ind_table(cpu->opcodes[i]); 71997468e2c8SBruno Larsen (billionai) for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 72007468e2c8SBruno Larsen (billionai) if (table[j] == &invalid_handler) { 72017468e2c8SBruno Larsen (billionai) continue; 72027468e2c8SBruno Larsen (billionai) } 72037468e2c8SBruno Larsen (billionai) if (is_indirect_opcode(table[j])) { 72047468e2c8SBruno Larsen (billionai) table_2 = ind_table(table[j]); 72057468e2c8SBruno Larsen (billionai) for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 72067468e2c8SBruno Larsen (billionai) if (table_2[k] != &invalid_handler && 72077468e2c8SBruno Larsen (billionai) is_indirect_opcode(table_2[k])) { 72087468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table_2[k] & 72097468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 72107468e2c8SBruno Larsen (billionai) } 72117468e2c8SBruno Larsen (billionai) } 72127468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)table[j] & 72137468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 72147468e2c8SBruno Larsen (billionai) } 72157468e2c8SBruno Larsen (billionai) } 72167468e2c8SBruno Larsen (billionai) g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 72177468e2c8SBruno Larsen (billionai) ~PPC_INDIRECT)); 72187468e2c8SBruno Larsen (billionai) } 72197468e2c8SBruno Larsen (billionai) } 72207468e2c8SBruno Larsen (billionai) } 72217468e2c8SBruno Larsen (billionai) 72227468e2c8SBruno Larsen (billionai) int ppc_fixup_cpu(PowerPCCPU *cpu) 72237468e2c8SBruno Larsen (billionai) { 72247468e2c8SBruno Larsen (billionai) CPUPPCState *env = &cpu->env; 72257468e2c8SBruno Larsen (billionai) 72267468e2c8SBruno Larsen (billionai) /* 72277468e2c8SBruno Larsen (billionai) * TCG doesn't (yet) emulate some groups of instructions that are 72287468e2c8SBruno Larsen (billionai) * implemented on some otherwise supported CPUs (e.g. VSX and 72297468e2c8SBruno Larsen (billionai) * decimal floating point instructions on POWER7). We remove 72307468e2c8SBruno Larsen (billionai) * unsupported instruction groups from the cpu state's instruction 72317468e2c8SBruno Larsen (billionai) * masks and hope the guest can cope. For at least the pseries 72327468e2c8SBruno Larsen (billionai) * machine, the unavailability of these instructions can be 72337468e2c8SBruno Larsen (billionai) * advertised to the guest via the device tree. 72347468e2c8SBruno Larsen (billionai) */ 72357468e2c8SBruno Larsen (billionai) if ((env->insns_flags & ~PPC_TCG_INSNS) 72367468e2c8SBruno Larsen (billionai) || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 72377468e2c8SBruno Larsen (billionai) warn_report("Disabling some instructions which are not " 72387468e2c8SBruno Larsen (billionai) "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 72397468e2c8SBruno Larsen (billionai) env->insns_flags & ~PPC_TCG_INSNS, 72407468e2c8SBruno Larsen (billionai) env->insns_flags2 & ~PPC_TCG_INSNS2); 72417468e2c8SBruno Larsen (billionai) } 72427468e2c8SBruno Larsen (billionai) env->insns_flags &= PPC_TCG_INSNS; 72437468e2c8SBruno Larsen (billionai) env->insns_flags2 &= PPC_TCG_INSNS2; 72447468e2c8SBruno Larsen (billionai) return 0; 72457468e2c8SBruno Larsen (billionai) } 72467468e2c8SBruno Larsen (billionai) 7247624cb07fSRichard Henderson static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) 7248624cb07fSRichard Henderson { 7249624cb07fSRichard Henderson opc_handler_t **table, *handler; 7250624cb07fSRichard Henderson uint32_t inval; 7251624cb07fSRichard Henderson 7252624cb07fSRichard Henderson ctx->opcode = insn; 7253624cb07fSRichard Henderson 7254624cb07fSRichard Henderson LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7255624cb07fSRichard Henderson insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7256624cb07fSRichard Henderson ctx->le_mode ? "little" : "big"); 7257624cb07fSRichard Henderson 7258624cb07fSRichard Henderson table = cpu->opcodes; 7259624cb07fSRichard Henderson handler = table[opc1(insn)]; 7260624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7261624cb07fSRichard Henderson table = ind_table(handler); 7262624cb07fSRichard Henderson handler = table[opc2(insn)]; 7263624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7264624cb07fSRichard Henderson table = ind_table(handler); 7265624cb07fSRichard Henderson handler = table[opc3(insn)]; 7266624cb07fSRichard Henderson if (is_indirect_opcode(handler)) { 7267624cb07fSRichard Henderson table = ind_table(handler); 7268624cb07fSRichard Henderson handler = table[opc4(insn)]; 7269624cb07fSRichard Henderson } 7270624cb07fSRichard Henderson } 7271624cb07fSRichard Henderson } 7272624cb07fSRichard Henderson 7273624cb07fSRichard Henderson /* Is opcode *REALLY* valid ? */ 7274624cb07fSRichard Henderson if (unlikely(handler->handler == &gen_invalid)) { 7275624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7276624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7277624cb07fSRichard Henderson TARGET_FMT_lx "\n", 7278624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7279624cb07fSRichard Henderson insn, ctx->cia); 7280624cb07fSRichard Henderson return false; 7281624cb07fSRichard Henderson } 7282624cb07fSRichard Henderson 7283624cb07fSRichard Henderson if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7284624cb07fSRichard Henderson && Rc(insn))) { 7285624cb07fSRichard Henderson inval = handler->inval2; 7286624cb07fSRichard Henderson } else { 7287624cb07fSRichard Henderson inval = handler->inval1; 7288624cb07fSRichard Henderson } 7289624cb07fSRichard Henderson 7290624cb07fSRichard Henderson if (unlikely((insn & inval) != 0)) { 7291624cb07fSRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7292624cb07fSRichard Henderson "%02x - %02x - %02x - %02x (%08x) " 7293624cb07fSRichard Henderson TARGET_FMT_lx "\n", insn & inval, 7294624cb07fSRichard Henderson opc1(insn), opc2(insn), opc3(insn), opc4(insn), 7295624cb07fSRichard Henderson insn, ctx->cia); 7296624cb07fSRichard Henderson return false; 7297624cb07fSRichard Henderson } 7298624cb07fSRichard Henderson 7299624cb07fSRichard Henderson handler->handler(ctx); 7300624cb07fSRichard Henderson return true; 7301624cb07fSRichard Henderson } 7302624cb07fSRichard Henderson 7303b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7304fcf5ef2aSThomas Huth { 7305b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 73069c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 73072df4fe7aSRichard Henderson uint32_t hflags = ctx->base.tb->flags; 7308fcf5ef2aSThomas Huth 7309b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 73102df4fe7aSRichard Henderson ctx->pr = (hflags >> HFLAGS_PR) & 1; 7311d764184dSRichard Henderson ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; 73122df4fe7aSRichard Henderson ctx->dr = (hflags >> HFLAGS_DR) & 1; 73132df4fe7aSRichard Henderson ctx->hv = (hflags >> HFLAGS_HV) & 1; 7314b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7315b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7316b0c2d521SEmilio G. Cota ctx->access_type = -1; 7317d57d72a8SGreg Kurz ctx->need_access_type = !mmu_is_64bit(env->mmu_model); 73182df4fe7aSRichard Henderson ctx->le_mode = (hflags >> HFLAGS_LE) & 1; 7319b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 73200e3bf489SRoman Kapl ctx->flags = env->flags; 7321fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 73222df4fe7aSRichard Henderson ctx->sf_mode = (hflags >> HFLAGS_64) & 1; 7323b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7324fcf5ef2aSThomas Huth #endif 7325e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7326d55dfd44SStephane Duverger || env->mmu_model & POWERPC_MMU_64; 7327fcf5ef2aSThomas Huth 73282df4fe7aSRichard Henderson ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; 73292df4fe7aSRichard Henderson ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; 73302df4fe7aSRichard Henderson ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; 73312df4fe7aSRichard Henderson ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; 73322df4fe7aSRichard Henderson ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; 7333f03de3b4SRichard Henderson ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; 73341db3632aSMatheus Ferst ctx->hr = (hflags >> HFLAGS_HR) & 1; 7335f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; 7336f7460df2SDaniel Henrique Barboza ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; 73378b3d1c49SLeandro Lupori ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; 73388b3d1c49SLeandro Lupori ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; 733946d396bdSDaniel Henrique Barboza ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; 73402df4fe7aSRichard Henderson 7341b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 73422df4fe7aSRichard Henderson if ((hflags >> HFLAGS_SE) & 1) { 73432df4fe7aSRichard Henderson ctx->singlestep_enabled |= CPU_SINGLE_STEP; 73449498d103SRichard Henderson ctx->base.max_insns = 1; 7345efe843d8SDavid Gibson } 73462df4fe7aSRichard Henderson if ((hflags >> HFLAGS_BE) & 1) { 7347b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7348efe843d8SDavid Gibson } 734913b45575SRichard Henderson } 7350fcf5ef2aSThomas Huth 7351b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7352b0c2d521SEmilio G. Cota { 7353b0c2d521SEmilio G. Cota } 7354fcf5ef2aSThomas Huth 7355b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7356b0c2d521SEmilio G. Cota { 7357b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7358b0c2d521SEmilio G. Cota } 7359b0c2d521SEmilio G. Cota 736099082815SRichard Henderson static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) 736199082815SRichard Henderson { 736299082815SRichard Henderson REQUIRE_INSNS_FLAGS2(ctx, ISA310); 736399082815SRichard Henderson return opc1(insn) == 1; 736499082815SRichard Henderson } 736599082815SRichard Henderson 7366b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7367b0c2d521SEmilio G. Cota { 7368b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 736928876bf2SAlex Bennée PowerPCCPU *cpu = POWERPC_CPU(cs); 7370b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 737199082815SRichard Henderson target_ulong pc; 7372624cb07fSRichard Henderson uint32_t insn; 7373624cb07fSRichard Henderson bool ok; 7374b0c2d521SEmilio G. Cota 7375fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7376fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7377b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7378b0c2d521SEmilio G. Cota 737999082815SRichard Henderson ctx->cia = pc = ctx->base.pc_next; 73804e116893SIlya Leoshkevich insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); 738199082815SRichard Henderson ctx->base.pc_next = pc += 4; 7382fcf5ef2aSThomas Huth 738399082815SRichard Henderson if (!is_prefix_insn(ctx, insn)) { 738499082815SRichard Henderson ok = (decode_insn32(ctx, insn) || 738599082815SRichard Henderson decode_legacy(cpu, ctx, insn)); 738699082815SRichard Henderson } else if ((pc & 63) == 0) { 738799082815SRichard Henderson /* 738899082815SRichard Henderson * Power v3.1, section 1.9 Exceptions: 738999082815SRichard Henderson * attempt to execute a prefixed instruction that crosses a 739099082815SRichard Henderson * 64-byte address boundary (system alignment error). 739199082815SRichard Henderson */ 739299082815SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); 739399082815SRichard Henderson ok = true; 739499082815SRichard Henderson } else { 73954e116893SIlya Leoshkevich uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, 73964e116893SIlya Leoshkevich need_byteswap(ctx)); 739799082815SRichard Henderson ctx->base.pc_next = pc += 4; 739899082815SRichard Henderson ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); 739999082815SRichard Henderson } 7400624cb07fSRichard Henderson if (!ok) { 7401624cb07fSRichard Henderson gen_invalid(ctx); 7402fcf5ef2aSThomas Huth } 7403624cb07fSRichard Henderson 740464a0f644SRichard Henderson /* End the TB when crossing a page boundary. */ 740599082815SRichard Henderson if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { 740664a0f644SRichard Henderson ctx->base.is_jmp = DISAS_TOO_MANY; 740764a0f644SRichard Henderson } 7408fcf5ef2aSThomas Huth } 7409b0c2d521SEmilio G. Cota 7410b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7411b0c2d521SEmilio G. Cota { 7412b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7413a9b5b3d0SRichard Henderson DisasJumpType is_jmp = ctx->base.is_jmp; 7414a9b5b3d0SRichard Henderson target_ulong nip = ctx->base.pc_next; 7415b0c2d521SEmilio G. Cota 7416a9b5b3d0SRichard Henderson if (is_jmp == DISAS_NORETURN) { 7417a9b5b3d0SRichard Henderson /* We have already exited the TB. */ 74183d8a5b69SRichard Henderson return; 74193d8a5b69SRichard Henderson } 74203d8a5b69SRichard Henderson 7421a9b5b3d0SRichard Henderson /* Honor single stepping. */ 742298a18f4dSNicholas Piggin if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { 7423a11e3a15SNicholas Piggin bool rfi_type = false; 7424a11e3a15SNicholas Piggin 7425a9b5b3d0SRichard Henderson switch (is_jmp) { 7426a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7427a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7428a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7429a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7430a9b5b3d0SRichard Henderson break; 7431a9b5b3d0SRichard Henderson case DISAS_EXIT: 7432a9b5b3d0SRichard Henderson case DISAS_CHAIN: 7433a11e3a15SNicholas Piggin /* 7434a11e3a15SNicholas Piggin * This is a heuristic, to put it kindly. The rfi class of 7435a11e3a15SNicholas Piggin * instructions are among the few outside branches that change 7436a11e3a15SNicholas Piggin * NIP without taking an interrupt. Single step trace interrupts 7437a11e3a15SNicholas Piggin * do not fire on completion of these instructions. 7438a11e3a15SNicholas Piggin */ 7439a11e3a15SNicholas Piggin rfi_type = true; 7440a9b5b3d0SRichard Henderson break; 7441a9b5b3d0SRichard Henderson default: 7442a9b5b3d0SRichard Henderson g_assert_not_reached(); 7443fcf5ef2aSThomas Huth } 744413b45575SRichard Henderson 7445a11e3a15SNicholas Piggin gen_debug_exception(ctx, rfi_type); 7446a9b5b3d0SRichard Henderson return; 7447a9b5b3d0SRichard Henderson } 7448a9b5b3d0SRichard Henderson 7449a9b5b3d0SRichard Henderson switch (is_jmp) { 7450a9b5b3d0SRichard Henderson case DISAS_TOO_MANY: 7451a9b5b3d0SRichard Henderson if (use_goto_tb(ctx, nip)) { 745246d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 7453a9b5b3d0SRichard Henderson tcg_gen_goto_tb(0); 7454a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7455a9b5b3d0SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, 0); 7456a9b5b3d0SRichard Henderson break; 7457a9b5b3d0SRichard Henderson } 7458a9b5b3d0SRichard Henderson /* fall through */ 7459a9b5b3d0SRichard Henderson case DISAS_CHAIN_UPDATE: 7460a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7461a9b5b3d0SRichard Henderson /* fall through */ 7462a9b5b3d0SRichard Henderson case DISAS_CHAIN: 746346d396bdSDaniel Henrique Barboza /* 746446d396bdSDaniel Henrique Barboza * tcg_gen_lookup_and_goto_ptr will exit the TB if 746546d396bdSDaniel Henrique Barboza * CF_NO_GOTO_PTR is set. Count insns now. 746646d396bdSDaniel Henrique Barboza */ 746746d396bdSDaniel Henrique Barboza if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { 746846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 746946d396bdSDaniel Henrique Barboza } 747046d396bdSDaniel Henrique Barboza 7471a9b5b3d0SRichard Henderson tcg_gen_lookup_and_goto_ptr(); 7472a9b5b3d0SRichard Henderson break; 7473a9b5b3d0SRichard Henderson 7474a9b5b3d0SRichard Henderson case DISAS_EXIT_UPDATE: 7475a9b5b3d0SRichard Henderson gen_update_nip(ctx, nip); 7476a9b5b3d0SRichard Henderson /* fall through */ 7477a9b5b3d0SRichard Henderson case DISAS_EXIT: 747846d396bdSDaniel Henrique Barboza pmu_count_insns(ctx); 747907ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7480a9b5b3d0SRichard Henderson break; 7481a9b5b3d0SRichard Henderson 7482a9b5b3d0SRichard Henderson default: 7483a9b5b3d0SRichard Henderson g_assert_not_reached(); 7484fcf5ef2aSThomas Huth } 7485fcf5ef2aSThomas Huth } 7486b0c2d521SEmilio G. Cota 74878eb806a7SRichard Henderson static void ppc_tr_disas_log(const DisasContextBase *dcbase, 74888eb806a7SRichard Henderson CPUState *cs, FILE *logfile) 7489b0c2d521SEmilio G. Cota { 74908eb806a7SRichard Henderson fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 74918eb806a7SRichard Henderson target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); 7492b0c2d521SEmilio G. Cota } 7493b0c2d521SEmilio G. Cota 7494b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7495b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7496b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7497b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7498b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7499b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7500b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7501b0c2d521SEmilio G. Cota }; 7502b0c2d521SEmilio G. Cota 7503597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 7504306c8721SRichard Henderson target_ulong pc, void *host_pc) 7505b0c2d521SEmilio G. Cota { 7506b0c2d521SEmilio G. Cota DisasContext ctx; 7507b0c2d521SEmilio G. Cota 7508306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); 7509fcf5ef2aSThomas Huth } 7510