1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26fcf5ef2aSThomas Huth #include "tcg-op.h" 27fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #include "trace-tcg.h" 34fcf5ef2aSThomas Huth #include "exec/log.h" 35fcf5ef2aSThomas Huth 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 38fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 39fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 40fcf5ef2aSThomas Huth 41fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 42fcf5ef2aSThomas Huth //#define PPC_DEBUG_DISAS 43fcf5ef2aSThomas Huth //#define DO_PPC_STATISTICS 44fcf5ef2aSThomas Huth 45fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 46fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 47fcf5ef2aSThomas Huth #else 48fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 49fcf5ef2aSThomas Huth #endif 50fcf5ef2aSThomas Huth /*****************************************************************************/ 51fcf5ef2aSThomas Huth /* Code translation helpers */ 52fcf5ef2aSThomas Huth 53fcf5ef2aSThomas Huth /* global register indexes */ 54fcf5ef2aSThomas Huth static TCGv_env cpu_env; 55fcf5ef2aSThomas Huth static char cpu_reg_names[10*3 + 22*4 /* GPR */ 56fcf5ef2aSThomas Huth + 10*4 + 22*5 /* SPE GPRh */ 57fcf5ef2aSThomas Huth + 10*4 + 22*5 /* FPR */ 58fcf5ef2aSThomas Huth + 2*(10*6 + 22*7) /* AVRh, AVRl */ 59fcf5ef2aSThomas Huth + 10*5 + 22*6 /* VSR */ 60fcf5ef2aSThomas Huth + 8*5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[32]; 64fcf5ef2aSThomas Huth static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 65fcf5ef2aSThomas Huth static TCGv_i64 cpu_vsr[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char* p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth static int done_init = 0; 88fcf5ef2aSThomas Huth 89fcf5ef2aSThomas Huth if (done_init) 90fcf5ef2aSThomas Huth return; 91fcf5ef2aSThomas Huth 92fcf5ef2aSThomas Huth cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); 93fcf5ef2aSThomas Huth tcg_ctx.tcg_env = cpu_env; 94fcf5ef2aSThomas Huth 95fcf5ef2aSThomas Huth p = cpu_reg_names; 96fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 97fcf5ef2aSThomas Huth 98fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 99fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 100fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 101fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 102fcf5ef2aSThomas Huth p += 5; 103fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 104fcf5ef2aSThomas Huth } 105fcf5ef2aSThomas Huth 106fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 107fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 108fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 109fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 110fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 111fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 112fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 113fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 114fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 115fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 116fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 117fcf5ef2aSThomas Huth 118fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "fp%d", i); 119fcf5ef2aSThomas Huth cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 120fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpr[i]), p); 121fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 122fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 123fcf5ef2aSThomas Huth 124fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dH", i); 125fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 126fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 127fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 128fcf5ef2aSThomas Huth #else 129fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 130fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 131fcf5ef2aSThomas Huth #endif 132fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 133fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 134fcf5ef2aSThomas Huth 135fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dL", i); 136fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 137fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 138fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 139fcf5ef2aSThomas Huth #else 140fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 141fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 142fcf5ef2aSThomas Huth #endif 143fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 144fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 145fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "vsr%d", i); 146fcf5ef2aSThomas Huth cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 147fcf5ef2aSThomas Huth offsetof(CPUPPCState, vsr[i]), p); 148fcf5ef2aSThomas Huth p += (i < 10) ? 5 : 6; 149fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 5 : 6; 150fcf5ef2aSThomas Huth } 151fcf5ef2aSThomas Huth 152fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 153fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 154fcf5ef2aSThomas Huth 155fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 156fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 157fcf5ef2aSThomas Huth 158fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 159fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 160fcf5ef2aSThomas Huth 161fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 162fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 163fcf5ef2aSThomas Huth 164fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 165fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 166fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 167fcf5ef2aSThomas Huth #endif 168fcf5ef2aSThomas Huth 169fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 170fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 171fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 172fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 173fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 174fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 175fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 176fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 177dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 178dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 179dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 180dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 181fcf5ef2aSThomas Huth 182fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 183fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 184fcf5ef2aSThomas Huth "reserve_addr"); 185253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 186253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 187253ce7b2SNikunj A Dadhania "reserve_val"); 188fcf5ef2aSThomas Huth 189fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 190fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 191fcf5ef2aSThomas Huth 192fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 193fcf5ef2aSThomas Huth offsetof(CPUPPCState, access_type), "access_type"); 194fcf5ef2aSThomas Huth 195fcf5ef2aSThomas Huth done_init = 1; 196fcf5ef2aSThomas Huth } 197fcf5ef2aSThomas Huth 198fcf5ef2aSThomas Huth /* internal defines */ 199fcf5ef2aSThomas Huth struct DisasContext { 200fcf5ef2aSThomas Huth struct TranslationBlock *tb; 201fcf5ef2aSThomas Huth target_ulong nip; 202fcf5ef2aSThomas Huth uint32_t opcode; 203fcf5ef2aSThomas Huth uint32_t exception; 204fcf5ef2aSThomas Huth /* Routine used to access memory */ 205fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 206fcf5ef2aSThomas Huth bool lazy_tlb_flush; 207fcf5ef2aSThomas Huth bool need_access_type; 208fcf5ef2aSThomas Huth int mem_idx; 209fcf5ef2aSThomas Huth int access_type; 210fcf5ef2aSThomas Huth /* Translation flags */ 211fcf5ef2aSThomas Huth TCGMemOp default_tcg_memop_mask; 212fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 213fcf5ef2aSThomas Huth bool sf_mode; 214fcf5ef2aSThomas Huth bool has_cfar; 215fcf5ef2aSThomas Huth #endif 216fcf5ef2aSThomas Huth bool fpu_enabled; 217fcf5ef2aSThomas Huth bool altivec_enabled; 218fcf5ef2aSThomas Huth bool vsx_enabled; 219fcf5ef2aSThomas Huth bool spe_enabled; 220fcf5ef2aSThomas Huth bool tm_enabled; 221c6fd28fdSSuraj Jitindar Singh bool gtse; 222fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 223fcf5ef2aSThomas Huth int singlestep_enabled; 224fcf5ef2aSThomas Huth uint64_t insns_flags; 225fcf5ef2aSThomas Huth uint64_t insns_flags2; 226fcf5ef2aSThomas Huth }; 227fcf5ef2aSThomas Huth 228fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 229fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 230fcf5ef2aSThomas Huth { 231fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 232fcf5ef2aSThomas Huth return ctx->le_mode; 233fcf5ef2aSThomas Huth #else 234fcf5ef2aSThomas Huth return !ctx->le_mode; 235fcf5ef2aSThomas Huth #endif 236fcf5ef2aSThomas Huth } 237fcf5ef2aSThomas Huth 238fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 239fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 240fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 241fcf5ef2aSThomas Huth #else 242fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 243fcf5ef2aSThomas Huth #endif 244fcf5ef2aSThomas Huth 245fcf5ef2aSThomas Huth struct opc_handler_t { 246fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 247fcf5ef2aSThomas Huth uint32_t inval1; 248fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 249fcf5ef2aSThomas Huth uint32_t inval2; 250fcf5ef2aSThomas Huth /* instruction type */ 251fcf5ef2aSThomas Huth uint64_t type; 252fcf5ef2aSThomas Huth /* extended instruction type */ 253fcf5ef2aSThomas Huth uint64_t type2; 254fcf5ef2aSThomas Huth /* handler */ 255fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 256fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 257fcf5ef2aSThomas Huth const char *oname; 258fcf5ef2aSThomas Huth #endif 259fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 260fcf5ef2aSThomas Huth uint64_t count; 261fcf5ef2aSThomas Huth #endif 262fcf5ef2aSThomas Huth }; 263fcf5ef2aSThomas Huth 264fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 265fcf5ef2aSThomas Huth { 266fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 267fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 268fcf5ef2aSThomas Huth ctx->access_type = access_type; 269fcf5ef2aSThomas Huth } 270fcf5ef2aSThomas Huth } 271fcf5ef2aSThomas Huth 272fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 273fcf5ef2aSThomas Huth { 274fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 275fcf5ef2aSThomas Huth nip = (uint32_t)nip; 276fcf5ef2aSThomas Huth } 277fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 278fcf5ef2aSThomas Huth } 279fcf5ef2aSThomas Huth 280fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 281fcf5ef2aSThomas Huth { 282fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 283fcf5ef2aSThomas Huth 284fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 285fcf5ef2aSThomas Huth * the faulting instruction 286fcf5ef2aSThomas Huth */ 287fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 288fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 289fcf5ef2aSThomas Huth } 290fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 291fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 292fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 293fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 294fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 295fcf5ef2aSThomas Huth ctx->exception = (excp); 296fcf5ef2aSThomas Huth } 297fcf5ef2aSThomas Huth 298fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 299fcf5ef2aSThomas Huth { 300fcf5ef2aSThomas Huth TCGv_i32 t0; 301fcf5ef2aSThomas Huth 302fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 303fcf5ef2aSThomas Huth * the faulting instruction 304fcf5ef2aSThomas Huth */ 305fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 306fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 307fcf5ef2aSThomas Huth } 308fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 309fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 310fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 311fcf5ef2aSThomas Huth ctx->exception = (excp); 312fcf5ef2aSThomas Huth } 313fcf5ef2aSThomas Huth 314fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 315fcf5ef2aSThomas Huth target_ulong nip) 316fcf5ef2aSThomas Huth { 317fcf5ef2aSThomas Huth TCGv_i32 t0; 318fcf5ef2aSThomas Huth 319fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 320fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 321fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 322fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 323fcf5ef2aSThomas Huth ctx->exception = (excp); 324fcf5ef2aSThomas Huth } 325fcf5ef2aSThomas Huth 326fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 327fcf5ef2aSThomas Huth { 328fcf5ef2aSThomas Huth TCGv_i32 t0; 329fcf5ef2aSThomas Huth 330fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 331fcf5ef2aSThomas Huth * the faulting instruction 332fcf5ef2aSThomas Huth */ 333fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 334fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 335fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 336fcf5ef2aSThomas Huth } 337fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 338fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 339fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 340fcf5ef2aSThomas Huth } 341fcf5ef2aSThomas Huth 342fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 343fcf5ef2aSThomas Huth { 344fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 345fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 346fcf5ef2aSThomas Huth } 347fcf5ef2aSThomas Huth 348fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 349fcf5ef2aSThomas Huth { 350fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 351fcf5ef2aSThomas Huth } 352fcf5ef2aSThomas Huth 353fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 354fcf5ef2aSThomas Huth { 355fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 356fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 357fcf5ef2aSThomas Huth } 358fcf5ef2aSThomas Huth 359fcf5ef2aSThomas Huth /* Stop translation */ 360fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 361fcf5ef2aSThomas Huth { 362fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 363fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 364fcf5ef2aSThomas Huth } 365fcf5ef2aSThomas Huth 366fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 367fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 368fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 369fcf5ef2aSThomas Huth { 370fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 371fcf5ef2aSThomas Huth } 372fcf5ef2aSThomas Huth #endif 373fcf5ef2aSThomas Huth 374fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 375fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 376fcf5ef2aSThomas Huth 377fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 378fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 379fcf5ef2aSThomas Huth 380fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 381fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 382fcf5ef2aSThomas Huth 383fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 384fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 385fcf5ef2aSThomas Huth 386fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 387fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 388fcf5ef2aSThomas Huth 389fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 390fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 391fcf5ef2aSThomas Huth 392fcf5ef2aSThomas Huth typedef struct opcode_t { 393fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 394fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 395fcf5ef2aSThomas Huth unsigned char pad[4]; 396fcf5ef2aSThomas Huth #endif 397fcf5ef2aSThomas Huth opc_handler_t handler; 398fcf5ef2aSThomas Huth const char *oname; 399fcf5ef2aSThomas Huth } opcode_t; 400fcf5ef2aSThomas Huth 401fcf5ef2aSThomas Huth /* Helpers for priv. check */ 402fcf5ef2aSThomas Huth #define GEN_PRIV \ 403fcf5ef2aSThomas Huth do { \ 404fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 405fcf5ef2aSThomas Huth } while (0) 406fcf5ef2aSThomas Huth 407fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 408fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 409fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 410fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 411fcf5ef2aSThomas Huth #else 412fcf5ef2aSThomas Huth #define CHK_HV \ 413fcf5ef2aSThomas Huth do { \ 414fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 415fcf5ef2aSThomas Huth GEN_PRIV; \ 416fcf5ef2aSThomas Huth } \ 417fcf5ef2aSThomas Huth } while (0) 418fcf5ef2aSThomas Huth #define CHK_SV \ 419fcf5ef2aSThomas Huth do { \ 420fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 421fcf5ef2aSThomas Huth GEN_PRIV; \ 422fcf5ef2aSThomas Huth } \ 423fcf5ef2aSThomas Huth } while (0) 424fcf5ef2aSThomas Huth #define CHK_HVRM \ 425fcf5ef2aSThomas Huth do { \ 426fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 427fcf5ef2aSThomas Huth GEN_PRIV; \ 428fcf5ef2aSThomas Huth } \ 429fcf5ef2aSThomas Huth } while (0) 430fcf5ef2aSThomas Huth #endif 431fcf5ef2aSThomas Huth 432fcf5ef2aSThomas Huth #define CHK_NONE 433fcf5ef2aSThomas Huth 434fcf5ef2aSThomas Huth /*****************************************************************************/ 435fcf5ef2aSThomas Huth /* PowerPC instructions table */ 436fcf5ef2aSThomas Huth 437fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 438fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 439fcf5ef2aSThomas Huth { \ 440fcf5ef2aSThomas Huth .opc1 = op1, \ 441fcf5ef2aSThomas Huth .opc2 = op2, \ 442fcf5ef2aSThomas Huth .opc3 = op3, \ 443fcf5ef2aSThomas Huth .opc4 = 0xff, \ 444fcf5ef2aSThomas Huth .handler = { \ 445fcf5ef2aSThomas Huth .inval1 = invl, \ 446fcf5ef2aSThomas Huth .type = _typ, \ 447fcf5ef2aSThomas Huth .type2 = _typ2, \ 448fcf5ef2aSThomas Huth .handler = &gen_##name, \ 449fcf5ef2aSThomas Huth .oname = stringify(name), \ 450fcf5ef2aSThomas Huth }, \ 451fcf5ef2aSThomas Huth .oname = stringify(name), \ 452fcf5ef2aSThomas Huth } 453fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 454fcf5ef2aSThomas Huth { \ 455fcf5ef2aSThomas Huth .opc1 = op1, \ 456fcf5ef2aSThomas Huth .opc2 = op2, \ 457fcf5ef2aSThomas Huth .opc3 = op3, \ 458fcf5ef2aSThomas Huth .opc4 = 0xff, \ 459fcf5ef2aSThomas Huth .handler = { \ 460fcf5ef2aSThomas Huth .inval1 = invl1, \ 461fcf5ef2aSThomas Huth .inval2 = invl2, \ 462fcf5ef2aSThomas Huth .type = _typ, \ 463fcf5ef2aSThomas Huth .type2 = _typ2, \ 464fcf5ef2aSThomas Huth .handler = &gen_##name, \ 465fcf5ef2aSThomas Huth .oname = stringify(name), \ 466fcf5ef2aSThomas Huth }, \ 467fcf5ef2aSThomas Huth .oname = stringify(name), \ 468fcf5ef2aSThomas Huth } 469fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 470fcf5ef2aSThomas Huth { \ 471fcf5ef2aSThomas Huth .opc1 = op1, \ 472fcf5ef2aSThomas Huth .opc2 = op2, \ 473fcf5ef2aSThomas Huth .opc3 = op3, \ 474fcf5ef2aSThomas Huth .opc4 = 0xff, \ 475fcf5ef2aSThomas Huth .handler = { \ 476fcf5ef2aSThomas Huth .inval1 = invl, \ 477fcf5ef2aSThomas Huth .type = _typ, \ 478fcf5ef2aSThomas Huth .type2 = _typ2, \ 479fcf5ef2aSThomas Huth .handler = &gen_##name, \ 480fcf5ef2aSThomas Huth .oname = onam, \ 481fcf5ef2aSThomas Huth }, \ 482fcf5ef2aSThomas Huth .oname = onam, \ 483fcf5ef2aSThomas Huth } 484fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 485fcf5ef2aSThomas Huth { \ 486fcf5ef2aSThomas Huth .opc1 = op1, \ 487fcf5ef2aSThomas Huth .opc2 = op2, \ 488fcf5ef2aSThomas Huth .opc3 = op3, \ 489fcf5ef2aSThomas Huth .opc4 = op4, \ 490fcf5ef2aSThomas Huth .handler = { \ 491fcf5ef2aSThomas Huth .inval1 = invl, \ 492fcf5ef2aSThomas Huth .type = _typ, \ 493fcf5ef2aSThomas Huth .type2 = _typ2, \ 494fcf5ef2aSThomas Huth .handler = &gen_##name, \ 495fcf5ef2aSThomas Huth .oname = stringify(name), \ 496fcf5ef2aSThomas Huth }, \ 497fcf5ef2aSThomas Huth .oname = stringify(name), \ 498fcf5ef2aSThomas Huth } 499fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 500fcf5ef2aSThomas Huth { \ 501fcf5ef2aSThomas Huth .opc1 = op1, \ 502fcf5ef2aSThomas Huth .opc2 = op2, \ 503fcf5ef2aSThomas Huth .opc3 = op3, \ 504fcf5ef2aSThomas Huth .opc4 = op4, \ 505fcf5ef2aSThomas Huth .handler = { \ 506fcf5ef2aSThomas Huth .inval1 = invl, \ 507fcf5ef2aSThomas Huth .type = _typ, \ 508fcf5ef2aSThomas Huth .type2 = _typ2, \ 509fcf5ef2aSThomas Huth .handler = &gen_##name, \ 510fcf5ef2aSThomas Huth .oname = onam, \ 511fcf5ef2aSThomas Huth }, \ 512fcf5ef2aSThomas Huth .oname = onam, \ 513fcf5ef2aSThomas Huth } 514fcf5ef2aSThomas Huth #else 515fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 516fcf5ef2aSThomas Huth { \ 517fcf5ef2aSThomas Huth .opc1 = op1, \ 518fcf5ef2aSThomas Huth .opc2 = op2, \ 519fcf5ef2aSThomas Huth .opc3 = op3, \ 520fcf5ef2aSThomas Huth .opc4 = 0xff, \ 521fcf5ef2aSThomas Huth .handler = { \ 522fcf5ef2aSThomas Huth .inval1 = invl, \ 523fcf5ef2aSThomas Huth .type = _typ, \ 524fcf5ef2aSThomas Huth .type2 = _typ2, \ 525fcf5ef2aSThomas Huth .handler = &gen_##name, \ 526fcf5ef2aSThomas Huth }, \ 527fcf5ef2aSThomas Huth .oname = stringify(name), \ 528fcf5ef2aSThomas Huth } 529fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 530fcf5ef2aSThomas Huth { \ 531fcf5ef2aSThomas Huth .opc1 = op1, \ 532fcf5ef2aSThomas Huth .opc2 = op2, \ 533fcf5ef2aSThomas Huth .opc3 = op3, \ 534fcf5ef2aSThomas Huth .opc4 = 0xff, \ 535fcf5ef2aSThomas Huth .handler = { \ 536fcf5ef2aSThomas Huth .inval1 = invl1, \ 537fcf5ef2aSThomas Huth .inval2 = invl2, \ 538fcf5ef2aSThomas Huth .type = _typ, \ 539fcf5ef2aSThomas Huth .type2 = _typ2, \ 540fcf5ef2aSThomas Huth .handler = &gen_##name, \ 541fcf5ef2aSThomas Huth }, \ 542fcf5ef2aSThomas Huth .oname = stringify(name), \ 543fcf5ef2aSThomas Huth } 544fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 545fcf5ef2aSThomas Huth { \ 546fcf5ef2aSThomas Huth .opc1 = op1, \ 547fcf5ef2aSThomas Huth .opc2 = op2, \ 548fcf5ef2aSThomas Huth .opc3 = op3, \ 549fcf5ef2aSThomas Huth .opc4 = 0xff, \ 550fcf5ef2aSThomas Huth .handler = { \ 551fcf5ef2aSThomas Huth .inval1 = invl, \ 552fcf5ef2aSThomas Huth .type = _typ, \ 553fcf5ef2aSThomas Huth .type2 = _typ2, \ 554fcf5ef2aSThomas Huth .handler = &gen_##name, \ 555fcf5ef2aSThomas Huth }, \ 556fcf5ef2aSThomas Huth .oname = onam, \ 557fcf5ef2aSThomas Huth } 558fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 559fcf5ef2aSThomas Huth { \ 560fcf5ef2aSThomas Huth .opc1 = op1, \ 561fcf5ef2aSThomas Huth .opc2 = op2, \ 562fcf5ef2aSThomas Huth .opc3 = op3, \ 563fcf5ef2aSThomas Huth .opc4 = op4, \ 564fcf5ef2aSThomas Huth .handler = { \ 565fcf5ef2aSThomas Huth .inval1 = invl, \ 566fcf5ef2aSThomas Huth .type = _typ, \ 567fcf5ef2aSThomas Huth .type2 = _typ2, \ 568fcf5ef2aSThomas Huth .handler = &gen_##name, \ 569fcf5ef2aSThomas Huth }, \ 570fcf5ef2aSThomas Huth .oname = stringify(name), \ 571fcf5ef2aSThomas Huth } 572fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 573fcf5ef2aSThomas Huth { \ 574fcf5ef2aSThomas Huth .opc1 = op1, \ 575fcf5ef2aSThomas Huth .opc2 = op2, \ 576fcf5ef2aSThomas Huth .opc3 = op3, \ 577fcf5ef2aSThomas Huth .opc4 = op4, \ 578fcf5ef2aSThomas Huth .handler = { \ 579fcf5ef2aSThomas Huth .inval1 = invl, \ 580fcf5ef2aSThomas Huth .type = _typ, \ 581fcf5ef2aSThomas Huth .type2 = _typ2, \ 582fcf5ef2aSThomas Huth .handler = &gen_##name, \ 583fcf5ef2aSThomas Huth }, \ 584fcf5ef2aSThomas Huth .oname = onam, \ 585fcf5ef2aSThomas Huth } 586fcf5ef2aSThomas Huth #endif 587fcf5ef2aSThomas Huth 588fcf5ef2aSThomas Huth /* SPR load/store helpers */ 589fcf5ef2aSThomas Huth static inline void gen_load_spr(TCGv t, int reg) 590fcf5ef2aSThomas Huth { 591fcf5ef2aSThomas Huth tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 592fcf5ef2aSThomas Huth } 593fcf5ef2aSThomas Huth 594fcf5ef2aSThomas Huth static inline void gen_store_spr(int reg, TCGv t) 595fcf5ef2aSThomas Huth { 596fcf5ef2aSThomas Huth tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 597fcf5ef2aSThomas Huth } 598fcf5ef2aSThomas Huth 599fcf5ef2aSThomas Huth /* Invalid instruction */ 600fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 601fcf5ef2aSThomas Huth { 602fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 603fcf5ef2aSThomas Huth } 604fcf5ef2aSThomas Huth 605fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 606fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 607fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 608fcf5ef2aSThomas Huth .type = PPC_NONE, 609fcf5ef2aSThomas Huth .type2 = PPC_NONE, 610fcf5ef2aSThomas Huth .handler = gen_invalid, 611fcf5ef2aSThomas Huth }; 612fcf5ef2aSThomas Huth 613fcf5ef2aSThomas Huth /*** Integer comparison ***/ 614fcf5ef2aSThomas Huth 615fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 616fcf5ef2aSThomas Huth { 617fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 618fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 619fcf5ef2aSThomas Huth 620fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 621fcf5ef2aSThomas Huth 622fcf5ef2aSThomas Huth tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); 623fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 624efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_LT_BIT); 625fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 626fcf5ef2aSThomas Huth 627fcf5ef2aSThomas Huth tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); 628fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 629efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_GT_BIT); 630fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 631fcf5ef2aSThomas Huth 632fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); 633fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t0); 634efa73196SNikunj A Dadhania tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT); 635fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); 636fcf5ef2aSThomas Huth 637fcf5ef2aSThomas Huth tcg_temp_free(t0); 638fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 639fcf5ef2aSThomas Huth } 640fcf5ef2aSThomas Huth 641fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 642fcf5ef2aSThomas Huth { 643fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 644fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 645fcf5ef2aSThomas Huth tcg_temp_free(t0); 646fcf5ef2aSThomas Huth } 647fcf5ef2aSThomas Huth 648fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 649fcf5ef2aSThomas Huth { 650fcf5ef2aSThomas Huth TCGv t0, t1; 651fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 652fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 653fcf5ef2aSThomas Huth if (s) { 654fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 655fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 656fcf5ef2aSThomas Huth } else { 657fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 658fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 659fcf5ef2aSThomas Huth } 660fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 661fcf5ef2aSThomas Huth tcg_temp_free(t1); 662fcf5ef2aSThomas Huth tcg_temp_free(t0); 663fcf5ef2aSThomas Huth } 664fcf5ef2aSThomas Huth 665fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 666fcf5ef2aSThomas Huth { 667fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 668fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 669fcf5ef2aSThomas Huth tcg_temp_free(t0); 670fcf5ef2aSThomas Huth } 671fcf5ef2aSThomas Huth 672fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 673fcf5ef2aSThomas Huth { 674fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 675fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 676fcf5ef2aSThomas Huth } else { 677fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 678fcf5ef2aSThomas Huth } 679fcf5ef2aSThomas Huth } 680fcf5ef2aSThomas Huth 681fcf5ef2aSThomas Huth /* cmp */ 682fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 683fcf5ef2aSThomas Huth { 684fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 685fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 686fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 687fcf5ef2aSThomas Huth } else { 688fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 689fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 690fcf5ef2aSThomas Huth } 691fcf5ef2aSThomas Huth } 692fcf5ef2aSThomas Huth 693fcf5ef2aSThomas Huth /* cmpi */ 694fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 695fcf5ef2aSThomas Huth { 696fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 697fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 698fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 699fcf5ef2aSThomas Huth } else { 700fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 701fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 702fcf5ef2aSThomas Huth } 703fcf5ef2aSThomas Huth } 704fcf5ef2aSThomas Huth 705fcf5ef2aSThomas Huth /* cmpl */ 706fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 707fcf5ef2aSThomas Huth { 708fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 709fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 710fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 711fcf5ef2aSThomas Huth } else { 712fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 713fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 714fcf5ef2aSThomas Huth } 715fcf5ef2aSThomas Huth } 716fcf5ef2aSThomas Huth 717fcf5ef2aSThomas Huth /* cmpli */ 718fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 719fcf5ef2aSThomas Huth { 720fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 721fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 722fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 723fcf5ef2aSThomas Huth } else { 724fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 725fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 726fcf5ef2aSThomas Huth } 727fcf5ef2aSThomas Huth } 728fcf5ef2aSThomas Huth 729fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 730fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 731fcf5ef2aSThomas Huth { 732fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 733fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 734fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 735fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 736fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 737fcf5ef2aSThomas Huth 738fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 739fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 740fcf5ef2aSThomas Huth 741fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 742fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 743fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 744fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 745fcf5ef2aSThomas Huth 746fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 747fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 748fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 749fcf5ef2aSThomas Huth 750fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 751fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 752fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 753fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 754fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 755fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 756fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 757fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 758fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 759fcf5ef2aSThomas Huth } 760efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 761fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 762fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 763fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 764fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 765fcf5ef2aSThomas Huth } 766fcf5ef2aSThomas Huth 767fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 768fcf5ef2aSThomas Huth /* cmpeqb */ 769fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 770fcf5ef2aSThomas Huth { 771fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 772fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 773fcf5ef2aSThomas Huth } 774fcf5ef2aSThomas Huth #endif 775fcf5ef2aSThomas Huth 776fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 777fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 778fcf5ef2aSThomas Huth { 779fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 780fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 781fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 782fcf5ef2aSThomas Huth TCGv zr; 783fcf5ef2aSThomas Huth 784fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 785fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 786fcf5ef2aSThomas Huth 787fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 788fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 789fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 790fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 791fcf5ef2aSThomas Huth tcg_temp_free(zr); 792fcf5ef2aSThomas Huth tcg_temp_free(t0); 793fcf5ef2aSThomas Huth } 794fcf5ef2aSThomas Huth 795fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 796fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 797fcf5ef2aSThomas Huth { 798fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 799fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 800fcf5ef2aSThomas Huth } 801fcf5ef2aSThomas Huth 802fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 803fcf5ef2aSThomas Huth 804fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 805fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 806fcf5ef2aSThomas Huth { 807fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 808fcf5ef2aSThomas Huth 809fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 810fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 811fcf5ef2aSThomas Huth if (sub) { 812fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 813fcf5ef2aSThomas Huth } else { 814fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 815fcf5ef2aSThomas Huth } 816fcf5ef2aSThomas Huth tcg_temp_free(t0); 817fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 818dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 819dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 820dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 821fcf5ef2aSThomas Huth } 822dc0ad844SNikunj A Dadhania } else { 823dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 824dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 825dc0ad844SNikunj A Dadhania } 82638a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 827dc0ad844SNikunj A Dadhania } 828fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 829fcf5ef2aSThomas Huth } 830fcf5ef2aSThomas Huth 8316b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8326b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 8336b10d008SNikunj A Dadhania int sub) 8346b10d008SNikunj A Dadhania { 8356b10d008SNikunj A Dadhania TCGv t0; 8366b10d008SNikunj A Dadhania 8376b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8386b10d008SNikunj A Dadhania return; 8396b10d008SNikunj A Dadhania } 8406b10d008SNikunj A Dadhania 8416b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 84233903d0aSNikunj A Dadhania if (sub) { 84333903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 84433903d0aSNikunj A Dadhania } else { 8456b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 84633903d0aSNikunj A Dadhania } 8476b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 8486b10d008SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); 8496b10d008SNikunj A Dadhania tcg_temp_free(t0); 8506b10d008SNikunj A Dadhania } 8516b10d008SNikunj A Dadhania 852fcf5ef2aSThomas Huth /* Common add function */ 853fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 854fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 855fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 856fcf5ef2aSThomas Huth { 857fcf5ef2aSThomas Huth TCGv t0 = ret; 858fcf5ef2aSThomas Huth 859fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 860fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 861fcf5ef2aSThomas Huth } 862fcf5ef2aSThomas Huth 863fcf5ef2aSThomas Huth if (compute_ca) { 864fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 865fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 866fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 867fcf5ef2aSThomas Huth carry into bit 32. */ 868fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 869fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 870fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 871fcf5ef2aSThomas Huth if (add_ca) { 872fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 873fcf5ef2aSThomas Huth } 874fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 875fcf5ef2aSThomas Huth tcg_temp_free(t1); 876e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 8776b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 8786b10d008SNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 8796b10d008SNikunj A Dadhania } 880fcf5ef2aSThomas Huth } else { 881fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 882fcf5ef2aSThomas Huth if (add_ca) { 883fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 884fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 885fcf5ef2aSThomas Huth } else { 886fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 887fcf5ef2aSThomas Huth } 8886b10d008SNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); 889fcf5ef2aSThomas Huth tcg_temp_free(zero); 890fcf5ef2aSThomas Huth } 891fcf5ef2aSThomas Huth } else { 892fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 893fcf5ef2aSThomas Huth if (add_ca) { 894fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 895fcf5ef2aSThomas Huth } 896fcf5ef2aSThomas Huth } 897fcf5ef2aSThomas Huth 898fcf5ef2aSThomas Huth if (compute_ov) { 899fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 900fcf5ef2aSThomas Huth } 901fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 902fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 903fcf5ef2aSThomas Huth } 904fcf5ef2aSThomas Huth 905*11f4e8f8SRichard Henderson if (t0 != ret) { 906fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 907fcf5ef2aSThomas Huth tcg_temp_free(t0); 908fcf5ef2aSThomas Huth } 909fcf5ef2aSThomas Huth } 910fcf5ef2aSThomas Huth /* Add functions with two operands */ 911fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 912fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 913fcf5ef2aSThomas Huth { \ 914fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 915fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 916fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 917fcf5ef2aSThomas Huth } 918fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 919fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 920fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 921fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 922fcf5ef2aSThomas Huth { \ 923fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 924fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 925fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 926fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 927fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 928fcf5ef2aSThomas Huth } 929fcf5ef2aSThomas Huth 930fcf5ef2aSThomas Huth /* add add. addo addo. */ 931fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 932fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 933fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 934fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 935fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 936fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 937fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 938fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 939fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 940fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 941fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 942fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 943fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 944fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 945fcf5ef2aSThomas Huth /* addi */ 946fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 947fcf5ef2aSThomas Huth { 948fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 949fcf5ef2aSThomas Huth 950fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 951fcf5ef2aSThomas Huth /* li case */ 952fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 953fcf5ef2aSThomas Huth } else { 954fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 955fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 956fcf5ef2aSThomas Huth } 957fcf5ef2aSThomas Huth } 958fcf5ef2aSThomas Huth /* addic addic.*/ 959fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 960fcf5ef2aSThomas Huth { 961fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 962fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 963fcf5ef2aSThomas Huth c, 0, 1, 0, compute_rc0); 964fcf5ef2aSThomas Huth tcg_temp_free(c); 965fcf5ef2aSThomas Huth } 966fcf5ef2aSThomas Huth 967fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 968fcf5ef2aSThomas Huth { 969fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 970fcf5ef2aSThomas Huth } 971fcf5ef2aSThomas Huth 972fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 973fcf5ef2aSThomas Huth { 974fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 975fcf5ef2aSThomas Huth } 976fcf5ef2aSThomas Huth 977fcf5ef2aSThomas Huth /* addis */ 978fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 979fcf5ef2aSThomas Huth { 980fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 981fcf5ef2aSThomas Huth 982fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 983fcf5ef2aSThomas Huth /* lis case */ 984fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 985fcf5ef2aSThomas Huth } else { 986fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 987fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 988fcf5ef2aSThomas Huth } 989fcf5ef2aSThomas Huth } 990fcf5ef2aSThomas Huth 991fcf5ef2aSThomas Huth /* addpcis */ 992fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 993fcf5ef2aSThomas Huth { 994fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 995fcf5ef2aSThomas Huth 996fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16)); 997fcf5ef2aSThomas Huth } 998fcf5ef2aSThomas Huth 999fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1000fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1001fcf5ef2aSThomas Huth { 1002fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1003fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1004fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1005fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1006fcf5ef2aSThomas Huth 1007fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1008fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1009fcf5ef2aSThomas Huth if (sign) { 1010fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1011fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1012fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1013fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1014fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1015fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1016fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1017fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1018fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1019fcf5ef2aSThomas Huth } else { 1020fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1021fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1022fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1023fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1024fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1025fcf5ef2aSThomas Huth } 1026fcf5ef2aSThomas Huth if (compute_ov) { 1027fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1028c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1029c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1030c44027ffSNikunj A Dadhania } 1031fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1032fcf5ef2aSThomas Huth } 1033fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1034fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1035fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1036fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1037fcf5ef2aSThomas Huth 1038fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1039fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1040fcf5ef2aSThomas Huth } 1041fcf5ef2aSThomas Huth /* Div functions */ 1042fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1043fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1044fcf5ef2aSThomas Huth { \ 1045fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1046fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1047fcf5ef2aSThomas Huth sign, compute_ov); \ 1048fcf5ef2aSThomas Huth } 1049fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1050fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1051fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1052fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1053fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1054fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1055fcf5ef2aSThomas Huth 1056fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1057fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1058fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1059fcf5ef2aSThomas Huth { \ 1060fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1061fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1062fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1063fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1064fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1065fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1066fcf5ef2aSThomas Huth } \ 1067fcf5ef2aSThomas Huth } 1068fcf5ef2aSThomas Huth 1069fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1070fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1071fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1072fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1073fcf5ef2aSThomas Huth 1074fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1075fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1076fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1077fcf5ef2aSThomas Huth { 1078fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1079fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1080fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1081fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1082fcf5ef2aSThomas Huth 1083fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1084fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1085fcf5ef2aSThomas Huth if (sign) { 1086fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1087fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1088fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1089fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1090fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1091fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1092fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1093fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1094fcf5ef2aSThomas Huth } else { 1095fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1096fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1097fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1098fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1099fcf5ef2aSThomas Huth } 1100fcf5ef2aSThomas Huth if (compute_ov) { 1101fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1102c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1103c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1104c44027ffSNikunj A Dadhania } 1105fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1106fcf5ef2aSThomas Huth } 1107fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1108fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1109fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1110fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1111fcf5ef2aSThomas Huth 1112fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1113fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1114fcf5ef2aSThomas Huth } 1115fcf5ef2aSThomas Huth 1116fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1117fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1118fcf5ef2aSThomas Huth { \ 1119fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1120fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1121fcf5ef2aSThomas Huth sign, compute_ov); \ 1122fcf5ef2aSThomas Huth } 1123c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1124fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1125fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1126c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1127fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1128fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1129fcf5ef2aSThomas Huth 1130fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1131fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1132fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1133fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1134fcf5ef2aSThomas Huth #endif 1135fcf5ef2aSThomas Huth 1136fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1137fcf5ef2aSThomas Huth TCGv arg2, int sign) 1138fcf5ef2aSThomas Huth { 1139fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1140fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1141fcf5ef2aSThomas Huth 1142fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1143fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1144fcf5ef2aSThomas Huth if (sign) { 1145fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1146fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1147fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1148fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1149fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1150fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1151fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1152fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1153fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1154fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1155fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1156fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1157fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1158fcf5ef2aSThomas Huth } else { 1159fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1160fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1161fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1162fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1163fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1164fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1165fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1166fcf5ef2aSThomas Huth } 1167fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1168fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1169fcf5ef2aSThomas Huth } 1170fcf5ef2aSThomas Huth 1171fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1172fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1173fcf5ef2aSThomas Huth { \ 1174fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1175fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1176fcf5ef2aSThomas Huth sign); \ 1177fcf5ef2aSThomas Huth } 1178fcf5ef2aSThomas Huth 1179fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1180fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1181fcf5ef2aSThomas Huth 1182fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1183fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1184fcf5ef2aSThomas Huth TCGv arg2, int sign) 1185fcf5ef2aSThomas Huth { 1186fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1187fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1188fcf5ef2aSThomas Huth 1189fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1190fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1191fcf5ef2aSThomas Huth if (sign) { 1192fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1193fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1194fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1195fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1196fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1197fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1198fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1199fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1200fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1201fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1202fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1203fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1204fcf5ef2aSThomas Huth } else { 1205fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1206fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1207fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1208fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1209fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1210fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1211fcf5ef2aSThomas Huth } 1212fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1213fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1214fcf5ef2aSThomas Huth } 1215fcf5ef2aSThomas Huth 1216fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1217fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1218fcf5ef2aSThomas Huth { \ 1219fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1220fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1221fcf5ef2aSThomas Huth sign); \ 1222fcf5ef2aSThomas Huth } 1223fcf5ef2aSThomas Huth 1224fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1225fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1226fcf5ef2aSThomas Huth #endif 1227fcf5ef2aSThomas Huth 1228fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1229fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1230fcf5ef2aSThomas Huth { 1231fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1232fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1235fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1236fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1237fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1238fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1239fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1240fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1241fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1242fcf5ef2aSThomas Huth } 1243fcf5ef2aSThomas Huth 1244fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1245fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1246fcf5ef2aSThomas Huth { 1247fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1248fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1249fcf5ef2aSThomas Huth 1250fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1251fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1252fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1253fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1254fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1255fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1256fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1257fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1258fcf5ef2aSThomas Huth } 1259fcf5ef2aSThomas Huth 1260fcf5ef2aSThomas Huth /* mullw mullw. */ 1261fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1262fcf5ef2aSThomas Huth { 1263fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1264fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1265fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1266fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1267fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1268fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1269fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1270fcf5ef2aSThomas Huth tcg_temp_free(t0); 1271fcf5ef2aSThomas Huth tcg_temp_free(t1); 1272fcf5ef2aSThomas Huth #else 1273fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1274fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1275fcf5ef2aSThomas Huth #endif 1276fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1277fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1278fcf5ef2aSThomas Huth } 1279fcf5ef2aSThomas Huth 1280fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1281fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1282fcf5ef2aSThomas Huth { 1283fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1284fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1285fcf5ef2aSThomas Huth 1286fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1287fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1288fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1289fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1290fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1291fcf5ef2aSThomas Huth #else 1292fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1293fcf5ef2aSThomas Huth #endif 1294fcf5ef2aSThomas Huth 1295fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1296fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1297fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 129861aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 129961aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 130061aa9a69SNikunj A Dadhania } 1301fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1302fcf5ef2aSThomas Huth 1303fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1304fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1305fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1306fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1307fcf5ef2aSThomas Huth } 1308fcf5ef2aSThomas Huth 1309fcf5ef2aSThomas Huth /* mulli */ 1310fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1311fcf5ef2aSThomas Huth { 1312fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1313fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1314fcf5ef2aSThomas Huth } 1315fcf5ef2aSThomas Huth 1316fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1317fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1318fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1319fcf5ef2aSThomas Huth { 1320fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1321fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1322fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1323fcf5ef2aSThomas Huth tcg_temp_free(lo); 1324fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1325fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1326fcf5ef2aSThomas Huth } 1327fcf5ef2aSThomas Huth } 1328fcf5ef2aSThomas Huth 1329fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1330fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1331fcf5ef2aSThomas Huth { 1332fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1333fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1334fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1335fcf5ef2aSThomas Huth tcg_temp_free(lo); 1336fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1337fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1338fcf5ef2aSThomas Huth } 1339fcf5ef2aSThomas Huth } 1340fcf5ef2aSThomas Huth 1341fcf5ef2aSThomas Huth /* mulld mulld. */ 1342fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1343fcf5ef2aSThomas Huth { 1344fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1345fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1346fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1347fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1348fcf5ef2aSThomas Huth } 1349fcf5ef2aSThomas Huth 1350fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1351fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1352fcf5ef2aSThomas Huth { 1353fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1354fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1355fcf5ef2aSThomas Huth 1356fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1357fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1358fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1359fcf5ef2aSThomas Huth 1360fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1361fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 136261aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 136361aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 136461aa9a69SNikunj A Dadhania } 1365fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1366fcf5ef2aSThomas Huth 1367fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1368fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1369fcf5ef2aSThomas Huth 1370fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1371fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1372fcf5ef2aSThomas Huth } 1373fcf5ef2aSThomas Huth } 1374fcf5ef2aSThomas Huth #endif 1375fcf5ef2aSThomas Huth 1376fcf5ef2aSThomas Huth /* Common subf function */ 1377fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1378fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1379fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1380fcf5ef2aSThomas Huth { 1381fcf5ef2aSThomas Huth TCGv t0 = ret; 1382fcf5ef2aSThomas Huth 1383fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1384fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1385fcf5ef2aSThomas Huth } 1386fcf5ef2aSThomas Huth 1387fcf5ef2aSThomas Huth if (compute_ca) { 1388fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1389fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1390fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 1391fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 1392fcf5ef2aSThomas Huth carry into bit 32. */ 1393fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1394fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1395fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1396fcf5ef2aSThomas Huth if (add_ca) { 1397fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1398fcf5ef2aSThomas Huth } else { 1399fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1400fcf5ef2aSThomas Huth } 1401fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1402fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1403fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1404fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1405fcf5ef2aSThomas Huth tcg_temp_free(t1); 1406e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 140733903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 140833903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 140933903d0aSNikunj A Dadhania } 1410fcf5ef2aSThomas Huth } else if (add_ca) { 1411fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1412fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1413fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1414fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1415fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 141633903d0aSNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); 1417fcf5ef2aSThomas Huth tcg_temp_free(zero); 1418fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1419fcf5ef2aSThomas Huth } else { 1420fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1421fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 142233903d0aSNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); 1423fcf5ef2aSThomas Huth } 1424fcf5ef2aSThomas Huth } else if (add_ca) { 1425fcf5ef2aSThomas Huth /* Since we're ignoring carry-out, we can simplify the 1426fcf5ef2aSThomas Huth standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1427fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1428fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1429fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1430fcf5ef2aSThomas Huth } else { 1431fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1432fcf5ef2aSThomas Huth } 1433fcf5ef2aSThomas Huth 1434fcf5ef2aSThomas Huth if (compute_ov) { 1435fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1436fcf5ef2aSThomas Huth } 1437fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1438fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1439fcf5ef2aSThomas Huth } 1440fcf5ef2aSThomas Huth 1441*11f4e8f8SRichard Henderson if (t0 != ret) { 1442fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1443fcf5ef2aSThomas Huth tcg_temp_free(t0); 1444fcf5ef2aSThomas Huth } 1445fcf5ef2aSThomas Huth } 1446fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1447fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1448fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1449fcf5ef2aSThomas Huth { \ 1450fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1451fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1452fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1453fcf5ef2aSThomas Huth } 1454fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1455fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1456fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1457fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1458fcf5ef2aSThomas Huth { \ 1459fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1460fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1461fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1462fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1463fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1464fcf5ef2aSThomas Huth } 1465fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1466fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1467fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1468fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1469fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1470fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1471fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1472fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1473fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1474fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1475fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1476fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1477fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1478fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1479fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1480fcf5ef2aSThomas Huth 1481fcf5ef2aSThomas Huth /* subfic */ 1482fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1483fcf5ef2aSThomas Huth { 1484fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1485fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1486fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1487fcf5ef2aSThomas Huth tcg_temp_free(c); 1488fcf5ef2aSThomas Huth } 1489fcf5ef2aSThomas Huth 1490fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1491fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1492fcf5ef2aSThomas Huth { 1493fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1494fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1495fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1496fcf5ef2aSThomas Huth tcg_temp_free(zero); 1497fcf5ef2aSThomas Huth } 1498fcf5ef2aSThomas Huth 1499fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1500fcf5ef2aSThomas Huth { 15011480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 15021480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 15031480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 15041480d71cSNikunj A Dadhania } 1505fcf5ef2aSThomas Huth } 1506fcf5ef2aSThomas Huth 1507fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1508fcf5ef2aSThomas Huth { 1509fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1510fcf5ef2aSThomas Huth } 1511fcf5ef2aSThomas Huth 1512fcf5ef2aSThomas Huth /*** Integer logical ***/ 1513fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1514fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1515fcf5ef2aSThomas Huth { \ 1516fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1517fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1518fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1519fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1520fcf5ef2aSThomas Huth } 1521fcf5ef2aSThomas Huth 1522fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1523fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1524fcf5ef2aSThomas Huth { \ 1525fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1526fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1527fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1528fcf5ef2aSThomas Huth } 1529fcf5ef2aSThomas Huth 1530fcf5ef2aSThomas Huth /* and & and. */ 1531fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1532fcf5ef2aSThomas Huth /* andc & andc. */ 1533fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1534fcf5ef2aSThomas Huth 1535fcf5ef2aSThomas Huth /* andi. */ 1536fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1537fcf5ef2aSThomas Huth { 1538fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1539fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1540fcf5ef2aSThomas Huth } 1541fcf5ef2aSThomas Huth 1542fcf5ef2aSThomas Huth /* andis. */ 1543fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1544fcf5ef2aSThomas Huth { 1545fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1546fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1547fcf5ef2aSThomas Huth } 1548fcf5ef2aSThomas Huth 1549fcf5ef2aSThomas Huth /* cntlzw */ 1550fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1551fcf5ef2aSThomas Huth { 15529b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15539b8514e5SRichard Henderson 15549b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15559b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15569b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15579b8514e5SRichard Henderson tcg_temp_free_i32(t); 15589b8514e5SRichard Henderson 1559fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1560fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1561fcf5ef2aSThomas Huth } 1562fcf5ef2aSThomas Huth 1563fcf5ef2aSThomas Huth /* cnttzw */ 1564fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1565fcf5ef2aSThomas Huth { 15669b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15679b8514e5SRichard Henderson 15689b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15699b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15709b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15719b8514e5SRichard Henderson tcg_temp_free_i32(t); 15729b8514e5SRichard Henderson 1573fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1574fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1575fcf5ef2aSThomas Huth } 1576fcf5ef2aSThomas Huth } 1577fcf5ef2aSThomas Huth 1578fcf5ef2aSThomas Huth /* eqv & eqv. */ 1579fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1580fcf5ef2aSThomas Huth /* extsb & extsb. */ 1581fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1582fcf5ef2aSThomas Huth /* extsh & extsh. */ 1583fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1584fcf5ef2aSThomas Huth /* nand & nand. */ 1585fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1586fcf5ef2aSThomas Huth /* nor & nor. */ 1587fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1588fcf5ef2aSThomas Huth 1589fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1590fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1591fcf5ef2aSThomas Huth { 1592fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1593fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1594fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1595fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1596fcf5ef2aSThomas Huth 1597fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1598fcf5ef2aSThomas Huth gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 1599fcf5ef2aSThomas Huth } 1600fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1601fcf5ef2aSThomas Huth 1602fcf5ef2aSThomas Huth /* or & or. */ 1603fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1604fcf5ef2aSThomas Huth { 1605fcf5ef2aSThomas Huth int rs, ra, rb; 1606fcf5ef2aSThomas Huth 1607fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1608fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1609fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1610fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1611fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1612fcf5ef2aSThomas Huth if (rs != rb) 1613fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1614fcf5ef2aSThomas Huth else 1615fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1616fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1617fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1618fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1619fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1620fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1621fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1622fcf5ef2aSThomas Huth int prio = 0; 1623fcf5ef2aSThomas Huth 1624fcf5ef2aSThomas Huth switch (rs) { 1625fcf5ef2aSThomas Huth case 1: 1626fcf5ef2aSThomas Huth /* Set process priority to low */ 1627fcf5ef2aSThomas Huth prio = 2; 1628fcf5ef2aSThomas Huth break; 1629fcf5ef2aSThomas Huth case 6: 1630fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1631fcf5ef2aSThomas Huth prio = 3; 1632fcf5ef2aSThomas Huth break; 1633fcf5ef2aSThomas Huth case 2: 1634fcf5ef2aSThomas Huth /* Set process priority to normal */ 1635fcf5ef2aSThomas Huth prio = 4; 1636fcf5ef2aSThomas Huth break; 1637fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1638fcf5ef2aSThomas Huth case 31: 1639fcf5ef2aSThomas Huth if (!ctx->pr) { 1640fcf5ef2aSThomas Huth /* Set process priority to very low */ 1641fcf5ef2aSThomas Huth prio = 1; 1642fcf5ef2aSThomas Huth } 1643fcf5ef2aSThomas Huth break; 1644fcf5ef2aSThomas Huth case 5: 1645fcf5ef2aSThomas Huth if (!ctx->pr) { 1646fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1647fcf5ef2aSThomas Huth prio = 5; 1648fcf5ef2aSThomas Huth } 1649fcf5ef2aSThomas Huth break; 1650fcf5ef2aSThomas Huth case 3: 1651fcf5ef2aSThomas Huth if (!ctx->pr) { 1652fcf5ef2aSThomas Huth /* Set process priority to high */ 1653fcf5ef2aSThomas Huth prio = 6; 1654fcf5ef2aSThomas Huth } 1655fcf5ef2aSThomas Huth break; 1656fcf5ef2aSThomas Huth case 7: 1657fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1658fcf5ef2aSThomas Huth /* Set process priority to very high */ 1659fcf5ef2aSThomas Huth prio = 7; 1660fcf5ef2aSThomas Huth } 1661fcf5ef2aSThomas Huth break; 1662fcf5ef2aSThomas Huth #endif 1663fcf5ef2aSThomas Huth default: 1664fcf5ef2aSThomas Huth break; 1665fcf5ef2aSThomas Huth } 1666fcf5ef2aSThomas Huth if (prio) { 1667fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1668fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1669fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1670fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1671fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1672fcf5ef2aSThomas Huth tcg_temp_free(t0); 1673fcf5ef2aSThomas Huth } 1674fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1675fcf5ef2aSThomas Huth /* Pause out of TCG otherwise spin loops with smt_low eat too much 1676fcf5ef2aSThomas Huth * CPU and the kernel hangs. This applies to all encodings other 1677fcf5ef2aSThomas Huth * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1678fcf5ef2aSThomas Huth * and all currently undefined. 1679fcf5ef2aSThomas Huth */ 1680fcf5ef2aSThomas Huth gen_pause(ctx); 1681fcf5ef2aSThomas Huth #endif 1682fcf5ef2aSThomas Huth #endif 1683fcf5ef2aSThomas Huth } 1684fcf5ef2aSThomas Huth } 1685fcf5ef2aSThomas Huth /* orc & orc. */ 1686fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1687fcf5ef2aSThomas Huth 1688fcf5ef2aSThomas Huth /* xor & xor. */ 1689fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1690fcf5ef2aSThomas Huth { 1691fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1692fcf5ef2aSThomas Huth if (rS(ctx->opcode) != rB(ctx->opcode)) 1693fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1694fcf5ef2aSThomas Huth else 1695fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1696fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1697fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1698fcf5ef2aSThomas Huth } 1699fcf5ef2aSThomas Huth 1700fcf5ef2aSThomas Huth /* ori */ 1701fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1702fcf5ef2aSThomas Huth { 1703fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1704fcf5ef2aSThomas Huth 1705fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1706fcf5ef2aSThomas Huth return; 1707fcf5ef2aSThomas Huth } 1708fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1709fcf5ef2aSThomas Huth } 1710fcf5ef2aSThomas Huth 1711fcf5ef2aSThomas Huth /* oris */ 1712fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1713fcf5ef2aSThomas Huth { 1714fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1715fcf5ef2aSThomas Huth 1716fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1717fcf5ef2aSThomas Huth /* NOP */ 1718fcf5ef2aSThomas Huth return; 1719fcf5ef2aSThomas Huth } 1720fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1721fcf5ef2aSThomas Huth } 1722fcf5ef2aSThomas Huth 1723fcf5ef2aSThomas Huth /* xori */ 1724fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1725fcf5ef2aSThomas Huth { 1726fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1727fcf5ef2aSThomas Huth 1728fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1729fcf5ef2aSThomas Huth /* NOP */ 1730fcf5ef2aSThomas Huth return; 1731fcf5ef2aSThomas Huth } 1732fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1733fcf5ef2aSThomas Huth } 1734fcf5ef2aSThomas Huth 1735fcf5ef2aSThomas Huth /* xoris */ 1736fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1737fcf5ef2aSThomas Huth { 1738fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1739fcf5ef2aSThomas Huth 1740fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1741fcf5ef2aSThomas Huth /* NOP */ 1742fcf5ef2aSThomas Huth return; 1743fcf5ef2aSThomas Huth } 1744fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1745fcf5ef2aSThomas Huth } 1746fcf5ef2aSThomas Huth 1747fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1748fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1749fcf5ef2aSThomas Huth { 1750fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1751fcf5ef2aSThomas Huth } 1752fcf5ef2aSThomas Huth 1753fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1754fcf5ef2aSThomas Huth { 175579770002SRichard Henderson #if defined(TARGET_PPC64) 1756fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 175779770002SRichard Henderson #else 175879770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 175979770002SRichard Henderson #endif 1760fcf5ef2aSThomas Huth } 1761fcf5ef2aSThomas Huth 1762fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1763fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1764fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1765fcf5ef2aSThomas Huth { 176679770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1767fcf5ef2aSThomas Huth } 1768fcf5ef2aSThomas Huth #endif 1769fcf5ef2aSThomas Huth 1770fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1771fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1772fcf5ef2aSThomas Huth { 1773fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1774fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1775fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1776fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1777fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1778fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1779fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1780fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1781fcf5ef2aSThomas Huth tcg_temp_free(t0); 1782fcf5ef2aSThomas Huth } 1783fcf5ef2aSThomas Huth 1784fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1785fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1786fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1787fcf5ef2aSThomas Huth { 1788fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1789fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1790fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1791fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1792fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1793fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1794fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1795fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1796fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1797fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1798fcf5ef2aSThomas Huth tcg_temp_free(t0); 1799fcf5ef2aSThomas Huth } 1800fcf5ef2aSThomas Huth #endif 1801fcf5ef2aSThomas Huth 1802fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1803fcf5ef2aSThomas Huth /* bpermd */ 1804fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1805fcf5ef2aSThomas Huth { 1806fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1807fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1808fcf5ef2aSThomas Huth } 1809fcf5ef2aSThomas Huth #endif 1810fcf5ef2aSThomas Huth 1811fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1812fcf5ef2aSThomas Huth /* extsw & extsw. */ 1813fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1814fcf5ef2aSThomas Huth 1815fcf5ef2aSThomas Huth /* cntlzd */ 1816fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1817fcf5ef2aSThomas Huth { 18189b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1819fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1820fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1821fcf5ef2aSThomas Huth } 1822fcf5ef2aSThomas Huth 1823fcf5ef2aSThomas Huth /* cnttzd */ 1824fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1825fcf5ef2aSThomas Huth { 18269b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1827fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1828fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1829fcf5ef2aSThomas Huth } 1830fcf5ef2aSThomas Huth } 1831fcf5ef2aSThomas Huth 1832fcf5ef2aSThomas Huth /* darn */ 1833fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1834fcf5ef2aSThomas Huth { 1835fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1836fcf5ef2aSThomas Huth 1837fcf5ef2aSThomas Huth if (l == 0) { 1838fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1839fcf5ef2aSThomas Huth } else if (l <= 2) { 1840fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1841fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1842fcf5ef2aSThomas Huth } else { 1843fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1844fcf5ef2aSThomas Huth } 1845fcf5ef2aSThomas Huth } 1846fcf5ef2aSThomas Huth #endif 1847fcf5ef2aSThomas Huth 1848fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1849fcf5ef2aSThomas Huth 1850fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1851fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1852fcf5ef2aSThomas Huth { 1853fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1854fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1855fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1856fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1857fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1858fcf5ef2aSThomas Huth 1859fcf5ef2aSThomas Huth if (sh == (31-me) && mb <= me) { 1860fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1861fcf5ef2aSThomas Huth } else { 1862fcf5ef2aSThomas Huth target_ulong mask; 1863fcf5ef2aSThomas Huth TCGv t1; 1864fcf5ef2aSThomas Huth 1865fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1866fcf5ef2aSThomas Huth mb += 32; 1867fcf5ef2aSThomas Huth me += 32; 1868fcf5ef2aSThomas Huth #endif 1869fcf5ef2aSThomas Huth mask = MASK(mb, me); 1870fcf5ef2aSThomas Huth 1871fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1872fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1873fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1874fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1875fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1876fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1877fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1878fcf5ef2aSThomas Huth } else { 1879fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1880fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1881fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1882fcf5ef2aSThomas Huth #else 1883fcf5ef2aSThomas Huth g_assert_not_reached(); 1884fcf5ef2aSThomas Huth #endif 1885fcf5ef2aSThomas Huth } 1886fcf5ef2aSThomas Huth 1887fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1888fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1889fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1890fcf5ef2aSThomas Huth tcg_temp_free(t1); 1891fcf5ef2aSThomas Huth } 1892fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1893fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1894fcf5ef2aSThomas Huth } 1895fcf5ef2aSThomas Huth } 1896fcf5ef2aSThomas Huth 1897fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1898fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1899fcf5ef2aSThomas Huth { 1900fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1901fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 19027b4d326fSRichard Henderson int sh = SH(ctx->opcode); 19037b4d326fSRichard Henderson int mb = MB(ctx->opcode); 19047b4d326fSRichard Henderson int me = ME(ctx->opcode); 19057b4d326fSRichard Henderson int len = me - mb + 1; 19067b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1907fcf5ef2aSThomas Huth 19087b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 19097b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 19107b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 19117b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1912fcf5ef2aSThomas Huth } else { 1913fcf5ef2aSThomas Huth target_ulong mask; 1914fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1915fcf5ef2aSThomas Huth mb += 32; 1916fcf5ef2aSThomas Huth me += 32; 1917fcf5ef2aSThomas Huth #endif 1918fcf5ef2aSThomas Huth mask = MASK(mb, me); 19197b4d326fSRichard Henderson if (sh == 0) { 19207b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 19217b4d326fSRichard Henderson } else if (mask <= 0xffffffffu) { 1922fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1923fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1924fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1925fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1926fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1927fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1928fcf5ef2aSThomas Huth } else { 1929fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1930fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1931fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1932fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1933fcf5ef2aSThomas Huth #else 1934fcf5ef2aSThomas Huth g_assert_not_reached(); 1935fcf5ef2aSThomas Huth #endif 1936fcf5ef2aSThomas Huth } 1937fcf5ef2aSThomas Huth } 1938fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1939fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1940fcf5ef2aSThomas Huth } 1941fcf5ef2aSThomas Huth } 1942fcf5ef2aSThomas Huth 1943fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1944fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1945fcf5ef2aSThomas Huth { 1946fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1947fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1948fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1949fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1950fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1951fcf5ef2aSThomas Huth target_ulong mask; 1952fcf5ef2aSThomas Huth 1953fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1954fcf5ef2aSThomas Huth mb += 32; 1955fcf5ef2aSThomas Huth me += 32; 1956fcf5ef2aSThomas Huth #endif 1957fcf5ef2aSThomas Huth mask = MASK(mb, me); 1958fcf5ef2aSThomas Huth 1959fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1960fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1961fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1962fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1963fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1964fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1965fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1966fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1967fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1968fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1969fcf5ef2aSThomas Huth } else { 1970fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1971fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1972fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1973fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1974fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1975fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1976fcf5ef2aSThomas Huth #else 1977fcf5ef2aSThomas Huth g_assert_not_reached(); 1978fcf5ef2aSThomas Huth #endif 1979fcf5ef2aSThomas Huth } 1980fcf5ef2aSThomas Huth 1981fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 1982fcf5ef2aSThomas Huth 1983fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1984fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1985fcf5ef2aSThomas Huth } 1986fcf5ef2aSThomas Huth } 1987fcf5ef2aSThomas Huth 1988fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1989fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 1990fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 1991fcf5ef2aSThomas Huth { \ 1992fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 1993fcf5ef2aSThomas Huth } \ 1994fcf5ef2aSThomas Huth \ 1995fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 1996fcf5ef2aSThomas Huth { \ 1997fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 1998fcf5ef2aSThomas Huth } 1999fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2000fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2001fcf5ef2aSThomas Huth { \ 2002fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2003fcf5ef2aSThomas Huth } \ 2004fcf5ef2aSThomas Huth \ 2005fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2006fcf5ef2aSThomas Huth { \ 2007fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2008fcf5ef2aSThomas Huth } \ 2009fcf5ef2aSThomas Huth \ 2010fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2011fcf5ef2aSThomas Huth { \ 2012fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2013fcf5ef2aSThomas Huth } \ 2014fcf5ef2aSThomas Huth \ 2015fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2016fcf5ef2aSThomas Huth { \ 2017fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2018fcf5ef2aSThomas Huth } 2019fcf5ef2aSThomas Huth 2020fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2021fcf5ef2aSThomas Huth { 2022fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2023fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20247b4d326fSRichard Henderson int len = me - mb + 1; 20257b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2026fcf5ef2aSThomas Huth 20277b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20287b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20297b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20307b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2031fcf5ef2aSThomas Huth } else { 2032fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2033fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2034fcf5ef2aSThomas Huth } 2035fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2036fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2037fcf5ef2aSThomas Huth } 2038fcf5ef2aSThomas Huth } 2039fcf5ef2aSThomas Huth 2040fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2041fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2042fcf5ef2aSThomas Huth { 2043fcf5ef2aSThomas Huth uint32_t sh, mb; 2044fcf5ef2aSThomas Huth 2045fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2046fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2047fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2048fcf5ef2aSThomas Huth } 2049fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2050fcf5ef2aSThomas Huth 2051fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2052fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2053fcf5ef2aSThomas Huth { 2054fcf5ef2aSThomas Huth uint32_t sh, me; 2055fcf5ef2aSThomas Huth 2056fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2057fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2058fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2059fcf5ef2aSThomas Huth } 2060fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2061fcf5ef2aSThomas Huth 2062fcf5ef2aSThomas Huth /* rldic - rldic. */ 2063fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2064fcf5ef2aSThomas Huth { 2065fcf5ef2aSThomas Huth uint32_t sh, mb; 2066fcf5ef2aSThomas Huth 2067fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2068fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2069fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2070fcf5ef2aSThomas Huth } 2071fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2072fcf5ef2aSThomas Huth 2073fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2074fcf5ef2aSThomas Huth { 2075fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2076fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2077fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2078fcf5ef2aSThomas Huth TCGv t0; 2079fcf5ef2aSThomas Huth 2080fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2081fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2082fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2083fcf5ef2aSThomas Huth tcg_temp_free(t0); 2084fcf5ef2aSThomas Huth 2085fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2086fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2087fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2088fcf5ef2aSThomas Huth } 2089fcf5ef2aSThomas Huth } 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2092fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2093fcf5ef2aSThomas Huth { 2094fcf5ef2aSThomas Huth uint32_t mb; 2095fcf5ef2aSThomas Huth 2096fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2097fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2098fcf5ef2aSThomas Huth } 2099fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2100fcf5ef2aSThomas Huth 2101fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2102fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2103fcf5ef2aSThomas Huth { 2104fcf5ef2aSThomas Huth uint32_t me; 2105fcf5ef2aSThomas Huth 2106fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2107fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2108fcf5ef2aSThomas Huth } 2109fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2110fcf5ef2aSThomas Huth 2111fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2112fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2113fcf5ef2aSThomas Huth { 2114fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2115fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2116fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2117fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2118fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2119fcf5ef2aSThomas Huth 2120fcf5ef2aSThomas Huth if (mb <= me) { 2121fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2122fcf5ef2aSThomas Huth } else { 2123fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2124fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2125fcf5ef2aSThomas Huth 2126fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2127fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2128fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2129fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2130fcf5ef2aSThomas Huth tcg_temp_free(t1); 2131fcf5ef2aSThomas Huth } 2132fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2133fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2134fcf5ef2aSThomas Huth } 2135fcf5ef2aSThomas Huth } 2136fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2137fcf5ef2aSThomas Huth #endif 2138fcf5ef2aSThomas Huth 2139fcf5ef2aSThomas Huth /*** Integer shift ***/ 2140fcf5ef2aSThomas Huth 2141fcf5ef2aSThomas Huth /* slw & slw. */ 2142fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2143fcf5ef2aSThomas Huth { 2144fcf5ef2aSThomas Huth TCGv t0, t1; 2145fcf5ef2aSThomas Huth 2146fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2147fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2148fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2149fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2150fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2151fcf5ef2aSThomas Huth #else 2152fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2153fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2154fcf5ef2aSThomas Huth #endif 2155fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2156fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2157fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2158fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2159fcf5ef2aSThomas Huth tcg_temp_free(t1); 2160fcf5ef2aSThomas Huth tcg_temp_free(t0); 2161fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2162fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2163fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2164fcf5ef2aSThomas Huth } 2165fcf5ef2aSThomas Huth 2166fcf5ef2aSThomas Huth /* sraw & sraw. */ 2167fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2168fcf5ef2aSThomas Huth { 2169fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2170fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2171fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2172fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2173fcf5ef2aSThomas Huth } 2174fcf5ef2aSThomas Huth 2175fcf5ef2aSThomas Huth /* srawi & srawi. */ 2176fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2177fcf5ef2aSThomas Huth { 2178fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2179fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2180fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2181fcf5ef2aSThomas Huth if (sh == 0) { 2182fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2183fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2184af1c259fSSandipan Das if (is_isa300(ctx)) { 2185af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2186af1c259fSSandipan Das } 2187fcf5ef2aSThomas Huth } else { 2188fcf5ef2aSThomas Huth TCGv t0; 2189fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2190fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2191fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2192fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2193fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2194fcf5ef2aSThomas Huth tcg_temp_free(t0); 2195fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2196af1c259fSSandipan Das if (is_isa300(ctx)) { 2197af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2198af1c259fSSandipan Das } 2199fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2200fcf5ef2aSThomas Huth } 2201fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2202fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2203fcf5ef2aSThomas Huth } 2204fcf5ef2aSThomas Huth } 2205fcf5ef2aSThomas Huth 2206fcf5ef2aSThomas Huth /* srw & srw. */ 2207fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2208fcf5ef2aSThomas Huth { 2209fcf5ef2aSThomas Huth TCGv t0, t1; 2210fcf5ef2aSThomas Huth 2211fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2212fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2213fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2214fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2215fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2216fcf5ef2aSThomas Huth #else 2217fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2218fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2219fcf5ef2aSThomas Huth #endif 2220fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2221fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2222fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2223fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2224fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2225fcf5ef2aSThomas Huth tcg_temp_free(t1); 2226fcf5ef2aSThomas Huth tcg_temp_free(t0); 2227fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2228fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2229fcf5ef2aSThomas Huth } 2230fcf5ef2aSThomas Huth 2231fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2232fcf5ef2aSThomas Huth /* sld & sld. */ 2233fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2234fcf5ef2aSThomas Huth { 2235fcf5ef2aSThomas Huth TCGv t0, t1; 2236fcf5ef2aSThomas Huth 2237fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2238fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2239fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2240fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2241fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2242fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2243fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2244fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2245fcf5ef2aSThomas Huth tcg_temp_free(t1); 2246fcf5ef2aSThomas Huth tcg_temp_free(t0); 2247fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2248fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2249fcf5ef2aSThomas Huth } 2250fcf5ef2aSThomas Huth 2251fcf5ef2aSThomas Huth /* srad & srad. */ 2252fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2253fcf5ef2aSThomas Huth { 2254fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2255fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2256fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2257fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2258fcf5ef2aSThomas Huth } 2259fcf5ef2aSThomas Huth /* sradi & sradi. */ 2260fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2261fcf5ef2aSThomas Huth { 2262fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2263fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2264fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2265fcf5ef2aSThomas Huth if (sh == 0) { 2266fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2267fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2268af1c259fSSandipan Das if (is_isa300(ctx)) { 2269af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2270af1c259fSSandipan Das } 2271fcf5ef2aSThomas Huth } else { 2272fcf5ef2aSThomas Huth TCGv t0; 2273fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2274fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2275fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2276fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2277fcf5ef2aSThomas Huth tcg_temp_free(t0); 2278fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2279af1c259fSSandipan Das if (is_isa300(ctx)) { 2280af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2281af1c259fSSandipan Das } 2282fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2283fcf5ef2aSThomas Huth } 2284fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2285fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2286fcf5ef2aSThomas Huth } 2287fcf5ef2aSThomas Huth } 2288fcf5ef2aSThomas Huth 2289fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2290fcf5ef2aSThomas Huth { 2291fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2292fcf5ef2aSThomas Huth } 2293fcf5ef2aSThomas Huth 2294fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2295fcf5ef2aSThomas Huth { 2296fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2297fcf5ef2aSThomas Huth } 2298fcf5ef2aSThomas Huth 2299fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2300fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2301fcf5ef2aSThomas Huth { 2302fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2303fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2304fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2305fcf5ef2aSThomas Huth 2306fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2307fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2308fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2309fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2310fcf5ef2aSThomas Huth } 2311fcf5ef2aSThomas Huth } 2312fcf5ef2aSThomas Huth 2313fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2314fcf5ef2aSThomas Huth { 2315fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2316fcf5ef2aSThomas Huth } 2317fcf5ef2aSThomas Huth 2318fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2319fcf5ef2aSThomas Huth { 2320fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2321fcf5ef2aSThomas Huth } 2322fcf5ef2aSThomas Huth 2323fcf5ef2aSThomas Huth /* srd & srd. */ 2324fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2325fcf5ef2aSThomas Huth { 2326fcf5ef2aSThomas Huth TCGv t0, t1; 2327fcf5ef2aSThomas Huth 2328fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2329fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2330fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2331fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2332fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2333fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2334fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2335fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2336fcf5ef2aSThomas Huth tcg_temp_free(t1); 2337fcf5ef2aSThomas Huth tcg_temp_free(t0); 2338fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2339fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2340fcf5ef2aSThomas Huth } 2341fcf5ef2aSThomas Huth #endif 2342fcf5ef2aSThomas Huth 2343fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2344fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2345fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2346fcf5ef2aSThomas Huth target_long maskl) 2347fcf5ef2aSThomas Huth { 2348fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2349fcf5ef2aSThomas Huth 2350fcf5ef2aSThomas Huth simm &= ~maskl; 2351fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2352fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2353fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2354fcf5ef2aSThomas Huth } 2355fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2356fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2357fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2358fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2359fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2360fcf5ef2aSThomas Huth } 2361fcf5ef2aSThomas Huth } else { 2362fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2363fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2364fcf5ef2aSThomas Huth } else { 2365fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2366fcf5ef2aSThomas Huth } 2367fcf5ef2aSThomas Huth } 2368fcf5ef2aSThomas Huth } 2369fcf5ef2aSThomas Huth 2370fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2371fcf5ef2aSThomas Huth { 2372fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2373fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2374fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2375fcf5ef2aSThomas Huth } else { 2376fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2377fcf5ef2aSThomas Huth } 2378fcf5ef2aSThomas Huth } else { 2379fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2380fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2381fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2382fcf5ef2aSThomas Huth } 2383fcf5ef2aSThomas Huth } 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth 2386fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2387fcf5ef2aSThomas Huth { 2388fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2389fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2390fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2391fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2392fcf5ef2aSThomas Huth } else { 2393fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2394fcf5ef2aSThomas Huth } 2395fcf5ef2aSThomas Huth } 2396fcf5ef2aSThomas Huth 2397fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2398fcf5ef2aSThomas Huth target_long val) 2399fcf5ef2aSThomas Huth { 2400fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2401fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2402fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2403fcf5ef2aSThomas Huth } 2404fcf5ef2aSThomas Huth } 2405fcf5ef2aSThomas Huth 2406fcf5ef2aSThomas Huth static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) 2407fcf5ef2aSThomas Huth { 2408fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 2409fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 2410fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2411fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, EA, mask); 2412fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 2413fcf5ef2aSThomas Huth t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); 2414fcf5ef2aSThomas Huth t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); 2415fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip - 4); 2416fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t1, t2); 2417fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2418fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2419fcf5ef2aSThomas Huth gen_set_label(l1); 2420fcf5ef2aSThomas Huth tcg_temp_free(t0); 2421fcf5ef2aSThomas Huth } 2422fcf5ef2aSThomas Huth 2423fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2424fcf5ef2aSThomas Huth { 2425fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2426fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2427fcf5ef2aSThomas Huth } 2428fcf5ef2aSThomas Huth 2429fcf5ef2aSThomas Huth /*** Integer load ***/ 2430fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2431fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2432fcf5ef2aSThomas Huth 2433fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2434fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2435fcf5ef2aSThomas Huth TCGv val, \ 2436fcf5ef2aSThomas Huth TCGv addr) \ 2437fcf5ef2aSThomas Huth { \ 2438fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2439fcf5ef2aSThomas Huth } 2440fcf5ef2aSThomas Huth 2441fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2442fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2443fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2444fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2445fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2446fcf5ef2aSThomas Huth 2447fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2448fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2449fcf5ef2aSThomas Huth 2450fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2451fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2452fcf5ef2aSThomas Huth TCGv_i64 val, \ 2453fcf5ef2aSThomas Huth TCGv addr) \ 2454fcf5ef2aSThomas Huth { \ 2455fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2456fcf5ef2aSThomas Huth } 2457fcf5ef2aSThomas Huth 2458fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2459fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2460fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2461fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2462fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2463fcf5ef2aSThomas Huth 2464fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2465fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2466fcf5ef2aSThomas Huth #endif 2467fcf5ef2aSThomas Huth 2468fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2469fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2470fcf5ef2aSThomas Huth TCGv val, \ 2471fcf5ef2aSThomas Huth TCGv addr) \ 2472fcf5ef2aSThomas Huth { \ 2473fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2474fcf5ef2aSThomas Huth } 2475fcf5ef2aSThomas Huth 2476fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2477fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2478fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2479fcf5ef2aSThomas Huth 2480fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2481fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2482fcf5ef2aSThomas Huth 2483fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2484fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2485fcf5ef2aSThomas Huth TCGv_i64 val, \ 2486fcf5ef2aSThomas Huth TCGv addr) \ 2487fcf5ef2aSThomas Huth { \ 2488fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2489fcf5ef2aSThomas Huth } 2490fcf5ef2aSThomas Huth 2491fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2492fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2493fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2494fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2495fcf5ef2aSThomas Huth 2496fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2497fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2498fcf5ef2aSThomas Huth #endif 2499fcf5ef2aSThomas Huth 2500fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2501fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2502fcf5ef2aSThomas Huth { \ 2503fcf5ef2aSThomas Huth TCGv EA; \ 2504fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2505fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2506fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2507fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2508fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2509fcf5ef2aSThomas Huth } 2510fcf5ef2aSThomas Huth 2511fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2512fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2513fcf5ef2aSThomas Huth { \ 2514fcf5ef2aSThomas Huth TCGv EA; \ 2515fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2516fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2517fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2518fcf5ef2aSThomas Huth return; \ 2519fcf5ef2aSThomas Huth } \ 2520fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2521fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2522fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2523fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2524fcf5ef2aSThomas Huth else \ 2525fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2526fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2527fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2528fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2529fcf5ef2aSThomas Huth } 2530fcf5ef2aSThomas Huth 2531fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2532fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2533fcf5ef2aSThomas Huth { \ 2534fcf5ef2aSThomas Huth TCGv EA; \ 2535fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2536fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2537fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2538fcf5ef2aSThomas Huth return; \ 2539fcf5ef2aSThomas Huth } \ 2540fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2541fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2542fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2543fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2544fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2545fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2546fcf5ef2aSThomas Huth } 2547fcf5ef2aSThomas Huth 2548fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2549fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2550fcf5ef2aSThomas Huth { \ 2551fcf5ef2aSThomas Huth TCGv EA; \ 2552fcf5ef2aSThomas Huth chk; \ 2553fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2554fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2555fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2556fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2557fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2558fcf5ef2aSThomas Huth } 2559fcf5ef2aSThomas Huth 2560fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2561fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2562fcf5ef2aSThomas Huth 2563fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2564fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2565fcf5ef2aSThomas Huth 2566fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2567fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2568fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2569fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2570fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2571fcf5ef2aSThomas Huth 2572fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2573fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2574fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2575fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2576fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2577fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2578fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2579fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2580fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2581fcf5ef2aSThomas Huth /* lwaux */ 2582fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2583fcf5ef2aSThomas Huth /* lwax */ 2584fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2585fcf5ef2aSThomas Huth /* ldux */ 2586fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2587fcf5ef2aSThomas Huth /* ldx */ 2588fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2589fcf5ef2aSThomas Huth 2590fcf5ef2aSThomas Huth /* CI load/store variants */ 2591fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2592fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2593fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2594fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2595fcf5ef2aSThomas Huth 2596fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2597fcf5ef2aSThomas Huth { 2598fcf5ef2aSThomas Huth TCGv EA; 2599fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2600fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2601fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2602fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2603fcf5ef2aSThomas Huth return; 2604fcf5ef2aSThomas Huth } 2605fcf5ef2aSThomas Huth } 2606fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2607fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2608fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2609fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2610fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2611fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2612fcf5ef2aSThomas Huth } else { 2613fcf5ef2aSThomas Huth /* ld - ldu */ 2614fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2615fcf5ef2aSThomas Huth } 2616fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2617fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2618fcf5ef2aSThomas Huth tcg_temp_free(EA); 2619fcf5ef2aSThomas Huth } 2620fcf5ef2aSThomas Huth 2621fcf5ef2aSThomas Huth /* lq */ 2622fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2623fcf5ef2aSThomas Huth { 2624fcf5ef2aSThomas Huth int ra, rd; 2625fcf5ef2aSThomas Huth TCGv EA; 2626fcf5ef2aSThomas Huth 2627fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2628fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2629fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2630fcf5ef2aSThomas Huth 2631fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2632fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2633fcf5ef2aSThomas Huth return; 2634fcf5ef2aSThomas Huth } 2635fcf5ef2aSThomas Huth 2636fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2637fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2638fcf5ef2aSThomas Huth return; 2639fcf5ef2aSThomas Huth } 2640fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2641fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2642fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2643fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2644fcf5ef2aSThomas Huth return; 2645fcf5ef2aSThomas Huth } 2646fcf5ef2aSThomas Huth 2647fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2648fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2649fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2650fcf5ef2aSThomas Huth 2651fcf5ef2aSThomas Huth /* We only need to swap high and low halves. gen_qemu_ld64_i64 does 2652fcf5ef2aSThomas Huth necessary 64-bit byteswap already. */ 2653fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 2654fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2655fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2656fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2657fcf5ef2aSThomas Huth } else { 2658fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); 2659fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2660fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); 2661fcf5ef2aSThomas Huth } 2662fcf5ef2aSThomas Huth tcg_temp_free(EA); 2663fcf5ef2aSThomas Huth } 2664fcf5ef2aSThomas Huth #endif 2665fcf5ef2aSThomas Huth 2666fcf5ef2aSThomas Huth /*** Integer store ***/ 2667fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2668fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2669fcf5ef2aSThomas Huth { \ 2670fcf5ef2aSThomas Huth TCGv EA; \ 2671fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2672fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2673fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2674fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2675fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2676fcf5ef2aSThomas Huth } 2677fcf5ef2aSThomas Huth 2678fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2679fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2680fcf5ef2aSThomas Huth { \ 2681fcf5ef2aSThomas Huth TCGv EA; \ 2682fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2683fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2684fcf5ef2aSThomas Huth return; \ 2685fcf5ef2aSThomas Huth } \ 2686fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2687fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2688fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2689fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2690fcf5ef2aSThomas Huth else \ 2691fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2692fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2693fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2694fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2695fcf5ef2aSThomas Huth } 2696fcf5ef2aSThomas Huth 2697fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2698fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2699fcf5ef2aSThomas Huth { \ 2700fcf5ef2aSThomas Huth TCGv EA; \ 2701fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2702fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2703fcf5ef2aSThomas Huth return; \ 2704fcf5ef2aSThomas Huth } \ 2705fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2706fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2707fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2708fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2709fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2710fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2711fcf5ef2aSThomas Huth } 2712fcf5ef2aSThomas Huth 2713fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2714fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2715fcf5ef2aSThomas Huth { \ 2716fcf5ef2aSThomas Huth TCGv EA; \ 2717fcf5ef2aSThomas Huth chk; \ 2718fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2719fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2720fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2721fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2722fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2723fcf5ef2aSThomas Huth } 2724fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2725fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2726fcf5ef2aSThomas Huth 2727fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2728fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2729fcf5ef2aSThomas Huth 2730fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2731fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2732fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2733fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2734fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2735fcf5ef2aSThomas Huth 2736fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2737fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2738fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2739fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2740fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2741fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2742fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2743fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2744fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2745fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2746fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2747fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2748fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2751fcf5ef2aSThomas Huth { 2752fcf5ef2aSThomas Huth int rs; 2753fcf5ef2aSThomas Huth TCGv EA; 2754fcf5ef2aSThomas Huth 2755fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2756fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2757fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2758fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2759fcf5ef2aSThomas Huth 2760fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2761fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2762fcf5ef2aSThomas Huth } 2763fcf5ef2aSThomas Huth 2764fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2765fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2766fcf5ef2aSThomas Huth return; 2767fcf5ef2aSThomas Huth } 2768fcf5ef2aSThomas Huth 2769fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2770fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2771fcf5ef2aSThomas Huth return; 2772fcf5ef2aSThomas Huth } 2773fcf5ef2aSThomas Huth 2774fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2775fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2776fcf5ef2aSThomas Huth return; 2777fcf5ef2aSThomas Huth } 2778fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2779fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2780fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2781fcf5ef2aSThomas Huth 2782fcf5ef2aSThomas Huth /* We only need to swap high and low halves. gen_qemu_st64_i64 does 2783fcf5ef2aSThomas Huth necessary 64-bit byteswap already. */ 2784fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 2785fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2786fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2787fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2788fcf5ef2aSThomas Huth } else { 2789fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2790fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2791fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); 2792fcf5ef2aSThomas Huth } 2793fcf5ef2aSThomas Huth tcg_temp_free(EA); 2794fcf5ef2aSThomas Huth } else { 2795fcf5ef2aSThomas Huth /* std / stdu*/ 2796fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2797fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2798fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2799fcf5ef2aSThomas Huth return; 2800fcf5ef2aSThomas Huth } 2801fcf5ef2aSThomas Huth } 2802fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2803fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2804fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2805fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2806fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2807fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2808fcf5ef2aSThomas Huth tcg_temp_free(EA); 2809fcf5ef2aSThomas Huth } 2810fcf5ef2aSThomas Huth } 2811fcf5ef2aSThomas Huth #endif 2812fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2813fcf5ef2aSThomas Huth 2814fcf5ef2aSThomas Huth /* lhbrx */ 2815fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2816fcf5ef2aSThomas Huth 2817fcf5ef2aSThomas Huth /* lwbrx */ 2818fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2819fcf5ef2aSThomas Huth 2820fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2821fcf5ef2aSThomas Huth /* ldbrx */ 2822fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2823fcf5ef2aSThomas Huth /* stdbrx */ 2824fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2825fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2826fcf5ef2aSThomas Huth 2827fcf5ef2aSThomas Huth /* sthbrx */ 2828fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2829fcf5ef2aSThomas Huth /* stwbrx */ 2830fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2831fcf5ef2aSThomas Huth 2832fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2833fcf5ef2aSThomas Huth 2834fcf5ef2aSThomas Huth /* lmw */ 2835fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2836fcf5ef2aSThomas Huth { 2837fcf5ef2aSThomas Huth TCGv t0; 2838fcf5ef2aSThomas Huth TCGv_i32 t1; 2839fcf5ef2aSThomas Huth 2840fcf5ef2aSThomas Huth if (ctx->le_mode) { 2841fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2842fcf5ef2aSThomas Huth return; 2843fcf5ef2aSThomas Huth } 2844fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2845fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2846fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2847fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2848fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2849fcf5ef2aSThomas Huth tcg_temp_free(t0); 2850fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2851fcf5ef2aSThomas Huth } 2852fcf5ef2aSThomas Huth 2853fcf5ef2aSThomas Huth /* stmw */ 2854fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2855fcf5ef2aSThomas Huth { 2856fcf5ef2aSThomas Huth TCGv t0; 2857fcf5ef2aSThomas Huth TCGv_i32 t1; 2858fcf5ef2aSThomas Huth 2859fcf5ef2aSThomas Huth if (ctx->le_mode) { 2860fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2861fcf5ef2aSThomas Huth return; 2862fcf5ef2aSThomas Huth } 2863fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2864fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2865fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2866fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2867fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2868fcf5ef2aSThomas Huth tcg_temp_free(t0); 2869fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2870fcf5ef2aSThomas Huth } 2871fcf5ef2aSThomas Huth 2872fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2873fcf5ef2aSThomas Huth 2874fcf5ef2aSThomas Huth /* lswi */ 2875fcf5ef2aSThomas Huth /* PowerPC32 specification says we must generate an exception if 2876fcf5ef2aSThomas Huth * rA is in the range of registers to be loaded. 2877fcf5ef2aSThomas Huth * In an other hand, IBM says this is valid, but rA won't be loaded. 2878fcf5ef2aSThomas Huth * For now, I'll follow the spec... 2879fcf5ef2aSThomas Huth */ 2880fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2881fcf5ef2aSThomas Huth { 2882fcf5ef2aSThomas Huth TCGv t0; 2883fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2884fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2885fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2886fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2887fcf5ef2aSThomas Huth int nr; 2888fcf5ef2aSThomas Huth 2889fcf5ef2aSThomas Huth if (ctx->le_mode) { 2890fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2891fcf5ef2aSThomas Huth return; 2892fcf5ef2aSThomas Huth } 2893fcf5ef2aSThomas Huth if (nb == 0) 2894fcf5ef2aSThomas Huth nb = 32; 2895f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 2896fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2897fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2898fcf5ef2aSThomas Huth return; 2899fcf5ef2aSThomas Huth } 2900fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2901fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2902fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2903fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2904fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 2905fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 2906fcf5ef2aSThomas Huth tcg_temp_free(t0); 2907fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2908fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2909fcf5ef2aSThomas Huth } 2910fcf5ef2aSThomas Huth 2911fcf5ef2aSThomas Huth /* lswx */ 2912fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 2913fcf5ef2aSThomas Huth { 2914fcf5ef2aSThomas Huth TCGv t0; 2915fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 2916fcf5ef2aSThomas Huth 2917fcf5ef2aSThomas Huth if (ctx->le_mode) { 2918fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2919fcf5ef2aSThomas Huth return; 2920fcf5ef2aSThomas Huth } 2921fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2922fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2923fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2924fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2925fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 2926fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 2927fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2928fcf5ef2aSThomas Huth tcg_temp_free(t0); 2929fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2930fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2931fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2932fcf5ef2aSThomas Huth } 2933fcf5ef2aSThomas Huth 2934fcf5ef2aSThomas Huth /* stswi */ 2935fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 2936fcf5ef2aSThomas Huth { 2937fcf5ef2aSThomas Huth TCGv t0; 2938fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2939fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2940fcf5ef2aSThomas Huth 2941fcf5ef2aSThomas Huth if (ctx->le_mode) { 2942fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2943fcf5ef2aSThomas Huth return; 2944fcf5ef2aSThomas Huth } 2945fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2946fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2947fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2948fcf5ef2aSThomas Huth if (nb == 0) 2949fcf5ef2aSThomas Huth nb = 32; 2950fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2951fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2952fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2953fcf5ef2aSThomas Huth tcg_temp_free(t0); 2954fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2955fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2956fcf5ef2aSThomas Huth } 2957fcf5ef2aSThomas Huth 2958fcf5ef2aSThomas Huth /* stswx */ 2959fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 2960fcf5ef2aSThomas Huth { 2961fcf5ef2aSThomas Huth TCGv t0; 2962fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2963fcf5ef2aSThomas Huth 2964fcf5ef2aSThomas Huth if (ctx->le_mode) { 2965fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2966fcf5ef2aSThomas Huth return; 2967fcf5ef2aSThomas Huth } 2968fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2969fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2970fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2971fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 2972fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 2973fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 2974fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2975fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2976fcf5ef2aSThomas Huth tcg_temp_free(t0); 2977fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2978fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2979fcf5ef2aSThomas Huth } 2980fcf5ef2aSThomas Huth 2981fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 2982fcf5ef2aSThomas Huth /* eieio */ 2983fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 2984fcf5ef2aSThomas Huth { 29854771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC); 2986fcf5ef2aSThomas Huth } 2987fcf5ef2aSThomas Huth 2988fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 2989fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 2990fcf5ef2aSThomas Huth { 2991fcf5ef2aSThomas Huth TCGv_i32 t; 2992fcf5ef2aSThomas Huth TCGLabel *l; 2993fcf5ef2aSThomas Huth 2994fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 2995fcf5ef2aSThomas Huth return; 2996fcf5ef2aSThomas Huth } 2997fcf5ef2aSThomas Huth l = gen_new_label(); 2998fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 2999fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3000fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3001fcf5ef2aSThomas Huth if (global) { 3002fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3003fcf5ef2aSThomas Huth } else { 3004fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3005fcf5ef2aSThomas Huth } 3006fcf5ef2aSThomas Huth gen_set_label(l); 3007fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3008fcf5ef2aSThomas Huth } 3009fcf5ef2aSThomas Huth #else 3010fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3011fcf5ef2aSThomas Huth #endif 3012fcf5ef2aSThomas Huth 3013fcf5ef2aSThomas Huth /* isync */ 3014fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3015fcf5ef2aSThomas Huth { 3016fcf5ef2aSThomas Huth /* 3017fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3018fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3019fcf5ef2aSThomas Huth */ 3020fcf5ef2aSThomas Huth if (!ctx->pr) { 3021fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3022fcf5ef2aSThomas Huth } 30234771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3024fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3025fcf5ef2aSThomas Huth } 3026fcf5ef2aSThomas Huth 3027fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3028fcf5ef2aSThomas Huth 3029fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3030fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3031fcf5ef2aSThomas Huth { \ 3032fcf5ef2aSThomas Huth TCGv t0; \ 3033fcf5ef2aSThomas Huth TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ 3034fcf5ef2aSThomas Huth int len = MEMOP_GET_SIZE(memop); \ 3035fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); \ 3036fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); \ 3037fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); \ 3038fcf5ef2aSThomas Huth if ((len) > 1) { \ 3039fcf5ef2aSThomas Huth gen_check_align(ctx, t0, (len)-1); \ 3040fcf5ef2aSThomas Huth } \ 3041fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ 3042fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, t0); \ 3043253ce7b2SNikunj A Dadhania tcg_gen_mov_tl(cpu_reserve_val, gpr); \ 30444771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \ 3045fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 3046fcf5ef2aSThomas Huth } 3047fcf5ef2aSThomas Huth 3048fcf5ef2aSThomas Huth /* lwarx */ 3049fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3050fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3051fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3052fcf5ef2aSThomas Huth 3053a68a6146SBalamuruhan S #define LD_ATOMIC(name, memop, tp, op, eop) \ 3054a68a6146SBalamuruhan S static void gen_##name(DisasContext *ctx) \ 3055a68a6146SBalamuruhan S { \ 3056a68a6146SBalamuruhan S int len = MEMOP_GET_SIZE(memop); \ 3057a68a6146SBalamuruhan S uint32_t gpr_FC = FC(ctx->opcode); \ 3058a68a6146SBalamuruhan S TCGv EA = tcg_temp_local_new(); \ 3059a68a6146SBalamuruhan S TCGv_##tp t0, t1; \ 3060a68a6146SBalamuruhan S \ 3061a68a6146SBalamuruhan S gen_addr_register(ctx, EA); \ 3062a68a6146SBalamuruhan S if (len > 1) { \ 3063a68a6146SBalamuruhan S gen_check_align(ctx, EA, len - 1); \ 3064a68a6146SBalamuruhan S } \ 3065a68a6146SBalamuruhan S t0 = tcg_temp_new_##tp(); \ 3066a68a6146SBalamuruhan S t1 = tcg_temp_new_##tp(); \ 3067a68a6146SBalamuruhan S tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3068a68a6146SBalamuruhan S \ 3069a68a6146SBalamuruhan S switch (gpr_FC) { \ 3070a68a6146SBalamuruhan S case 0: /* Fetch and add */ \ 3071a68a6146SBalamuruhan S tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3072a68a6146SBalamuruhan S break; \ 3073a68a6146SBalamuruhan S case 1: /* Fetch and xor */ \ 3074a68a6146SBalamuruhan S tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3075a68a6146SBalamuruhan S break; \ 3076a68a6146SBalamuruhan S case 2: /* Fetch and or */ \ 3077a68a6146SBalamuruhan S tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3078a68a6146SBalamuruhan S break; \ 3079a68a6146SBalamuruhan S case 3: /* Fetch and 'and' */ \ 3080a68a6146SBalamuruhan S tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3081a68a6146SBalamuruhan S break; \ 3082a68a6146SBalamuruhan S case 8: /* Swap */ \ 3083a68a6146SBalamuruhan S tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3084a68a6146SBalamuruhan S break; \ 3085a68a6146SBalamuruhan S case 4: /* Fetch and max unsigned */ \ 3086a68a6146SBalamuruhan S case 5: /* Fetch and max signed */ \ 3087a68a6146SBalamuruhan S case 6: /* Fetch and min unsigned */ \ 3088a68a6146SBalamuruhan S case 7: /* Fetch and min signed */ \ 3089a68a6146SBalamuruhan S case 16: /* compare and swap not equal */ \ 3090a68a6146SBalamuruhan S case 24: /* Fetch and increment bounded */ \ 3091a68a6146SBalamuruhan S case 25: /* Fetch and increment equal */ \ 3092a68a6146SBalamuruhan S case 28: /* Fetch and decrement bounded */ \ 3093a68a6146SBalamuruhan S gen_invalid(ctx); \ 3094a68a6146SBalamuruhan S break; \ 3095a68a6146SBalamuruhan S default: \ 3096a68a6146SBalamuruhan S /* invoke data storage error handler */ \ 3097a68a6146SBalamuruhan S gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3098a68a6146SBalamuruhan S } \ 3099a68a6146SBalamuruhan S tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ 3100a68a6146SBalamuruhan S tcg_temp_free_##tp(t0); \ 3101a68a6146SBalamuruhan S tcg_temp_free_##tp(t1); \ 3102a68a6146SBalamuruhan S tcg_temp_free(EA); \ 3103a68a6146SBalamuruhan S } 3104a68a6146SBalamuruhan S 3105a68a6146SBalamuruhan S LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) 3106a68a6146SBalamuruhan S #if defined(TARGET_PPC64) 3107a68a6146SBalamuruhan S LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) 3108a68a6146SBalamuruhan S #endif 3109a68a6146SBalamuruhan S 3110a3401188SBalamuruhan S #define ST_ATOMIC(name, memop, tp, op) \ 3111a3401188SBalamuruhan S static void gen_##name(DisasContext *ctx) \ 3112a3401188SBalamuruhan S { \ 3113a3401188SBalamuruhan S int len = MEMOP_GET_SIZE(memop); \ 3114a3401188SBalamuruhan S uint32_t gpr_FC = FC(ctx->opcode); \ 3115a3401188SBalamuruhan S TCGv EA = tcg_temp_local_new(); \ 3116a3401188SBalamuruhan S TCGv_##tp t0, t1; \ 3117a3401188SBalamuruhan S \ 3118a3401188SBalamuruhan S gen_addr_register(ctx, EA); \ 3119a3401188SBalamuruhan S if (len > 1) { \ 3120a3401188SBalamuruhan S gen_check_align(ctx, EA, len - 1); \ 3121a3401188SBalamuruhan S } \ 3122a3401188SBalamuruhan S t0 = tcg_temp_new_##tp(); \ 3123a3401188SBalamuruhan S t1 = tcg_temp_new_##tp(); \ 3124a3401188SBalamuruhan S tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ 3125a3401188SBalamuruhan S \ 3126a3401188SBalamuruhan S switch (gpr_FC) { \ 3127a3401188SBalamuruhan S case 0: /* add and Store */ \ 3128a3401188SBalamuruhan S tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3129a3401188SBalamuruhan S break; \ 3130a3401188SBalamuruhan S case 1: /* xor and Store */ \ 3131a3401188SBalamuruhan S tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3132a3401188SBalamuruhan S break; \ 3133a3401188SBalamuruhan S case 2: /* Or and Store */ \ 3134a3401188SBalamuruhan S tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3135a3401188SBalamuruhan S break; \ 3136a3401188SBalamuruhan S case 3: /* 'and' and Store */ \ 3137a3401188SBalamuruhan S tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ 3138a3401188SBalamuruhan S break; \ 3139a3401188SBalamuruhan S case 4: /* Store max unsigned */ \ 3140a3401188SBalamuruhan S case 5: /* Store max signed */ \ 3141a3401188SBalamuruhan S case 6: /* Store min unsigned */ \ 3142a3401188SBalamuruhan S case 7: /* Store min signed */ \ 3143a3401188SBalamuruhan S case 24: /* Store twin */ \ 3144a3401188SBalamuruhan S gen_invalid(ctx); \ 3145a3401188SBalamuruhan S break; \ 3146a3401188SBalamuruhan S default: \ 3147a3401188SBalamuruhan S /* invoke data storage error handler */ \ 3148a3401188SBalamuruhan S gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ 3149a3401188SBalamuruhan S } \ 3150a3401188SBalamuruhan S tcg_temp_free_##tp(t0); \ 3151a3401188SBalamuruhan S tcg_temp_free_##tp(t1); \ 3152a3401188SBalamuruhan S tcg_temp_free(EA); \ 3153a3401188SBalamuruhan S } 3154a3401188SBalamuruhan S 3155a3401188SBalamuruhan S ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) 3156a3401188SBalamuruhan S #if defined(TARGET_PPC64) 3157a3401188SBalamuruhan S ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) 3158a3401188SBalamuruhan S #endif 3159a3401188SBalamuruhan S 3160fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3161fcf5ef2aSThomas Huth static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3162fcf5ef2aSThomas Huth int reg, int memop) 3163fcf5ef2aSThomas Huth { 3164fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3165fcf5ef2aSThomas Huth 3166fcf5ef2aSThomas Huth tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); 3167fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); 3168fcf5ef2aSThomas Huth tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); 3169fcf5ef2aSThomas Huth tcg_temp_free(t0); 3170fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); 3171fcf5ef2aSThomas Huth } 3172fcf5ef2aSThomas Huth #else 3173fcf5ef2aSThomas Huth static void gen_conditional_store(DisasContext *ctx, TCGv EA, 3174fcf5ef2aSThomas Huth int reg, int memop) 3175fcf5ef2aSThomas Huth { 3176253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3177253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3178253ce7b2SNikunj A Dadhania TCGv t0; 3179fcf5ef2aSThomas Huth 3180fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3181253ce7b2SNikunj A Dadhania 3182253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3183253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3184253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3185253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3186253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3187253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3188253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3189253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3190253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3191253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3192253ce7b2SNikunj A Dadhania 3193fcf5ef2aSThomas Huth gen_set_label(l1); 31944771df23SNikunj A Dadhania 31954771df23SNikunj A Dadhania /* Address mismatch implies failure. But we still need to provide the 31964771df23SNikunj A Dadhania memory barrier semantics of the instruction. */ 31974771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3198253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3199253ce7b2SNikunj A Dadhania 3200253ce7b2SNikunj A Dadhania gen_set_label(l2); 3201fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3202fcf5ef2aSThomas Huth } 3203fcf5ef2aSThomas Huth #endif 3204fcf5ef2aSThomas Huth 3205fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3206fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3207fcf5ef2aSThomas Huth { \ 3208fcf5ef2aSThomas Huth TCGv t0; \ 3209fcf5ef2aSThomas Huth int len = MEMOP_GET_SIZE(memop); \ 3210fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); \ 3211fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); \ 3212fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); \ 3213fcf5ef2aSThomas Huth if (len > 1) { \ 3214fcf5ef2aSThomas Huth gen_check_align(ctx, t0, (len) - 1); \ 3215fcf5ef2aSThomas Huth } \ 3216fcf5ef2aSThomas Huth gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ 3217fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 3218fcf5ef2aSThomas Huth } 3219fcf5ef2aSThomas Huth 3220fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3221fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3222fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3223fcf5ef2aSThomas Huth 3224fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3225fcf5ef2aSThomas Huth /* ldarx */ 3226fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3227fcf5ef2aSThomas Huth /* stdcx. */ 3228fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3229fcf5ef2aSThomas Huth 3230fcf5ef2aSThomas Huth /* lqarx */ 3231fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3232fcf5ef2aSThomas Huth { 3233fcf5ef2aSThomas Huth TCGv EA; 3234fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 3235fcf5ef2aSThomas Huth TCGv gpr1, gpr2; 3236fcf5ef2aSThomas Huth 3237fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3238fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3239fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3240fcf5ef2aSThomas Huth return; 3241fcf5ef2aSThomas Huth } 3242fcf5ef2aSThomas Huth 3243fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 3244fcf5ef2aSThomas Huth EA = tcg_temp_local_new(); 3245fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3246fcf5ef2aSThomas Huth gen_check_align(ctx, EA, 15); 3247fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 3248fcf5ef2aSThomas Huth gpr1 = cpu_gpr[rd+1]; 3249fcf5ef2aSThomas Huth gpr2 = cpu_gpr[rd]; 3250fcf5ef2aSThomas Huth } else { 3251fcf5ef2aSThomas Huth gpr1 = cpu_gpr[rd]; 3252fcf5ef2aSThomas Huth gpr2 = cpu_gpr[rd+1]; 3253fcf5ef2aSThomas Huth } 3254fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3255fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3256fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3257fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3258fcf5ef2aSThomas Huth 3259fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); 3260fcf5ef2aSThomas Huth tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3261fcf5ef2aSThomas Huth tcg_temp_free(EA); 3262fcf5ef2aSThomas Huth } 3263fcf5ef2aSThomas Huth 3264fcf5ef2aSThomas Huth /* stqcx. */ 3265fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3266fcf5ef2aSThomas Huth { 3267fcf5ef2aSThomas Huth TCGv EA; 3268fcf5ef2aSThomas Huth int reg = rS(ctx->opcode); 3269fcf5ef2aSThomas Huth int len = 16; 3270fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3271fcf5ef2aSThomas Huth TCGLabel *l1; 3272fcf5ef2aSThomas Huth TCGv gpr1, gpr2; 3273fcf5ef2aSThomas Huth #endif 3274fcf5ef2aSThomas Huth 3275fcf5ef2aSThomas Huth if (unlikely((rD(ctx->opcode) & 1))) { 3276fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3277fcf5ef2aSThomas Huth return; 3278fcf5ef2aSThomas Huth } 3279fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 3280fcf5ef2aSThomas Huth EA = tcg_temp_local_new(); 3281fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3282fcf5ef2aSThomas Huth if (len > 1) { 3283fcf5ef2aSThomas Huth gen_check_align(ctx, EA, (len) - 1); 3284fcf5ef2aSThomas Huth } 3285fcf5ef2aSThomas Huth 3286fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3287fcf5ef2aSThomas Huth gen_conditional_store(ctx, EA, reg, 16); 3288fcf5ef2aSThomas Huth #else 3289fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3290fcf5ef2aSThomas Huth l1 = gen_new_label(); 3291fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); 3292efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 3293fcf5ef2aSThomas Huth 3294fcf5ef2aSThomas Huth if (unlikely(ctx->le_mode)) { 3295fcf5ef2aSThomas Huth gpr1 = cpu_gpr[reg + 1]; 3296fcf5ef2aSThomas Huth gpr2 = cpu_gpr[reg]; 3297fcf5ef2aSThomas Huth } else { 3298fcf5ef2aSThomas Huth gpr1 = cpu_gpr[reg]; 3299fcf5ef2aSThomas Huth gpr2 = cpu_gpr[reg + 1]; 3300fcf5ef2aSThomas Huth } 3301fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3302fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 3303fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); 3304fcf5ef2aSThomas Huth 3305fcf5ef2aSThomas Huth gen_set_label(l1); 3306fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3307fcf5ef2aSThomas Huth #endif 3308fcf5ef2aSThomas Huth tcg_temp_free(EA); 3309fcf5ef2aSThomas Huth } 3310fcf5ef2aSThomas Huth 3311fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3312fcf5ef2aSThomas Huth 3313fcf5ef2aSThomas Huth /* sync */ 3314fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3315fcf5ef2aSThomas Huth { 3316fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3317fcf5ef2aSThomas Huth 3318fcf5ef2aSThomas Huth /* 3319fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3320fcf5ef2aSThomas Huth * 3321fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3322fcf5ef2aSThomas Huth * 3323fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3324fcf5ef2aSThomas Huth * check MSR_PR as well. 3325fcf5ef2aSThomas Huth */ 3326fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3327fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3328fcf5ef2aSThomas Huth } 33294771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3330fcf5ef2aSThomas Huth } 3331fcf5ef2aSThomas Huth 3332fcf5ef2aSThomas Huth /* wait */ 3333fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3334fcf5ef2aSThomas Huth { 3335fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3336fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3337fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3338fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3339fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3340fcf5ef2aSThomas Huth gen_exception_nip(ctx, EXCP_HLT, ctx->nip); 3341fcf5ef2aSThomas Huth } 3342fcf5ef2aSThomas Huth 3343fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3344fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3345fcf5ef2aSThomas Huth { 3346fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3347fcf5ef2aSThomas Huth GEN_PRIV; 3348fcf5ef2aSThomas Huth #else 3349fcf5ef2aSThomas Huth TCGv_i32 t; 3350fcf5ef2aSThomas Huth 3351fcf5ef2aSThomas Huth CHK_HV; 3352fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3353fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3354fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3355fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3356fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3357fcf5ef2aSThomas Huth } 3358fcf5ef2aSThomas Huth 3359fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3360fcf5ef2aSThomas Huth { 3361fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3362fcf5ef2aSThomas Huth GEN_PRIV; 3363fcf5ef2aSThomas Huth #else 3364fcf5ef2aSThomas Huth TCGv_i32 t; 3365fcf5ef2aSThomas Huth 3366fcf5ef2aSThomas Huth CHK_HV; 3367fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3368fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3369fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3370fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3371fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3372fcf5ef2aSThomas Huth } 3373fcf5ef2aSThomas Huth 3374cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3375cdee0e72SNikunj A Dadhania { 3376cdee0e72SNikunj A Dadhania gen_nap(ctx); 3377cdee0e72SNikunj A Dadhania } 3378cdee0e72SNikunj A Dadhania 3379fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3380fcf5ef2aSThomas Huth { 3381fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3382fcf5ef2aSThomas Huth GEN_PRIV; 3383fcf5ef2aSThomas Huth #else 3384fcf5ef2aSThomas Huth TCGv_i32 t; 3385fcf5ef2aSThomas Huth 3386fcf5ef2aSThomas Huth CHK_HV; 3387fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3388fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3389fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3390fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3391fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3392fcf5ef2aSThomas Huth } 3393fcf5ef2aSThomas Huth 3394fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3395fcf5ef2aSThomas Huth { 3396fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3397fcf5ef2aSThomas Huth GEN_PRIV; 3398fcf5ef2aSThomas Huth #else 3399fcf5ef2aSThomas Huth TCGv_i32 t; 3400fcf5ef2aSThomas Huth 3401fcf5ef2aSThomas Huth CHK_HV; 3402fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3403fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3404fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3405fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3406fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3407fcf5ef2aSThomas Huth } 3408fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3409fcf5ef2aSThomas Huth 3410fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3411fcf5ef2aSThomas Huth { 3412fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3413fcf5ef2aSThomas Huth if (ctx->has_cfar) 3414fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3415fcf5ef2aSThomas Huth #endif 3416fcf5ef2aSThomas Huth } 3417fcf5ef2aSThomas Huth 3418fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3419fcf5ef2aSThomas Huth { 3420fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3421fcf5ef2aSThomas Huth return false; 3422fcf5ef2aSThomas Huth } 3423fcf5ef2aSThomas Huth 3424fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3425fcf5ef2aSThomas Huth return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3426fcf5ef2aSThomas Huth #else 3427fcf5ef2aSThomas Huth return true; 3428fcf5ef2aSThomas Huth #endif 3429fcf5ef2aSThomas Huth } 3430fcf5ef2aSThomas Huth 3431fcf5ef2aSThomas Huth /*** Branch ***/ 3432fcf5ef2aSThomas Huth static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3433fcf5ef2aSThomas Huth { 3434fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3435fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3436fcf5ef2aSThomas Huth } 3437fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3438fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3439fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 3440fcf5ef2aSThomas Huth tcg_gen_exit_tb((uintptr_t)ctx->tb + n); 3441fcf5ef2aSThomas Huth } else { 3442fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 3443fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3444fcf5ef2aSThomas Huth if ((ctx->singlestep_enabled & 3445fcf5ef2aSThomas Huth (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && 3446fcf5ef2aSThomas Huth (ctx->exception == POWERPC_EXCP_BRANCH || 3447fcf5ef2aSThomas Huth ctx->exception == POWERPC_EXCP_TRACE)) { 3448fcf5ef2aSThomas Huth gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); 3449fcf5ef2aSThomas Huth } 3450fcf5ef2aSThomas Huth if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { 3451fcf5ef2aSThomas Huth gen_debug_exception(ctx); 3452fcf5ef2aSThomas Huth } 3453fcf5ef2aSThomas Huth } 3454fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3455fcf5ef2aSThomas Huth } 3456fcf5ef2aSThomas Huth } 3457fcf5ef2aSThomas Huth 3458fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3459fcf5ef2aSThomas Huth { 3460fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3461fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3462fcf5ef2aSThomas Huth } 3463fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3464fcf5ef2aSThomas Huth } 3465fcf5ef2aSThomas Huth 3466fcf5ef2aSThomas Huth /* b ba bl bla */ 3467fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3468fcf5ef2aSThomas Huth { 3469fcf5ef2aSThomas Huth target_ulong li, target; 3470fcf5ef2aSThomas Huth 3471fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3472fcf5ef2aSThomas Huth /* sign extend LI */ 3473fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3474fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3475fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3476fcf5ef2aSThomas Huth target = ctx->nip + li - 4; 3477fcf5ef2aSThomas Huth } else { 3478fcf5ef2aSThomas Huth target = li; 3479fcf5ef2aSThomas Huth } 3480fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3481fcf5ef2aSThomas Huth gen_setlr(ctx, ctx->nip); 3482fcf5ef2aSThomas Huth } 3483fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3484fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3485fcf5ef2aSThomas Huth } 3486fcf5ef2aSThomas Huth 3487fcf5ef2aSThomas Huth #define BCOND_IM 0 3488fcf5ef2aSThomas Huth #define BCOND_LR 1 3489fcf5ef2aSThomas Huth #define BCOND_CTR 2 3490fcf5ef2aSThomas Huth #define BCOND_TAR 3 3491fcf5ef2aSThomas Huth 3492fcf5ef2aSThomas Huth static inline void gen_bcond(DisasContext *ctx, int type) 3493fcf5ef2aSThomas Huth { 3494fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3495fcf5ef2aSThomas Huth TCGLabel *l1; 3496fcf5ef2aSThomas Huth TCGv target; 3497fcf5ef2aSThomas Huth 3498fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3499fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3500fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3501fcf5ef2aSThomas Huth if (type == BCOND_CTR) 3502fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3503fcf5ef2aSThomas Huth else if (type == BCOND_TAR) 3504fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3505fcf5ef2aSThomas Huth else 3506fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3507fcf5ef2aSThomas Huth } else { 3508fcf5ef2aSThomas Huth TCGV_UNUSED(target); 3509fcf5ef2aSThomas Huth } 3510fcf5ef2aSThomas Huth if (LK(ctx->opcode)) 3511fcf5ef2aSThomas Huth gen_setlr(ctx, ctx->nip); 3512fcf5ef2aSThomas Huth l1 = gen_new_label(); 3513fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3514fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3515fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3516fcf5ef2aSThomas Huth if (unlikely(type == BCOND_CTR)) { 3517fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3518fcf5ef2aSThomas Huth return; 3519fcf5ef2aSThomas Huth } 3520fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3521fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3522fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3523fcf5ef2aSThomas Huth } else { 3524fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3525fcf5ef2aSThomas Huth } 3526fcf5ef2aSThomas Huth if (bo & 0x2) { 3527fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3528fcf5ef2aSThomas Huth } else { 3529fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3530fcf5ef2aSThomas Huth } 3531fcf5ef2aSThomas Huth tcg_temp_free(temp); 3532fcf5ef2aSThomas Huth } 3533fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3534fcf5ef2aSThomas Huth /* Test CR */ 3535fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3536fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3537fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3538fcf5ef2aSThomas Huth 3539fcf5ef2aSThomas Huth if (bo & 0x8) { 3540fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3541fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3542fcf5ef2aSThomas Huth } else { 3543fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3544fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3545fcf5ef2aSThomas Huth } 3546fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3547fcf5ef2aSThomas Huth } 3548fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3549fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3550fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3551fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3552fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, ctx->nip + li - 4); 3553fcf5ef2aSThomas Huth } else { 3554fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3555fcf5ef2aSThomas Huth } 3556fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 3557fcf5ef2aSThomas Huth gen_set_label(l1); 3558fcf5ef2aSThomas Huth gen_goto_tb(ctx, 1, ctx->nip); 3559fcf5ef2aSThomas Huth } 3560fcf5ef2aSThomas Huth } else { 3561fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3562fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3563fcf5ef2aSThomas Huth } else { 3564fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3565fcf5ef2aSThomas Huth } 3566fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3567fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 3568fcf5ef2aSThomas Huth gen_set_label(l1); 3569fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 3570fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 3571fcf5ef2aSThomas Huth } 3572fcf5ef2aSThomas Huth } 3573fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3574fcf5ef2aSThomas Huth tcg_temp_free(target); 3575fcf5ef2aSThomas Huth } 3576fcf5ef2aSThomas Huth } 3577fcf5ef2aSThomas Huth 3578fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3579fcf5ef2aSThomas Huth { 3580fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3581fcf5ef2aSThomas Huth } 3582fcf5ef2aSThomas Huth 3583fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3584fcf5ef2aSThomas Huth { 3585fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3586fcf5ef2aSThomas Huth } 3587fcf5ef2aSThomas Huth 3588fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3589fcf5ef2aSThomas Huth { 3590fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3591fcf5ef2aSThomas Huth } 3592fcf5ef2aSThomas Huth 3593fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3594fcf5ef2aSThomas Huth { 3595fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3596fcf5ef2aSThomas Huth } 3597fcf5ef2aSThomas Huth 3598fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3599fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3600fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3601fcf5ef2aSThomas Huth { \ 3602fcf5ef2aSThomas Huth uint8_t bitmask; \ 3603fcf5ef2aSThomas Huth int sh; \ 3604fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3605fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3606fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3607fcf5ef2aSThomas Huth if (sh > 0) \ 3608fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3609fcf5ef2aSThomas Huth else if (sh < 0) \ 3610fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3611fcf5ef2aSThomas Huth else \ 3612fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3613fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3614fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3615fcf5ef2aSThomas Huth if (sh > 0) \ 3616fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3617fcf5ef2aSThomas Huth else if (sh < 0) \ 3618fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3619fcf5ef2aSThomas Huth else \ 3620fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3621fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3622fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3623fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3624fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3625fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3626fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3627fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3628fcf5ef2aSThomas Huth } 3629fcf5ef2aSThomas Huth 3630fcf5ef2aSThomas Huth /* crand */ 3631fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3632fcf5ef2aSThomas Huth /* crandc */ 3633fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3634fcf5ef2aSThomas Huth /* creqv */ 3635fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3636fcf5ef2aSThomas Huth /* crnand */ 3637fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3638fcf5ef2aSThomas Huth /* crnor */ 3639fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3640fcf5ef2aSThomas Huth /* cror */ 3641fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3642fcf5ef2aSThomas Huth /* crorc */ 3643fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3644fcf5ef2aSThomas Huth /* crxor */ 3645fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3646fcf5ef2aSThomas Huth 3647fcf5ef2aSThomas Huth /* mcrf */ 3648fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3649fcf5ef2aSThomas Huth { 3650fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3651fcf5ef2aSThomas Huth } 3652fcf5ef2aSThomas Huth 3653fcf5ef2aSThomas Huth /*** System linkage ***/ 3654fcf5ef2aSThomas Huth 3655fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3656fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3657fcf5ef2aSThomas Huth { 3658fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3659fcf5ef2aSThomas Huth GEN_PRIV; 3660fcf5ef2aSThomas Huth #else 3661fcf5ef2aSThomas Huth /* This instruction doesn't exist anymore on 64-bit server 3662fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3663fcf5ef2aSThomas Huth */ 3664fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_SEGMENT_64B) { 3665fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3666fcf5ef2aSThomas Huth return; 3667fcf5ef2aSThomas Huth } 3668fcf5ef2aSThomas Huth /* Restore CPU state */ 3669fcf5ef2aSThomas Huth CHK_SV; 3670fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3671fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3672fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3673fcf5ef2aSThomas Huth #endif 3674fcf5ef2aSThomas Huth } 3675fcf5ef2aSThomas Huth 3676fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3677fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 3678fcf5ef2aSThomas Huth { 3679fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3680fcf5ef2aSThomas Huth GEN_PRIV; 3681fcf5ef2aSThomas Huth #else 3682fcf5ef2aSThomas Huth /* Restore CPU state */ 3683fcf5ef2aSThomas Huth CHK_SV; 3684fcf5ef2aSThomas Huth gen_update_cfar(ctx, ctx->nip - 4); 3685fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 3686fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3687fcf5ef2aSThomas Huth #endif 3688fcf5ef2aSThomas Huth } 3689fcf5ef2aSThomas Huth 3690fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 3691fcf5ef2aSThomas Huth { 3692fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3693fcf5ef2aSThomas Huth GEN_PRIV; 3694fcf5ef2aSThomas Huth #else 3695fcf5ef2aSThomas Huth /* Restore CPU state */ 3696fcf5ef2aSThomas Huth CHK_HV; 3697fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 3698fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3699fcf5ef2aSThomas Huth #endif 3700fcf5ef2aSThomas Huth } 3701fcf5ef2aSThomas Huth #endif 3702fcf5ef2aSThomas Huth 3703fcf5ef2aSThomas Huth /* sc */ 3704fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3705fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3706fcf5ef2aSThomas Huth #else 3707fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3708fcf5ef2aSThomas Huth #endif 3709fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 3710fcf5ef2aSThomas Huth { 3711fcf5ef2aSThomas Huth uint32_t lev; 3712fcf5ef2aSThomas Huth 3713fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 3714fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3715fcf5ef2aSThomas Huth } 3716fcf5ef2aSThomas Huth 3717fcf5ef2aSThomas Huth /*** Trap ***/ 3718fcf5ef2aSThomas Huth 3719fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 3720fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 3721fcf5ef2aSThomas Huth { 3722fcf5ef2aSThomas Huth /* Trap never */ 3723fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 3724fcf5ef2aSThomas Huth return true; 3725fcf5ef2aSThomas Huth } 3726fcf5ef2aSThomas Huth /* Trap always */ 3727fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 3728fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3729fcf5ef2aSThomas Huth return true; 3730fcf5ef2aSThomas Huth } 3731fcf5ef2aSThomas Huth return false; 3732fcf5ef2aSThomas Huth } 3733fcf5ef2aSThomas Huth 3734fcf5ef2aSThomas Huth /* tw */ 3735fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 3736fcf5ef2aSThomas Huth { 3737fcf5ef2aSThomas Huth TCGv_i32 t0; 3738fcf5ef2aSThomas Huth 3739fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3740fcf5ef2aSThomas Huth return; 3741fcf5ef2aSThomas Huth } 3742fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3743fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3744fcf5ef2aSThomas Huth t0); 3745fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3746fcf5ef2aSThomas Huth } 3747fcf5ef2aSThomas Huth 3748fcf5ef2aSThomas Huth /* twi */ 3749fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 3750fcf5ef2aSThomas Huth { 3751fcf5ef2aSThomas Huth TCGv t0; 3752fcf5ef2aSThomas Huth TCGv_i32 t1; 3753fcf5ef2aSThomas Huth 3754fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3755fcf5ef2aSThomas Huth return; 3756fcf5ef2aSThomas Huth } 3757fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3758fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3759fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3760fcf5ef2aSThomas Huth tcg_temp_free(t0); 3761fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3762fcf5ef2aSThomas Huth } 3763fcf5ef2aSThomas Huth 3764fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3765fcf5ef2aSThomas Huth /* td */ 3766fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 3767fcf5ef2aSThomas Huth { 3768fcf5ef2aSThomas Huth TCGv_i32 t0; 3769fcf5ef2aSThomas Huth 3770fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3771fcf5ef2aSThomas Huth return; 3772fcf5ef2aSThomas Huth } 3773fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3774fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3775fcf5ef2aSThomas Huth t0); 3776fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3777fcf5ef2aSThomas Huth } 3778fcf5ef2aSThomas Huth 3779fcf5ef2aSThomas Huth /* tdi */ 3780fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 3781fcf5ef2aSThomas Huth { 3782fcf5ef2aSThomas Huth TCGv t0; 3783fcf5ef2aSThomas Huth TCGv_i32 t1; 3784fcf5ef2aSThomas Huth 3785fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3786fcf5ef2aSThomas Huth return; 3787fcf5ef2aSThomas Huth } 3788fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3789fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3790fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3791fcf5ef2aSThomas Huth tcg_temp_free(t0); 3792fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3793fcf5ef2aSThomas Huth } 3794fcf5ef2aSThomas Huth #endif 3795fcf5ef2aSThomas Huth 3796fcf5ef2aSThomas Huth /*** Processor control ***/ 3797fcf5ef2aSThomas Huth 3798dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 3799fcf5ef2aSThomas Huth { 3800fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 3801fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 3802fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 3803fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 3804fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 3805fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 3806fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 3807fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 3808fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 3809fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 3810dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 3811dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 3812dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 3813dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 3814dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 3815dd09c361SNikunj A Dadhania } 3816fcf5ef2aSThomas Huth tcg_temp_free(t0); 3817fcf5ef2aSThomas Huth tcg_temp_free(t1); 3818fcf5ef2aSThomas Huth tcg_temp_free(t2); 3819fcf5ef2aSThomas Huth } 3820fcf5ef2aSThomas Huth 3821fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 3822fcf5ef2aSThomas Huth { 3823dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 3824fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 3825dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 3826dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 3827dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 3828dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 3829dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 38301bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 38311bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 38321bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 3833fcf5ef2aSThomas Huth } 3834fcf5ef2aSThomas Huth 3835fcf5ef2aSThomas Huth /* mcrxr */ 3836fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 3837fcf5ef2aSThomas Huth { 3838fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3839fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 3840fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3841fcf5ef2aSThomas Huth 3842fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 3843fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 3844fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 3845fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 3846fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 3847fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 3848fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 3849fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 3850fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3851fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3852fcf5ef2aSThomas Huth 3853fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 3854fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 3855fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 3856fcf5ef2aSThomas Huth } 3857fcf5ef2aSThomas Huth 3858b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 3859b63d0434SNikunj A Dadhania /* mcrxrx */ 3860b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 3861b63d0434SNikunj A Dadhania { 3862b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 3863b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 3864b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 3865b63d0434SNikunj A Dadhania 3866b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 3867b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 3868b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 3869b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 3870b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 3871b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 3872b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 3873b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 3874b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 3875b63d0434SNikunj A Dadhania tcg_temp_free(t0); 3876b63d0434SNikunj A Dadhania tcg_temp_free(t1); 3877b63d0434SNikunj A Dadhania } 3878b63d0434SNikunj A Dadhania #endif 3879b63d0434SNikunj A Dadhania 3880fcf5ef2aSThomas Huth /* mfcr mfocrf */ 3881fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 3882fcf5ef2aSThomas Huth { 3883fcf5ef2aSThomas Huth uint32_t crm, crn; 3884fcf5ef2aSThomas Huth 3885fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 3886fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 3887fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 3888fcf5ef2aSThomas Huth crn = ctz32 (crm); 3889fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 3890fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 3891fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 3892fcf5ef2aSThomas Huth } 3893fcf5ef2aSThomas Huth } else { 3894fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 3895fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 3896fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3897fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 3898fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3899fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 3900fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3901fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 3902fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3903fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 3904fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3905fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 3906fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3907fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 3908fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 3909fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 3910fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 3911fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3912fcf5ef2aSThomas Huth } 3913fcf5ef2aSThomas Huth } 3914fcf5ef2aSThomas Huth 3915fcf5ef2aSThomas Huth /* mfmsr */ 3916fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 3917fcf5ef2aSThomas Huth { 3918fcf5ef2aSThomas Huth CHK_SV; 3919fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 3920fcf5ef2aSThomas Huth } 3921fcf5ef2aSThomas Huth 3922fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 3923fcf5ef2aSThomas Huth { 3924fcf5ef2aSThomas Huth #if 0 3925fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 3926fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 3927fcf5ef2aSThomas Huth #endif 3928fcf5ef2aSThomas Huth } 3929fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 3930fcf5ef2aSThomas Huth 3931fcf5ef2aSThomas Huth /* mfspr */ 3932fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 3933fcf5ef2aSThomas Huth { 3934fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 3935fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 3936fcf5ef2aSThomas Huth 3937fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3938fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 3939fcf5ef2aSThomas Huth #else 3940fcf5ef2aSThomas Huth if (ctx->pr) { 3941fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 3942fcf5ef2aSThomas Huth } else if (ctx->hv) { 3943fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 3944fcf5ef2aSThomas Huth } else { 3945fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 3946fcf5ef2aSThomas Huth } 3947fcf5ef2aSThomas Huth #endif 3948fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 3949fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 3950fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 3951fcf5ef2aSThomas Huth } else { 3952fcf5ef2aSThomas Huth /* Privilege exception */ 3953fcf5ef2aSThomas Huth /* This is a hack to avoid warnings when running Linux: 3954fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 3955fcf5ef2aSThomas Huth * allowing userland application to read the PVR 3956fcf5ef2aSThomas Huth */ 3957fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 3958fcf5ef2aSThomas Huth fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at " 3959fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3960fcf5ef2aSThomas Huth if (qemu_log_separate()) { 3961fcf5ef2aSThomas Huth qemu_log("Trying to read privileged spr %d (0x%03x) at " 3962fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3963fcf5ef2aSThomas Huth } 3964fcf5ef2aSThomas Huth } 3965fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 3966fcf5ef2aSThomas Huth } 3967fcf5ef2aSThomas Huth } else { 3968fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 3969fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 3970fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 3971fcf5ef2aSThomas Huth /* This is a nop */ 3972fcf5ef2aSThomas Huth return; 3973fcf5ef2aSThomas Huth } 3974fcf5ef2aSThomas Huth /* Not defined */ 3975fcf5ef2aSThomas Huth fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " 3976fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3977fcf5ef2aSThomas Huth if (qemu_log_separate()) { 3978fcf5ef2aSThomas Huth qemu_log("Trying to read invalid spr %d (0x%03x) at " 3979fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 3980fcf5ef2aSThomas Huth } 3981fcf5ef2aSThomas Huth 3982fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 3983fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 3984fcf5ef2aSThomas Huth */ 3985fcf5ef2aSThomas Huth if (sprn & 0x10) { 3986fcf5ef2aSThomas Huth if (ctx->pr) { 3987fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3988fcf5ef2aSThomas Huth } 3989fcf5ef2aSThomas Huth } else { 3990fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 3991fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 3992fcf5ef2aSThomas Huth } 3993fcf5ef2aSThomas Huth } 3994fcf5ef2aSThomas Huth } 3995fcf5ef2aSThomas Huth } 3996fcf5ef2aSThomas Huth 3997fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 3998fcf5ef2aSThomas Huth { 3999fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4000fcf5ef2aSThomas Huth } 4001fcf5ef2aSThomas Huth 4002fcf5ef2aSThomas Huth /* mftb */ 4003fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4004fcf5ef2aSThomas Huth { 4005fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4006fcf5ef2aSThomas Huth } 4007fcf5ef2aSThomas Huth 4008fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4009fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4010fcf5ef2aSThomas Huth { 4011fcf5ef2aSThomas Huth uint32_t crm, crn; 4012fcf5ef2aSThomas Huth 4013fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4014fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4015fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4016fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4017fcf5ef2aSThomas Huth crn = ctz32 (crm); 4018fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4019fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4020fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4021fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4022fcf5ef2aSThomas Huth } 4023fcf5ef2aSThomas Huth } else { 4024fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4025fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4026fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4027fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4028fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4029fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4030fcf5ef2aSThomas Huth } 4031fcf5ef2aSThomas Huth } 4032fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4033fcf5ef2aSThomas Huth } 4034fcf5ef2aSThomas Huth } 4035fcf5ef2aSThomas Huth 4036fcf5ef2aSThomas Huth /* mtmsr */ 4037fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4038fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4039fcf5ef2aSThomas Huth { 4040fcf5ef2aSThomas Huth CHK_SV; 4041fcf5ef2aSThomas Huth 4042fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4043fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4044fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4045fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4046fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4047fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4048fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4049fcf5ef2aSThomas Huth tcg_temp_free(t0); 4050fcf5ef2aSThomas Huth } else { 4051fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4052fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4053fcf5ef2aSThomas Huth * directly from ppc_store_msr 4054fcf5ef2aSThomas Huth */ 4055fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 4056fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4057fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4058fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4059fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4060fcf5ef2aSThomas Huth } 4061fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4062fcf5ef2aSThomas Huth } 4063fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4064fcf5ef2aSThomas Huth 4065fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4066fcf5ef2aSThomas Huth { 4067fcf5ef2aSThomas Huth CHK_SV; 4068fcf5ef2aSThomas Huth 4069fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4070fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4071fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4072fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4073fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4074fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4075fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4076fcf5ef2aSThomas Huth tcg_temp_free(t0); 4077fcf5ef2aSThomas Huth } else { 4078fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4079fcf5ef2aSThomas Huth 4080fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4081fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4082fcf5ef2aSThomas Huth * directly from ppc_store_msr 4083fcf5ef2aSThomas Huth */ 4084fcf5ef2aSThomas Huth gen_update_nip(ctx, ctx->nip); 4085fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4086fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4087fcf5ef2aSThomas Huth #else 4088fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4089fcf5ef2aSThomas Huth #endif 4090fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4091fcf5ef2aSThomas Huth tcg_temp_free(msr); 4092fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4093fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4094fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4095fcf5ef2aSThomas Huth } 4096fcf5ef2aSThomas Huth #endif 4097fcf5ef2aSThomas Huth } 4098fcf5ef2aSThomas Huth 4099fcf5ef2aSThomas Huth /* mtspr */ 4100fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4101fcf5ef2aSThomas Huth { 4102fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4103fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4104fcf5ef2aSThomas Huth 4105fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4106fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4107fcf5ef2aSThomas Huth #else 4108fcf5ef2aSThomas Huth if (ctx->pr) { 4109fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4110fcf5ef2aSThomas Huth } else if (ctx->hv) { 4111fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4112fcf5ef2aSThomas Huth } else { 4113fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4114fcf5ef2aSThomas Huth } 4115fcf5ef2aSThomas Huth #endif 4116fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4117fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4118fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4119fcf5ef2aSThomas Huth } else { 4120fcf5ef2aSThomas Huth /* Privilege exception */ 4121fcf5ef2aSThomas Huth fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at " 4122fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4123fcf5ef2aSThomas Huth if (qemu_log_separate()) { 4124fcf5ef2aSThomas Huth qemu_log("Trying to write privileged spr %d (0x%03x) at " 4125fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4126fcf5ef2aSThomas Huth } 4127fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4128fcf5ef2aSThomas Huth } 4129fcf5ef2aSThomas Huth } else { 4130fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4131fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4132fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4133fcf5ef2aSThomas Huth /* This is a nop */ 4134fcf5ef2aSThomas Huth return; 4135fcf5ef2aSThomas Huth } 4136fcf5ef2aSThomas Huth 4137fcf5ef2aSThomas Huth /* Not defined */ 4138fcf5ef2aSThomas Huth if (qemu_log_separate()) { 4139fcf5ef2aSThomas Huth qemu_log("Trying to write invalid spr %d (0x%03x) at " 4140fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4141fcf5ef2aSThomas Huth } 4142fcf5ef2aSThomas Huth fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " 4143fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); 4144fcf5ef2aSThomas Huth 4145fcf5ef2aSThomas Huth 4146fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4147fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4148fcf5ef2aSThomas Huth */ 4149fcf5ef2aSThomas Huth if (sprn & 0x10) { 4150fcf5ef2aSThomas Huth if (ctx->pr) { 4151fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4152fcf5ef2aSThomas Huth } 4153fcf5ef2aSThomas Huth } else { 4154fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4155fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4156fcf5ef2aSThomas Huth } 4157fcf5ef2aSThomas Huth } 4158fcf5ef2aSThomas Huth } 4159fcf5ef2aSThomas Huth } 4160fcf5ef2aSThomas Huth 4161fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4162fcf5ef2aSThomas Huth /* setb */ 4163fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4164fcf5ef2aSThomas Huth { 4165fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4166fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4167fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4168fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4169fcf5ef2aSThomas Huth 4170fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4171fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4172fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4173fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4174fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4175fcf5ef2aSThomas Huth 4176fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4177fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4178fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4179fcf5ef2aSThomas Huth } 4180fcf5ef2aSThomas Huth #endif 4181fcf5ef2aSThomas Huth 4182fcf5ef2aSThomas Huth /*** Cache management ***/ 4183fcf5ef2aSThomas Huth 4184fcf5ef2aSThomas Huth /* dcbf */ 4185fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4186fcf5ef2aSThomas Huth { 4187fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4188fcf5ef2aSThomas Huth TCGv t0; 4189fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4190fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4191fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4192fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4193fcf5ef2aSThomas Huth tcg_temp_free(t0); 4194fcf5ef2aSThomas Huth } 4195fcf5ef2aSThomas Huth 4196fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4197fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4198fcf5ef2aSThomas Huth { 4199fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4200fcf5ef2aSThomas Huth GEN_PRIV; 4201fcf5ef2aSThomas Huth #else 4202fcf5ef2aSThomas Huth TCGv EA, val; 4203fcf5ef2aSThomas Huth 4204fcf5ef2aSThomas Huth CHK_SV; 4205fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4206fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4207fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4208fcf5ef2aSThomas Huth val = tcg_temp_new(); 4209fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4210fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4211fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4212fcf5ef2aSThomas Huth tcg_temp_free(val); 4213fcf5ef2aSThomas Huth tcg_temp_free(EA); 4214fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4215fcf5ef2aSThomas Huth } 4216fcf5ef2aSThomas Huth 4217fcf5ef2aSThomas Huth /* dcdst */ 4218fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4219fcf5ef2aSThomas Huth { 4220fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4221fcf5ef2aSThomas Huth TCGv t0; 4222fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4223fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4224fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4225fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4226fcf5ef2aSThomas Huth tcg_temp_free(t0); 4227fcf5ef2aSThomas Huth } 4228fcf5ef2aSThomas Huth 4229fcf5ef2aSThomas Huth /* dcbt */ 4230fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4231fcf5ef2aSThomas Huth { 4232fcf5ef2aSThomas Huth /* interpreted as no-op */ 4233fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4234fcf5ef2aSThomas Huth * but does not generate any exception 4235fcf5ef2aSThomas Huth */ 4236fcf5ef2aSThomas Huth } 4237fcf5ef2aSThomas Huth 4238fcf5ef2aSThomas Huth /* dcbtst */ 4239fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4240fcf5ef2aSThomas Huth { 4241fcf5ef2aSThomas Huth /* interpreted as no-op */ 4242fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4243fcf5ef2aSThomas Huth * but does not generate any exception 4244fcf5ef2aSThomas Huth */ 4245fcf5ef2aSThomas Huth } 4246fcf5ef2aSThomas Huth 4247fcf5ef2aSThomas Huth /* dcbtls */ 4248fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4249fcf5ef2aSThomas Huth { 4250fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4251fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4252fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4253fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4254fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4255fcf5ef2aSThomas Huth tcg_temp_free(t0); 4256fcf5ef2aSThomas Huth } 4257fcf5ef2aSThomas Huth 4258fcf5ef2aSThomas Huth /* dcbz */ 4259fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4260fcf5ef2aSThomas Huth { 4261fcf5ef2aSThomas Huth TCGv tcgv_addr; 4262fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4263fcf5ef2aSThomas Huth 4264fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4265fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4266fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4267fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4268fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4269fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4270fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4271fcf5ef2aSThomas Huth } 4272fcf5ef2aSThomas Huth 4273fcf5ef2aSThomas Huth /* dst / dstt */ 4274fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4275fcf5ef2aSThomas Huth { 4276fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4277fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4278fcf5ef2aSThomas Huth } else { 4279fcf5ef2aSThomas Huth /* interpreted as no-op */ 4280fcf5ef2aSThomas Huth } 4281fcf5ef2aSThomas Huth } 4282fcf5ef2aSThomas Huth 4283fcf5ef2aSThomas Huth /* dstst /dststt */ 4284fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4285fcf5ef2aSThomas Huth { 4286fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4287fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4288fcf5ef2aSThomas Huth } else { 4289fcf5ef2aSThomas Huth /* interpreted as no-op */ 4290fcf5ef2aSThomas Huth } 4291fcf5ef2aSThomas Huth 4292fcf5ef2aSThomas Huth } 4293fcf5ef2aSThomas Huth 4294fcf5ef2aSThomas Huth /* dss / dssall */ 4295fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4296fcf5ef2aSThomas Huth { 4297fcf5ef2aSThomas Huth /* interpreted as no-op */ 4298fcf5ef2aSThomas Huth } 4299fcf5ef2aSThomas Huth 4300fcf5ef2aSThomas Huth /* icbi */ 4301fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4302fcf5ef2aSThomas Huth { 4303fcf5ef2aSThomas Huth TCGv t0; 4304fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4305fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4306fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4307fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4308fcf5ef2aSThomas Huth tcg_temp_free(t0); 4309fcf5ef2aSThomas Huth } 4310fcf5ef2aSThomas Huth 4311fcf5ef2aSThomas Huth /* Optional: */ 4312fcf5ef2aSThomas Huth /* dcba */ 4313fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4314fcf5ef2aSThomas Huth { 4315fcf5ef2aSThomas Huth /* interpreted as no-op */ 4316fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a store by the MMU 4317fcf5ef2aSThomas Huth * but does not generate any exception 4318fcf5ef2aSThomas Huth */ 4319fcf5ef2aSThomas Huth } 4320fcf5ef2aSThomas Huth 4321fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4322fcf5ef2aSThomas Huth /* Supervisor only: */ 4323fcf5ef2aSThomas Huth 4324fcf5ef2aSThomas Huth /* mfsr */ 4325fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4326fcf5ef2aSThomas Huth { 4327fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4328fcf5ef2aSThomas Huth GEN_PRIV; 4329fcf5ef2aSThomas Huth #else 4330fcf5ef2aSThomas Huth TCGv t0; 4331fcf5ef2aSThomas Huth 4332fcf5ef2aSThomas Huth CHK_SV; 4333fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4334fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4335fcf5ef2aSThomas Huth tcg_temp_free(t0); 4336fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4337fcf5ef2aSThomas Huth } 4338fcf5ef2aSThomas Huth 4339fcf5ef2aSThomas Huth /* mfsrin */ 4340fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4341fcf5ef2aSThomas Huth { 4342fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4343fcf5ef2aSThomas Huth GEN_PRIV; 4344fcf5ef2aSThomas Huth #else 4345fcf5ef2aSThomas Huth TCGv t0; 4346fcf5ef2aSThomas Huth 4347fcf5ef2aSThomas Huth CHK_SV; 4348fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4349e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4350fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4351fcf5ef2aSThomas Huth tcg_temp_free(t0); 4352fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4353fcf5ef2aSThomas Huth } 4354fcf5ef2aSThomas Huth 4355fcf5ef2aSThomas Huth /* mtsr */ 4356fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4357fcf5ef2aSThomas Huth { 4358fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4359fcf5ef2aSThomas Huth GEN_PRIV; 4360fcf5ef2aSThomas Huth #else 4361fcf5ef2aSThomas Huth TCGv t0; 4362fcf5ef2aSThomas Huth 4363fcf5ef2aSThomas Huth CHK_SV; 4364fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4365fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4366fcf5ef2aSThomas Huth tcg_temp_free(t0); 4367fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4368fcf5ef2aSThomas Huth } 4369fcf5ef2aSThomas Huth 4370fcf5ef2aSThomas Huth /* mtsrin */ 4371fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4372fcf5ef2aSThomas Huth { 4373fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4374fcf5ef2aSThomas Huth GEN_PRIV; 4375fcf5ef2aSThomas Huth #else 4376fcf5ef2aSThomas Huth TCGv t0; 4377fcf5ef2aSThomas Huth CHK_SV; 4378fcf5ef2aSThomas Huth 4379fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4380e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4381fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4382fcf5ef2aSThomas Huth tcg_temp_free(t0); 4383fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4384fcf5ef2aSThomas Huth } 4385fcf5ef2aSThomas Huth 4386fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4387fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4388fcf5ef2aSThomas Huth 4389fcf5ef2aSThomas Huth /* mfsr */ 4390fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4391fcf5ef2aSThomas Huth { 4392fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4393fcf5ef2aSThomas Huth GEN_PRIV; 4394fcf5ef2aSThomas Huth #else 4395fcf5ef2aSThomas Huth TCGv t0; 4396fcf5ef2aSThomas Huth 4397fcf5ef2aSThomas Huth CHK_SV; 4398fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4399fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4400fcf5ef2aSThomas Huth tcg_temp_free(t0); 4401fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4402fcf5ef2aSThomas Huth } 4403fcf5ef2aSThomas Huth 4404fcf5ef2aSThomas Huth /* mfsrin */ 4405fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4406fcf5ef2aSThomas Huth { 4407fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4408fcf5ef2aSThomas Huth GEN_PRIV; 4409fcf5ef2aSThomas Huth #else 4410fcf5ef2aSThomas Huth TCGv t0; 4411fcf5ef2aSThomas Huth 4412fcf5ef2aSThomas Huth CHK_SV; 4413fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4414e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4415fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4416fcf5ef2aSThomas Huth tcg_temp_free(t0); 4417fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4418fcf5ef2aSThomas Huth } 4419fcf5ef2aSThomas Huth 4420fcf5ef2aSThomas Huth /* mtsr */ 4421fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4422fcf5ef2aSThomas Huth { 4423fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4424fcf5ef2aSThomas Huth GEN_PRIV; 4425fcf5ef2aSThomas Huth #else 4426fcf5ef2aSThomas Huth TCGv t0; 4427fcf5ef2aSThomas Huth 4428fcf5ef2aSThomas Huth CHK_SV; 4429fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4430fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4431fcf5ef2aSThomas Huth tcg_temp_free(t0); 4432fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4433fcf5ef2aSThomas Huth } 4434fcf5ef2aSThomas Huth 4435fcf5ef2aSThomas Huth /* mtsrin */ 4436fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4437fcf5ef2aSThomas Huth { 4438fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4439fcf5ef2aSThomas Huth GEN_PRIV; 4440fcf5ef2aSThomas Huth #else 4441fcf5ef2aSThomas Huth TCGv t0; 4442fcf5ef2aSThomas Huth 4443fcf5ef2aSThomas Huth CHK_SV; 4444fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4445e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4446fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4447fcf5ef2aSThomas Huth tcg_temp_free(t0); 4448fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4449fcf5ef2aSThomas Huth } 4450fcf5ef2aSThomas Huth 4451fcf5ef2aSThomas Huth /* slbmte */ 4452fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4453fcf5ef2aSThomas Huth { 4454fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4455fcf5ef2aSThomas Huth GEN_PRIV; 4456fcf5ef2aSThomas Huth #else 4457fcf5ef2aSThomas Huth CHK_SV; 4458fcf5ef2aSThomas Huth 4459fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4460fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4461fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4462fcf5ef2aSThomas Huth } 4463fcf5ef2aSThomas Huth 4464fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4465fcf5ef2aSThomas Huth { 4466fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4467fcf5ef2aSThomas Huth GEN_PRIV; 4468fcf5ef2aSThomas Huth #else 4469fcf5ef2aSThomas Huth CHK_SV; 4470fcf5ef2aSThomas Huth 4471fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4472fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4473fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4474fcf5ef2aSThomas Huth } 4475fcf5ef2aSThomas Huth 4476fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4477fcf5ef2aSThomas Huth { 4478fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4479fcf5ef2aSThomas Huth GEN_PRIV; 4480fcf5ef2aSThomas Huth #else 4481fcf5ef2aSThomas Huth CHK_SV; 4482fcf5ef2aSThomas Huth 4483fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4484fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4485fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4486fcf5ef2aSThomas Huth } 4487fcf5ef2aSThomas Huth 4488fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4489fcf5ef2aSThomas Huth { 4490fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4491fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4492fcf5ef2aSThomas Huth #else 4493fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4494fcf5ef2aSThomas Huth 4495fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4496fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4497fcf5ef2aSThomas Huth return; 4498fcf5ef2aSThomas Huth } 4499fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4500fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4501fcf5ef2aSThomas Huth l1 = gen_new_label(); 4502fcf5ef2aSThomas Huth l2 = gen_new_label(); 4503fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4504fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4505efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4506fcf5ef2aSThomas Huth tcg_gen_br(l2); 4507fcf5ef2aSThomas Huth gen_set_label(l1); 4508fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4509fcf5ef2aSThomas Huth gen_set_label(l2); 4510fcf5ef2aSThomas Huth #endif 4511fcf5ef2aSThomas Huth } 4512fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4513fcf5ef2aSThomas Huth 4514fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4515fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4516fcf5ef2aSThomas Huth 4517fcf5ef2aSThomas Huth /* tlbia */ 4518fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4519fcf5ef2aSThomas Huth { 4520fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4521fcf5ef2aSThomas Huth GEN_PRIV; 4522fcf5ef2aSThomas Huth #else 4523fcf5ef2aSThomas Huth CHK_HV; 4524fcf5ef2aSThomas Huth 4525fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4526fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4527fcf5ef2aSThomas Huth } 4528fcf5ef2aSThomas Huth 4529fcf5ef2aSThomas Huth /* tlbiel */ 4530fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4531fcf5ef2aSThomas Huth { 4532fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4533fcf5ef2aSThomas Huth GEN_PRIV; 4534fcf5ef2aSThomas Huth #else 4535fcf5ef2aSThomas Huth CHK_SV; 4536fcf5ef2aSThomas Huth 4537fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4538fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4539fcf5ef2aSThomas Huth } 4540fcf5ef2aSThomas Huth 4541fcf5ef2aSThomas Huth /* tlbie */ 4542fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4543fcf5ef2aSThomas Huth { 4544fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4545fcf5ef2aSThomas Huth GEN_PRIV; 4546fcf5ef2aSThomas Huth #else 4547fcf5ef2aSThomas Huth TCGv_i32 t1; 4548c6fd28fdSSuraj Jitindar Singh 4549c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 4550c6fd28fdSSuraj Jitindar Singh CHK_SV; /* If gtse is set then tblie is supervisor privileged */ 4551c6fd28fdSSuraj Jitindar Singh } else { 4552c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 4553c6fd28fdSSuraj Jitindar Singh } 4554fcf5ef2aSThomas Huth 4555fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4556fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4557fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4558fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4559fcf5ef2aSThomas Huth tcg_temp_free(t0); 4560fcf5ef2aSThomas Huth } else { 4561fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4562fcf5ef2aSThomas Huth } 4563fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4564fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4565fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4566fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4567fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4568fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4569fcf5ef2aSThomas Huth } 4570fcf5ef2aSThomas Huth 4571fcf5ef2aSThomas Huth /* tlbsync */ 4572fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4573fcf5ef2aSThomas Huth { 4574fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4575fcf5ef2aSThomas Huth GEN_PRIV; 4576fcf5ef2aSThomas Huth #else 4577fcf5ef2aSThomas Huth CHK_HV; 4578fcf5ef2aSThomas Huth 4579fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4580fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4581fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4582fcf5ef2aSThomas Huth } 4583fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4584fcf5ef2aSThomas Huth } 4585fcf5ef2aSThomas Huth 4586fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4587fcf5ef2aSThomas Huth /* slbia */ 4588fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 4589fcf5ef2aSThomas Huth { 4590fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4591fcf5ef2aSThomas Huth GEN_PRIV; 4592fcf5ef2aSThomas Huth #else 4593fcf5ef2aSThomas Huth CHK_SV; 4594fcf5ef2aSThomas Huth 4595fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 4596fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4597fcf5ef2aSThomas Huth } 4598fcf5ef2aSThomas Huth 4599fcf5ef2aSThomas Huth /* slbie */ 4600fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 4601fcf5ef2aSThomas Huth { 4602fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4603fcf5ef2aSThomas Huth GEN_PRIV; 4604fcf5ef2aSThomas Huth #else 4605fcf5ef2aSThomas Huth CHK_SV; 4606fcf5ef2aSThomas Huth 4607fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4608fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4609fcf5ef2aSThomas Huth } 4610a63f1dfcSNikunj A Dadhania 4611a63f1dfcSNikunj A Dadhania /* slbieg */ 4612a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 4613a63f1dfcSNikunj A Dadhania { 4614a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 4615a63f1dfcSNikunj A Dadhania GEN_PRIV; 4616a63f1dfcSNikunj A Dadhania #else 4617a63f1dfcSNikunj A Dadhania CHK_SV; 4618a63f1dfcSNikunj A Dadhania 4619a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4620a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 4621a63f1dfcSNikunj A Dadhania } 4622a63f1dfcSNikunj A Dadhania 462362d897caSNikunj A Dadhania /* slbsync */ 462462d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 462562d897caSNikunj A Dadhania { 462662d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 462762d897caSNikunj A Dadhania GEN_PRIV; 462862d897caSNikunj A Dadhania #else 462962d897caSNikunj A Dadhania CHK_SV; 463062d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 463162d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 463262d897caSNikunj A Dadhania } 463362d897caSNikunj A Dadhania 4634fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4635fcf5ef2aSThomas Huth 4636fcf5ef2aSThomas Huth /*** External control ***/ 4637fcf5ef2aSThomas Huth /* Optional: */ 4638fcf5ef2aSThomas Huth 4639fcf5ef2aSThomas Huth /* eciwx */ 4640fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 4641fcf5ef2aSThomas Huth { 4642fcf5ef2aSThomas Huth TCGv t0; 4643fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4644fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4645fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4646fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4647fcf5ef2aSThomas Huth gen_check_align(ctx, t0, 0x03); 4648fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4649fcf5ef2aSThomas Huth tcg_temp_free(t0); 4650fcf5ef2aSThomas Huth } 4651fcf5ef2aSThomas Huth 4652fcf5ef2aSThomas Huth /* ecowx */ 4653fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 4654fcf5ef2aSThomas Huth { 4655fcf5ef2aSThomas Huth TCGv t0; 4656fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4657fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4658fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4659fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4660fcf5ef2aSThomas Huth gen_check_align(ctx, t0, 0x03); 4661fcf5ef2aSThomas Huth gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); 4662fcf5ef2aSThomas Huth tcg_temp_free(t0); 4663fcf5ef2aSThomas Huth } 4664fcf5ef2aSThomas Huth 4665fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 4666fcf5ef2aSThomas Huth 4667fcf5ef2aSThomas Huth /* abs - abs. */ 4668fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 4669fcf5ef2aSThomas Huth { 4670fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4671fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4672fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4673fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4674fcf5ef2aSThomas Huth tcg_gen_br(l2); 4675fcf5ef2aSThomas Huth gen_set_label(l1); 4676fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4677fcf5ef2aSThomas Huth gen_set_label(l2); 4678fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4679fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4680fcf5ef2aSThomas Huth } 4681fcf5ef2aSThomas Huth 4682fcf5ef2aSThomas Huth /* abso - abso. */ 4683fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 4684fcf5ef2aSThomas Huth { 4685fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4686fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4687fcf5ef2aSThomas Huth TCGLabel *l3 = gen_new_label(); 4688fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4689fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4690fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4691fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4692fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4693fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4694fcf5ef2aSThomas Huth tcg_gen_br(l2); 4695fcf5ef2aSThomas Huth gen_set_label(l1); 4696fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4697fcf5ef2aSThomas Huth tcg_gen_br(l3); 4698fcf5ef2aSThomas Huth gen_set_label(l2); 4699fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4700fcf5ef2aSThomas Huth gen_set_label(l3); 4701fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4702fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4703fcf5ef2aSThomas Huth } 4704fcf5ef2aSThomas Huth 4705fcf5ef2aSThomas Huth /* clcs */ 4706fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 4707fcf5ef2aSThomas Huth { 4708fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4709fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4710fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4711fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 4712fcf5ef2aSThomas Huth } 4713fcf5ef2aSThomas Huth 4714fcf5ef2aSThomas Huth /* div - div. */ 4715fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 4716fcf5ef2aSThomas Huth { 4717fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4718fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4719fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4720fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4721fcf5ef2aSThomas Huth } 4722fcf5ef2aSThomas Huth 4723fcf5ef2aSThomas Huth /* divo - divo. */ 4724fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 4725fcf5ef2aSThomas Huth { 4726fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4727fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4728fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4729fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4730fcf5ef2aSThomas Huth } 4731fcf5ef2aSThomas Huth 4732fcf5ef2aSThomas Huth /* divs - divs. */ 4733fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 4734fcf5ef2aSThomas Huth { 4735fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4736fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4737fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4738fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4739fcf5ef2aSThomas Huth } 4740fcf5ef2aSThomas Huth 4741fcf5ef2aSThomas Huth /* divso - divso. */ 4742fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 4743fcf5ef2aSThomas Huth { 4744fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4745fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4746fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4747fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4748fcf5ef2aSThomas Huth } 4749fcf5ef2aSThomas Huth 4750fcf5ef2aSThomas Huth /* doz - doz. */ 4751fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 4752fcf5ef2aSThomas Huth { 4753fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4754fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4755fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4756fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4757fcf5ef2aSThomas Huth tcg_gen_br(l2); 4758fcf5ef2aSThomas Huth gen_set_label(l1); 4759fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4760fcf5ef2aSThomas Huth gen_set_label(l2); 4761fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4762fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4763fcf5ef2aSThomas Huth } 4764fcf5ef2aSThomas Huth 4765fcf5ef2aSThomas Huth /* dozo - dozo. */ 4766fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 4767fcf5ef2aSThomas Huth { 4768fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4769fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4770fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4771fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4772fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4773fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4774fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4775fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4776fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4777fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4778fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4779fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 4780fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4781fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4782fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4783fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4784fcf5ef2aSThomas Huth tcg_gen_br(l2); 4785fcf5ef2aSThomas Huth gen_set_label(l1); 4786fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4787fcf5ef2aSThomas Huth gen_set_label(l2); 4788fcf5ef2aSThomas Huth tcg_temp_free(t0); 4789fcf5ef2aSThomas Huth tcg_temp_free(t1); 4790fcf5ef2aSThomas Huth tcg_temp_free(t2); 4791fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4792fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4793fcf5ef2aSThomas Huth } 4794fcf5ef2aSThomas Huth 4795fcf5ef2aSThomas Huth /* dozi */ 4796fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 4797fcf5ef2aSThomas Huth { 4798fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 4799fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4800fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4801fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 4802fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 4803fcf5ef2aSThomas Huth tcg_gen_br(l2); 4804fcf5ef2aSThomas Huth gen_set_label(l1); 4805fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4806fcf5ef2aSThomas Huth gen_set_label(l2); 4807fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4808fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4809fcf5ef2aSThomas Huth } 4810fcf5ef2aSThomas Huth 4811fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 4812fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 4813fcf5ef2aSThomas Huth { 4814fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4815fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 4816fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 4817fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 4818fcf5ef2aSThomas Huth 4819fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4820fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 4821fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4822fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 4823fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 4824fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 4825fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 4826fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4827fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 4828fcf5ef2aSThomas Huth tcg_temp_free(t0); 4829fcf5ef2aSThomas Huth } 4830fcf5ef2aSThomas Huth 4831fcf5ef2aSThomas Huth /* maskg - maskg. */ 4832fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 4833fcf5ef2aSThomas Huth { 4834fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4835fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4836fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4837fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4838fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 4839fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 4840fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4841fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 4842fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 4843fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 4844fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 4845fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 4846fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 4847fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4848fcf5ef2aSThomas Huth gen_set_label(l1); 4849fcf5ef2aSThomas Huth tcg_temp_free(t0); 4850fcf5ef2aSThomas Huth tcg_temp_free(t1); 4851fcf5ef2aSThomas Huth tcg_temp_free(t2); 4852fcf5ef2aSThomas Huth tcg_temp_free(t3); 4853fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4854fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4855fcf5ef2aSThomas Huth } 4856fcf5ef2aSThomas Huth 4857fcf5ef2aSThomas Huth /* maskir - maskir. */ 4858fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 4859fcf5ef2aSThomas Huth { 4860fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4861fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4862fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4863fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4864fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4865fcf5ef2aSThomas Huth tcg_temp_free(t0); 4866fcf5ef2aSThomas Huth tcg_temp_free(t1); 4867fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4868fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4869fcf5ef2aSThomas Huth } 4870fcf5ef2aSThomas Huth 4871fcf5ef2aSThomas Huth /* mul - mul. */ 4872fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 4873fcf5ef2aSThomas Huth { 4874fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 4875fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 4876fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4877fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4878fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4879fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 4880fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 4881fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 4882fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 4883fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4884fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 4885fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 4886fcf5ef2aSThomas Huth tcg_temp_free(t2); 4887fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4888fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4889fcf5ef2aSThomas Huth } 4890fcf5ef2aSThomas Huth 4891fcf5ef2aSThomas Huth /* mulo - mulo. */ 4892fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 4893fcf5ef2aSThomas Huth { 4894fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4895fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 4896fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 4897fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4898fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4899fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4900fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 4901fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 4902fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 4903fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 4904fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 4905fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 4906fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 4907fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 4908fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 4909fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4910fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4911fcf5ef2aSThomas Huth gen_set_label(l1); 4912fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 4913fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 4914fcf5ef2aSThomas Huth tcg_temp_free(t2); 4915fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4916fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4917fcf5ef2aSThomas Huth } 4918fcf5ef2aSThomas Huth 4919fcf5ef2aSThomas Huth /* nabs - nabs. */ 4920fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 4921fcf5ef2aSThomas Huth { 4922fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4923fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4924fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4925fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4926fcf5ef2aSThomas Huth tcg_gen_br(l2); 4927fcf5ef2aSThomas Huth gen_set_label(l1); 4928fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4929fcf5ef2aSThomas Huth gen_set_label(l2); 4930fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4931fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4932fcf5ef2aSThomas Huth } 4933fcf5ef2aSThomas Huth 4934fcf5ef2aSThomas Huth /* nabso - nabso. */ 4935fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 4936fcf5ef2aSThomas Huth { 4937fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4938fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4939fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 4940fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4941fcf5ef2aSThomas Huth tcg_gen_br(l2); 4942fcf5ef2aSThomas Huth gen_set_label(l1); 4943fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4944fcf5ef2aSThomas Huth gen_set_label(l2); 4945fcf5ef2aSThomas Huth /* nabs never overflows */ 4946fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4947fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4948fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4949fcf5ef2aSThomas Huth } 4950fcf5ef2aSThomas Huth 4951fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 4952fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 4953fcf5ef2aSThomas Huth { 4954fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 4955fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 4956fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4957fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4958fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4959fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 4960fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 4961fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 4962fcf5ef2aSThomas Huth tcg_temp_free(t0); 4963fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4964fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4965fcf5ef2aSThomas Huth } 4966fcf5ef2aSThomas Huth 4967fcf5ef2aSThomas Huth /* rrib - rrib. */ 4968fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 4969fcf5ef2aSThomas Huth { 4970fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4971fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4972fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 4973fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 4974fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 4975fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 4976fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 4977fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 4978fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 4979fcf5ef2aSThomas Huth tcg_temp_free(t0); 4980fcf5ef2aSThomas Huth tcg_temp_free(t1); 4981fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4982fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 4983fcf5ef2aSThomas Huth } 4984fcf5ef2aSThomas Huth 4985fcf5ef2aSThomas Huth /* sle - sle. */ 4986fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 4987fcf5ef2aSThomas Huth { 4988fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4989fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4990fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 4991fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 4992fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 4993fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 4994fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 4995fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 4996fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 4997fcf5ef2aSThomas Huth tcg_temp_free(t0); 4998fcf5ef2aSThomas Huth tcg_temp_free(t1); 4999fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5000fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5001fcf5ef2aSThomas Huth } 5002fcf5ef2aSThomas Huth 5003fcf5ef2aSThomas Huth /* sleq - sleq. */ 5004fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5005fcf5ef2aSThomas Huth { 5006fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5007fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5008fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5009fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5010fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5011fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5012fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5013fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5014fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5015fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5016fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5017fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5018fcf5ef2aSThomas Huth tcg_temp_free(t0); 5019fcf5ef2aSThomas Huth tcg_temp_free(t1); 5020fcf5ef2aSThomas Huth tcg_temp_free(t2); 5021fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5022fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5023fcf5ef2aSThomas Huth } 5024fcf5ef2aSThomas Huth 5025fcf5ef2aSThomas Huth /* sliq - sliq. */ 5026fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5027fcf5ef2aSThomas Huth { 5028fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5029fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5030fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5031fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5032fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5033fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5034fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5035fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5036fcf5ef2aSThomas Huth tcg_temp_free(t0); 5037fcf5ef2aSThomas Huth tcg_temp_free(t1); 5038fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5039fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5040fcf5ef2aSThomas Huth } 5041fcf5ef2aSThomas Huth 5042fcf5ef2aSThomas Huth /* slliq - slliq. */ 5043fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5044fcf5ef2aSThomas Huth { 5045fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5046fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5047fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5048fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5049fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5050fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5051fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5052fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5053fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5054fcf5ef2aSThomas Huth tcg_temp_free(t0); 5055fcf5ef2aSThomas Huth tcg_temp_free(t1); 5056fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5057fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5058fcf5ef2aSThomas Huth } 5059fcf5ef2aSThomas Huth 5060fcf5ef2aSThomas Huth /* sllq - sllq. */ 5061fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5062fcf5ef2aSThomas Huth { 5063fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5064fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5065fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5066fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5067fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5068fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5069fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5070fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5071fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5072fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5073fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5074fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5075fcf5ef2aSThomas Huth tcg_gen_br(l2); 5076fcf5ef2aSThomas Huth gen_set_label(l1); 5077fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5078fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5079fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5080fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5081fcf5ef2aSThomas Huth gen_set_label(l2); 5082fcf5ef2aSThomas Huth tcg_temp_free(t0); 5083fcf5ef2aSThomas Huth tcg_temp_free(t1); 5084fcf5ef2aSThomas Huth tcg_temp_free(t2); 5085fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5086fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5087fcf5ef2aSThomas Huth } 5088fcf5ef2aSThomas Huth 5089fcf5ef2aSThomas Huth /* slq - slq. */ 5090fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5091fcf5ef2aSThomas Huth { 5092fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5093fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5094fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5095fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5096fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5097fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5098fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5099fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5100fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5101fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5102fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5103fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5104fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5105fcf5ef2aSThomas Huth gen_set_label(l1); 5106fcf5ef2aSThomas Huth tcg_temp_free(t0); 5107fcf5ef2aSThomas Huth tcg_temp_free(t1); 5108fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5109fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5110fcf5ef2aSThomas Huth } 5111fcf5ef2aSThomas Huth 5112fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5113fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5114fcf5ef2aSThomas Huth { 5115fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5116fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5117fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5118fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5119fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5120fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5121fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5122fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5123fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5124fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5125fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5126fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5127fcf5ef2aSThomas Huth gen_set_label(l1); 5128fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5129fcf5ef2aSThomas Huth tcg_temp_free(t0); 5130fcf5ef2aSThomas Huth tcg_temp_free(t1); 5131fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5132fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5133fcf5ef2aSThomas Huth } 5134fcf5ef2aSThomas Huth 5135fcf5ef2aSThomas Huth /* sraq - sraq. */ 5136fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5137fcf5ef2aSThomas Huth { 5138fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5139fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5140fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5141fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5142fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5143fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5144fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5145fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5146fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5147fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5148fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5149fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5150fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5151fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5152fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5153fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5154fcf5ef2aSThomas Huth gen_set_label(l1); 5155fcf5ef2aSThomas Huth tcg_temp_free(t0); 5156fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5157fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5158fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5159fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5160fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5161fcf5ef2aSThomas Huth gen_set_label(l2); 5162fcf5ef2aSThomas Huth tcg_temp_free(t1); 5163fcf5ef2aSThomas Huth tcg_temp_free(t2); 5164fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5165fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5166fcf5ef2aSThomas Huth } 5167fcf5ef2aSThomas Huth 5168fcf5ef2aSThomas Huth /* sre - sre. */ 5169fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5170fcf5ef2aSThomas Huth { 5171fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5172fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5173fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5174fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5175fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5176fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5177fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5178fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5179fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5180fcf5ef2aSThomas Huth tcg_temp_free(t0); 5181fcf5ef2aSThomas Huth tcg_temp_free(t1); 5182fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5183fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5184fcf5ef2aSThomas Huth } 5185fcf5ef2aSThomas Huth 5186fcf5ef2aSThomas Huth /* srea - srea. */ 5187fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5188fcf5ef2aSThomas Huth { 5189fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5190fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5191fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5192fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5193fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5194fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5195fcf5ef2aSThomas Huth tcg_temp_free(t0); 5196fcf5ef2aSThomas Huth tcg_temp_free(t1); 5197fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5198fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5199fcf5ef2aSThomas Huth } 5200fcf5ef2aSThomas Huth 5201fcf5ef2aSThomas Huth /* sreq */ 5202fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5203fcf5ef2aSThomas Huth { 5204fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5205fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5206fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5207fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5208fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5209fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5210fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5211fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5212fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5213fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5214fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5215fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5216fcf5ef2aSThomas Huth tcg_temp_free(t0); 5217fcf5ef2aSThomas Huth tcg_temp_free(t1); 5218fcf5ef2aSThomas Huth tcg_temp_free(t2); 5219fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5220fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5221fcf5ef2aSThomas Huth } 5222fcf5ef2aSThomas Huth 5223fcf5ef2aSThomas Huth /* sriq */ 5224fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5225fcf5ef2aSThomas Huth { 5226fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5227fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5228fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5229fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5230fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5231fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5232fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5233fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5234fcf5ef2aSThomas Huth tcg_temp_free(t0); 5235fcf5ef2aSThomas Huth tcg_temp_free(t1); 5236fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5237fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5238fcf5ef2aSThomas Huth } 5239fcf5ef2aSThomas Huth 5240fcf5ef2aSThomas Huth /* srliq */ 5241fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5242fcf5ef2aSThomas Huth { 5243fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5244fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5245fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5246fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5247fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5248fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5249fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5250fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5251fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5252fcf5ef2aSThomas Huth tcg_temp_free(t0); 5253fcf5ef2aSThomas Huth tcg_temp_free(t1); 5254fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5255fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5256fcf5ef2aSThomas Huth } 5257fcf5ef2aSThomas Huth 5258fcf5ef2aSThomas Huth /* srlq */ 5259fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5260fcf5ef2aSThomas Huth { 5261fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5262fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5263fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5264fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5265fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5266fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5267fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5268fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5269fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5270fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5271fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5272fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5273fcf5ef2aSThomas Huth tcg_gen_br(l2); 5274fcf5ef2aSThomas Huth gen_set_label(l1); 5275fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5276fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5277fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5278fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5279fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5280fcf5ef2aSThomas Huth gen_set_label(l2); 5281fcf5ef2aSThomas Huth tcg_temp_free(t0); 5282fcf5ef2aSThomas Huth tcg_temp_free(t1); 5283fcf5ef2aSThomas Huth tcg_temp_free(t2); 5284fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5285fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5286fcf5ef2aSThomas Huth } 5287fcf5ef2aSThomas Huth 5288fcf5ef2aSThomas Huth /* srq */ 5289fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5290fcf5ef2aSThomas Huth { 5291fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5292fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5293fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5294fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5295fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5296fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5297fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5298fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5299fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5300fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5301fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5302fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5303fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5304fcf5ef2aSThomas Huth gen_set_label(l1); 5305fcf5ef2aSThomas Huth tcg_temp_free(t0); 5306fcf5ef2aSThomas Huth tcg_temp_free(t1); 5307fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5308fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5309fcf5ef2aSThomas Huth } 5310fcf5ef2aSThomas Huth 5311fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5312fcf5ef2aSThomas Huth 5313fcf5ef2aSThomas Huth /* dsa */ 5314fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5315fcf5ef2aSThomas Huth { 5316fcf5ef2aSThomas Huth /* XXX: TODO */ 5317fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5318fcf5ef2aSThomas Huth } 5319fcf5ef2aSThomas Huth 5320fcf5ef2aSThomas Huth /* esa */ 5321fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5322fcf5ef2aSThomas Huth { 5323fcf5ef2aSThomas Huth /* XXX: TODO */ 5324fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5325fcf5ef2aSThomas Huth } 5326fcf5ef2aSThomas Huth 5327fcf5ef2aSThomas Huth /* mfrom */ 5328fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5329fcf5ef2aSThomas Huth { 5330fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5331fcf5ef2aSThomas Huth GEN_PRIV; 5332fcf5ef2aSThomas Huth #else 5333fcf5ef2aSThomas Huth CHK_SV; 5334fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5335fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5336fcf5ef2aSThomas Huth } 5337fcf5ef2aSThomas Huth 5338fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5339fcf5ef2aSThomas Huth 5340fcf5ef2aSThomas Huth /* tlbld */ 5341fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5342fcf5ef2aSThomas Huth { 5343fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5344fcf5ef2aSThomas Huth GEN_PRIV; 5345fcf5ef2aSThomas Huth #else 5346fcf5ef2aSThomas Huth CHK_SV; 5347fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5348fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5349fcf5ef2aSThomas Huth } 5350fcf5ef2aSThomas Huth 5351fcf5ef2aSThomas Huth /* tlbli */ 5352fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5353fcf5ef2aSThomas Huth { 5354fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5355fcf5ef2aSThomas Huth GEN_PRIV; 5356fcf5ef2aSThomas Huth #else 5357fcf5ef2aSThomas Huth CHK_SV; 5358fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5359fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5360fcf5ef2aSThomas Huth } 5361fcf5ef2aSThomas Huth 5362fcf5ef2aSThomas Huth /* 74xx TLB management */ 5363fcf5ef2aSThomas Huth 5364fcf5ef2aSThomas Huth /* tlbld */ 5365fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5366fcf5ef2aSThomas Huth { 5367fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5368fcf5ef2aSThomas Huth GEN_PRIV; 5369fcf5ef2aSThomas Huth #else 5370fcf5ef2aSThomas Huth CHK_SV; 5371fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5372fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5373fcf5ef2aSThomas Huth } 5374fcf5ef2aSThomas Huth 5375fcf5ef2aSThomas Huth /* tlbli */ 5376fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5377fcf5ef2aSThomas Huth { 5378fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5379fcf5ef2aSThomas Huth GEN_PRIV; 5380fcf5ef2aSThomas Huth #else 5381fcf5ef2aSThomas Huth CHK_SV; 5382fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5383fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5384fcf5ef2aSThomas Huth } 5385fcf5ef2aSThomas Huth 5386fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5387fcf5ef2aSThomas Huth 5388fcf5ef2aSThomas Huth /* clf */ 5389fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5390fcf5ef2aSThomas Huth { 5391fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5392fcf5ef2aSThomas Huth } 5393fcf5ef2aSThomas Huth 5394fcf5ef2aSThomas Huth /* cli */ 5395fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5396fcf5ef2aSThomas Huth { 5397fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5398fcf5ef2aSThomas Huth GEN_PRIV; 5399fcf5ef2aSThomas Huth #else 5400fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5401fcf5ef2aSThomas Huth CHK_SV; 5402fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5403fcf5ef2aSThomas Huth } 5404fcf5ef2aSThomas Huth 5405fcf5ef2aSThomas Huth /* dclst */ 5406fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5407fcf5ef2aSThomas Huth { 5408fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5409fcf5ef2aSThomas Huth } 5410fcf5ef2aSThomas Huth 5411fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5412fcf5ef2aSThomas Huth { 5413fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5414fcf5ef2aSThomas Huth GEN_PRIV; 5415fcf5ef2aSThomas Huth #else 5416fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5417fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5418fcf5ef2aSThomas Huth TCGv t0; 5419fcf5ef2aSThomas Huth 5420fcf5ef2aSThomas Huth CHK_SV; 5421fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5422fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5423e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 5424fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5425fcf5ef2aSThomas Huth tcg_temp_free(t0); 5426fcf5ef2aSThomas Huth if (ra != 0 && ra != rd) 5427fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5428fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5429fcf5ef2aSThomas Huth } 5430fcf5ef2aSThomas Huth 5431fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5432fcf5ef2aSThomas Huth { 5433fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5434fcf5ef2aSThomas Huth GEN_PRIV; 5435fcf5ef2aSThomas Huth #else 5436fcf5ef2aSThomas Huth TCGv t0; 5437fcf5ef2aSThomas Huth 5438fcf5ef2aSThomas Huth CHK_SV; 5439fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5440fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5441fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5442fcf5ef2aSThomas Huth tcg_temp_free(t0); 5443fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5444fcf5ef2aSThomas Huth } 5445fcf5ef2aSThomas Huth 5446fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5447fcf5ef2aSThomas Huth { 5448fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5449fcf5ef2aSThomas Huth GEN_PRIV; 5450fcf5ef2aSThomas Huth #else 5451fcf5ef2aSThomas Huth CHK_SV; 5452fcf5ef2aSThomas Huth 5453fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5454fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5455fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5456fcf5ef2aSThomas Huth } 5457fcf5ef2aSThomas Huth 5458fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5459fcf5ef2aSThomas Huth 5460fcf5ef2aSThomas Huth /* BookE specific instructions */ 5461fcf5ef2aSThomas Huth 5462fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5463fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5464fcf5ef2aSThomas Huth { 5465fcf5ef2aSThomas Huth /* XXX: TODO */ 5466fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5467fcf5ef2aSThomas Huth } 5468fcf5ef2aSThomas Huth 5469fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5470fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5471fcf5ef2aSThomas Huth { 5472fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5473fcf5ef2aSThomas Huth GEN_PRIV; 5474fcf5ef2aSThomas Huth #else 5475fcf5ef2aSThomas Huth TCGv t0; 5476fcf5ef2aSThomas Huth 5477fcf5ef2aSThomas Huth CHK_SV; 5478fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5479fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5480fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5481fcf5ef2aSThomas Huth tcg_temp_free(t0); 5482fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5483fcf5ef2aSThomas Huth } 5484fcf5ef2aSThomas Huth 5485fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5486fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5487fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5488fcf5ef2aSThomas Huth { 5489fcf5ef2aSThomas Huth TCGv t0, t1; 5490fcf5ef2aSThomas Huth 5491fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5492fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5493fcf5ef2aSThomas Huth 5494fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5495fcf5ef2aSThomas Huth case 0x05: 5496fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5497fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5498fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5499fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5500fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5501fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5502fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5503fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5504fcf5ef2aSThomas Huth break; 5505fcf5ef2aSThomas Huth case 0x04: 5506fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5507fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5508fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5509fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5510fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5511fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5512fcf5ef2aSThomas Huth break; 5513fcf5ef2aSThomas Huth case 0x01: 5514fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5515fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5516fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5517fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5518fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5519fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5520fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5521fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5522fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5523fcf5ef2aSThomas Huth break; 5524fcf5ef2aSThomas Huth case 0x00: 5525fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5526fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5527fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5528fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5529fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5530fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5531fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5532fcf5ef2aSThomas Huth break; 5533fcf5ef2aSThomas Huth case 0x0D: 5534fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5535fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5536fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5537fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5538fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5539fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5540fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5541fcf5ef2aSThomas Huth break; 5542fcf5ef2aSThomas Huth case 0x0C: 5543fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5544fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5545fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5546fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5547fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5548fcf5ef2aSThomas Huth break; 5549fcf5ef2aSThomas Huth } 5550fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5551fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5552fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5553fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5554fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5555fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5556fcf5ef2aSThomas Huth } else { 5557fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5558fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5559fcf5ef2aSThomas Huth } 5560fcf5ef2aSThomas Huth 5561fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5562fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5563fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5564fcf5ef2aSThomas Huth 5565fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5566fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5567fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5568fcf5ef2aSThomas Huth } 5569fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5570fcf5ef2aSThomas Huth /* Signed */ 5571fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5572fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5573fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5574fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5575fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5576fcf5ef2aSThomas Huth /* Saturate */ 5577fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5578fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5579fcf5ef2aSThomas Huth } 5580fcf5ef2aSThomas Huth } else { 5581fcf5ef2aSThomas Huth /* Unsigned */ 5582fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5583fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5584fcf5ef2aSThomas Huth /* Saturate */ 5585fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5586fcf5ef2aSThomas Huth } 5587fcf5ef2aSThomas Huth } 5588fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5589fcf5ef2aSThomas Huth /* Check overflow */ 5590fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5591fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5592fcf5ef2aSThomas Huth } 5593fcf5ef2aSThomas Huth gen_set_label(l1); 5594fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5595fcf5ef2aSThomas Huth } 5596fcf5ef2aSThomas Huth } else { 5597fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5598fcf5ef2aSThomas Huth } 5599fcf5ef2aSThomas Huth tcg_temp_free(t0); 5600fcf5ef2aSThomas Huth tcg_temp_free(t1); 5601fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5602fcf5ef2aSThomas Huth /* Update Rc0 */ 5603fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5604fcf5ef2aSThomas Huth } 5605fcf5ef2aSThomas Huth } 5606fcf5ef2aSThomas Huth 5607fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5608fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5609fcf5ef2aSThomas Huth { \ 5610fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5611fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5612fcf5ef2aSThomas Huth } 5613fcf5ef2aSThomas Huth 5614fcf5ef2aSThomas Huth /* macchw - macchw. */ 5615fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5616fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5617fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5618fcf5ef2aSThomas Huth /* macchws - macchws. */ 5619fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5620fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5621fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5622fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5623fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5624fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5625fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5626fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5627fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5628fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5629fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5630fcf5ef2aSThomas Huth /* machhw - machhw. */ 5631fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5632fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5633fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5634fcf5ef2aSThomas Huth /* machhws - machhws. */ 5635fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5636fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5637fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5638fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5639fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5640fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5641fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5642fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5643fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5644fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5645fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5646fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5647fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5648fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5649fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5650fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5651fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5652fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5653fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5654fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5655fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5656fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5657fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5658fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5659fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5660fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5661fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5662fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5663fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5664fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5665fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5666fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5667fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5668fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5669fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5670fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5671fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5672fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5673fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5674fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5675fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5676fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5677fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5678fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5679fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5680fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5681fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5682fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5683fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5684fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5685fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5686fcf5ef2aSThomas Huth 5687fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5688fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5689fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5690fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5691fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5692fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5693fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5694fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5695fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5696fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5697fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5698fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5699fcf5ef2aSThomas Huth 5700fcf5ef2aSThomas Huth /* mfdcr */ 5701fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5702fcf5ef2aSThomas Huth { 5703fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5704fcf5ef2aSThomas Huth GEN_PRIV; 5705fcf5ef2aSThomas Huth #else 5706fcf5ef2aSThomas Huth TCGv dcrn; 5707fcf5ef2aSThomas Huth 5708fcf5ef2aSThomas Huth CHK_SV; 5709fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5710fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5711fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5712fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5713fcf5ef2aSThomas Huth } 5714fcf5ef2aSThomas Huth 5715fcf5ef2aSThomas Huth /* mtdcr */ 5716fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5717fcf5ef2aSThomas Huth { 5718fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5719fcf5ef2aSThomas Huth GEN_PRIV; 5720fcf5ef2aSThomas Huth #else 5721fcf5ef2aSThomas Huth TCGv dcrn; 5722fcf5ef2aSThomas Huth 5723fcf5ef2aSThomas Huth CHK_SV; 5724fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5725fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5726fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5727fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5728fcf5ef2aSThomas Huth } 5729fcf5ef2aSThomas Huth 5730fcf5ef2aSThomas Huth /* mfdcrx */ 5731fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5732fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5733fcf5ef2aSThomas Huth { 5734fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5735fcf5ef2aSThomas Huth GEN_PRIV; 5736fcf5ef2aSThomas Huth #else 5737fcf5ef2aSThomas Huth CHK_SV; 5738fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5739fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5740fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5741fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5742fcf5ef2aSThomas Huth } 5743fcf5ef2aSThomas Huth 5744fcf5ef2aSThomas Huth /* mtdcrx */ 5745fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5746fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5747fcf5ef2aSThomas Huth { 5748fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5749fcf5ef2aSThomas Huth GEN_PRIV; 5750fcf5ef2aSThomas Huth #else 5751fcf5ef2aSThomas Huth CHK_SV; 5752fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5753fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5754fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5755fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5756fcf5ef2aSThomas Huth } 5757fcf5ef2aSThomas Huth 5758fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 5759fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 5760fcf5ef2aSThomas Huth { 5761fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5762fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5763fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5764fcf5ef2aSThomas Huth } 5765fcf5ef2aSThomas Huth 5766fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 5767fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 5768fcf5ef2aSThomas Huth { 5769fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5770fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5771fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5772fcf5ef2aSThomas Huth } 5773fcf5ef2aSThomas Huth 5774fcf5ef2aSThomas Huth /* dccci */ 5775fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5776fcf5ef2aSThomas Huth { 5777fcf5ef2aSThomas Huth CHK_SV; 5778fcf5ef2aSThomas Huth /* interpreted as no-op */ 5779fcf5ef2aSThomas Huth } 5780fcf5ef2aSThomas Huth 5781fcf5ef2aSThomas Huth /* dcread */ 5782fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5783fcf5ef2aSThomas Huth { 5784fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5785fcf5ef2aSThomas Huth GEN_PRIV; 5786fcf5ef2aSThomas Huth #else 5787fcf5ef2aSThomas Huth TCGv EA, val; 5788fcf5ef2aSThomas Huth 5789fcf5ef2aSThomas Huth CHK_SV; 5790fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5791fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5792fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5793fcf5ef2aSThomas Huth val = tcg_temp_new(); 5794fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5795fcf5ef2aSThomas Huth tcg_temp_free(val); 5796fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5797fcf5ef2aSThomas Huth tcg_temp_free(EA); 5798fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5799fcf5ef2aSThomas Huth } 5800fcf5ef2aSThomas Huth 5801fcf5ef2aSThomas Huth /* icbt */ 5802fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 5803fcf5ef2aSThomas Huth { 5804fcf5ef2aSThomas Huth /* interpreted as no-op */ 5805fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 5806fcf5ef2aSThomas Huth * but does not generate any exception 5807fcf5ef2aSThomas Huth */ 5808fcf5ef2aSThomas Huth } 5809fcf5ef2aSThomas Huth 5810fcf5ef2aSThomas Huth /* iccci */ 5811fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 5812fcf5ef2aSThomas Huth { 5813fcf5ef2aSThomas Huth CHK_SV; 5814fcf5ef2aSThomas Huth /* interpreted as no-op */ 5815fcf5ef2aSThomas Huth } 5816fcf5ef2aSThomas Huth 5817fcf5ef2aSThomas Huth /* icread */ 5818fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 5819fcf5ef2aSThomas Huth { 5820fcf5ef2aSThomas Huth CHK_SV; 5821fcf5ef2aSThomas Huth /* interpreted as no-op */ 5822fcf5ef2aSThomas Huth } 5823fcf5ef2aSThomas Huth 5824fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 5825fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 5826fcf5ef2aSThomas Huth { 5827fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5828fcf5ef2aSThomas Huth GEN_PRIV; 5829fcf5ef2aSThomas Huth #else 5830fcf5ef2aSThomas Huth CHK_SV; 5831fcf5ef2aSThomas Huth /* Restore CPU state */ 5832fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 5833fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5834fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5835fcf5ef2aSThomas Huth } 5836fcf5ef2aSThomas Huth 5837fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 5838fcf5ef2aSThomas Huth { 5839fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5840fcf5ef2aSThomas Huth GEN_PRIV; 5841fcf5ef2aSThomas Huth #else 5842fcf5ef2aSThomas Huth CHK_SV; 5843fcf5ef2aSThomas Huth /* Restore CPU state */ 5844fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 5845fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5846fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5847fcf5ef2aSThomas Huth } 5848fcf5ef2aSThomas Huth 5849fcf5ef2aSThomas Huth /* BookE specific */ 5850fcf5ef2aSThomas Huth 5851fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5852fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 5853fcf5ef2aSThomas Huth { 5854fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5855fcf5ef2aSThomas Huth GEN_PRIV; 5856fcf5ef2aSThomas Huth #else 5857fcf5ef2aSThomas Huth CHK_SV; 5858fcf5ef2aSThomas Huth /* Restore CPU state */ 5859fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 5860fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5861fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5862fcf5ef2aSThomas Huth } 5863fcf5ef2aSThomas Huth 5864fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5865fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 5866fcf5ef2aSThomas Huth { 5867fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5868fcf5ef2aSThomas Huth GEN_PRIV; 5869fcf5ef2aSThomas Huth #else 5870fcf5ef2aSThomas Huth CHK_SV; 5871fcf5ef2aSThomas Huth /* Restore CPU state */ 5872fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 5873fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5874fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5875fcf5ef2aSThomas Huth } 5876fcf5ef2aSThomas Huth 5877fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 5878fcf5ef2aSThomas Huth 5879fcf5ef2aSThomas Huth /* tlbre */ 5880fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 5881fcf5ef2aSThomas Huth { 5882fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5883fcf5ef2aSThomas Huth GEN_PRIV; 5884fcf5ef2aSThomas Huth #else 5885fcf5ef2aSThomas Huth CHK_SV; 5886fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5887fcf5ef2aSThomas Huth case 0: 5888fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 5889fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5890fcf5ef2aSThomas Huth break; 5891fcf5ef2aSThomas Huth case 1: 5892fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 5893fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5894fcf5ef2aSThomas Huth break; 5895fcf5ef2aSThomas Huth default: 5896fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5897fcf5ef2aSThomas Huth break; 5898fcf5ef2aSThomas Huth } 5899fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5900fcf5ef2aSThomas Huth } 5901fcf5ef2aSThomas Huth 5902fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5903fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 5904fcf5ef2aSThomas Huth { 5905fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5906fcf5ef2aSThomas Huth GEN_PRIV; 5907fcf5ef2aSThomas Huth #else 5908fcf5ef2aSThomas Huth TCGv t0; 5909fcf5ef2aSThomas Huth 5910fcf5ef2aSThomas Huth CHK_SV; 5911fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5912fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5913fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5914fcf5ef2aSThomas Huth tcg_temp_free(t0); 5915fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5916fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5917fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5918fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5919fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5920fcf5ef2aSThomas Huth gen_set_label(l1); 5921fcf5ef2aSThomas Huth } 5922fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5923fcf5ef2aSThomas Huth } 5924fcf5ef2aSThomas Huth 5925fcf5ef2aSThomas Huth /* tlbwe */ 5926fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 5927fcf5ef2aSThomas Huth { 5928fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5929fcf5ef2aSThomas Huth GEN_PRIV; 5930fcf5ef2aSThomas Huth #else 5931fcf5ef2aSThomas Huth CHK_SV; 5932fcf5ef2aSThomas Huth 5933fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5934fcf5ef2aSThomas Huth case 0: 5935fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 5936fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5937fcf5ef2aSThomas Huth break; 5938fcf5ef2aSThomas Huth case 1: 5939fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 5940fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5941fcf5ef2aSThomas Huth break; 5942fcf5ef2aSThomas Huth default: 5943fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5944fcf5ef2aSThomas Huth break; 5945fcf5ef2aSThomas Huth } 5946fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5947fcf5ef2aSThomas Huth } 5948fcf5ef2aSThomas Huth 5949fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 5950fcf5ef2aSThomas Huth 5951fcf5ef2aSThomas Huth /* tlbre */ 5952fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 5953fcf5ef2aSThomas Huth { 5954fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5955fcf5ef2aSThomas Huth GEN_PRIV; 5956fcf5ef2aSThomas Huth #else 5957fcf5ef2aSThomas Huth CHK_SV; 5958fcf5ef2aSThomas Huth 5959fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 5960fcf5ef2aSThomas Huth case 0: 5961fcf5ef2aSThomas Huth case 1: 5962fcf5ef2aSThomas Huth case 2: 5963fcf5ef2aSThomas Huth { 5964fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 5965fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 5966fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 5967fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 5968fcf5ef2aSThomas Huth } 5969fcf5ef2aSThomas Huth break; 5970fcf5ef2aSThomas Huth default: 5971fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5972fcf5ef2aSThomas Huth break; 5973fcf5ef2aSThomas Huth } 5974fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5975fcf5ef2aSThomas Huth } 5976fcf5ef2aSThomas Huth 5977fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 5978fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 5979fcf5ef2aSThomas Huth { 5980fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5981fcf5ef2aSThomas Huth GEN_PRIV; 5982fcf5ef2aSThomas Huth #else 5983fcf5ef2aSThomas Huth TCGv t0; 5984fcf5ef2aSThomas Huth 5985fcf5ef2aSThomas Huth CHK_SV; 5986fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5987fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5988fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5989fcf5ef2aSThomas Huth tcg_temp_free(t0); 5990fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 5991fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5992fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 5993fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 5994fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 5995fcf5ef2aSThomas Huth gen_set_label(l1); 5996fcf5ef2aSThomas Huth } 5997fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5998fcf5ef2aSThomas Huth } 5999fcf5ef2aSThomas Huth 6000fcf5ef2aSThomas Huth /* tlbwe */ 6001fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6002fcf5ef2aSThomas Huth { 6003fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6004fcf5ef2aSThomas Huth GEN_PRIV; 6005fcf5ef2aSThomas Huth #else 6006fcf5ef2aSThomas Huth CHK_SV; 6007fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6008fcf5ef2aSThomas Huth case 0: 6009fcf5ef2aSThomas Huth case 1: 6010fcf5ef2aSThomas Huth case 2: 6011fcf5ef2aSThomas Huth { 6012fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6013fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6014fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6015fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6016fcf5ef2aSThomas Huth } 6017fcf5ef2aSThomas Huth break; 6018fcf5ef2aSThomas Huth default: 6019fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6020fcf5ef2aSThomas Huth break; 6021fcf5ef2aSThomas Huth } 6022fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6023fcf5ef2aSThomas Huth } 6024fcf5ef2aSThomas Huth 6025fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6026fcf5ef2aSThomas Huth 6027fcf5ef2aSThomas Huth /* tlbre */ 6028fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6029fcf5ef2aSThomas Huth { 6030fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6031fcf5ef2aSThomas Huth GEN_PRIV; 6032fcf5ef2aSThomas Huth #else 6033fcf5ef2aSThomas Huth CHK_SV; 6034fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6035fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6036fcf5ef2aSThomas Huth } 6037fcf5ef2aSThomas Huth 6038fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6039fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6040fcf5ef2aSThomas Huth { 6041fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6042fcf5ef2aSThomas Huth GEN_PRIV; 6043fcf5ef2aSThomas Huth #else 6044fcf5ef2aSThomas Huth TCGv t0; 6045fcf5ef2aSThomas Huth 6046fcf5ef2aSThomas Huth CHK_SV; 6047fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6048fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6049fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6050fcf5ef2aSThomas Huth } else { 6051fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6052fcf5ef2aSThomas Huth } 6053fcf5ef2aSThomas Huth 6054fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6055fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6056fcf5ef2aSThomas Huth tcg_temp_free(t0); 6057fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6058fcf5ef2aSThomas Huth } 6059fcf5ef2aSThomas Huth 6060fcf5ef2aSThomas Huth /* tlbwe */ 6061fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6062fcf5ef2aSThomas Huth { 6063fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6064fcf5ef2aSThomas Huth GEN_PRIV; 6065fcf5ef2aSThomas Huth #else 6066fcf5ef2aSThomas Huth CHK_SV; 6067fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6068fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6069fcf5ef2aSThomas Huth } 6070fcf5ef2aSThomas Huth 6071fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6072fcf5ef2aSThomas Huth { 6073fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6074fcf5ef2aSThomas Huth GEN_PRIV; 6075fcf5ef2aSThomas Huth #else 6076fcf5ef2aSThomas Huth TCGv t0; 6077fcf5ef2aSThomas Huth 6078fcf5ef2aSThomas Huth CHK_SV; 6079fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6080fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6081fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6082fcf5ef2aSThomas Huth tcg_temp_free(t0); 6083fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6084fcf5ef2aSThomas Huth } 6085fcf5ef2aSThomas Huth 6086fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6087fcf5ef2aSThomas Huth { 6088fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6089fcf5ef2aSThomas Huth GEN_PRIV; 6090fcf5ef2aSThomas Huth #else 6091fcf5ef2aSThomas Huth TCGv t0; 6092fcf5ef2aSThomas Huth 6093fcf5ef2aSThomas Huth CHK_SV; 6094fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6095fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6096fcf5ef2aSThomas Huth 6097fcf5ef2aSThomas Huth switch((ctx->opcode >> 21) & 0x3) { 6098fcf5ef2aSThomas Huth case 0: 6099fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6100fcf5ef2aSThomas Huth break; 6101fcf5ef2aSThomas Huth case 1: 6102fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6103fcf5ef2aSThomas Huth break; 6104fcf5ef2aSThomas Huth case 3: 6105fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6106fcf5ef2aSThomas Huth break; 6107fcf5ef2aSThomas Huth default: 6108fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6109fcf5ef2aSThomas Huth break; 6110fcf5ef2aSThomas Huth } 6111fcf5ef2aSThomas Huth 6112fcf5ef2aSThomas Huth tcg_temp_free(t0); 6113fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6114fcf5ef2aSThomas Huth } 6115fcf5ef2aSThomas Huth 6116fcf5ef2aSThomas Huth 6117fcf5ef2aSThomas Huth /* wrtee */ 6118fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6119fcf5ef2aSThomas Huth { 6120fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6121fcf5ef2aSThomas Huth GEN_PRIV; 6122fcf5ef2aSThomas Huth #else 6123fcf5ef2aSThomas Huth TCGv t0; 6124fcf5ef2aSThomas Huth 6125fcf5ef2aSThomas Huth CHK_SV; 6126fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6127fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6128fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6129fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6130fcf5ef2aSThomas Huth tcg_temp_free(t0); 6131fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception 6132fcf5ef2aSThomas Huth * if we just set msr_ee to 1 6133fcf5ef2aSThomas Huth */ 6134fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6135fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6136fcf5ef2aSThomas Huth } 6137fcf5ef2aSThomas Huth 6138fcf5ef2aSThomas Huth /* wrteei */ 6139fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6140fcf5ef2aSThomas Huth { 6141fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6142fcf5ef2aSThomas Huth GEN_PRIV; 6143fcf5ef2aSThomas Huth #else 6144fcf5ef2aSThomas Huth CHK_SV; 6145fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6146fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6147fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6148fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6149fcf5ef2aSThomas Huth } else { 6150fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6151fcf5ef2aSThomas Huth } 6152fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6153fcf5ef2aSThomas Huth } 6154fcf5ef2aSThomas Huth 6155fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6156fcf5ef2aSThomas Huth 6157fcf5ef2aSThomas Huth /* dlmzb */ 6158fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6159fcf5ef2aSThomas Huth { 6160fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6161fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6162fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6163fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6164fcf5ef2aSThomas Huth } 6165fcf5ef2aSThomas Huth 6166fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6167fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6168fcf5ef2aSThomas Huth { 6169fcf5ef2aSThomas Huth /* interpreted as no-op */ 6170fcf5ef2aSThomas Huth } 6171fcf5ef2aSThomas Huth 6172fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6173fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6174fcf5ef2aSThomas Huth { 6175fcf5ef2aSThomas Huth /* interpreted as no-op */ 6176fcf5ef2aSThomas Huth } 6177fcf5ef2aSThomas Huth 6178fcf5ef2aSThomas Huth /* icbt */ 6179fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6180fcf5ef2aSThomas Huth { 6181fcf5ef2aSThomas Huth /* interpreted as no-op */ 6182fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6183fcf5ef2aSThomas Huth * but does not generate any exception 6184fcf5ef2aSThomas Huth */ 6185fcf5ef2aSThomas Huth } 6186fcf5ef2aSThomas Huth 6187fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6188fcf5ef2aSThomas Huth 6189fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6190fcf5ef2aSThomas Huth { 6191fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6192fcf5ef2aSThomas Huth GEN_PRIV; 6193fcf5ef2aSThomas Huth #else 6194fcf5ef2aSThomas Huth CHK_SV; 6195fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 6196fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6197fcf5ef2aSThomas Huth } 6198fcf5ef2aSThomas Huth 6199fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6200fcf5ef2aSThomas Huth { 6201fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6202fcf5ef2aSThomas Huth GEN_PRIV; 6203fcf5ef2aSThomas Huth #else 6204fcf5ef2aSThomas Huth CHK_SV; 6205fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 6206fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6207fcf5ef2aSThomas Huth } 6208fcf5ef2aSThomas Huth 6209fcf5ef2aSThomas Huth 6210fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6211fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6212fcf5ef2aSThomas Huth { 6213fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6214fcf5ef2aSThomas Huth 6215fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6216fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6217fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6218fcf5ef2aSThomas Huth } 6219fcf5ef2aSThomas Huth 6220fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6221fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6222fcf5ef2aSThomas Huth { 6223fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6224fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6225fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6226fcf5ef2aSThomas Huth 6227fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6228fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6229fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6230fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6231fcf5ef2aSThomas Huth } else { 6232fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6233fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6234fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6235fcf5ef2aSThomas Huth } 6236fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6237fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6238fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6239fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6240fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6241fcf5ef2aSThomas Huth } 6242fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6243fcf5ef2aSThomas Huth 6244fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6245fcf5ef2aSThomas Huth { 6246fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6247fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6248fcf5ef2aSThomas Huth return; 6249fcf5ef2aSThomas Huth } 6250fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6251fcf5ef2aSThomas Huth } 6252fcf5ef2aSThomas Huth 6253fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6254fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6255fcf5ef2aSThomas Huth { \ 6256fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6257fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6258fcf5ef2aSThomas Huth return; \ 6259fcf5ef2aSThomas Huth } \ 6260fcf5ef2aSThomas Huth /* Because tbegin always fails in QEMU, these user \ 6261fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6262fcf5ef2aSThomas Huth * \ 6263fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6264fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6265fcf5ef2aSThomas Huth */ \ 6266fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6267fcf5ef2aSThomas Huth } 6268fcf5ef2aSThomas Huth 6269fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6270fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6271fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6272fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6273fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6274fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6275fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6276b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6277b8b4576eSSuraj Jitindar Singh { 6278b8b4576eSSuraj Jitindar Singh // Do Nothing 6279b8b4576eSSuraj Jitindar Singh } 6280fcf5ef2aSThomas Huth 628180b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 628280b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 628380b8c1eeSNikunj A Dadhania { \ 628480b8c1eeSNikunj A Dadhania /* Generate invalid exception until \ 628580b8c1eeSNikunj A Dadhania * we have an implementation of the copy \ 628680b8c1eeSNikunj A Dadhania * paste facility \ 628780b8c1eeSNikunj A Dadhania */ \ 628880b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 628980b8c1eeSNikunj A Dadhania } 629080b8c1eeSNikunj A Dadhania 629180b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 629280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 629380b8c1eeSNikunj A Dadhania 6294fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6295fcf5ef2aSThomas Huth { 6296fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6297fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6298fcf5ef2aSThomas Huth return; 6299fcf5ef2aSThomas Huth } 6300fcf5ef2aSThomas Huth /* Because tbegin always fails, the tcheck implementation 6301fcf5ef2aSThomas Huth * is simple: 6302fcf5ef2aSThomas Huth * 6303fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6304fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6305fcf5ef2aSThomas Huth */ 6306fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6307fcf5ef2aSThomas Huth } 6308fcf5ef2aSThomas Huth 6309fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6310fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6311fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6312fcf5ef2aSThomas Huth { \ 6313fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6314fcf5ef2aSThomas Huth } 6315fcf5ef2aSThomas Huth 6316fcf5ef2aSThomas Huth #else 6317fcf5ef2aSThomas Huth 6318fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6319fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6320fcf5ef2aSThomas Huth { \ 6321fcf5ef2aSThomas Huth CHK_SV; \ 6322fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6323fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6324fcf5ef2aSThomas Huth return; \ 6325fcf5ef2aSThomas Huth } \ 6326fcf5ef2aSThomas Huth /* Because tbegin always fails, the implementation is \ 6327fcf5ef2aSThomas Huth * simple: \ 6328fcf5ef2aSThomas Huth * \ 6329fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6330fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6331fcf5ef2aSThomas Huth */ \ 6332fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6333fcf5ef2aSThomas Huth } 6334fcf5ef2aSThomas Huth 6335fcf5ef2aSThomas Huth #endif 6336fcf5ef2aSThomas Huth 6337fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6338fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6339fcf5ef2aSThomas Huth 6340fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6341fcf5ef2aSThomas Huth 6342fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6343fcf5ef2aSThomas Huth 6344fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6345fcf5ef2aSThomas Huth 6346fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6347fcf5ef2aSThomas Huth 6348fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6349fcf5ef2aSThomas Huth 63505cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 63515cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 63525cb091a4SNikunj A Dadhania { 63535cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 63545cb091a4SNikunj A Dadhania case 0: /* lfdp */ 63555cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 63565cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 63575cb091a4SNikunj A Dadhania } 63585cb091a4SNikunj A Dadhania break; 63595cb091a4SNikunj A Dadhania case 2: /* lxsd */ 63605cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 63615cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 63625cb091a4SNikunj A Dadhania } 63635cb091a4SNikunj A Dadhania break; 63645cb091a4SNikunj A Dadhania case 3: /* lxssp */ 63655cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 63665cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 63675cb091a4SNikunj A Dadhania } 63685cb091a4SNikunj A Dadhania break; 63695cb091a4SNikunj A Dadhania } 63705cb091a4SNikunj A Dadhania return gen_invalid(ctx); 63715cb091a4SNikunj A Dadhania } 63725cb091a4SNikunj A Dadhania 6373d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6374e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6375e3001664SNikunj A Dadhania { 6376e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6377e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6378e3001664SNikunj A Dadhania case 1: /* lxv */ 6379d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6380d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6381d59ba583SNikunj A Dadhania } 6382e3001664SNikunj A Dadhania break; 6383e3001664SNikunj A Dadhania case 5: /* stxv */ 6384d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6385d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6386d59ba583SNikunj A Dadhania } 6387e3001664SNikunj A Dadhania break; 6388e3001664SNikunj A Dadhania } 6389e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6390e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6391e3001664SNikunj A Dadhania case 0: /* stfdp */ 6392e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6393e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6394e3001664SNikunj A Dadhania } 6395e3001664SNikunj A Dadhania break; 6396e3001664SNikunj A Dadhania case 2: /* stxsd */ 6397e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6398e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6399e3001664SNikunj A Dadhania } 6400e3001664SNikunj A Dadhania break; 6401e3001664SNikunj A Dadhania case 3: /* stxssp */ 6402e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6403e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6404e3001664SNikunj A Dadhania } 6405e3001664SNikunj A Dadhania break; 6406e3001664SNikunj A Dadhania } 6407e3001664SNikunj A Dadhania } 6408e3001664SNikunj A Dadhania return gen_invalid(ctx); 6409e3001664SNikunj A Dadhania } 6410e3001664SNikunj A Dadhania 6411fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6412fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6413fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6414fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6415fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6416fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6417fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6418fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6419fcf5ef2aSThomas Huth #endif 6420fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6421fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6422fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6423fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6424fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6425fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6426fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6427fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6428fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6429fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6430fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6431fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6432fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6433fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6434fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6435fcf5ef2aSThomas Huth #endif 6436fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6437fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6438fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6439fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6440fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6441fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6442fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 644380b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6444b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 644580b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6446fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6447fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6448fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6449fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6450fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6451fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6452fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6453fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6454fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6455fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6456fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6457fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6458fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6459fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6460fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6461fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6462fcf5ef2aSThomas Huth #endif 6463fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6464fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6465fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6466fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6467fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6468fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6469fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6470fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6471fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6472fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6473fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6474fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6475fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6476fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6477fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6478fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6479fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6480fcf5ef2aSThomas Huth #endif 6481fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6482fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6483fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6484fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6485fcf5ef2aSThomas Huth #endif 64865cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 64875cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6488d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6489e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6490fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6491fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6492fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6493fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6494fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6495fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6496fcf5ef2aSThomas Huth GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), 6497fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6498fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6499fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6500fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6501a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6502a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6503fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6504fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6505fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6506fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6507a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6508a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6509fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6510fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6511fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6512fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6513fcf5ef2aSThomas Huth #endif 6514fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6515fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6516c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6517fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6518fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6519fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6520fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6521fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6522fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6523fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6524fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6525fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6526cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6527fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6528fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6529fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6530fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6531fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6532fcf5ef2aSThomas Huth #endif 6533fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6534fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6535fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6536fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6537fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6538fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6539fcf5ef2aSThomas Huth #endif 6540fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6541fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6542fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6543fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6544fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6545fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6546fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6547fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6548fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6549b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6550fcf5ef2aSThomas Huth #endif 6551fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6552fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6553fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6554fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6555fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6556fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6557fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6558fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6559fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6560fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 6561fcf5ef2aSThomas Huth GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), 6562fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6563fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6564fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6565fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6566fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6567fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6568fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6569fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6570fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6571fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6572fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6573fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6574fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6575fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6576fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6577fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6578fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6579fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6580fcf5ef2aSThomas Huth #endif 6581fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6582fcf5ef2aSThomas Huth /* XXX Those instructions will need to be handled differently for 6583fcf5ef2aSThomas Huth * different ISA versions */ 6584fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6585fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6586c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 6587c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 6588fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6589fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6590fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6591fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6592a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 659362d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6594fcf5ef2aSThomas Huth #endif 6595fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6596fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6597fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6598fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6599fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6600fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6601fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6602fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6603fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6604fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6605fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6606fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6607fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6608fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6609fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6610fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6611fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6612fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6613fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6614fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6615fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6616fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6617fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6618fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6619fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6620fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6621fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6622fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6623fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6624fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6625fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6626fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6627fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6628fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6629fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6630fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6631fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6632fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6633fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6634fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6635fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6636fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6637fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6638fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6639fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6640fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6641fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6642fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6643fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6644fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6645fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6646fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6647fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6648fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6649fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6650fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6651fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6652fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6653fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6654fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6655fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6656fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6657fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6658fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6659fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6660fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6661fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6662fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6663fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6664fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6665fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6666fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6667fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6668fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6669fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6670fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6671fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6672fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6673fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6674fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6675fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6676fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6677fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6678fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6679fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6680fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6681fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6682fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6683fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6684fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6685fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6686fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6687fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6688fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6689fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6690fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6691fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6692fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6693fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6694fcf5ef2aSThomas Huth GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6695fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6696fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6697fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6698fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6699fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6700fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6701fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6702fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6703fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6704fcf5ef2aSThomas Huth PPC2_ISA300), 6705fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6706fcf5ef2aSThomas Huth #endif 6707fcf5ef2aSThomas Huth 6708fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6709fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6710fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6711fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6712fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6713fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6714fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6715fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6716fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6717fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6718fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6719fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6720fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6721fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6722fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6723fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6724fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6725fcf5ef2aSThomas Huth 6726fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6727fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6728fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6729fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6730fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6731fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6732fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6733fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6734fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6735fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6736fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6737fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6738fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6739fcf5ef2aSThomas Huth 6740fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6741fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6742fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6743fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6744fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6745fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6746fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6747fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6748fcf5ef2aSThomas Huth 6749fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6750fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6751fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6752fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6753fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6754fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6755fcf5ef2aSThomas Huth 6756fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6757fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6758fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6759fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6760fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6761fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6762fcf5ef2aSThomas Huth #endif 6763fcf5ef2aSThomas Huth 6764fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6765fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6766fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6767fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6768fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6769fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6770fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6771fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6772fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6773fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6774fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6775fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 6776fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 6777fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 6778fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 6779fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 6780fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 6781fcf5ef2aSThomas Huth 6782fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 6783fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 6784fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 6785fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 6786fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 6787fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 6788fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 6789fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 6790fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 6791fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 6792fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 6793fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 6794fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 6795fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 6796fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6797fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 6798fcf5ef2aSThomas Huth #endif 6799fcf5ef2aSThomas Huth 6800fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6801fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 6802fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 6803fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 6804fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6805fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6806fcf5ef2aSThomas Huth PPC_64B) 6807fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 6808fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 6809fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 6810fcf5ef2aSThomas Huth PPC_64B), \ 6811fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 6812fcf5ef2aSThomas Huth PPC_64B), \ 6813fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 6814fcf5ef2aSThomas Huth PPC_64B) 6815fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 6816fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 6817fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 6818fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 6819fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 6820fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 6821fcf5ef2aSThomas Huth #endif 6822fcf5ef2aSThomas Huth 6823fcf5ef2aSThomas Huth #undef GEN_LD 6824fcf5ef2aSThomas Huth #undef GEN_LDU 6825fcf5ef2aSThomas Huth #undef GEN_LDUX 6826fcf5ef2aSThomas Huth #undef GEN_LDX_E 6827fcf5ef2aSThomas Huth #undef GEN_LDS 6828fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 6829fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6830fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 6831fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 6832fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 6833fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6834fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 6835fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6836fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 6837fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 6838fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 6839fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 6840fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 6841fcf5ef2aSThomas Huth 6842fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 6843fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 6844fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 6845fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 6846fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6847fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 6848fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 6849fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 6850fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 6851fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 6852fcf5ef2aSThomas Huth 6853fcf5ef2aSThomas Huth /* HV/P7 and later only */ 6854fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 6855fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 6856fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 6857fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 6858fcf5ef2aSThomas Huth #endif 6859fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 6860fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 6861fcf5ef2aSThomas Huth 6862fcf5ef2aSThomas Huth #undef GEN_ST 6863fcf5ef2aSThomas Huth #undef GEN_STU 6864fcf5ef2aSThomas Huth #undef GEN_STUX 6865fcf5ef2aSThomas Huth #undef GEN_STX_E 6866fcf5ef2aSThomas Huth #undef GEN_STS 6867fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 6868fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 6869fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 6870fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 6871fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 6872fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 6873fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 6874fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 6875fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 6876fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 6877fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 6878fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 6879fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 6880fcf5ef2aSThomas Huth 6881fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 6882fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 6883fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 6884fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6885fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 6886fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 6887fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 6888fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 6889fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 6890fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 6891fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 6892fcf5ef2aSThomas Huth #endif 6893fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 6894fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 6895fcf5ef2aSThomas Huth 6896fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 6897fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 6898fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 6899fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 6900fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 6901fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 6902fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 6903fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 6904fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 6905fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 6906fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 6907fcf5ef2aSThomas Huth 6908fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 6909fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 6910fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 6911fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 6912fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 6913fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 6914fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 6915fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 6916fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 6917fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 6918fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 6919fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 6920fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 6921fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 6922fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 6923fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 6924fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 6925fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 6926fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 6927fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 6928fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 6929fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 6930fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 6931fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 6932fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 6933fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 6934fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 6935fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 6936fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 6937fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 6938fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 6939fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 6940fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 6941fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 6942fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 6943fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 6944fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 6945fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 6946fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 6947fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 6948fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 6949fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 6950fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 6951fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 6952fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 6953fcf5ef2aSThomas Huth 6954fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 6955fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6956fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 6957fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6958fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 6959fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6960fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 6961fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6962fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 6963fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6964fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 6965fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6966fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 6967fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6968fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 6969fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6970fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 6971fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6972fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 6973fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6974fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 6975fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 6976fcf5ef2aSThomas Huth 6977fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 6978fcf5ef2aSThomas Huth 6979fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 6980fcf5ef2aSThomas Huth 6981fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 6982fcf5ef2aSThomas Huth 6983fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 6984fcf5ef2aSThomas Huth 6985fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 6986fcf5ef2aSThomas Huth }; 6987fcf5ef2aSThomas Huth 6988fcf5ef2aSThomas Huth #include "helper_regs.h" 6989fcf5ef2aSThomas Huth #include "translate_init.c" 6990fcf5ef2aSThomas Huth 6991fcf5ef2aSThomas Huth /*****************************************************************************/ 6992fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 6993fcf5ef2aSThomas Huth void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 6994fcf5ef2aSThomas Huth int flags) 6995fcf5ef2aSThomas Huth { 6996fcf5ef2aSThomas Huth #define RGPL 4 6997fcf5ef2aSThomas Huth #define RFPL 4 6998fcf5ef2aSThomas Huth 6999fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7000fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 7001fcf5ef2aSThomas Huth int i; 7002fcf5ef2aSThomas Huth 7003fcf5ef2aSThomas Huth cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7004fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7005fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 7006fcf5ef2aSThomas Huth cs->cpu_index); 7007fcf5ef2aSThomas Huth cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7008fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 7009fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 7010fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 7011fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 7012fcf5ef2aSThomas Huth cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7013fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7014fcf5ef2aSThomas Huth " DECR %08" PRIu32 7015fcf5ef2aSThomas Huth #endif 7016fcf5ef2aSThomas Huth "\n", 7017fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7018fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7019fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 7020fcf5ef2aSThomas Huth #endif 7021fcf5ef2aSThomas Huth ); 7022fcf5ef2aSThomas Huth #endif 7023fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7024fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == 0) 7025fcf5ef2aSThomas Huth cpu_fprintf(f, "GPR%02d", i); 7026fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7027fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == (RGPL - 1)) 7028fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7029fcf5ef2aSThomas Huth } 7030fcf5ef2aSThomas Huth cpu_fprintf(f, "CR "); 7031fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 7032fcf5ef2aSThomas Huth cpu_fprintf(f, "%01x", env->crf[i]); 7033fcf5ef2aSThomas Huth cpu_fprintf(f, " ["); 7034fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 7035fcf5ef2aSThomas Huth char a = '-'; 7036fcf5ef2aSThomas Huth if (env->crf[i] & 0x08) 7037fcf5ef2aSThomas Huth a = 'L'; 7038fcf5ef2aSThomas Huth else if (env->crf[i] & 0x04) 7039fcf5ef2aSThomas Huth a = 'G'; 7040fcf5ef2aSThomas Huth else if (env->crf[i] & 0x02) 7041fcf5ef2aSThomas Huth a = 'E'; 7042fcf5ef2aSThomas Huth cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7043fcf5ef2aSThomas Huth } 7044fcf5ef2aSThomas Huth cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7045fcf5ef2aSThomas Huth env->reserve_addr); 7046fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7047fcf5ef2aSThomas Huth if ((i & (RFPL - 1)) == 0) 7048fcf5ef2aSThomas Huth cpu_fprintf(f, "FPR%02d", i); 7049fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 7050fcf5ef2aSThomas Huth if ((i & (RFPL - 1)) == (RFPL - 1)) 7051fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7052fcf5ef2aSThomas Huth } 7053fcf5ef2aSThomas Huth cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7054fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7055fcf5ef2aSThomas Huth cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7056fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7057fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7058fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7059fcf5ef2aSThomas Huth 7060fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7061fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7062fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7063fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7064fcf5ef2aSThomas Huth 7065fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7066fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7067fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7068fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7069fcf5ef2aSThomas Huth 7070fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7071fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7072fcf5ef2aSThomas Huth env->excp_model == POWERPC_EXCP_POWER8) { 7073fcf5ef2aSThomas Huth cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7074fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7075fcf5ef2aSThomas Huth } 7076fcf5ef2aSThomas Huth #endif 7077fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 7078fcf5ef2aSThomas Huth cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7079fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7080fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7081fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7082fcf5ef2aSThomas Huth 7083fcf5ef2aSThomas Huth cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7084fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7085fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7086fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7087fcf5ef2aSThomas Huth 7088fcf5ef2aSThomas Huth cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7089fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7090fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7091fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7092fcf5ef2aSThomas Huth 7093fcf5ef2aSThomas Huth cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7094fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7095fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7096fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7097fcf5ef2aSThomas Huth 7098fcf5ef2aSThomas Huth /* FSL-specific */ 7099fcf5ef2aSThomas Huth cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7100fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7101fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7102fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7103fcf5ef2aSThomas Huth 7104fcf5ef2aSThomas Huth /* 7105fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7106fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7107fcf5ef2aSThomas Huth */ 7108fcf5ef2aSThomas Huth } 7109fcf5ef2aSThomas Huth 7110fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7111fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 7112fcf5ef2aSThomas Huth cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7113fcf5ef2aSThomas Huth } 7114fcf5ef2aSThomas Huth #endif 7115fcf5ef2aSThomas Huth 7116d801a61eSSuraj Jitindar Singh if (env->spr_cb[SPR_LPCR].name) 7117d801a61eSSuraj Jitindar Singh cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7118d801a61eSSuraj Jitindar Singh 7119ec975e83SSam Bobroff switch (POWERPC_MMU_VER(env->mmu_model)) { 7120fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7121fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7122fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7123fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7124fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7125ec975e83SSam Bobroff case POWERPC_MMU_VER_64B: 7126ec975e83SSam Bobroff case POWERPC_MMU_VER_2_03: 7127ec975e83SSam Bobroff case POWERPC_MMU_VER_2_06: 7128ec975e83SSam Bobroff case POWERPC_MMU_VER_2_07: 7129ec975e83SSam Bobroff case POWERPC_MMU_VER_3_00: 7130fcf5ef2aSThomas Huth #endif 71314f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 71324f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 71334f4f28ffSSuraj Jitindar Singh } 71344f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7135fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7136fcf5ef2aSThomas Huth break; 7137fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 7138fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7139fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7140fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7141fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7142fcf5ef2aSThomas Huth 7143fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7144fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7145fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7146fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7147fcf5ef2aSThomas Huth 7148fcf5ef2aSThomas Huth cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7149fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7150fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7151fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7152fcf5ef2aSThomas Huth break; 7153fcf5ef2aSThomas Huth default: 7154fcf5ef2aSThomas Huth break; 7155fcf5ef2aSThomas Huth } 7156fcf5ef2aSThomas Huth #endif 7157fcf5ef2aSThomas Huth 7158fcf5ef2aSThomas Huth #undef RGPL 7159fcf5ef2aSThomas Huth #undef RFPL 7160fcf5ef2aSThomas Huth } 7161fcf5ef2aSThomas Huth 7162fcf5ef2aSThomas Huth void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7163fcf5ef2aSThomas Huth fprintf_function cpu_fprintf, int flags) 7164fcf5ef2aSThomas Huth { 7165fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7166fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7167fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7168fcf5ef2aSThomas Huth int op1, op2, op3; 7169fcf5ef2aSThomas Huth 7170fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7171fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7172fcf5ef2aSThomas Huth handler = t1[op1]; 7173fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7174fcf5ef2aSThomas Huth t2 = ind_table(handler); 7175fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7176fcf5ef2aSThomas Huth handler = t2[op2]; 7177fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7178fcf5ef2aSThomas Huth t3 = ind_table(handler); 7179fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7180fcf5ef2aSThomas Huth handler = t3[op3]; 7181fcf5ef2aSThomas Huth if (handler->count == 0) 7182fcf5ef2aSThomas Huth continue; 7183fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7184fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7185fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7186fcf5ef2aSThomas Huth handler->oname, 7187fcf5ef2aSThomas Huth handler->count, handler->count); 7188fcf5ef2aSThomas Huth } 7189fcf5ef2aSThomas Huth } else { 7190fcf5ef2aSThomas Huth if (handler->count == 0) 7191fcf5ef2aSThomas Huth continue; 7192fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7193fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7194fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7195fcf5ef2aSThomas Huth handler->count, handler->count); 7196fcf5ef2aSThomas Huth } 7197fcf5ef2aSThomas Huth } 7198fcf5ef2aSThomas Huth } else { 7199fcf5ef2aSThomas Huth if (handler->count == 0) 7200fcf5ef2aSThomas Huth continue; 7201fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7202fcf5ef2aSThomas Huth " %" PRId64 "\n", 7203fcf5ef2aSThomas Huth op1, op1, handler->oname, 7204fcf5ef2aSThomas Huth handler->count, handler->count); 7205fcf5ef2aSThomas Huth } 7206fcf5ef2aSThomas Huth } 7207fcf5ef2aSThomas Huth #endif 7208fcf5ef2aSThomas Huth } 7209fcf5ef2aSThomas Huth 7210fcf5ef2aSThomas Huth /*****************************************************************************/ 72119c489ea6SLluís Vilanova void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 7212fcf5ef2aSThomas Huth { 72139c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 7214fcf5ef2aSThomas Huth DisasContext ctx, *ctxp = &ctx; 7215fcf5ef2aSThomas Huth opc_handler_t **table, *handler; 7216fcf5ef2aSThomas Huth target_ulong pc_start; 7217fcf5ef2aSThomas Huth int num_insns; 7218fcf5ef2aSThomas Huth int max_insns; 7219fcf5ef2aSThomas Huth 7220fcf5ef2aSThomas Huth pc_start = tb->pc; 7221fcf5ef2aSThomas Huth ctx.nip = pc_start; 7222fcf5ef2aSThomas Huth ctx.tb = tb; 7223fcf5ef2aSThomas Huth ctx.exception = POWERPC_EXCP_NONE; 7224fcf5ef2aSThomas Huth ctx.spr_cb = env->spr_cb; 7225fcf5ef2aSThomas Huth ctx.pr = msr_pr; 7226fcf5ef2aSThomas Huth ctx.mem_idx = env->dmmu_idx; 7227fcf5ef2aSThomas Huth ctx.dr = msr_dr; 7228fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7229fcf5ef2aSThomas Huth ctx.hv = msr_hv || !env->has_hv_mode; 7230fcf5ef2aSThomas Huth #endif 7231fcf5ef2aSThomas Huth ctx.insns_flags = env->insns_flags; 7232fcf5ef2aSThomas Huth ctx.insns_flags2 = env->insns_flags2; 7233fcf5ef2aSThomas Huth ctx.access_type = -1; 7234fcf5ef2aSThomas Huth ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7235fcf5ef2aSThomas Huth ctx.le_mode = !!(env->hflags & (1 << MSR_LE)); 7236fcf5ef2aSThomas Huth ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; 7237fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7238fcf5ef2aSThomas Huth ctx.sf_mode = msr_is_64bit(env, env->msr); 7239fcf5ef2aSThomas Huth ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7240fcf5ef2aSThomas Huth #endif 7241fcf5ef2aSThomas Huth if (env->mmu_model == POWERPC_MMU_32B || 7242fcf5ef2aSThomas Huth env->mmu_model == POWERPC_MMU_601 || 7243fcf5ef2aSThomas Huth (env->mmu_model & POWERPC_MMU_64B)) 7244fcf5ef2aSThomas Huth ctx.lazy_tlb_flush = true; 7245fcf5ef2aSThomas Huth 7246fcf5ef2aSThomas Huth ctx.fpu_enabled = !!msr_fp; 7247fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7248fcf5ef2aSThomas Huth ctx.spe_enabled = !!msr_spe; 7249fcf5ef2aSThomas Huth else 7250fcf5ef2aSThomas Huth ctx.spe_enabled = false; 7251fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7252fcf5ef2aSThomas Huth ctx.altivec_enabled = !!msr_vr; 7253fcf5ef2aSThomas Huth else 7254fcf5ef2aSThomas Huth ctx.altivec_enabled = false; 7255fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7256fcf5ef2aSThomas Huth ctx.vsx_enabled = !!msr_vsx; 7257fcf5ef2aSThomas Huth } else { 7258fcf5ef2aSThomas Huth ctx.vsx_enabled = false; 7259fcf5ef2aSThomas Huth } 7260fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7261fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7262fcf5ef2aSThomas Huth ctx.tm_enabled = !!msr_tm; 7263fcf5ef2aSThomas Huth } else { 7264fcf5ef2aSThomas Huth ctx.tm_enabled = false; 7265fcf5ef2aSThomas Huth } 7266fcf5ef2aSThomas Huth #endif 7267c6fd28fdSSuraj Jitindar Singh ctx.gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7268fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7269fcf5ef2aSThomas Huth ctx.singlestep_enabled = CPU_SINGLE_STEP; 7270fcf5ef2aSThomas Huth else 7271fcf5ef2aSThomas Huth ctx.singlestep_enabled = 0; 7272fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7273fcf5ef2aSThomas Huth ctx.singlestep_enabled |= CPU_BRANCH_STEP; 7274fcf5ef2aSThomas Huth if (unlikely(cs->singlestep_enabled)) { 7275fcf5ef2aSThomas Huth ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7276fcf5ef2aSThomas Huth } 7277fcf5ef2aSThomas Huth #if defined (DO_SINGLE_STEP) && 0 7278fcf5ef2aSThomas Huth /* Single step trace mode */ 7279fcf5ef2aSThomas Huth msr_se = 1; 7280fcf5ef2aSThomas Huth #endif 7281fcf5ef2aSThomas Huth num_insns = 0; 7282fcf5ef2aSThomas Huth max_insns = tb->cflags & CF_COUNT_MASK; 7283fcf5ef2aSThomas Huth if (max_insns == 0) { 7284fcf5ef2aSThomas Huth max_insns = CF_COUNT_MASK; 7285fcf5ef2aSThomas Huth } 7286fcf5ef2aSThomas Huth if (max_insns > TCG_MAX_INSNS) { 7287fcf5ef2aSThomas Huth max_insns = TCG_MAX_INSNS; 7288fcf5ef2aSThomas Huth } 7289fcf5ef2aSThomas Huth 7290fcf5ef2aSThomas Huth gen_tb_start(tb); 7291fcf5ef2aSThomas Huth tcg_clear_temp_count(); 7292fcf5ef2aSThomas Huth /* Set env in case of segfault during code fetch */ 7293fcf5ef2aSThomas Huth while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) { 7294fcf5ef2aSThomas Huth tcg_gen_insn_start(ctx.nip); 7295fcf5ef2aSThomas Huth num_insns++; 7296fcf5ef2aSThomas Huth 7297fcf5ef2aSThomas Huth if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { 7298fcf5ef2aSThomas Huth gen_debug_exception(ctxp); 7299fcf5ef2aSThomas Huth /* The address covered by the breakpoint must be included in 7300fcf5ef2aSThomas Huth [tb->pc, tb->pc + tb->size) in order to for it to be 7301fcf5ef2aSThomas Huth properly cleared -- thus we increment the PC here so that 7302fcf5ef2aSThomas Huth the logic setting tb->size below does the right thing. */ 7303fcf5ef2aSThomas Huth ctx.nip += 4; 7304fcf5ef2aSThomas Huth break; 7305fcf5ef2aSThomas Huth } 7306fcf5ef2aSThomas Huth 7307fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7308fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7309fcf5ef2aSThomas Huth ctx.nip, ctx.mem_idx, (int)msr_ir); 7310fcf5ef2aSThomas Huth if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) 7311fcf5ef2aSThomas Huth gen_io_start(); 7312fcf5ef2aSThomas Huth if (unlikely(need_byteswap(&ctx))) { 7313fcf5ef2aSThomas Huth ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); 7314fcf5ef2aSThomas Huth } else { 7315fcf5ef2aSThomas Huth ctx.opcode = cpu_ldl_code(env, ctx.nip); 7316fcf5ef2aSThomas Huth } 7317fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7318fcf5ef2aSThomas Huth ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), 7319fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7320fcf5ef2aSThomas Huth ctx.le_mode ? "little" : "big"); 7321fcf5ef2aSThomas Huth ctx.nip += 4; 7322fcf5ef2aSThomas Huth table = env->opcodes; 7323fcf5ef2aSThomas Huth handler = table[opc1(ctx.opcode)]; 7324fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7325fcf5ef2aSThomas Huth table = ind_table(handler); 7326fcf5ef2aSThomas Huth handler = table[opc2(ctx.opcode)]; 7327fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7328fcf5ef2aSThomas Huth table = ind_table(handler); 7329fcf5ef2aSThomas Huth handler = table[opc3(ctx.opcode)]; 7330fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7331fcf5ef2aSThomas Huth table = ind_table(handler); 7332fcf5ef2aSThomas Huth handler = table[opc4(ctx.opcode)]; 7333fcf5ef2aSThomas Huth } 7334fcf5ef2aSThomas Huth } 7335fcf5ef2aSThomas Huth } 7336fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7337fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7338fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7339fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7340fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7341fcf5ef2aSThomas Huth opc1(ctx.opcode), opc2(ctx.opcode), 7342fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7343fcf5ef2aSThomas Huth ctx.opcode, ctx.nip - 4, (int)msr_ir); 7344fcf5ef2aSThomas Huth } else { 7345fcf5ef2aSThomas Huth uint32_t inval; 7346fcf5ef2aSThomas Huth 7347fcf5ef2aSThomas Huth if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { 7348fcf5ef2aSThomas Huth inval = handler->inval2; 7349fcf5ef2aSThomas Huth } else { 7350fcf5ef2aSThomas Huth inval = handler->inval1; 7351fcf5ef2aSThomas Huth } 7352fcf5ef2aSThomas Huth 7353fcf5ef2aSThomas Huth if (unlikely((ctx.opcode & inval) != 0)) { 7354fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7355fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7356fcf5ef2aSThomas Huth TARGET_FMT_lx "\n", ctx.opcode & inval, 7357fcf5ef2aSThomas Huth opc1(ctx.opcode), opc2(ctx.opcode), 7358fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), 7359fcf5ef2aSThomas Huth ctx.opcode, ctx.nip - 4); 7360fcf5ef2aSThomas Huth gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); 7361fcf5ef2aSThomas Huth break; 7362fcf5ef2aSThomas Huth } 7363fcf5ef2aSThomas Huth } 7364fcf5ef2aSThomas Huth (*(handler->handler))(&ctx); 7365fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7366fcf5ef2aSThomas Huth handler->count++; 7367fcf5ef2aSThomas Huth #endif 7368fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7369fcf5ef2aSThomas Huth if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && 7370fcf5ef2aSThomas Huth (ctx.nip <= 0x100 || ctx.nip > 0xF00) && 7371fcf5ef2aSThomas Huth ctx.exception != POWERPC_SYSCALL && 7372fcf5ef2aSThomas Huth ctx.exception != POWERPC_EXCP_TRAP && 7373fcf5ef2aSThomas Huth ctx.exception != POWERPC_EXCP_BRANCH)) { 7374fcf5ef2aSThomas Huth gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); 7375fcf5ef2aSThomas Huth } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || 7376fcf5ef2aSThomas Huth (cs->singlestep_enabled) || 7377fcf5ef2aSThomas Huth singlestep || 7378fcf5ef2aSThomas Huth num_insns >= max_insns)) { 7379fcf5ef2aSThomas Huth /* if we reach a page boundary or are single stepping, stop 7380fcf5ef2aSThomas Huth * generation 7381fcf5ef2aSThomas Huth */ 7382fcf5ef2aSThomas Huth break; 7383fcf5ef2aSThomas Huth } 7384fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7385fcf5ef2aSThomas Huth fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " 7386fcf5ef2aSThomas Huth "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), 7387fcf5ef2aSThomas Huth opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); 7388fcf5ef2aSThomas Huth exit(1); 7389fcf5ef2aSThomas Huth } 7390fcf5ef2aSThomas Huth } 7391fcf5ef2aSThomas Huth if (tb->cflags & CF_LAST_IO) 7392fcf5ef2aSThomas Huth gen_io_end(); 7393fcf5ef2aSThomas Huth if (ctx.exception == POWERPC_EXCP_NONE) { 7394fcf5ef2aSThomas Huth gen_goto_tb(&ctx, 0, ctx.nip); 7395fcf5ef2aSThomas Huth } else if (ctx.exception != POWERPC_EXCP_BRANCH) { 7396fcf5ef2aSThomas Huth if (unlikely(cs->singlestep_enabled)) { 7397fcf5ef2aSThomas Huth gen_debug_exception(ctxp); 7398fcf5ef2aSThomas Huth } 7399fcf5ef2aSThomas Huth /* Generate the return instruction */ 7400fcf5ef2aSThomas Huth tcg_gen_exit_tb(0); 7401fcf5ef2aSThomas Huth } 7402fcf5ef2aSThomas Huth gen_tb_end(tb, num_insns); 7403fcf5ef2aSThomas Huth 7404fcf5ef2aSThomas Huth tb->size = ctx.nip - pc_start; 7405fcf5ef2aSThomas Huth tb->icount = num_insns; 7406fcf5ef2aSThomas Huth 7407fcf5ef2aSThomas Huth #if defined(DEBUG_DISAS) 7408fcf5ef2aSThomas Huth if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 7409fcf5ef2aSThomas Huth && qemu_log_in_addr_range(pc_start)) { 7410fcf5ef2aSThomas Huth int flags; 7411fcf5ef2aSThomas Huth flags = env->bfd_mach; 7412fcf5ef2aSThomas Huth flags |= ctx.le_mode << 16; 7413fcf5ef2aSThomas Huth qemu_log_lock(); 7414fcf5ef2aSThomas Huth qemu_log("IN: %s\n", lookup_symbol(pc_start)); 7415fcf5ef2aSThomas Huth log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); 7416fcf5ef2aSThomas Huth qemu_log("\n"); 7417fcf5ef2aSThomas Huth qemu_log_unlock(); 7418fcf5ef2aSThomas Huth } 7419fcf5ef2aSThomas Huth #endif 7420fcf5ef2aSThomas Huth } 7421fcf5ef2aSThomas Huth 7422fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7423fcf5ef2aSThomas Huth target_ulong *data) 7424fcf5ef2aSThomas Huth { 7425fcf5ef2aSThomas Huth env->nip = data[0]; 7426fcf5ef2aSThomas Huth } 7427