1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * PowerPC emulation for qemu: main translation routines. 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer 5fcf5ef2aSThomas Huth * Copyright (C) 2011 Freescale Semiconductor, Inc. 6fcf5ef2aSThomas Huth * 7fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 8fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 9fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 10fcf5ef2aSThomas Huth * version 2 of the License, or (at your option) any later version. 11fcf5ef2aSThomas Huth * 12fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 13fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 14fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15fcf5ef2aSThomas Huth * Lesser General Public License for more details. 16fcf5ef2aSThomas Huth * 17fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 18fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth 21fcf5ef2aSThomas Huth #include "qemu/osdep.h" 22fcf5ef2aSThomas Huth #include "cpu.h" 23fcf5ef2aSThomas Huth #include "internal.h" 24fcf5ef2aSThomas Huth #include "disas/disas.h" 25fcf5ef2aSThomas Huth #include "exec/exec-all.h" 26fcf5ef2aSThomas Huth #include "tcg-op.h" 27fcf5ef2aSThomas Huth #include "qemu/host-utils.h" 28fcf5ef2aSThomas Huth #include "exec/cpu_ldst.h" 29fcf5ef2aSThomas Huth 30fcf5ef2aSThomas Huth #include "exec/helper-proto.h" 31fcf5ef2aSThomas Huth #include "exec/helper-gen.h" 32fcf5ef2aSThomas Huth 33fcf5ef2aSThomas Huth #include "trace-tcg.h" 34b6bac4bcSEmilio G. Cota #include "exec/translator.h" 35fcf5ef2aSThomas Huth #include "exec/log.h" 36fcf5ef2aSThomas Huth 37fcf5ef2aSThomas Huth 38fcf5ef2aSThomas Huth #define CPU_SINGLE_STEP 0x1 39fcf5ef2aSThomas Huth #define CPU_BRANCH_STEP 0x2 40fcf5ef2aSThomas Huth #define GDBSTUB_SINGLE_STEP 0x4 41fcf5ef2aSThomas Huth 42fcf5ef2aSThomas Huth /* Include definitions for instructions classes and implementations flags */ 43fcf5ef2aSThomas Huth //#define PPC_DEBUG_DISAS 44fcf5ef2aSThomas Huth //#define DO_PPC_STATISTICS 45fcf5ef2aSThomas Huth 46fcf5ef2aSThomas Huth #ifdef PPC_DEBUG_DISAS 47fcf5ef2aSThomas Huth # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 48fcf5ef2aSThomas Huth #else 49fcf5ef2aSThomas Huth # define LOG_DISAS(...) do { } while (0) 50fcf5ef2aSThomas Huth #endif 51fcf5ef2aSThomas Huth /*****************************************************************************/ 52fcf5ef2aSThomas Huth /* Code translation helpers */ 53fcf5ef2aSThomas Huth 54fcf5ef2aSThomas Huth /* global register indexes */ 55fcf5ef2aSThomas Huth static char cpu_reg_names[10*3 + 22*4 /* GPR */ 56fcf5ef2aSThomas Huth + 10*4 + 22*5 /* SPE GPRh */ 57fcf5ef2aSThomas Huth + 10*4 + 22*5 /* FPR */ 58fcf5ef2aSThomas Huth + 2*(10*6 + 22*7) /* AVRh, AVRl */ 59fcf5ef2aSThomas Huth + 10*5 + 22*6 /* VSR */ 60fcf5ef2aSThomas Huth + 8*5 /* CRF */]; 61fcf5ef2aSThomas Huth static TCGv cpu_gpr[32]; 62fcf5ef2aSThomas Huth static TCGv cpu_gprh[32]; 63fcf5ef2aSThomas Huth static TCGv_i64 cpu_fpr[32]; 64fcf5ef2aSThomas Huth static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; 65fcf5ef2aSThomas Huth static TCGv_i64 cpu_vsr[32]; 66fcf5ef2aSThomas Huth static TCGv_i32 cpu_crf[8]; 67fcf5ef2aSThomas Huth static TCGv cpu_nip; 68fcf5ef2aSThomas Huth static TCGv cpu_msr; 69fcf5ef2aSThomas Huth static TCGv cpu_ctr; 70fcf5ef2aSThomas Huth static TCGv cpu_lr; 71fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 72fcf5ef2aSThomas Huth static TCGv cpu_cfar; 73fcf5ef2aSThomas Huth #endif 74dd09c361SNikunj A Dadhania static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; 75fcf5ef2aSThomas Huth static TCGv cpu_reserve; 76253ce7b2SNikunj A Dadhania static TCGv cpu_reserve_val; 77fcf5ef2aSThomas Huth static TCGv cpu_fpscr; 78fcf5ef2aSThomas Huth static TCGv_i32 cpu_access_type; 79fcf5ef2aSThomas Huth 80fcf5ef2aSThomas Huth #include "exec/gen-icount.h" 81fcf5ef2aSThomas Huth 82fcf5ef2aSThomas Huth void ppc_translate_init(void) 83fcf5ef2aSThomas Huth { 84fcf5ef2aSThomas Huth int i; 85fcf5ef2aSThomas Huth char* p; 86fcf5ef2aSThomas Huth size_t cpu_reg_names_size; 87fcf5ef2aSThomas Huth 88fcf5ef2aSThomas Huth p = cpu_reg_names; 89fcf5ef2aSThomas Huth cpu_reg_names_size = sizeof(cpu_reg_names); 90fcf5ef2aSThomas Huth 91fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 92fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "crf%d", i); 93fcf5ef2aSThomas Huth cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, 94fcf5ef2aSThomas Huth offsetof(CPUPPCState, crf[i]), p); 95fcf5ef2aSThomas Huth p += 5; 96fcf5ef2aSThomas Huth cpu_reg_names_size -= 5; 97fcf5ef2aSThomas Huth } 98fcf5ef2aSThomas Huth 99fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 100fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%d", i); 101fcf5ef2aSThomas Huth cpu_gpr[i] = tcg_global_mem_new(cpu_env, 102fcf5ef2aSThomas Huth offsetof(CPUPPCState, gpr[i]), p); 103fcf5ef2aSThomas Huth p += (i < 10) ? 3 : 4; 104fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 3 : 4; 105fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "r%dH", i); 106fcf5ef2aSThomas Huth cpu_gprh[i] = tcg_global_mem_new(cpu_env, 107fcf5ef2aSThomas Huth offsetof(CPUPPCState, gprh[i]), p); 108fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 109fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 110fcf5ef2aSThomas Huth 111fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "fp%d", i); 112fcf5ef2aSThomas Huth cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 113fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpr[i]), p); 114fcf5ef2aSThomas Huth p += (i < 10) ? 4 : 5; 115fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 4 : 5; 116fcf5ef2aSThomas Huth 117fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dH", i); 118fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 119fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 120fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 121fcf5ef2aSThomas Huth #else 122fcf5ef2aSThomas Huth cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, 123fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 124fcf5ef2aSThomas Huth #endif 125fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 126fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 127fcf5ef2aSThomas Huth 128fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "avr%dL", i); 129fcf5ef2aSThomas Huth #ifdef HOST_WORDS_BIGENDIAN 130fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 131fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[1]), p); 132fcf5ef2aSThomas Huth #else 133fcf5ef2aSThomas Huth cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, 134fcf5ef2aSThomas Huth offsetof(CPUPPCState, avr[i].u64[0]), p); 135fcf5ef2aSThomas Huth #endif 136fcf5ef2aSThomas Huth p += (i < 10) ? 6 : 7; 137fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 6 : 7; 138fcf5ef2aSThomas Huth snprintf(p, cpu_reg_names_size, "vsr%d", i); 139fcf5ef2aSThomas Huth cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, 140fcf5ef2aSThomas Huth offsetof(CPUPPCState, vsr[i]), p); 141fcf5ef2aSThomas Huth p += (i < 10) ? 5 : 6; 142fcf5ef2aSThomas Huth cpu_reg_names_size -= (i < 10) ? 5 : 6; 143fcf5ef2aSThomas Huth } 144fcf5ef2aSThomas Huth 145fcf5ef2aSThomas Huth cpu_nip = tcg_global_mem_new(cpu_env, 146fcf5ef2aSThomas Huth offsetof(CPUPPCState, nip), "nip"); 147fcf5ef2aSThomas Huth 148fcf5ef2aSThomas Huth cpu_msr = tcg_global_mem_new(cpu_env, 149fcf5ef2aSThomas Huth offsetof(CPUPPCState, msr), "msr"); 150fcf5ef2aSThomas Huth 151fcf5ef2aSThomas Huth cpu_ctr = tcg_global_mem_new(cpu_env, 152fcf5ef2aSThomas Huth offsetof(CPUPPCState, ctr), "ctr"); 153fcf5ef2aSThomas Huth 154fcf5ef2aSThomas Huth cpu_lr = tcg_global_mem_new(cpu_env, 155fcf5ef2aSThomas Huth offsetof(CPUPPCState, lr), "lr"); 156fcf5ef2aSThomas Huth 157fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 158fcf5ef2aSThomas Huth cpu_cfar = tcg_global_mem_new(cpu_env, 159fcf5ef2aSThomas Huth offsetof(CPUPPCState, cfar), "cfar"); 160fcf5ef2aSThomas Huth #endif 161fcf5ef2aSThomas Huth 162fcf5ef2aSThomas Huth cpu_xer = tcg_global_mem_new(cpu_env, 163fcf5ef2aSThomas Huth offsetof(CPUPPCState, xer), "xer"); 164fcf5ef2aSThomas Huth cpu_so = tcg_global_mem_new(cpu_env, 165fcf5ef2aSThomas Huth offsetof(CPUPPCState, so), "SO"); 166fcf5ef2aSThomas Huth cpu_ov = tcg_global_mem_new(cpu_env, 167fcf5ef2aSThomas Huth offsetof(CPUPPCState, ov), "OV"); 168fcf5ef2aSThomas Huth cpu_ca = tcg_global_mem_new(cpu_env, 169fcf5ef2aSThomas Huth offsetof(CPUPPCState, ca), "CA"); 170dd09c361SNikunj A Dadhania cpu_ov32 = tcg_global_mem_new(cpu_env, 171dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ov32), "OV32"); 172dd09c361SNikunj A Dadhania cpu_ca32 = tcg_global_mem_new(cpu_env, 173dd09c361SNikunj A Dadhania offsetof(CPUPPCState, ca32), "CA32"); 174fcf5ef2aSThomas Huth 175fcf5ef2aSThomas Huth cpu_reserve = tcg_global_mem_new(cpu_env, 176fcf5ef2aSThomas Huth offsetof(CPUPPCState, reserve_addr), 177fcf5ef2aSThomas Huth "reserve_addr"); 178253ce7b2SNikunj A Dadhania cpu_reserve_val = tcg_global_mem_new(cpu_env, 179253ce7b2SNikunj A Dadhania offsetof(CPUPPCState, reserve_val), 180253ce7b2SNikunj A Dadhania "reserve_val"); 181fcf5ef2aSThomas Huth 182fcf5ef2aSThomas Huth cpu_fpscr = tcg_global_mem_new(cpu_env, 183fcf5ef2aSThomas Huth offsetof(CPUPPCState, fpscr), "fpscr"); 184fcf5ef2aSThomas Huth 185fcf5ef2aSThomas Huth cpu_access_type = tcg_global_mem_new_i32(cpu_env, 186fcf5ef2aSThomas Huth offsetof(CPUPPCState, access_type), "access_type"); 187fcf5ef2aSThomas Huth } 188fcf5ef2aSThomas Huth 189fcf5ef2aSThomas Huth /* internal defines */ 190fcf5ef2aSThomas Huth struct DisasContext { 191b6bac4bcSEmilio G. Cota DisasContextBase base; 192fcf5ef2aSThomas Huth uint32_t opcode; 193fcf5ef2aSThomas Huth uint32_t exception; 194fcf5ef2aSThomas Huth /* Routine used to access memory */ 195fcf5ef2aSThomas Huth bool pr, hv, dr, le_mode; 196fcf5ef2aSThomas Huth bool lazy_tlb_flush; 197fcf5ef2aSThomas Huth bool need_access_type; 198fcf5ef2aSThomas Huth int mem_idx; 199fcf5ef2aSThomas Huth int access_type; 200fcf5ef2aSThomas Huth /* Translation flags */ 201fcf5ef2aSThomas Huth TCGMemOp default_tcg_memop_mask; 202fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 203fcf5ef2aSThomas Huth bool sf_mode; 204fcf5ef2aSThomas Huth bool has_cfar; 205fcf5ef2aSThomas Huth #endif 206fcf5ef2aSThomas Huth bool fpu_enabled; 207fcf5ef2aSThomas Huth bool altivec_enabled; 208fcf5ef2aSThomas Huth bool vsx_enabled; 209fcf5ef2aSThomas Huth bool spe_enabled; 210fcf5ef2aSThomas Huth bool tm_enabled; 211c6fd28fdSSuraj Jitindar Singh bool gtse; 212fcf5ef2aSThomas Huth ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ 213fcf5ef2aSThomas Huth int singlestep_enabled; 214*0e3bf489SRoman Kapl uint32_t flags; 215fcf5ef2aSThomas Huth uint64_t insns_flags; 216fcf5ef2aSThomas Huth uint64_t insns_flags2; 217fcf5ef2aSThomas Huth }; 218fcf5ef2aSThomas Huth 219fcf5ef2aSThomas Huth /* Return true iff byteswap is needed in a scalar memop */ 220fcf5ef2aSThomas Huth static inline bool need_byteswap(const DisasContext *ctx) 221fcf5ef2aSThomas Huth { 222fcf5ef2aSThomas Huth #if defined(TARGET_WORDS_BIGENDIAN) 223fcf5ef2aSThomas Huth return ctx->le_mode; 224fcf5ef2aSThomas Huth #else 225fcf5ef2aSThomas Huth return !ctx->le_mode; 226fcf5ef2aSThomas Huth #endif 227fcf5ef2aSThomas Huth } 228fcf5ef2aSThomas Huth 229fcf5ef2aSThomas Huth /* True when active word size < size of target_long. */ 230fcf5ef2aSThomas Huth #ifdef TARGET_PPC64 231fcf5ef2aSThomas Huth # define NARROW_MODE(C) (!(C)->sf_mode) 232fcf5ef2aSThomas Huth #else 233fcf5ef2aSThomas Huth # define NARROW_MODE(C) 0 234fcf5ef2aSThomas Huth #endif 235fcf5ef2aSThomas Huth 236fcf5ef2aSThomas Huth struct opc_handler_t { 237fcf5ef2aSThomas Huth /* invalid bits for instruction 1 (Rc(opcode) == 0) */ 238fcf5ef2aSThomas Huth uint32_t inval1; 239fcf5ef2aSThomas Huth /* invalid bits for instruction 2 (Rc(opcode) == 1) */ 240fcf5ef2aSThomas Huth uint32_t inval2; 241fcf5ef2aSThomas Huth /* instruction type */ 242fcf5ef2aSThomas Huth uint64_t type; 243fcf5ef2aSThomas Huth /* extended instruction type */ 244fcf5ef2aSThomas Huth uint64_t type2; 245fcf5ef2aSThomas Huth /* handler */ 246fcf5ef2aSThomas Huth void (*handler)(DisasContext *ctx); 247fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 248fcf5ef2aSThomas Huth const char *oname; 249fcf5ef2aSThomas Huth #endif 250fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 251fcf5ef2aSThomas Huth uint64_t count; 252fcf5ef2aSThomas Huth #endif 253fcf5ef2aSThomas Huth }; 254fcf5ef2aSThomas Huth 255*0e3bf489SRoman Kapl /* SPR load/store helpers */ 256*0e3bf489SRoman Kapl static inline void gen_load_spr(TCGv t, int reg) 257*0e3bf489SRoman Kapl { 258*0e3bf489SRoman Kapl tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 259*0e3bf489SRoman Kapl } 260*0e3bf489SRoman Kapl 261*0e3bf489SRoman Kapl static inline void gen_store_spr(int reg, TCGv t) 262*0e3bf489SRoman Kapl { 263*0e3bf489SRoman Kapl tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); 264*0e3bf489SRoman Kapl } 265*0e3bf489SRoman Kapl 266fcf5ef2aSThomas Huth static inline void gen_set_access_type(DisasContext *ctx, int access_type) 267fcf5ef2aSThomas Huth { 268fcf5ef2aSThomas Huth if (ctx->need_access_type && ctx->access_type != access_type) { 269fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_access_type, access_type); 270fcf5ef2aSThomas Huth ctx->access_type = access_type; 271fcf5ef2aSThomas Huth } 272fcf5ef2aSThomas Huth } 273fcf5ef2aSThomas Huth 274fcf5ef2aSThomas Huth static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) 275fcf5ef2aSThomas Huth { 276fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 277fcf5ef2aSThomas Huth nip = (uint32_t)nip; 278fcf5ef2aSThomas Huth } 279fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, nip); 280fcf5ef2aSThomas Huth } 281fcf5ef2aSThomas Huth 282fcf5ef2aSThomas Huth static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) 283fcf5ef2aSThomas Huth { 284fcf5ef2aSThomas Huth TCGv_i32 t0, t1; 285fcf5ef2aSThomas Huth 286fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 287fcf5ef2aSThomas Huth * the faulting instruction 288fcf5ef2aSThomas Huth */ 289fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 290b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 291fcf5ef2aSThomas Huth } 292fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 293fcf5ef2aSThomas Huth t1 = tcg_const_i32(error); 294fcf5ef2aSThomas Huth gen_helper_raise_exception_err(cpu_env, t0, t1); 295fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 296fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 297fcf5ef2aSThomas Huth ctx->exception = (excp); 298fcf5ef2aSThomas Huth } 299fcf5ef2aSThomas Huth 300fcf5ef2aSThomas Huth static void gen_exception(DisasContext *ctx, uint32_t excp) 301fcf5ef2aSThomas Huth { 302fcf5ef2aSThomas Huth TCGv_i32 t0; 303fcf5ef2aSThomas Huth 304fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 305fcf5ef2aSThomas Huth * the faulting instruction 306fcf5ef2aSThomas Huth */ 307fcf5ef2aSThomas Huth if (ctx->exception == POWERPC_EXCP_NONE) { 308b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next - 4); 309fcf5ef2aSThomas Huth } 310fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 311fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 312fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 313fcf5ef2aSThomas Huth ctx->exception = (excp); 314fcf5ef2aSThomas Huth } 315fcf5ef2aSThomas Huth 316fcf5ef2aSThomas Huth static void gen_exception_nip(DisasContext *ctx, uint32_t excp, 317fcf5ef2aSThomas Huth target_ulong nip) 318fcf5ef2aSThomas Huth { 319fcf5ef2aSThomas Huth TCGv_i32 t0; 320fcf5ef2aSThomas Huth 321fcf5ef2aSThomas Huth gen_update_nip(ctx, nip); 322fcf5ef2aSThomas Huth t0 = tcg_const_i32(excp); 323fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 324fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 325fcf5ef2aSThomas Huth ctx->exception = (excp); 326fcf5ef2aSThomas Huth } 327fcf5ef2aSThomas Huth 328*0e3bf489SRoman Kapl /* Translates the EXCP_TRACE/BRANCH exceptions used on most PowerPCs to 329*0e3bf489SRoman Kapl * EXCP_DEBUG, if we are running on cores using the debug enable bit (e.g. 330*0e3bf489SRoman Kapl * BookE). 331*0e3bf489SRoman Kapl */ 332*0e3bf489SRoman Kapl static uint32_t gen_prep_dbgex(DisasContext *ctx, uint32_t excp) 333*0e3bf489SRoman Kapl { 334*0e3bf489SRoman Kapl if ((ctx->singlestep_enabled & CPU_SINGLE_STEP) 335*0e3bf489SRoman Kapl && (excp == POWERPC_EXCP_BRANCH)) { 336*0e3bf489SRoman Kapl /* Trace excpt. has priority */ 337*0e3bf489SRoman Kapl excp = POWERPC_EXCP_TRACE; 338*0e3bf489SRoman Kapl } 339*0e3bf489SRoman Kapl if (ctx->flags & POWERPC_FLAG_DE) { 340*0e3bf489SRoman Kapl target_ulong dbsr = 0; 341*0e3bf489SRoman Kapl switch (excp) { 342*0e3bf489SRoman Kapl case POWERPC_EXCP_TRACE: 343*0e3bf489SRoman Kapl dbsr = DBCR0_ICMP; 344*0e3bf489SRoman Kapl break; 345*0e3bf489SRoman Kapl case POWERPC_EXCP_BRANCH: 346*0e3bf489SRoman Kapl dbsr = DBCR0_BRT; 347*0e3bf489SRoman Kapl break; 348*0e3bf489SRoman Kapl } 349*0e3bf489SRoman Kapl TCGv t0 = tcg_temp_new(); 350*0e3bf489SRoman Kapl gen_load_spr(t0, SPR_BOOKE_DBSR); 351*0e3bf489SRoman Kapl tcg_gen_ori_tl(t0, t0, dbsr); 352*0e3bf489SRoman Kapl gen_store_spr(SPR_BOOKE_DBSR, t0); 353*0e3bf489SRoman Kapl tcg_temp_free(t0); 354*0e3bf489SRoman Kapl return POWERPC_EXCP_DEBUG; 355*0e3bf489SRoman Kapl } else { 356*0e3bf489SRoman Kapl return excp; 357*0e3bf489SRoman Kapl } 358*0e3bf489SRoman Kapl } 359*0e3bf489SRoman Kapl 360fcf5ef2aSThomas Huth static void gen_debug_exception(DisasContext *ctx) 361fcf5ef2aSThomas Huth { 362fcf5ef2aSThomas Huth TCGv_i32 t0; 363fcf5ef2aSThomas Huth 364fcf5ef2aSThomas Huth /* These are all synchronous exceptions, we set the PC back to 365fcf5ef2aSThomas Huth * the faulting instruction 366fcf5ef2aSThomas Huth */ 367fcf5ef2aSThomas Huth if ((ctx->exception != POWERPC_EXCP_BRANCH) && 368fcf5ef2aSThomas Huth (ctx->exception != POWERPC_EXCP_SYNC)) { 369b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 370fcf5ef2aSThomas Huth } 371fcf5ef2aSThomas Huth t0 = tcg_const_i32(EXCP_DEBUG); 372fcf5ef2aSThomas Huth gen_helper_raise_exception(cpu_env, t0); 373fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 374fcf5ef2aSThomas Huth } 375fcf5ef2aSThomas Huth 376fcf5ef2aSThomas Huth static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) 377fcf5ef2aSThomas Huth { 378fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 379fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); 380fcf5ef2aSThomas Huth } 381fcf5ef2aSThomas Huth 382fcf5ef2aSThomas Huth static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) 383fcf5ef2aSThomas Huth { 384fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); 385fcf5ef2aSThomas Huth } 386fcf5ef2aSThomas Huth 387fcf5ef2aSThomas Huth static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) 388fcf5ef2aSThomas Huth { 389fcf5ef2aSThomas Huth /* Will be converted to program check if needed */ 390fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); 391fcf5ef2aSThomas Huth } 392fcf5ef2aSThomas Huth 393fcf5ef2aSThomas Huth /* Stop translation */ 394fcf5ef2aSThomas Huth static inline void gen_stop_exception(DisasContext *ctx) 395fcf5ef2aSThomas Huth { 396b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 397fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_STOP; 398fcf5ef2aSThomas Huth } 399fcf5ef2aSThomas Huth 400fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 401fcf5ef2aSThomas Huth /* No need to update nip here, as execution flow will change */ 402fcf5ef2aSThomas Huth static inline void gen_sync_exception(DisasContext *ctx) 403fcf5ef2aSThomas Huth { 404fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_SYNC; 405fcf5ef2aSThomas Huth } 406fcf5ef2aSThomas Huth #endif 407fcf5ef2aSThomas Huth 408fcf5ef2aSThomas Huth #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ 409fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) 410fcf5ef2aSThomas Huth 411fcf5ef2aSThomas Huth #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ 412fcf5ef2aSThomas Huth GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) 413fcf5ef2aSThomas Huth 414fcf5ef2aSThomas Huth #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ 415fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) 416fcf5ef2aSThomas Huth 417fcf5ef2aSThomas Huth #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ 418fcf5ef2aSThomas Huth GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) 419fcf5ef2aSThomas Huth 420fcf5ef2aSThomas Huth #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ 421fcf5ef2aSThomas Huth GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) 422fcf5ef2aSThomas Huth 423fcf5ef2aSThomas Huth #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ 424fcf5ef2aSThomas Huth GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) 425fcf5ef2aSThomas Huth 426fcf5ef2aSThomas Huth typedef struct opcode_t { 427fcf5ef2aSThomas Huth unsigned char opc1, opc2, opc3, opc4; 428fcf5ef2aSThomas Huth #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ 429fcf5ef2aSThomas Huth unsigned char pad[4]; 430fcf5ef2aSThomas Huth #endif 431fcf5ef2aSThomas Huth opc_handler_t handler; 432fcf5ef2aSThomas Huth const char *oname; 433fcf5ef2aSThomas Huth } opcode_t; 434fcf5ef2aSThomas Huth 435fcf5ef2aSThomas Huth /* Helpers for priv. check */ 436fcf5ef2aSThomas Huth #define GEN_PRIV \ 437fcf5ef2aSThomas Huth do { \ 438fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ 439fcf5ef2aSThomas Huth } while (0) 440fcf5ef2aSThomas Huth 441fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 442fcf5ef2aSThomas Huth #define CHK_HV GEN_PRIV 443fcf5ef2aSThomas Huth #define CHK_SV GEN_PRIV 444fcf5ef2aSThomas Huth #define CHK_HVRM GEN_PRIV 445fcf5ef2aSThomas Huth #else 446fcf5ef2aSThomas Huth #define CHK_HV \ 447fcf5ef2aSThomas Huth do { \ 448fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv)) { \ 449fcf5ef2aSThomas Huth GEN_PRIV; \ 450fcf5ef2aSThomas Huth } \ 451fcf5ef2aSThomas Huth } while (0) 452fcf5ef2aSThomas Huth #define CHK_SV \ 453fcf5ef2aSThomas Huth do { \ 454fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { \ 455fcf5ef2aSThomas Huth GEN_PRIV; \ 456fcf5ef2aSThomas Huth } \ 457fcf5ef2aSThomas Huth } while (0) 458fcf5ef2aSThomas Huth #define CHK_HVRM \ 459fcf5ef2aSThomas Huth do { \ 460fcf5ef2aSThomas Huth if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ 461fcf5ef2aSThomas Huth GEN_PRIV; \ 462fcf5ef2aSThomas Huth } \ 463fcf5ef2aSThomas Huth } while (0) 464fcf5ef2aSThomas Huth #endif 465fcf5ef2aSThomas Huth 466fcf5ef2aSThomas Huth #define CHK_NONE 467fcf5ef2aSThomas Huth 468fcf5ef2aSThomas Huth /*****************************************************************************/ 469fcf5ef2aSThomas Huth /* PowerPC instructions table */ 470fcf5ef2aSThomas Huth 471fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 472fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 473fcf5ef2aSThomas Huth { \ 474fcf5ef2aSThomas Huth .opc1 = op1, \ 475fcf5ef2aSThomas Huth .opc2 = op2, \ 476fcf5ef2aSThomas Huth .opc3 = op3, \ 477fcf5ef2aSThomas Huth .opc4 = 0xff, \ 478fcf5ef2aSThomas Huth .handler = { \ 479fcf5ef2aSThomas Huth .inval1 = invl, \ 480fcf5ef2aSThomas Huth .type = _typ, \ 481fcf5ef2aSThomas Huth .type2 = _typ2, \ 482fcf5ef2aSThomas Huth .handler = &gen_##name, \ 483fcf5ef2aSThomas Huth .oname = stringify(name), \ 484fcf5ef2aSThomas Huth }, \ 485fcf5ef2aSThomas Huth .oname = stringify(name), \ 486fcf5ef2aSThomas Huth } 487fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 488fcf5ef2aSThomas Huth { \ 489fcf5ef2aSThomas Huth .opc1 = op1, \ 490fcf5ef2aSThomas Huth .opc2 = op2, \ 491fcf5ef2aSThomas Huth .opc3 = op3, \ 492fcf5ef2aSThomas Huth .opc4 = 0xff, \ 493fcf5ef2aSThomas Huth .handler = { \ 494fcf5ef2aSThomas Huth .inval1 = invl1, \ 495fcf5ef2aSThomas Huth .inval2 = invl2, \ 496fcf5ef2aSThomas Huth .type = _typ, \ 497fcf5ef2aSThomas Huth .type2 = _typ2, \ 498fcf5ef2aSThomas Huth .handler = &gen_##name, \ 499fcf5ef2aSThomas Huth .oname = stringify(name), \ 500fcf5ef2aSThomas Huth }, \ 501fcf5ef2aSThomas Huth .oname = stringify(name), \ 502fcf5ef2aSThomas Huth } 503fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 504fcf5ef2aSThomas Huth { \ 505fcf5ef2aSThomas Huth .opc1 = op1, \ 506fcf5ef2aSThomas Huth .opc2 = op2, \ 507fcf5ef2aSThomas Huth .opc3 = op3, \ 508fcf5ef2aSThomas Huth .opc4 = 0xff, \ 509fcf5ef2aSThomas Huth .handler = { \ 510fcf5ef2aSThomas Huth .inval1 = invl, \ 511fcf5ef2aSThomas Huth .type = _typ, \ 512fcf5ef2aSThomas Huth .type2 = _typ2, \ 513fcf5ef2aSThomas Huth .handler = &gen_##name, \ 514fcf5ef2aSThomas Huth .oname = onam, \ 515fcf5ef2aSThomas Huth }, \ 516fcf5ef2aSThomas Huth .oname = onam, \ 517fcf5ef2aSThomas Huth } 518fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 519fcf5ef2aSThomas Huth { \ 520fcf5ef2aSThomas Huth .opc1 = op1, \ 521fcf5ef2aSThomas Huth .opc2 = op2, \ 522fcf5ef2aSThomas Huth .opc3 = op3, \ 523fcf5ef2aSThomas Huth .opc4 = op4, \ 524fcf5ef2aSThomas Huth .handler = { \ 525fcf5ef2aSThomas Huth .inval1 = invl, \ 526fcf5ef2aSThomas Huth .type = _typ, \ 527fcf5ef2aSThomas Huth .type2 = _typ2, \ 528fcf5ef2aSThomas Huth .handler = &gen_##name, \ 529fcf5ef2aSThomas Huth .oname = stringify(name), \ 530fcf5ef2aSThomas Huth }, \ 531fcf5ef2aSThomas Huth .oname = stringify(name), \ 532fcf5ef2aSThomas Huth } 533fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 534fcf5ef2aSThomas Huth { \ 535fcf5ef2aSThomas Huth .opc1 = op1, \ 536fcf5ef2aSThomas Huth .opc2 = op2, \ 537fcf5ef2aSThomas Huth .opc3 = op3, \ 538fcf5ef2aSThomas Huth .opc4 = op4, \ 539fcf5ef2aSThomas Huth .handler = { \ 540fcf5ef2aSThomas Huth .inval1 = invl, \ 541fcf5ef2aSThomas Huth .type = _typ, \ 542fcf5ef2aSThomas Huth .type2 = _typ2, \ 543fcf5ef2aSThomas Huth .handler = &gen_##name, \ 544fcf5ef2aSThomas Huth .oname = onam, \ 545fcf5ef2aSThomas Huth }, \ 546fcf5ef2aSThomas Huth .oname = onam, \ 547fcf5ef2aSThomas Huth } 548fcf5ef2aSThomas Huth #else 549fcf5ef2aSThomas Huth #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ 550fcf5ef2aSThomas Huth { \ 551fcf5ef2aSThomas Huth .opc1 = op1, \ 552fcf5ef2aSThomas Huth .opc2 = op2, \ 553fcf5ef2aSThomas Huth .opc3 = op3, \ 554fcf5ef2aSThomas Huth .opc4 = 0xff, \ 555fcf5ef2aSThomas Huth .handler = { \ 556fcf5ef2aSThomas Huth .inval1 = invl, \ 557fcf5ef2aSThomas Huth .type = _typ, \ 558fcf5ef2aSThomas Huth .type2 = _typ2, \ 559fcf5ef2aSThomas Huth .handler = &gen_##name, \ 560fcf5ef2aSThomas Huth }, \ 561fcf5ef2aSThomas Huth .oname = stringify(name), \ 562fcf5ef2aSThomas Huth } 563fcf5ef2aSThomas Huth #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ 564fcf5ef2aSThomas Huth { \ 565fcf5ef2aSThomas Huth .opc1 = op1, \ 566fcf5ef2aSThomas Huth .opc2 = op2, \ 567fcf5ef2aSThomas Huth .opc3 = op3, \ 568fcf5ef2aSThomas Huth .opc4 = 0xff, \ 569fcf5ef2aSThomas Huth .handler = { \ 570fcf5ef2aSThomas Huth .inval1 = invl1, \ 571fcf5ef2aSThomas Huth .inval2 = invl2, \ 572fcf5ef2aSThomas Huth .type = _typ, \ 573fcf5ef2aSThomas Huth .type2 = _typ2, \ 574fcf5ef2aSThomas Huth .handler = &gen_##name, \ 575fcf5ef2aSThomas Huth }, \ 576fcf5ef2aSThomas Huth .oname = stringify(name), \ 577fcf5ef2aSThomas Huth } 578fcf5ef2aSThomas Huth #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ 579fcf5ef2aSThomas Huth { \ 580fcf5ef2aSThomas Huth .opc1 = op1, \ 581fcf5ef2aSThomas Huth .opc2 = op2, \ 582fcf5ef2aSThomas Huth .opc3 = op3, \ 583fcf5ef2aSThomas Huth .opc4 = 0xff, \ 584fcf5ef2aSThomas Huth .handler = { \ 585fcf5ef2aSThomas Huth .inval1 = invl, \ 586fcf5ef2aSThomas Huth .type = _typ, \ 587fcf5ef2aSThomas Huth .type2 = _typ2, \ 588fcf5ef2aSThomas Huth .handler = &gen_##name, \ 589fcf5ef2aSThomas Huth }, \ 590fcf5ef2aSThomas Huth .oname = onam, \ 591fcf5ef2aSThomas Huth } 592fcf5ef2aSThomas Huth #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ 593fcf5ef2aSThomas Huth { \ 594fcf5ef2aSThomas Huth .opc1 = op1, \ 595fcf5ef2aSThomas Huth .opc2 = op2, \ 596fcf5ef2aSThomas Huth .opc3 = op3, \ 597fcf5ef2aSThomas Huth .opc4 = op4, \ 598fcf5ef2aSThomas Huth .handler = { \ 599fcf5ef2aSThomas Huth .inval1 = invl, \ 600fcf5ef2aSThomas Huth .type = _typ, \ 601fcf5ef2aSThomas Huth .type2 = _typ2, \ 602fcf5ef2aSThomas Huth .handler = &gen_##name, \ 603fcf5ef2aSThomas Huth }, \ 604fcf5ef2aSThomas Huth .oname = stringify(name), \ 605fcf5ef2aSThomas Huth } 606fcf5ef2aSThomas Huth #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ 607fcf5ef2aSThomas Huth { \ 608fcf5ef2aSThomas Huth .opc1 = op1, \ 609fcf5ef2aSThomas Huth .opc2 = op2, \ 610fcf5ef2aSThomas Huth .opc3 = op3, \ 611fcf5ef2aSThomas Huth .opc4 = op4, \ 612fcf5ef2aSThomas Huth .handler = { \ 613fcf5ef2aSThomas Huth .inval1 = invl, \ 614fcf5ef2aSThomas Huth .type = _typ, \ 615fcf5ef2aSThomas Huth .type2 = _typ2, \ 616fcf5ef2aSThomas Huth .handler = &gen_##name, \ 617fcf5ef2aSThomas Huth }, \ 618fcf5ef2aSThomas Huth .oname = onam, \ 619fcf5ef2aSThomas Huth } 620fcf5ef2aSThomas Huth #endif 621fcf5ef2aSThomas Huth 622fcf5ef2aSThomas Huth /* Invalid instruction */ 623fcf5ef2aSThomas Huth static void gen_invalid(DisasContext *ctx) 624fcf5ef2aSThomas Huth { 625fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 626fcf5ef2aSThomas Huth } 627fcf5ef2aSThomas Huth 628fcf5ef2aSThomas Huth static opc_handler_t invalid_handler = { 629fcf5ef2aSThomas Huth .inval1 = 0xFFFFFFFF, 630fcf5ef2aSThomas Huth .inval2 = 0xFFFFFFFF, 631fcf5ef2aSThomas Huth .type = PPC_NONE, 632fcf5ef2aSThomas Huth .type2 = PPC_NONE, 633fcf5ef2aSThomas Huth .handler = gen_invalid, 634fcf5ef2aSThomas Huth }; 635fcf5ef2aSThomas Huth 636fcf5ef2aSThomas Huth /*** Integer comparison ***/ 637fcf5ef2aSThomas Huth 638fcf5ef2aSThomas Huth static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) 639fcf5ef2aSThomas Huth { 640fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 641b62b3686Spbonzini@redhat.com TCGv t1 = tcg_temp_new(); 642b62b3686Spbonzini@redhat.com TCGv_i32 t = tcg_temp_new_i32(); 643fcf5ef2aSThomas Huth 644b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t0, CRF_EQ); 645b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_LT); 646b62b3686Spbonzini@redhat.com tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0); 647b62b3686Spbonzini@redhat.com tcg_gen_movi_tl(t1, CRF_GT); 648b62b3686Spbonzini@redhat.com tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0); 649b62b3686Spbonzini@redhat.com 650b62b3686Spbonzini@redhat.com tcg_gen_trunc_tl_i32(t, t0); 651fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); 652b62b3686Spbonzini@redhat.com tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); 653fcf5ef2aSThomas Huth 654fcf5ef2aSThomas Huth tcg_temp_free(t0); 655b62b3686Spbonzini@redhat.com tcg_temp_free(t1); 656b62b3686Spbonzini@redhat.com tcg_temp_free_i32(t); 657fcf5ef2aSThomas Huth } 658fcf5ef2aSThomas Huth 659fcf5ef2aSThomas Huth static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) 660fcf5ef2aSThomas Huth { 661fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 662fcf5ef2aSThomas Huth gen_op_cmp(arg0, t0, s, crf); 663fcf5ef2aSThomas Huth tcg_temp_free(t0); 664fcf5ef2aSThomas Huth } 665fcf5ef2aSThomas Huth 666fcf5ef2aSThomas Huth static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) 667fcf5ef2aSThomas Huth { 668fcf5ef2aSThomas Huth TCGv t0, t1; 669fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 670fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 671fcf5ef2aSThomas Huth if (s) { 672fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, arg0); 673fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, arg1); 674fcf5ef2aSThomas Huth } else { 675fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, arg0); 676fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t1, arg1); 677fcf5ef2aSThomas Huth } 678fcf5ef2aSThomas Huth gen_op_cmp(t0, t1, s, crf); 679fcf5ef2aSThomas Huth tcg_temp_free(t1); 680fcf5ef2aSThomas Huth tcg_temp_free(t0); 681fcf5ef2aSThomas Huth } 682fcf5ef2aSThomas Huth 683fcf5ef2aSThomas Huth static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) 684fcf5ef2aSThomas Huth { 685fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(arg1); 686fcf5ef2aSThomas Huth gen_op_cmp32(arg0, t0, s, crf); 687fcf5ef2aSThomas Huth tcg_temp_free(t0); 688fcf5ef2aSThomas Huth } 689fcf5ef2aSThomas Huth 690fcf5ef2aSThomas Huth static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) 691fcf5ef2aSThomas Huth { 692fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 693fcf5ef2aSThomas Huth gen_op_cmpi32(reg, 0, 1, 0); 694fcf5ef2aSThomas Huth } else { 695fcf5ef2aSThomas Huth gen_op_cmpi(reg, 0, 1, 0); 696fcf5ef2aSThomas Huth } 697fcf5ef2aSThomas Huth } 698fcf5ef2aSThomas Huth 699fcf5ef2aSThomas Huth /* cmp */ 700fcf5ef2aSThomas Huth static void gen_cmp(DisasContext *ctx) 701fcf5ef2aSThomas Huth { 702fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 703fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 704fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 705fcf5ef2aSThomas Huth } else { 706fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 707fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 708fcf5ef2aSThomas Huth } 709fcf5ef2aSThomas Huth } 710fcf5ef2aSThomas Huth 711fcf5ef2aSThomas Huth /* cmpi */ 712fcf5ef2aSThomas Huth static void gen_cmpi(DisasContext *ctx) 713fcf5ef2aSThomas Huth { 714fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 715fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 716fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 717fcf5ef2aSThomas Huth } else { 718fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), 719fcf5ef2aSThomas Huth 1, crfD(ctx->opcode)); 720fcf5ef2aSThomas Huth } 721fcf5ef2aSThomas Huth } 722fcf5ef2aSThomas Huth 723fcf5ef2aSThomas Huth /* cmpl */ 724fcf5ef2aSThomas Huth static void gen_cmpl(DisasContext *ctx) 725fcf5ef2aSThomas Huth { 726fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 727fcf5ef2aSThomas Huth gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 728fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 729fcf5ef2aSThomas Huth } else { 730fcf5ef2aSThomas Huth gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 731fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 732fcf5ef2aSThomas Huth } 733fcf5ef2aSThomas Huth } 734fcf5ef2aSThomas Huth 735fcf5ef2aSThomas Huth /* cmpli */ 736fcf5ef2aSThomas Huth static void gen_cmpli(DisasContext *ctx) 737fcf5ef2aSThomas Huth { 738fcf5ef2aSThomas Huth if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { 739fcf5ef2aSThomas Huth gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 740fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 741fcf5ef2aSThomas Huth } else { 742fcf5ef2aSThomas Huth gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), 743fcf5ef2aSThomas Huth 0, crfD(ctx->opcode)); 744fcf5ef2aSThomas Huth } 745fcf5ef2aSThomas Huth } 746fcf5ef2aSThomas Huth 747fcf5ef2aSThomas Huth /* cmprb - range comparison: isupper, isaplha, islower*/ 748fcf5ef2aSThomas Huth static void gen_cmprb(DisasContext *ctx) 749fcf5ef2aSThomas Huth { 750fcf5ef2aSThomas Huth TCGv_i32 src1 = tcg_temp_new_i32(); 751fcf5ef2aSThomas Huth TCGv_i32 src2 = tcg_temp_new_i32(); 752fcf5ef2aSThomas Huth TCGv_i32 src2lo = tcg_temp_new_i32(); 753fcf5ef2aSThomas Huth TCGv_i32 src2hi = tcg_temp_new_i32(); 754fcf5ef2aSThomas Huth TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; 755fcf5ef2aSThomas Huth 756fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); 757fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); 758fcf5ef2aSThomas Huth 759fcf5ef2aSThomas Huth tcg_gen_andi_i32(src1, src1, 0xFF); 760fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 761fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 762fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 763fcf5ef2aSThomas Huth 764fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 765fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 766fcf5ef2aSThomas Huth tcg_gen_and_i32(crf, src2lo, src2hi); 767fcf5ef2aSThomas Huth 768fcf5ef2aSThomas Huth if (ctx->opcode & 0x00200000) { 769fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 770fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2lo, src2); 771fcf5ef2aSThomas Huth tcg_gen_shri_i32(src2, src2, 8); 772fcf5ef2aSThomas Huth tcg_gen_ext8u_i32(src2hi, src2); 773fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); 774fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); 775fcf5ef2aSThomas Huth tcg_gen_and_i32(src2lo, src2lo, src2hi); 776fcf5ef2aSThomas Huth tcg_gen_or_i32(crf, crf, src2lo); 777fcf5ef2aSThomas Huth } 778efa73196SNikunj A Dadhania tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); 779fcf5ef2aSThomas Huth tcg_temp_free_i32(src1); 780fcf5ef2aSThomas Huth tcg_temp_free_i32(src2); 781fcf5ef2aSThomas Huth tcg_temp_free_i32(src2lo); 782fcf5ef2aSThomas Huth tcg_temp_free_i32(src2hi); 783fcf5ef2aSThomas Huth } 784fcf5ef2aSThomas Huth 785fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 786fcf5ef2aSThomas Huth /* cmpeqb */ 787fcf5ef2aSThomas Huth static void gen_cmpeqb(DisasContext *ctx) 788fcf5ef2aSThomas Huth { 789fcf5ef2aSThomas Huth gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 790fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 791fcf5ef2aSThomas Huth } 792fcf5ef2aSThomas Huth #endif 793fcf5ef2aSThomas Huth 794fcf5ef2aSThomas Huth /* isel (PowerPC 2.03 specification) */ 795fcf5ef2aSThomas Huth static void gen_isel(DisasContext *ctx) 796fcf5ef2aSThomas Huth { 797fcf5ef2aSThomas Huth uint32_t bi = rC(ctx->opcode); 798fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 799fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 800fcf5ef2aSThomas Huth TCGv zr; 801fcf5ef2aSThomas Huth 802fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); 803fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, mask); 804fcf5ef2aSThomas Huth 805fcf5ef2aSThomas Huth zr = tcg_const_tl(0); 806fcf5ef2aSThomas Huth tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, 807fcf5ef2aSThomas Huth rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, 808fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 809fcf5ef2aSThomas Huth tcg_temp_free(zr); 810fcf5ef2aSThomas Huth tcg_temp_free(t0); 811fcf5ef2aSThomas Huth } 812fcf5ef2aSThomas Huth 813fcf5ef2aSThomas Huth /* cmpb: PowerPC 2.05 specification */ 814fcf5ef2aSThomas Huth static void gen_cmpb(DisasContext *ctx) 815fcf5ef2aSThomas Huth { 816fcf5ef2aSThomas Huth gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 817fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 818fcf5ef2aSThomas Huth } 819fcf5ef2aSThomas Huth 820fcf5ef2aSThomas Huth /*** Integer arithmetic ***/ 821fcf5ef2aSThomas Huth 822fcf5ef2aSThomas Huth static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, 823fcf5ef2aSThomas Huth TCGv arg1, TCGv arg2, int sub) 824fcf5ef2aSThomas Huth { 825fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 826fcf5ef2aSThomas Huth 827fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ov, arg0, arg2); 828fcf5ef2aSThomas Huth tcg_gen_xor_tl(t0, arg1, arg2); 829fcf5ef2aSThomas Huth if (sub) { 830fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ov, cpu_ov, t0); 831fcf5ef2aSThomas Huth } else { 832fcf5ef2aSThomas Huth tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); 833fcf5ef2aSThomas Huth } 834fcf5ef2aSThomas Huth tcg_temp_free(t0); 835fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 836dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); 837dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 838dc0ad844SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 839fcf5ef2aSThomas Huth } 840dc0ad844SNikunj A Dadhania } else { 841dc0ad844SNikunj A Dadhania if (is_isa300(ctx)) { 842dc0ad844SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); 843dc0ad844SNikunj A Dadhania } 84438a61d34SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); 845dc0ad844SNikunj A Dadhania } 846fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 847fcf5ef2aSThomas Huth } 848fcf5ef2aSThomas Huth 8496b10d008SNikunj A Dadhania static inline void gen_op_arith_compute_ca32(DisasContext *ctx, 8506b10d008SNikunj A Dadhania TCGv res, TCGv arg0, TCGv arg1, 8516b10d008SNikunj A Dadhania int sub) 8526b10d008SNikunj A Dadhania { 8536b10d008SNikunj A Dadhania TCGv t0; 8546b10d008SNikunj A Dadhania 8556b10d008SNikunj A Dadhania if (!is_isa300(ctx)) { 8566b10d008SNikunj A Dadhania return; 8576b10d008SNikunj A Dadhania } 8586b10d008SNikunj A Dadhania 8596b10d008SNikunj A Dadhania t0 = tcg_temp_new(); 86033903d0aSNikunj A Dadhania if (sub) { 86133903d0aSNikunj A Dadhania tcg_gen_eqv_tl(t0, arg0, arg1); 86233903d0aSNikunj A Dadhania } else { 8636b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, arg0, arg1); 86433903d0aSNikunj A Dadhania } 8656b10d008SNikunj A Dadhania tcg_gen_xor_tl(t0, t0, res); 8666b10d008SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, t0, 32, 1); 8676b10d008SNikunj A Dadhania tcg_temp_free(t0); 8686b10d008SNikunj A Dadhania } 8696b10d008SNikunj A Dadhania 870fcf5ef2aSThomas Huth /* Common add function */ 871fcf5ef2aSThomas Huth static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 872fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 873fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 874fcf5ef2aSThomas Huth { 875fcf5ef2aSThomas Huth TCGv t0 = ret; 876fcf5ef2aSThomas Huth 877fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 878fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 879fcf5ef2aSThomas Huth } 880fcf5ef2aSThomas Huth 881fcf5ef2aSThomas Huth if (compute_ca) { 882fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 883fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 884fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 885fcf5ef2aSThomas Huth carry into bit 32. */ 886fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 887fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ 888fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 889fcf5ef2aSThomas Huth if (add_ca) { 890fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 891fcf5ef2aSThomas Huth } 892fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ 893fcf5ef2aSThomas Huth tcg_temp_free(t1); 894e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 8956b10d008SNikunj A Dadhania if (is_isa300(ctx)) { 8966b10d008SNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 8976b10d008SNikunj A Dadhania } 898fcf5ef2aSThomas Huth } else { 899fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 900fcf5ef2aSThomas Huth if (add_ca) { 901fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); 902fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); 903fcf5ef2aSThomas Huth } else { 904fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); 905fcf5ef2aSThomas Huth } 9066b10d008SNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0); 907fcf5ef2aSThomas Huth tcg_temp_free(zero); 908fcf5ef2aSThomas Huth } 909fcf5ef2aSThomas Huth } else { 910fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg1, arg2); 911fcf5ef2aSThomas Huth if (add_ca) { 912fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 913fcf5ef2aSThomas Huth } 914fcf5ef2aSThomas Huth } 915fcf5ef2aSThomas Huth 916fcf5ef2aSThomas Huth if (compute_ov) { 917fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); 918fcf5ef2aSThomas Huth } 919fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 920fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 921fcf5ef2aSThomas Huth } 922fcf5ef2aSThomas Huth 92311f4e8f8SRichard Henderson if (t0 != ret) { 924fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 925fcf5ef2aSThomas Huth tcg_temp_free(t0); 926fcf5ef2aSThomas Huth } 927fcf5ef2aSThomas Huth } 928fcf5ef2aSThomas Huth /* Add functions with two operands */ 929fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 930fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 931fcf5ef2aSThomas Huth { \ 932fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 933fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 934fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 935fcf5ef2aSThomas Huth } 936fcf5ef2aSThomas Huth /* Add functions with one operand and one immediate */ 937fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 938fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 939fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 940fcf5ef2aSThomas Huth { \ 941fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 942fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ 943fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 944fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 945fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 946fcf5ef2aSThomas Huth } 947fcf5ef2aSThomas Huth 948fcf5ef2aSThomas Huth /* add add. addo addo. */ 949fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 950fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 951fcf5ef2aSThomas Huth /* addc addc. addco addco. */ 952fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 953fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 954fcf5ef2aSThomas Huth /* adde adde. addeo addeo. */ 955fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 956fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 957fcf5ef2aSThomas Huth /* addme addme. addmeo addmeo. */ 958fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 959fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 960fcf5ef2aSThomas Huth /* addze addze. addzeo addzeo.*/ 961fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 962fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 963fcf5ef2aSThomas Huth /* addi */ 964fcf5ef2aSThomas Huth static void gen_addi(DisasContext *ctx) 965fcf5ef2aSThomas Huth { 966fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 967fcf5ef2aSThomas Huth 968fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 969fcf5ef2aSThomas Huth /* li case */ 970fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); 971fcf5ef2aSThomas Huth } else { 972fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 973fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm); 974fcf5ef2aSThomas Huth } 975fcf5ef2aSThomas Huth } 976fcf5ef2aSThomas Huth /* addic addic.*/ 977fcf5ef2aSThomas Huth static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) 978fcf5ef2aSThomas Huth { 979fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 980fcf5ef2aSThomas Huth gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 981fcf5ef2aSThomas Huth c, 0, 1, 0, compute_rc0); 982fcf5ef2aSThomas Huth tcg_temp_free(c); 983fcf5ef2aSThomas Huth } 984fcf5ef2aSThomas Huth 985fcf5ef2aSThomas Huth static void gen_addic(DisasContext *ctx) 986fcf5ef2aSThomas Huth { 987fcf5ef2aSThomas Huth gen_op_addic(ctx, 0); 988fcf5ef2aSThomas Huth } 989fcf5ef2aSThomas Huth 990fcf5ef2aSThomas Huth static void gen_addic_(DisasContext *ctx) 991fcf5ef2aSThomas Huth { 992fcf5ef2aSThomas Huth gen_op_addic(ctx, 1); 993fcf5ef2aSThomas Huth } 994fcf5ef2aSThomas Huth 995fcf5ef2aSThomas Huth /* addis */ 996fcf5ef2aSThomas Huth static void gen_addis(DisasContext *ctx) 997fcf5ef2aSThomas Huth { 998fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 999fcf5ef2aSThomas Huth 1000fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 1001fcf5ef2aSThomas Huth /* lis case */ 1002fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); 1003fcf5ef2aSThomas Huth } else { 1004fcf5ef2aSThomas Huth tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], 1005fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], simm << 16); 1006fcf5ef2aSThomas Huth } 1007fcf5ef2aSThomas Huth } 1008fcf5ef2aSThomas Huth 1009fcf5ef2aSThomas Huth /* addpcis */ 1010fcf5ef2aSThomas Huth static void gen_addpcis(DisasContext *ctx) 1011fcf5ef2aSThomas Huth { 1012fcf5ef2aSThomas Huth target_long d = DX(ctx->opcode); 1013fcf5ef2aSThomas Huth 1014b6bac4bcSEmilio G. Cota tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); 1015fcf5ef2aSThomas Huth } 1016fcf5ef2aSThomas Huth 1017fcf5ef2aSThomas Huth static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, 1018fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1019fcf5ef2aSThomas Huth { 1020fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1021fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1022fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1023fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1024fcf5ef2aSThomas Huth 1025fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1026fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1027fcf5ef2aSThomas Huth if (sign) { 1028fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1029fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1030fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1031fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1032fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1033fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1034fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1035fcf5ef2aSThomas Huth tcg_gen_div_i32(t3, t0, t1); 1036fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1037fcf5ef2aSThomas Huth } else { 1038fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); 1039fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1040fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1041fcf5ef2aSThomas Huth tcg_gen_divu_i32(t3, t0, t1); 1042fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1043fcf5ef2aSThomas Huth } 1044fcf5ef2aSThomas Huth if (compute_ov) { 1045fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t2); 1046c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1047c44027ffSNikunj A Dadhania tcg_gen_extu_i32_tl(cpu_ov32, t2); 1048c44027ffSNikunj A Dadhania } 1049fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1050fcf5ef2aSThomas Huth } 1051fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1052fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1053fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1054fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1055fcf5ef2aSThomas Huth 1056fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1057fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1058fcf5ef2aSThomas Huth } 1059fcf5ef2aSThomas Huth /* Div functions */ 1060fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 1061fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1062fcf5ef2aSThomas Huth { \ 1063fcf5ef2aSThomas Huth gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1064fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1065fcf5ef2aSThomas Huth sign, compute_ov); \ 1066fcf5ef2aSThomas Huth } 1067fcf5ef2aSThomas Huth /* divwu divwu. divwuo divwuo. */ 1068fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); 1069fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); 1070fcf5ef2aSThomas Huth /* divw divw. divwo divwo. */ 1071fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); 1072fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); 1073fcf5ef2aSThomas Huth 1074fcf5ef2aSThomas Huth /* div[wd]eu[o][.] */ 1075fcf5ef2aSThomas Huth #define GEN_DIVE(name, hlpr, compute_ov) \ 1076fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 1077fcf5ef2aSThomas Huth { \ 1078fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(compute_ov); \ 1079fcf5ef2aSThomas Huth gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ 1080fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ 1081fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 1082fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { \ 1083fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ 1084fcf5ef2aSThomas Huth } \ 1085fcf5ef2aSThomas Huth } 1086fcf5ef2aSThomas Huth 1087fcf5ef2aSThomas Huth GEN_DIVE(divweu, divweu, 0); 1088fcf5ef2aSThomas Huth GEN_DIVE(divweuo, divweu, 1); 1089fcf5ef2aSThomas Huth GEN_DIVE(divwe, divwe, 0); 1090fcf5ef2aSThomas Huth GEN_DIVE(divweo, divwe, 1); 1091fcf5ef2aSThomas Huth 1092fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1093fcf5ef2aSThomas Huth static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, 1094fcf5ef2aSThomas Huth TCGv arg2, int sign, int compute_ov) 1095fcf5ef2aSThomas Huth { 1096fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1097fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1098fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1099fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1100fcf5ef2aSThomas Huth 1101fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1102fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1103fcf5ef2aSThomas Huth if (sign) { 1104fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1105fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1106fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1107fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1108fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1109fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1110fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1111fcf5ef2aSThomas Huth tcg_gen_div_i64(ret, t0, t1); 1112fcf5ef2aSThomas Huth } else { 1113fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); 1114fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1115fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1116fcf5ef2aSThomas Huth tcg_gen_divu_i64(ret, t0, t1); 1117fcf5ef2aSThomas Huth } 1118fcf5ef2aSThomas Huth if (compute_ov) { 1119fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_ov, t2); 1120c44027ffSNikunj A Dadhania if (is_isa300(ctx)) { 1121c44027ffSNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, t2); 1122c44027ffSNikunj A Dadhania } 1123fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1124fcf5ef2aSThomas Huth } 1125fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1126fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1127fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1128fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1129fcf5ef2aSThomas Huth 1130fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1131fcf5ef2aSThomas Huth gen_set_Rc0(ctx, ret); 1132fcf5ef2aSThomas Huth } 1133fcf5ef2aSThomas Huth 1134fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 1135fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1136fcf5ef2aSThomas Huth { \ 1137fcf5ef2aSThomas Huth gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1138fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1139fcf5ef2aSThomas Huth sign, compute_ov); \ 1140fcf5ef2aSThomas Huth } 1141c44027ffSNikunj A Dadhania /* divdu divdu. divduo divduo. */ 1142fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); 1143fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); 1144c44027ffSNikunj A Dadhania /* divd divd. divdo divdo. */ 1145fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); 1146fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); 1147fcf5ef2aSThomas Huth 1148fcf5ef2aSThomas Huth GEN_DIVE(divdeu, divdeu, 0); 1149fcf5ef2aSThomas Huth GEN_DIVE(divdeuo, divdeu, 1); 1150fcf5ef2aSThomas Huth GEN_DIVE(divde, divde, 0); 1151fcf5ef2aSThomas Huth GEN_DIVE(divdeo, divde, 1); 1152fcf5ef2aSThomas Huth #endif 1153fcf5ef2aSThomas Huth 1154fcf5ef2aSThomas Huth static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, 1155fcf5ef2aSThomas Huth TCGv arg2, int sign) 1156fcf5ef2aSThomas Huth { 1157fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1158fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1159fcf5ef2aSThomas Huth 1160fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, arg1); 1161fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, arg2); 1162fcf5ef2aSThomas Huth if (sign) { 1163fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_temp_new_i32(); 1164fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_temp_new_i32(); 1165fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); 1166fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); 1167fcf5ef2aSThomas Huth tcg_gen_and_i32(t2, t2, t3); 1168fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); 1169fcf5ef2aSThomas Huth tcg_gen_or_i32(t2, t2, t3); 1170fcf5ef2aSThomas Huth tcg_gen_movi_i32(t3, 0); 1171fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); 1172fcf5ef2aSThomas Huth tcg_gen_rem_i32(t3, t0, t1); 1173fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(ret, t3); 1174fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1175fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1176fcf5ef2aSThomas Huth } else { 1177fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(1); 1178fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(0); 1179fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); 1180fcf5ef2aSThomas Huth tcg_gen_remu_i32(t3, t0, t1); 1181fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(ret, t3); 1182fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 1183fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 1184fcf5ef2aSThomas Huth } 1185fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1186fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1187fcf5ef2aSThomas Huth } 1188fcf5ef2aSThomas Huth 1189fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODW(name, opc3, sign) \ 1190fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1191fcf5ef2aSThomas Huth { \ 1192fcf5ef2aSThomas Huth gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ 1193fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1194fcf5ef2aSThomas Huth sign); \ 1195fcf5ef2aSThomas Huth } 1196fcf5ef2aSThomas Huth 1197fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(moduw, 0x08, 0); 1198fcf5ef2aSThomas Huth GEN_INT_ARITH_MODW(modsw, 0x18, 1); 1199fcf5ef2aSThomas Huth 1200fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1201fcf5ef2aSThomas Huth static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, 1202fcf5ef2aSThomas Huth TCGv arg2, int sign) 1203fcf5ef2aSThomas Huth { 1204fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1205fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1206fcf5ef2aSThomas Huth 1207fcf5ef2aSThomas Huth tcg_gen_mov_i64(t0, arg1); 1208fcf5ef2aSThomas Huth tcg_gen_mov_i64(t1, arg2); 1209fcf5ef2aSThomas Huth if (sign) { 1210fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_temp_new_i64(); 1211fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_temp_new_i64(); 1212fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); 1213fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); 1214fcf5ef2aSThomas Huth tcg_gen_and_i64(t2, t2, t3); 1215fcf5ef2aSThomas Huth tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); 1216fcf5ef2aSThomas Huth tcg_gen_or_i64(t2, t2, t3); 1217fcf5ef2aSThomas Huth tcg_gen_movi_i64(t3, 0); 1218fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); 1219fcf5ef2aSThomas Huth tcg_gen_rem_i64(ret, t0, t1); 1220fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1221fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1222fcf5ef2aSThomas Huth } else { 1223fcf5ef2aSThomas Huth TCGv_i64 t2 = tcg_const_i64(1); 1224fcf5ef2aSThomas Huth TCGv_i64 t3 = tcg_const_i64(0); 1225fcf5ef2aSThomas Huth tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); 1226fcf5ef2aSThomas Huth tcg_gen_remu_i64(ret, t0, t1); 1227fcf5ef2aSThomas Huth tcg_temp_free_i64(t2); 1228fcf5ef2aSThomas Huth tcg_temp_free_i64(t3); 1229fcf5ef2aSThomas Huth } 1230fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1231fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1232fcf5ef2aSThomas Huth } 1233fcf5ef2aSThomas Huth 1234fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MODD(name, opc3, sign) \ 1235fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1236fcf5ef2aSThomas Huth { \ 1237fcf5ef2aSThomas Huth gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ 1238fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1239fcf5ef2aSThomas Huth sign); \ 1240fcf5ef2aSThomas Huth } 1241fcf5ef2aSThomas Huth 1242fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modud, 0x08, 0); 1243fcf5ef2aSThomas Huth GEN_INT_ARITH_MODD(modsd, 0x18, 1); 1244fcf5ef2aSThomas Huth #endif 1245fcf5ef2aSThomas Huth 1246fcf5ef2aSThomas Huth /* mulhw mulhw. */ 1247fcf5ef2aSThomas Huth static void gen_mulhw(DisasContext *ctx) 1248fcf5ef2aSThomas Huth { 1249fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1250fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1251fcf5ef2aSThomas Huth 1252fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1253fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1254fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1255fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1256fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1257fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1258fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1259fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1260fcf5ef2aSThomas Huth } 1261fcf5ef2aSThomas Huth 1262fcf5ef2aSThomas Huth /* mulhwu mulhwu. */ 1263fcf5ef2aSThomas Huth static void gen_mulhwu(DisasContext *ctx) 1264fcf5ef2aSThomas Huth { 1265fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1266fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1267fcf5ef2aSThomas Huth 1268fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1269fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1270fcf5ef2aSThomas Huth tcg_gen_mulu2_i32(t0, t1, t0, t1); 1271fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); 1272fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1273fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1274fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1275fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1276fcf5ef2aSThomas Huth } 1277fcf5ef2aSThomas Huth 1278fcf5ef2aSThomas Huth /* mullw mullw. */ 1279fcf5ef2aSThomas Huth static void gen_mullw(DisasContext *ctx) 1280fcf5ef2aSThomas Huth { 1281fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1282fcf5ef2aSThomas Huth TCGv_i64 t0, t1; 1283fcf5ef2aSThomas Huth t0 = tcg_temp_new_i64(); 1284fcf5ef2aSThomas Huth t1 = tcg_temp_new_i64(); 1285fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); 1286fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); 1287fcf5ef2aSThomas Huth tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1288fcf5ef2aSThomas Huth tcg_temp_free(t0); 1289fcf5ef2aSThomas Huth tcg_temp_free(t1); 1290fcf5ef2aSThomas Huth #else 1291fcf5ef2aSThomas Huth tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1292fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1293fcf5ef2aSThomas Huth #endif 1294fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1295fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1296fcf5ef2aSThomas Huth } 1297fcf5ef2aSThomas Huth 1298fcf5ef2aSThomas Huth /* mullwo mullwo. */ 1299fcf5ef2aSThomas Huth static void gen_mullwo(DisasContext *ctx) 1300fcf5ef2aSThomas Huth { 1301fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1302fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1303fcf5ef2aSThomas Huth 1304fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); 1305fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); 1306fcf5ef2aSThomas Huth tcg_gen_muls2_i32(t0, t1, t0, t1); 1307fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1308fcf5ef2aSThomas Huth tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); 1309fcf5ef2aSThomas Huth #else 1310fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); 1311fcf5ef2aSThomas Huth #endif 1312fcf5ef2aSThomas Huth 1313fcf5ef2aSThomas Huth tcg_gen_sari_i32(t0, t0, 31); 1314fcf5ef2aSThomas Huth tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); 1315fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_ov, t0); 131661aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 131761aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 131861aa9a69SNikunj A Dadhania } 1319fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1320fcf5ef2aSThomas Huth 1321fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1322fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1323fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1324fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1325fcf5ef2aSThomas Huth } 1326fcf5ef2aSThomas Huth 1327fcf5ef2aSThomas Huth /* mulli */ 1328fcf5ef2aSThomas Huth static void gen_mulli(DisasContext *ctx) 1329fcf5ef2aSThomas Huth { 1330fcf5ef2aSThomas Huth tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1331fcf5ef2aSThomas Huth SIMM(ctx->opcode)); 1332fcf5ef2aSThomas Huth } 1333fcf5ef2aSThomas Huth 1334fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1335fcf5ef2aSThomas Huth /* mulhd mulhd. */ 1336fcf5ef2aSThomas Huth static void gen_mulhd(DisasContext *ctx) 1337fcf5ef2aSThomas Huth { 1338fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1339fcf5ef2aSThomas Huth tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1340fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1341fcf5ef2aSThomas Huth tcg_temp_free(lo); 1342fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1343fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1344fcf5ef2aSThomas Huth } 1345fcf5ef2aSThomas Huth } 1346fcf5ef2aSThomas Huth 1347fcf5ef2aSThomas Huth /* mulhdu mulhdu. */ 1348fcf5ef2aSThomas Huth static void gen_mulhdu(DisasContext *ctx) 1349fcf5ef2aSThomas Huth { 1350fcf5ef2aSThomas Huth TCGv lo = tcg_temp_new(); 1351fcf5ef2aSThomas Huth tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], 1352fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1353fcf5ef2aSThomas Huth tcg_temp_free(lo); 1354fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1355fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1356fcf5ef2aSThomas Huth } 1357fcf5ef2aSThomas Huth } 1358fcf5ef2aSThomas Huth 1359fcf5ef2aSThomas Huth /* mulld mulld. */ 1360fcf5ef2aSThomas Huth static void gen_mulld(DisasContext *ctx) 1361fcf5ef2aSThomas Huth { 1362fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1363fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1364fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1365fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1366fcf5ef2aSThomas Huth } 1367fcf5ef2aSThomas Huth 1368fcf5ef2aSThomas Huth /* mulldo mulldo. */ 1369fcf5ef2aSThomas Huth static void gen_mulldo(DisasContext *ctx) 1370fcf5ef2aSThomas Huth { 1371fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1372fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 1373fcf5ef2aSThomas Huth 1374fcf5ef2aSThomas Huth tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], 1375fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 1376fcf5ef2aSThomas Huth tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); 1377fcf5ef2aSThomas Huth 1378fcf5ef2aSThomas Huth tcg_gen_sari_i64(t0, t0, 63); 1379fcf5ef2aSThomas Huth tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); 138061aa9a69SNikunj A Dadhania if (is_isa300(ctx)) { 138161aa9a69SNikunj A Dadhania tcg_gen_mov_tl(cpu_ov32, cpu_ov); 138261aa9a69SNikunj A Dadhania } 1383fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); 1384fcf5ef2aSThomas Huth 1385fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1386fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 1387fcf5ef2aSThomas Huth 1388fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1389fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 1390fcf5ef2aSThomas Huth } 1391fcf5ef2aSThomas Huth } 1392fcf5ef2aSThomas Huth #endif 1393fcf5ef2aSThomas Huth 1394fcf5ef2aSThomas Huth /* Common subf function */ 1395fcf5ef2aSThomas Huth static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 1396fcf5ef2aSThomas Huth TCGv arg2, bool add_ca, bool compute_ca, 1397fcf5ef2aSThomas Huth bool compute_ov, bool compute_rc0) 1398fcf5ef2aSThomas Huth { 1399fcf5ef2aSThomas Huth TCGv t0 = ret; 1400fcf5ef2aSThomas Huth 1401fcf5ef2aSThomas Huth if (compute_ca || compute_ov) { 1402fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 1403fcf5ef2aSThomas Huth } 1404fcf5ef2aSThomas Huth 1405fcf5ef2aSThomas Huth if (compute_ca) { 1406fcf5ef2aSThomas Huth /* dest = ~arg1 + arg2 [+ ca]. */ 1407fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 1408fcf5ef2aSThomas Huth /* Caution: a non-obvious corner case of the spec is that we 1409fcf5ef2aSThomas Huth must produce the *entire* 64-bit addition, but produce the 1410fcf5ef2aSThomas Huth carry into bit 32. */ 1411fcf5ef2aSThomas Huth TCGv inv1 = tcg_temp_new(); 1412fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 1413fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1414fcf5ef2aSThomas Huth if (add_ca) { 1415fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, arg2, cpu_ca); 1416fcf5ef2aSThomas Huth } else { 1417fcf5ef2aSThomas Huth tcg_gen_addi_tl(t0, arg2, 1); 1418fcf5ef2aSThomas Huth } 1419fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ 1420fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, inv1); 1421fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1422fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ 1423fcf5ef2aSThomas Huth tcg_temp_free(t1); 1424e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); 142533903d0aSNikunj A Dadhania if (is_isa300(ctx)) { 142633903d0aSNikunj A Dadhania tcg_gen_mov_tl(cpu_ca32, cpu_ca); 142733903d0aSNikunj A Dadhania } 1428fcf5ef2aSThomas Huth } else if (add_ca) { 1429fcf5ef2aSThomas Huth TCGv zero, inv1 = tcg_temp_new(); 1430fcf5ef2aSThomas Huth tcg_gen_not_tl(inv1, arg1); 1431fcf5ef2aSThomas Huth zero = tcg_const_tl(0); 1432fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); 1433fcf5ef2aSThomas Huth tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); 143433903d0aSNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0); 1435fcf5ef2aSThomas Huth tcg_temp_free(zero); 1436fcf5ef2aSThomas Huth tcg_temp_free(inv1); 1437fcf5ef2aSThomas Huth } else { 1438fcf5ef2aSThomas Huth tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); 1439fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 144033903d0aSNikunj A Dadhania gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1); 1441fcf5ef2aSThomas Huth } 1442fcf5ef2aSThomas Huth } else if (add_ca) { 1443fcf5ef2aSThomas Huth /* Since we're ignoring carry-out, we can simplify the 1444fcf5ef2aSThomas Huth standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ 1445fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1446fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_ca); 1447fcf5ef2aSThomas Huth tcg_gen_subi_tl(t0, t0, 1); 1448fcf5ef2aSThomas Huth } else { 1449fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, arg2, arg1); 1450fcf5ef2aSThomas Huth } 1451fcf5ef2aSThomas Huth 1452fcf5ef2aSThomas Huth if (compute_ov) { 1453fcf5ef2aSThomas Huth gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); 1454fcf5ef2aSThomas Huth } 1455fcf5ef2aSThomas Huth if (unlikely(compute_rc0)) { 1456fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 1457fcf5ef2aSThomas Huth } 1458fcf5ef2aSThomas Huth 145911f4e8f8SRichard Henderson if (t0 != ret) { 1460fcf5ef2aSThomas Huth tcg_gen_mov_tl(ret, t0); 1461fcf5ef2aSThomas Huth tcg_temp_free(t0); 1462fcf5ef2aSThomas Huth } 1463fcf5ef2aSThomas Huth } 1464fcf5ef2aSThomas Huth /* Sub functions with Two operands functions */ 1465fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 1466fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1467fcf5ef2aSThomas Huth { \ 1468fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1469fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ 1470fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1471fcf5ef2aSThomas Huth } 1472fcf5ef2aSThomas Huth /* Sub functions with one operand and one immediate */ 1473fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 1474fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 1475fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1476fcf5ef2aSThomas Huth { \ 1477fcf5ef2aSThomas Huth TCGv t0 = tcg_const_tl(const_val); \ 1478fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ 1479fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], t0, \ 1480fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ 1481fcf5ef2aSThomas Huth tcg_temp_free(t0); \ 1482fcf5ef2aSThomas Huth } 1483fcf5ef2aSThomas Huth /* subf subf. subfo subfo. */ 1484fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 1485fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 1486fcf5ef2aSThomas Huth /* subfc subfc. subfco subfco. */ 1487fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 1488fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 1489fcf5ef2aSThomas Huth /* subfe subfe. subfeo subfo. */ 1490fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 1491fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 1492fcf5ef2aSThomas Huth /* subfme subfme. subfmeo subfmeo. */ 1493fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 1494fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 1495fcf5ef2aSThomas Huth /* subfze subfze. subfzeo subfzeo.*/ 1496fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 1497fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 1498fcf5ef2aSThomas Huth 1499fcf5ef2aSThomas Huth /* subfic */ 1500fcf5ef2aSThomas Huth static void gen_subfic(DisasContext *ctx) 1501fcf5ef2aSThomas Huth { 1502fcf5ef2aSThomas Huth TCGv c = tcg_const_tl(SIMM(ctx->opcode)); 1503fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1504fcf5ef2aSThomas Huth c, 0, 1, 0, 0); 1505fcf5ef2aSThomas Huth tcg_temp_free(c); 1506fcf5ef2aSThomas Huth } 1507fcf5ef2aSThomas Huth 1508fcf5ef2aSThomas Huth /* neg neg. nego nego. */ 1509fcf5ef2aSThomas Huth static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) 1510fcf5ef2aSThomas Huth { 1511fcf5ef2aSThomas Huth TCGv zero = tcg_const_tl(0); 1512fcf5ef2aSThomas Huth gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1513fcf5ef2aSThomas Huth zero, 0, 0, compute_ov, Rc(ctx->opcode)); 1514fcf5ef2aSThomas Huth tcg_temp_free(zero); 1515fcf5ef2aSThomas Huth } 1516fcf5ef2aSThomas Huth 1517fcf5ef2aSThomas Huth static void gen_neg(DisasContext *ctx) 1518fcf5ef2aSThomas Huth { 15191480d71cSNikunj A Dadhania tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 15201480d71cSNikunj A Dadhania if (unlikely(Rc(ctx->opcode))) { 15211480d71cSNikunj A Dadhania gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 15221480d71cSNikunj A Dadhania } 1523fcf5ef2aSThomas Huth } 1524fcf5ef2aSThomas Huth 1525fcf5ef2aSThomas Huth static void gen_nego(DisasContext *ctx) 1526fcf5ef2aSThomas Huth { 1527fcf5ef2aSThomas Huth gen_op_arith_neg(ctx, 1); 1528fcf5ef2aSThomas Huth } 1529fcf5ef2aSThomas Huth 1530fcf5ef2aSThomas Huth /*** Integer logical ***/ 1531fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 1532fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1533fcf5ef2aSThomas Huth { \ 1534fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ 1535fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); \ 1536fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1537fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1538fcf5ef2aSThomas Huth } 1539fcf5ef2aSThomas Huth 1540fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 1541fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 1542fcf5ef2aSThomas Huth { \ 1543fcf5ef2aSThomas Huth tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ 1544fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) \ 1545fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ 1546fcf5ef2aSThomas Huth } 1547fcf5ef2aSThomas Huth 1548fcf5ef2aSThomas Huth /* and & and. */ 1549fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); 1550fcf5ef2aSThomas Huth /* andc & andc. */ 1551fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); 1552fcf5ef2aSThomas Huth 1553fcf5ef2aSThomas Huth /* andi. */ 1554fcf5ef2aSThomas Huth static void gen_andi_(DisasContext *ctx) 1555fcf5ef2aSThomas Huth { 1556fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); 1557fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1558fcf5ef2aSThomas Huth } 1559fcf5ef2aSThomas Huth 1560fcf5ef2aSThomas Huth /* andis. */ 1561fcf5ef2aSThomas Huth static void gen_andis_(DisasContext *ctx) 1562fcf5ef2aSThomas Huth { 1563fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); 1564fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1565fcf5ef2aSThomas Huth } 1566fcf5ef2aSThomas Huth 1567fcf5ef2aSThomas Huth /* cntlzw */ 1568fcf5ef2aSThomas Huth static void gen_cntlzw(DisasContext *ctx) 1569fcf5ef2aSThomas Huth { 15709b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15719b8514e5SRichard Henderson 15729b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15739b8514e5SRichard Henderson tcg_gen_clzi_i32(t, t, 32); 15749b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15759b8514e5SRichard Henderson tcg_temp_free_i32(t); 15769b8514e5SRichard Henderson 1577fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1578fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1579fcf5ef2aSThomas Huth } 1580fcf5ef2aSThomas Huth 1581fcf5ef2aSThomas Huth /* cnttzw */ 1582fcf5ef2aSThomas Huth static void gen_cnttzw(DisasContext *ctx) 1583fcf5ef2aSThomas Huth { 15849b8514e5SRichard Henderson TCGv_i32 t = tcg_temp_new_i32(); 15859b8514e5SRichard Henderson 15869b8514e5SRichard Henderson tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); 15879b8514e5SRichard Henderson tcg_gen_ctzi_i32(t, t, 32); 15889b8514e5SRichard Henderson tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); 15899b8514e5SRichard Henderson tcg_temp_free_i32(t); 15909b8514e5SRichard Henderson 1591fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1592fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1593fcf5ef2aSThomas Huth } 1594fcf5ef2aSThomas Huth } 1595fcf5ef2aSThomas Huth 1596fcf5ef2aSThomas Huth /* eqv & eqv. */ 1597fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); 1598fcf5ef2aSThomas Huth /* extsb & extsb. */ 1599fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); 1600fcf5ef2aSThomas Huth /* extsh & extsh. */ 1601fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); 1602fcf5ef2aSThomas Huth /* nand & nand. */ 1603fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); 1604fcf5ef2aSThomas Huth /* nor & nor. */ 1605fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); 1606fcf5ef2aSThomas Huth 1607fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 1608fcf5ef2aSThomas Huth static void gen_pause(DisasContext *ctx) 1609fcf5ef2aSThomas Huth { 1610fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(0); 1611fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 1612fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 1613fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1614fcf5ef2aSThomas Huth 1615fcf5ef2aSThomas Huth /* Stop translation, this gives other CPUs a chance to run */ 1616b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 1617fcf5ef2aSThomas Huth } 1618fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 1619fcf5ef2aSThomas Huth 1620fcf5ef2aSThomas Huth /* or & or. */ 1621fcf5ef2aSThomas Huth static void gen_or(DisasContext *ctx) 1622fcf5ef2aSThomas Huth { 1623fcf5ef2aSThomas Huth int rs, ra, rb; 1624fcf5ef2aSThomas Huth 1625fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 1626fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 1627fcf5ef2aSThomas Huth rb = rB(ctx->opcode); 1628fcf5ef2aSThomas Huth /* Optimisation for mr. ri case */ 1629fcf5ef2aSThomas Huth if (rs != ra || rs != rb) { 1630fcf5ef2aSThomas Huth if (rs != rb) 1631fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); 1632fcf5ef2aSThomas Huth else 1633fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); 1634fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1635fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[ra]); 1636fcf5ef2aSThomas Huth } else if (unlikely(Rc(ctx->opcode) != 0)) { 1637fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rs]); 1638fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1639fcf5ef2aSThomas Huth } else if (rs != 0) { /* 0 is nop */ 1640fcf5ef2aSThomas Huth int prio = 0; 1641fcf5ef2aSThomas Huth 1642fcf5ef2aSThomas Huth switch (rs) { 1643fcf5ef2aSThomas Huth case 1: 1644fcf5ef2aSThomas Huth /* Set process priority to low */ 1645fcf5ef2aSThomas Huth prio = 2; 1646fcf5ef2aSThomas Huth break; 1647fcf5ef2aSThomas Huth case 6: 1648fcf5ef2aSThomas Huth /* Set process priority to medium-low */ 1649fcf5ef2aSThomas Huth prio = 3; 1650fcf5ef2aSThomas Huth break; 1651fcf5ef2aSThomas Huth case 2: 1652fcf5ef2aSThomas Huth /* Set process priority to normal */ 1653fcf5ef2aSThomas Huth prio = 4; 1654fcf5ef2aSThomas Huth break; 1655fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1656fcf5ef2aSThomas Huth case 31: 1657fcf5ef2aSThomas Huth if (!ctx->pr) { 1658fcf5ef2aSThomas Huth /* Set process priority to very low */ 1659fcf5ef2aSThomas Huth prio = 1; 1660fcf5ef2aSThomas Huth } 1661fcf5ef2aSThomas Huth break; 1662fcf5ef2aSThomas Huth case 5: 1663fcf5ef2aSThomas Huth if (!ctx->pr) { 1664fcf5ef2aSThomas Huth /* Set process priority to medium-hight */ 1665fcf5ef2aSThomas Huth prio = 5; 1666fcf5ef2aSThomas Huth } 1667fcf5ef2aSThomas Huth break; 1668fcf5ef2aSThomas Huth case 3: 1669fcf5ef2aSThomas Huth if (!ctx->pr) { 1670fcf5ef2aSThomas Huth /* Set process priority to high */ 1671fcf5ef2aSThomas Huth prio = 6; 1672fcf5ef2aSThomas Huth } 1673fcf5ef2aSThomas Huth break; 1674fcf5ef2aSThomas Huth case 7: 1675fcf5ef2aSThomas Huth if (ctx->hv && !ctx->pr) { 1676fcf5ef2aSThomas Huth /* Set process priority to very high */ 1677fcf5ef2aSThomas Huth prio = 7; 1678fcf5ef2aSThomas Huth } 1679fcf5ef2aSThomas Huth break; 1680fcf5ef2aSThomas Huth #endif 1681fcf5ef2aSThomas Huth default: 1682fcf5ef2aSThomas Huth break; 1683fcf5ef2aSThomas Huth } 1684fcf5ef2aSThomas Huth if (prio) { 1685fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1686fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_PPR); 1687fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); 1688fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); 1689fcf5ef2aSThomas Huth gen_store_spr(SPR_PPR, t0); 1690fcf5ef2aSThomas Huth tcg_temp_free(t0); 1691fcf5ef2aSThomas Huth } 1692fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 1693fcf5ef2aSThomas Huth /* Pause out of TCG otherwise spin loops with smt_low eat too much 1694fcf5ef2aSThomas Huth * CPU and the kernel hangs. This applies to all encodings other 1695fcf5ef2aSThomas Huth * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), 1696fcf5ef2aSThomas Huth * and all currently undefined. 1697fcf5ef2aSThomas Huth */ 1698fcf5ef2aSThomas Huth gen_pause(ctx); 1699fcf5ef2aSThomas Huth #endif 1700fcf5ef2aSThomas Huth #endif 1701fcf5ef2aSThomas Huth } 1702fcf5ef2aSThomas Huth } 1703fcf5ef2aSThomas Huth /* orc & orc. */ 1704fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); 1705fcf5ef2aSThomas Huth 1706fcf5ef2aSThomas Huth /* xor & xor. */ 1707fcf5ef2aSThomas Huth static void gen_xor(DisasContext *ctx) 1708fcf5ef2aSThomas Huth { 1709fcf5ef2aSThomas Huth /* Optimisation for "set to zero" case */ 1710fcf5ef2aSThomas Huth if (rS(ctx->opcode) != rB(ctx->opcode)) 1711fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1712fcf5ef2aSThomas Huth else 1713fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 1714fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1715fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1716fcf5ef2aSThomas Huth } 1717fcf5ef2aSThomas Huth 1718fcf5ef2aSThomas Huth /* ori */ 1719fcf5ef2aSThomas Huth static void gen_ori(DisasContext *ctx) 1720fcf5ef2aSThomas Huth { 1721fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1722fcf5ef2aSThomas Huth 1723fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1724fcf5ef2aSThomas Huth return; 1725fcf5ef2aSThomas Huth } 1726fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1727fcf5ef2aSThomas Huth } 1728fcf5ef2aSThomas Huth 1729fcf5ef2aSThomas Huth /* oris */ 1730fcf5ef2aSThomas Huth static void gen_oris(DisasContext *ctx) 1731fcf5ef2aSThomas Huth { 1732fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1733fcf5ef2aSThomas Huth 1734fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1735fcf5ef2aSThomas Huth /* NOP */ 1736fcf5ef2aSThomas Huth return; 1737fcf5ef2aSThomas Huth } 1738fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1739fcf5ef2aSThomas Huth } 1740fcf5ef2aSThomas Huth 1741fcf5ef2aSThomas Huth /* xori */ 1742fcf5ef2aSThomas Huth static void gen_xori(DisasContext *ctx) 1743fcf5ef2aSThomas Huth { 1744fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1745fcf5ef2aSThomas Huth 1746fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1747fcf5ef2aSThomas Huth /* NOP */ 1748fcf5ef2aSThomas Huth return; 1749fcf5ef2aSThomas Huth } 1750fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); 1751fcf5ef2aSThomas Huth } 1752fcf5ef2aSThomas Huth 1753fcf5ef2aSThomas Huth /* xoris */ 1754fcf5ef2aSThomas Huth static void gen_xoris(DisasContext *ctx) 1755fcf5ef2aSThomas Huth { 1756fcf5ef2aSThomas Huth target_ulong uimm = UIMM(ctx->opcode); 1757fcf5ef2aSThomas Huth 1758fcf5ef2aSThomas Huth if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { 1759fcf5ef2aSThomas Huth /* NOP */ 1760fcf5ef2aSThomas Huth return; 1761fcf5ef2aSThomas Huth } 1762fcf5ef2aSThomas Huth tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); 1763fcf5ef2aSThomas Huth } 1764fcf5ef2aSThomas Huth 1765fcf5ef2aSThomas Huth /* popcntb : PowerPC 2.03 specification */ 1766fcf5ef2aSThomas Huth static void gen_popcntb(DisasContext *ctx) 1767fcf5ef2aSThomas Huth { 1768fcf5ef2aSThomas Huth gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1769fcf5ef2aSThomas Huth } 1770fcf5ef2aSThomas Huth 1771fcf5ef2aSThomas Huth static void gen_popcntw(DisasContext *ctx) 1772fcf5ef2aSThomas Huth { 177379770002SRichard Henderson #if defined(TARGET_PPC64) 1774fcf5ef2aSThomas Huth gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 177579770002SRichard Henderson #else 177679770002SRichard Henderson tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 177779770002SRichard Henderson #endif 1778fcf5ef2aSThomas Huth } 1779fcf5ef2aSThomas Huth 1780fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1781fcf5ef2aSThomas Huth /* popcntd: PowerPC 2.06 specification */ 1782fcf5ef2aSThomas Huth static void gen_popcntd(DisasContext *ctx) 1783fcf5ef2aSThomas Huth { 178479770002SRichard Henderson tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); 1785fcf5ef2aSThomas Huth } 1786fcf5ef2aSThomas Huth #endif 1787fcf5ef2aSThomas Huth 1788fcf5ef2aSThomas Huth /* prtyw: PowerPC 2.05 specification */ 1789fcf5ef2aSThomas Huth static void gen_prtyw(DisasContext *ctx) 1790fcf5ef2aSThomas Huth { 1791fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1792fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1793fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1794fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 16); 1795fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1796fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1797fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1798fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); 1799fcf5ef2aSThomas Huth tcg_temp_free(t0); 1800fcf5ef2aSThomas Huth } 1801fcf5ef2aSThomas Huth 1802fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1803fcf5ef2aSThomas Huth /* prtyd: PowerPC 2.05 specification */ 1804fcf5ef2aSThomas Huth static void gen_prtyd(DisasContext *ctx) 1805fcf5ef2aSThomas Huth { 1806fcf5ef2aSThomas Huth TCGv ra = cpu_gpr[rA(ctx->opcode)]; 1807fcf5ef2aSThomas Huth TCGv rs = cpu_gpr[rS(ctx->opcode)]; 1808fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 1809fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, rs, 32); 1810fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, rs, t0); 1811fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 16); 1812fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1813fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, ra, 8); 1814fcf5ef2aSThomas Huth tcg_gen_xor_tl(ra, ra, t0); 1815fcf5ef2aSThomas Huth tcg_gen_andi_tl(ra, ra, 1); 1816fcf5ef2aSThomas Huth tcg_temp_free(t0); 1817fcf5ef2aSThomas Huth } 1818fcf5ef2aSThomas Huth #endif 1819fcf5ef2aSThomas Huth 1820fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1821fcf5ef2aSThomas Huth /* bpermd */ 1822fcf5ef2aSThomas Huth static void gen_bpermd(DisasContext *ctx) 1823fcf5ef2aSThomas Huth { 1824fcf5ef2aSThomas Huth gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], 1825fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 1826fcf5ef2aSThomas Huth } 1827fcf5ef2aSThomas Huth #endif 1828fcf5ef2aSThomas Huth 1829fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1830fcf5ef2aSThomas Huth /* extsw & extsw. */ 1831fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); 1832fcf5ef2aSThomas Huth 1833fcf5ef2aSThomas Huth /* cntlzd */ 1834fcf5ef2aSThomas Huth static void gen_cntlzd(DisasContext *ctx) 1835fcf5ef2aSThomas Huth { 18369b8514e5SRichard Henderson tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1837fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 1838fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1839fcf5ef2aSThomas Huth } 1840fcf5ef2aSThomas Huth 1841fcf5ef2aSThomas Huth /* cnttzd */ 1842fcf5ef2aSThomas Huth static void gen_cnttzd(DisasContext *ctx) 1843fcf5ef2aSThomas Huth { 18449b8514e5SRichard Henderson tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); 1845fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1846fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 1847fcf5ef2aSThomas Huth } 1848fcf5ef2aSThomas Huth } 1849fcf5ef2aSThomas Huth 1850fcf5ef2aSThomas Huth /* darn */ 1851fcf5ef2aSThomas Huth static void gen_darn(DisasContext *ctx) 1852fcf5ef2aSThomas Huth { 1853fcf5ef2aSThomas Huth int l = L(ctx->opcode); 1854fcf5ef2aSThomas Huth 1855fcf5ef2aSThomas Huth if (l == 0) { 1856fcf5ef2aSThomas Huth gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); 1857fcf5ef2aSThomas Huth } else if (l <= 2) { 1858fcf5ef2aSThomas Huth /* Return 64-bit random for both CRN and RRN */ 1859fcf5ef2aSThomas Huth gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); 1860fcf5ef2aSThomas Huth } else { 1861fcf5ef2aSThomas Huth tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); 1862fcf5ef2aSThomas Huth } 1863fcf5ef2aSThomas Huth } 1864fcf5ef2aSThomas Huth #endif 1865fcf5ef2aSThomas Huth 1866fcf5ef2aSThomas Huth /*** Integer rotate ***/ 1867fcf5ef2aSThomas Huth 1868fcf5ef2aSThomas Huth /* rlwimi & rlwimi. */ 1869fcf5ef2aSThomas Huth static void gen_rlwimi(DisasContext *ctx) 1870fcf5ef2aSThomas Huth { 1871fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1872fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1873fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode); 1874fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1875fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1876fcf5ef2aSThomas Huth 1877fcf5ef2aSThomas Huth if (sh == (31-me) && mb <= me) { 1878fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 1879fcf5ef2aSThomas Huth } else { 1880fcf5ef2aSThomas Huth target_ulong mask; 1881fcf5ef2aSThomas Huth TCGv t1; 1882fcf5ef2aSThomas Huth 1883fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1884fcf5ef2aSThomas Huth mb += 32; 1885fcf5ef2aSThomas Huth me += 32; 1886fcf5ef2aSThomas Huth #endif 1887fcf5ef2aSThomas Huth mask = MASK(mb, me); 1888fcf5ef2aSThomas Huth 1889fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 1890fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1891fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1892fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1893fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1894fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t1, t0); 1895fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1896fcf5ef2aSThomas Huth } else { 1897fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1898fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); 1899fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t1, t1, sh); 1900fcf5ef2aSThomas Huth #else 1901fcf5ef2aSThomas Huth g_assert_not_reached(); 1902fcf5ef2aSThomas Huth #endif 1903fcf5ef2aSThomas Huth } 1904fcf5ef2aSThomas Huth 1905fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 1906fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 1907fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 1908fcf5ef2aSThomas Huth tcg_temp_free(t1); 1909fcf5ef2aSThomas Huth } 1910fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1911fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1912fcf5ef2aSThomas Huth } 1913fcf5ef2aSThomas Huth } 1914fcf5ef2aSThomas Huth 1915fcf5ef2aSThomas Huth /* rlwinm & rlwinm. */ 1916fcf5ef2aSThomas Huth static void gen_rlwinm(DisasContext *ctx) 1917fcf5ef2aSThomas Huth { 1918fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1919fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 19207b4d326fSRichard Henderson int sh = SH(ctx->opcode); 19217b4d326fSRichard Henderson int mb = MB(ctx->opcode); 19227b4d326fSRichard Henderson int me = ME(ctx->opcode); 19237b4d326fSRichard Henderson int len = me - mb + 1; 19247b4d326fSRichard Henderson int rsh = (32 - sh) & 31; 1925fcf5ef2aSThomas Huth 19267b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (31 - sh)) { 19277b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 19287b4d326fSRichard Henderson } else if (me == 31 && rsh + len <= 32) { 19297b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 1930fcf5ef2aSThomas Huth } else { 1931fcf5ef2aSThomas Huth target_ulong mask; 1932fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1933fcf5ef2aSThomas Huth mb += 32; 1934fcf5ef2aSThomas Huth me += 32; 1935fcf5ef2aSThomas Huth #endif 1936fcf5ef2aSThomas Huth mask = MASK(mb, me); 19377b4d326fSRichard Henderson if (sh == 0) { 19387b4d326fSRichard Henderson tcg_gen_andi_tl(t_ra, t_rs, mask); 19397b4d326fSRichard Henderson } else if (mask <= 0xffffffffu) { 1940fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1941fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rs); 1942fcf5ef2aSThomas Huth tcg_gen_rotli_i32(t0, t0, sh); 1943fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, mask); 1944fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t0); 1945fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1946fcf5ef2aSThomas Huth } else { 1947fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1948fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1949fcf5ef2aSThomas Huth tcg_gen_rotli_i64(t_ra, t_ra, sh); 1950fcf5ef2aSThomas Huth tcg_gen_andi_i64(t_ra, t_ra, mask); 1951fcf5ef2aSThomas Huth #else 1952fcf5ef2aSThomas Huth g_assert_not_reached(); 1953fcf5ef2aSThomas Huth #endif 1954fcf5ef2aSThomas Huth } 1955fcf5ef2aSThomas Huth } 1956fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 1957fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 1958fcf5ef2aSThomas Huth } 1959fcf5ef2aSThomas Huth } 1960fcf5ef2aSThomas Huth 1961fcf5ef2aSThomas Huth /* rlwnm & rlwnm. */ 1962fcf5ef2aSThomas Huth static void gen_rlwnm(DisasContext *ctx) 1963fcf5ef2aSThomas Huth { 1964fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 1965fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 1966fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 1967fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 1968fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 1969fcf5ef2aSThomas Huth target_ulong mask; 1970fcf5ef2aSThomas Huth 1971fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1972fcf5ef2aSThomas Huth mb += 32; 1973fcf5ef2aSThomas Huth me += 32; 1974fcf5ef2aSThomas Huth #endif 1975fcf5ef2aSThomas Huth mask = MASK(mb, me); 1976fcf5ef2aSThomas Huth 1977fcf5ef2aSThomas Huth if (mask <= 0xffffffffu) { 1978fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 1979fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 1980fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, t_rb); 1981fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, t_rs); 1982fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, 0x1f); 1983fcf5ef2aSThomas Huth tcg_gen_rotl_i32(t1, t1, t0); 1984fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(t_ra, t1); 1985fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 1986fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 1987fcf5ef2aSThomas Huth } else { 1988fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 1989fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 1990fcf5ef2aSThomas Huth tcg_gen_andi_i64(t0, t_rb, 0x1f); 1991fcf5ef2aSThomas Huth tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); 1992fcf5ef2aSThomas Huth tcg_gen_rotl_i64(t_ra, t_ra, t0); 1993fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 1994fcf5ef2aSThomas Huth #else 1995fcf5ef2aSThomas Huth g_assert_not_reached(); 1996fcf5ef2aSThomas Huth #endif 1997fcf5ef2aSThomas Huth } 1998fcf5ef2aSThomas Huth 1999fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, mask); 2000fcf5ef2aSThomas Huth 2001fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2002fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2003fcf5ef2aSThomas Huth } 2004fcf5ef2aSThomas Huth } 2005fcf5ef2aSThomas Huth 2006fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2007fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 2008fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2009fcf5ef2aSThomas Huth { \ 2010fcf5ef2aSThomas Huth gen_##name(ctx, 0); \ 2011fcf5ef2aSThomas Huth } \ 2012fcf5ef2aSThomas Huth \ 2013fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2014fcf5ef2aSThomas Huth { \ 2015fcf5ef2aSThomas Huth gen_##name(ctx, 1); \ 2016fcf5ef2aSThomas Huth } 2017fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 2018fcf5ef2aSThomas Huth static void glue(gen_, name##0)(DisasContext *ctx) \ 2019fcf5ef2aSThomas Huth { \ 2020fcf5ef2aSThomas Huth gen_##name(ctx, 0, 0); \ 2021fcf5ef2aSThomas Huth } \ 2022fcf5ef2aSThomas Huth \ 2023fcf5ef2aSThomas Huth static void glue(gen_, name##1)(DisasContext *ctx) \ 2024fcf5ef2aSThomas Huth { \ 2025fcf5ef2aSThomas Huth gen_##name(ctx, 0, 1); \ 2026fcf5ef2aSThomas Huth } \ 2027fcf5ef2aSThomas Huth \ 2028fcf5ef2aSThomas Huth static void glue(gen_, name##2)(DisasContext *ctx) \ 2029fcf5ef2aSThomas Huth { \ 2030fcf5ef2aSThomas Huth gen_##name(ctx, 1, 0); \ 2031fcf5ef2aSThomas Huth } \ 2032fcf5ef2aSThomas Huth \ 2033fcf5ef2aSThomas Huth static void glue(gen_, name##3)(DisasContext *ctx) \ 2034fcf5ef2aSThomas Huth { \ 2035fcf5ef2aSThomas Huth gen_##name(ctx, 1, 1); \ 2036fcf5ef2aSThomas Huth } 2037fcf5ef2aSThomas Huth 2038fcf5ef2aSThomas Huth static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) 2039fcf5ef2aSThomas Huth { 2040fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2041fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 20427b4d326fSRichard Henderson int len = me - mb + 1; 20437b4d326fSRichard Henderson int rsh = (64 - sh) & 63; 2044fcf5ef2aSThomas Huth 20457b4d326fSRichard Henderson if (sh != 0 && len > 0 && me == (63 - sh)) { 20467b4d326fSRichard Henderson tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); 20477b4d326fSRichard Henderson } else if (me == 63 && rsh + len <= 64) { 20487b4d326fSRichard Henderson tcg_gen_extract_tl(t_ra, t_rs, rsh, len); 2049fcf5ef2aSThomas Huth } else { 2050fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t_ra, t_rs, sh); 2051fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2052fcf5ef2aSThomas Huth } 2053fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2054fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2055fcf5ef2aSThomas Huth } 2056fcf5ef2aSThomas Huth } 2057fcf5ef2aSThomas Huth 2058fcf5ef2aSThomas Huth /* rldicl - rldicl. */ 2059fcf5ef2aSThomas Huth static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) 2060fcf5ef2aSThomas Huth { 2061fcf5ef2aSThomas Huth uint32_t sh, mb; 2062fcf5ef2aSThomas Huth 2063fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2064fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2065fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63, sh); 2066fcf5ef2aSThomas Huth } 2067fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00); 2068fcf5ef2aSThomas Huth 2069fcf5ef2aSThomas Huth /* rldicr - rldicr. */ 2070fcf5ef2aSThomas Huth static inline void gen_rldicr(DisasContext *ctx, int men, int shn) 2071fcf5ef2aSThomas Huth { 2072fcf5ef2aSThomas Huth uint32_t sh, me; 2073fcf5ef2aSThomas Huth 2074fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2075fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2076fcf5ef2aSThomas Huth gen_rldinm(ctx, 0, me, sh); 2077fcf5ef2aSThomas Huth } 2078fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02); 2079fcf5ef2aSThomas Huth 2080fcf5ef2aSThomas Huth /* rldic - rldic. */ 2081fcf5ef2aSThomas Huth static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) 2082fcf5ef2aSThomas Huth { 2083fcf5ef2aSThomas Huth uint32_t sh, mb; 2084fcf5ef2aSThomas Huth 2085fcf5ef2aSThomas Huth sh = SH(ctx->opcode) | (shn << 5); 2086fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2087fcf5ef2aSThomas Huth gen_rldinm(ctx, mb, 63 - sh, sh); 2088fcf5ef2aSThomas Huth } 2089fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04); 2090fcf5ef2aSThomas Huth 2091fcf5ef2aSThomas Huth static void gen_rldnm(DisasContext *ctx, int mb, int me) 2092fcf5ef2aSThomas Huth { 2093fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2094fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2095fcf5ef2aSThomas Huth TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; 2096fcf5ef2aSThomas Huth TCGv t0; 2097fcf5ef2aSThomas Huth 2098fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2099fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t_rb, 0x3f); 2100fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t_ra, t_rs, t0); 2101fcf5ef2aSThomas Huth tcg_temp_free(t0); 2102fcf5ef2aSThomas Huth 2103fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); 2104fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2105fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2106fcf5ef2aSThomas Huth } 2107fcf5ef2aSThomas Huth } 2108fcf5ef2aSThomas Huth 2109fcf5ef2aSThomas Huth /* rldcl - rldcl. */ 2110fcf5ef2aSThomas Huth static inline void gen_rldcl(DisasContext *ctx, int mbn) 2111fcf5ef2aSThomas Huth { 2112fcf5ef2aSThomas Huth uint32_t mb; 2113fcf5ef2aSThomas Huth 2114fcf5ef2aSThomas Huth mb = MB(ctx->opcode) | (mbn << 5); 2115fcf5ef2aSThomas Huth gen_rldnm(ctx, mb, 63); 2116fcf5ef2aSThomas Huth } 2117fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08); 2118fcf5ef2aSThomas Huth 2119fcf5ef2aSThomas Huth /* rldcr - rldcr. */ 2120fcf5ef2aSThomas Huth static inline void gen_rldcr(DisasContext *ctx, int men) 2121fcf5ef2aSThomas Huth { 2122fcf5ef2aSThomas Huth uint32_t me; 2123fcf5ef2aSThomas Huth 2124fcf5ef2aSThomas Huth me = MB(ctx->opcode) | (men << 5); 2125fcf5ef2aSThomas Huth gen_rldnm(ctx, 0, me); 2126fcf5ef2aSThomas Huth } 2127fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09); 2128fcf5ef2aSThomas Huth 2129fcf5ef2aSThomas Huth /* rldimi - rldimi. */ 2130fcf5ef2aSThomas Huth static void gen_rldimi(DisasContext *ctx, int mbn, int shn) 2131fcf5ef2aSThomas Huth { 2132fcf5ef2aSThomas Huth TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; 2133fcf5ef2aSThomas Huth TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; 2134fcf5ef2aSThomas Huth uint32_t sh = SH(ctx->opcode) | (shn << 5); 2135fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode) | (mbn << 5); 2136fcf5ef2aSThomas Huth uint32_t me = 63 - sh; 2137fcf5ef2aSThomas Huth 2138fcf5ef2aSThomas Huth if (mb <= me) { 2139fcf5ef2aSThomas Huth tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); 2140fcf5ef2aSThomas Huth } else { 2141fcf5ef2aSThomas Huth target_ulong mask = MASK(mb, me); 2142fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 2143fcf5ef2aSThomas Huth 2144fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t1, t_rs, sh); 2145fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, mask); 2146fcf5ef2aSThomas Huth tcg_gen_andi_tl(t_ra, t_ra, ~mask); 2147fcf5ef2aSThomas Huth tcg_gen_or_tl(t_ra, t_ra, t1); 2148fcf5ef2aSThomas Huth tcg_temp_free(t1); 2149fcf5ef2aSThomas Huth } 2150fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2151fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t_ra); 2152fcf5ef2aSThomas Huth } 2153fcf5ef2aSThomas Huth } 2154fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06); 2155fcf5ef2aSThomas Huth #endif 2156fcf5ef2aSThomas Huth 2157fcf5ef2aSThomas Huth /*** Integer shift ***/ 2158fcf5ef2aSThomas Huth 2159fcf5ef2aSThomas Huth /* slw & slw. */ 2160fcf5ef2aSThomas Huth static void gen_slw(DisasContext *ctx) 2161fcf5ef2aSThomas Huth { 2162fcf5ef2aSThomas Huth TCGv t0, t1; 2163fcf5ef2aSThomas Huth 2164fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2165fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2166fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2167fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2168fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2169fcf5ef2aSThomas Huth #else 2170fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2171fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2172fcf5ef2aSThomas Huth #endif 2173fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2174fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2175fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2176fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2177fcf5ef2aSThomas Huth tcg_temp_free(t1); 2178fcf5ef2aSThomas Huth tcg_temp_free(t0); 2179fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 2180fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2181fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2182fcf5ef2aSThomas Huth } 2183fcf5ef2aSThomas Huth 2184fcf5ef2aSThomas Huth /* sraw & sraw. */ 2185fcf5ef2aSThomas Huth static void gen_sraw(DisasContext *ctx) 2186fcf5ef2aSThomas Huth { 2187fcf5ef2aSThomas Huth gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, 2188fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2189fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2190fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2191fcf5ef2aSThomas Huth } 2192fcf5ef2aSThomas Huth 2193fcf5ef2aSThomas Huth /* srawi & srawi. */ 2194fcf5ef2aSThomas Huth static void gen_srawi(DisasContext *ctx) 2195fcf5ef2aSThomas Huth { 2196fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 2197fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2198fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2199fcf5ef2aSThomas Huth if (sh == 0) { 2200fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2201fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2202af1c259fSSandipan Das if (is_isa300(ctx)) { 2203af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2204af1c259fSSandipan Das } 2205fcf5ef2aSThomas Huth } else { 2206fcf5ef2aSThomas Huth TCGv t0; 2207fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2208fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); 2209fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2210fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); 2211fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2212fcf5ef2aSThomas Huth tcg_temp_free(t0); 2213fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2214af1c259fSSandipan Das if (is_isa300(ctx)) { 2215af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2216af1c259fSSandipan Das } 2217fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, dst, sh); 2218fcf5ef2aSThomas Huth } 2219fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2220fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2221fcf5ef2aSThomas Huth } 2222fcf5ef2aSThomas Huth } 2223fcf5ef2aSThomas Huth 2224fcf5ef2aSThomas Huth /* srw & srw. */ 2225fcf5ef2aSThomas Huth static void gen_srw(DisasContext *ctx) 2226fcf5ef2aSThomas Huth { 2227fcf5ef2aSThomas Huth TCGv t0, t1; 2228fcf5ef2aSThomas Huth 2229fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2230fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x20 */ 2231fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2232fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); 2233fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2234fcf5ef2aSThomas Huth #else 2235fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); 2236fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x1f); 2237fcf5ef2aSThomas Huth #endif 2238fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2239fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, t0); 2240fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2241fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); 2242fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2243fcf5ef2aSThomas Huth tcg_temp_free(t1); 2244fcf5ef2aSThomas Huth tcg_temp_free(t0); 2245fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2246fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2247fcf5ef2aSThomas Huth } 2248fcf5ef2aSThomas Huth 2249fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2250fcf5ef2aSThomas Huth /* sld & sld. */ 2251fcf5ef2aSThomas Huth static void gen_sld(DisasContext *ctx) 2252fcf5ef2aSThomas Huth { 2253fcf5ef2aSThomas Huth TCGv t0, t1; 2254fcf5ef2aSThomas Huth 2255fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2256fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2257fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2258fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2259fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2260fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2261fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2262fcf5ef2aSThomas Huth tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2263fcf5ef2aSThomas Huth tcg_temp_free(t1); 2264fcf5ef2aSThomas Huth tcg_temp_free(t0); 2265fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2266fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2267fcf5ef2aSThomas Huth } 2268fcf5ef2aSThomas Huth 2269fcf5ef2aSThomas Huth /* srad & srad. */ 2270fcf5ef2aSThomas Huth static void gen_srad(DisasContext *ctx) 2271fcf5ef2aSThomas Huth { 2272fcf5ef2aSThomas Huth gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, 2273fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2274fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2275fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2276fcf5ef2aSThomas Huth } 2277fcf5ef2aSThomas Huth /* sradi & sradi. */ 2278fcf5ef2aSThomas Huth static inline void gen_sradi(DisasContext *ctx, int n) 2279fcf5ef2aSThomas Huth { 2280fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2281fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2282fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2283fcf5ef2aSThomas Huth if (sh == 0) { 2284fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, src); 2285fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 2286af1c259fSSandipan Das if (is_isa300(ctx)) { 2287af1c259fSSandipan Das tcg_gen_movi_tl(cpu_ca32, 0); 2288af1c259fSSandipan Das } 2289fcf5ef2aSThomas Huth } else { 2290fcf5ef2aSThomas Huth TCGv t0; 2291fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); 2292fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2293fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); 2294fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_ca, cpu_ca, t0); 2295fcf5ef2aSThomas Huth tcg_temp_free(t0); 2296fcf5ef2aSThomas Huth tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); 2297af1c259fSSandipan Das if (is_isa300(ctx)) { 2298af1c259fSSandipan Das tcg_gen_mov_tl(cpu_ca32, cpu_ca); 2299af1c259fSSandipan Das } 2300fcf5ef2aSThomas Huth tcg_gen_sari_tl(dst, src, sh); 2301fcf5ef2aSThomas Huth } 2302fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2303fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2304fcf5ef2aSThomas Huth } 2305fcf5ef2aSThomas Huth } 2306fcf5ef2aSThomas Huth 2307fcf5ef2aSThomas Huth static void gen_sradi0(DisasContext *ctx) 2308fcf5ef2aSThomas Huth { 2309fcf5ef2aSThomas Huth gen_sradi(ctx, 0); 2310fcf5ef2aSThomas Huth } 2311fcf5ef2aSThomas Huth 2312fcf5ef2aSThomas Huth static void gen_sradi1(DisasContext *ctx) 2313fcf5ef2aSThomas Huth { 2314fcf5ef2aSThomas Huth gen_sradi(ctx, 1); 2315fcf5ef2aSThomas Huth } 2316fcf5ef2aSThomas Huth 2317fcf5ef2aSThomas Huth /* extswsli & extswsli. */ 2318fcf5ef2aSThomas Huth static inline void gen_extswsli(DisasContext *ctx, int n) 2319fcf5ef2aSThomas Huth { 2320fcf5ef2aSThomas Huth int sh = SH(ctx->opcode) + (n << 5); 2321fcf5ef2aSThomas Huth TCGv dst = cpu_gpr[rA(ctx->opcode)]; 2322fcf5ef2aSThomas Huth TCGv src = cpu_gpr[rS(ctx->opcode)]; 2323fcf5ef2aSThomas Huth 2324fcf5ef2aSThomas Huth tcg_gen_ext32s_tl(dst, src); 2325fcf5ef2aSThomas Huth tcg_gen_shli_tl(dst, dst, sh); 2326fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) { 2327fcf5ef2aSThomas Huth gen_set_Rc0(ctx, dst); 2328fcf5ef2aSThomas Huth } 2329fcf5ef2aSThomas Huth } 2330fcf5ef2aSThomas Huth 2331fcf5ef2aSThomas Huth static void gen_extswsli0(DisasContext *ctx) 2332fcf5ef2aSThomas Huth { 2333fcf5ef2aSThomas Huth gen_extswsli(ctx, 0); 2334fcf5ef2aSThomas Huth } 2335fcf5ef2aSThomas Huth 2336fcf5ef2aSThomas Huth static void gen_extswsli1(DisasContext *ctx) 2337fcf5ef2aSThomas Huth { 2338fcf5ef2aSThomas Huth gen_extswsli(ctx, 1); 2339fcf5ef2aSThomas Huth } 2340fcf5ef2aSThomas Huth 2341fcf5ef2aSThomas Huth /* srd & srd. */ 2342fcf5ef2aSThomas Huth static void gen_srd(DisasContext *ctx) 2343fcf5ef2aSThomas Huth { 2344fcf5ef2aSThomas Huth TCGv t0, t1; 2345fcf5ef2aSThomas Huth 2346fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2347fcf5ef2aSThomas Huth /* AND rS with a mask that is 0 when rB >= 0x40 */ 2348fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); 2349fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, t0, 0x3f); 2350fcf5ef2aSThomas Huth tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 2351fcf5ef2aSThomas Huth t1 = tcg_temp_new(); 2352fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); 2353fcf5ef2aSThomas Huth tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 2354fcf5ef2aSThomas Huth tcg_temp_free(t1); 2355fcf5ef2aSThomas Huth tcg_temp_free(t0); 2356fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 2357fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 2358fcf5ef2aSThomas Huth } 2359fcf5ef2aSThomas Huth #endif 2360fcf5ef2aSThomas Huth 2361fcf5ef2aSThomas Huth /*** Addressing modes ***/ 2362fcf5ef2aSThomas Huth /* Register indirect with immediate index : EA = (rA|0) + SIMM */ 2363fcf5ef2aSThomas Huth static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, 2364fcf5ef2aSThomas Huth target_long maskl) 2365fcf5ef2aSThomas Huth { 2366fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 2367fcf5ef2aSThomas Huth 2368fcf5ef2aSThomas Huth simm &= ~maskl; 2369fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2370fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2371fcf5ef2aSThomas Huth simm = (uint32_t)simm; 2372fcf5ef2aSThomas Huth } 2373fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, simm); 2374fcf5ef2aSThomas Huth } else if (likely(simm != 0)) { 2375fcf5ef2aSThomas Huth tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); 2376fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2377fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2378fcf5ef2aSThomas Huth } 2379fcf5ef2aSThomas Huth } else { 2380fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2381fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2382fcf5ef2aSThomas Huth } else { 2383fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2384fcf5ef2aSThomas Huth } 2385fcf5ef2aSThomas Huth } 2386fcf5ef2aSThomas Huth } 2387fcf5ef2aSThomas Huth 2388fcf5ef2aSThomas Huth static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) 2389fcf5ef2aSThomas Huth { 2390fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2391fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2392fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2393fcf5ef2aSThomas Huth } else { 2394fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); 2395fcf5ef2aSThomas Huth } 2396fcf5ef2aSThomas Huth } else { 2397fcf5ef2aSThomas Huth tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 2398fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2399fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, EA); 2400fcf5ef2aSThomas Huth } 2401fcf5ef2aSThomas Huth } 2402fcf5ef2aSThomas Huth } 2403fcf5ef2aSThomas Huth 2404fcf5ef2aSThomas Huth static inline void gen_addr_register(DisasContext *ctx, TCGv EA) 2405fcf5ef2aSThomas Huth { 2406fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 2407fcf5ef2aSThomas Huth tcg_gen_movi_tl(EA, 0); 2408fcf5ef2aSThomas Huth } else if (NARROW_MODE(ctx)) { 2409fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2410fcf5ef2aSThomas Huth } else { 2411fcf5ef2aSThomas Huth tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); 2412fcf5ef2aSThomas Huth } 2413fcf5ef2aSThomas Huth } 2414fcf5ef2aSThomas Huth 2415fcf5ef2aSThomas Huth static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, 2416fcf5ef2aSThomas Huth target_long val) 2417fcf5ef2aSThomas Huth { 2418fcf5ef2aSThomas Huth tcg_gen_addi_tl(ret, arg1, val); 2419fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 2420fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(ret, ret); 2421fcf5ef2aSThomas Huth } 2422fcf5ef2aSThomas Huth } 2423fcf5ef2aSThomas Huth 2424fcf5ef2aSThomas Huth static inline void gen_align_no_le(DisasContext *ctx) 2425fcf5ef2aSThomas Huth { 2426fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_ALIGN, 2427fcf5ef2aSThomas Huth (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); 2428fcf5ef2aSThomas Huth } 2429fcf5ef2aSThomas Huth 2430fcf5ef2aSThomas Huth /*** Integer load ***/ 2431fcf5ef2aSThomas Huth #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) 2432fcf5ef2aSThomas Huth #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) 2433fcf5ef2aSThomas Huth 2434fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_TL(ldop, op) \ 2435fcf5ef2aSThomas Huth static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ 2436fcf5ef2aSThomas Huth TCGv val, \ 2437fcf5ef2aSThomas Huth TCGv addr) \ 2438fcf5ef2aSThomas Huth { \ 2439fcf5ef2aSThomas Huth tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ 2440fcf5ef2aSThomas Huth } 2441fcf5ef2aSThomas Huth 2442fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) 2443fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) 2444fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) 2445fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) 2446fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) 2447fcf5ef2aSThomas Huth 2448fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) 2449fcf5ef2aSThomas Huth GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) 2450fcf5ef2aSThomas Huth 2451fcf5ef2aSThomas Huth #define GEN_QEMU_LOAD_64(ldop, op) \ 2452fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ 2453fcf5ef2aSThomas Huth TCGv_i64 val, \ 2454fcf5ef2aSThomas Huth TCGv addr) \ 2455fcf5ef2aSThomas Huth { \ 2456fcf5ef2aSThomas Huth tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ 2457fcf5ef2aSThomas Huth } 2458fcf5ef2aSThomas Huth 2459fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) 2460fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) 2461fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) 2462fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) 2463fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) 2464fcf5ef2aSThomas Huth 2465fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2466fcf5ef2aSThomas Huth GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) 2467fcf5ef2aSThomas Huth #endif 2468fcf5ef2aSThomas Huth 2469fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_TL(stop, op) \ 2470fcf5ef2aSThomas Huth static void glue(gen_qemu_, stop)(DisasContext *ctx, \ 2471fcf5ef2aSThomas Huth TCGv val, \ 2472fcf5ef2aSThomas Huth TCGv addr) \ 2473fcf5ef2aSThomas Huth { \ 2474fcf5ef2aSThomas Huth tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ 2475fcf5ef2aSThomas Huth } 2476fcf5ef2aSThomas Huth 2477fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) 2478fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) 2479fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) 2480fcf5ef2aSThomas Huth 2481fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) 2482fcf5ef2aSThomas Huth GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) 2483fcf5ef2aSThomas Huth 2484fcf5ef2aSThomas Huth #define GEN_QEMU_STORE_64(stop, op) \ 2485fcf5ef2aSThomas Huth static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ 2486fcf5ef2aSThomas Huth TCGv_i64 val, \ 2487fcf5ef2aSThomas Huth TCGv addr) \ 2488fcf5ef2aSThomas Huth { \ 2489fcf5ef2aSThomas Huth tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ 2490fcf5ef2aSThomas Huth } 2491fcf5ef2aSThomas Huth 2492fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) 2493fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) 2494fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) 2495fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) 2496fcf5ef2aSThomas Huth 2497fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2498fcf5ef2aSThomas Huth GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) 2499fcf5ef2aSThomas Huth #endif 2500fcf5ef2aSThomas Huth 2501fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 2502fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2503fcf5ef2aSThomas Huth { \ 2504fcf5ef2aSThomas Huth TCGv EA; \ 2505fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2506fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2507fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2508fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2509fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2510fcf5ef2aSThomas Huth } 2511fcf5ef2aSThomas Huth 2512fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 2513fcf5ef2aSThomas Huth static void glue(gen_, name##u)(DisasContext *ctx) \ 2514fcf5ef2aSThomas Huth { \ 2515fcf5ef2aSThomas Huth TCGv EA; \ 2516fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2517fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2518fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2519fcf5ef2aSThomas Huth return; \ 2520fcf5ef2aSThomas Huth } \ 2521fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2522fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2523fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2524fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2525fcf5ef2aSThomas Huth else \ 2526fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2527fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2528fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2529fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2530fcf5ef2aSThomas Huth } 2531fcf5ef2aSThomas Huth 2532fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 2533fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2534fcf5ef2aSThomas Huth { \ 2535fcf5ef2aSThomas Huth TCGv EA; \ 2536fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || \ 2537fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { \ 2538fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2539fcf5ef2aSThomas Huth return; \ 2540fcf5ef2aSThomas Huth } \ 2541fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2542fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2543fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2544fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2545fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2546fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2547fcf5ef2aSThomas Huth } 2548fcf5ef2aSThomas Huth 2549fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 2550fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2551fcf5ef2aSThomas Huth { \ 2552fcf5ef2aSThomas Huth TCGv EA; \ 2553fcf5ef2aSThomas Huth chk; \ 2554fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2555fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2556fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2557fcf5ef2aSThomas Huth gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2558fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2559fcf5ef2aSThomas Huth } 2560fcf5ef2aSThomas Huth 2561fcf5ef2aSThomas Huth #define GEN_LDX(name, ldop, opc2, opc3, type) \ 2562fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2563fcf5ef2aSThomas Huth 2564fcf5ef2aSThomas Huth #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ 2565fcf5ef2aSThomas Huth GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2566fcf5ef2aSThomas Huth 2567fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 2568fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type); \ 2569fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type); \ 2570fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ 2571fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 2572fcf5ef2aSThomas Huth 2573fcf5ef2aSThomas Huth /* lbz lbzu lbzux lbzx */ 2574fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); 2575fcf5ef2aSThomas Huth /* lha lhau lhaux lhax */ 2576fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); 2577fcf5ef2aSThomas Huth /* lhz lhzu lhzux lhzx */ 2578fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); 2579fcf5ef2aSThomas Huth /* lwz lwzu lwzux lwzx */ 2580fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); 2581fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2582fcf5ef2aSThomas Huth /* lwaux */ 2583fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); 2584fcf5ef2aSThomas Huth /* lwax */ 2585fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); 2586fcf5ef2aSThomas Huth /* ldux */ 2587fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); 2588fcf5ef2aSThomas Huth /* ldx */ 2589fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); 2590fcf5ef2aSThomas Huth 2591fcf5ef2aSThomas Huth /* CI load/store variants */ 2592fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 2593fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) 2594fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 2595fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 2596fcf5ef2aSThomas Huth 2597fcf5ef2aSThomas Huth static void gen_ld(DisasContext *ctx) 2598fcf5ef2aSThomas Huth { 2599fcf5ef2aSThomas Huth TCGv EA; 2600fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2601fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0 || 2602fcf5ef2aSThomas Huth rA(ctx->opcode) == rD(ctx->opcode))) { 2603fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2604fcf5ef2aSThomas Huth return; 2605fcf5ef2aSThomas Huth } 2606fcf5ef2aSThomas Huth } 2607fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2608fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2609fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2610fcf5ef2aSThomas Huth if (ctx->opcode & 0x02) { 2611fcf5ef2aSThomas Huth /* lwa (lwau is undefined) */ 2612fcf5ef2aSThomas Huth gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2613fcf5ef2aSThomas Huth } else { 2614fcf5ef2aSThomas Huth /* ld - ldu */ 2615fcf5ef2aSThomas Huth gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); 2616fcf5ef2aSThomas Huth } 2617fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2618fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2619fcf5ef2aSThomas Huth tcg_temp_free(EA); 2620fcf5ef2aSThomas Huth } 2621fcf5ef2aSThomas Huth 2622fcf5ef2aSThomas Huth /* lq */ 2623fcf5ef2aSThomas Huth static void gen_lq(DisasContext *ctx) 2624fcf5ef2aSThomas Huth { 2625fcf5ef2aSThomas Huth int ra, rd; 262694bf2658SRichard Henderson TCGv EA, hi, lo; 2627fcf5ef2aSThomas Huth 2628fcf5ef2aSThomas Huth /* lq is a legal user mode instruction starting in ISA 2.07 */ 2629fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2630fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2631fcf5ef2aSThomas Huth 2632fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2633fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2634fcf5ef2aSThomas Huth return; 2635fcf5ef2aSThomas Huth } 2636fcf5ef2aSThomas Huth 2637fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2638fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2639fcf5ef2aSThomas Huth return; 2640fcf5ef2aSThomas Huth } 2641fcf5ef2aSThomas Huth ra = rA(ctx->opcode); 2642fcf5ef2aSThomas Huth rd = rD(ctx->opcode); 2643fcf5ef2aSThomas Huth if (unlikely((rd & 1) || rd == ra)) { 2644fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2645fcf5ef2aSThomas Huth return; 2646fcf5ef2aSThomas Huth } 2647fcf5ef2aSThomas Huth 2648fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2649fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2650fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x0F); 2651fcf5ef2aSThomas Huth 265294bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 265394bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 265494bf2658SRichard Henderson hi = cpu_gpr[rd]; 265594bf2658SRichard Henderson 265694bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 265794bf2658SRichard Henderson #ifdef CONFIG_ATOMIC128 265894bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 265994bf2658SRichard Henderson if (ctx->le_mode) { 266094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 266194bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 2662fcf5ef2aSThomas Huth } else { 266394bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 266494bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 266594bf2658SRichard Henderson } 266694bf2658SRichard Henderson tcg_temp_free_i32(oi); 266794bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 266894bf2658SRichard Henderson #else 266994bf2658SRichard Henderson /* Restart with exclusive lock. */ 267094bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 267194bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 267294bf2658SRichard Henderson #endif 267394bf2658SRichard Henderson } else if (ctx->le_mode) { 267494bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2675fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 267694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 267794bf2658SRichard Henderson } else { 267894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); 267994bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 268094bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2681fcf5ef2aSThomas Huth } 2682fcf5ef2aSThomas Huth tcg_temp_free(EA); 2683fcf5ef2aSThomas Huth } 2684fcf5ef2aSThomas Huth #endif 2685fcf5ef2aSThomas Huth 2686fcf5ef2aSThomas Huth /*** Integer store ***/ 2687fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 2688fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 2689fcf5ef2aSThomas Huth { \ 2690fcf5ef2aSThomas Huth TCGv EA; \ 2691fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2692fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2693fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2694fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2695fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2696fcf5ef2aSThomas Huth } 2697fcf5ef2aSThomas Huth 2698fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 2699fcf5ef2aSThomas Huth static void glue(gen_, stop##u)(DisasContext *ctx) \ 2700fcf5ef2aSThomas Huth { \ 2701fcf5ef2aSThomas Huth TCGv EA; \ 2702fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2703fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2704fcf5ef2aSThomas Huth return; \ 2705fcf5ef2aSThomas Huth } \ 2706fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2707fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2708fcf5ef2aSThomas Huth if (type == PPC_64B) \ 2709fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); \ 2710fcf5ef2aSThomas Huth else \ 2711fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0); \ 2712fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2713fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2714fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2715fcf5ef2aSThomas Huth } 2716fcf5ef2aSThomas Huth 2717fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 2718fcf5ef2aSThomas Huth static void glue(gen_, name##ux)(DisasContext *ctx) \ 2719fcf5ef2aSThomas Huth { \ 2720fcf5ef2aSThomas Huth TCGv EA; \ 2721fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { \ 2722fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ 2723fcf5ef2aSThomas Huth return; \ 2724fcf5ef2aSThomas Huth } \ 2725fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2726fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2727fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2728fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2729fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ 2730fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2731fcf5ef2aSThomas Huth } 2732fcf5ef2aSThomas Huth 2733fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 2734fcf5ef2aSThomas Huth static void glue(gen_, name##x)(DisasContext *ctx) \ 2735fcf5ef2aSThomas Huth { \ 2736fcf5ef2aSThomas Huth TCGv EA; \ 2737fcf5ef2aSThomas Huth chk; \ 2738fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); \ 2739fcf5ef2aSThomas Huth EA = tcg_temp_new(); \ 2740fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); \ 2741fcf5ef2aSThomas Huth gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ 2742fcf5ef2aSThomas Huth tcg_temp_free(EA); \ 2743fcf5ef2aSThomas Huth } 2744fcf5ef2aSThomas Huth #define GEN_STX(name, stop, opc2, opc3, type) \ 2745fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) 2746fcf5ef2aSThomas Huth 2747fcf5ef2aSThomas Huth #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ 2748fcf5ef2aSThomas Huth GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) 2749fcf5ef2aSThomas Huth 2750fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 2751fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type); \ 2752fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type); \ 2753fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type); \ 2754fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 2755fcf5ef2aSThomas Huth 2756fcf5ef2aSThomas Huth /* stb stbu stbux stbx */ 2757fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER); 2758fcf5ef2aSThomas Huth /* sth sthu sthux sthx */ 2759fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER); 2760fcf5ef2aSThomas Huth /* stw stwu stwux stwx */ 2761fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER); 2762fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2763fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); 2764fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); 2765fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 2766fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 2767fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 2768fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 2769fcf5ef2aSThomas Huth 2770fcf5ef2aSThomas Huth static void gen_std(DisasContext *ctx) 2771fcf5ef2aSThomas Huth { 2772fcf5ef2aSThomas Huth int rs; 2773fcf5ef2aSThomas Huth TCGv EA; 2774fcf5ef2aSThomas Huth 2775fcf5ef2aSThomas Huth rs = rS(ctx->opcode); 2776fcf5ef2aSThomas Huth if ((ctx->opcode & 0x3) == 0x2) { /* stq */ 2777fcf5ef2aSThomas Huth bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2778fcf5ef2aSThomas Huth bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; 2779f89ced5fSRichard Henderson TCGv hi, lo; 2780fcf5ef2aSThomas Huth 2781fcf5ef2aSThomas Huth if (!(ctx->insns_flags & PPC_64BX)) { 2782fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2783fcf5ef2aSThomas Huth } 2784fcf5ef2aSThomas Huth 2785fcf5ef2aSThomas Huth if (!legal_in_user_mode && ctx->pr) { 2786fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); 2787fcf5ef2aSThomas Huth return; 2788fcf5ef2aSThomas Huth } 2789fcf5ef2aSThomas Huth 2790fcf5ef2aSThomas Huth if (!le_is_supported && ctx->le_mode) { 2791fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2792fcf5ef2aSThomas Huth return; 2793fcf5ef2aSThomas Huth } 2794fcf5ef2aSThomas Huth 2795fcf5ef2aSThomas Huth if (unlikely(rs & 1)) { 2796fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2797fcf5ef2aSThomas Huth return; 2798fcf5ef2aSThomas Huth } 2799fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2800fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2801fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2802fcf5ef2aSThomas Huth 2803f89ced5fSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 2804f89ced5fSRichard Henderson lo = cpu_gpr[rs + 1]; 2805f89ced5fSRichard Henderson hi = cpu_gpr[rs]; 2806f89ced5fSRichard Henderson 2807f89ced5fSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 2808f89ced5fSRichard Henderson #ifdef CONFIG_ATOMIC128 2809f89ced5fSRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 2810f89ced5fSRichard Henderson if (ctx->le_mode) { 2811f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); 2812f89ced5fSRichard Henderson gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); 2813fcf5ef2aSThomas Huth } else { 2814f89ced5fSRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); 2815f89ced5fSRichard Henderson gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); 2816f89ced5fSRichard Henderson } 2817f89ced5fSRichard Henderson tcg_temp_free_i32(oi); 2818f89ced5fSRichard Henderson #else 2819f89ced5fSRichard Henderson /* Restart with exclusive lock. */ 2820f89ced5fSRichard Henderson gen_helper_exit_atomic(cpu_env); 2821f89ced5fSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 2822f89ced5fSRichard Henderson #endif 2823f89ced5fSRichard Henderson } else if (ctx->le_mode) { 2824f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); 2825fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 2826f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); 2827f89ced5fSRichard Henderson } else { 2828f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); 2829f89ced5fSRichard Henderson gen_addr_add(ctx, EA, EA, 8); 2830f89ced5fSRichard Henderson tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); 2831fcf5ef2aSThomas Huth } 2832fcf5ef2aSThomas Huth tcg_temp_free(EA); 2833fcf5ef2aSThomas Huth } else { 2834fcf5ef2aSThomas Huth /* std / stdu */ 2835fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 2836fcf5ef2aSThomas Huth if (unlikely(rA(ctx->opcode) == 0)) { 2837fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 2838fcf5ef2aSThomas Huth return; 2839fcf5ef2aSThomas Huth } 2840fcf5ef2aSThomas Huth } 2841fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2842fcf5ef2aSThomas Huth EA = tcg_temp_new(); 2843fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, EA, 0x03); 2844fcf5ef2aSThomas Huth gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); 2845fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) 2846fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); 2847fcf5ef2aSThomas Huth tcg_temp_free(EA); 2848fcf5ef2aSThomas Huth } 2849fcf5ef2aSThomas Huth } 2850fcf5ef2aSThomas Huth #endif 2851fcf5ef2aSThomas Huth /*** Integer load and store with byte reverse ***/ 2852fcf5ef2aSThomas Huth 2853fcf5ef2aSThomas Huth /* lhbrx */ 2854fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); 2855fcf5ef2aSThomas Huth 2856fcf5ef2aSThomas Huth /* lwbrx */ 2857fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); 2858fcf5ef2aSThomas Huth 2859fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 2860fcf5ef2aSThomas Huth /* ldbrx */ 2861fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); 2862fcf5ef2aSThomas Huth /* stdbrx */ 2863fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); 2864fcf5ef2aSThomas Huth #endif /* TARGET_PPC64 */ 2865fcf5ef2aSThomas Huth 2866fcf5ef2aSThomas Huth /* sthbrx */ 2867fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); 2868fcf5ef2aSThomas Huth /* stwbrx */ 2869fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); 2870fcf5ef2aSThomas Huth 2871fcf5ef2aSThomas Huth /*** Integer load and store multiple ***/ 2872fcf5ef2aSThomas Huth 2873fcf5ef2aSThomas Huth /* lmw */ 2874fcf5ef2aSThomas Huth static void gen_lmw(DisasContext *ctx) 2875fcf5ef2aSThomas Huth { 2876fcf5ef2aSThomas Huth TCGv t0; 2877fcf5ef2aSThomas Huth TCGv_i32 t1; 2878fcf5ef2aSThomas Huth 2879fcf5ef2aSThomas Huth if (ctx->le_mode) { 2880fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2881fcf5ef2aSThomas Huth return; 2882fcf5ef2aSThomas Huth } 2883fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2884fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2885fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2886fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2887fcf5ef2aSThomas Huth gen_helper_lmw(cpu_env, t0, t1); 2888fcf5ef2aSThomas Huth tcg_temp_free(t0); 2889fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2890fcf5ef2aSThomas Huth } 2891fcf5ef2aSThomas Huth 2892fcf5ef2aSThomas Huth /* stmw */ 2893fcf5ef2aSThomas Huth static void gen_stmw(DisasContext *ctx) 2894fcf5ef2aSThomas Huth { 2895fcf5ef2aSThomas Huth TCGv t0; 2896fcf5ef2aSThomas Huth TCGv_i32 t1; 2897fcf5ef2aSThomas Huth 2898fcf5ef2aSThomas Huth if (ctx->le_mode) { 2899fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2900fcf5ef2aSThomas Huth return; 2901fcf5ef2aSThomas Huth } 2902fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2903fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2904fcf5ef2aSThomas Huth t1 = tcg_const_i32(rS(ctx->opcode)); 2905fcf5ef2aSThomas Huth gen_addr_imm_index(ctx, t0, 0); 2906fcf5ef2aSThomas Huth gen_helper_stmw(cpu_env, t0, t1); 2907fcf5ef2aSThomas Huth tcg_temp_free(t0); 2908fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2909fcf5ef2aSThomas Huth } 2910fcf5ef2aSThomas Huth 2911fcf5ef2aSThomas Huth /*** Integer load and store strings ***/ 2912fcf5ef2aSThomas Huth 2913fcf5ef2aSThomas Huth /* lswi */ 2914fcf5ef2aSThomas Huth /* PowerPC32 specification says we must generate an exception if 2915fcf5ef2aSThomas Huth * rA is in the range of registers to be loaded. 2916fcf5ef2aSThomas Huth * In an other hand, IBM says this is valid, but rA won't be loaded. 2917fcf5ef2aSThomas Huth * For now, I'll follow the spec... 2918fcf5ef2aSThomas Huth */ 2919fcf5ef2aSThomas Huth static void gen_lswi(DisasContext *ctx) 2920fcf5ef2aSThomas Huth { 2921fcf5ef2aSThomas Huth TCGv t0; 2922fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2923fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2924fcf5ef2aSThomas Huth int start = rD(ctx->opcode); 2925fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 2926fcf5ef2aSThomas Huth int nr; 2927fcf5ef2aSThomas Huth 2928fcf5ef2aSThomas Huth if (ctx->le_mode) { 2929fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2930fcf5ef2aSThomas Huth return; 2931fcf5ef2aSThomas Huth } 2932fcf5ef2aSThomas Huth if (nb == 0) 2933fcf5ef2aSThomas Huth nb = 32; 2934f0704d78SMarc-André Lureau nr = DIV_ROUND_UP(nb, 4); 2935fcf5ef2aSThomas Huth if (unlikely(lsw_reg_in_range(start, nr, ra))) { 2936fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); 2937fcf5ef2aSThomas Huth return; 2938fcf5ef2aSThomas Huth } 2939fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2940fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2941fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2942fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2943fcf5ef2aSThomas Huth t2 = tcg_const_i32(start); 2944fcf5ef2aSThomas Huth gen_helper_lsw(cpu_env, t0, t1, t2); 2945fcf5ef2aSThomas Huth tcg_temp_free(t0); 2946fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2947fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2948fcf5ef2aSThomas Huth } 2949fcf5ef2aSThomas Huth 2950fcf5ef2aSThomas Huth /* lswx */ 2951fcf5ef2aSThomas Huth static void gen_lswx(DisasContext *ctx) 2952fcf5ef2aSThomas Huth { 2953fcf5ef2aSThomas Huth TCGv t0; 2954fcf5ef2aSThomas Huth TCGv_i32 t1, t2, t3; 2955fcf5ef2aSThomas Huth 2956fcf5ef2aSThomas Huth if (ctx->le_mode) { 2957fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2958fcf5ef2aSThomas Huth return; 2959fcf5ef2aSThomas Huth } 2960fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2961fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2962fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 2963fcf5ef2aSThomas Huth t1 = tcg_const_i32(rD(ctx->opcode)); 2964fcf5ef2aSThomas Huth t2 = tcg_const_i32(rA(ctx->opcode)); 2965fcf5ef2aSThomas Huth t3 = tcg_const_i32(rB(ctx->opcode)); 2966fcf5ef2aSThomas Huth gen_helper_lswx(cpu_env, t0, t1, t2, t3); 2967fcf5ef2aSThomas Huth tcg_temp_free(t0); 2968fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2969fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2970fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 2971fcf5ef2aSThomas Huth } 2972fcf5ef2aSThomas Huth 2973fcf5ef2aSThomas Huth /* stswi */ 2974fcf5ef2aSThomas Huth static void gen_stswi(DisasContext *ctx) 2975fcf5ef2aSThomas Huth { 2976fcf5ef2aSThomas Huth TCGv t0; 2977fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 2978fcf5ef2aSThomas Huth int nb = NB(ctx->opcode); 2979fcf5ef2aSThomas Huth 2980fcf5ef2aSThomas Huth if (ctx->le_mode) { 2981fcf5ef2aSThomas Huth gen_align_no_le(ctx); 2982fcf5ef2aSThomas Huth return; 2983fcf5ef2aSThomas Huth } 2984fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 2985fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 2986fcf5ef2aSThomas Huth gen_addr_register(ctx, t0); 2987fcf5ef2aSThomas Huth if (nb == 0) 2988fcf5ef2aSThomas Huth nb = 32; 2989fcf5ef2aSThomas Huth t1 = tcg_const_i32(nb); 2990fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 2991fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 2992fcf5ef2aSThomas Huth tcg_temp_free(t0); 2993fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 2994fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 2995fcf5ef2aSThomas Huth } 2996fcf5ef2aSThomas Huth 2997fcf5ef2aSThomas Huth /* stswx */ 2998fcf5ef2aSThomas Huth static void gen_stswx(DisasContext *ctx) 2999fcf5ef2aSThomas Huth { 3000fcf5ef2aSThomas Huth TCGv t0; 3001fcf5ef2aSThomas Huth TCGv_i32 t1, t2; 3002fcf5ef2aSThomas Huth 3003fcf5ef2aSThomas Huth if (ctx->le_mode) { 3004fcf5ef2aSThomas Huth gen_align_no_le(ctx); 3005fcf5ef2aSThomas Huth return; 3006fcf5ef2aSThomas Huth } 3007fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_INT); 3008fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 3009fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 3010fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 3011fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_xer); 3012fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, t1, 0x7F); 3013fcf5ef2aSThomas Huth t2 = tcg_const_i32(rS(ctx->opcode)); 3014fcf5ef2aSThomas Huth gen_helper_stsw(cpu_env, t0, t1, t2); 3015fcf5ef2aSThomas Huth tcg_temp_free(t0); 3016fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3017fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 3018fcf5ef2aSThomas Huth } 3019fcf5ef2aSThomas Huth 3020fcf5ef2aSThomas Huth /*** Memory synchronisation ***/ 3021fcf5ef2aSThomas Huth /* eieio */ 3022fcf5ef2aSThomas Huth static void gen_eieio(DisasContext *ctx) 3023fcf5ef2aSThomas Huth { 3024c8fd8373SCédric Le Goater TCGBar bar = TCG_MO_LD_ST; 3025c8fd8373SCédric Le Goater 3026c8fd8373SCédric Le Goater /* 3027c8fd8373SCédric Le Goater * POWER9 has a eieio instruction variant using bit 6 as a hint to 3028c8fd8373SCédric Le Goater * tell the CPU it is a store-forwarding barrier. 3029c8fd8373SCédric Le Goater */ 3030c8fd8373SCédric Le Goater if (ctx->opcode & 0x2000000) { 3031c8fd8373SCédric Le Goater /* 3032c8fd8373SCédric Le Goater * ISA says that "Reserved fields in instructions are ignored 3033c8fd8373SCédric Le Goater * by the processor". So ignore the bit 6 on non-POWER9 CPU but 3034c8fd8373SCédric Le Goater * as this is not an instruction software should be using, 3035c8fd8373SCédric Le Goater * complain to the user. 3036c8fd8373SCédric Le Goater */ 3037c8fd8373SCédric Le Goater if (!(ctx->insns_flags2 & PPC2_ISA300)) { 3038c8fd8373SCédric Le Goater qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" 3039c8fd8373SCédric Le Goater TARGET_FMT_lx "\n", ctx->base.pc_next - 4); 3040c8fd8373SCédric Le Goater } else { 3041c8fd8373SCédric Le Goater bar = TCG_MO_ST_LD; 3042c8fd8373SCédric Le Goater } 3043c8fd8373SCédric Le Goater } 3044c8fd8373SCédric Le Goater 3045c8fd8373SCédric Le Goater tcg_gen_mb(bar | TCG_BAR_SC); 3046fcf5ef2aSThomas Huth } 3047fcf5ef2aSThomas Huth 3048fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 3049fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) 3050fcf5ef2aSThomas Huth { 3051fcf5ef2aSThomas Huth TCGv_i32 t; 3052fcf5ef2aSThomas Huth TCGLabel *l; 3053fcf5ef2aSThomas Huth 3054fcf5ef2aSThomas Huth if (!ctx->lazy_tlb_flush) { 3055fcf5ef2aSThomas Huth return; 3056fcf5ef2aSThomas Huth } 3057fcf5ef2aSThomas Huth l = gen_new_label(); 3058fcf5ef2aSThomas Huth t = tcg_temp_new_i32(); 3059fcf5ef2aSThomas Huth tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 3060fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); 3061fcf5ef2aSThomas Huth if (global) { 3062fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_global(cpu_env); 3063fcf5ef2aSThomas Huth } else { 3064fcf5ef2aSThomas Huth gen_helper_check_tlb_flush_local(cpu_env); 3065fcf5ef2aSThomas Huth } 3066fcf5ef2aSThomas Huth gen_set_label(l); 3067fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3068fcf5ef2aSThomas Huth } 3069fcf5ef2aSThomas Huth #else 3070fcf5ef2aSThomas Huth static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } 3071fcf5ef2aSThomas Huth #endif 3072fcf5ef2aSThomas Huth 3073fcf5ef2aSThomas Huth /* isync */ 3074fcf5ef2aSThomas Huth static void gen_isync(DisasContext *ctx) 3075fcf5ef2aSThomas Huth { 3076fcf5ef2aSThomas Huth /* 3077fcf5ef2aSThomas Huth * We need to check for a pending TLB flush. This can only happen in 3078fcf5ef2aSThomas Huth * kernel mode however so check MSR_PR 3079fcf5ef2aSThomas Huth */ 3080fcf5ef2aSThomas Huth if (!ctx->pr) { 3081fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, false); 3082fcf5ef2aSThomas Huth } 30834771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3084fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3085fcf5ef2aSThomas Huth } 3086fcf5ef2aSThomas Huth 3087fcf5ef2aSThomas Huth #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) 3088fcf5ef2aSThomas Huth 30892a4e6c1bSRichard Henderson static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) 30902a4e6c1bSRichard Henderson { 30912a4e6c1bSRichard Henderson TCGv gpr = cpu_gpr[rD(ctx->opcode)]; 30922a4e6c1bSRichard Henderson TCGv t0 = tcg_temp_new(); 30932a4e6c1bSRichard Henderson 30942a4e6c1bSRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 30952a4e6c1bSRichard Henderson gen_addr_reg_index(ctx, t0); 30962a4e6c1bSRichard Henderson tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); 30972a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve, t0); 30982a4e6c1bSRichard Henderson tcg_gen_mov_tl(cpu_reserve_val, gpr); 30992a4e6c1bSRichard Henderson tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); 31002a4e6c1bSRichard Henderson tcg_temp_free(t0); 31012a4e6c1bSRichard Henderson } 31022a4e6c1bSRichard Henderson 3103fcf5ef2aSThomas Huth #define LARX(name, memop) \ 3104fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3105fcf5ef2aSThomas Huth { \ 31062a4e6c1bSRichard Henderson gen_load_locked(ctx, memop); \ 3107fcf5ef2aSThomas Huth } 3108fcf5ef2aSThomas Huth 3109fcf5ef2aSThomas Huth /* lwarx */ 3110fcf5ef2aSThomas Huth LARX(lbarx, DEF_MEMOP(MO_UB)) 3111fcf5ef2aSThomas Huth LARX(lharx, DEF_MEMOP(MO_UW)) 3112fcf5ef2aSThomas Huth LARX(lwarx, DEF_MEMOP(MO_UL)) 3113fcf5ef2aSThomas Huth 311420923c1dSRichard Henderson static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, 311520923c1dSRichard Henderson TCGv EA, TCGCond cond, int addend) 311620923c1dSRichard Henderson { 311720923c1dSRichard Henderson TCGv t = tcg_temp_new(); 311820923c1dSRichard Henderson TCGv t2 = tcg_temp_new(); 311920923c1dSRichard Henderson TCGv u = tcg_temp_new(); 312020923c1dSRichard Henderson 312120923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 312220923c1dSRichard Henderson tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); 312320923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); 312420923c1dSRichard Henderson tcg_gen_addi_tl(u, t, addend); 312520923c1dSRichard Henderson 312620923c1dSRichard Henderson /* E.g. for fetch and increment bounded... */ 312720923c1dSRichard Henderson /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ 312820923c1dSRichard Henderson tcg_gen_movcond_tl(cond, u, t, t2, u, t); 312920923c1dSRichard Henderson tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); 313020923c1dSRichard Henderson 313120923c1dSRichard Henderson /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ 313220923c1dSRichard Henderson tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); 313320923c1dSRichard Henderson tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); 313420923c1dSRichard Henderson 313520923c1dSRichard Henderson tcg_temp_free(t); 313620923c1dSRichard Henderson tcg_temp_free(t2); 313720923c1dSRichard Henderson tcg_temp_free(u); 313820923c1dSRichard Henderson } 313920923c1dSRichard Henderson 314020ba8504SRichard Henderson static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) 314120ba8504SRichard Henderson { 314220ba8504SRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 314320ba8504SRichard Henderson TCGv EA = tcg_temp_new(); 314420923c1dSRichard Henderson int rt = rD(ctx->opcode); 314520923c1dSRichard Henderson bool need_serial; 314620ba8504SRichard Henderson TCGv src, dst; 314720ba8504SRichard Henderson 314820ba8504SRichard Henderson gen_addr_register(ctx, EA); 314920923c1dSRichard Henderson dst = cpu_gpr[rt]; 315020923c1dSRichard Henderson src = cpu_gpr[(rt + 1) & 31]; 315120ba8504SRichard Henderson 315220923c1dSRichard Henderson need_serial = false; 315320ba8504SRichard Henderson memop |= MO_ALIGN; 315420ba8504SRichard Henderson switch (gpr_FC) { 315520ba8504SRichard Henderson case 0: /* Fetch and add */ 315620ba8504SRichard Henderson tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); 315720ba8504SRichard Henderson break; 315820ba8504SRichard Henderson case 1: /* Fetch and xor */ 315920ba8504SRichard Henderson tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); 316020ba8504SRichard Henderson break; 316120ba8504SRichard Henderson case 2: /* Fetch and or */ 316220ba8504SRichard Henderson tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); 316320ba8504SRichard Henderson break; 316420ba8504SRichard Henderson case 3: /* Fetch and 'and' */ 316520ba8504SRichard Henderson tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); 316620ba8504SRichard Henderson break; 3167b8ce0f86SRichard Henderson case 4: /* Fetch and max unsigned */ 3168b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); 3169b8ce0f86SRichard Henderson break; 3170b8ce0f86SRichard Henderson case 5: /* Fetch and max signed */ 3171b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); 3172b8ce0f86SRichard Henderson break; 3173b8ce0f86SRichard Henderson case 6: /* Fetch and min unsigned */ 3174b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); 3175b8ce0f86SRichard Henderson break; 3176b8ce0f86SRichard Henderson case 7: /* Fetch and min signed */ 3177b8ce0f86SRichard Henderson tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); 3178b8ce0f86SRichard Henderson break; 317920ba8504SRichard Henderson case 8: /* Swap */ 318020ba8504SRichard Henderson tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); 318120ba8504SRichard Henderson break; 318220923c1dSRichard Henderson 318320923c1dSRichard Henderson case 16: /* Compare and swap not equal */ 318420923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 318520923c1dSRichard Henderson need_serial = true; 318620923c1dSRichard Henderson } else { 318720923c1dSRichard Henderson TCGv t0 = tcg_temp_new(); 318820923c1dSRichard Henderson TCGv t1 = tcg_temp_new(); 318920923c1dSRichard Henderson 319020923c1dSRichard Henderson tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); 319120923c1dSRichard Henderson if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { 319220923c1dSRichard Henderson tcg_gen_mov_tl(t1, src); 319320923c1dSRichard Henderson } else { 319420923c1dSRichard Henderson tcg_gen_ext32u_tl(t1, src); 319520923c1dSRichard Henderson } 319620923c1dSRichard Henderson tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, 319720923c1dSRichard Henderson cpu_gpr[(rt + 2) & 31], t0); 319820923c1dSRichard Henderson tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); 319920923c1dSRichard Henderson tcg_gen_mov_tl(dst, t0); 320020923c1dSRichard Henderson 320120923c1dSRichard Henderson tcg_temp_free(t0); 320220923c1dSRichard Henderson tcg_temp_free(t1); 320320923c1dSRichard Henderson } 320420ba8504SRichard Henderson break; 320520923c1dSRichard Henderson 320620923c1dSRichard Henderson case 24: /* Fetch and increment bounded */ 320720923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 320820923c1dSRichard Henderson need_serial = true; 320920923c1dSRichard Henderson } else { 321020923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); 321120923c1dSRichard Henderson } 321220923c1dSRichard Henderson break; 321320923c1dSRichard Henderson case 25: /* Fetch and increment equal */ 321420923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 321520923c1dSRichard Henderson need_serial = true; 321620923c1dSRichard Henderson } else { 321720923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); 321820923c1dSRichard Henderson } 321920923c1dSRichard Henderson break; 322020923c1dSRichard Henderson case 28: /* Fetch and decrement bounded */ 322120923c1dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 322220923c1dSRichard Henderson need_serial = true; 322320923c1dSRichard Henderson } else { 322420923c1dSRichard Henderson gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); 322520923c1dSRichard Henderson } 322620923c1dSRichard Henderson break; 322720923c1dSRichard Henderson 322820ba8504SRichard Henderson default: 322920ba8504SRichard Henderson /* invoke data storage error handler */ 323020ba8504SRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 323120ba8504SRichard Henderson } 323220ba8504SRichard Henderson tcg_temp_free(EA); 323320923c1dSRichard Henderson 323420923c1dSRichard Henderson if (need_serial) { 323520923c1dSRichard Henderson /* Restart with exclusive lock. */ 323620923c1dSRichard Henderson gen_helper_exit_atomic(cpu_env); 323720923c1dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 323820923c1dSRichard Henderson } 3239a68a6146SBalamuruhan S } 3240a68a6146SBalamuruhan S 324120ba8504SRichard Henderson static void gen_lwat(DisasContext *ctx) 324220ba8504SRichard Henderson { 324320ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); 324420ba8504SRichard Henderson } 324520ba8504SRichard Henderson 324620ba8504SRichard Henderson #ifdef TARGET_PPC64 324720ba8504SRichard Henderson static void gen_ldat(DisasContext *ctx) 324820ba8504SRichard Henderson { 324920ba8504SRichard Henderson gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); 325020ba8504SRichard Henderson } 3251a68a6146SBalamuruhan S #endif 3252a68a6146SBalamuruhan S 32539deb041cSRichard Henderson static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) 32549deb041cSRichard Henderson { 32559deb041cSRichard Henderson uint32_t gpr_FC = FC(ctx->opcode); 32569deb041cSRichard Henderson TCGv EA = tcg_temp_new(); 32579deb041cSRichard Henderson TCGv src, discard; 32589deb041cSRichard Henderson 32599deb041cSRichard Henderson gen_addr_register(ctx, EA); 32609deb041cSRichard Henderson src = cpu_gpr[rD(ctx->opcode)]; 32619deb041cSRichard Henderson discard = tcg_temp_new(); 32629deb041cSRichard Henderson 32639deb041cSRichard Henderson memop |= MO_ALIGN; 32649deb041cSRichard Henderson switch (gpr_FC) { 32659deb041cSRichard Henderson case 0: /* add and Store */ 32669deb041cSRichard Henderson tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 32679deb041cSRichard Henderson break; 32689deb041cSRichard Henderson case 1: /* xor and Store */ 32699deb041cSRichard Henderson tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 32709deb041cSRichard Henderson break; 32719deb041cSRichard Henderson case 2: /* Or and Store */ 32729deb041cSRichard Henderson tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 32739deb041cSRichard Henderson break; 32749deb041cSRichard Henderson case 3: /* 'and' and Store */ 32759deb041cSRichard Henderson tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 32769deb041cSRichard Henderson break; 32779deb041cSRichard Henderson case 4: /* Store max unsigned */ 3278b8ce0f86SRichard Henderson tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3279b8ce0f86SRichard Henderson break; 32809deb041cSRichard Henderson case 5: /* Store max signed */ 3281b8ce0f86SRichard Henderson tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3282b8ce0f86SRichard Henderson break; 32839deb041cSRichard Henderson case 6: /* Store min unsigned */ 3284b8ce0f86SRichard Henderson tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3285b8ce0f86SRichard Henderson break; 32869deb041cSRichard Henderson case 7: /* Store min signed */ 3287b8ce0f86SRichard Henderson tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); 3288b8ce0f86SRichard Henderson break; 32899deb041cSRichard Henderson case 24: /* Store twin */ 32907fbc2b20SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 32917fbc2b20SRichard Henderson /* Restart with exclusive lock. */ 32927fbc2b20SRichard Henderson gen_helper_exit_atomic(cpu_env); 32937fbc2b20SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 32947fbc2b20SRichard Henderson } else { 32957fbc2b20SRichard Henderson TCGv t = tcg_temp_new(); 32967fbc2b20SRichard Henderson TCGv t2 = tcg_temp_new(); 32977fbc2b20SRichard Henderson TCGv s = tcg_temp_new(); 32987fbc2b20SRichard Henderson TCGv s2 = tcg_temp_new(); 32997fbc2b20SRichard Henderson TCGv ea_plus_s = tcg_temp_new(); 33007fbc2b20SRichard Henderson 33017fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); 33027fbc2b20SRichard Henderson tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); 33037fbc2b20SRichard Henderson tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); 33047fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); 33057fbc2b20SRichard Henderson tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); 33067fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); 33077fbc2b20SRichard Henderson tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); 33087fbc2b20SRichard Henderson 33097fbc2b20SRichard Henderson tcg_temp_free(ea_plus_s); 33107fbc2b20SRichard Henderson tcg_temp_free(s2); 33117fbc2b20SRichard Henderson tcg_temp_free(s); 33127fbc2b20SRichard Henderson tcg_temp_free(t2); 33137fbc2b20SRichard Henderson tcg_temp_free(t); 33147fbc2b20SRichard Henderson } 33159deb041cSRichard Henderson break; 33169deb041cSRichard Henderson default: 33179deb041cSRichard Henderson /* invoke data storage error handler */ 33189deb041cSRichard Henderson gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); 33199deb041cSRichard Henderson } 33209deb041cSRichard Henderson tcg_temp_free(discard); 33219deb041cSRichard Henderson tcg_temp_free(EA); 3322a3401188SBalamuruhan S } 3323a3401188SBalamuruhan S 33249deb041cSRichard Henderson static void gen_stwat(DisasContext *ctx) 33259deb041cSRichard Henderson { 33269deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); 33279deb041cSRichard Henderson } 33289deb041cSRichard Henderson 33299deb041cSRichard Henderson #ifdef TARGET_PPC64 33309deb041cSRichard Henderson static void gen_stdat(DisasContext *ctx) 33319deb041cSRichard Henderson { 33329deb041cSRichard Henderson gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); 33339deb041cSRichard Henderson } 3334a3401188SBalamuruhan S #endif 3335a3401188SBalamuruhan S 3336d8b86898SRichard Henderson static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) 3337fcf5ef2aSThomas Huth { 3338253ce7b2SNikunj A Dadhania TCGLabel *l1 = gen_new_label(); 3339253ce7b2SNikunj A Dadhania TCGLabel *l2 = gen_new_label(); 3340d8b86898SRichard Henderson TCGv t0 = tcg_temp_new(); 3341d8b86898SRichard Henderson int reg = rS(ctx->opcode); 3342fcf5ef2aSThomas Huth 3343d8b86898SRichard Henderson gen_set_access_type(ctx, ACCESS_RES); 3344d8b86898SRichard Henderson gen_addr_reg_index(ctx, t0); 3345d8b86898SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); 3346d8b86898SRichard Henderson tcg_temp_free(t0); 3347253ce7b2SNikunj A Dadhania 3348253ce7b2SNikunj A Dadhania t0 = tcg_temp_new(); 3349253ce7b2SNikunj A Dadhania tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, 3350253ce7b2SNikunj A Dadhania cpu_gpr[reg], ctx->mem_idx, 3351253ce7b2SNikunj A Dadhania DEF_MEMOP(memop) | MO_ALIGN); 3352253ce7b2SNikunj A Dadhania tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); 3353253ce7b2SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); 3354253ce7b2SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_so); 3355253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], t0); 3356253ce7b2SNikunj A Dadhania tcg_temp_free(t0); 3357253ce7b2SNikunj A Dadhania tcg_gen_br(l2); 3358253ce7b2SNikunj A Dadhania 3359fcf5ef2aSThomas Huth gen_set_label(l1); 33604771df23SNikunj A Dadhania 33614771df23SNikunj A Dadhania /* Address mismatch implies failure. But we still need to provide the 33624771df23SNikunj A Dadhania memory barrier semantics of the instruction. */ 33634771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); 3364253ce7b2SNikunj A Dadhania tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 3365253ce7b2SNikunj A Dadhania 3366253ce7b2SNikunj A Dadhania gen_set_label(l2); 3367fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_reserve, -1); 3368fcf5ef2aSThomas Huth } 3369fcf5ef2aSThomas Huth 3370fcf5ef2aSThomas Huth #define STCX(name, memop) \ 3371fcf5ef2aSThomas Huth static void gen_##name(DisasContext *ctx) \ 3372fcf5ef2aSThomas Huth { \ 3373d8b86898SRichard Henderson gen_conditional_store(ctx, memop); \ 3374fcf5ef2aSThomas Huth } 3375fcf5ef2aSThomas Huth 3376fcf5ef2aSThomas Huth STCX(stbcx_, DEF_MEMOP(MO_UB)) 3377fcf5ef2aSThomas Huth STCX(sthcx_, DEF_MEMOP(MO_UW)) 3378fcf5ef2aSThomas Huth STCX(stwcx_, DEF_MEMOP(MO_UL)) 3379fcf5ef2aSThomas Huth 3380fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3381fcf5ef2aSThomas Huth /* ldarx */ 3382fcf5ef2aSThomas Huth LARX(ldarx, DEF_MEMOP(MO_Q)) 3383fcf5ef2aSThomas Huth /* stdcx. */ 3384fcf5ef2aSThomas Huth STCX(stdcx_, DEF_MEMOP(MO_Q)) 3385fcf5ef2aSThomas Huth 3386fcf5ef2aSThomas Huth /* lqarx */ 3387fcf5ef2aSThomas Huth static void gen_lqarx(DisasContext *ctx) 3388fcf5ef2aSThomas Huth { 3389fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 339094bf2658SRichard Henderson TCGv EA, hi, lo; 3391fcf5ef2aSThomas Huth 3392fcf5ef2aSThomas Huth if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || 3393fcf5ef2aSThomas Huth (rd == rB(ctx->opcode)))) { 3394fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3395fcf5ef2aSThomas Huth return; 3396fcf5ef2aSThomas Huth } 3397fcf5ef2aSThomas Huth 3398fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 339994bf2658SRichard Henderson EA = tcg_temp_new(); 3400fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 340194bf2658SRichard Henderson 340294bf2658SRichard Henderson /* Note that the low part is always in RD+1, even in LE mode. */ 340394bf2658SRichard Henderson lo = cpu_gpr[rd + 1]; 340494bf2658SRichard Henderson hi = cpu_gpr[rd]; 340594bf2658SRichard Henderson 340694bf2658SRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 340794bf2658SRichard Henderson #ifdef CONFIG_ATOMIC128 340894bf2658SRichard Henderson TCGv_i32 oi = tcg_temp_new_i32(); 340994bf2658SRichard Henderson if (ctx->le_mode) { 341094bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, 341194bf2658SRichard Henderson ctx->mem_idx)); 341294bf2658SRichard Henderson gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); 3413fcf5ef2aSThomas Huth } else { 341494bf2658SRichard Henderson tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, 341594bf2658SRichard Henderson ctx->mem_idx)); 341694bf2658SRichard Henderson gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); 3417fcf5ef2aSThomas Huth } 341894bf2658SRichard Henderson tcg_temp_free_i32(oi); 341994bf2658SRichard Henderson tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); 342094bf2658SRichard Henderson #else 342194bf2658SRichard Henderson /* Restart with exclusive lock. */ 342294bf2658SRichard Henderson gen_helper_exit_atomic(cpu_env); 342394bf2658SRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 342494bf2658SRichard Henderson tcg_temp_free(EA); 342594bf2658SRichard Henderson return; 342694bf2658SRichard Henderson #endif 342794bf2658SRichard Henderson } else if (ctx->le_mode) { 342894bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); 3429fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_reserve, EA); 3430fcf5ef2aSThomas Huth gen_addr_add(ctx, EA, EA, 8); 343194bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); 343294bf2658SRichard Henderson } else { 343394bf2658SRichard Henderson tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); 343494bf2658SRichard Henderson tcg_gen_mov_tl(cpu_reserve, EA); 343594bf2658SRichard Henderson gen_addr_add(ctx, EA, EA, 8); 343694bf2658SRichard Henderson tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); 343794bf2658SRichard Henderson } 3438fcf5ef2aSThomas Huth tcg_temp_free(EA); 343994bf2658SRichard Henderson 344094bf2658SRichard Henderson tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); 344194bf2658SRichard Henderson tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); 3442fcf5ef2aSThomas Huth } 3443fcf5ef2aSThomas Huth 3444fcf5ef2aSThomas Huth /* stqcx. */ 3445fcf5ef2aSThomas Huth static void gen_stqcx_(DisasContext *ctx) 3446fcf5ef2aSThomas Huth { 34474a9b3c5dSRichard Henderson int rs = rS(ctx->opcode); 34484a9b3c5dSRichard Henderson TCGv EA, hi, lo; 3449fcf5ef2aSThomas Huth 34504a9b3c5dSRichard Henderson if (unlikely(rs & 1)) { 3451fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3452fcf5ef2aSThomas Huth return; 3453fcf5ef2aSThomas Huth } 34544a9b3c5dSRichard Henderson 3455fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_RES); 34564a9b3c5dSRichard Henderson EA = tcg_temp_new(); 3457fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 3458fcf5ef2aSThomas Huth 34594a9b3c5dSRichard Henderson /* Note that the low part is always in RS+1, even in LE mode. */ 34604a9b3c5dSRichard Henderson lo = cpu_gpr[rs + 1]; 34614a9b3c5dSRichard Henderson hi = cpu_gpr[rs]; 3462fcf5ef2aSThomas Huth 34634a9b3c5dSRichard Henderson if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { 34644a9b3c5dSRichard Henderson TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); 34654a9b3c5dSRichard Henderson #ifdef CONFIG_ATOMIC128 34664a9b3c5dSRichard Henderson if (ctx->le_mode) { 34674a9b3c5dSRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); 3468fcf5ef2aSThomas Huth } else { 34694a9b3c5dSRichard Henderson gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); 3470fcf5ef2aSThomas Huth } 34714a9b3c5dSRichard Henderson #else 34724a9b3c5dSRichard Henderson /* Restart with exclusive lock. */ 34734a9b3c5dSRichard Henderson gen_helper_exit_atomic(cpu_env); 34744a9b3c5dSRichard Henderson ctx->base.is_jmp = DISAS_NORETURN; 3475fcf5ef2aSThomas Huth #endif 3476fcf5ef2aSThomas Huth tcg_temp_free(EA); 34774a9b3c5dSRichard Henderson tcg_temp_free_i32(oi); 34784a9b3c5dSRichard Henderson } else { 34794a9b3c5dSRichard Henderson TCGLabel *lab_fail = gen_new_label(); 34804a9b3c5dSRichard Henderson TCGLabel *lab_over = gen_new_label(); 34814a9b3c5dSRichard Henderson TCGv_i64 t0 = tcg_temp_new_i64(); 34824a9b3c5dSRichard Henderson TCGv_i64 t1 = tcg_temp_new_i64(); 3483fcf5ef2aSThomas Huth 34844a9b3c5dSRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); 34854a9b3c5dSRichard Henderson tcg_temp_free(EA); 34864a9b3c5dSRichard Henderson 34874a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, cpu_reserve); 34884a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 34894a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val2) 34904a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val))); 34914a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 34924a9b3c5dSRichard Henderson 34934a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 34944a9b3c5dSRichard Henderson gen_qemu_ld64_i64(ctx, t0, t0); 34954a9b3c5dSRichard Henderson tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode 34964a9b3c5dSRichard Henderson ? offsetof(CPUPPCState, reserve_val) 34974a9b3c5dSRichard Henderson : offsetof(CPUPPCState, reserve_val2))); 34984a9b3c5dSRichard Henderson tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); 34994a9b3c5dSRichard Henderson 35004a9b3c5dSRichard Henderson /* Success */ 35014a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); 35024a9b3c5dSRichard Henderson tcg_gen_addi_i64(t0, cpu_reserve, 8); 35034a9b3c5dSRichard Henderson gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); 35044a9b3c5dSRichard Henderson 35054a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35064a9b3c5dSRichard Henderson tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 35074a9b3c5dSRichard Henderson tcg_gen_br(lab_over); 35084a9b3c5dSRichard Henderson 35094a9b3c5dSRichard Henderson gen_set_label(lab_fail); 35104a9b3c5dSRichard Henderson tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 35114a9b3c5dSRichard Henderson 35124a9b3c5dSRichard Henderson gen_set_label(lab_over); 35134a9b3c5dSRichard Henderson tcg_gen_movi_tl(cpu_reserve, -1); 35144a9b3c5dSRichard Henderson tcg_temp_free_i64(t0); 35154a9b3c5dSRichard Henderson tcg_temp_free_i64(t1); 35164a9b3c5dSRichard Henderson } 35174a9b3c5dSRichard Henderson } 3518fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 3519fcf5ef2aSThomas Huth 3520fcf5ef2aSThomas Huth /* sync */ 3521fcf5ef2aSThomas Huth static void gen_sync(DisasContext *ctx) 3522fcf5ef2aSThomas Huth { 3523fcf5ef2aSThomas Huth uint32_t l = (ctx->opcode >> 21) & 3; 3524fcf5ef2aSThomas Huth 3525fcf5ef2aSThomas Huth /* 3526fcf5ef2aSThomas Huth * We may need to check for a pending TLB flush. 3527fcf5ef2aSThomas Huth * 3528fcf5ef2aSThomas Huth * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. 3529fcf5ef2aSThomas Huth * 3530fcf5ef2aSThomas Huth * Additionally, this can only happen in kernel mode however so 3531fcf5ef2aSThomas Huth * check MSR_PR as well. 3532fcf5ef2aSThomas Huth */ 3533fcf5ef2aSThomas Huth if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { 3534fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 3535fcf5ef2aSThomas Huth } 35364771df23SNikunj A Dadhania tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 3537fcf5ef2aSThomas Huth } 3538fcf5ef2aSThomas Huth 3539fcf5ef2aSThomas Huth /* wait */ 3540fcf5ef2aSThomas Huth static void gen_wait(DisasContext *ctx) 3541fcf5ef2aSThomas Huth { 3542fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(1); 3543fcf5ef2aSThomas Huth tcg_gen_st_i32(t0, cpu_env, 3544fcf5ef2aSThomas Huth -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); 3545fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3546fcf5ef2aSThomas Huth /* Stop translation, as the CPU is supposed to sleep from now */ 3547b6bac4bcSEmilio G. Cota gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); 3548fcf5ef2aSThomas Huth } 3549fcf5ef2aSThomas Huth 3550fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3551fcf5ef2aSThomas Huth static void gen_doze(DisasContext *ctx) 3552fcf5ef2aSThomas Huth { 3553fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3554fcf5ef2aSThomas Huth GEN_PRIV; 3555fcf5ef2aSThomas Huth #else 3556fcf5ef2aSThomas Huth TCGv_i32 t; 3557fcf5ef2aSThomas Huth 3558fcf5ef2aSThomas Huth CHK_HV; 3559fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_DOZE); 3560fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3561fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3562fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3563fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3564fcf5ef2aSThomas Huth } 3565fcf5ef2aSThomas Huth 3566fcf5ef2aSThomas Huth static void gen_nap(DisasContext *ctx) 3567fcf5ef2aSThomas Huth { 3568fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3569fcf5ef2aSThomas Huth GEN_PRIV; 3570fcf5ef2aSThomas Huth #else 3571fcf5ef2aSThomas Huth TCGv_i32 t; 3572fcf5ef2aSThomas Huth 3573fcf5ef2aSThomas Huth CHK_HV; 3574fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_NAP); 3575fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3576fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3577fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3578fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3579fcf5ef2aSThomas Huth } 3580fcf5ef2aSThomas Huth 3581cdee0e72SNikunj A Dadhania static void gen_stop(DisasContext *ctx) 3582cdee0e72SNikunj A Dadhania { 3583cdee0e72SNikunj A Dadhania gen_nap(ctx); 3584cdee0e72SNikunj A Dadhania } 3585cdee0e72SNikunj A Dadhania 3586fcf5ef2aSThomas Huth static void gen_sleep(DisasContext *ctx) 3587fcf5ef2aSThomas Huth { 3588fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3589fcf5ef2aSThomas Huth GEN_PRIV; 3590fcf5ef2aSThomas Huth #else 3591fcf5ef2aSThomas Huth TCGv_i32 t; 3592fcf5ef2aSThomas Huth 3593fcf5ef2aSThomas Huth CHK_HV; 3594fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_SLEEP); 3595fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3596fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3597fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3598fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3599fcf5ef2aSThomas Huth } 3600fcf5ef2aSThomas Huth 3601fcf5ef2aSThomas Huth static void gen_rvwinkle(DisasContext *ctx) 3602fcf5ef2aSThomas Huth { 3603fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3604fcf5ef2aSThomas Huth GEN_PRIV; 3605fcf5ef2aSThomas Huth #else 3606fcf5ef2aSThomas Huth TCGv_i32 t; 3607fcf5ef2aSThomas Huth 3608fcf5ef2aSThomas Huth CHK_HV; 3609fcf5ef2aSThomas Huth t = tcg_const_i32(PPC_PM_RVWINKLE); 3610fcf5ef2aSThomas Huth gen_helper_pminsn(cpu_env, t); 3611fcf5ef2aSThomas Huth tcg_temp_free_i32(t); 3612fcf5ef2aSThomas Huth gen_stop_exception(ctx); 3613fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 3614fcf5ef2aSThomas Huth } 3615fcf5ef2aSThomas Huth #endif /* #if defined(TARGET_PPC64) */ 3616fcf5ef2aSThomas Huth 3617fcf5ef2aSThomas Huth static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) 3618fcf5ef2aSThomas Huth { 3619fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3620fcf5ef2aSThomas Huth if (ctx->has_cfar) 3621fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_cfar, nip); 3622fcf5ef2aSThomas Huth #endif 3623fcf5ef2aSThomas Huth } 3624fcf5ef2aSThomas Huth 3625fcf5ef2aSThomas Huth static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3626fcf5ef2aSThomas Huth { 3627fcf5ef2aSThomas Huth if (unlikely(ctx->singlestep_enabled)) { 3628fcf5ef2aSThomas Huth return false; 3629fcf5ef2aSThomas Huth } 3630fcf5ef2aSThomas Huth 3631fcf5ef2aSThomas Huth #ifndef CONFIG_USER_ONLY 3632b6bac4bcSEmilio G. Cota return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3633fcf5ef2aSThomas Huth #else 3634fcf5ef2aSThomas Huth return true; 3635fcf5ef2aSThomas Huth #endif 3636fcf5ef2aSThomas Huth } 3637fcf5ef2aSThomas Huth 3638*0e3bf489SRoman Kapl static void gen_lookup_and_goto_ptr(DisasContext *ctx) 3639*0e3bf489SRoman Kapl { 3640*0e3bf489SRoman Kapl int sse = ctx->singlestep_enabled; 3641*0e3bf489SRoman Kapl if (unlikely(sse)) { 3642*0e3bf489SRoman Kapl if (sse & GDBSTUB_SINGLE_STEP) { 3643*0e3bf489SRoman Kapl gen_debug_exception(ctx); 3644*0e3bf489SRoman Kapl } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { 3645*0e3bf489SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_BRANCH); 3646*0e3bf489SRoman Kapl if (excp != POWERPC_EXCP_NONE) { 3647*0e3bf489SRoman Kapl gen_exception(ctx, excp); 3648*0e3bf489SRoman Kapl } 3649*0e3bf489SRoman Kapl } 3650*0e3bf489SRoman Kapl tcg_gen_exit_tb(NULL, 0); 3651*0e3bf489SRoman Kapl } else { 3652*0e3bf489SRoman Kapl tcg_gen_lookup_and_goto_ptr(); 3653*0e3bf489SRoman Kapl } 3654*0e3bf489SRoman Kapl } 3655*0e3bf489SRoman Kapl 3656fcf5ef2aSThomas Huth /*** Branch ***/ 3657c4a2e3a9SRichard Henderson static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3658fcf5ef2aSThomas Huth { 3659fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3660fcf5ef2aSThomas Huth dest = (uint32_t) dest; 3661fcf5ef2aSThomas Huth } 3662fcf5ef2aSThomas Huth if (use_goto_tb(ctx, dest)) { 3663fcf5ef2aSThomas Huth tcg_gen_goto_tb(n); 3664fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 366507ea28b4SRichard Henderson tcg_gen_exit_tb(ctx->base.tb, n); 3666fcf5ef2aSThomas Huth } else { 3667fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_nip, dest & ~3); 3668*0e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3669fcf5ef2aSThomas Huth } 3670fcf5ef2aSThomas Huth } 3671fcf5ef2aSThomas Huth 3672fcf5ef2aSThomas Huth static inline void gen_setlr(DisasContext *ctx, target_ulong nip) 3673fcf5ef2aSThomas Huth { 3674fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3675fcf5ef2aSThomas Huth nip = (uint32_t)nip; 3676fcf5ef2aSThomas Huth } 3677fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_lr, nip); 3678fcf5ef2aSThomas Huth } 3679fcf5ef2aSThomas Huth 3680fcf5ef2aSThomas Huth /* b ba bl bla */ 3681fcf5ef2aSThomas Huth static void gen_b(DisasContext *ctx) 3682fcf5ef2aSThomas Huth { 3683fcf5ef2aSThomas Huth target_ulong li, target; 3684fcf5ef2aSThomas Huth 3685fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3686fcf5ef2aSThomas Huth /* sign extend LI */ 3687fcf5ef2aSThomas Huth li = LI(ctx->opcode); 3688fcf5ef2aSThomas Huth li = (li ^ 0x02000000) - 0x02000000; 3689fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3690b6bac4bcSEmilio G. Cota target = ctx->base.pc_next + li - 4; 3691fcf5ef2aSThomas Huth } else { 3692fcf5ef2aSThomas Huth target = li; 3693fcf5ef2aSThomas Huth } 3694fcf5ef2aSThomas Huth if (LK(ctx->opcode)) { 3695b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3696fcf5ef2aSThomas Huth } 3697b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3698fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, target); 3699fcf5ef2aSThomas Huth } 3700fcf5ef2aSThomas Huth 3701fcf5ef2aSThomas Huth #define BCOND_IM 0 3702fcf5ef2aSThomas Huth #define BCOND_LR 1 3703fcf5ef2aSThomas Huth #define BCOND_CTR 2 3704fcf5ef2aSThomas Huth #define BCOND_TAR 3 3705fcf5ef2aSThomas Huth 3706c4a2e3a9SRichard Henderson static void gen_bcond(DisasContext *ctx, int type) 3707fcf5ef2aSThomas Huth { 3708fcf5ef2aSThomas Huth uint32_t bo = BO(ctx->opcode); 3709fcf5ef2aSThomas Huth TCGLabel *l1; 3710fcf5ef2aSThomas Huth TCGv target; 3711fcf5ef2aSThomas Huth ctx->exception = POWERPC_EXCP_BRANCH; 3712*0e3bf489SRoman Kapl 3713fcf5ef2aSThomas Huth if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { 3714fcf5ef2aSThomas Huth target = tcg_temp_local_new(); 3715fcf5ef2aSThomas Huth if (type == BCOND_CTR) 3716fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_ctr); 3717fcf5ef2aSThomas Huth else if (type == BCOND_TAR) 3718fcf5ef2aSThomas Huth gen_load_spr(target, SPR_TAR); 3719fcf5ef2aSThomas Huth else 3720fcf5ef2aSThomas Huth tcg_gen_mov_tl(target, cpu_lr); 3721fcf5ef2aSThomas Huth } else { 3722f764718dSRichard Henderson target = NULL; 3723fcf5ef2aSThomas Huth } 3724fcf5ef2aSThomas Huth if (LK(ctx->opcode)) 3725b6bac4bcSEmilio G. Cota gen_setlr(ctx, ctx->base.pc_next); 3726fcf5ef2aSThomas Huth l1 = gen_new_label(); 3727fcf5ef2aSThomas Huth if ((bo & 0x4) == 0) { 3728fcf5ef2aSThomas Huth /* Decrement and test CTR */ 3729fcf5ef2aSThomas Huth TCGv temp = tcg_temp_new(); 3730fcf5ef2aSThomas Huth if (unlikely(type == BCOND_CTR)) { 3731fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3732fcf5ef2aSThomas Huth return; 3733fcf5ef2aSThomas Huth } 3734fcf5ef2aSThomas Huth tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); 3735fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3736fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(temp, cpu_ctr); 3737fcf5ef2aSThomas Huth } else { 3738fcf5ef2aSThomas Huth tcg_gen_mov_tl(temp, cpu_ctr); 3739fcf5ef2aSThomas Huth } 3740fcf5ef2aSThomas Huth if (bo & 0x2) { 3741fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); 3742fcf5ef2aSThomas Huth } else { 3743fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); 3744fcf5ef2aSThomas Huth } 3745fcf5ef2aSThomas Huth tcg_temp_free(temp); 3746fcf5ef2aSThomas Huth } 3747fcf5ef2aSThomas Huth if ((bo & 0x10) == 0) { 3748fcf5ef2aSThomas Huth /* Test CR */ 3749fcf5ef2aSThomas Huth uint32_t bi = BI(ctx->opcode); 3750fcf5ef2aSThomas Huth uint32_t mask = 0x08 >> (bi & 0x03); 3751fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 3752fcf5ef2aSThomas Huth 3753fcf5ef2aSThomas Huth if (bo & 0x8) { 3754fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3755fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); 3756fcf5ef2aSThomas Huth } else { 3757fcf5ef2aSThomas Huth tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); 3758fcf5ef2aSThomas Huth tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); 3759fcf5ef2aSThomas Huth } 3760fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 3761fcf5ef2aSThomas Huth } 3762b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3763fcf5ef2aSThomas Huth if (type == BCOND_IM) { 3764fcf5ef2aSThomas Huth target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); 3765fcf5ef2aSThomas Huth if (likely(AA(ctx->opcode) == 0)) { 3766b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); 3767fcf5ef2aSThomas Huth } else { 3768fcf5ef2aSThomas Huth gen_goto_tb(ctx, 0, li); 3769fcf5ef2aSThomas Huth } 3770fcf5ef2aSThomas Huth } else { 3771fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 3772fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); 3773fcf5ef2aSThomas Huth } else { 3774fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_nip, target, ~3); 3775fcf5ef2aSThomas Huth } 3776*0e3bf489SRoman Kapl gen_lookup_and_goto_ptr(ctx); 3777c4a2e3a9SRichard Henderson tcg_temp_free(target); 3778c4a2e3a9SRichard Henderson } 3779fcf5ef2aSThomas Huth if ((bo & 0x14) != 0x14) { 3780*0e3bf489SRoman Kapl /* fallthrough case */ 3781fcf5ef2aSThomas Huth gen_set_label(l1); 3782b6bac4bcSEmilio G. Cota gen_goto_tb(ctx, 1, ctx->base.pc_next); 3783fcf5ef2aSThomas Huth } 3784fcf5ef2aSThomas Huth } 3785fcf5ef2aSThomas Huth 3786fcf5ef2aSThomas Huth static void gen_bc(DisasContext *ctx) 3787fcf5ef2aSThomas Huth { 3788fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_IM); 3789fcf5ef2aSThomas Huth } 3790fcf5ef2aSThomas Huth 3791fcf5ef2aSThomas Huth static void gen_bcctr(DisasContext *ctx) 3792fcf5ef2aSThomas Huth { 3793fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_CTR); 3794fcf5ef2aSThomas Huth } 3795fcf5ef2aSThomas Huth 3796fcf5ef2aSThomas Huth static void gen_bclr(DisasContext *ctx) 3797fcf5ef2aSThomas Huth { 3798fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_LR); 3799fcf5ef2aSThomas Huth } 3800fcf5ef2aSThomas Huth 3801fcf5ef2aSThomas Huth static void gen_bctar(DisasContext *ctx) 3802fcf5ef2aSThomas Huth { 3803fcf5ef2aSThomas Huth gen_bcond(ctx, BCOND_TAR); 3804fcf5ef2aSThomas Huth } 3805fcf5ef2aSThomas Huth 3806fcf5ef2aSThomas Huth /*** Condition register logical ***/ 3807fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 3808fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 3809fcf5ef2aSThomas Huth { \ 3810fcf5ef2aSThomas Huth uint8_t bitmask; \ 3811fcf5ef2aSThomas Huth int sh; \ 3812fcf5ef2aSThomas Huth TCGv_i32 t0, t1; \ 3813fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ 3814fcf5ef2aSThomas Huth t0 = tcg_temp_new_i32(); \ 3815fcf5ef2aSThomas Huth if (sh > 0) \ 3816fcf5ef2aSThomas Huth tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ 3817fcf5ef2aSThomas Huth else if (sh < 0) \ 3818fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ 3819fcf5ef2aSThomas Huth else \ 3820fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ 3821fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); \ 3822fcf5ef2aSThomas Huth sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ 3823fcf5ef2aSThomas Huth if (sh > 0) \ 3824fcf5ef2aSThomas Huth tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ 3825fcf5ef2aSThomas Huth else if (sh < 0) \ 3826fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ 3827fcf5ef2aSThomas Huth else \ 3828fcf5ef2aSThomas Huth tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ 3829fcf5ef2aSThomas Huth tcg_op(t0, t0, t1); \ 3830fcf5ef2aSThomas Huth bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ 3831fcf5ef2aSThomas Huth tcg_gen_andi_i32(t0, t0, bitmask); \ 3832fcf5ef2aSThomas Huth tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 3833fcf5ef2aSThomas Huth tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ 3834fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); \ 3835fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); \ 3836fcf5ef2aSThomas Huth } 3837fcf5ef2aSThomas Huth 3838fcf5ef2aSThomas Huth /* crand */ 3839fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); 3840fcf5ef2aSThomas Huth /* crandc */ 3841fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); 3842fcf5ef2aSThomas Huth /* creqv */ 3843fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); 3844fcf5ef2aSThomas Huth /* crnand */ 3845fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); 3846fcf5ef2aSThomas Huth /* crnor */ 3847fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); 3848fcf5ef2aSThomas Huth /* cror */ 3849fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); 3850fcf5ef2aSThomas Huth /* crorc */ 3851fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); 3852fcf5ef2aSThomas Huth /* crxor */ 3853fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); 3854fcf5ef2aSThomas Huth 3855fcf5ef2aSThomas Huth /* mcrf */ 3856fcf5ef2aSThomas Huth static void gen_mcrf(DisasContext *ctx) 3857fcf5ef2aSThomas Huth { 3858fcf5ef2aSThomas Huth tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); 3859fcf5ef2aSThomas Huth } 3860fcf5ef2aSThomas Huth 3861fcf5ef2aSThomas Huth /*** System linkage ***/ 3862fcf5ef2aSThomas Huth 3863fcf5ef2aSThomas Huth /* rfi (supervisor only) */ 3864fcf5ef2aSThomas Huth static void gen_rfi(DisasContext *ctx) 3865fcf5ef2aSThomas Huth { 3866fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3867fcf5ef2aSThomas Huth GEN_PRIV; 3868fcf5ef2aSThomas Huth #else 3869fcf5ef2aSThomas Huth /* This instruction doesn't exist anymore on 64-bit server 3870fcf5ef2aSThomas Huth * processors compliant with arch 2.x 3871fcf5ef2aSThomas Huth */ 3872fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_SEGMENT_64B) { 3873fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 3874fcf5ef2aSThomas Huth return; 3875fcf5ef2aSThomas Huth } 3876fcf5ef2aSThomas Huth /* Restore CPU state */ 3877fcf5ef2aSThomas Huth CHK_SV; 3878b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3879fcf5ef2aSThomas Huth gen_helper_rfi(cpu_env); 3880fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3881fcf5ef2aSThomas Huth #endif 3882fcf5ef2aSThomas Huth } 3883fcf5ef2aSThomas Huth 3884fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3885fcf5ef2aSThomas Huth static void gen_rfid(DisasContext *ctx) 3886fcf5ef2aSThomas Huth { 3887fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3888fcf5ef2aSThomas Huth GEN_PRIV; 3889fcf5ef2aSThomas Huth #else 3890fcf5ef2aSThomas Huth /* Restore CPU state */ 3891fcf5ef2aSThomas Huth CHK_SV; 3892b6bac4bcSEmilio G. Cota gen_update_cfar(ctx, ctx->base.pc_next - 4); 3893fcf5ef2aSThomas Huth gen_helper_rfid(cpu_env); 3894fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3895fcf5ef2aSThomas Huth #endif 3896fcf5ef2aSThomas Huth } 3897fcf5ef2aSThomas Huth 3898fcf5ef2aSThomas Huth static void gen_hrfid(DisasContext *ctx) 3899fcf5ef2aSThomas Huth { 3900fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3901fcf5ef2aSThomas Huth GEN_PRIV; 3902fcf5ef2aSThomas Huth #else 3903fcf5ef2aSThomas Huth /* Restore CPU state */ 3904fcf5ef2aSThomas Huth CHK_HV; 3905fcf5ef2aSThomas Huth gen_helper_hrfid(cpu_env); 3906fcf5ef2aSThomas Huth gen_sync_exception(ctx); 3907fcf5ef2aSThomas Huth #endif 3908fcf5ef2aSThomas Huth } 3909fcf5ef2aSThomas Huth #endif 3910fcf5ef2aSThomas Huth 3911fcf5ef2aSThomas Huth /* sc */ 3912fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 3913fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER 3914fcf5ef2aSThomas Huth #else 3915fcf5ef2aSThomas Huth #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL 3916fcf5ef2aSThomas Huth #endif 3917fcf5ef2aSThomas Huth static void gen_sc(DisasContext *ctx) 3918fcf5ef2aSThomas Huth { 3919fcf5ef2aSThomas Huth uint32_t lev; 3920fcf5ef2aSThomas Huth 3921fcf5ef2aSThomas Huth lev = (ctx->opcode >> 5) & 0x7F; 3922fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_SYSCALL, lev); 3923fcf5ef2aSThomas Huth } 3924fcf5ef2aSThomas Huth 3925fcf5ef2aSThomas Huth /*** Trap ***/ 3926fcf5ef2aSThomas Huth 3927fcf5ef2aSThomas Huth /* Check for unconditional traps (always or never) */ 3928fcf5ef2aSThomas Huth static bool check_unconditional_trap(DisasContext *ctx) 3929fcf5ef2aSThomas Huth { 3930fcf5ef2aSThomas Huth /* Trap never */ 3931fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 0) { 3932fcf5ef2aSThomas Huth return true; 3933fcf5ef2aSThomas Huth } 3934fcf5ef2aSThomas Huth /* Trap always */ 3935fcf5ef2aSThomas Huth if (TO(ctx->opcode) == 31) { 3936fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); 3937fcf5ef2aSThomas Huth return true; 3938fcf5ef2aSThomas Huth } 3939fcf5ef2aSThomas Huth return false; 3940fcf5ef2aSThomas Huth } 3941fcf5ef2aSThomas Huth 3942fcf5ef2aSThomas Huth /* tw */ 3943fcf5ef2aSThomas Huth static void gen_tw(DisasContext *ctx) 3944fcf5ef2aSThomas Huth { 3945fcf5ef2aSThomas Huth TCGv_i32 t0; 3946fcf5ef2aSThomas Huth 3947fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3948fcf5ef2aSThomas Huth return; 3949fcf5ef2aSThomas Huth } 3950fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3951fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3952fcf5ef2aSThomas Huth t0); 3953fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3954fcf5ef2aSThomas Huth } 3955fcf5ef2aSThomas Huth 3956fcf5ef2aSThomas Huth /* twi */ 3957fcf5ef2aSThomas Huth static void gen_twi(DisasContext *ctx) 3958fcf5ef2aSThomas Huth { 3959fcf5ef2aSThomas Huth TCGv t0; 3960fcf5ef2aSThomas Huth TCGv_i32 t1; 3961fcf5ef2aSThomas Huth 3962fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3963fcf5ef2aSThomas Huth return; 3964fcf5ef2aSThomas Huth } 3965fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3966fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3967fcf5ef2aSThomas Huth gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3968fcf5ef2aSThomas Huth tcg_temp_free(t0); 3969fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 3970fcf5ef2aSThomas Huth } 3971fcf5ef2aSThomas Huth 3972fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 3973fcf5ef2aSThomas Huth /* td */ 3974fcf5ef2aSThomas Huth static void gen_td(DisasContext *ctx) 3975fcf5ef2aSThomas Huth { 3976fcf5ef2aSThomas Huth TCGv_i32 t0; 3977fcf5ef2aSThomas Huth 3978fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3979fcf5ef2aSThomas Huth return; 3980fcf5ef2aSThomas Huth } 3981fcf5ef2aSThomas Huth t0 = tcg_const_i32(TO(ctx->opcode)); 3982fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], 3983fcf5ef2aSThomas Huth t0); 3984fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 3985fcf5ef2aSThomas Huth } 3986fcf5ef2aSThomas Huth 3987fcf5ef2aSThomas Huth /* tdi */ 3988fcf5ef2aSThomas Huth static void gen_tdi(DisasContext *ctx) 3989fcf5ef2aSThomas Huth { 3990fcf5ef2aSThomas Huth TCGv t0; 3991fcf5ef2aSThomas Huth TCGv_i32 t1; 3992fcf5ef2aSThomas Huth 3993fcf5ef2aSThomas Huth if (check_unconditional_trap(ctx)) { 3994fcf5ef2aSThomas Huth return; 3995fcf5ef2aSThomas Huth } 3996fcf5ef2aSThomas Huth t0 = tcg_const_tl(SIMM(ctx->opcode)); 3997fcf5ef2aSThomas Huth t1 = tcg_const_i32(TO(ctx->opcode)); 3998fcf5ef2aSThomas Huth gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); 3999fcf5ef2aSThomas Huth tcg_temp_free(t0); 4000fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4001fcf5ef2aSThomas Huth } 4002fcf5ef2aSThomas Huth #endif 4003fcf5ef2aSThomas Huth 4004fcf5ef2aSThomas Huth /*** Processor control ***/ 4005fcf5ef2aSThomas Huth 4006dd09c361SNikunj A Dadhania static void gen_read_xer(DisasContext *ctx, TCGv dst) 4007fcf5ef2aSThomas Huth { 4008fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4009fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4010fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4011fcf5ef2aSThomas Huth tcg_gen_mov_tl(dst, cpu_xer); 4012fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_so, XER_SO); 4013fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_ov, XER_OV); 4014fcf5ef2aSThomas Huth tcg_gen_shli_tl(t2, cpu_ca, XER_CA); 4015fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 4016fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t2); 4017fcf5ef2aSThomas Huth tcg_gen_or_tl(dst, dst, t0); 4018dd09c361SNikunj A Dadhania if (is_isa300(ctx)) { 4019dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); 4020dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4021dd09c361SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); 4022dd09c361SNikunj A Dadhania tcg_gen_or_tl(dst, dst, t0); 4023dd09c361SNikunj A Dadhania } 4024fcf5ef2aSThomas Huth tcg_temp_free(t0); 4025fcf5ef2aSThomas Huth tcg_temp_free(t1); 4026fcf5ef2aSThomas Huth tcg_temp_free(t2); 4027fcf5ef2aSThomas Huth } 4028fcf5ef2aSThomas Huth 4029fcf5ef2aSThomas Huth static void gen_write_xer(TCGv src) 4030fcf5ef2aSThomas Huth { 4031dd09c361SNikunj A Dadhania /* Write all flags, while reading back check for isa300 */ 4032fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, src, 4033dd09c361SNikunj A Dadhania ~((1u << XER_SO) | 4034dd09c361SNikunj A Dadhania (1u << XER_OV) | (1u << XER_OV32) | 4035dd09c361SNikunj A Dadhania (1u << XER_CA) | (1u << XER_CA32))); 4036dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); 4037dd09c361SNikunj A Dadhania tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); 40381bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); 40391bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); 40401bd33d0dSNikunj A Dadhania tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); 4041fcf5ef2aSThomas Huth } 4042fcf5ef2aSThomas Huth 4043fcf5ef2aSThomas Huth /* mcrxr */ 4044fcf5ef2aSThomas Huth static void gen_mcrxr(DisasContext *ctx) 4045fcf5ef2aSThomas Huth { 4046fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4047fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_temp_new_i32(); 4048fcf5ef2aSThomas Huth TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4049fcf5ef2aSThomas Huth 4050fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t0, cpu_so); 4051fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(t1, cpu_ov); 4052fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(dst, cpu_ca); 4053fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 3); 4054fcf5ef2aSThomas Huth tcg_gen_shli_i32(t1, t1, 2); 4055fcf5ef2aSThomas Huth tcg_gen_shli_i32(dst, dst, 1); 4056fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t0); 4057fcf5ef2aSThomas Huth tcg_gen_or_i32(dst, dst, t1); 4058fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4059fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4060fcf5ef2aSThomas Huth 4061fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 0); 4062fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4063fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 4064fcf5ef2aSThomas Huth } 4065fcf5ef2aSThomas Huth 4066b63d0434SNikunj A Dadhania #ifdef TARGET_PPC64 4067b63d0434SNikunj A Dadhania /* mcrxrx */ 4068b63d0434SNikunj A Dadhania static void gen_mcrxrx(DisasContext *ctx) 4069b63d0434SNikunj A Dadhania { 4070b63d0434SNikunj A Dadhania TCGv t0 = tcg_temp_new(); 4071b63d0434SNikunj A Dadhania TCGv t1 = tcg_temp_new(); 4072b63d0434SNikunj A Dadhania TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; 4073b63d0434SNikunj A Dadhania 4074b63d0434SNikunj A Dadhania /* copy OV and OV32 */ 4075b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, cpu_ov, 1); 4076b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, cpu_ov32); 4077b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t0, t0, 2); 4078b63d0434SNikunj A Dadhania /* copy CA and CA32 */ 4079b63d0434SNikunj A Dadhania tcg_gen_shli_tl(t1, cpu_ca, 1); 4080b63d0434SNikunj A Dadhania tcg_gen_or_tl(t1, t1, cpu_ca32); 4081b63d0434SNikunj A Dadhania tcg_gen_or_tl(t0, t0, t1); 4082b63d0434SNikunj A Dadhania tcg_gen_trunc_tl_i32(dst, t0); 4083b63d0434SNikunj A Dadhania tcg_temp_free(t0); 4084b63d0434SNikunj A Dadhania tcg_temp_free(t1); 4085b63d0434SNikunj A Dadhania } 4086b63d0434SNikunj A Dadhania #endif 4087b63d0434SNikunj A Dadhania 4088fcf5ef2aSThomas Huth /* mfcr mfocrf */ 4089fcf5ef2aSThomas Huth static void gen_mfcr(DisasContext *ctx) 4090fcf5ef2aSThomas Huth { 4091fcf5ef2aSThomas Huth uint32_t crm, crn; 4092fcf5ef2aSThomas Huth 4093fcf5ef2aSThomas Huth if (likely(ctx->opcode & 0x00100000)) { 4094fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4095fcf5ef2aSThomas Huth if (likely(crm && ((crm & (crm - 1)) == 0))) { 4096fcf5ef2aSThomas Huth crn = ctz32 (crm); 4097fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); 4098fcf5ef2aSThomas Huth tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], 4099fcf5ef2aSThomas Huth cpu_gpr[rD(ctx->opcode)], crn * 4); 4100fcf5ef2aSThomas Huth } 4101fcf5ef2aSThomas Huth } else { 4102fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4103fcf5ef2aSThomas Huth tcg_gen_mov_i32(t0, cpu_crf[0]); 4104fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4105fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[1]); 4106fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4107fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[2]); 4108fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4109fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[3]); 4110fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4111fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[4]); 4112fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4113fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[5]); 4114fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4115fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[6]); 4116fcf5ef2aSThomas Huth tcg_gen_shli_i32(t0, t0, 4); 4117fcf5ef2aSThomas Huth tcg_gen_or_i32(t0, t0, cpu_crf[7]); 4118fcf5ef2aSThomas Huth tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4119fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4120fcf5ef2aSThomas Huth } 4121fcf5ef2aSThomas Huth } 4122fcf5ef2aSThomas Huth 4123fcf5ef2aSThomas Huth /* mfmsr */ 4124fcf5ef2aSThomas Huth static void gen_mfmsr(DisasContext *ctx) 4125fcf5ef2aSThomas Huth { 4126fcf5ef2aSThomas Huth CHK_SV; 4127fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); 4128fcf5ef2aSThomas Huth } 4129fcf5ef2aSThomas Huth 4130fcf5ef2aSThomas Huth static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) 4131fcf5ef2aSThomas Huth { 4132fcf5ef2aSThomas Huth #if 0 4133fcf5ef2aSThomas Huth sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); 4134fcf5ef2aSThomas Huth printf("ERROR: try to access SPR %d !\n", sprn); 4135fcf5ef2aSThomas Huth #endif 4136fcf5ef2aSThomas Huth } 4137fcf5ef2aSThomas Huth #define SPR_NOACCESS (&spr_noaccess) 4138fcf5ef2aSThomas Huth 4139fcf5ef2aSThomas Huth /* mfspr */ 4140fcf5ef2aSThomas Huth static inline void gen_op_mfspr(DisasContext *ctx) 4141fcf5ef2aSThomas Huth { 4142fcf5ef2aSThomas Huth void (*read_cb)(DisasContext *ctx, int gprn, int sprn); 4143fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4144fcf5ef2aSThomas Huth 4145fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4146fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4147fcf5ef2aSThomas Huth #else 4148fcf5ef2aSThomas Huth if (ctx->pr) { 4149fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].uea_read; 4150fcf5ef2aSThomas Huth } else if (ctx->hv) { 4151fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].hea_read; 4152fcf5ef2aSThomas Huth } else { 4153fcf5ef2aSThomas Huth read_cb = ctx->spr_cb[sprn].oea_read; 4154fcf5ef2aSThomas Huth } 4155fcf5ef2aSThomas Huth #endif 4156fcf5ef2aSThomas Huth if (likely(read_cb != NULL)) { 4157fcf5ef2aSThomas Huth if (likely(read_cb != SPR_NOACCESS)) { 4158fcf5ef2aSThomas Huth (*read_cb)(ctx, rD(ctx->opcode), sprn); 4159fcf5ef2aSThomas Huth } else { 4160fcf5ef2aSThomas Huth /* Privilege exception */ 4161fcf5ef2aSThomas Huth /* This is a hack to avoid warnings when running Linux: 4162fcf5ef2aSThomas Huth * this OS breaks the PowerPC virtualisation model, 4163fcf5ef2aSThomas Huth * allowing userland application to read the PVR 4164fcf5ef2aSThomas Huth */ 4165fcf5ef2aSThomas Huth if (sprn != SPR_PVR) { 416631085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " 416731085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 4168b6bac4bcSEmilio G. Cota ctx->base.pc_next - 4); 4169fcf5ef2aSThomas Huth } 4170fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4171fcf5ef2aSThomas Huth } 4172fcf5ef2aSThomas Huth } else { 4173fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4174fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4175fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4176fcf5ef2aSThomas Huth /* This is a nop */ 4177fcf5ef2aSThomas Huth return; 4178fcf5ef2aSThomas Huth } 4179fcf5ef2aSThomas Huth /* Not defined */ 418031085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 418131085338SThomas Huth "Trying to read invalid spr %d (0x%03x) at " 4182b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4183fcf5ef2aSThomas Huth 4184fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4185fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4186fcf5ef2aSThomas Huth */ 4187fcf5ef2aSThomas Huth if (sprn & 0x10) { 4188fcf5ef2aSThomas Huth if (ctx->pr) { 4189fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4190fcf5ef2aSThomas Huth } 4191fcf5ef2aSThomas Huth } else { 4192fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { 4193fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4194fcf5ef2aSThomas Huth } 4195fcf5ef2aSThomas Huth } 4196fcf5ef2aSThomas Huth } 4197fcf5ef2aSThomas Huth } 4198fcf5ef2aSThomas Huth 4199fcf5ef2aSThomas Huth static void gen_mfspr(DisasContext *ctx) 4200fcf5ef2aSThomas Huth { 4201fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4202fcf5ef2aSThomas Huth } 4203fcf5ef2aSThomas Huth 4204fcf5ef2aSThomas Huth /* mftb */ 4205fcf5ef2aSThomas Huth static void gen_mftb(DisasContext *ctx) 4206fcf5ef2aSThomas Huth { 4207fcf5ef2aSThomas Huth gen_op_mfspr(ctx); 4208fcf5ef2aSThomas Huth } 4209fcf5ef2aSThomas Huth 4210fcf5ef2aSThomas Huth /* mtcrf mtocrf*/ 4211fcf5ef2aSThomas Huth static void gen_mtcrf(DisasContext *ctx) 4212fcf5ef2aSThomas Huth { 4213fcf5ef2aSThomas Huth uint32_t crm, crn; 4214fcf5ef2aSThomas Huth 4215fcf5ef2aSThomas Huth crm = CRM(ctx->opcode); 4216fcf5ef2aSThomas Huth if (likely((ctx->opcode & 0x00100000))) { 4217fcf5ef2aSThomas Huth if (crm && ((crm & (crm - 1)) == 0)) { 4218fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4219fcf5ef2aSThomas Huth crn = ctz32 (crm); 4220fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4221fcf5ef2aSThomas Huth tcg_gen_shri_i32(temp, temp, crn * 4); 4222fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); 4223fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4224fcf5ef2aSThomas Huth } 4225fcf5ef2aSThomas Huth } else { 4226fcf5ef2aSThomas Huth TCGv_i32 temp = tcg_temp_new_i32(); 4227fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); 4228fcf5ef2aSThomas Huth for (crn = 0 ; crn < 8 ; crn++) { 4229fcf5ef2aSThomas Huth if (crm & (1 << crn)) { 4230fcf5ef2aSThomas Huth tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); 4231fcf5ef2aSThomas Huth tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); 4232fcf5ef2aSThomas Huth } 4233fcf5ef2aSThomas Huth } 4234fcf5ef2aSThomas Huth tcg_temp_free_i32(temp); 4235fcf5ef2aSThomas Huth } 4236fcf5ef2aSThomas Huth } 4237fcf5ef2aSThomas Huth 4238fcf5ef2aSThomas Huth /* mtmsr */ 4239fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4240fcf5ef2aSThomas Huth static void gen_mtmsrd(DisasContext *ctx) 4241fcf5ef2aSThomas Huth { 4242fcf5ef2aSThomas Huth CHK_SV; 4243fcf5ef2aSThomas Huth 4244fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4245fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4246fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4247fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4248fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4249fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4250fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4251fcf5ef2aSThomas Huth tcg_temp_free(t0); 4252fcf5ef2aSThomas Huth } else { 4253fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4254fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4255fcf5ef2aSThomas Huth * directly from ppc_store_msr 4256fcf5ef2aSThomas Huth */ 4257b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4258fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); 4259fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4260fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4261fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4262fcf5ef2aSThomas Huth } 4263fcf5ef2aSThomas Huth #endif /* !defined(CONFIG_USER_ONLY) */ 4264fcf5ef2aSThomas Huth } 4265fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4266fcf5ef2aSThomas Huth 4267fcf5ef2aSThomas Huth static void gen_mtmsr(DisasContext *ctx) 4268fcf5ef2aSThomas Huth { 4269fcf5ef2aSThomas Huth CHK_SV; 4270fcf5ef2aSThomas Huth 4271fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 4272fcf5ef2aSThomas Huth if (ctx->opcode & 0x00010000) { 4273fcf5ef2aSThomas Huth /* Special form that does not need any synchronisation */ 4274fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4275fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); 4276fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); 4277fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 4278fcf5ef2aSThomas Huth tcg_temp_free(t0); 4279fcf5ef2aSThomas Huth } else { 4280fcf5ef2aSThomas Huth TCGv msr = tcg_temp_new(); 4281fcf5ef2aSThomas Huth 4282fcf5ef2aSThomas Huth /* XXX: we need to update nip before the store 4283fcf5ef2aSThomas Huth * if we enter power saving mode, we will exit the loop 4284fcf5ef2aSThomas Huth * directly from ppc_store_msr 4285fcf5ef2aSThomas Huth */ 4286b6bac4bcSEmilio G. Cota gen_update_nip(ctx, ctx->base.pc_next); 4287fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4288fcf5ef2aSThomas Huth tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); 4289fcf5ef2aSThomas Huth #else 4290fcf5ef2aSThomas Huth tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); 4291fcf5ef2aSThomas Huth #endif 4292fcf5ef2aSThomas Huth gen_helper_store_msr(cpu_env, msr); 4293fcf5ef2aSThomas Huth tcg_temp_free(msr); 4294fcf5ef2aSThomas Huth /* Must stop the translation as machine state (may have) changed */ 4295fcf5ef2aSThomas Huth /* Note that mtmsr is not always defined as context-synchronizing */ 4296fcf5ef2aSThomas Huth gen_stop_exception(ctx); 4297fcf5ef2aSThomas Huth } 4298fcf5ef2aSThomas Huth #endif 4299fcf5ef2aSThomas Huth } 4300fcf5ef2aSThomas Huth 4301fcf5ef2aSThomas Huth /* mtspr */ 4302fcf5ef2aSThomas Huth static void gen_mtspr(DisasContext *ctx) 4303fcf5ef2aSThomas Huth { 4304fcf5ef2aSThomas Huth void (*write_cb)(DisasContext *ctx, int sprn, int gprn); 4305fcf5ef2aSThomas Huth uint32_t sprn = SPR(ctx->opcode); 4306fcf5ef2aSThomas Huth 4307fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4308fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4309fcf5ef2aSThomas Huth #else 4310fcf5ef2aSThomas Huth if (ctx->pr) { 4311fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].uea_write; 4312fcf5ef2aSThomas Huth } else if (ctx->hv) { 4313fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].hea_write; 4314fcf5ef2aSThomas Huth } else { 4315fcf5ef2aSThomas Huth write_cb = ctx->spr_cb[sprn].oea_write; 4316fcf5ef2aSThomas Huth } 4317fcf5ef2aSThomas Huth #endif 4318fcf5ef2aSThomas Huth if (likely(write_cb != NULL)) { 4319fcf5ef2aSThomas Huth if (likely(write_cb != SPR_NOACCESS)) { 4320fcf5ef2aSThomas Huth (*write_cb)(ctx, sprn, rS(ctx->opcode)); 4321fcf5ef2aSThomas Huth } else { 4322fcf5ef2aSThomas Huth /* Privilege exception */ 432331085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " 432431085338SThomas Huth "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, 432531085338SThomas Huth ctx->base.pc_next - 4); 4326fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); 4327fcf5ef2aSThomas Huth } 4328fcf5ef2aSThomas Huth } else { 4329fcf5ef2aSThomas Huth /* ISA 2.07 defines these as no-ops */ 4330fcf5ef2aSThomas Huth if ((ctx->insns_flags2 & PPC2_ISA207S) && 4331fcf5ef2aSThomas Huth (sprn >= 808 && sprn <= 811)) { 4332fcf5ef2aSThomas Huth /* This is a nop */ 4333fcf5ef2aSThomas Huth return; 4334fcf5ef2aSThomas Huth } 4335fcf5ef2aSThomas Huth 4336fcf5ef2aSThomas Huth /* Not defined */ 433731085338SThomas Huth qemu_log_mask(LOG_GUEST_ERROR, 433831085338SThomas Huth "Trying to write invalid spr %d (0x%03x) at " 4339b6bac4bcSEmilio G. Cota TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); 4340fcf5ef2aSThomas Huth 4341fcf5ef2aSThomas Huth 4342fcf5ef2aSThomas Huth /* The behaviour depends on MSR:PR and SPR# bit 0x10, 4343fcf5ef2aSThomas Huth * it can generate a priv, a hv emu or a no-op 4344fcf5ef2aSThomas Huth */ 4345fcf5ef2aSThomas Huth if (sprn & 0x10) { 4346fcf5ef2aSThomas Huth if (ctx->pr) { 4347fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4348fcf5ef2aSThomas Huth } 4349fcf5ef2aSThomas Huth } else { 4350fcf5ef2aSThomas Huth if (ctx->pr || sprn == 0) { 4351fcf5ef2aSThomas Huth gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); 4352fcf5ef2aSThomas Huth } 4353fcf5ef2aSThomas Huth } 4354fcf5ef2aSThomas Huth } 4355fcf5ef2aSThomas Huth } 4356fcf5ef2aSThomas Huth 4357fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4358fcf5ef2aSThomas Huth /* setb */ 4359fcf5ef2aSThomas Huth static void gen_setb(DisasContext *ctx) 4360fcf5ef2aSThomas Huth { 4361fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_temp_new_i32(); 4362fcf5ef2aSThomas Huth TCGv_i32 t8 = tcg_temp_new_i32(); 4363fcf5ef2aSThomas Huth TCGv_i32 tm1 = tcg_temp_new_i32(); 4364fcf5ef2aSThomas Huth int crf = crfS(ctx->opcode); 4365fcf5ef2aSThomas Huth 4366fcf5ef2aSThomas Huth tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); 4367fcf5ef2aSThomas Huth tcg_gen_movi_i32(t8, 8); 4368fcf5ef2aSThomas Huth tcg_gen_movi_i32(tm1, -1); 4369fcf5ef2aSThomas Huth tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); 4370fcf5ef2aSThomas Huth tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); 4371fcf5ef2aSThomas Huth 4372fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4373fcf5ef2aSThomas Huth tcg_temp_free_i32(t8); 4374fcf5ef2aSThomas Huth tcg_temp_free_i32(tm1); 4375fcf5ef2aSThomas Huth } 4376fcf5ef2aSThomas Huth #endif 4377fcf5ef2aSThomas Huth 4378fcf5ef2aSThomas Huth /*** Cache management ***/ 4379fcf5ef2aSThomas Huth 4380fcf5ef2aSThomas Huth /* dcbf */ 4381fcf5ef2aSThomas Huth static void gen_dcbf(DisasContext *ctx) 4382fcf5ef2aSThomas Huth { 4383fcf5ef2aSThomas Huth /* XXX: specification says this is treated as a load by the MMU */ 4384fcf5ef2aSThomas Huth TCGv t0; 4385fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4386fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4387fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4388fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4389fcf5ef2aSThomas Huth tcg_temp_free(t0); 4390fcf5ef2aSThomas Huth } 4391fcf5ef2aSThomas Huth 4392fcf5ef2aSThomas Huth /* dcbi (Supervisor only) */ 4393fcf5ef2aSThomas Huth static void gen_dcbi(DisasContext *ctx) 4394fcf5ef2aSThomas Huth { 4395fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4396fcf5ef2aSThomas Huth GEN_PRIV; 4397fcf5ef2aSThomas Huth #else 4398fcf5ef2aSThomas Huth TCGv EA, val; 4399fcf5ef2aSThomas Huth 4400fcf5ef2aSThomas Huth CHK_SV; 4401fcf5ef2aSThomas Huth EA = tcg_temp_new(); 4402fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4403fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 4404fcf5ef2aSThomas Huth val = tcg_temp_new(); 4405fcf5ef2aSThomas Huth /* XXX: specification says this should be treated as a store by the MMU */ 4406fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, val, EA); 4407fcf5ef2aSThomas Huth gen_qemu_st8(ctx, val, EA); 4408fcf5ef2aSThomas Huth tcg_temp_free(val); 4409fcf5ef2aSThomas Huth tcg_temp_free(EA); 4410fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4411fcf5ef2aSThomas Huth } 4412fcf5ef2aSThomas Huth 4413fcf5ef2aSThomas Huth /* dcdst */ 4414fcf5ef2aSThomas Huth static void gen_dcbst(DisasContext *ctx) 4415fcf5ef2aSThomas Huth { 4416fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU */ 4417fcf5ef2aSThomas Huth TCGv t0; 4418fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4419fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4420fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4421fcf5ef2aSThomas Huth gen_qemu_ld8u(ctx, t0, t0); 4422fcf5ef2aSThomas Huth tcg_temp_free(t0); 4423fcf5ef2aSThomas Huth } 4424fcf5ef2aSThomas Huth 4425fcf5ef2aSThomas Huth /* dcbt */ 4426fcf5ef2aSThomas Huth static void gen_dcbt(DisasContext *ctx) 4427fcf5ef2aSThomas Huth { 4428fcf5ef2aSThomas Huth /* interpreted as no-op */ 4429fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4430fcf5ef2aSThomas Huth * but does not generate any exception 4431fcf5ef2aSThomas Huth */ 4432fcf5ef2aSThomas Huth } 4433fcf5ef2aSThomas Huth 4434fcf5ef2aSThomas Huth /* dcbtst */ 4435fcf5ef2aSThomas Huth static void gen_dcbtst(DisasContext *ctx) 4436fcf5ef2aSThomas Huth { 4437fcf5ef2aSThomas Huth /* interpreted as no-op */ 4438fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 4439fcf5ef2aSThomas Huth * but does not generate any exception 4440fcf5ef2aSThomas Huth */ 4441fcf5ef2aSThomas Huth } 4442fcf5ef2aSThomas Huth 4443fcf5ef2aSThomas Huth /* dcbtls */ 4444fcf5ef2aSThomas Huth static void gen_dcbtls(DisasContext *ctx) 4445fcf5ef2aSThomas Huth { 4446fcf5ef2aSThomas Huth /* Always fails locking the cache */ 4447fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4448fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_Exxx_L1CSR0); 4449fcf5ef2aSThomas Huth tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); 4450fcf5ef2aSThomas Huth gen_store_spr(SPR_Exxx_L1CSR0, t0); 4451fcf5ef2aSThomas Huth tcg_temp_free(t0); 4452fcf5ef2aSThomas Huth } 4453fcf5ef2aSThomas Huth 4454fcf5ef2aSThomas Huth /* dcbz */ 4455fcf5ef2aSThomas Huth static void gen_dcbz(DisasContext *ctx) 4456fcf5ef2aSThomas Huth { 4457fcf5ef2aSThomas Huth TCGv tcgv_addr; 4458fcf5ef2aSThomas Huth TCGv_i32 tcgv_op; 4459fcf5ef2aSThomas Huth 4460fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4461fcf5ef2aSThomas Huth tcgv_addr = tcg_temp_new(); 4462fcf5ef2aSThomas Huth tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); 4463fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, tcgv_addr); 4464fcf5ef2aSThomas Huth gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); 4465fcf5ef2aSThomas Huth tcg_temp_free(tcgv_addr); 4466fcf5ef2aSThomas Huth tcg_temp_free_i32(tcgv_op); 4467fcf5ef2aSThomas Huth } 4468fcf5ef2aSThomas Huth 4469fcf5ef2aSThomas Huth /* dst / dstt */ 4470fcf5ef2aSThomas Huth static void gen_dst(DisasContext *ctx) 4471fcf5ef2aSThomas Huth { 4472fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4473fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4474fcf5ef2aSThomas Huth } else { 4475fcf5ef2aSThomas Huth /* interpreted as no-op */ 4476fcf5ef2aSThomas Huth } 4477fcf5ef2aSThomas Huth } 4478fcf5ef2aSThomas Huth 4479fcf5ef2aSThomas Huth /* dstst /dststt */ 4480fcf5ef2aSThomas Huth static void gen_dstst(DisasContext *ctx) 4481fcf5ef2aSThomas Huth { 4482fcf5ef2aSThomas Huth if (rA(ctx->opcode) == 0) { 4483fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 4484fcf5ef2aSThomas Huth } else { 4485fcf5ef2aSThomas Huth /* interpreted as no-op */ 4486fcf5ef2aSThomas Huth } 4487fcf5ef2aSThomas Huth 4488fcf5ef2aSThomas Huth } 4489fcf5ef2aSThomas Huth 4490fcf5ef2aSThomas Huth /* dss / dssall */ 4491fcf5ef2aSThomas Huth static void gen_dss(DisasContext *ctx) 4492fcf5ef2aSThomas Huth { 4493fcf5ef2aSThomas Huth /* interpreted as no-op */ 4494fcf5ef2aSThomas Huth } 4495fcf5ef2aSThomas Huth 4496fcf5ef2aSThomas Huth /* icbi */ 4497fcf5ef2aSThomas Huth static void gen_icbi(DisasContext *ctx) 4498fcf5ef2aSThomas Huth { 4499fcf5ef2aSThomas Huth TCGv t0; 4500fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 4501fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4502fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4503fcf5ef2aSThomas Huth gen_helper_icbi(cpu_env, t0); 4504fcf5ef2aSThomas Huth tcg_temp_free(t0); 4505fcf5ef2aSThomas Huth } 4506fcf5ef2aSThomas Huth 4507fcf5ef2aSThomas Huth /* Optional: */ 4508fcf5ef2aSThomas Huth /* dcba */ 4509fcf5ef2aSThomas Huth static void gen_dcba(DisasContext *ctx) 4510fcf5ef2aSThomas Huth { 4511fcf5ef2aSThomas Huth /* interpreted as no-op */ 4512fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a store by the MMU 4513fcf5ef2aSThomas Huth * but does not generate any exception 4514fcf5ef2aSThomas Huth */ 4515fcf5ef2aSThomas Huth } 4516fcf5ef2aSThomas Huth 4517fcf5ef2aSThomas Huth /*** Segment register manipulation ***/ 4518fcf5ef2aSThomas Huth /* Supervisor only: */ 4519fcf5ef2aSThomas Huth 4520fcf5ef2aSThomas Huth /* mfsr */ 4521fcf5ef2aSThomas Huth static void gen_mfsr(DisasContext *ctx) 4522fcf5ef2aSThomas Huth { 4523fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4524fcf5ef2aSThomas Huth GEN_PRIV; 4525fcf5ef2aSThomas Huth #else 4526fcf5ef2aSThomas Huth TCGv t0; 4527fcf5ef2aSThomas Huth 4528fcf5ef2aSThomas Huth CHK_SV; 4529fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4530fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4531fcf5ef2aSThomas Huth tcg_temp_free(t0); 4532fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4533fcf5ef2aSThomas Huth } 4534fcf5ef2aSThomas Huth 4535fcf5ef2aSThomas Huth /* mfsrin */ 4536fcf5ef2aSThomas Huth static void gen_mfsrin(DisasContext *ctx) 4537fcf5ef2aSThomas Huth { 4538fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4539fcf5ef2aSThomas Huth GEN_PRIV; 4540fcf5ef2aSThomas Huth #else 4541fcf5ef2aSThomas Huth TCGv t0; 4542fcf5ef2aSThomas Huth 4543fcf5ef2aSThomas Huth CHK_SV; 4544fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4545e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4546fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4547fcf5ef2aSThomas Huth tcg_temp_free(t0); 4548fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4549fcf5ef2aSThomas Huth } 4550fcf5ef2aSThomas Huth 4551fcf5ef2aSThomas Huth /* mtsr */ 4552fcf5ef2aSThomas Huth static void gen_mtsr(DisasContext *ctx) 4553fcf5ef2aSThomas Huth { 4554fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4555fcf5ef2aSThomas Huth GEN_PRIV; 4556fcf5ef2aSThomas Huth #else 4557fcf5ef2aSThomas Huth TCGv t0; 4558fcf5ef2aSThomas Huth 4559fcf5ef2aSThomas Huth CHK_SV; 4560fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4561fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4562fcf5ef2aSThomas Huth tcg_temp_free(t0); 4563fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4564fcf5ef2aSThomas Huth } 4565fcf5ef2aSThomas Huth 4566fcf5ef2aSThomas Huth /* mtsrin */ 4567fcf5ef2aSThomas Huth static void gen_mtsrin(DisasContext *ctx) 4568fcf5ef2aSThomas Huth { 4569fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4570fcf5ef2aSThomas Huth GEN_PRIV; 4571fcf5ef2aSThomas Huth #else 4572fcf5ef2aSThomas Huth TCGv t0; 4573fcf5ef2aSThomas Huth CHK_SV; 4574fcf5ef2aSThomas Huth 4575fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4576e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4577fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); 4578fcf5ef2aSThomas Huth tcg_temp_free(t0); 4579fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4580fcf5ef2aSThomas Huth } 4581fcf5ef2aSThomas Huth 4582fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4583fcf5ef2aSThomas Huth /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ 4584fcf5ef2aSThomas Huth 4585fcf5ef2aSThomas Huth /* mfsr */ 4586fcf5ef2aSThomas Huth static void gen_mfsr_64b(DisasContext *ctx) 4587fcf5ef2aSThomas Huth { 4588fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4589fcf5ef2aSThomas Huth GEN_PRIV; 4590fcf5ef2aSThomas Huth #else 4591fcf5ef2aSThomas Huth TCGv t0; 4592fcf5ef2aSThomas Huth 4593fcf5ef2aSThomas Huth CHK_SV; 4594fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4595fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4596fcf5ef2aSThomas Huth tcg_temp_free(t0); 4597fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4598fcf5ef2aSThomas Huth } 4599fcf5ef2aSThomas Huth 4600fcf5ef2aSThomas Huth /* mfsrin */ 4601fcf5ef2aSThomas Huth static void gen_mfsrin_64b(DisasContext *ctx) 4602fcf5ef2aSThomas Huth { 4603fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4604fcf5ef2aSThomas Huth GEN_PRIV; 4605fcf5ef2aSThomas Huth #else 4606fcf5ef2aSThomas Huth TCGv t0; 4607fcf5ef2aSThomas Huth 4608fcf5ef2aSThomas Huth CHK_SV; 4609fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4610e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4611fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4612fcf5ef2aSThomas Huth tcg_temp_free(t0); 4613fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4614fcf5ef2aSThomas Huth } 4615fcf5ef2aSThomas Huth 4616fcf5ef2aSThomas Huth /* mtsr */ 4617fcf5ef2aSThomas Huth static void gen_mtsr_64b(DisasContext *ctx) 4618fcf5ef2aSThomas Huth { 4619fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4620fcf5ef2aSThomas Huth GEN_PRIV; 4621fcf5ef2aSThomas Huth #else 4622fcf5ef2aSThomas Huth TCGv t0; 4623fcf5ef2aSThomas Huth 4624fcf5ef2aSThomas Huth CHK_SV; 4625fcf5ef2aSThomas Huth t0 = tcg_const_tl(SR(ctx->opcode)); 4626fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4627fcf5ef2aSThomas Huth tcg_temp_free(t0); 4628fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4629fcf5ef2aSThomas Huth } 4630fcf5ef2aSThomas Huth 4631fcf5ef2aSThomas Huth /* mtsrin */ 4632fcf5ef2aSThomas Huth static void gen_mtsrin_64b(DisasContext *ctx) 4633fcf5ef2aSThomas Huth { 4634fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4635fcf5ef2aSThomas Huth GEN_PRIV; 4636fcf5ef2aSThomas Huth #else 4637fcf5ef2aSThomas Huth TCGv t0; 4638fcf5ef2aSThomas Huth 4639fcf5ef2aSThomas Huth CHK_SV; 4640fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4641e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); 4642fcf5ef2aSThomas Huth gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); 4643fcf5ef2aSThomas Huth tcg_temp_free(t0); 4644fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4645fcf5ef2aSThomas Huth } 4646fcf5ef2aSThomas Huth 4647fcf5ef2aSThomas Huth /* slbmte */ 4648fcf5ef2aSThomas Huth static void gen_slbmte(DisasContext *ctx) 4649fcf5ef2aSThomas Huth { 4650fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4651fcf5ef2aSThomas Huth GEN_PRIV; 4652fcf5ef2aSThomas Huth #else 4653fcf5ef2aSThomas Huth CHK_SV; 4654fcf5ef2aSThomas Huth 4655fcf5ef2aSThomas Huth gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], 4656fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 4657fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4658fcf5ef2aSThomas Huth } 4659fcf5ef2aSThomas Huth 4660fcf5ef2aSThomas Huth static void gen_slbmfee(DisasContext *ctx) 4661fcf5ef2aSThomas Huth { 4662fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4663fcf5ef2aSThomas Huth GEN_PRIV; 4664fcf5ef2aSThomas Huth #else 4665fcf5ef2aSThomas Huth CHK_SV; 4666fcf5ef2aSThomas Huth 4667fcf5ef2aSThomas Huth gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4668fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4669fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4670fcf5ef2aSThomas Huth } 4671fcf5ef2aSThomas Huth 4672fcf5ef2aSThomas Huth static void gen_slbmfev(DisasContext *ctx) 4673fcf5ef2aSThomas Huth { 4674fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4675fcf5ef2aSThomas Huth GEN_PRIV; 4676fcf5ef2aSThomas Huth #else 4677fcf5ef2aSThomas Huth CHK_SV; 4678fcf5ef2aSThomas Huth 4679fcf5ef2aSThomas Huth gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4680fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4681fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4682fcf5ef2aSThomas Huth } 4683fcf5ef2aSThomas Huth 4684fcf5ef2aSThomas Huth static void gen_slbfee_(DisasContext *ctx) 4685fcf5ef2aSThomas Huth { 4686fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4687fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4688fcf5ef2aSThomas Huth #else 4689fcf5ef2aSThomas Huth TCGLabel *l1, *l2; 4690fcf5ef2aSThomas Huth 4691fcf5ef2aSThomas Huth if (unlikely(ctx->pr)) { 4692fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 4693fcf5ef2aSThomas Huth return; 4694fcf5ef2aSThomas Huth } 4695fcf5ef2aSThomas Huth gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, 4696fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4697fcf5ef2aSThomas Huth l1 = gen_new_label(); 4698fcf5ef2aSThomas Huth l2 = gen_new_label(); 4699fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 4700fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); 4701efa73196SNikunj A Dadhania tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); 4702fcf5ef2aSThomas Huth tcg_gen_br(l2); 4703fcf5ef2aSThomas Huth gen_set_label(l1); 4704fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); 4705fcf5ef2aSThomas Huth gen_set_label(l2); 4706fcf5ef2aSThomas Huth #endif 4707fcf5ef2aSThomas Huth } 4708fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4709fcf5ef2aSThomas Huth 4710fcf5ef2aSThomas Huth /*** Lookaside buffer management ***/ 4711fcf5ef2aSThomas Huth /* Optional & supervisor only: */ 4712fcf5ef2aSThomas Huth 4713fcf5ef2aSThomas Huth /* tlbia */ 4714fcf5ef2aSThomas Huth static void gen_tlbia(DisasContext *ctx) 4715fcf5ef2aSThomas Huth { 4716fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4717fcf5ef2aSThomas Huth GEN_PRIV; 4718fcf5ef2aSThomas Huth #else 4719fcf5ef2aSThomas Huth CHK_HV; 4720fcf5ef2aSThomas Huth 4721fcf5ef2aSThomas Huth gen_helper_tlbia(cpu_env); 4722fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4723fcf5ef2aSThomas Huth } 4724fcf5ef2aSThomas Huth 4725fcf5ef2aSThomas Huth /* tlbiel */ 4726fcf5ef2aSThomas Huth static void gen_tlbiel(DisasContext *ctx) 4727fcf5ef2aSThomas Huth { 4728fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4729fcf5ef2aSThomas Huth GEN_PRIV; 4730fcf5ef2aSThomas Huth #else 4731fcf5ef2aSThomas Huth CHK_SV; 4732fcf5ef2aSThomas Huth 4733fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4734fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4735fcf5ef2aSThomas Huth } 4736fcf5ef2aSThomas Huth 4737fcf5ef2aSThomas Huth /* tlbie */ 4738fcf5ef2aSThomas Huth static void gen_tlbie(DisasContext *ctx) 4739fcf5ef2aSThomas Huth { 4740fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4741fcf5ef2aSThomas Huth GEN_PRIV; 4742fcf5ef2aSThomas Huth #else 4743fcf5ef2aSThomas Huth TCGv_i32 t1; 4744c6fd28fdSSuraj Jitindar Singh 4745c6fd28fdSSuraj Jitindar Singh if (ctx->gtse) { 474691c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ 4747c6fd28fdSSuraj Jitindar Singh } else { 4748c6fd28fdSSuraj Jitindar Singh CHK_HV; /* Else hypervisor privileged */ 4749c6fd28fdSSuraj Jitindar Singh } 4750fcf5ef2aSThomas Huth 4751fcf5ef2aSThomas Huth if (NARROW_MODE(ctx)) { 4752fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4753fcf5ef2aSThomas Huth tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); 4754fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, t0); 4755fcf5ef2aSThomas Huth tcg_temp_free(t0); 4756fcf5ef2aSThomas Huth } else { 4757fcf5ef2aSThomas Huth gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4758fcf5ef2aSThomas Huth } 4759fcf5ef2aSThomas Huth t1 = tcg_temp_new_i32(); 4760fcf5ef2aSThomas Huth tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4761fcf5ef2aSThomas Huth tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); 4762fcf5ef2aSThomas Huth tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); 4763fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 4764fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4765fcf5ef2aSThomas Huth } 4766fcf5ef2aSThomas Huth 4767fcf5ef2aSThomas Huth /* tlbsync */ 4768fcf5ef2aSThomas Huth static void gen_tlbsync(DisasContext *ctx) 4769fcf5ef2aSThomas Huth { 4770fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4771fcf5ef2aSThomas Huth GEN_PRIV; 4772fcf5ef2aSThomas Huth #else 477391c60f12SCédric Le Goater 477491c60f12SCédric Le Goater if (ctx->gtse) { 477591c60f12SCédric Le Goater CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ 477691c60f12SCédric Le Goater } else { 477791c60f12SCédric Le Goater CHK_HV; /* Else hypervisor privileged */ 477891c60f12SCédric Le Goater } 4779fcf5ef2aSThomas Huth 4780fcf5ef2aSThomas Huth /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ 4781fcf5ef2aSThomas Huth if (ctx->insns_flags & PPC_BOOKE) { 4782fcf5ef2aSThomas Huth gen_check_tlb_flush(ctx, true); 4783fcf5ef2aSThomas Huth } 4784fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4785fcf5ef2aSThomas Huth } 4786fcf5ef2aSThomas Huth 4787fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 4788fcf5ef2aSThomas Huth /* slbia */ 4789fcf5ef2aSThomas Huth static void gen_slbia(DisasContext *ctx) 4790fcf5ef2aSThomas Huth { 4791fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4792fcf5ef2aSThomas Huth GEN_PRIV; 4793fcf5ef2aSThomas Huth #else 4794fcf5ef2aSThomas Huth CHK_SV; 4795fcf5ef2aSThomas Huth 4796fcf5ef2aSThomas Huth gen_helper_slbia(cpu_env); 4797fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4798fcf5ef2aSThomas Huth } 4799fcf5ef2aSThomas Huth 4800fcf5ef2aSThomas Huth /* slbie */ 4801fcf5ef2aSThomas Huth static void gen_slbie(DisasContext *ctx) 4802fcf5ef2aSThomas Huth { 4803fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 4804fcf5ef2aSThomas Huth GEN_PRIV; 4805fcf5ef2aSThomas Huth #else 4806fcf5ef2aSThomas Huth CHK_SV; 4807fcf5ef2aSThomas Huth 4808fcf5ef2aSThomas Huth gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4809fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 4810fcf5ef2aSThomas Huth } 4811a63f1dfcSNikunj A Dadhania 4812a63f1dfcSNikunj A Dadhania /* slbieg */ 4813a63f1dfcSNikunj A Dadhania static void gen_slbieg(DisasContext *ctx) 4814a63f1dfcSNikunj A Dadhania { 4815a63f1dfcSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 4816a63f1dfcSNikunj A Dadhania GEN_PRIV; 4817a63f1dfcSNikunj A Dadhania #else 4818a63f1dfcSNikunj A Dadhania CHK_SV; 4819a63f1dfcSNikunj A Dadhania 4820a63f1dfcSNikunj A Dadhania gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); 4821a63f1dfcSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 4822a63f1dfcSNikunj A Dadhania } 4823a63f1dfcSNikunj A Dadhania 482462d897caSNikunj A Dadhania /* slbsync */ 482562d897caSNikunj A Dadhania static void gen_slbsync(DisasContext *ctx) 482662d897caSNikunj A Dadhania { 482762d897caSNikunj A Dadhania #if defined(CONFIG_USER_ONLY) 482862d897caSNikunj A Dadhania GEN_PRIV; 482962d897caSNikunj A Dadhania #else 483062d897caSNikunj A Dadhania CHK_SV; 483162d897caSNikunj A Dadhania gen_check_tlb_flush(ctx, true); 483262d897caSNikunj A Dadhania #endif /* defined(CONFIG_USER_ONLY) */ 483362d897caSNikunj A Dadhania } 483462d897caSNikunj A Dadhania 4835fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 4836fcf5ef2aSThomas Huth 4837fcf5ef2aSThomas Huth /*** External control ***/ 4838fcf5ef2aSThomas Huth /* Optional: */ 4839fcf5ef2aSThomas Huth 4840fcf5ef2aSThomas Huth /* eciwx */ 4841fcf5ef2aSThomas Huth static void gen_eciwx(DisasContext *ctx) 4842fcf5ef2aSThomas Huth { 4843fcf5ef2aSThomas Huth TCGv t0; 4844fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4845fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4846fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4847fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4848c674a983SRichard Henderson tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4849c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 4850fcf5ef2aSThomas Huth tcg_temp_free(t0); 4851fcf5ef2aSThomas Huth } 4852fcf5ef2aSThomas Huth 4853fcf5ef2aSThomas Huth /* ecowx */ 4854fcf5ef2aSThomas Huth static void gen_ecowx(DisasContext *ctx) 4855fcf5ef2aSThomas Huth { 4856fcf5ef2aSThomas Huth TCGv t0; 4857fcf5ef2aSThomas Huth /* Should check EAR[E] ! */ 4858fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_EXT); 4859fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 4860fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 4861c674a983SRichard Henderson tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, 4862c674a983SRichard Henderson DEF_MEMOP(MO_UL | MO_ALIGN)); 4863fcf5ef2aSThomas Huth tcg_temp_free(t0); 4864fcf5ef2aSThomas Huth } 4865fcf5ef2aSThomas Huth 4866fcf5ef2aSThomas Huth /* PowerPC 601 specific instructions */ 4867fcf5ef2aSThomas Huth 4868fcf5ef2aSThomas Huth /* abs - abs. */ 4869fcf5ef2aSThomas Huth static void gen_abs(DisasContext *ctx) 4870fcf5ef2aSThomas Huth { 4871fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4872fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4873fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); 4874fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4875fcf5ef2aSThomas Huth tcg_gen_br(l2); 4876fcf5ef2aSThomas Huth gen_set_label(l1); 4877fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4878fcf5ef2aSThomas Huth gen_set_label(l2); 4879fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4880fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4881fcf5ef2aSThomas Huth } 4882fcf5ef2aSThomas Huth 4883fcf5ef2aSThomas Huth /* abso - abso. */ 4884fcf5ef2aSThomas Huth static void gen_abso(DisasContext *ctx) 4885fcf5ef2aSThomas Huth { 4886fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4887fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4888fcf5ef2aSThomas Huth TCGLabel *l3 = gen_new_label(); 4889fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4890fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4891fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); 4892fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); 4893fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4894fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4895fcf5ef2aSThomas Huth tcg_gen_br(l2); 4896fcf5ef2aSThomas Huth gen_set_label(l1); 4897fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4898fcf5ef2aSThomas Huth tcg_gen_br(l3); 4899fcf5ef2aSThomas Huth gen_set_label(l2); 4900fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4901fcf5ef2aSThomas Huth gen_set_label(l3); 4902fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4903fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4904fcf5ef2aSThomas Huth } 4905fcf5ef2aSThomas Huth 4906fcf5ef2aSThomas Huth /* clcs */ 4907fcf5ef2aSThomas Huth static void gen_clcs(DisasContext *ctx) 4908fcf5ef2aSThomas Huth { 4909fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); 4910fcf5ef2aSThomas Huth gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 4911fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 4912fcf5ef2aSThomas Huth /* Rc=1 sets CR0 to an undefined state */ 4913fcf5ef2aSThomas Huth } 4914fcf5ef2aSThomas Huth 4915fcf5ef2aSThomas Huth /* div - div. */ 4916fcf5ef2aSThomas Huth static void gen_div(DisasContext *ctx) 4917fcf5ef2aSThomas Huth { 4918fcf5ef2aSThomas Huth gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4919fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4920fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4921fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4922fcf5ef2aSThomas Huth } 4923fcf5ef2aSThomas Huth 4924fcf5ef2aSThomas Huth /* divo - divo. */ 4925fcf5ef2aSThomas Huth static void gen_divo(DisasContext *ctx) 4926fcf5ef2aSThomas Huth { 4927fcf5ef2aSThomas Huth gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4928fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4929fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4930fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4931fcf5ef2aSThomas Huth } 4932fcf5ef2aSThomas Huth 4933fcf5ef2aSThomas Huth /* divs - divs. */ 4934fcf5ef2aSThomas Huth static void gen_divs(DisasContext *ctx) 4935fcf5ef2aSThomas Huth { 4936fcf5ef2aSThomas Huth gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], 4937fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 4938fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4939fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4940fcf5ef2aSThomas Huth } 4941fcf5ef2aSThomas Huth 4942fcf5ef2aSThomas Huth /* divso - divso. */ 4943fcf5ef2aSThomas Huth static void gen_divso(DisasContext *ctx) 4944fcf5ef2aSThomas Huth { 4945fcf5ef2aSThomas Huth gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, 4946fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 4947fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4948fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4949fcf5ef2aSThomas Huth } 4950fcf5ef2aSThomas Huth 4951fcf5ef2aSThomas Huth /* doz - doz. */ 4952fcf5ef2aSThomas Huth static void gen_doz(DisasContext *ctx) 4953fcf5ef2aSThomas Huth { 4954fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4955fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4956fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4957fcf5ef2aSThomas Huth tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4958fcf5ef2aSThomas Huth tcg_gen_br(l2); 4959fcf5ef2aSThomas Huth gen_set_label(l1); 4960fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4961fcf5ef2aSThomas Huth gen_set_label(l2); 4962fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4963fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4964fcf5ef2aSThomas Huth } 4965fcf5ef2aSThomas Huth 4966fcf5ef2aSThomas Huth /* dozo - dozo. */ 4967fcf5ef2aSThomas Huth static void gen_dozo(DisasContext *ctx) 4968fcf5ef2aSThomas Huth { 4969fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 4970fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 4971fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 4972fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 4973fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 4974fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 4975fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 4976fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); 4977fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4978fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 4979fcf5ef2aSThomas Huth tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); 4980fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 4981fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 4982fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 4983fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 4984fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 4985fcf5ef2aSThomas Huth tcg_gen_br(l2); 4986fcf5ef2aSThomas Huth gen_set_label(l1); 4987fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 4988fcf5ef2aSThomas Huth gen_set_label(l2); 4989fcf5ef2aSThomas Huth tcg_temp_free(t0); 4990fcf5ef2aSThomas Huth tcg_temp_free(t1); 4991fcf5ef2aSThomas Huth tcg_temp_free(t2); 4992fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 4993fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 4994fcf5ef2aSThomas Huth } 4995fcf5ef2aSThomas Huth 4996fcf5ef2aSThomas Huth /* dozi */ 4997fcf5ef2aSThomas Huth static void gen_dozi(DisasContext *ctx) 4998fcf5ef2aSThomas Huth { 4999fcf5ef2aSThomas Huth target_long simm = SIMM(ctx->opcode); 5000fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5001fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5002fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); 5003fcf5ef2aSThomas Huth tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); 5004fcf5ef2aSThomas Huth tcg_gen_br(l2); 5005fcf5ef2aSThomas Huth gen_set_label(l1); 5006fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); 5007fcf5ef2aSThomas Huth gen_set_label(l2); 5008fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5009fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5010fcf5ef2aSThomas Huth } 5011fcf5ef2aSThomas Huth 5012fcf5ef2aSThomas Huth /* lscbx - lscbx. */ 5013fcf5ef2aSThomas Huth static void gen_lscbx(DisasContext *ctx) 5014fcf5ef2aSThomas Huth { 5015fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5016fcf5ef2aSThomas Huth TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); 5017fcf5ef2aSThomas Huth TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); 5018fcf5ef2aSThomas Huth TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); 5019fcf5ef2aSThomas Huth 5020fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5021fcf5ef2aSThomas Huth gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); 5022fcf5ef2aSThomas Huth tcg_temp_free_i32(t1); 5023fcf5ef2aSThomas Huth tcg_temp_free_i32(t2); 5024fcf5ef2aSThomas Huth tcg_temp_free_i32(t3); 5025fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); 5026fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_xer, cpu_xer, t0); 5027fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5028fcf5ef2aSThomas Huth gen_set_Rc0(ctx, t0); 5029fcf5ef2aSThomas Huth tcg_temp_free(t0); 5030fcf5ef2aSThomas Huth } 5031fcf5ef2aSThomas Huth 5032fcf5ef2aSThomas Huth /* maskg - maskg. */ 5033fcf5ef2aSThomas Huth static void gen_maskg(DisasContext *ctx) 5034fcf5ef2aSThomas Huth { 5035fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5036fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5037fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5038fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5039fcf5ef2aSThomas Huth TCGv t3 = tcg_temp_new(); 5040fcf5ef2aSThomas Huth tcg_gen_movi_tl(t3, 0xFFFFFFFF); 5041fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5042fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); 5043fcf5ef2aSThomas Huth tcg_gen_addi_tl(t2, t0, 1); 5044fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t3, t2); 5045fcf5ef2aSThomas Huth tcg_gen_shr_tl(t3, t3, t1); 5046fcf5ef2aSThomas Huth tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); 5047fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); 5048fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5049fcf5ef2aSThomas Huth gen_set_label(l1); 5050fcf5ef2aSThomas Huth tcg_temp_free(t0); 5051fcf5ef2aSThomas Huth tcg_temp_free(t1); 5052fcf5ef2aSThomas Huth tcg_temp_free(t2); 5053fcf5ef2aSThomas Huth tcg_temp_free(t3); 5054fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5055fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5056fcf5ef2aSThomas Huth } 5057fcf5ef2aSThomas Huth 5058fcf5ef2aSThomas Huth /* maskir - maskir. */ 5059fcf5ef2aSThomas Huth static void gen_maskir(DisasContext *ctx) 5060fcf5ef2aSThomas Huth { 5061fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5062fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5063fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5064fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 5065fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5066fcf5ef2aSThomas Huth tcg_temp_free(t0); 5067fcf5ef2aSThomas Huth tcg_temp_free(t1); 5068fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5069fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5070fcf5ef2aSThomas Huth } 5071fcf5ef2aSThomas Huth 5072fcf5ef2aSThomas Huth /* mul - mul. */ 5073fcf5ef2aSThomas Huth static void gen_mul(DisasContext *ctx) 5074fcf5ef2aSThomas Huth { 5075fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5076fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5077fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5078fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5079fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5080fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5081fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5082fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5083fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5084fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5085fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5086fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5087fcf5ef2aSThomas Huth tcg_temp_free(t2); 5088fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5089fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5090fcf5ef2aSThomas Huth } 5091fcf5ef2aSThomas Huth 5092fcf5ef2aSThomas Huth /* mulo - mulo. */ 5093fcf5ef2aSThomas Huth static void gen_mulo(DisasContext *ctx) 5094fcf5ef2aSThomas Huth { 5095fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5096fcf5ef2aSThomas Huth TCGv_i64 t0 = tcg_temp_new_i64(); 5097fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 5098fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5099fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5100fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5101fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 5102fcf5ef2aSThomas Huth tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 5103fcf5ef2aSThomas Huth tcg_gen_mul_i64(t0, t0, t1); 5104fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(t2, t0); 5105fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t2); 5106fcf5ef2aSThomas Huth tcg_gen_shri_i64(t1, t0, 32); 5107fcf5ef2aSThomas Huth tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); 5108fcf5ef2aSThomas Huth tcg_gen_ext32s_i64(t1, t0); 5109fcf5ef2aSThomas Huth tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); 5110fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5111fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5112fcf5ef2aSThomas Huth gen_set_label(l1); 5113fcf5ef2aSThomas Huth tcg_temp_free_i64(t0); 5114fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 5115fcf5ef2aSThomas Huth tcg_temp_free(t2); 5116fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5117fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5118fcf5ef2aSThomas Huth } 5119fcf5ef2aSThomas Huth 5120fcf5ef2aSThomas Huth /* nabs - nabs. */ 5121fcf5ef2aSThomas Huth static void gen_nabs(DisasContext *ctx) 5122fcf5ef2aSThomas Huth { 5123fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5124fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5125fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 5126fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5127fcf5ef2aSThomas Huth tcg_gen_br(l2); 5128fcf5ef2aSThomas Huth gen_set_label(l1); 5129fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5130fcf5ef2aSThomas Huth gen_set_label(l2); 5131fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5132fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5133fcf5ef2aSThomas Huth } 5134fcf5ef2aSThomas Huth 5135fcf5ef2aSThomas Huth /* nabso - nabso. */ 5136fcf5ef2aSThomas Huth static void gen_nabso(DisasContext *ctx) 5137fcf5ef2aSThomas Huth { 5138fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5139fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5140fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); 5141fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5142fcf5ef2aSThomas Huth tcg_gen_br(l2); 5143fcf5ef2aSThomas Huth gen_set_label(l1); 5144fcf5ef2aSThomas Huth tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5145fcf5ef2aSThomas Huth gen_set_label(l2); 5146fcf5ef2aSThomas Huth /* nabs never overflows */ 5147fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5148fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5149fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); 5150fcf5ef2aSThomas Huth } 5151fcf5ef2aSThomas Huth 5152fcf5ef2aSThomas Huth /* rlmi - rlmi. */ 5153fcf5ef2aSThomas Huth static void gen_rlmi(DisasContext *ctx) 5154fcf5ef2aSThomas Huth { 5155fcf5ef2aSThomas Huth uint32_t mb = MB(ctx->opcode); 5156fcf5ef2aSThomas Huth uint32_t me = ME(ctx->opcode); 5157fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5158fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5159fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5160fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, MASK(mb, me)); 5161fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); 5162fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); 5163fcf5ef2aSThomas Huth tcg_temp_free(t0); 5164fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5165fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5166fcf5ef2aSThomas Huth } 5167fcf5ef2aSThomas Huth 5168fcf5ef2aSThomas Huth /* rrib - rrib. */ 5169fcf5ef2aSThomas Huth static void gen_rrib(DisasContext *ctx) 5170fcf5ef2aSThomas Huth { 5171fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5172fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5173fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5174fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0x80000000); 5175fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5176fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5177fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5178fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); 5179fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5180fcf5ef2aSThomas Huth tcg_temp_free(t0); 5181fcf5ef2aSThomas Huth tcg_temp_free(t1); 5182fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5183fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5184fcf5ef2aSThomas Huth } 5185fcf5ef2aSThomas Huth 5186fcf5ef2aSThomas Huth /* sle - sle. */ 5187fcf5ef2aSThomas Huth static void gen_sle(DisasContext *ctx) 5188fcf5ef2aSThomas Huth { 5189fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5190fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5191fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5192fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5193fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5194fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5195fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5196fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5197fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5198fcf5ef2aSThomas Huth tcg_temp_free(t0); 5199fcf5ef2aSThomas Huth tcg_temp_free(t1); 5200fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5201fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5202fcf5ef2aSThomas Huth } 5203fcf5ef2aSThomas Huth 5204fcf5ef2aSThomas Huth /* sleq - sleq. */ 5205fcf5ef2aSThomas Huth static void gen_sleq(DisasContext *ctx) 5206fcf5ef2aSThomas Huth { 5207fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5208fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5209fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5210fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5211fcf5ef2aSThomas Huth tcg_gen_movi_tl(t2, 0xFFFFFFFF); 5212fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, t2, t0); 5213fcf5ef2aSThomas Huth tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5214fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5215fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5216fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5217fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5218fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5219fcf5ef2aSThomas Huth tcg_temp_free(t0); 5220fcf5ef2aSThomas Huth tcg_temp_free(t1); 5221fcf5ef2aSThomas Huth tcg_temp_free(t2); 5222fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5223fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5224fcf5ef2aSThomas Huth } 5225fcf5ef2aSThomas Huth 5226fcf5ef2aSThomas Huth /* sliq - sliq. */ 5227fcf5ef2aSThomas Huth static void gen_sliq(DisasContext *ctx) 5228fcf5ef2aSThomas Huth { 5229fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5230fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5231fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5232fcf5ef2aSThomas Huth tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5233fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5234fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5235fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5236fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5237fcf5ef2aSThomas Huth tcg_temp_free(t0); 5238fcf5ef2aSThomas Huth tcg_temp_free(t1); 5239fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5240fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5241fcf5ef2aSThomas Huth } 5242fcf5ef2aSThomas Huth 5243fcf5ef2aSThomas Huth /* slliq - slliq. */ 5244fcf5ef2aSThomas Huth static void gen_slliq(DisasContext *ctx) 5245fcf5ef2aSThomas Huth { 5246fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5247fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5248fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5249fcf5ef2aSThomas Huth tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5250fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5251fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5252fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); 5253fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); 5254fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5255fcf5ef2aSThomas Huth tcg_temp_free(t0); 5256fcf5ef2aSThomas Huth tcg_temp_free(t1); 5257fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5258fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5259fcf5ef2aSThomas Huth } 5260fcf5ef2aSThomas Huth 5261fcf5ef2aSThomas Huth /* sllq - sllq. */ 5262fcf5ef2aSThomas Huth static void gen_sllq(DisasContext *ctx) 5263fcf5ef2aSThomas Huth { 5264fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5265fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5266fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5267fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5268fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5269fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5270fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5271fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, t1, t2); 5272fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5273fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5274fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5275fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5276fcf5ef2aSThomas Huth tcg_gen_br(l2); 5277fcf5ef2aSThomas Huth gen_set_label(l1); 5278fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5279fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5280fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t2, t1); 5281fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5282fcf5ef2aSThomas Huth gen_set_label(l2); 5283fcf5ef2aSThomas Huth tcg_temp_free(t0); 5284fcf5ef2aSThomas Huth tcg_temp_free(t1); 5285fcf5ef2aSThomas Huth tcg_temp_free(t2); 5286fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5287fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5288fcf5ef2aSThomas Huth } 5289fcf5ef2aSThomas Huth 5290fcf5ef2aSThomas Huth /* slq - slq. */ 5291fcf5ef2aSThomas Huth static void gen_slq(DisasContext *ctx) 5292fcf5ef2aSThomas Huth { 5293fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5294fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5295fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5296fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5297fcf5ef2aSThomas Huth tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5298fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5299fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5300fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5301fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5302fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5303fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5304fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5305fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5306fcf5ef2aSThomas Huth gen_set_label(l1); 5307fcf5ef2aSThomas Huth tcg_temp_free(t0); 5308fcf5ef2aSThomas Huth tcg_temp_free(t1); 5309fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5310fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5311fcf5ef2aSThomas Huth } 5312fcf5ef2aSThomas Huth 5313fcf5ef2aSThomas Huth /* sraiq - sraiq. */ 5314fcf5ef2aSThomas Huth static void gen_sraiq(DisasContext *ctx) 5315fcf5ef2aSThomas Huth { 5316fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5317fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5318fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5319fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5320fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5321fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5322fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t1); 5323fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5324fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5325fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); 5326fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); 5327fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5328fcf5ef2aSThomas Huth gen_set_label(l1); 5329fcf5ef2aSThomas Huth tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); 5330fcf5ef2aSThomas Huth tcg_temp_free(t0); 5331fcf5ef2aSThomas Huth tcg_temp_free(t1); 5332fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5333fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5334fcf5ef2aSThomas Huth } 5335fcf5ef2aSThomas Huth 5336fcf5ef2aSThomas Huth /* sraq - sraq. */ 5337fcf5ef2aSThomas Huth static void gen_sraq(DisasContext *ctx) 5338fcf5ef2aSThomas Huth { 5339fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5340fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5341fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5342fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5343fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5344fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5345fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5346fcf5ef2aSThomas Huth tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); 5347fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t2, 32, t2); 5348fcf5ef2aSThomas Huth tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); 5349fcf5ef2aSThomas Huth tcg_gen_or_tl(t0, t0, t2); 5350fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5351fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5352fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); 5353fcf5ef2aSThomas Huth tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); 5354fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); 5355fcf5ef2aSThomas Huth gen_set_label(l1); 5356fcf5ef2aSThomas Huth tcg_temp_free(t0); 5357fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); 5358fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 0); 5359fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); 5360fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); 5361fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ca, 1); 5362fcf5ef2aSThomas Huth gen_set_label(l2); 5363fcf5ef2aSThomas Huth tcg_temp_free(t1); 5364fcf5ef2aSThomas Huth tcg_temp_free(t2); 5365fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5366fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5367fcf5ef2aSThomas Huth } 5368fcf5ef2aSThomas Huth 5369fcf5ef2aSThomas Huth /* sre - sre. */ 5370fcf5ef2aSThomas Huth static void gen_sre(DisasContext *ctx) 5371fcf5ef2aSThomas Huth { 5372fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5373fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5374fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5375fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5376fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5377fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5378fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5379fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5380fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5381fcf5ef2aSThomas Huth tcg_temp_free(t0); 5382fcf5ef2aSThomas Huth tcg_temp_free(t1); 5383fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5384fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5385fcf5ef2aSThomas Huth } 5386fcf5ef2aSThomas Huth 5387fcf5ef2aSThomas Huth /* srea - srea. */ 5388fcf5ef2aSThomas Huth static void gen_srea(DisasContext *ctx) 5389fcf5ef2aSThomas Huth { 5390fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5391fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5392fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5393fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5394fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5395fcf5ef2aSThomas Huth tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); 5396fcf5ef2aSThomas Huth tcg_temp_free(t0); 5397fcf5ef2aSThomas Huth tcg_temp_free(t1); 5398fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5399fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5400fcf5ef2aSThomas Huth } 5401fcf5ef2aSThomas Huth 5402fcf5ef2aSThomas Huth /* sreq */ 5403fcf5ef2aSThomas Huth static void gen_sreq(DisasContext *ctx) 5404fcf5ef2aSThomas Huth { 5405fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5406fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5407fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_new(); 5408fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); 5409fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5410fcf5ef2aSThomas Huth tcg_gen_shr_tl(t1, t1, t0); 5411fcf5ef2aSThomas Huth tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); 5412fcf5ef2aSThomas Huth gen_load_spr(t2, SPR_MQ); 5413fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5414fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t1); 5415fcf5ef2aSThomas Huth tcg_gen_andc_tl(t2, t2, t1); 5416fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5417fcf5ef2aSThomas Huth tcg_temp_free(t0); 5418fcf5ef2aSThomas Huth tcg_temp_free(t1); 5419fcf5ef2aSThomas Huth tcg_temp_free(t2); 5420fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5421fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5422fcf5ef2aSThomas Huth } 5423fcf5ef2aSThomas Huth 5424fcf5ef2aSThomas Huth /* sriq */ 5425fcf5ef2aSThomas Huth static void gen_sriq(DisasContext *ctx) 5426fcf5ef2aSThomas Huth { 5427fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5428fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5429fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5430fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5431fcf5ef2aSThomas Huth tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); 5432fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5433fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5434fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5435fcf5ef2aSThomas Huth tcg_temp_free(t0); 5436fcf5ef2aSThomas Huth tcg_temp_free(t1); 5437fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5438fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5439fcf5ef2aSThomas Huth } 5440fcf5ef2aSThomas Huth 5441fcf5ef2aSThomas Huth /* srliq */ 5442fcf5ef2aSThomas Huth static void gen_srliq(DisasContext *ctx) 5443fcf5ef2aSThomas Huth { 5444fcf5ef2aSThomas Huth int sh = SH(ctx->opcode); 5445fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5446fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5447fcf5ef2aSThomas Huth tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); 5448fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5449fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t0); 5450fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); 5451fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); 5452fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5453fcf5ef2aSThomas Huth tcg_temp_free(t0); 5454fcf5ef2aSThomas Huth tcg_temp_free(t1); 5455fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5456fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5457fcf5ef2aSThomas Huth } 5458fcf5ef2aSThomas Huth 5459fcf5ef2aSThomas Huth /* srlq */ 5460fcf5ef2aSThomas Huth static void gen_srlq(DisasContext *ctx) 5461fcf5ef2aSThomas Huth { 5462fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5463fcf5ef2aSThomas Huth TCGLabel *l2 = gen_new_label(); 5464fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_local_new(); 5465fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_local_new(); 5466fcf5ef2aSThomas Huth TCGv t2 = tcg_temp_local_new(); 5467fcf5ef2aSThomas Huth tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); 5468fcf5ef2aSThomas Huth tcg_gen_movi_tl(t1, 0xFFFFFFFF); 5469fcf5ef2aSThomas Huth tcg_gen_shr_tl(t2, t1, t2); 5470fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); 5471fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5472fcf5ef2aSThomas Huth gen_load_spr(t0, SPR_MQ); 5473fcf5ef2aSThomas Huth tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); 5474fcf5ef2aSThomas Huth tcg_gen_br(l2); 5475fcf5ef2aSThomas Huth gen_set_label(l1); 5476fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); 5477fcf5ef2aSThomas Huth tcg_gen_and_tl(t0, t0, t2); 5478fcf5ef2aSThomas Huth gen_load_spr(t1, SPR_MQ); 5479fcf5ef2aSThomas Huth tcg_gen_andc_tl(t1, t1, t2); 5480fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); 5481fcf5ef2aSThomas Huth gen_set_label(l2); 5482fcf5ef2aSThomas Huth tcg_temp_free(t0); 5483fcf5ef2aSThomas Huth tcg_temp_free(t1); 5484fcf5ef2aSThomas Huth tcg_temp_free(t2); 5485fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5486fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5487fcf5ef2aSThomas Huth } 5488fcf5ef2aSThomas Huth 5489fcf5ef2aSThomas Huth /* srq */ 5490fcf5ef2aSThomas Huth static void gen_srq(DisasContext *ctx) 5491fcf5ef2aSThomas Huth { 5492fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5493fcf5ef2aSThomas Huth TCGv t0 = tcg_temp_new(); 5494fcf5ef2aSThomas Huth TCGv t1 = tcg_temp_new(); 5495fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); 5496fcf5ef2aSThomas Huth tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); 5497fcf5ef2aSThomas Huth tcg_gen_subfi_tl(t1, 32, t1); 5498fcf5ef2aSThomas Huth tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); 5499fcf5ef2aSThomas Huth tcg_gen_or_tl(t1, t0, t1); 5500fcf5ef2aSThomas Huth gen_store_spr(SPR_MQ, t1); 5501fcf5ef2aSThomas Huth tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); 5502fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); 5503fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); 5504fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); 5505fcf5ef2aSThomas Huth gen_set_label(l1); 5506fcf5ef2aSThomas Huth tcg_temp_free(t0); 5507fcf5ef2aSThomas Huth tcg_temp_free(t1); 5508fcf5ef2aSThomas Huth if (unlikely(Rc(ctx->opcode) != 0)) 5509fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); 5510fcf5ef2aSThomas Huth } 5511fcf5ef2aSThomas Huth 5512fcf5ef2aSThomas Huth /* PowerPC 602 specific instructions */ 5513fcf5ef2aSThomas Huth 5514fcf5ef2aSThomas Huth /* dsa */ 5515fcf5ef2aSThomas Huth static void gen_dsa(DisasContext *ctx) 5516fcf5ef2aSThomas Huth { 5517fcf5ef2aSThomas Huth /* XXX: TODO */ 5518fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5519fcf5ef2aSThomas Huth } 5520fcf5ef2aSThomas Huth 5521fcf5ef2aSThomas Huth /* esa */ 5522fcf5ef2aSThomas Huth static void gen_esa(DisasContext *ctx) 5523fcf5ef2aSThomas Huth { 5524fcf5ef2aSThomas Huth /* XXX: TODO */ 5525fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5526fcf5ef2aSThomas Huth } 5527fcf5ef2aSThomas Huth 5528fcf5ef2aSThomas Huth /* mfrom */ 5529fcf5ef2aSThomas Huth static void gen_mfrom(DisasContext *ctx) 5530fcf5ef2aSThomas Huth { 5531fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5532fcf5ef2aSThomas Huth GEN_PRIV; 5533fcf5ef2aSThomas Huth #else 5534fcf5ef2aSThomas Huth CHK_SV; 5535fcf5ef2aSThomas Huth gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 5536fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5537fcf5ef2aSThomas Huth } 5538fcf5ef2aSThomas Huth 5539fcf5ef2aSThomas Huth /* 602 - 603 - G2 TLB management */ 5540fcf5ef2aSThomas Huth 5541fcf5ef2aSThomas Huth /* tlbld */ 5542fcf5ef2aSThomas Huth static void gen_tlbld_6xx(DisasContext *ctx) 5543fcf5ef2aSThomas Huth { 5544fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5545fcf5ef2aSThomas Huth GEN_PRIV; 5546fcf5ef2aSThomas Huth #else 5547fcf5ef2aSThomas Huth CHK_SV; 5548fcf5ef2aSThomas Huth gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5549fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5550fcf5ef2aSThomas Huth } 5551fcf5ef2aSThomas Huth 5552fcf5ef2aSThomas Huth /* tlbli */ 5553fcf5ef2aSThomas Huth static void gen_tlbli_6xx(DisasContext *ctx) 5554fcf5ef2aSThomas Huth { 5555fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5556fcf5ef2aSThomas Huth GEN_PRIV; 5557fcf5ef2aSThomas Huth #else 5558fcf5ef2aSThomas Huth CHK_SV; 5559fcf5ef2aSThomas Huth gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5560fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5561fcf5ef2aSThomas Huth } 5562fcf5ef2aSThomas Huth 5563fcf5ef2aSThomas Huth /* 74xx TLB management */ 5564fcf5ef2aSThomas Huth 5565fcf5ef2aSThomas Huth /* tlbld */ 5566fcf5ef2aSThomas Huth static void gen_tlbld_74xx(DisasContext *ctx) 5567fcf5ef2aSThomas Huth { 5568fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5569fcf5ef2aSThomas Huth GEN_PRIV; 5570fcf5ef2aSThomas Huth #else 5571fcf5ef2aSThomas Huth CHK_SV; 5572fcf5ef2aSThomas Huth gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5573fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5574fcf5ef2aSThomas Huth } 5575fcf5ef2aSThomas Huth 5576fcf5ef2aSThomas Huth /* tlbli */ 5577fcf5ef2aSThomas Huth static void gen_tlbli_74xx(DisasContext *ctx) 5578fcf5ef2aSThomas Huth { 5579fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5580fcf5ef2aSThomas Huth GEN_PRIV; 5581fcf5ef2aSThomas Huth #else 5582fcf5ef2aSThomas Huth CHK_SV; 5583fcf5ef2aSThomas Huth gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5584fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5585fcf5ef2aSThomas Huth } 5586fcf5ef2aSThomas Huth 5587fcf5ef2aSThomas Huth /* POWER instructions not in PowerPC 601 */ 5588fcf5ef2aSThomas Huth 5589fcf5ef2aSThomas Huth /* clf */ 5590fcf5ef2aSThomas Huth static void gen_clf(DisasContext *ctx) 5591fcf5ef2aSThomas Huth { 5592fcf5ef2aSThomas Huth /* Cache line flush: implemented as no-op */ 5593fcf5ef2aSThomas Huth } 5594fcf5ef2aSThomas Huth 5595fcf5ef2aSThomas Huth /* cli */ 5596fcf5ef2aSThomas Huth static void gen_cli(DisasContext *ctx) 5597fcf5ef2aSThomas Huth { 5598fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5599fcf5ef2aSThomas Huth GEN_PRIV; 5600fcf5ef2aSThomas Huth #else 5601fcf5ef2aSThomas Huth /* Cache line invalidate: privileged and treated as no-op */ 5602fcf5ef2aSThomas Huth CHK_SV; 5603fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5604fcf5ef2aSThomas Huth } 5605fcf5ef2aSThomas Huth 5606fcf5ef2aSThomas Huth /* dclst */ 5607fcf5ef2aSThomas Huth static void gen_dclst(DisasContext *ctx) 5608fcf5ef2aSThomas Huth { 5609fcf5ef2aSThomas Huth /* Data cache line store: treated as no-op */ 5610fcf5ef2aSThomas Huth } 5611fcf5ef2aSThomas Huth 5612fcf5ef2aSThomas Huth static void gen_mfsri(DisasContext *ctx) 5613fcf5ef2aSThomas Huth { 5614fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5615fcf5ef2aSThomas Huth GEN_PRIV; 5616fcf5ef2aSThomas Huth #else 5617fcf5ef2aSThomas Huth int ra = rA(ctx->opcode); 5618fcf5ef2aSThomas Huth int rd = rD(ctx->opcode); 5619fcf5ef2aSThomas Huth TCGv t0; 5620fcf5ef2aSThomas Huth 5621fcf5ef2aSThomas Huth CHK_SV; 5622fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5623fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5624e2622073SPhilippe Mathieu-Daudé tcg_gen_extract_tl(t0, t0, 28, 4); 5625fcf5ef2aSThomas Huth gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); 5626fcf5ef2aSThomas Huth tcg_temp_free(t0); 5627fcf5ef2aSThomas Huth if (ra != 0 && ra != rd) 5628fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); 5629fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5630fcf5ef2aSThomas Huth } 5631fcf5ef2aSThomas Huth 5632fcf5ef2aSThomas Huth static void gen_rac(DisasContext *ctx) 5633fcf5ef2aSThomas Huth { 5634fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5635fcf5ef2aSThomas Huth GEN_PRIV; 5636fcf5ef2aSThomas Huth #else 5637fcf5ef2aSThomas Huth TCGv t0; 5638fcf5ef2aSThomas Huth 5639fcf5ef2aSThomas Huth CHK_SV; 5640fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5641fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5642fcf5ef2aSThomas Huth gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 5643fcf5ef2aSThomas Huth tcg_temp_free(t0); 5644fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5645fcf5ef2aSThomas Huth } 5646fcf5ef2aSThomas Huth 5647fcf5ef2aSThomas Huth static void gen_rfsvc(DisasContext *ctx) 5648fcf5ef2aSThomas Huth { 5649fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5650fcf5ef2aSThomas Huth GEN_PRIV; 5651fcf5ef2aSThomas Huth #else 5652fcf5ef2aSThomas Huth CHK_SV; 5653fcf5ef2aSThomas Huth 5654fcf5ef2aSThomas Huth gen_helper_rfsvc(cpu_env); 5655fcf5ef2aSThomas Huth gen_sync_exception(ctx); 5656fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5657fcf5ef2aSThomas Huth } 5658fcf5ef2aSThomas Huth 5659fcf5ef2aSThomas Huth /* svc is not implemented for now */ 5660fcf5ef2aSThomas Huth 5661fcf5ef2aSThomas Huth /* BookE specific instructions */ 5662fcf5ef2aSThomas Huth 5663fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5664fcf5ef2aSThomas Huth static void gen_mfapidi(DisasContext *ctx) 5665fcf5ef2aSThomas Huth { 5666fcf5ef2aSThomas Huth /* XXX: TODO */ 5667fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 5668fcf5ef2aSThomas Huth } 5669fcf5ef2aSThomas Huth 5670fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5671fcf5ef2aSThomas Huth static void gen_tlbiva(DisasContext *ctx) 5672fcf5ef2aSThomas Huth { 5673fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5674fcf5ef2aSThomas Huth GEN_PRIV; 5675fcf5ef2aSThomas Huth #else 5676fcf5ef2aSThomas Huth TCGv t0; 5677fcf5ef2aSThomas Huth 5678fcf5ef2aSThomas Huth CHK_SV; 5679fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 5680fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 5681fcf5ef2aSThomas Huth gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); 5682fcf5ef2aSThomas Huth tcg_temp_free(t0); 5683fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5684fcf5ef2aSThomas Huth } 5685fcf5ef2aSThomas Huth 5686fcf5ef2aSThomas Huth /* All 405 MAC instructions are translated here */ 5687fcf5ef2aSThomas Huth static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, 5688fcf5ef2aSThomas Huth int ra, int rb, int rt, int Rc) 5689fcf5ef2aSThomas Huth { 5690fcf5ef2aSThomas Huth TCGv t0, t1; 5691fcf5ef2aSThomas Huth 5692fcf5ef2aSThomas Huth t0 = tcg_temp_local_new(); 5693fcf5ef2aSThomas Huth t1 = tcg_temp_local_new(); 5694fcf5ef2aSThomas Huth 5695fcf5ef2aSThomas Huth switch (opc3 & 0x0D) { 5696fcf5ef2aSThomas Huth case 0x05: 5697fcf5ef2aSThomas Huth /* macchw - macchw. - macchwo - macchwo. */ 5698fcf5ef2aSThomas Huth /* macchws - macchws. - macchwso - macchwso. */ 5699fcf5ef2aSThomas Huth /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ 5700fcf5ef2aSThomas Huth /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ 5701fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5702fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5703fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5704fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5705fcf5ef2aSThomas Huth break; 5706fcf5ef2aSThomas Huth case 0x04: 5707fcf5ef2aSThomas Huth /* macchwu - macchwu. - macchwuo - macchwuo. */ 5708fcf5ef2aSThomas Huth /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ 5709fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5710fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5711fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5712fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5713fcf5ef2aSThomas Huth break; 5714fcf5ef2aSThomas Huth case 0x01: 5715fcf5ef2aSThomas Huth /* machhw - machhw. - machhwo - machhwo. */ 5716fcf5ef2aSThomas Huth /* machhws - machhws. - machhwso - machhwso. */ 5717fcf5ef2aSThomas Huth /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ 5718fcf5ef2aSThomas Huth /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ 5719fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5720fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); 5721fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, t0); 5722fcf5ef2aSThomas Huth tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); 5723fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, t1); 5724fcf5ef2aSThomas Huth break; 5725fcf5ef2aSThomas Huth case 0x00: 5726fcf5ef2aSThomas Huth /* machhwu - machhwu. - machhwuo - machhwuo. */ 5727fcf5ef2aSThomas Huth /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ 5728fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5729fcf5ef2aSThomas Huth tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); 5730fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, t0); 5731fcf5ef2aSThomas Huth tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); 5732fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, t1); 5733fcf5ef2aSThomas Huth break; 5734fcf5ef2aSThomas Huth case 0x0D: 5735fcf5ef2aSThomas Huth /* maclhw - maclhw. - maclhwo - maclhwo. */ 5736fcf5ef2aSThomas Huth /* maclhws - maclhws. - maclhwso - maclhwso. */ 5737fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ 5738fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ 5739fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5740fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); 5741fcf5ef2aSThomas Huth tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); 5742fcf5ef2aSThomas Huth break; 5743fcf5ef2aSThomas Huth case 0x0C: 5744fcf5ef2aSThomas Huth /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ 5745fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ 5746fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5747fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); 5748fcf5ef2aSThomas Huth tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); 5749fcf5ef2aSThomas Huth break; 5750fcf5ef2aSThomas Huth } 5751fcf5ef2aSThomas Huth if (opc2 & 0x04) { 5752fcf5ef2aSThomas Huth /* (n)multiply-and-accumulate (0x0C / 0x0E) */ 5753fcf5ef2aSThomas Huth tcg_gen_mul_tl(t1, t0, t1); 5754fcf5ef2aSThomas Huth if (opc2 & 0x02) { 5755fcf5ef2aSThomas Huth /* nmultiply-and-accumulate (0x0E) */ 5756fcf5ef2aSThomas Huth tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); 5757fcf5ef2aSThomas Huth } else { 5758fcf5ef2aSThomas Huth /* multiply-and-accumulate (0x0C) */ 5759fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, cpu_gpr[rt], t1); 5760fcf5ef2aSThomas Huth } 5761fcf5ef2aSThomas Huth 5762fcf5ef2aSThomas Huth if (opc3 & 0x12) { 5763fcf5ef2aSThomas Huth /* Check overflow and/or saturate */ 5764fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 5765fcf5ef2aSThomas Huth 5766fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5767fcf5ef2aSThomas Huth /* Start with XER OV disabled, the most likely case */ 5768fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 0); 5769fcf5ef2aSThomas Huth } 5770fcf5ef2aSThomas Huth if (opc3 & 0x01) { 5771fcf5ef2aSThomas Huth /* Signed */ 5772fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); 5773fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); 5774fcf5ef2aSThomas Huth tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); 5775fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); 5776fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5777fcf5ef2aSThomas Huth /* Saturate */ 5778fcf5ef2aSThomas Huth tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); 5779fcf5ef2aSThomas Huth tcg_gen_xori_tl(t0, t0, 0x7fffffff); 5780fcf5ef2aSThomas Huth } 5781fcf5ef2aSThomas Huth } else { 5782fcf5ef2aSThomas Huth /* Unsigned */ 5783fcf5ef2aSThomas Huth tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); 5784fcf5ef2aSThomas Huth if (opc3 & 0x02) { 5785fcf5ef2aSThomas Huth /* Saturate */ 5786fcf5ef2aSThomas Huth tcg_gen_movi_tl(t0, UINT32_MAX); 5787fcf5ef2aSThomas Huth } 5788fcf5ef2aSThomas Huth } 5789fcf5ef2aSThomas Huth if (opc3 & 0x10) { 5790fcf5ef2aSThomas Huth /* Check overflow */ 5791fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_ov, 1); 5792fcf5ef2aSThomas Huth tcg_gen_movi_tl(cpu_so, 1); 5793fcf5ef2aSThomas Huth } 5794fcf5ef2aSThomas Huth gen_set_label(l1); 5795fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rt], t0); 5796fcf5ef2aSThomas Huth } 5797fcf5ef2aSThomas Huth } else { 5798fcf5ef2aSThomas Huth tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); 5799fcf5ef2aSThomas Huth } 5800fcf5ef2aSThomas Huth tcg_temp_free(t0); 5801fcf5ef2aSThomas Huth tcg_temp_free(t1); 5802fcf5ef2aSThomas Huth if (unlikely(Rc) != 0) { 5803fcf5ef2aSThomas Huth /* Update Rc0 */ 5804fcf5ef2aSThomas Huth gen_set_Rc0(ctx, cpu_gpr[rt]); 5805fcf5ef2aSThomas Huth } 5806fcf5ef2aSThomas Huth } 5807fcf5ef2aSThomas Huth 5808fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 5809fcf5ef2aSThomas Huth static void glue(gen_, name)(DisasContext *ctx) \ 5810fcf5ef2aSThomas Huth { \ 5811fcf5ef2aSThomas Huth gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ 5812fcf5ef2aSThomas Huth rD(ctx->opcode), Rc(ctx->opcode)); \ 5813fcf5ef2aSThomas Huth } 5814fcf5ef2aSThomas Huth 5815fcf5ef2aSThomas Huth /* macchw - macchw. */ 5816fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05); 5817fcf5ef2aSThomas Huth /* macchwo - macchwo. */ 5818fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); 5819fcf5ef2aSThomas Huth /* macchws - macchws. */ 5820fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07); 5821fcf5ef2aSThomas Huth /* macchwso - macchwso. */ 5822fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); 5823fcf5ef2aSThomas Huth /* macchwsu - macchwsu. */ 5824fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); 5825fcf5ef2aSThomas Huth /* macchwsuo - macchwsuo. */ 5826fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); 5827fcf5ef2aSThomas Huth /* macchwu - macchwu. */ 5828fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); 5829fcf5ef2aSThomas Huth /* macchwuo - macchwuo. */ 5830fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); 5831fcf5ef2aSThomas Huth /* machhw - machhw. */ 5832fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01); 5833fcf5ef2aSThomas Huth /* machhwo - machhwo. */ 5834fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); 5835fcf5ef2aSThomas Huth /* machhws - machhws. */ 5836fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03); 5837fcf5ef2aSThomas Huth /* machhwso - machhwso. */ 5838fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); 5839fcf5ef2aSThomas Huth /* machhwsu - machhwsu. */ 5840fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); 5841fcf5ef2aSThomas Huth /* machhwsuo - machhwsuo. */ 5842fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); 5843fcf5ef2aSThomas Huth /* machhwu - machhwu. */ 5844fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); 5845fcf5ef2aSThomas Huth /* machhwuo - machhwuo. */ 5846fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); 5847fcf5ef2aSThomas Huth /* maclhw - maclhw. */ 5848fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); 5849fcf5ef2aSThomas Huth /* maclhwo - maclhwo. */ 5850fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); 5851fcf5ef2aSThomas Huth /* maclhws - maclhws. */ 5852fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); 5853fcf5ef2aSThomas Huth /* maclhwso - maclhwso. */ 5854fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); 5855fcf5ef2aSThomas Huth /* maclhwu - maclhwu. */ 5856fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); 5857fcf5ef2aSThomas Huth /* maclhwuo - maclhwuo. */ 5858fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); 5859fcf5ef2aSThomas Huth /* maclhwsu - maclhwsu. */ 5860fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); 5861fcf5ef2aSThomas Huth /* maclhwsuo - maclhwsuo. */ 5862fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); 5863fcf5ef2aSThomas Huth /* nmacchw - nmacchw. */ 5864fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); 5865fcf5ef2aSThomas Huth /* nmacchwo - nmacchwo. */ 5866fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); 5867fcf5ef2aSThomas Huth /* nmacchws - nmacchws. */ 5868fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); 5869fcf5ef2aSThomas Huth /* nmacchwso - nmacchwso. */ 5870fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); 5871fcf5ef2aSThomas Huth /* nmachhw - nmachhw. */ 5872fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); 5873fcf5ef2aSThomas Huth /* nmachhwo - nmachhwo. */ 5874fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); 5875fcf5ef2aSThomas Huth /* nmachhws - nmachhws. */ 5876fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); 5877fcf5ef2aSThomas Huth /* nmachhwso - nmachhwso. */ 5878fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); 5879fcf5ef2aSThomas Huth /* nmaclhw - nmaclhw. */ 5880fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); 5881fcf5ef2aSThomas Huth /* nmaclhwo - nmaclhwo. */ 5882fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); 5883fcf5ef2aSThomas Huth /* nmaclhws - nmaclhws. */ 5884fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); 5885fcf5ef2aSThomas Huth /* nmaclhwso - nmaclhwso. */ 5886fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); 5887fcf5ef2aSThomas Huth 5888fcf5ef2aSThomas Huth /* mulchw - mulchw. */ 5889fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05); 5890fcf5ef2aSThomas Huth /* mulchwu - mulchwu. */ 5891fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); 5892fcf5ef2aSThomas Huth /* mulhhw - mulhhw. */ 5893fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); 5894fcf5ef2aSThomas Huth /* mulhhwu - mulhhwu. */ 5895fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); 5896fcf5ef2aSThomas Huth /* mullhw - mullhw. */ 5897fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); 5898fcf5ef2aSThomas Huth /* mullhwu - mullhwu. */ 5899fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); 5900fcf5ef2aSThomas Huth 5901fcf5ef2aSThomas Huth /* mfdcr */ 5902fcf5ef2aSThomas Huth static void gen_mfdcr(DisasContext *ctx) 5903fcf5ef2aSThomas Huth { 5904fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5905fcf5ef2aSThomas Huth GEN_PRIV; 5906fcf5ef2aSThomas Huth #else 5907fcf5ef2aSThomas Huth TCGv dcrn; 5908fcf5ef2aSThomas Huth 5909fcf5ef2aSThomas Huth CHK_SV; 5910fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5911fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); 5912fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5913fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5914fcf5ef2aSThomas Huth } 5915fcf5ef2aSThomas Huth 5916fcf5ef2aSThomas Huth /* mtdcr */ 5917fcf5ef2aSThomas Huth static void gen_mtdcr(DisasContext *ctx) 5918fcf5ef2aSThomas Huth { 5919fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5920fcf5ef2aSThomas Huth GEN_PRIV; 5921fcf5ef2aSThomas Huth #else 5922fcf5ef2aSThomas Huth TCGv dcrn; 5923fcf5ef2aSThomas Huth 5924fcf5ef2aSThomas Huth CHK_SV; 5925fcf5ef2aSThomas Huth dcrn = tcg_const_tl(SPR(ctx->opcode)); 5926fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); 5927fcf5ef2aSThomas Huth tcg_temp_free(dcrn); 5928fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5929fcf5ef2aSThomas Huth } 5930fcf5ef2aSThomas Huth 5931fcf5ef2aSThomas Huth /* mfdcrx */ 5932fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5933fcf5ef2aSThomas Huth static void gen_mfdcrx(DisasContext *ctx) 5934fcf5ef2aSThomas Huth { 5935fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5936fcf5ef2aSThomas Huth GEN_PRIV; 5937fcf5ef2aSThomas Huth #else 5938fcf5ef2aSThomas Huth CHK_SV; 5939fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5940fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5941fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5942fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5943fcf5ef2aSThomas Huth } 5944fcf5ef2aSThomas Huth 5945fcf5ef2aSThomas Huth /* mtdcrx */ 5946fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 5947fcf5ef2aSThomas Huth static void gen_mtdcrx(DisasContext *ctx) 5948fcf5ef2aSThomas Huth { 5949fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5950fcf5ef2aSThomas Huth GEN_PRIV; 5951fcf5ef2aSThomas Huth #else 5952fcf5ef2aSThomas Huth CHK_SV; 5953fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5954fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5955fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5956fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 5957fcf5ef2aSThomas Huth } 5958fcf5ef2aSThomas Huth 5959fcf5ef2aSThomas Huth /* mfdcrux (PPC 460) : user-mode access to DCR */ 5960fcf5ef2aSThomas Huth static void gen_mfdcrux(DisasContext *ctx) 5961fcf5ef2aSThomas Huth { 5962fcf5ef2aSThomas Huth gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, 5963fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 5964fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5965fcf5ef2aSThomas Huth } 5966fcf5ef2aSThomas Huth 5967fcf5ef2aSThomas Huth /* mtdcrux (PPC 460) : user-mode access to DCR */ 5968fcf5ef2aSThomas Huth static void gen_mtdcrux(DisasContext *ctx) 5969fcf5ef2aSThomas Huth { 5970fcf5ef2aSThomas Huth gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], 5971fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 5972fcf5ef2aSThomas Huth /* Note: Rc update flag set leads to undefined state of Rc0 */ 5973fcf5ef2aSThomas Huth } 5974fcf5ef2aSThomas Huth 5975fcf5ef2aSThomas Huth /* dccci */ 5976fcf5ef2aSThomas Huth static void gen_dccci(DisasContext *ctx) 5977fcf5ef2aSThomas Huth { 5978fcf5ef2aSThomas Huth CHK_SV; 5979fcf5ef2aSThomas Huth /* interpreted as no-op */ 5980fcf5ef2aSThomas Huth } 5981fcf5ef2aSThomas Huth 5982fcf5ef2aSThomas Huth /* dcread */ 5983fcf5ef2aSThomas Huth static void gen_dcread(DisasContext *ctx) 5984fcf5ef2aSThomas Huth { 5985fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 5986fcf5ef2aSThomas Huth GEN_PRIV; 5987fcf5ef2aSThomas Huth #else 5988fcf5ef2aSThomas Huth TCGv EA, val; 5989fcf5ef2aSThomas Huth 5990fcf5ef2aSThomas Huth CHK_SV; 5991fcf5ef2aSThomas Huth gen_set_access_type(ctx, ACCESS_CACHE); 5992fcf5ef2aSThomas Huth EA = tcg_temp_new(); 5993fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, EA); 5994fcf5ef2aSThomas Huth val = tcg_temp_new(); 5995fcf5ef2aSThomas Huth gen_qemu_ld32u(ctx, val, EA); 5996fcf5ef2aSThomas Huth tcg_temp_free(val); 5997fcf5ef2aSThomas Huth tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); 5998fcf5ef2aSThomas Huth tcg_temp_free(EA); 5999fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6000fcf5ef2aSThomas Huth } 6001fcf5ef2aSThomas Huth 6002fcf5ef2aSThomas Huth /* icbt */ 6003fcf5ef2aSThomas Huth static void gen_icbt_40x(DisasContext *ctx) 6004fcf5ef2aSThomas Huth { 6005fcf5ef2aSThomas Huth /* interpreted as no-op */ 6006fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6007fcf5ef2aSThomas Huth * but does not generate any exception 6008fcf5ef2aSThomas Huth */ 6009fcf5ef2aSThomas Huth } 6010fcf5ef2aSThomas Huth 6011fcf5ef2aSThomas Huth /* iccci */ 6012fcf5ef2aSThomas Huth static void gen_iccci(DisasContext *ctx) 6013fcf5ef2aSThomas Huth { 6014fcf5ef2aSThomas Huth CHK_SV; 6015fcf5ef2aSThomas Huth /* interpreted as no-op */ 6016fcf5ef2aSThomas Huth } 6017fcf5ef2aSThomas Huth 6018fcf5ef2aSThomas Huth /* icread */ 6019fcf5ef2aSThomas Huth static void gen_icread(DisasContext *ctx) 6020fcf5ef2aSThomas Huth { 6021fcf5ef2aSThomas Huth CHK_SV; 6022fcf5ef2aSThomas Huth /* interpreted as no-op */ 6023fcf5ef2aSThomas Huth } 6024fcf5ef2aSThomas Huth 6025fcf5ef2aSThomas Huth /* rfci (supervisor only) */ 6026fcf5ef2aSThomas Huth static void gen_rfci_40x(DisasContext *ctx) 6027fcf5ef2aSThomas Huth { 6028fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6029fcf5ef2aSThomas Huth GEN_PRIV; 6030fcf5ef2aSThomas Huth #else 6031fcf5ef2aSThomas Huth CHK_SV; 6032fcf5ef2aSThomas Huth /* Restore CPU state */ 6033fcf5ef2aSThomas Huth gen_helper_40x_rfci(cpu_env); 6034fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6035fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6036fcf5ef2aSThomas Huth } 6037fcf5ef2aSThomas Huth 6038fcf5ef2aSThomas Huth static void gen_rfci(DisasContext *ctx) 6039fcf5ef2aSThomas Huth { 6040fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6041fcf5ef2aSThomas Huth GEN_PRIV; 6042fcf5ef2aSThomas Huth #else 6043fcf5ef2aSThomas Huth CHK_SV; 6044fcf5ef2aSThomas Huth /* Restore CPU state */ 6045fcf5ef2aSThomas Huth gen_helper_rfci(cpu_env); 6046fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6047fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6048fcf5ef2aSThomas Huth } 6049fcf5ef2aSThomas Huth 6050fcf5ef2aSThomas Huth /* BookE specific */ 6051fcf5ef2aSThomas Huth 6052fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6053fcf5ef2aSThomas Huth static void gen_rfdi(DisasContext *ctx) 6054fcf5ef2aSThomas Huth { 6055fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6056fcf5ef2aSThomas Huth GEN_PRIV; 6057fcf5ef2aSThomas Huth #else 6058fcf5ef2aSThomas Huth CHK_SV; 6059fcf5ef2aSThomas Huth /* Restore CPU state */ 6060fcf5ef2aSThomas Huth gen_helper_rfdi(cpu_env); 6061fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6062fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6063fcf5ef2aSThomas Huth } 6064fcf5ef2aSThomas Huth 6065fcf5ef2aSThomas Huth /* XXX: not implemented on 440 ? */ 6066fcf5ef2aSThomas Huth static void gen_rfmci(DisasContext *ctx) 6067fcf5ef2aSThomas Huth { 6068fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6069fcf5ef2aSThomas Huth GEN_PRIV; 6070fcf5ef2aSThomas Huth #else 6071fcf5ef2aSThomas Huth CHK_SV; 6072fcf5ef2aSThomas Huth /* Restore CPU state */ 6073fcf5ef2aSThomas Huth gen_helper_rfmci(cpu_env); 6074fcf5ef2aSThomas Huth gen_sync_exception(ctx); 6075fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6076fcf5ef2aSThomas Huth } 6077fcf5ef2aSThomas Huth 6078fcf5ef2aSThomas Huth /* TLB management - PowerPC 405 implementation */ 6079fcf5ef2aSThomas Huth 6080fcf5ef2aSThomas Huth /* tlbre */ 6081fcf5ef2aSThomas Huth static void gen_tlbre_40x(DisasContext *ctx) 6082fcf5ef2aSThomas Huth { 6083fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6084fcf5ef2aSThomas Huth GEN_PRIV; 6085fcf5ef2aSThomas Huth #else 6086fcf5ef2aSThomas Huth CHK_SV; 6087fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6088fcf5ef2aSThomas Huth case 0: 6089fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, 6090fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6091fcf5ef2aSThomas Huth break; 6092fcf5ef2aSThomas Huth case 1: 6093fcf5ef2aSThomas Huth gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, 6094fcf5ef2aSThomas Huth cpu_gpr[rA(ctx->opcode)]); 6095fcf5ef2aSThomas Huth break; 6096fcf5ef2aSThomas Huth default: 6097fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6098fcf5ef2aSThomas Huth break; 6099fcf5ef2aSThomas Huth } 6100fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6101fcf5ef2aSThomas Huth } 6102fcf5ef2aSThomas Huth 6103fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6104fcf5ef2aSThomas Huth static void gen_tlbsx_40x(DisasContext *ctx) 6105fcf5ef2aSThomas Huth { 6106fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6107fcf5ef2aSThomas Huth GEN_PRIV; 6108fcf5ef2aSThomas Huth #else 6109fcf5ef2aSThomas Huth TCGv t0; 6110fcf5ef2aSThomas Huth 6111fcf5ef2aSThomas Huth CHK_SV; 6112fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6113fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6114fcf5ef2aSThomas Huth gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6115fcf5ef2aSThomas Huth tcg_temp_free(t0); 6116fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6117fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6118fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6119fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6120fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6121fcf5ef2aSThomas Huth gen_set_label(l1); 6122fcf5ef2aSThomas Huth } 6123fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6124fcf5ef2aSThomas Huth } 6125fcf5ef2aSThomas Huth 6126fcf5ef2aSThomas Huth /* tlbwe */ 6127fcf5ef2aSThomas Huth static void gen_tlbwe_40x(DisasContext *ctx) 6128fcf5ef2aSThomas Huth { 6129fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6130fcf5ef2aSThomas Huth GEN_PRIV; 6131fcf5ef2aSThomas Huth #else 6132fcf5ef2aSThomas Huth CHK_SV; 6133fcf5ef2aSThomas Huth 6134fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6135fcf5ef2aSThomas Huth case 0: 6136fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], 6137fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6138fcf5ef2aSThomas Huth break; 6139fcf5ef2aSThomas Huth case 1: 6140fcf5ef2aSThomas Huth gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], 6141fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6142fcf5ef2aSThomas Huth break; 6143fcf5ef2aSThomas Huth default: 6144fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6145fcf5ef2aSThomas Huth break; 6146fcf5ef2aSThomas Huth } 6147fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6148fcf5ef2aSThomas Huth } 6149fcf5ef2aSThomas Huth 6150fcf5ef2aSThomas Huth /* TLB management - PowerPC 440 implementation */ 6151fcf5ef2aSThomas Huth 6152fcf5ef2aSThomas Huth /* tlbre */ 6153fcf5ef2aSThomas Huth static void gen_tlbre_440(DisasContext *ctx) 6154fcf5ef2aSThomas Huth { 6155fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6156fcf5ef2aSThomas Huth GEN_PRIV; 6157fcf5ef2aSThomas Huth #else 6158fcf5ef2aSThomas Huth CHK_SV; 6159fcf5ef2aSThomas Huth 6160fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6161fcf5ef2aSThomas Huth case 0: 6162fcf5ef2aSThomas Huth case 1: 6163fcf5ef2aSThomas Huth case 2: 6164fcf5ef2aSThomas Huth { 6165fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6166fcf5ef2aSThomas Huth gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, 6167fcf5ef2aSThomas Huth t0, cpu_gpr[rA(ctx->opcode)]); 6168fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6169fcf5ef2aSThomas Huth } 6170fcf5ef2aSThomas Huth break; 6171fcf5ef2aSThomas Huth default: 6172fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6173fcf5ef2aSThomas Huth break; 6174fcf5ef2aSThomas Huth } 6175fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6176fcf5ef2aSThomas Huth } 6177fcf5ef2aSThomas Huth 6178fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6179fcf5ef2aSThomas Huth static void gen_tlbsx_440(DisasContext *ctx) 6180fcf5ef2aSThomas Huth { 6181fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6182fcf5ef2aSThomas Huth GEN_PRIV; 6183fcf5ef2aSThomas Huth #else 6184fcf5ef2aSThomas Huth TCGv t0; 6185fcf5ef2aSThomas Huth 6186fcf5ef2aSThomas Huth CHK_SV; 6187fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6188fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6189fcf5ef2aSThomas Huth gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); 6190fcf5ef2aSThomas Huth tcg_temp_free(t0); 6191fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6192fcf5ef2aSThomas Huth TCGLabel *l1 = gen_new_label(); 6193fcf5ef2aSThomas Huth tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); 6194fcf5ef2aSThomas Huth tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); 6195fcf5ef2aSThomas Huth tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); 6196fcf5ef2aSThomas Huth gen_set_label(l1); 6197fcf5ef2aSThomas Huth } 6198fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6199fcf5ef2aSThomas Huth } 6200fcf5ef2aSThomas Huth 6201fcf5ef2aSThomas Huth /* tlbwe */ 6202fcf5ef2aSThomas Huth static void gen_tlbwe_440(DisasContext *ctx) 6203fcf5ef2aSThomas Huth { 6204fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6205fcf5ef2aSThomas Huth GEN_PRIV; 6206fcf5ef2aSThomas Huth #else 6207fcf5ef2aSThomas Huth CHK_SV; 6208fcf5ef2aSThomas Huth switch (rB(ctx->opcode)) { 6209fcf5ef2aSThomas Huth case 0: 6210fcf5ef2aSThomas Huth case 1: 6211fcf5ef2aSThomas Huth case 2: 6212fcf5ef2aSThomas Huth { 6213fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); 6214fcf5ef2aSThomas Huth gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], 6215fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)]); 6216fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6217fcf5ef2aSThomas Huth } 6218fcf5ef2aSThomas Huth break; 6219fcf5ef2aSThomas Huth default: 6220fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6221fcf5ef2aSThomas Huth break; 6222fcf5ef2aSThomas Huth } 6223fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6224fcf5ef2aSThomas Huth } 6225fcf5ef2aSThomas Huth 6226fcf5ef2aSThomas Huth /* TLB management - PowerPC BookE 2.06 implementation */ 6227fcf5ef2aSThomas Huth 6228fcf5ef2aSThomas Huth /* tlbre */ 6229fcf5ef2aSThomas Huth static void gen_tlbre_booke206(DisasContext *ctx) 6230fcf5ef2aSThomas Huth { 6231fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6232fcf5ef2aSThomas Huth GEN_PRIV; 6233fcf5ef2aSThomas Huth #else 6234fcf5ef2aSThomas Huth CHK_SV; 6235fcf5ef2aSThomas Huth gen_helper_booke206_tlbre(cpu_env); 6236fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6237fcf5ef2aSThomas Huth } 6238fcf5ef2aSThomas Huth 6239fcf5ef2aSThomas Huth /* tlbsx - tlbsx. */ 6240fcf5ef2aSThomas Huth static void gen_tlbsx_booke206(DisasContext *ctx) 6241fcf5ef2aSThomas Huth { 6242fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6243fcf5ef2aSThomas Huth GEN_PRIV; 6244fcf5ef2aSThomas Huth #else 6245fcf5ef2aSThomas Huth TCGv t0; 6246fcf5ef2aSThomas Huth 6247fcf5ef2aSThomas Huth CHK_SV; 6248fcf5ef2aSThomas Huth if (rA(ctx->opcode)) { 6249fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6250fcf5ef2aSThomas Huth tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); 6251fcf5ef2aSThomas Huth } else { 6252fcf5ef2aSThomas Huth t0 = tcg_const_tl(0); 6253fcf5ef2aSThomas Huth } 6254fcf5ef2aSThomas Huth 6255fcf5ef2aSThomas Huth tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); 6256fcf5ef2aSThomas Huth gen_helper_booke206_tlbsx(cpu_env, t0); 6257fcf5ef2aSThomas Huth tcg_temp_free(t0); 6258fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6259fcf5ef2aSThomas Huth } 6260fcf5ef2aSThomas Huth 6261fcf5ef2aSThomas Huth /* tlbwe */ 6262fcf5ef2aSThomas Huth static void gen_tlbwe_booke206(DisasContext *ctx) 6263fcf5ef2aSThomas Huth { 6264fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6265fcf5ef2aSThomas Huth GEN_PRIV; 6266fcf5ef2aSThomas Huth #else 6267fcf5ef2aSThomas Huth CHK_SV; 6268fcf5ef2aSThomas Huth gen_helper_booke206_tlbwe(cpu_env); 6269fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6270fcf5ef2aSThomas Huth } 6271fcf5ef2aSThomas Huth 6272fcf5ef2aSThomas Huth static void gen_tlbivax_booke206(DisasContext *ctx) 6273fcf5ef2aSThomas Huth { 6274fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6275fcf5ef2aSThomas Huth GEN_PRIV; 6276fcf5ef2aSThomas Huth #else 6277fcf5ef2aSThomas Huth TCGv t0; 6278fcf5ef2aSThomas Huth 6279fcf5ef2aSThomas Huth CHK_SV; 6280fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6281fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6282fcf5ef2aSThomas Huth gen_helper_booke206_tlbivax(cpu_env, t0); 6283fcf5ef2aSThomas Huth tcg_temp_free(t0); 6284fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6285fcf5ef2aSThomas Huth } 6286fcf5ef2aSThomas Huth 6287fcf5ef2aSThomas Huth static void gen_tlbilx_booke206(DisasContext *ctx) 6288fcf5ef2aSThomas Huth { 6289fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6290fcf5ef2aSThomas Huth GEN_PRIV; 6291fcf5ef2aSThomas Huth #else 6292fcf5ef2aSThomas Huth TCGv t0; 6293fcf5ef2aSThomas Huth 6294fcf5ef2aSThomas Huth CHK_SV; 6295fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6296fcf5ef2aSThomas Huth gen_addr_reg_index(ctx, t0); 6297fcf5ef2aSThomas Huth 6298fcf5ef2aSThomas Huth switch((ctx->opcode >> 21) & 0x3) { 6299fcf5ef2aSThomas Huth case 0: 6300fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx0(cpu_env, t0); 6301fcf5ef2aSThomas Huth break; 6302fcf5ef2aSThomas Huth case 1: 6303fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx1(cpu_env, t0); 6304fcf5ef2aSThomas Huth break; 6305fcf5ef2aSThomas Huth case 3: 6306fcf5ef2aSThomas Huth gen_helper_booke206_tlbilx3(cpu_env, t0); 6307fcf5ef2aSThomas Huth break; 6308fcf5ef2aSThomas Huth default: 6309fcf5ef2aSThomas Huth gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 6310fcf5ef2aSThomas Huth break; 6311fcf5ef2aSThomas Huth } 6312fcf5ef2aSThomas Huth 6313fcf5ef2aSThomas Huth tcg_temp_free(t0); 6314fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6315fcf5ef2aSThomas Huth } 6316fcf5ef2aSThomas Huth 6317fcf5ef2aSThomas Huth 6318fcf5ef2aSThomas Huth /* wrtee */ 6319fcf5ef2aSThomas Huth static void gen_wrtee(DisasContext *ctx) 6320fcf5ef2aSThomas Huth { 6321fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6322fcf5ef2aSThomas Huth GEN_PRIV; 6323fcf5ef2aSThomas Huth #else 6324fcf5ef2aSThomas Huth TCGv t0; 6325fcf5ef2aSThomas Huth 6326fcf5ef2aSThomas Huth CHK_SV; 6327fcf5ef2aSThomas Huth t0 = tcg_temp_new(); 6328fcf5ef2aSThomas Huth tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); 6329fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6330fcf5ef2aSThomas Huth tcg_gen_or_tl(cpu_msr, cpu_msr, t0); 6331fcf5ef2aSThomas Huth tcg_temp_free(t0); 6332fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception 6333fcf5ef2aSThomas Huth * if we just set msr_ee to 1 6334fcf5ef2aSThomas Huth */ 6335fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6336fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6337fcf5ef2aSThomas Huth } 6338fcf5ef2aSThomas Huth 6339fcf5ef2aSThomas Huth /* wrteei */ 6340fcf5ef2aSThomas Huth static void gen_wrteei(DisasContext *ctx) 6341fcf5ef2aSThomas Huth { 6342fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6343fcf5ef2aSThomas Huth GEN_PRIV; 6344fcf5ef2aSThomas Huth #else 6345fcf5ef2aSThomas Huth CHK_SV; 6346fcf5ef2aSThomas Huth if (ctx->opcode & 0x00008000) { 6347fcf5ef2aSThomas Huth tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); 6348fcf5ef2aSThomas Huth /* Stop translation to have a chance to raise an exception */ 6349fcf5ef2aSThomas Huth gen_stop_exception(ctx); 6350fcf5ef2aSThomas Huth } else { 6351fcf5ef2aSThomas Huth tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); 6352fcf5ef2aSThomas Huth } 6353fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6354fcf5ef2aSThomas Huth } 6355fcf5ef2aSThomas Huth 6356fcf5ef2aSThomas Huth /* PowerPC 440 specific instructions */ 6357fcf5ef2aSThomas Huth 6358fcf5ef2aSThomas Huth /* dlmzb */ 6359fcf5ef2aSThomas Huth static void gen_dlmzb(DisasContext *ctx) 6360fcf5ef2aSThomas Huth { 6361fcf5ef2aSThomas Huth TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); 6362fcf5ef2aSThomas Huth gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, 6363fcf5ef2aSThomas Huth cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); 6364fcf5ef2aSThomas Huth tcg_temp_free_i32(t0); 6365fcf5ef2aSThomas Huth } 6366fcf5ef2aSThomas Huth 6367fcf5ef2aSThomas Huth /* mbar replaces eieio on 440 */ 6368fcf5ef2aSThomas Huth static void gen_mbar(DisasContext *ctx) 6369fcf5ef2aSThomas Huth { 6370fcf5ef2aSThomas Huth /* interpreted as no-op */ 6371fcf5ef2aSThomas Huth } 6372fcf5ef2aSThomas Huth 6373fcf5ef2aSThomas Huth /* msync replaces sync on 440 */ 6374fcf5ef2aSThomas Huth static void gen_msync_4xx(DisasContext *ctx) 6375fcf5ef2aSThomas Huth { 6376fcf5ef2aSThomas Huth /* interpreted as no-op */ 6377fcf5ef2aSThomas Huth } 6378fcf5ef2aSThomas Huth 6379fcf5ef2aSThomas Huth /* icbt */ 6380fcf5ef2aSThomas Huth static void gen_icbt_440(DisasContext *ctx) 6381fcf5ef2aSThomas Huth { 6382fcf5ef2aSThomas Huth /* interpreted as no-op */ 6383fcf5ef2aSThomas Huth /* XXX: specification say this is treated as a load by the MMU 6384fcf5ef2aSThomas Huth * but does not generate any exception 6385fcf5ef2aSThomas Huth */ 6386fcf5ef2aSThomas Huth } 6387fcf5ef2aSThomas Huth 6388fcf5ef2aSThomas Huth /* Embedded.Processor Control */ 6389fcf5ef2aSThomas Huth 6390fcf5ef2aSThomas Huth static void gen_msgclr(DisasContext *ctx) 6391fcf5ef2aSThomas Huth { 6392fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6393fcf5ef2aSThomas Huth GEN_PRIV; 6394fcf5ef2aSThomas Huth #else 6395ebca5e6dSCédric Le Goater CHK_HV; 63967af1e7b0SCédric Le Goater /* 64-bit server processors compliant with arch 2.x */ 63977af1e7b0SCédric Le Goater if (ctx->insns_flags & PPC_SEGMENT_64B) { 63987af1e7b0SCédric Le Goater gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 63997af1e7b0SCédric Le Goater } else { 6400fcf5ef2aSThomas Huth gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); 64017af1e7b0SCédric Le Goater } 6402fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6403fcf5ef2aSThomas Huth } 6404fcf5ef2aSThomas Huth 6405fcf5ef2aSThomas Huth static void gen_msgsnd(DisasContext *ctx) 6406fcf5ef2aSThomas Huth { 6407fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6408fcf5ef2aSThomas Huth GEN_PRIV; 6409fcf5ef2aSThomas Huth #else 6410ebca5e6dSCédric Le Goater CHK_HV; 64117af1e7b0SCédric Le Goater /* 64-bit server processors compliant with arch 2.x */ 64127af1e7b0SCédric Le Goater if (ctx->insns_flags & PPC_SEGMENT_64B) { 64137af1e7b0SCédric Le Goater gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); 64147af1e7b0SCédric Le Goater } else { 6415fcf5ef2aSThomas Huth gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); 64167af1e7b0SCédric Le Goater } 6417fcf5ef2aSThomas Huth #endif /* defined(CONFIG_USER_ONLY) */ 6418fcf5ef2aSThomas Huth } 6419fcf5ef2aSThomas Huth 64207af1e7b0SCédric Le Goater static void gen_msgsync(DisasContext *ctx) 64217af1e7b0SCédric Le Goater { 64227af1e7b0SCédric Le Goater #if defined(CONFIG_USER_ONLY) 64237af1e7b0SCédric Le Goater GEN_PRIV; 64247af1e7b0SCédric Le Goater #else 64257af1e7b0SCédric Le Goater CHK_HV; 64267af1e7b0SCédric Le Goater #endif /* defined(CONFIG_USER_ONLY) */ 64277af1e7b0SCédric Le Goater /* interpreted as no-op */ 64287af1e7b0SCédric Le Goater } 6429fcf5ef2aSThomas Huth 6430fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6431fcf5ef2aSThomas Huth static void gen_maddld(DisasContext *ctx) 6432fcf5ef2aSThomas Huth { 6433fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6434fcf5ef2aSThomas Huth 6435fcf5ef2aSThomas Huth tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 6436fcf5ef2aSThomas Huth tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); 6437fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6438fcf5ef2aSThomas Huth } 6439fcf5ef2aSThomas Huth 6440fcf5ef2aSThomas Huth /* maddhd maddhdu */ 6441fcf5ef2aSThomas Huth static void gen_maddhd_maddhdu(DisasContext *ctx) 6442fcf5ef2aSThomas Huth { 6443fcf5ef2aSThomas Huth TCGv_i64 lo = tcg_temp_new_i64(); 6444fcf5ef2aSThomas Huth TCGv_i64 hi = tcg_temp_new_i64(); 6445fcf5ef2aSThomas Huth TCGv_i64 t1 = tcg_temp_new_i64(); 6446fcf5ef2aSThomas Huth 6447fcf5ef2aSThomas Huth if (Rc(ctx->opcode)) { 6448fcf5ef2aSThomas Huth tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6449fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6450fcf5ef2aSThomas Huth tcg_gen_movi_i64(t1, 0); 6451fcf5ef2aSThomas Huth } else { 6452fcf5ef2aSThomas Huth tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], 6453fcf5ef2aSThomas Huth cpu_gpr[rB(ctx->opcode)]); 6454fcf5ef2aSThomas Huth tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); 6455fcf5ef2aSThomas Huth } 6456fcf5ef2aSThomas Huth tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, 6457fcf5ef2aSThomas Huth cpu_gpr[rC(ctx->opcode)], t1); 6458fcf5ef2aSThomas Huth tcg_temp_free_i64(lo); 6459fcf5ef2aSThomas Huth tcg_temp_free_i64(hi); 6460fcf5ef2aSThomas Huth tcg_temp_free_i64(t1); 6461fcf5ef2aSThomas Huth } 6462fcf5ef2aSThomas Huth #endif /* defined(TARGET_PPC64) */ 6463fcf5ef2aSThomas Huth 6464fcf5ef2aSThomas Huth static void gen_tbegin(DisasContext *ctx) 6465fcf5ef2aSThomas Huth { 6466fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6467fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6468fcf5ef2aSThomas Huth return; 6469fcf5ef2aSThomas Huth } 6470fcf5ef2aSThomas Huth gen_helper_tbegin(cpu_env); 6471fcf5ef2aSThomas Huth } 6472fcf5ef2aSThomas Huth 6473fcf5ef2aSThomas Huth #define GEN_TM_NOOP(name) \ 6474fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6475fcf5ef2aSThomas Huth { \ 6476fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6477fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6478fcf5ef2aSThomas Huth return; \ 6479fcf5ef2aSThomas Huth } \ 6480fcf5ef2aSThomas Huth /* Because tbegin always fails in QEMU, these user \ 6481fcf5ef2aSThomas Huth * space instructions all have a simple implementation: \ 6482fcf5ef2aSThomas Huth * \ 6483fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6484fcf5ef2aSThomas Huth * = 0b0 || 0b00 || 0b0 \ 6485fcf5ef2aSThomas Huth */ \ 6486fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6487fcf5ef2aSThomas Huth } 6488fcf5ef2aSThomas Huth 6489fcf5ef2aSThomas Huth GEN_TM_NOOP(tend); 6490fcf5ef2aSThomas Huth GEN_TM_NOOP(tabort); 6491fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwc); 6492fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortwci); 6493fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdc); 6494fcf5ef2aSThomas Huth GEN_TM_NOOP(tabortdci); 6495fcf5ef2aSThomas Huth GEN_TM_NOOP(tsr); 6496b8b4576eSSuraj Jitindar Singh static inline void gen_cp_abort(DisasContext *ctx) 6497b8b4576eSSuraj Jitindar Singh { 6498b8b4576eSSuraj Jitindar Singh // Do Nothing 6499b8b4576eSSuraj Jitindar Singh } 6500fcf5ef2aSThomas Huth 650180b8c1eeSNikunj A Dadhania #define GEN_CP_PASTE_NOOP(name) \ 650280b8c1eeSNikunj A Dadhania static inline void gen_##name(DisasContext *ctx) \ 650380b8c1eeSNikunj A Dadhania { \ 650480b8c1eeSNikunj A Dadhania /* Generate invalid exception until \ 650580b8c1eeSNikunj A Dadhania * we have an implementation of the copy \ 650680b8c1eeSNikunj A Dadhania * paste facility \ 650780b8c1eeSNikunj A Dadhania */ \ 650880b8c1eeSNikunj A Dadhania gen_invalid(ctx); \ 650980b8c1eeSNikunj A Dadhania } 651080b8c1eeSNikunj A Dadhania 651180b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(copy) 651280b8c1eeSNikunj A Dadhania GEN_CP_PASTE_NOOP(paste) 651380b8c1eeSNikunj A Dadhania 6514fcf5ef2aSThomas Huth static void gen_tcheck(DisasContext *ctx) 6515fcf5ef2aSThomas Huth { 6516fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { 6517fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); 6518fcf5ef2aSThomas Huth return; 6519fcf5ef2aSThomas Huth } 6520fcf5ef2aSThomas Huth /* Because tbegin always fails, the tcheck implementation 6521fcf5ef2aSThomas Huth * is simple: 6522fcf5ef2aSThomas Huth * 6523fcf5ef2aSThomas Huth * CR[CRF] = TDOOMED || MSR[TS] || 0b0 6524fcf5ef2aSThomas Huth * = 0b1 || 0b00 || 0b0 6525fcf5ef2aSThomas Huth */ 6526fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); 6527fcf5ef2aSThomas Huth } 6528fcf5ef2aSThomas Huth 6529fcf5ef2aSThomas Huth #if defined(CONFIG_USER_ONLY) 6530fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6531fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6532fcf5ef2aSThomas Huth { \ 6533fcf5ef2aSThomas Huth gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ 6534fcf5ef2aSThomas Huth } 6535fcf5ef2aSThomas Huth 6536fcf5ef2aSThomas Huth #else 6537fcf5ef2aSThomas Huth 6538fcf5ef2aSThomas Huth #define GEN_TM_PRIV_NOOP(name) \ 6539fcf5ef2aSThomas Huth static inline void gen_##name(DisasContext *ctx) \ 6540fcf5ef2aSThomas Huth { \ 6541fcf5ef2aSThomas Huth CHK_SV; \ 6542fcf5ef2aSThomas Huth if (unlikely(!ctx->tm_enabled)) { \ 6543fcf5ef2aSThomas Huth gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ 6544fcf5ef2aSThomas Huth return; \ 6545fcf5ef2aSThomas Huth } \ 6546fcf5ef2aSThomas Huth /* Because tbegin always fails, the implementation is \ 6547fcf5ef2aSThomas Huth * simple: \ 6548fcf5ef2aSThomas Huth * \ 6549fcf5ef2aSThomas Huth * CR[0] = 0b0 || MSR[TS] || 0b0 \ 6550fcf5ef2aSThomas Huth * = 0b0 || 0b00 | 0b0 \ 6551fcf5ef2aSThomas Huth */ \ 6552fcf5ef2aSThomas Huth tcg_gen_movi_i32(cpu_crf[0], 0); \ 6553fcf5ef2aSThomas Huth } 6554fcf5ef2aSThomas Huth 6555fcf5ef2aSThomas Huth #endif 6556fcf5ef2aSThomas Huth 6557fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(treclaim); 6558fcf5ef2aSThomas Huth GEN_TM_PRIV_NOOP(trechkpt); 6559fcf5ef2aSThomas Huth 6560fcf5ef2aSThomas Huth #include "translate/fp-impl.inc.c" 6561fcf5ef2aSThomas Huth 6562fcf5ef2aSThomas Huth #include "translate/vmx-impl.inc.c" 6563fcf5ef2aSThomas Huth 6564fcf5ef2aSThomas Huth #include "translate/vsx-impl.inc.c" 6565fcf5ef2aSThomas Huth 6566fcf5ef2aSThomas Huth #include "translate/dfp-impl.inc.c" 6567fcf5ef2aSThomas Huth 6568fcf5ef2aSThomas Huth #include "translate/spe-impl.inc.c" 6569fcf5ef2aSThomas Huth 65705cb091a4SNikunj A Dadhania /* Handles lfdp, lxsd, lxssp */ 65715cb091a4SNikunj A Dadhania static void gen_dform39(DisasContext *ctx) 65725cb091a4SNikunj A Dadhania { 65735cb091a4SNikunj A Dadhania switch (ctx->opcode & 0x3) { 65745cb091a4SNikunj A Dadhania case 0: /* lfdp */ 65755cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 65765cb091a4SNikunj A Dadhania return gen_lfdp(ctx); 65775cb091a4SNikunj A Dadhania } 65785cb091a4SNikunj A Dadhania break; 65795cb091a4SNikunj A Dadhania case 2: /* lxsd */ 65805cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 65815cb091a4SNikunj A Dadhania return gen_lxsd(ctx); 65825cb091a4SNikunj A Dadhania } 65835cb091a4SNikunj A Dadhania break; 65845cb091a4SNikunj A Dadhania case 3: /* lxssp */ 65855cb091a4SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 65865cb091a4SNikunj A Dadhania return gen_lxssp(ctx); 65875cb091a4SNikunj A Dadhania } 65885cb091a4SNikunj A Dadhania break; 65895cb091a4SNikunj A Dadhania } 65905cb091a4SNikunj A Dadhania return gen_invalid(ctx); 65915cb091a4SNikunj A Dadhania } 65925cb091a4SNikunj A Dadhania 6593d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp lxvx */ 6594e3001664SNikunj A Dadhania static void gen_dform3D(DisasContext *ctx) 6595e3001664SNikunj A Dadhania { 6596e3001664SNikunj A Dadhania if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ 6597e3001664SNikunj A Dadhania switch (ctx->opcode & 0x7) { 6598e3001664SNikunj A Dadhania case 1: /* lxv */ 6599d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6600d59ba583SNikunj A Dadhania return gen_lxv(ctx); 6601d59ba583SNikunj A Dadhania } 6602e3001664SNikunj A Dadhania break; 6603e3001664SNikunj A Dadhania case 5: /* stxv */ 6604d59ba583SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6605d59ba583SNikunj A Dadhania return gen_stxv(ctx); 6606d59ba583SNikunj A Dadhania } 6607e3001664SNikunj A Dadhania break; 6608e3001664SNikunj A Dadhania } 6609e3001664SNikunj A Dadhania } else { /* DS-FORM */ 6610e3001664SNikunj A Dadhania switch (ctx->opcode & 0x3) { 6611e3001664SNikunj A Dadhania case 0: /* stfdp */ 6612e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA205) { 6613e3001664SNikunj A Dadhania return gen_stfdp(ctx); 6614e3001664SNikunj A Dadhania } 6615e3001664SNikunj A Dadhania break; 6616e3001664SNikunj A Dadhania case 2: /* stxsd */ 6617e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6618e3001664SNikunj A Dadhania return gen_stxsd(ctx); 6619e3001664SNikunj A Dadhania } 6620e3001664SNikunj A Dadhania break; 6621e3001664SNikunj A Dadhania case 3: /* stxssp */ 6622e3001664SNikunj A Dadhania if (ctx->insns_flags2 & PPC2_ISA300) { 6623e3001664SNikunj A Dadhania return gen_stxssp(ctx); 6624e3001664SNikunj A Dadhania } 6625e3001664SNikunj A Dadhania break; 6626e3001664SNikunj A Dadhania } 6627e3001664SNikunj A Dadhania } 6628e3001664SNikunj A Dadhania return gen_invalid(ctx); 6629e3001664SNikunj A Dadhania } 6630e3001664SNikunj A Dadhania 6631fcf5ef2aSThomas Huth static opcode_t opcodes[] = { 6632fcf5ef2aSThomas Huth GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), 6633fcf5ef2aSThomas Huth GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), 6634fcf5ef2aSThomas Huth GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6635fcf5ef2aSThomas Huth GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), 6636fcf5ef2aSThomas Huth GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), 6637fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6638fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), 6639fcf5ef2aSThomas Huth #endif 6640fcf5ef2aSThomas Huth GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), 6641fcf5ef2aSThomas Huth GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), 6642fcf5ef2aSThomas Huth GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), 6643fcf5ef2aSThomas Huth GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6644fcf5ef2aSThomas Huth GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6645fcf5ef2aSThomas Huth GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6646fcf5ef2aSThomas Huth GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6647fcf5ef2aSThomas Huth GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6648fcf5ef2aSThomas Huth GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), 6649fcf5ef2aSThomas Huth GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), 6650fcf5ef2aSThomas Huth GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), 6651fcf5ef2aSThomas Huth GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), 6652fcf5ef2aSThomas Huth GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6653fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6654fcf5ef2aSThomas Huth GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), 6655fcf5ef2aSThomas Huth #endif 6656fcf5ef2aSThomas Huth GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), 6657fcf5ef2aSThomas Huth GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), 6658fcf5ef2aSThomas Huth GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6659fcf5ef2aSThomas Huth GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6660fcf5ef2aSThomas Huth GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6661fcf5ef2aSThomas Huth GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), 6662fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), 666380b8c1eeSNikunj A Dadhania GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), 6664b8b4576eSSuraj Jitindar Singh GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 666580b8c1eeSNikunj A Dadhania GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), 6666fcf5ef2aSThomas Huth GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), 6667fcf5ef2aSThomas Huth GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), 6668fcf5ef2aSThomas Huth GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6669fcf5ef2aSThomas Huth GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6670fcf5ef2aSThomas Huth GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6671fcf5ef2aSThomas Huth GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6672fcf5ef2aSThomas Huth GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), 6673fcf5ef2aSThomas Huth GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), 6674fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), 6675fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6676fcf5ef2aSThomas Huth GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), 6677fcf5ef2aSThomas Huth GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), 6678fcf5ef2aSThomas Huth GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), 6679fcf5ef2aSThomas Huth GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), 6680fcf5ef2aSThomas Huth GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), 6681fcf5ef2aSThomas Huth GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), 6682fcf5ef2aSThomas Huth #endif 6683fcf5ef2aSThomas Huth GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6684fcf5ef2aSThomas Huth GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6685fcf5ef2aSThomas Huth GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6686fcf5ef2aSThomas Huth GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), 6687fcf5ef2aSThomas Huth GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), 6688fcf5ef2aSThomas Huth GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), 6689fcf5ef2aSThomas Huth GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), 6690fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6691fcf5ef2aSThomas Huth GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), 6692fcf5ef2aSThomas Huth GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), 6693fcf5ef2aSThomas Huth GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), 6694fcf5ef2aSThomas Huth GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), 6695fcf5ef2aSThomas Huth GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), 6696fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, 6697fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6698fcf5ef2aSThomas Huth GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, 6699fcf5ef2aSThomas Huth PPC_NONE, PPC2_ISA300), 6700fcf5ef2aSThomas Huth #endif 6701fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6702fcf5ef2aSThomas Huth GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), 6703fcf5ef2aSThomas Huth GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), 6704fcf5ef2aSThomas Huth GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), 6705fcf5ef2aSThomas Huth #endif 67065cb091a4SNikunj A Dadhania /* handles lfdp, lxsd, lxssp */ 67075cb091a4SNikunj A Dadhania GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6708d59ba583SNikunj A Dadhania /* handles stfdp, lxv, stxsd, stxssp, stxv */ 6709e3001664SNikunj A Dadhania GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), 6710fcf5ef2aSThomas Huth GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6711fcf5ef2aSThomas Huth GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), 6712fcf5ef2aSThomas Huth GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), 6713fcf5ef2aSThomas Huth GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), 6714fcf5ef2aSThomas Huth GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), 6715fcf5ef2aSThomas Huth GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), 6716c8fd8373SCédric Le Goater GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), 6717fcf5ef2aSThomas Huth GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), 6718fcf5ef2aSThomas Huth GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6719fcf5ef2aSThomas Huth GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6720fcf5ef2aSThomas Huth GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), 6721a68a6146SBalamuruhan S GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), 6722a3401188SBalamuruhan S GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), 6723fcf5ef2aSThomas Huth GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6724fcf5ef2aSThomas Huth GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), 6725fcf5ef2aSThomas Huth GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), 6726fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6727a68a6146SBalamuruhan S GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), 6728a3401188SBalamuruhan S GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), 6729fcf5ef2aSThomas Huth GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), 6730fcf5ef2aSThomas Huth GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), 6731fcf5ef2aSThomas Huth GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), 6732fcf5ef2aSThomas Huth GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), 6733fcf5ef2aSThomas Huth #endif 6734fcf5ef2aSThomas Huth GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), 6735fcf5ef2aSThomas Huth GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), 6736c09cec68SNikunj A Dadhania GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), 6737fcf5ef2aSThomas Huth GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6738fcf5ef2aSThomas Huth GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6739fcf5ef2aSThomas Huth GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), 6740fcf5ef2aSThomas Huth GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), 6741fcf5ef2aSThomas Huth GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), 6742fcf5ef2aSThomas Huth GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), 6743fcf5ef2aSThomas Huth GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), 6744fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6745fcf5ef2aSThomas Huth GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), 6746cdee0e72SNikunj A Dadhania GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6747fcf5ef2aSThomas Huth GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6748fcf5ef2aSThomas Huth GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6749fcf5ef2aSThomas Huth GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6750fcf5ef2aSThomas Huth GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), 6751fcf5ef2aSThomas Huth GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), 6752fcf5ef2aSThomas Huth #endif 6753fcf5ef2aSThomas Huth GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), 6754fcf5ef2aSThomas Huth GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), 6755fcf5ef2aSThomas Huth GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), 6756fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6757fcf5ef2aSThomas Huth GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), 6758fcf5ef2aSThomas Huth GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), 6759fcf5ef2aSThomas Huth #endif 6760fcf5ef2aSThomas Huth GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), 6761fcf5ef2aSThomas Huth GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), 6762fcf5ef2aSThomas Huth GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), 6763fcf5ef2aSThomas Huth GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), 6764fcf5ef2aSThomas Huth GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), 6765fcf5ef2aSThomas Huth GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), 6766fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6767fcf5ef2aSThomas Huth GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), 6768fcf5ef2aSThomas Huth GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), 6769b63d0434SNikunj A Dadhania GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), 6770fcf5ef2aSThomas Huth #endif 6771fcf5ef2aSThomas Huth GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), 6772fcf5ef2aSThomas Huth GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), 6773fcf5ef2aSThomas Huth GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), 6774fcf5ef2aSThomas Huth GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), 6775fcf5ef2aSThomas Huth GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), 6776fcf5ef2aSThomas Huth GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), 6777fcf5ef2aSThomas Huth GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), 6778fcf5ef2aSThomas Huth GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), 6779fcf5ef2aSThomas Huth GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), 6780fcf5ef2aSThomas Huth GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), 678199d45f8fSBALATON Zoltan GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), 6782fcf5ef2aSThomas Huth GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), 6783fcf5ef2aSThomas Huth GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), 6784fcf5ef2aSThomas Huth GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), 6785fcf5ef2aSThomas Huth GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), 6786fcf5ef2aSThomas Huth GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), 6787fcf5ef2aSThomas Huth GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), 6788fcf5ef2aSThomas Huth GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), 6789fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6790fcf5ef2aSThomas Huth GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), 6791fcf5ef2aSThomas Huth GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, 6792fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6793fcf5ef2aSThomas Huth GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), 6794fcf5ef2aSThomas Huth GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, 6795fcf5ef2aSThomas Huth PPC_SEGMENT_64B), 6796fcf5ef2aSThomas Huth GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), 6797fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), 6798fcf5ef2aSThomas Huth GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), 6799fcf5ef2aSThomas Huth GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), 6800fcf5ef2aSThomas Huth #endif 6801fcf5ef2aSThomas Huth GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), 6802fcf5ef2aSThomas Huth /* XXX Those instructions will need to be handled differently for 6803fcf5ef2aSThomas Huth * different ISA versions */ 6804fcf5ef2aSThomas Huth GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), 6805fcf5ef2aSThomas Huth GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), 6806c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), 6807c8830502SSuraj Jitindar Singh GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), 6808fcf5ef2aSThomas Huth GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), 6809fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6810fcf5ef2aSThomas Huth GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), 6811fcf5ef2aSThomas Huth GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), 6812a63f1dfcSNikunj A Dadhania GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), 681362d897caSNikunj A Dadhania GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), 6814fcf5ef2aSThomas Huth #endif 6815fcf5ef2aSThomas Huth GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), 6816fcf5ef2aSThomas Huth GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), 6817fcf5ef2aSThomas Huth GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), 6818fcf5ef2aSThomas Huth GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), 6819fcf5ef2aSThomas Huth GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), 6820fcf5ef2aSThomas Huth GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), 6821fcf5ef2aSThomas Huth GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), 6822fcf5ef2aSThomas Huth GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), 6823fcf5ef2aSThomas Huth GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), 6824fcf5ef2aSThomas Huth GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), 6825fcf5ef2aSThomas Huth GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), 6826fcf5ef2aSThomas Huth GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6827fcf5ef2aSThomas Huth GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), 6828fcf5ef2aSThomas Huth GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), 6829fcf5ef2aSThomas Huth GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), 6830fcf5ef2aSThomas Huth GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), 6831fcf5ef2aSThomas Huth GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), 6832fcf5ef2aSThomas Huth GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), 6833fcf5ef2aSThomas Huth GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), 6834fcf5ef2aSThomas Huth GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), 6835fcf5ef2aSThomas Huth GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), 6836fcf5ef2aSThomas Huth GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), 6837fcf5ef2aSThomas Huth GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), 6838fcf5ef2aSThomas Huth GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), 6839fcf5ef2aSThomas Huth GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), 6840fcf5ef2aSThomas Huth GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), 6841fcf5ef2aSThomas Huth GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), 6842fcf5ef2aSThomas Huth GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), 6843fcf5ef2aSThomas Huth GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), 6844fcf5ef2aSThomas Huth GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), 6845fcf5ef2aSThomas Huth GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), 6846fcf5ef2aSThomas Huth GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), 6847fcf5ef2aSThomas Huth GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), 6848fcf5ef2aSThomas Huth GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), 6849fcf5ef2aSThomas Huth GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), 6850fcf5ef2aSThomas Huth GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), 6851fcf5ef2aSThomas Huth GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), 6852fcf5ef2aSThomas Huth GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), 6853fcf5ef2aSThomas Huth GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), 6854fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), 6855fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), 6856fcf5ef2aSThomas Huth GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), 6857fcf5ef2aSThomas Huth GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), 6858fcf5ef2aSThomas Huth GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), 6859fcf5ef2aSThomas Huth GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), 6860fcf5ef2aSThomas Huth GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), 6861fcf5ef2aSThomas Huth GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), 6862fcf5ef2aSThomas Huth GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), 6863fcf5ef2aSThomas Huth GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), 6864fcf5ef2aSThomas Huth GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6865fcf5ef2aSThomas Huth GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6866fcf5ef2aSThomas Huth GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), 6867fcf5ef2aSThomas Huth GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), 6868fcf5ef2aSThomas Huth GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6869fcf5ef2aSThomas Huth GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), 6870fcf5ef2aSThomas Huth GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), 6871fcf5ef2aSThomas Huth GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), 6872fcf5ef2aSThomas Huth GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), 6873fcf5ef2aSThomas Huth GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), 6874fcf5ef2aSThomas Huth GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), 6875fcf5ef2aSThomas Huth GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), 6876fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), 6877fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), 6878fcf5ef2aSThomas Huth GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), 6879fcf5ef2aSThomas Huth GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), 6880fcf5ef2aSThomas Huth GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), 6881fcf5ef2aSThomas Huth GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), 6882fcf5ef2aSThomas Huth GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), 6883fcf5ef2aSThomas Huth GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), 6884fcf5ef2aSThomas Huth GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), 6885fcf5ef2aSThomas Huth GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), 6886fcf5ef2aSThomas Huth GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), 6887fcf5ef2aSThomas Huth GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), 6888fcf5ef2aSThomas Huth GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), 6889fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), 6890fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), 6891fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), 6892fcf5ef2aSThomas Huth GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), 6893fcf5ef2aSThomas Huth GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), 6894fcf5ef2aSThomas Huth GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), 6895fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, 6896fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6897fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, 6898fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6899fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, 6900fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6901fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, 6902fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6903fcf5ef2aSThomas Huth GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, 6904fcf5ef2aSThomas Huth PPC_NONE, PPC2_BOOKE206), 6905fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, 6906fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 6907fcf5ef2aSThomas Huth GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, 6908fcf5ef2aSThomas Huth PPC_NONE, PPC2_PRCNTL), 69097af1e7b0SCédric Le Goater GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000, 69107af1e7b0SCédric Le Goater PPC_NONE, PPC2_PRCNTL), 6911fcf5ef2aSThomas Huth GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), 6912fcf5ef2aSThomas Huth GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), 6913fcf5ef2aSThomas Huth GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), 6914fcf5ef2aSThomas Huth GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, 6915fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 6916fcf5ef2aSThomas Huth GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), 6917fcf5ef2aSThomas Huth GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, 6918fcf5ef2aSThomas Huth PPC_BOOKE, PPC2_BOOKE206), 69190c8d8c8bSBALATON Zoltan GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, 69200c8d8c8bSBALATON Zoltan PPC_440_SPEC), 6921fcf5ef2aSThomas Huth GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), 6922fcf5ef2aSThomas Huth GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), 6923fcf5ef2aSThomas Huth GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), 6924fcf5ef2aSThomas Huth GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), 6925fcf5ef2aSThomas Huth GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), 6926fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6927fcf5ef2aSThomas Huth GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, 6928fcf5ef2aSThomas Huth PPC2_ISA300), 6929fcf5ef2aSThomas Huth GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), 6930fcf5ef2aSThomas Huth #endif 6931fcf5ef2aSThomas Huth 6932fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD 6933fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_ADD_CONST 6934fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ 6935fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), 6936fcf5ef2aSThomas Huth #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ 6937fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6938fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), 6939fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) 6940fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) 6941fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) 6942fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) 6943fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) 6944fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) 6945fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) 6946fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) 6947fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) 6948fcf5ef2aSThomas Huth GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) 6949fcf5ef2aSThomas Huth 6950fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVW 6951fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ 6952fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) 6953fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), 6954fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), 6955fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), 6956fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), 6957fcf5ef2aSThomas Huth GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6958fcf5ef2aSThomas Huth GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6959fcf5ef2aSThomas Huth GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6960fcf5ef2aSThomas Huth GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6961fcf5ef2aSThomas Huth GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6962fcf5ef2aSThomas Huth GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6963fcf5ef2aSThomas Huth 6964fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 6965fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_DIVD 6966fcf5ef2aSThomas Huth #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ 6967fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6968fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), 6969fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), 6970fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), 6971fcf5ef2aSThomas Huth GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), 6972fcf5ef2aSThomas Huth 6973fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6974fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), 6975fcf5ef2aSThomas Huth GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6976fcf5ef2aSThomas Huth GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), 6977fcf5ef2aSThomas Huth GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), 6978fcf5ef2aSThomas Huth GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), 6979fcf5ef2aSThomas Huth 6980fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_MUL_HELPER 6981fcf5ef2aSThomas Huth #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ 6982fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) 6983fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), 6984fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), 6985fcf5ef2aSThomas Huth GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), 6986fcf5ef2aSThomas Huth #endif 6987fcf5ef2aSThomas Huth 6988fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF 6989fcf5ef2aSThomas Huth #undef GEN_INT_ARITH_SUBF_CONST 6990fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ 6991fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), 6992fcf5ef2aSThomas Huth #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ 6993fcf5ef2aSThomas Huth add_ca, compute_ca, compute_ov) \ 6994fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), 6995fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) 6996fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) 6997fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) 6998fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) 6999fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) 7000fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) 7001fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) 7002fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) 7003fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) 7004fcf5ef2aSThomas Huth GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) 7005fcf5ef2aSThomas Huth 7006fcf5ef2aSThomas Huth #undef GEN_LOGICAL1 7007fcf5ef2aSThomas Huth #undef GEN_LOGICAL2 7008fcf5ef2aSThomas Huth #define GEN_LOGICAL2(name, tcg_op, opc, type) \ 7009fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) 7010fcf5ef2aSThomas Huth #define GEN_LOGICAL1(name, tcg_op, opc, type) \ 7011fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) 7012fcf5ef2aSThomas Huth GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), 7013fcf5ef2aSThomas Huth GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), 7014fcf5ef2aSThomas Huth GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), 7015fcf5ef2aSThomas Huth GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), 7016fcf5ef2aSThomas Huth GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), 7017fcf5ef2aSThomas Huth GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), 7018fcf5ef2aSThomas Huth GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), 7019fcf5ef2aSThomas Huth GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), 7020fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7021fcf5ef2aSThomas Huth GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), 7022fcf5ef2aSThomas Huth #endif 7023fcf5ef2aSThomas Huth 7024fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7025fcf5ef2aSThomas Huth #undef GEN_PPC64_R2 7026fcf5ef2aSThomas Huth #undef GEN_PPC64_R4 7027fcf5ef2aSThomas Huth #define GEN_PPC64_R2(name, opc1, opc2) \ 7028fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7029fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7030fcf5ef2aSThomas Huth PPC_64B) 7031fcf5ef2aSThomas Huth #define GEN_PPC64_R4(name, opc1, opc2) \ 7032fcf5ef2aSThomas Huth GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ 7033fcf5ef2aSThomas Huth GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ 7034fcf5ef2aSThomas Huth PPC_64B), \ 7035fcf5ef2aSThomas Huth GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ 7036fcf5ef2aSThomas Huth PPC_64B), \ 7037fcf5ef2aSThomas Huth GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ 7038fcf5ef2aSThomas Huth PPC_64B) 7039fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicl, 0x1E, 0x00), 7040fcf5ef2aSThomas Huth GEN_PPC64_R4(rldicr, 0x1E, 0x02), 7041fcf5ef2aSThomas Huth GEN_PPC64_R4(rldic, 0x1E, 0x04), 7042fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcl, 0x1E, 0x08), 7043fcf5ef2aSThomas Huth GEN_PPC64_R2(rldcr, 0x1E, 0x09), 7044fcf5ef2aSThomas Huth GEN_PPC64_R4(rldimi, 0x1E, 0x06), 7045fcf5ef2aSThomas Huth #endif 7046fcf5ef2aSThomas Huth 7047fcf5ef2aSThomas Huth #undef GEN_LD 7048fcf5ef2aSThomas Huth #undef GEN_LDU 7049fcf5ef2aSThomas Huth #undef GEN_LDUX 7050fcf5ef2aSThomas Huth #undef GEN_LDX_E 7051fcf5ef2aSThomas Huth #undef GEN_LDS 7052fcf5ef2aSThomas Huth #define GEN_LD(name, ldop, opc, type) \ 7053fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7054fcf5ef2aSThomas Huth #define GEN_LDU(name, ldop, opc, type) \ 7055fcf5ef2aSThomas Huth GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), 7056fcf5ef2aSThomas Huth #define GEN_LDUX(name, ldop, opc2, opc3, type) \ 7057fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7058fcf5ef2aSThomas Huth #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ 7059fcf5ef2aSThomas Huth GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), 7060fcf5ef2aSThomas Huth #define GEN_LDS(name, ldop, op, type) \ 7061fcf5ef2aSThomas Huth GEN_LD(name, ldop, op | 0x20, type) \ 7062fcf5ef2aSThomas Huth GEN_LDU(name, ldop, op | 0x21, type) \ 7063fcf5ef2aSThomas Huth GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ 7064fcf5ef2aSThomas Huth GEN_LDX(name, ldop, 0x17, op | 0x00, type) 7065fcf5ef2aSThomas Huth 7066fcf5ef2aSThomas Huth GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) 7067fcf5ef2aSThomas Huth GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) 7068fcf5ef2aSThomas Huth GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) 7069fcf5ef2aSThomas Huth GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) 7070fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7071fcf5ef2aSThomas Huth GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) 7072fcf5ef2aSThomas Huth GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) 7073fcf5ef2aSThomas Huth GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) 7074fcf5ef2aSThomas Huth GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) 7075fcf5ef2aSThomas Huth GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) 7076fcf5ef2aSThomas Huth 7077fcf5ef2aSThomas Huth /* HV/P7 and later only */ 7078fcf5ef2aSThomas Huth GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) 7079fcf5ef2aSThomas Huth GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) 7080fcf5ef2aSThomas Huth GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) 7081fcf5ef2aSThomas Huth GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) 7082fcf5ef2aSThomas Huth #endif 7083fcf5ef2aSThomas Huth GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) 7084fcf5ef2aSThomas Huth GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) 7085fcf5ef2aSThomas Huth 7086fcf5ef2aSThomas Huth #undef GEN_ST 7087fcf5ef2aSThomas Huth #undef GEN_STU 7088fcf5ef2aSThomas Huth #undef GEN_STUX 7089fcf5ef2aSThomas Huth #undef GEN_STX_E 7090fcf5ef2aSThomas Huth #undef GEN_STS 7091fcf5ef2aSThomas Huth #define GEN_ST(name, stop, opc, type) \ 7092fcf5ef2aSThomas Huth GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), 7093fcf5ef2aSThomas Huth #define GEN_STU(name, stop, opc, type) \ 7094fcf5ef2aSThomas Huth GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), 7095fcf5ef2aSThomas Huth #define GEN_STUX(name, stop, opc2, opc3, type) \ 7096fcf5ef2aSThomas Huth GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), 7097fcf5ef2aSThomas Huth #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ 70980123d3cbSBALATON Zoltan GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), 7099fcf5ef2aSThomas Huth #define GEN_STS(name, stop, op, type) \ 7100fcf5ef2aSThomas Huth GEN_ST(name, stop, op | 0x20, type) \ 7101fcf5ef2aSThomas Huth GEN_STU(name, stop, op | 0x21, type) \ 7102fcf5ef2aSThomas Huth GEN_STUX(name, stop, 0x17, op | 0x01, type) \ 7103fcf5ef2aSThomas Huth GEN_STX(name, stop, 0x17, op | 0x00, type) 7104fcf5ef2aSThomas Huth 7105fcf5ef2aSThomas Huth GEN_STS(stb, st8, 0x06, PPC_INTEGER) 7106fcf5ef2aSThomas Huth GEN_STS(sth, st16, 0x0C, PPC_INTEGER) 7107fcf5ef2aSThomas Huth GEN_STS(stw, st32, 0x04, PPC_INTEGER) 7108fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7109fcf5ef2aSThomas Huth GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) 7110fcf5ef2aSThomas Huth GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) 7111fcf5ef2aSThomas Huth GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) 7112fcf5ef2aSThomas Huth GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) 7113fcf5ef2aSThomas Huth GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) 7114fcf5ef2aSThomas Huth GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) 7115fcf5ef2aSThomas Huth GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) 7116fcf5ef2aSThomas Huth #endif 7117fcf5ef2aSThomas Huth GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) 7118fcf5ef2aSThomas Huth GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) 7119fcf5ef2aSThomas Huth 7120fcf5ef2aSThomas Huth #undef GEN_CRLOGIC 7121fcf5ef2aSThomas Huth #define GEN_CRLOGIC(name, tcg_op, opc) \ 7122fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) 7123fcf5ef2aSThomas Huth GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), 7124fcf5ef2aSThomas Huth GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), 7125fcf5ef2aSThomas Huth GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), 7126fcf5ef2aSThomas Huth GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), 7127fcf5ef2aSThomas Huth GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), 7128fcf5ef2aSThomas Huth GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), 7129fcf5ef2aSThomas Huth GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), 7130fcf5ef2aSThomas Huth GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), 7131fcf5ef2aSThomas Huth 7132fcf5ef2aSThomas Huth #undef GEN_MAC_HANDLER 7133fcf5ef2aSThomas Huth #define GEN_MAC_HANDLER(name, opc2, opc3) \ 7134fcf5ef2aSThomas Huth GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) 7135fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchw, 0x0C, 0x05), 7136fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), 7137fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchws, 0x0C, 0x07), 7138fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), 7139fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), 7140fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), 7141fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), 7142fcf5ef2aSThomas Huth GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), 7143fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhw, 0x0C, 0x01), 7144fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), 7145fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhws, 0x0C, 0x03), 7146fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), 7147fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), 7148fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), 7149fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), 7150fcf5ef2aSThomas Huth GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), 7151fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), 7152fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), 7153fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), 7154fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), 7155fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), 7156fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), 7157fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), 7158fcf5ef2aSThomas Huth GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), 7159fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), 7160fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), 7161fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), 7162fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), 7163fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), 7164fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), 7165fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), 7166fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), 7167fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), 7168fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), 7169fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), 7170fcf5ef2aSThomas Huth GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), 7171fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchw, 0x08, 0x05), 7172fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), 7173fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), 7174fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), 7175fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), 7176fcf5ef2aSThomas Huth GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), 7177fcf5ef2aSThomas Huth 7178fcf5ef2aSThomas Huth GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ 7179fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7180fcf5ef2aSThomas Huth GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ 7181fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7182fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ 7183fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7184fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ 7185fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7186fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ 7187fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7188fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ 7189fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7190fcf5ef2aSThomas Huth GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ 7191fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7192fcf5ef2aSThomas Huth GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ 7193fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7194fcf5ef2aSThomas Huth GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ 7195fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7196fcf5ef2aSThomas Huth GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ 7197fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7198fcf5ef2aSThomas Huth GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ 7199fcf5ef2aSThomas Huth PPC_NONE, PPC2_TM), 7200fcf5ef2aSThomas Huth 7201fcf5ef2aSThomas Huth #include "translate/fp-ops.inc.c" 7202fcf5ef2aSThomas Huth 7203fcf5ef2aSThomas Huth #include "translate/vmx-ops.inc.c" 7204fcf5ef2aSThomas Huth 7205fcf5ef2aSThomas Huth #include "translate/vsx-ops.inc.c" 7206fcf5ef2aSThomas Huth 7207fcf5ef2aSThomas Huth #include "translate/dfp-ops.inc.c" 7208fcf5ef2aSThomas Huth 7209fcf5ef2aSThomas Huth #include "translate/spe-ops.inc.c" 7210fcf5ef2aSThomas Huth }; 7211fcf5ef2aSThomas Huth 7212fcf5ef2aSThomas Huth #include "helper_regs.h" 72135b27a92dSPaolo Bonzini #include "translate_init.inc.c" 7214fcf5ef2aSThomas Huth 7215fcf5ef2aSThomas Huth /*****************************************************************************/ 7216fcf5ef2aSThomas Huth /* Misc PowerPC helpers */ 7217fcf5ef2aSThomas Huth void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 7218fcf5ef2aSThomas Huth int flags) 7219fcf5ef2aSThomas Huth { 7220fcf5ef2aSThomas Huth #define RGPL 4 7221fcf5ef2aSThomas Huth #define RFPL 4 7222fcf5ef2aSThomas Huth 7223fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7224fcf5ef2aSThomas Huth CPUPPCState *env = &cpu->env; 7225fcf5ef2aSThomas Huth int i; 7226fcf5ef2aSThomas Huth 7227fcf5ef2aSThomas Huth cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7228fcf5ef2aSThomas Huth TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7229fcf5ef2aSThomas Huth env->nip, env->lr, env->ctr, cpu_read_xer(env), 7230fcf5ef2aSThomas Huth cs->cpu_index); 7231fcf5ef2aSThomas Huth cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7232fcf5ef2aSThomas Huth TARGET_FMT_lx " iidx %d didx %d\n", 7233fcf5ef2aSThomas Huth env->msr, env->spr[SPR_HID0], 7234fcf5ef2aSThomas Huth env->hflags, env->immu_idx, env->dmmu_idx); 7235fcf5ef2aSThomas Huth #if !defined(NO_TIMER_DUMP) 7236fcf5ef2aSThomas Huth cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7237fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7238fcf5ef2aSThomas Huth " DECR %08" PRIu32 7239fcf5ef2aSThomas Huth #endif 7240fcf5ef2aSThomas Huth "\n", 7241fcf5ef2aSThomas Huth cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7242fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7243fcf5ef2aSThomas Huth , cpu_ppc_load_decr(env) 7244fcf5ef2aSThomas Huth #endif 7245fcf5ef2aSThomas Huth ); 7246fcf5ef2aSThomas Huth #endif 7247fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7248fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == 0) 7249fcf5ef2aSThomas Huth cpu_fprintf(f, "GPR%02d", i); 7250fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7251fcf5ef2aSThomas Huth if ((i & (RGPL - 1)) == (RGPL - 1)) 7252fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7253fcf5ef2aSThomas Huth } 7254fcf5ef2aSThomas Huth cpu_fprintf(f, "CR "); 7255fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) 7256fcf5ef2aSThomas Huth cpu_fprintf(f, "%01x", env->crf[i]); 7257fcf5ef2aSThomas Huth cpu_fprintf(f, " ["); 7258fcf5ef2aSThomas Huth for (i = 0; i < 8; i++) { 7259fcf5ef2aSThomas Huth char a = '-'; 7260fcf5ef2aSThomas Huth if (env->crf[i] & 0x08) 7261fcf5ef2aSThomas Huth a = 'L'; 7262fcf5ef2aSThomas Huth else if (env->crf[i] & 0x04) 7263fcf5ef2aSThomas Huth a = 'G'; 7264fcf5ef2aSThomas Huth else if (env->crf[i] & 0x02) 7265fcf5ef2aSThomas Huth a = 'E'; 7266fcf5ef2aSThomas Huth cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7267fcf5ef2aSThomas Huth } 7268fcf5ef2aSThomas Huth cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7269fcf5ef2aSThomas Huth env->reserve_addr); 7270685f1ce2SRichard Henderson 7271685f1ce2SRichard Henderson if (flags & CPU_DUMP_FPU) { 7272fcf5ef2aSThomas Huth for (i = 0; i < 32; i++) { 7273685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == 0) { 7274fcf5ef2aSThomas Huth cpu_fprintf(f, "FPR%02d", i); 7275685f1ce2SRichard Henderson } 7276fcf5ef2aSThomas Huth cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); 7277685f1ce2SRichard Henderson if ((i & (RFPL - 1)) == (RFPL - 1)) { 7278fcf5ef2aSThomas Huth cpu_fprintf(f, "\n"); 7279fcf5ef2aSThomas Huth } 7280685f1ce2SRichard Henderson } 7281fcf5ef2aSThomas Huth cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7282685f1ce2SRichard Henderson } 7283685f1ce2SRichard Henderson 7284fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7285fcf5ef2aSThomas Huth cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7286fcf5ef2aSThomas Huth " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7287fcf5ef2aSThomas Huth env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7288fcf5ef2aSThomas Huth env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7289fcf5ef2aSThomas Huth 7290fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7291fcf5ef2aSThomas Huth " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7292fcf5ef2aSThomas Huth env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7293fcf5ef2aSThomas Huth env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7294fcf5ef2aSThomas Huth 7295fcf5ef2aSThomas Huth cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7296fcf5ef2aSThomas Huth " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7297fcf5ef2aSThomas Huth env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7298fcf5ef2aSThomas Huth env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7299fcf5ef2aSThomas Huth 7300fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7301fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_POWER7 || 7302fcf5ef2aSThomas Huth env->excp_model == POWERPC_EXCP_POWER8) { 7303fcf5ef2aSThomas Huth cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7304fcf5ef2aSThomas Huth env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7305fcf5ef2aSThomas Huth } 7306fcf5ef2aSThomas Huth #endif 7307fcf5ef2aSThomas Huth if (env->excp_model == POWERPC_EXCP_BOOKE) { 7308fcf5ef2aSThomas Huth cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7309fcf5ef2aSThomas Huth " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7310fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7311fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7312fcf5ef2aSThomas Huth 7313fcf5ef2aSThomas Huth cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7314fcf5ef2aSThomas Huth " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7315fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7316fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7317fcf5ef2aSThomas Huth 7318fcf5ef2aSThomas Huth cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7319fcf5ef2aSThomas Huth " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7320fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7321fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7322fcf5ef2aSThomas Huth 7323fcf5ef2aSThomas Huth cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7324fcf5ef2aSThomas Huth " EPR " TARGET_FMT_lx "\n", 7325fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7326fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_EPR]); 7327fcf5ef2aSThomas Huth 7328fcf5ef2aSThomas Huth /* FSL-specific */ 7329fcf5ef2aSThomas Huth cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7330fcf5ef2aSThomas Huth " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7331fcf5ef2aSThomas Huth env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7332fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7333fcf5ef2aSThomas Huth 7334fcf5ef2aSThomas Huth /* 7335fcf5ef2aSThomas Huth * IVORs are left out as they are large and do not change often -- 7336fcf5ef2aSThomas Huth * they can be read with "p $ivor0", "p $ivor1", etc. 7337fcf5ef2aSThomas Huth */ 7338fcf5ef2aSThomas Huth } 7339fcf5ef2aSThomas Huth 7340fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7341fcf5ef2aSThomas Huth if (env->flags & POWERPC_FLAG_CFAR) { 7342fcf5ef2aSThomas Huth cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7343fcf5ef2aSThomas Huth } 7344fcf5ef2aSThomas Huth #endif 7345fcf5ef2aSThomas Huth 7346d801a61eSSuraj Jitindar Singh if (env->spr_cb[SPR_LPCR].name) 7347d801a61eSSuraj Jitindar Singh cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7348d801a61eSSuraj Jitindar Singh 73490941d728SDavid Gibson switch (env->mmu_model) { 7350fcf5ef2aSThomas Huth case POWERPC_MMU_32B: 7351fcf5ef2aSThomas Huth case POWERPC_MMU_601: 7352fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_6xx: 7353fcf5ef2aSThomas Huth case POWERPC_MMU_SOFT_74xx: 7354fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 73550941d728SDavid Gibson case POWERPC_MMU_64B: 73560941d728SDavid Gibson case POWERPC_MMU_2_03: 73570941d728SDavid Gibson case POWERPC_MMU_2_06: 73580941d728SDavid Gibson case POWERPC_MMU_2_07: 73590941d728SDavid Gibson case POWERPC_MMU_3_00: 7360fcf5ef2aSThomas Huth #endif 73614f4f28ffSSuraj Jitindar Singh if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 73624f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 73634f4f28ffSSuraj Jitindar Singh } 73644a7518e0SCédric Le Goater if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 73654a7518e0SCédric Le Goater cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 73664a7518e0SCédric Le Goater } 73674f4f28ffSSuraj Jitindar Singh cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7368fcf5ef2aSThomas Huth env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7369fcf5ef2aSThomas Huth break; 7370fcf5ef2aSThomas Huth case POWERPC_MMU_BOOKE206: 7371fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7372fcf5ef2aSThomas Huth " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7373fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7374fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7375fcf5ef2aSThomas Huth 7376fcf5ef2aSThomas Huth cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7377fcf5ef2aSThomas Huth " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7378fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7379fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7380fcf5ef2aSThomas Huth 7381fcf5ef2aSThomas Huth cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7382fcf5ef2aSThomas Huth " TLB1CFG " TARGET_FMT_lx "\n", 7383fcf5ef2aSThomas Huth env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7384fcf5ef2aSThomas Huth env->spr[SPR_BOOKE_TLB1CFG]); 7385fcf5ef2aSThomas Huth break; 7386fcf5ef2aSThomas Huth default: 7387fcf5ef2aSThomas Huth break; 7388fcf5ef2aSThomas Huth } 7389fcf5ef2aSThomas Huth #endif 7390fcf5ef2aSThomas Huth 7391fcf5ef2aSThomas Huth #undef RGPL 7392fcf5ef2aSThomas Huth #undef RFPL 7393fcf5ef2aSThomas Huth } 7394fcf5ef2aSThomas Huth 7395fcf5ef2aSThomas Huth void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, 7396fcf5ef2aSThomas Huth fprintf_function cpu_fprintf, int flags) 7397fcf5ef2aSThomas Huth { 7398fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7399fcf5ef2aSThomas Huth PowerPCCPU *cpu = POWERPC_CPU(cs); 7400fcf5ef2aSThomas Huth opc_handler_t **t1, **t2, **t3, *handler; 7401fcf5ef2aSThomas Huth int op1, op2, op3; 7402fcf5ef2aSThomas Huth 7403fcf5ef2aSThomas Huth t1 = cpu->env.opcodes; 7404fcf5ef2aSThomas Huth for (op1 = 0; op1 < 64; op1++) { 7405fcf5ef2aSThomas Huth handler = t1[op1]; 7406fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7407fcf5ef2aSThomas Huth t2 = ind_table(handler); 7408fcf5ef2aSThomas Huth for (op2 = 0; op2 < 32; op2++) { 7409fcf5ef2aSThomas Huth handler = t2[op2]; 7410fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7411fcf5ef2aSThomas Huth t3 = ind_table(handler); 7412fcf5ef2aSThomas Huth for (op3 = 0; op3 < 32; op3++) { 7413fcf5ef2aSThomas Huth handler = t3[op3]; 7414fcf5ef2aSThomas Huth if (handler->count == 0) 7415fcf5ef2aSThomas Huth continue; 7416fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " 7417fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7418fcf5ef2aSThomas Huth op1, op2, op3, op1, (op3 << 5) | op2, 7419fcf5ef2aSThomas Huth handler->oname, 7420fcf5ef2aSThomas Huth handler->count, handler->count); 7421fcf5ef2aSThomas Huth } 7422fcf5ef2aSThomas Huth } else { 7423fcf5ef2aSThomas Huth if (handler->count == 0) 7424fcf5ef2aSThomas Huth continue; 7425fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " 7426fcf5ef2aSThomas Huth "%016" PRIx64 " %" PRId64 "\n", 7427fcf5ef2aSThomas Huth op1, op2, op1, op2, handler->oname, 7428fcf5ef2aSThomas Huth handler->count, handler->count); 7429fcf5ef2aSThomas Huth } 7430fcf5ef2aSThomas Huth } 7431fcf5ef2aSThomas Huth } else { 7432fcf5ef2aSThomas Huth if (handler->count == 0) 7433fcf5ef2aSThomas Huth continue; 7434fcf5ef2aSThomas Huth cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 7435fcf5ef2aSThomas Huth " %" PRId64 "\n", 7436fcf5ef2aSThomas Huth op1, op1, handler->oname, 7437fcf5ef2aSThomas Huth handler->count, handler->count); 7438fcf5ef2aSThomas Huth } 7439fcf5ef2aSThomas Huth } 7440fcf5ef2aSThomas Huth #endif 7441fcf5ef2aSThomas Huth } 7442fcf5ef2aSThomas Huth 7443b542683dSEmilio G. Cota static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 7444fcf5ef2aSThomas Huth { 7445b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 74469c489ea6SLluís Vilanova CPUPPCState *env = cs->env_ptr; 7447b0c2d521SEmilio G. Cota int bound; 7448fcf5ef2aSThomas Huth 7449b0c2d521SEmilio G. Cota ctx->exception = POWERPC_EXCP_NONE; 7450b0c2d521SEmilio G. Cota ctx->spr_cb = env->spr_cb; 7451b0c2d521SEmilio G. Cota ctx->pr = msr_pr; 7452b0c2d521SEmilio G. Cota ctx->mem_idx = env->dmmu_idx; 7453b0c2d521SEmilio G. Cota ctx->dr = msr_dr; 7454fcf5ef2aSThomas Huth #if !defined(CONFIG_USER_ONLY) 7455b0c2d521SEmilio G. Cota ctx->hv = msr_hv || !env->has_hv_mode; 7456fcf5ef2aSThomas Huth #endif 7457b0c2d521SEmilio G. Cota ctx->insns_flags = env->insns_flags; 7458b0c2d521SEmilio G. Cota ctx->insns_flags2 = env->insns_flags2; 7459b0c2d521SEmilio G. Cota ctx->access_type = -1; 7460b0c2d521SEmilio G. Cota ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); 7461b0c2d521SEmilio G. Cota ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); 7462b0c2d521SEmilio G. Cota ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; 7463*0e3bf489SRoman Kapl ctx->flags = env->flags; 7464fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7465b0c2d521SEmilio G. Cota ctx->sf_mode = msr_is_64bit(env, env->msr); 7466b0c2d521SEmilio G. Cota ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); 7467fcf5ef2aSThomas Huth #endif 7468e69ba2b4SDavid Gibson ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B 7469e69ba2b4SDavid Gibson || env->mmu_model == POWERPC_MMU_601 7470e69ba2b4SDavid Gibson || (env->mmu_model & POWERPC_MMU_64B); 7471fcf5ef2aSThomas Huth 7472b0c2d521SEmilio G. Cota ctx->fpu_enabled = !!msr_fp; 7473fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) 7474b0c2d521SEmilio G. Cota ctx->spe_enabled = !!msr_spe; 7475fcf5ef2aSThomas Huth else 7476b0c2d521SEmilio G. Cota ctx->spe_enabled = false; 7477fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) 7478b0c2d521SEmilio G. Cota ctx->altivec_enabled = !!msr_vr; 7479fcf5ef2aSThomas Huth else 7480b0c2d521SEmilio G. Cota ctx->altivec_enabled = false; 7481fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { 7482b0c2d521SEmilio G. Cota ctx->vsx_enabled = !!msr_vsx; 7483fcf5ef2aSThomas Huth } else { 7484b0c2d521SEmilio G. Cota ctx->vsx_enabled = false; 7485fcf5ef2aSThomas Huth } 7486fcf5ef2aSThomas Huth #if defined(TARGET_PPC64) 7487fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { 7488b0c2d521SEmilio G. Cota ctx->tm_enabled = !!msr_tm; 7489fcf5ef2aSThomas Huth } else { 7490b0c2d521SEmilio G. Cota ctx->tm_enabled = false; 7491fcf5ef2aSThomas Huth } 7492fcf5ef2aSThomas Huth #endif 7493b0c2d521SEmilio G. Cota ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); 7494fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_SE) && msr_se) 7495b0c2d521SEmilio G. Cota ctx->singlestep_enabled = CPU_SINGLE_STEP; 7496fcf5ef2aSThomas Huth else 7497b0c2d521SEmilio G. Cota ctx->singlestep_enabled = 0; 7498fcf5ef2aSThomas Huth if ((env->flags & POWERPC_FLAG_BE) && msr_be) 7499b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7500*0e3bf489SRoman Kapl if ((env->flags & POWERPC_FLAG_DE) && msr_de) { 7501*0e3bf489SRoman Kapl ctx->singlestep_enabled = 0; 7502*0e3bf489SRoman Kapl target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 7503*0e3bf489SRoman Kapl if (dbcr0 & DBCR0_ICMP) { 7504*0e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_SINGLE_STEP; 7505*0e3bf489SRoman Kapl } 7506*0e3bf489SRoman Kapl if (dbcr0 & DBCR0_BRT) { 7507*0e3bf489SRoman Kapl ctx->singlestep_enabled |= CPU_BRANCH_STEP; 7508*0e3bf489SRoman Kapl } 7509*0e3bf489SRoman Kapl 7510*0e3bf489SRoman Kapl } 7511b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7512b0c2d521SEmilio G. Cota ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; 7513fcf5ef2aSThomas Huth } 7514fcf5ef2aSThomas Huth #if defined (DO_SINGLE_STEP) && 0 7515fcf5ef2aSThomas Huth /* Single step trace mode */ 7516fcf5ef2aSThomas Huth msr_se = 1; 7517fcf5ef2aSThomas Huth #endif 7518b0c2d521SEmilio G. Cota 7519b0c2d521SEmilio G. Cota bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; 7520b542683dSEmilio G. Cota ctx->base.max_insns = MIN(ctx->base.max_insns, bound); 7521fcf5ef2aSThomas Huth } 7522fcf5ef2aSThomas Huth 7523b0c2d521SEmilio G. Cota static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) 7524b0c2d521SEmilio G. Cota { 7525b0c2d521SEmilio G. Cota } 7526fcf5ef2aSThomas Huth 7527b0c2d521SEmilio G. Cota static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) 7528b0c2d521SEmilio G. Cota { 7529b0c2d521SEmilio G. Cota tcg_gen_insn_start(dcbase->pc_next); 7530b0c2d521SEmilio G. Cota } 7531b0c2d521SEmilio G. Cota 7532b0c2d521SEmilio G. Cota static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, 7533b0c2d521SEmilio G. Cota const CPUBreakpoint *bp) 7534b0c2d521SEmilio G. Cota { 7535b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7536b0c2d521SEmilio G. Cota 7537b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 75382a8ceefcSEmilio G. Cota dcbase->is_jmp = DISAS_NORETURN; 7539fcf5ef2aSThomas Huth /* The address covered by the breakpoint must be included in 7540fcf5ef2aSThomas Huth [tb->pc, tb->pc + tb->size) in order to for it to be 7541fcf5ef2aSThomas Huth properly cleared -- thus we increment the PC here so that 7542fcf5ef2aSThomas Huth the logic setting tb->size below does the right thing. */ 7543b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7544b0c2d521SEmilio G. Cota return true; 7545fcf5ef2aSThomas Huth } 7546fcf5ef2aSThomas Huth 7547b0c2d521SEmilio G. Cota static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) 7548b0c2d521SEmilio G. Cota { 7549b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7550b0c2d521SEmilio G. Cota CPUPPCState *env = cs->env_ptr; 7551b0c2d521SEmilio G. Cota opc_handler_t **table, *handler; 7552b0c2d521SEmilio G. Cota 7553fcf5ef2aSThomas Huth LOG_DISAS("----------------\n"); 7554fcf5ef2aSThomas Huth LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", 7555b0c2d521SEmilio G. Cota ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); 7556b0c2d521SEmilio G. Cota 7557b0c2d521SEmilio G. Cota if (unlikely(need_byteswap(ctx))) { 7558b0c2d521SEmilio G. Cota ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); 7559fcf5ef2aSThomas Huth } else { 7560b0c2d521SEmilio G. Cota ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); 7561fcf5ef2aSThomas Huth } 7562fcf5ef2aSThomas Huth LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", 7563b0c2d521SEmilio G. Cota ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), 7564b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7565b0c2d521SEmilio G. Cota ctx->le_mode ? "little" : "big"); 7566b0c2d521SEmilio G. Cota ctx->base.pc_next += 4; 7567fcf5ef2aSThomas Huth table = env->opcodes; 7568b0c2d521SEmilio G. Cota handler = table[opc1(ctx->opcode)]; 7569fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7570fcf5ef2aSThomas Huth table = ind_table(handler); 7571b0c2d521SEmilio G. Cota handler = table[opc2(ctx->opcode)]; 7572fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7573fcf5ef2aSThomas Huth table = ind_table(handler); 7574b0c2d521SEmilio G. Cota handler = table[opc3(ctx->opcode)]; 7575fcf5ef2aSThomas Huth if (is_indirect_opcode(handler)) { 7576fcf5ef2aSThomas Huth table = ind_table(handler); 7577b0c2d521SEmilio G. Cota handler = table[opc4(ctx->opcode)]; 7578fcf5ef2aSThomas Huth } 7579fcf5ef2aSThomas Huth } 7580fcf5ef2aSThomas Huth } 7581fcf5ef2aSThomas Huth /* Is opcode *REALLY* valid ? */ 7582fcf5ef2aSThomas Huth if (unlikely(handler->handler == &gen_invalid)) { 7583fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " 7584fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7585fcf5ef2aSThomas Huth TARGET_FMT_lx " %d\n", 7586b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7587b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7588b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); 7589fcf5ef2aSThomas Huth } else { 7590fcf5ef2aSThomas Huth uint32_t inval; 7591fcf5ef2aSThomas Huth 7592b0c2d521SEmilio G. Cota if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) 7593b0c2d521SEmilio G. Cota && Rc(ctx->opcode))) { 7594fcf5ef2aSThomas Huth inval = handler->inval2; 7595fcf5ef2aSThomas Huth } else { 7596fcf5ef2aSThomas Huth inval = handler->inval1; 7597fcf5ef2aSThomas Huth } 7598fcf5ef2aSThomas Huth 7599b0c2d521SEmilio G. Cota if (unlikely((ctx->opcode & inval) != 0)) { 7600fcf5ef2aSThomas Huth qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " 7601fcf5ef2aSThomas Huth "%02x - %02x - %02x - %02x (%08x) " 7602b0c2d521SEmilio G. Cota TARGET_FMT_lx "\n", ctx->opcode & inval, 7603b0c2d521SEmilio G. Cota opc1(ctx->opcode), opc2(ctx->opcode), 7604b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), 7605b0c2d521SEmilio G. Cota ctx->opcode, ctx->base.pc_next - 4); 7606b0c2d521SEmilio G. Cota gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 7607b0c2d521SEmilio G. Cota ctx->base.is_jmp = DISAS_NORETURN; 7608b0c2d521SEmilio G. Cota return; 7609fcf5ef2aSThomas Huth } 7610fcf5ef2aSThomas Huth } 7611b0c2d521SEmilio G. Cota (*(handler->handler))(ctx); 7612fcf5ef2aSThomas Huth #if defined(DO_PPC_STATISTICS) 7613fcf5ef2aSThomas Huth handler->count++; 7614fcf5ef2aSThomas Huth #endif 7615fcf5ef2aSThomas Huth /* Check trace mode exceptions */ 7616b0c2d521SEmilio G. Cota if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && 7617b0c2d521SEmilio G. Cota (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && 7618b0c2d521SEmilio G. Cota ctx->exception != POWERPC_SYSCALL && 7619b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_TRAP && 7620b0c2d521SEmilio G. Cota ctx->exception != POWERPC_EXCP_BRANCH)) { 7621*0e3bf489SRoman Kapl uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_TRACE); 7622*0e3bf489SRoman Kapl if (excp != POWERPC_EXCP_NONE) 7623*0e3bf489SRoman Kapl gen_exception_nip(ctx, excp, ctx->base.pc_next); 7624fcf5ef2aSThomas Huth } 7625b0c2d521SEmilio G. Cota 7626fcf5ef2aSThomas Huth if (tcg_check_temp_count()) { 7627b0c2d521SEmilio G. Cota qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " 7628b0c2d521SEmilio G. Cota "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), 7629b0c2d521SEmilio G. Cota opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); 7630fcf5ef2aSThomas Huth } 7631b0c2d521SEmilio G. Cota 7632b0c2d521SEmilio G. Cota ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? 7633b0c2d521SEmilio G. Cota DISAS_NEXT : DISAS_NORETURN; 7634fcf5ef2aSThomas Huth } 7635b0c2d521SEmilio G. Cota 7636b0c2d521SEmilio G. Cota static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) 7637b0c2d521SEmilio G. Cota { 7638b0c2d521SEmilio G. Cota DisasContext *ctx = container_of(dcbase, DisasContext, base); 7639b0c2d521SEmilio G. Cota 7640b0c2d521SEmilio G. Cota if (ctx->exception == POWERPC_EXCP_NONE) { 7641b0c2d521SEmilio G. Cota gen_goto_tb(ctx, 0, ctx->base.pc_next); 7642b0c2d521SEmilio G. Cota } else if (ctx->exception != POWERPC_EXCP_BRANCH) { 7643b0c2d521SEmilio G. Cota if (unlikely(ctx->base.singlestep_enabled)) { 7644b0c2d521SEmilio G. Cota gen_debug_exception(ctx); 7645fcf5ef2aSThomas Huth } 7646fcf5ef2aSThomas Huth /* Generate the return instruction */ 764707ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 7648fcf5ef2aSThomas Huth } 7649fcf5ef2aSThomas Huth } 7650b0c2d521SEmilio G. Cota 7651b0c2d521SEmilio G. Cota static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) 7652b0c2d521SEmilio G. Cota { 7653b0c2d521SEmilio G. Cota qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 7654b0c2d521SEmilio G. Cota log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); 7655b0c2d521SEmilio G. Cota } 7656b0c2d521SEmilio G. Cota 7657b0c2d521SEmilio G. Cota static const TranslatorOps ppc_tr_ops = { 7658b0c2d521SEmilio G. Cota .init_disas_context = ppc_tr_init_disas_context, 7659b0c2d521SEmilio G. Cota .tb_start = ppc_tr_tb_start, 7660b0c2d521SEmilio G. Cota .insn_start = ppc_tr_insn_start, 7661b0c2d521SEmilio G. Cota .breakpoint_check = ppc_tr_breakpoint_check, 7662b0c2d521SEmilio G. Cota .translate_insn = ppc_tr_translate_insn, 7663b0c2d521SEmilio G. Cota .tb_stop = ppc_tr_tb_stop, 7664b0c2d521SEmilio G. Cota .disas_log = ppc_tr_disas_log, 7665b0c2d521SEmilio G. Cota }; 7666b0c2d521SEmilio G. Cota 7667b0c2d521SEmilio G. Cota void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 7668b0c2d521SEmilio G. Cota { 7669b0c2d521SEmilio G. Cota DisasContext ctx; 7670b0c2d521SEmilio G. Cota 7671b0c2d521SEmilio G. Cota translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); 7672fcf5ef2aSThomas Huth } 7673fcf5ef2aSThomas Huth 7674fcf5ef2aSThomas Huth void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, 7675fcf5ef2aSThomas Huth target_ulong *data) 7676fcf5ef2aSThomas Huth { 7677fcf5ef2aSThomas Huth env->nip = data[0]; 7678fcf5ef2aSThomas Huth } 7679