1*a2b0a27dSPhilippe Mathieu-Daudé /* 2*a2b0a27dSPhilippe Mathieu-Daudé * Toshiba TX79-specific instructions translation routines 3*a2b0a27dSPhilippe Mathieu-Daudé * 4*a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2018 Fredrik Noring 5*a2b0a27dSPhilippe Mathieu-Daudé * 6*a2b0a27dSPhilippe Mathieu-Daudé * SPDX-License-Identifier: GPL-2.0-or-later 7*a2b0a27dSPhilippe Mathieu-Daudé */ 8*a2b0a27dSPhilippe Mathieu-Daudé 9*a2b0a27dSPhilippe Mathieu-Daudé #include "qemu/osdep.h" 10*a2b0a27dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 11*a2b0a27dSPhilippe Mathieu-Daudé #include "exec/helper-gen.h" 12*a2b0a27dSPhilippe Mathieu-Daudé #include "translate.h" 13*a2b0a27dSPhilippe Mathieu-Daudé 14*a2b0a27dSPhilippe Mathieu-Daudé /* Include the auto-generated decoder. */ 15*a2b0a27dSPhilippe Mathieu-Daudé #include "decode-tx79.c.inc" 16*a2b0a27dSPhilippe Mathieu-Daudé 17*a2b0a27dSPhilippe Mathieu-Daudé /* 18*a2b0a27dSPhilippe Mathieu-Daudé * Overview of the TX79-specific instruction set 19*a2b0a27dSPhilippe Mathieu-Daudé * ============================================= 20*a2b0a27dSPhilippe Mathieu-Daudé * 21*a2b0a27dSPhilippe Mathieu-Daudé * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits 22*a2b0a27dSPhilippe Mathieu-Daudé * are only used by the specific quadword (128-bit) LQ/SQ load/store 23*a2b0a27dSPhilippe Mathieu-Daudé * instructions and certain multimedia instructions (MMIs). These MMIs 24*a2b0a27dSPhilippe Mathieu-Daudé * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit 25*a2b0a27dSPhilippe Mathieu-Daudé * or sixteen 8-bit paths. 26*a2b0a27dSPhilippe Mathieu-Daudé * 27*a2b0a27dSPhilippe Mathieu-Daudé * Reference: 28*a2b0a27dSPhilippe Mathieu-Daudé * 29*a2b0a27dSPhilippe Mathieu-Daudé * The Toshiba TX System RISC TX79 Core Architecture manual, 30*a2b0a27dSPhilippe Mathieu-Daudé * https://wiki.qemu.org/File:C790.pdf 31*a2b0a27dSPhilippe Mathieu-Daudé */ 32*a2b0a27dSPhilippe Mathieu-Daudé 33*a2b0a27dSPhilippe Mathieu-Daudé bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) 34*a2b0a27dSPhilippe Mathieu-Daudé { 35*a2b0a27dSPhilippe Mathieu-Daudé if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) { 36*a2b0a27dSPhilippe Mathieu-Daudé return true; 37*a2b0a27dSPhilippe Mathieu-Daudé } 38*a2b0a27dSPhilippe Mathieu-Daudé return false; 39*a2b0a27dSPhilippe Mathieu-Daudé } 40*a2b0a27dSPhilippe Mathieu-Daudé 41*a2b0a27dSPhilippe Mathieu-Daudé /* 42*a2b0a27dSPhilippe Mathieu-Daudé * Three-Operand Multiply and Multiply-Add (4 instructions) 43*a2b0a27dSPhilippe Mathieu-Daudé * -------------------------------------------------------- 44*a2b0a27dSPhilippe Mathieu-Daudé * MADD [rd,] rs, rt Multiply/Add 45*a2b0a27dSPhilippe Mathieu-Daudé * MADDU [rd,] rs, rt Multiply/Add Unsigned 46*a2b0a27dSPhilippe Mathieu-Daudé * MULT [rd,] rs, rt Multiply (3-operand) 47*a2b0a27dSPhilippe Mathieu-Daudé * MULTU [rd,] rs, rt Multiply Unsigned (3-operand) 48*a2b0a27dSPhilippe Mathieu-Daudé */ 49*a2b0a27dSPhilippe Mathieu-Daudé 50*a2b0a27dSPhilippe Mathieu-Daudé /* 51*a2b0a27dSPhilippe Mathieu-Daudé * Multiply Instructions for Pipeline 1 (10 instructions) 52*a2b0a27dSPhilippe Mathieu-Daudé * ------------------------------------------------------ 53*a2b0a27dSPhilippe Mathieu-Daudé * MULT1 [rd,] rs, rt Multiply Pipeline 1 54*a2b0a27dSPhilippe Mathieu-Daudé * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1 55*a2b0a27dSPhilippe Mathieu-Daudé * DIV1 rs, rt Divide Pipeline 1 56*a2b0a27dSPhilippe Mathieu-Daudé * DIVU1 rs, rt Divide Unsigned Pipeline 1 57*a2b0a27dSPhilippe Mathieu-Daudé * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1 58*a2b0a27dSPhilippe Mathieu-Daudé * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1 59*a2b0a27dSPhilippe Mathieu-Daudé * MFHI1 rd Move From HI1 Register 60*a2b0a27dSPhilippe Mathieu-Daudé * MFLO1 rd Move From LO1 Register 61*a2b0a27dSPhilippe Mathieu-Daudé * MTHI1 rs Move To HI1 Register 62*a2b0a27dSPhilippe Mathieu-Daudé * MTLO1 rs Move To LO1 Register 63*a2b0a27dSPhilippe Mathieu-Daudé */ 64*a2b0a27dSPhilippe Mathieu-Daudé 65*a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) 66*a2b0a27dSPhilippe Mathieu-Daudé { 67*a2b0a27dSPhilippe Mathieu-Daudé gen_store_gpr(cpu_HI[1], a->rd); 68*a2b0a27dSPhilippe Mathieu-Daudé 69*a2b0a27dSPhilippe Mathieu-Daudé return true; 70*a2b0a27dSPhilippe Mathieu-Daudé } 71*a2b0a27dSPhilippe Mathieu-Daudé 72*a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) 73*a2b0a27dSPhilippe Mathieu-Daudé { 74*a2b0a27dSPhilippe Mathieu-Daudé gen_store_gpr(cpu_LO[1], a->rd); 75*a2b0a27dSPhilippe Mathieu-Daudé 76*a2b0a27dSPhilippe Mathieu-Daudé return true; 77*a2b0a27dSPhilippe Mathieu-Daudé } 78*a2b0a27dSPhilippe Mathieu-Daudé 79*a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) 80*a2b0a27dSPhilippe Mathieu-Daudé { 81*a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(cpu_HI[1], a->rs); 82*a2b0a27dSPhilippe Mathieu-Daudé 83*a2b0a27dSPhilippe Mathieu-Daudé return true; 84*a2b0a27dSPhilippe Mathieu-Daudé } 85*a2b0a27dSPhilippe Mathieu-Daudé 86*a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) 87*a2b0a27dSPhilippe Mathieu-Daudé { 88*a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(cpu_LO[1], a->rs); 89*a2b0a27dSPhilippe Mathieu-Daudé 90*a2b0a27dSPhilippe Mathieu-Daudé return true; 91*a2b0a27dSPhilippe Mathieu-Daudé } 92*a2b0a27dSPhilippe Mathieu-Daudé 93*a2b0a27dSPhilippe Mathieu-Daudé /* 94*a2b0a27dSPhilippe Mathieu-Daudé * Arithmetic (19 instructions) 95*a2b0a27dSPhilippe Mathieu-Daudé * ---------------------------- 96*a2b0a27dSPhilippe Mathieu-Daudé * PADDB rd, rs, rt Parallel Add Byte 97*a2b0a27dSPhilippe Mathieu-Daudé * PSUBB rd, rs, rt Parallel Subtract Byte 98*a2b0a27dSPhilippe Mathieu-Daudé * PADDH rd, rs, rt Parallel Add Halfword 99*a2b0a27dSPhilippe Mathieu-Daudé * PSUBH rd, rs, rt Parallel Subtract Halfword 100*a2b0a27dSPhilippe Mathieu-Daudé * PADDW rd, rs, rt Parallel Add Word 101*a2b0a27dSPhilippe Mathieu-Daudé * PSUBW rd, rs, rt Parallel Subtract Word 102*a2b0a27dSPhilippe Mathieu-Daudé * PADSBH rd, rs, rt Parallel Add/Subtract Halfword 103*a2b0a27dSPhilippe Mathieu-Daudé * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte 104*a2b0a27dSPhilippe Mathieu-Daudé * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte 105*a2b0a27dSPhilippe Mathieu-Daudé * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword 106*a2b0a27dSPhilippe Mathieu-Daudé * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword 107*a2b0a27dSPhilippe Mathieu-Daudé * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word 108*a2b0a27dSPhilippe Mathieu-Daudé * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word 109*a2b0a27dSPhilippe Mathieu-Daudé * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte 110*a2b0a27dSPhilippe Mathieu-Daudé * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte 111*a2b0a27dSPhilippe Mathieu-Daudé * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword 112*a2b0a27dSPhilippe Mathieu-Daudé * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword 113*a2b0a27dSPhilippe Mathieu-Daudé * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word 114*a2b0a27dSPhilippe Mathieu-Daudé * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word 115*a2b0a27dSPhilippe Mathieu-Daudé */ 116*a2b0a27dSPhilippe Mathieu-Daudé 117*a2b0a27dSPhilippe Mathieu-Daudé /* 118*a2b0a27dSPhilippe Mathieu-Daudé * Min/Max (4 instructions) 119*a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 120*a2b0a27dSPhilippe Mathieu-Daudé * PMAXH rd, rs, rt Parallel Maximum Halfword 121*a2b0a27dSPhilippe Mathieu-Daudé * PMINH rd, rs, rt Parallel Minimum Halfword 122*a2b0a27dSPhilippe Mathieu-Daudé * PMAXW rd, rs, rt Parallel Maximum Word 123*a2b0a27dSPhilippe Mathieu-Daudé * PMINW rd, rs, rt Parallel Minimum Word 124*a2b0a27dSPhilippe Mathieu-Daudé */ 125*a2b0a27dSPhilippe Mathieu-Daudé 126*a2b0a27dSPhilippe Mathieu-Daudé /* 127*a2b0a27dSPhilippe Mathieu-Daudé * Absolute (2 instructions) 128*a2b0a27dSPhilippe Mathieu-Daudé * ------------------------- 129*a2b0a27dSPhilippe Mathieu-Daudé * PABSH rd, rt Parallel Absolute Halfword 130*a2b0a27dSPhilippe Mathieu-Daudé * PABSW rd, rt Parallel Absolute Word 131*a2b0a27dSPhilippe Mathieu-Daudé */ 132*a2b0a27dSPhilippe Mathieu-Daudé 133*a2b0a27dSPhilippe Mathieu-Daudé /* 134*a2b0a27dSPhilippe Mathieu-Daudé * Logical (4 instructions) 135*a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 136*a2b0a27dSPhilippe Mathieu-Daudé * PAND rd, rs, rt Parallel AND 137*a2b0a27dSPhilippe Mathieu-Daudé * POR rd, rs, rt Parallel OR 138*a2b0a27dSPhilippe Mathieu-Daudé * PXOR rd, rs, rt Parallel XOR 139*a2b0a27dSPhilippe Mathieu-Daudé * PNOR rd, rs, rt Parallel NOR 140*a2b0a27dSPhilippe Mathieu-Daudé */ 141*a2b0a27dSPhilippe Mathieu-Daudé 142*a2b0a27dSPhilippe Mathieu-Daudé /* 143*a2b0a27dSPhilippe Mathieu-Daudé * Shift (9 instructions) 144*a2b0a27dSPhilippe Mathieu-Daudé * ---------------------- 145*a2b0a27dSPhilippe Mathieu-Daudé * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword 146*a2b0a27dSPhilippe Mathieu-Daudé * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword 147*a2b0a27dSPhilippe Mathieu-Daudé * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword 148*a2b0a27dSPhilippe Mathieu-Daudé * PSLLW rd, rt, sa Parallel Shift Left Logical Word 149*a2b0a27dSPhilippe Mathieu-Daudé * PSRLW rd, rt, sa Parallel Shift Right Logical Word 150*a2b0a27dSPhilippe Mathieu-Daudé * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word 151*a2b0a27dSPhilippe Mathieu-Daudé * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word 152*a2b0a27dSPhilippe Mathieu-Daudé * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word 153*a2b0a27dSPhilippe Mathieu-Daudé * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word 154*a2b0a27dSPhilippe Mathieu-Daudé */ 155*a2b0a27dSPhilippe Mathieu-Daudé 156*a2b0a27dSPhilippe Mathieu-Daudé /* 157*a2b0a27dSPhilippe Mathieu-Daudé * Compare (6 instructions) 158*a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 159*a2b0a27dSPhilippe Mathieu-Daudé * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte 160*a2b0a27dSPhilippe Mathieu-Daudé * PCEQB rd, rs, rt Parallel Compare for Equal Byte 161*a2b0a27dSPhilippe Mathieu-Daudé * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword 162*a2b0a27dSPhilippe Mathieu-Daudé * PCEQH rd, rs, rt Parallel Compare for Equal Halfword 163*a2b0a27dSPhilippe Mathieu-Daudé * PCGTW rd, rs, rt Parallel Compare for Greater Than Word 164*a2b0a27dSPhilippe Mathieu-Daudé * PCEQW rd, rs, rt Parallel Compare for Equal Word 165*a2b0a27dSPhilippe Mathieu-Daudé */ 166*a2b0a27dSPhilippe Mathieu-Daudé 167*a2b0a27dSPhilippe Mathieu-Daudé /* 168*a2b0a27dSPhilippe Mathieu-Daudé * LZC (1 instruction) 169*a2b0a27dSPhilippe Mathieu-Daudé * ------------------- 170*a2b0a27dSPhilippe Mathieu-Daudé * PLZCW rd, rs Parallel Leading Zero or One Count Word 171*a2b0a27dSPhilippe Mathieu-Daudé */ 172*a2b0a27dSPhilippe Mathieu-Daudé 173*a2b0a27dSPhilippe Mathieu-Daudé /* 174*a2b0a27dSPhilippe Mathieu-Daudé * Quadword Load and Store (2 instructions) 175*a2b0a27dSPhilippe Mathieu-Daudé * ---------------------------------------- 176*a2b0a27dSPhilippe Mathieu-Daudé * LQ rt, offset(base) Load Quadword 177*a2b0a27dSPhilippe Mathieu-Daudé * SQ rt, offset(base) Store Quadword 178*a2b0a27dSPhilippe Mathieu-Daudé */ 179*a2b0a27dSPhilippe Mathieu-Daudé 180*a2b0a27dSPhilippe Mathieu-Daudé /* 181*a2b0a27dSPhilippe Mathieu-Daudé * Multiply and Divide (19 instructions) 182*a2b0a27dSPhilippe Mathieu-Daudé * ------------------------------------- 183*a2b0a27dSPhilippe Mathieu-Daudé * PMULTW rd, rs, rt Parallel Multiply Word 184*a2b0a27dSPhilippe Mathieu-Daudé * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word 185*a2b0a27dSPhilippe Mathieu-Daudé * PDIVW rs, rt Parallel Divide Word 186*a2b0a27dSPhilippe Mathieu-Daudé * PDIVUW rs, rt Parallel Divide Unsigned Word 187*a2b0a27dSPhilippe Mathieu-Daudé * PMADDW rd, rs, rt Parallel Multiply-Add Word 188*a2b0a27dSPhilippe Mathieu-Daudé * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word 189*a2b0a27dSPhilippe Mathieu-Daudé * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word 190*a2b0a27dSPhilippe Mathieu-Daudé * PMULTH rd, rs, rt Parallel Multiply Halfword 191*a2b0a27dSPhilippe Mathieu-Daudé * PMADDH rd, rs, rt Parallel Multiply-Add Halfword 192*a2b0a27dSPhilippe Mathieu-Daudé * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword 193*a2b0a27dSPhilippe Mathieu-Daudé * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword 194*a2b0a27dSPhilippe Mathieu-Daudé * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword 195*a2b0a27dSPhilippe Mathieu-Daudé * PDIVBW rs, rt Parallel Divide Broadcast Word 196*a2b0a27dSPhilippe Mathieu-Daudé * PMFHI rd Parallel Move From HI Register 197*a2b0a27dSPhilippe Mathieu-Daudé * PMFLO rd Parallel Move From LO Register 198*a2b0a27dSPhilippe Mathieu-Daudé * PMTHI rs Parallel Move To HI Register 199*a2b0a27dSPhilippe Mathieu-Daudé * PMTLO rs Parallel Move To LO Register 200*a2b0a27dSPhilippe Mathieu-Daudé * PMFHL rd Parallel Move From HI/LO Register 201*a2b0a27dSPhilippe Mathieu-Daudé * PMTHL rs Parallel Move To HI/LO Register 202*a2b0a27dSPhilippe Mathieu-Daudé */ 203*a2b0a27dSPhilippe Mathieu-Daudé 204*a2b0a27dSPhilippe Mathieu-Daudé /* 205*a2b0a27dSPhilippe Mathieu-Daudé * Pack/Extend (11 instructions) 206*a2b0a27dSPhilippe Mathieu-Daudé * ----------------------------- 207*a2b0a27dSPhilippe Mathieu-Daudé * PPAC5 rd, rt Parallel Pack to 5 bits 208*a2b0a27dSPhilippe Mathieu-Daudé * PPACB rd, rs, rt Parallel Pack to Byte 209*a2b0a27dSPhilippe Mathieu-Daudé * PPACH rd, rs, rt Parallel Pack to Halfword 210*a2b0a27dSPhilippe Mathieu-Daudé * PPACW rd, rs, rt Parallel Pack to Word 211*a2b0a27dSPhilippe Mathieu-Daudé * PEXT5 rd, rt Parallel Extend Upper from 5 bits 212*a2b0a27dSPhilippe Mathieu-Daudé * PEXTUB rd, rs, rt Parallel Extend Upper from Byte 213*a2b0a27dSPhilippe Mathieu-Daudé * PEXTLB rd, rs, rt Parallel Extend Lower from Byte 214*a2b0a27dSPhilippe Mathieu-Daudé * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword 215*a2b0a27dSPhilippe Mathieu-Daudé * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword 216*a2b0a27dSPhilippe Mathieu-Daudé * PEXTUW rd, rs, rt Parallel Extend Upper from Word 217*a2b0a27dSPhilippe Mathieu-Daudé * PEXTLW rd, rs, rt Parallel Extend Lower from Word 218*a2b0a27dSPhilippe Mathieu-Daudé */ 219*a2b0a27dSPhilippe Mathieu-Daudé 220*a2b0a27dSPhilippe Mathieu-Daudé /* 221*a2b0a27dSPhilippe Mathieu-Daudé * Others (16 instructions) 222*a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 223*a2b0a27dSPhilippe Mathieu-Daudé * PCPYH rd, rt Parallel Copy Halfword 224*a2b0a27dSPhilippe Mathieu-Daudé * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword 225*a2b0a27dSPhilippe Mathieu-Daudé * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword 226*a2b0a27dSPhilippe Mathieu-Daudé * PREVH rd, rt Parallel Reverse Halfword 227*a2b0a27dSPhilippe Mathieu-Daudé * PINTH rd, rs, rt Parallel Interleave Halfword 228*a2b0a27dSPhilippe Mathieu-Daudé * PINTEH rd, rs, rt Parallel Interleave Even Halfword 229*a2b0a27dSPhilippe Mathieu-Daudé * PEXEH rd, rt Parallel Exchange Even Halfword 230*a2b0a27dSPhilippe Mathieu-Daudé * PEXCH rd, rt Parallel Exchange Center Halfword 231*a2b0a27dSPhilippe Mathieu-Daudé * PEXEW rd, rt Parallel Exchange Even Word 232*a2b0a27dSPhilippe Mathieu-Daudé * PEXCW rd, rt Parallel Exchange Center Word 233*a2b0a27dSPhilippe Mathieu-Daudé * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable 234*a2b0a27dSPhilippe Mathieu-Daudé * MFSA rd Move from Shift Amount Register 235*a2b0a27dSPhilippe Mathieu-Daudé * MTSA rs Move to Shift Amount Register 236*a2b0a27dSPhilippe Mathieu-Daudé * MTSAB rs, immediate Move Byte Count to Shift Amount Register 237*a2b0a27dSPhilippe Mathieu-Daudé * MTSAH rs, immediate Move Halfword Count to Shift Amount Register 238*a2b0a27dSPhilippe Mathieu-Daudé * PROT3W rd, rt Parallel Rotate 3 Words 239*a2b0a27dSPhilippe Mathieu-Daudé */ 240*a2b0a27dSPhilippe Mathieu-Daudé 241*a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Halfword */ 242*a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYH(DisasContext *s, arg_rtype *a) 243*a2b0a27dSPhilippe Mathieu-Daudé { 244*a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 245*a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 246*a2b0a27dSPhilippe Mathieu-Daudé return true; 247*a2b0a27dSPhilippe Mathieu-Daudé } 248*a2b0a27dSPhilippe Mathieu-Daudé 249*a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 250*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 251*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 252*a2b0a27dSPhilippe Mathieu-Daudé return true; 253*a2b0a27dSPhilippe Mathieu-Daudé } 254*a2b0a27dSPhilippe Mathieu-Daudé 255*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16); 256*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32); 257*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16); 258*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32); 259*a2b0a27dSPhilippe Mathieu-Daudé 260*a2b0a27dSPhilippe Mathieu-Daudé return true; 261*a2b0a27dSPhilippe Mathieu-Daudé } 262*a2b0a27dSPhilippe Mathieu-Daudé 263*a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Lower Doubleword */ 264*a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) 265*a2b0a27dSPhilippe Mathieu-Daudé { 266*a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 267*a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 268*a2b0a27dSPhilippe Mathieu-Daudé return true; 269*a2b0a27dSPhilippe Mathieu-Daudé } 270*a2b0a27dSPhilippe Mathieu-Daudé 271*a2b0a27dSPhilippe Mathieu-Daudé if (a->rs == 0) { 272*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 273*a2b0a27dSPhilippe Mathieu-Daudé } else { 274*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]); 275*a2b0a27dSPhilippe Mathieu-Daudé } 276*a2b0a27dSPhilippe Mathieu-Daudé 277*a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 278*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 279*a2b0a27dSPhilippe Mathieu-Daudé } else if (a->rd != a->rt) { 280*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); 281*a2b0a27dSPhilippe Mathieu-Daudé } 282*a2b0a27dSPhilippe Mathieu-Daudé 283*a2b0a27dSPhilippe Mathieu-Daudé return true; 284*a2b0a27dSPhilippe Mathieu-Daudé } 285*a2b0a27dSPhilippe Mathieu-Daudé 286*a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Upper Doubleword */ 287*a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) 288*a2b0a27dSPhilippe Mathieu-Daudé { 289*a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 290*a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 291*a2b0a27dSPhilippe Mathieu-Daudé return true; 292*a2b0a27dSPhilippe Mathieu-Daudé } 293*a2b0a27dSPhilippe Mathieu-Daudé 294*a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr_hi(cpu_gpr[a->rd], a->rs); 295*a2b0a27dSPhilippe Mathieu-Daudé 296*a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 297*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 298*a2b0a27dSPhilippe Mathieu-Daudé } else if (a->rd != a->rt) { 299*a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); 300*a2b0a27dSPhilippe Mathieu-Daudé } 301*a2b0a27dSPhilippe Mathieu-Daudé 302*a2b0a27dSPhilippe Mathieu-Daudé return true; 303*a2b0a27dSPhilippe Mathieu-Daudé } 304