1a2b0a27dSPhilippe Mathieu-Daudé /* 2a2b0a27dSPhilippe Mathieu-Daudé * Toshiba TX79-specific instructions translation routines 3a2b0a27dSPhilippe Mathieu-Daudé * 4a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2018 Fredrik Noring 52d4ab117SPhilippe Mathieu-Daudé * Copyright (c) 2021 Philippe Mathieu-Daudé 6a2b0a27dSPhilippe Mathieu-Daudé * 7a2b0a27dSPhilippe Mathieu-Daudé * SPDX-License-Identifier: GPL-2.0-or-later 8a2b0a27dSPhilippe Mathieu-Daudé */ 9a2b0a27dSPhilippe Mathieu-Daudé 10a2b0a27dSPhilippe Mathieu-Daudé #include "qemu/osdep.h" 11a2b0a27dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 12709324dcSPhilippe Mathieu-Daudé #include "tcg/tcg-op-gvec.h" 13a2b0a27dSPhilippe Mathieu-Daudé #include "exec/helper-gen.h" 14a2b0a27dSPhilippe Mathieu-Daudé #include "translate.h" 15a2b0a27dSPhilippe Mathieu-Daudé 16a2b0a27dSPhilippe Mathieu-Daudé /* Include the auto-generated decoder. */ 17a2b0a27dSPhilippe Mathieu-Daudé #include "decode-tx79.c.inc" 18a2b0a27dSPhilippe Mathieu-Daudé 19a2b0a27dSPhilippe Mathieu-Daudé /* 20a2b0a27dSPhilippe Mathieu-Daudé * Overview of the TX79-specific instruction set 21a2b0a27dSPhilippe Mathieu-Daudé * ============================================= 22a2b0a27dSPhilippe Mathieu-Daudé * 23a2b0a27dSPhilippe Mathieu-Daudé * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits 24a2b0a27dSPhilippe Mathieu-Daudé * are only used by the specific quadword (128-bit) LQ/SQ load/store 25a2b0a27dSPhilippe Mathieu-Daudé * instructions and certain multimedia instructions (MMIs). These MMIs 26a2b0a27dSPhilippe Mathieu-Daudé * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit 27a2b0a27dSPhilippe Mathieu-Daudé * or sixteen 8-bit paths. 28a2b0a27dSPhilippe Mathieu-Daudé * 29a2b0a27dSPhilippe Mathieu-Daudé * Reference: 30a2b0a27dSPhilippe Mathieu-Daudé * 31a2b0a27dSPhilippe Mathieu-Daudé * The Toshiba TX System RISC TX79 Core Architecture manual, 32a2b0a27dSPhilippe Mathieu-Daudé * https://wiki.qemu.org/File:C790.pdf 33a2b0a27dSPhilippe Mathieu-Daudé */ 34a2b0a27dSPhilippe Mathieu-Daudé 35a2b0a27dSPhilippe Mathieu-Daudé bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) 36a2b0a27dSPhilippe Mathieu-Daudé { 37a2b0a27dSPhilippe Mathieu-Daudé if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) { 38a2b0a27dSPhilippe Mathieu-Daudé return true; 39a2b0a27dSPhilippe Mathieu-Daudé } 40a2b0a27dSPhilippe Mathieu-Daudé return false; 41a2b0a27dSPhilippe Mathieu-Daudé } 42a2b0a27dSPhilippe Mathieu-Daudé 43a2b0a27dSPhilippe Mathieu-Daudé /* 44a2b0a27dSPhilippe Mathieu-Daudé * Three-Operand Multiply and Multiply-Add (4 instructions) 45a2b0a27dSPhilippe Mathieu-Daudé * -------------------------------------------------------- 46a2b0a27dSPhilippe Mathieu-Daudé * MADD [rd,] rs, rt Multiply/Add 47a2b0a27dSPhilippe Mathieu-Daudé * MADDU [rd,] rs, rt Multiply/Add Unsigned 48a2b0a27dSPhilippe Mathieu-Daudé * MULT [rd,] rs, rt Multiply (3-operand) 49a2b0a27dSPhilippe Mathieu-Daudé * MULTU [rd,] rs, rt Multiply Unsigned (3-operand) 50a2b0a27dSPhilippe Mathieu-Daudé */ 51a2b0a27dSPhilippe Mathieu-Daudé 52a2b0a27dSPhilippe Mathieu-Daudé /* 53a2b0a27dSPhilippe Mathieu-Daudé * Multiply Instructions for Pipeline 1 (10 instructions) 54a2b0a27dSPhilippe Mathieu-Daudé * ------------------------------------------------------ 55a2b0a27dSPhilippe Mathieu-Daudé * MULT1 [rd,] rs, rt Multiply Pipeline 1 56a2b0a27dSPhilippe Mathieu-Daudé * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1 57a2b0a27dSPhilippe Mathieu-Daudé * DIV1 rs, rt Divide Pipeline 1 58a2b0a27dSPhilippe Mathieu-Daudé * DIVU1 rs, rt Divide Unsigned Pipeline 1 59a2b0a27dSPhilippe Mathieu-Daudé * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1 60a2b0a27dSPhilippe Mathieu-Daudé * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1 61a2b0a27dSPhilippe Mathieu-Daudé * MFHI1 rd Move From HI1 Register 62a2b0a27dSPhilippe Mathieu-Daudé * MFLO1 rd Move From LO1 Register 63a2b0a27dSPhilippe Mathieu-Daudé * MTHI1 rs Move To HI1 Register 64a2b0a27dSPhilippe Mathieu-Daudé * MTLO1 rs Move To LO1 Register 65a2b0a27dSPhilippe Mathieu-Daudé */ 66a2b0a27dSPhilippe Mathieu-Daudé 67a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) 68a2b0a27dSPhilippe Mathieu-Daudé { 69a2b0a27dSPhilippe Mathieu-Daudé gen_store_gpr(cpu_HI[1], a->rd); 70a2b0a27dSPhilippe Mathieu-Daudé 71a2b0a27dSPhilippe Mathieu-Daudé return true; 72a2b0a27dSPhilippe Mathieu-Daudé } 73a2b0a27dSPhilippe Mathieu-Daudé 74a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) 75a2b0a27dSPhilippe Mathieu-Daudé { 76a2b0a27dSPhilippe Mathieu-Daudé gen_store_gpr(cpu_LO[1], a->rd); 77a2b0a27dSPhilippe Mathieu-Daudé 78a2b0a27dSPhilippe Mathieu-Daudé return true; 79a2b0a27dSPhilippe Mathieu-Daudé } 80a2b0a27dSPhilippe Mathieu-Daudé 81a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) 82a2b0a27dSPhilippe Mathieu-Daudé { 83a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(cpu_HI[1], a->rs); 84a2b0a27dSPhilippe Mathieu-Daudé 85a2b0a27dSPhilippe Mathieu-Daudé return true; 86a2b0a27dSPhilippe Mathieu-Daudé } 87a2b0a27dSPhilippe Mathieu-Daudé 88a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) 89a2b0a27dSPhilippe Mathieu-Daudé { 90a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(cpu_LO[1], a->rs); 91a2b0a27dSPhilippe Mathieu-Daudé 92a2b0a27dSPhilippe Mathieu-Daudé return true; 93a2b0a27dSPhilippe Mathieu-Daudé } 94a2b0a27dSPhilippe Mathieu-Daudé 95a2b0a27dSPhilippe Mathieu-Daudé /* 96a2b0a27dSPhilippe Mathieu-Daudé * Arithmetic (19 instructions) 97a2b0a27dSPhilippe Mathieu-Daudé * ---------------------------- 98a2b0a27dSPhilippe Mathieu-Daudé * PADDB rd, rs, rt Parallel Add Byte 99a2b0a27dSPhilippe Mathieu-Daudé * PSUBB rd, rs, rt Parallel Subtract Byte 100a2b0a27dSPhilippe Mathieu-Daudé * PADDH rd, rs, rt Parallel Add Halfword 101a2b0a27dSPhilippe Mathieu-Daudé * PSUBH rd, rs, rt Parallel Subtract Halfword 102a2b0a27dSPhilippe Mathieu-Daudé * PADDW rd, rs, rt Parallel Add Word 103a2b0a27dSPhilippe Mathieu-Daudé * PSUBW rd, rs, rt Parallel Subtract Word 104a2b0a27dSPhilippe Mathieu-Daudé * PADSBH rd, rs, rt Parallel Add/Subtract Halfword 105a2b0a27dSPhilippe Mathieu-Daudé * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte 106a2b0a27dSPhilippe Mathieu-Daudé * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte 107a2b0a27dSPhilippe Mathieu-Daudé * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword 108a2b0a27dSPhilippe Mathieu-Daudé * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword 109a2b0a27dSPhilippe Mathieu-Daudé * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word 110a2b0a27dSPhilippe Mathieu-Daudé * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word 111a2b0a27dSPhilippe Mathieu-Daudé * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte 112a2b0a27dSPhilippe Mathieu-Daudé * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte 113a2b0a27dSPhilippe Mathieu-Daudé * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword 114a2b0a27dSPhilippe Mathieu-Daudé * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword 115a2b0a27dSPhilippe Mathieu-Daudé * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word 116a2b0a27dSPhilippe Mathieu-Daudé * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word 117a2b0a27dSPhilippe Mathieu-Daudé */ 118a2b0a27dSPhilippe Mathieu-Daudé 1192d4ab117SPhilippe Mathieu-Daudé static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a, 1202d4ab117SPhilippe Mathieu-Daudé void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64)) 1212d4ab117SPhilippe Mathieu-Daudé { 1222d4ab117SPhilippe Mathieu-Daudé TCGv_i64 ax, bx; 1232d4ab117SPhilippe Mathieu-Daudé 1242d4ab117SPhilippe Mathieu-Daudé if (a->rd == 0) { 1252d4ab117SPhilippe Mathieu-Daudé /* nop */ 1262d4ab117SPhilippe Mathieu-Daudé return true; 1272d4ab117SPhilippe Mathieu-Daudé } 1282d4ab117SPhilippe Mathieu-Daudé 1292d4ab117SPhilippe Mathieu-Daudé ax = tcg_temp_new_i64(); 1302d4ab117SPhilippe Mathieu-Daudé bx = tcg_temp_new_i64(); 1312d4ab117SPhilippe Mathieu-Daudé 1322d4ab117SPhilippe Mathieu-Daudé /* Lower half */ 1332d4ab117SPhilippe Mathieu-Daudé gen_load_gpr(ax, a->rs); 1342d4ab117SPhilippe Mathieu-Daudé gen_load_gpr(bx, a->rt); 1352d4ab117SPhilippe Mathieu-Daudé gen_logic_i64(cpu_gpr[a->rd], ax, bx); 1362d4ab117SPhilippe Mathieu-Daudé 1372d4ab117SPhilippe Mathieu-Daudé /* Upper half */ 1382d4ab117SPhilippe Mathieu-Daudé gen_load_gpr_hi(ax, a->rs); 1392d4ab117SPhilippe Mathieu-Daudé gen_load_gpr_hi(bx, a->rt); 1402d4ab117SPhilippe Mathieu-Daudé gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); 1412d4ab117SPhilippe Mathieu-Daudé 1422d4ab117SPhilippe Mathieu-Daudé tcg_temp_free(bx); 1432d4ab117SPhilippe Mathieu-Daudé tcg_temp_free(ax); 1442d4ab117SPhilippe Mathieu-Daudé 1452d4ab117SPhilippe Mathieu-Daudé return true; 1462d4ab117SPhilippe Mathieu-Daudé } 1472d4ab117SPhilippe Mathieu-Daudé 148709324dcSPhilippe Mathieu-Daudé /* Parallel Subtract Byte */ 149709324dcSPhilippe Mathieu-Daudé static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a) 150709324dcSPhilippe Mathieu-Daudé { 151709324dcSPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64); 152709324dcSPhilippe Mathieu-Daudé } 153709324dcSPhilippe Mathieu-Daudé 154709324dcSPhilippe Mathieu-Daudé /* Parallel Subtract Halfword */ 155709324dcSPhilippe Mathieu-Daudé static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a) 156709324dcSPhilippe Mathieu-Daudé { 157709324dcSPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64); 158709324dcSPhilippe Mathieu-Daudé } 159709324dcSPhilippe Mathieu-Daudé 160709324dcSPhilippe Mathieu-Daudé /* Parallel Subtract Word */ 161709324dcSPhilippe Mathieu-Daudé static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a) 162709324dcSPhilippe Mathieu-Daudé { 163709324dcSPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64); 164709324dcSPhilippe Mathieu-Daudé } 165709324dcSPhilippe Mathieu-Daudé 166a2b0a27dSPhilippe Mathieu-Daudé /* 167a2b0a27dSPhilippe Mathieu-Daudé * Min/Max (4 instructions) 168a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 169a2b0a27dSPhilippe Mathieu-Daudé * PMAXH rd, rs, rt Parallel Maximum Halfword 170a2b0a27dSPhilippe Mathieu-Daudé * PMINH rd, rs, rt Parallel Minimum Halfword 171a2b0a27dSPhilippe Mathieu-Daudé * PMAXW rd, rs, rt Parallel Maximum Word 172a2b0a27dSPhilippe Mathieu-Daudé * PMINW rd, rs, rt Parallel Minimum Word 173a2b0a27dSPhilippe Mathieu-Daudé */ 174a2b0a27dSPhilippe Mathieu-Daudé 175a2b0a27dSPhilippe Mathieu-Daudé /* 176a2b0a27dSPhilippe Mathieu-Daudé * Absolute (2 instructions) 177a2b0a27dSPhilippe Mathieu-Daudé * ------------------------- 178a2b0a27dSPhilippe Mathieu-Daudé * PABSH rd, rt Parallel Absolute Halfword 179a2b0a27dSPhilippe Mathieu-Daudé * PABSW rd, rt Parallel Absolute Word 180a2b0a27dSPhilippe Mathieu-Daudé */ 181a2b0a27dSPhilippe Mathieu-Daudé 182a2b0a27dSPhilippe Mathieu-Daudé /* 183a2b0a27dSPhilippe Mathieu-Daudé * Logical (4 instructions) 184a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 185a2b0a27dSPhilippe Mathieu-Daudé * PAND rd, rs, rt Parallel AND 186a2b0a27dSPhilippe Mathieu-Daudé * POR rd, rs, rt Parallel OR 187a2b0a27dSPhilippe Mathieu-Daudé * PXOR rd, rs, rt Parallel XOR 188a2b0a27dSPhilippe Mathieu-Daudé * PNOR rd, rs, rt Parallel NOR 189a2b0a27dSPhilippe Mathieu-Daudé */ 190a2b0a27dSPhilippe Mathieu-Daudé 1912d4ab117SPhilippe Mathieu-Daudé /* Parallel And */ 1922d4ab117SPhilippe Mathieu-Daudé static bool trans_PAND(DisasContext *ctx, arg_rtype *a) 1932d4ab117SPhilippe Mathieu-Daudé { 1942d4ab117SPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_and_i64); 1952d4ab117SPhilippe Mathieu-Daudé } 1962d4ab117SPhilippe Mathieu-Daudé 1972d4ab117SPhilippe Mathieu-Daudé /* Parallel Or */ 1982d4ab117SPhilippe Mathieu-Daudé static bool trans_POR(DisasContext *ctx, arg_rtype *a) 1992d4ab117SPhilippe Mathieu-Daudé { 2002d4ab117SPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_or_i64); 2012d4ab117SPhilippe Mathieu-Daudé } 2022d4ab117SPhilippe Mathieu-Daudé 2032d4ab117SPhilippe Mathieu-Daudé /* Parallel Exclusive Or */ 2042d4ab117SPhilippe Mathieu-Daudé static bool trans_PXOR(DisasContext *ctx, arg_rtype *a) 2052d4ab117SPhilippe Mathieu-Daudé { 2062d4ab117SPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_xor_i64); 2072d4ab117SPhilippe Mathieu-Daudé } 2082d4ab117SPhilippe Mathieu-Daudé 2092d4ab117SPhilippe Mathieu-Daudé /* Parallel Not Or */ 2102d4ab117SPhilippe Mathieu-Daudé static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) 2112d4ab117SPhilippe Mathieu-Daudé { 2122d4ab117SPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_nor_i64); 2132d4ab117SPhilippe Mathieu-Daudé } 2142d4ab117SPhilippe Mathieu-Daudé 215a2b0a27dSPhilippe Mathieu-Daudé /* 216a2b0a27dSPhilippe Mathieu-Daudé * Shift (9 instructions) 217a2b0a27dSPhilippe Mathieu-Daudé * ---------------------- 218a2b0a27dSPhilippe Mathieu-Daudé * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword 219a2b0a27dSPhilippe Mathieu-Daudé * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword 220a2b0a27dSPhilippe Mathieu-Daudé * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword 221a2b0a27dSPhilippe Mathieu-Daudé * PSLLW rd, rt, sa Parallel Shift Left Logical Word 222a2b0a27dSPhilippe Mathieu-Daudé * PSRLW rd, rt, sa Parallel Shift Right Logical Word 223a2b0a27dSPhilippe Mathieu-Daudé * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word 224a2b0a27dSPhilippe Mathieu-Daudé * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word 225a2b0a27dSPhilippe Mathieu-Daudé * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word 226a2b0a27dSPhilippe Mathieu-Daudé * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word 227a2b0a27dSPhilippe Mathieu-Daudé */ 228a2b0a27dSPhilippe Mathieu-Daudé 229a2b0a27dSPhilippe Mathieu-Daudé /* 230a2b0a27dSPhilippe Mathieu-Daudé * Compare (6 instructions) 231a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 232a2b0a27dSPhilippe Mathieu-Daudé * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte 233a2b0a27dSPhilippe Mathieu-Daudé * PCEQB rd, rs, rt Parallel Compare for Equal Byte 234a2b0a27dSPhilippe Mathieu-Daudé * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword 235a2b0a27dSPhilippe Mathieu-Daudé * PCEQH rd, rs, rt Parallel Compare for Equal Halfword 236a2b0a27dSPhilippe Mathieu-Daudé * PCGTW rd, rs, rt Parallel Compare for Greater Than Word 237a2b0a27dSPhilippe Mathieu-Daudé * PCEQW rd, rs, rt Parallel Compare for Equal Word 238a2b0a27dSPhilippe Mathieu-Daudé */ 239a2b0a27dSPhilippe Mathieu-Daudé 24082fbf9fcSPhilippe Mathieu-Daudé static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a, 24182fbf9fcSPhilippe Mathieu-Daudé TCGCond cond, unsigned wlen) 24282fbf9fcSPhilippe Mathieu-Daudé { 24382fbf9fcSPhilippe Mathieu-Daudé TCGv_i64 c0, c1, ax, bx, t0, t1, t2; 24482fbf9fcSPhilippe Mathieu-Daudé 24582fbf9fcSPhilippe Mathieu-Daudé if (a->rd == 0) { 24682fbf9fcSPhilippe Mathieu-Daudé /* nop */ 24782fbf9fcSPhilippe Mathieu-Daudé return true; 24882fbf9fcSPhilippe Mathieu-Daudé } 24982fbf9fcSPhilippe Mathieu-Daudé 25082fbf9fcSPhilippe Mathieu-Daudé c0 = tcg_const_tl(0); 25182fbf9fcSPhilippe Mathieu-Daudé c1 = tcg_const_tl(0xffffffff); 25282fbf9fcSPhilippe Mathieu-Daudé ax = tcg_temp_new_i64(); 25382fbf9fcSPhilippe Mathieu-Daudé bx = tcg_temp_new_i64(); 25482fbf9fcSPhilippe Mathieu-Daudé t0 = tcg_temp_new_i64(); 25582fbf9fcSPhilippe Mathieu-Daudé t1 = tcg_temp_new_i64(); 25682fbf9fcSPhilippe Mathieu-Daudé t2 = tcg_temp_new_i64(); 25782fbf9fcSPhilippe Mathieu-Daudé 25882fbf9fcSPhilippe Mathieu-Daudé /* Lower half */ 25982fbf9fcSPhilippe Mathieu-Daudé gen_load_gpr(ax, a->rs); 26082fbf9fcSPhilippe Mathieu-Daudé gen_load_gpr(bx, a->rt); 26182fbf9fcSPhilippe Mathieu-Daudé for (int i = 0; i < (64 / wlen); i++) { 26282fbf9fcSPhilippe Mathieu-Daudé tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); 26382fbf9fcSPhilippe Mathieu-Daudé tcg_gen_sextract_i64(t1, bx, wlen * i, wlen); 26482fbf9fcSPhilippe Mathieu-Daudé tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); 26582fbf9fcSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); 26682fbf9fcSPhilippe Mathieu-Daudé } 26782fbf9fcSPhilippe Mathieu-Daudé /* Upper half */ 26882fbf9fcSPhilippe Mathieu-Daudé gen_load_gpr_hi(ax, a->rs); 26982fbf9fcSPhilippe Mathieu-Daudé gen_load_gpr_hi(bx, a->rt); 27082fbf9fcSPhilippe Mathieu-Daudé for (int i = 0; i < (64 / wlen); i++) { 27182fbf9fcSPhilippe Mathieu-Daudé tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); 27282fbf9fcSPhilippe Mathieu-Daudé tcg_gen_sextract_i64(t1, bx, wlen * i, wlen); 27382fbf9fcSPhilippe Mathieu-Daudé tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); 27482fbf9fcSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen); 27582fbf9fcSPhilippe Mathieu-Daudé } 27682fbf9fcSPhilippe Mathieu-Daudé 27782fbf9fcSPhilippe Mathieu-Daudé tcg_temp_free(t2); 27882fbf9fcSPhilippe Mathieu-Daudé tcg_temp_free(t1); 27982fbf9fcSPhilippe Mathieu-Daudé tcg_temp_free(t0); 28082fbf9fcSPhilippe Mathieu-Daudé tcg_temp_free(bx); 28182fbf9fcSPhilippe Mathieu-Daudé tcg_temp_free(ax); 28282fbf9fcSPhilippe Mathieu-Daudé tcg_temp_free(c1); 28382fbf9fcSPhilippe Mathieu-Daudé tcg_temp_free(c0); 28482fbf9fcSPhilippe Mathieu-Daudé 28582fbf9fcSPhilippe Mathieu-Daudé return true; 28682fbf9fcSPhilippe Mathieu-Daudé } 28782fbf9fcSPhilippe Mathieu-Daudé 2888bd42c00SPhilippe Mathieu-Daudé /* Parallel Compare for Greater Than Byte */ 2898bd42c00SPhilippe Mathieu-Daudé static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a) 2908bd42c00SPhilippe Mathieu-Daudé { 2918bd42c00SPhilippe Mathieu-Daudé return trans_parallel_compare(ctx, a, TCG_COND_GE, 8); 2928bd42c00SPhilippe Mathieu-Daudé } 2938bd42c00SPhilippe Mathieu-Daudé 29482fbf9fcSPhilippe Mathieu-Daudé /* Parallel Compare for Equal Byte */ 29582fbf9fcSPhilippe Mathieu-Daudé static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a) 29682fbf9fcSPhilippe Mathieu-Daudé { 29782fbf9fcSPhilippe Mathieu-Daudé return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8); 29882fbf9fcSPhilippe Mathieu-Daudé } 29982fbf9fcSPhilippe Mathieu-Daudé 3008bd42c00SPhilippe Mathieu-Daudé /* Parallel Compare for Greater Than Halfword */ 3018bd42c00SPhilippe Mathieu-Daudé static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a) 3028bd42c00SPhilippe Mathieu-Daudé { 3038bd42c00SPhilippe Mathieu-Daudé return trans_parallel_compare(ctx, a, TCG_COND_GE, 16); 3048bd42c00SPhilippe Mathieu-Daudé } 3058bd42c00SPhilippe Mathieu-Daudé 30682fbf9fcSPhilippe Mathieu-Daudé /* Parallel Compare for Equal Halfword */ 30782fbf9fcSPhilippe Mathieu-Daudé static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a) 30882fbf9fcSPhilippe Mathieu-Daudé { 30982fbf9fcSPhilippe Mathieu-Daudé return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16); 31082fbf9fcSPhilippe Mathieu-Daudé } 31182fbf9fcSPhilippe Mathieu-Daudé 3128bd42c00SPhilippe Mathieu-Daudé /* Parallel Compare for Greater Than Word */ 3138bd42c00SPhilippe Mathieu-Daudé static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a) 3148bd42c00SPhilippe Mathieu-Daudé { 3158bd42c00SPhilippe Mathieu-Daudé return trans_parallel_compare(ctx, a, TCG_COND_GE, 32); 3168bd42c00SPhilippe Mathieu-Daudé } 3178bd42c00SPhilippe Mathieu-Daudé 31882fbf9fcSPhilippe Mathieu-Daudé /* Parallel Compare for Equal Word */ 31982fbf9fcSPhilippe Mathieu-Daudé static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) 32082fbf9fcSPhilippe Mathieu-Daudé { 32182fbf9fcSPhilippe Mathieu-Daudé return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32); 32282fbf9fcSPhilippe Mathieu-Daudé } 32382fbf9fcSPhilippe Mathieu-Daudé 324a2b0a27dSPhilippe Mathieu-Daudé /* 325a2b0a27dSPhilippe Mathieu-Daudé * LZC (1 instruction) 326a2b0a27dSPhilippe Mathieu-Daudé * ------------------- 327a2b0a27dSPhilippe Mathieu-Daudé * PLZCW rd, rs Parallel Leading Zero or One Count Word 328a2b0a27dSPhilippe Mathieu-Daudé */ 329a2b0a27dSPhilippe Mathieu-Daudé 330a2b0a27dSPhilippe Mathieu-Daudé /* 331a2b0a27dSPhilippe Mathieu-Daudé * Quadword Load and Store (2 instructions) 332a2b0a27dSPhilippe Mathieu-Daudé * ---------------------------------------- 333a2b0a27dSPhilippe Mathieu-Daudé * LQ rt, offset(base) Load Quadword 334a2b0a27dSPhilippe Mathieu-Daudé * SQ rt, offset(base) Store Quadword 335a2b0a27dSPhilippe Mathieu-Daudé */ 336a2b0a27dSPhilippe Mathieu-Daudé 337aaaa82a9SPhilippe Mathieu-Daudé static bool trans_LQ(DisasContext *ctx, arg_itype *a) 338aaaa82a9SPhilippe Mathieu-Daudé { 339aaaa82a9SPhilippe Mathieu-Daudé TCGv_i64 t0; 340aaaa82a9SPhilippe Mathieu-Daudé TCGv addr; 341aaaa82a9SPhilippe Mathieu-Daudé 342aaaa82a9SPhilippe Mathieu-Daudé if (a->rt == 0) { 343aaaa82a9SPhilippe Mathieu-Daudé /* nop */ 344aaaa82a9SPhilippe Mathieu-Daudé return true; 345aaaa82a9SPhilippe Mathieu-Daudé } 346aaaa82a9SPhilippe Mathieu-Daudé 347aaaa82a9SPhilippe Mathieu-Daudé t0 = tcg_temp_new_i64(); 348aaaa82a9SPhilippe Mathieu-Daudé addr = tcg_temp_new(); 349aaaa82a9SPhilippe Mathieu-Daudé 350aaaa82a9SPhilippe Mathieu-Daudé gen_base_offset_addr(ctx, addr, a->base, a->offset); 351aaaa82a9SPhilippe Mathieu-Daudé /* 352aaaa82a9SPhilippe Mathieu-Daudé * Clear least-significant four bits of the effective 353aaaa82a9SPhilippe Mathieu-Daudé * address, effectively creating an aligned address. 354aaaa82a9SPhilippe Mathieu-Daudé */ 355aaaa82a9SPhilippe Mathieu-Daudé tcg_gen_andi_tl(addr, addr, ~0xf); 356aaaa82a9SPhilippe Mathieu-Daudé 357aaaa82a9SPhilippe Mathieu-Daudé /* Lower half */ 358aaaa82a9SPhilippe Mathieu-Daudé tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ); 359aaaa82a9SPhilippe Mathieu-Daudé gen_store_gpr(t0, a->rt); 360aaaa82a9SPhilippe Mathieu-Daudé 361aaaa82a9SPhilippe Mathieu-Daudé /* Upper half */ 362aaaa82a9SPhilippe Mathieu-Daudé tcg_gen_addi_i64(addr, addr, 8); 363aaaa82a9SPhilippe Mathieu-Daudé tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ); 364aaaa82a9SPhilippe Mathieu-Daudé gen_store_gpr_hi(t0, a->rt); 365aaaa82a9SPhilippe Mathieu-Daudé 366aaaa82a9SPhilippe Mathieu-Daudé tcg_temp_free(t0); 367aaaa82a9SPhilippe Mathieu-Daudé tcg_temp_free(addr); 368aaaa82a9SPhilippe Mathieu-Daudé 369aaaa82a9SPhilippe Mathieu-Daudé return true; 370aaaa82a9SPhilippe Mathieu-Daudé } 371aaaa82a9SPhilippe Mathieu-Daudé 372*80ad6303SPhilippe Mathieu-Daudé static bool trans_SQ(DisasContext *ctx, arg_itype *a) 373*80ad6303SPhilippe Mathieu-Daudé { 374*80ad6303SPhilippe Mathieu-Daudé TCGv_i64 t0 = tcg_temp_new_i64(); 375*80ad6303SPhilippe Mathieu-Daudé TCGv addr = tcg_temp_new(); 376*80ad6303SPhilippe Mathieu-Daudé 377*80ad6303SPhilippe Mathieu-Daudé gen_base_offset_addr(ctx, addr, a->base, a->offset); 378*80ad6303SPhilippe Mathieu-Daudé /* 379*80ad6303SPhilippe Mathieu-Daudé * Clear least-significant four bits of the effective 380*80ad6303SPhilippe Mathieu-Daudé * address, effectively creating an aligned address. 381*80ad6303SPhilippe Mathieu-Daudé */ 382*80ad6303SPhilippe Mathieu-Daudé tcg_gen_andi_tl(addr, addr, ~0xf); 383*80ad6303SPhilippe Mathieu-Daudé 384*80ad6303SPhilippe Mathieu-Daudé /* Lower half */ 385*80ad6303SPhilippe Mathieu-Daudé gen_load_gpr(t0, a->rt); 386*80ad6303SPhilippe Mathieu-Daudé tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); 387*80ad6303SPhilippe Mathieu-Daudé 388*80ad6303SPhilippe Mathieu-Daudé /* Upper half */ 389*80ad6303SPhilippe Mathieu-Daudé tcg_gen_addi_i64(addr, addr, 8); 390*80ad6303SPhilippe Mathieu-Daudé gen_load_gpr_hi(t0, a->rt); 391*80ad6303SPhilippe Mathieu-Daudé tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); 392*80ad6303SPhilippe Mathieu-Daudé 393*80ad6303SPhilippe Mathieu-Daudé tcg_temp_free(addr); 394*80ad6303SPhilippe Mathieu-Daudé tcg_temp_free(t0); 395*80ad6303SPhilippe Mathieu-Daudé 396*80ad6303SPhilippe Mathieu-Daudé return true; 397*80ad6303SPhilippe Mathieu-Daudé } 398*80ad6303SPhilippe Mathieu-Daudé 399a2b0a27dSPhilippe Mathieu-Daudé /* 400a2b0a27dSPhilippe Mathieu-Daudé * Multiply and Divide (19 instructions) 401a2b0a27dSPhilippe Mathieu-Daudé * ------------------------------------- 402a2b0a27dSPhilippe Mathieu-Daudé * PMULTW rd, rs, rt Parallel Multiply Word 403a2b0a27dSPhilippe Mathieu-Daudé * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word 404a2b0a27dSPhilippe Mathieu-Daudé * PDIVW rs, rt Parallel Divide Word 405a2b0a27dSPhilippe Mathieu-Daudé * PDIVUW rs, rt Parallel Divide Unsigned Word 406a2b0a27dSPhilippe Mathieu-Daudé * PMADDW rd, rs, rt Parallel Multiply-Add Word 407a2b0a27dSPhilippe Mathieu-Daudé * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word 408a2b0a27dSPhilippe Mathieu-Daudé * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word 409a2b0a27dSPhilippe Mathieu-Daudé * PMULTH rd, rs, rt Parallel Multiply Halfword 410a2b0a27dSPhilippe Mathieu-Daudé * PMADDH rd, rs, rt Parallel Multiply-Add Halfword 411a2b0a27dSPhilippe Mathieu-Daudé * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword 412a2b0a27dSPhilippe Mathieu-Daudé * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword 413a2b0a27dSPhilippe Mathieu-Daudé * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword 414a2b0a27dSPhilippe Mathieu-Daudé * PDIVBW rs, rt Parallel Divide Broadcast Word 415a2b0a27dSPhilippe Mathieu-Daudé * PMFHI rd Parallel Move From HI Register 416a2b0a27dSPhilippe Mathieu-Daudé * PMFLO rd Parallel Move From LO Register 417a2b0a27dSPhilippe Mathieu-Daudé * PMTHI rs Parallel Move To HI Register 418a2b0a27dSPhilippe Mathieu-Daudé * PMTLO rs Parallel Move To LO Register 419a2b0a27dSPhilippe Mathieu-Daudé * PMFHL rd Parallel Move From HI/LO Register 420a2b0a27dSPhilippe Mathieu-Daudé * PMTHL rs Parallel Move To HI/LO Register 421a2b0a27dSPhilippe Mathieu-Daudé */ 422a2b0a27dSPhilippe Mathieu-Daudé 423a2b0a27dSPhilippe Mathieu-Daudé /* 424a2b0a27dSPhilippe Mathieu-Daudé * Pack/Extend (11 instructions) 425a2b0a27dSPhilippe Mathieu-Daudé * ----------------------------- 426a2b0a27dSPhilippe Mathieu-Daudé * PPAC5 rd, rt Parallel Pack to 5 bits 427a2b0a27dSPhilippe Mathieu-Daudé * PPACB rd, rs, rt Parallel Pack to Byte 428a2b0a27dSPhilippe Mathieu-Daudé * PPACH rd, rs, rt Parallel Pack to Halfword 429a2b0a27dSPhilippe Mathieu-Daudé * PPACW rd, rs, rt Parallel Pack to Word 430a2b0a27dSPhilippe Mathieu-Daudé * PEXT5 rd, rt Parallel Extend Upper from 5 bits 431a2b0a27dSPhilippe Mathieu-Daudé * PEXTUB rd, rs, rt Parallel Extend Upper from Byte 432a2b0a27dSPhilippe Mathieu-Daudé * PEXTLB rd, rs, rt Parallel Extend Lower from Byte 433a2b0a27dSPhilippe Mathieu-Daudé * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword 434a2b0a27dSPhilippe Mathieu-Daudé * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword 435a2b0a27dSPhilippe Mathieu-Daudé * PEXTUW rd, rs, rt Parallel Extend Upper from Word 436a2b0a27dSPhilippe Mathieu-Daudé * PEXTLW rd, rs, rt Parallel Extend Lower from Word 437a2b0a27dSPhilippe Mathieu-Daudé */ 438a2b0a27dSPhilippe Mathieu-Daudé 43971c49f39SPhilippe Mathieu-Daudé /* Parallel Pack to Word */ 44071c49f39SPhilippe Mathieu-Daudé static bool trans_PPACW(DisasContext *ctx, arg_rtype *a) 44171c49f39SPhilippe Mathieu-Daudé { 44271c49f39SPhilippe Mathieu-Daudé TCGv_i64 a0, b0, t0; 44371c49f39SPhilippe Mathieu-Daudé 44471c49f39SPhilippe Mathieu-Daudé if (a->rd == 0) { 44571c49f39SPhilippe Mathieu-Daudé /* nop */ 44671c49f39SPhilippe Mathieu-Daudé return true; 44771c49f39SPhilippe Mathieu-Daudé } 44871c49f39SPhilippe Mathieu-Daudé 44971c49f39SPhilippe Mathieu-Daudé a0 = tcg_temp_new_i64(); 45071c49f39SPhilippe Mathieu-Daudé b0 = tcg_temp_new_i64(); 45171c49f39SPhilippe Mathieu-Daudé t0 = tcg_temp_new_i64(); 45271c49f39SPhilippe Mathieu-Daudé 45371c49f39SPhilippe Mathieu-Daudé gen_load_gpr(a0, a->rs); 45471c49f39SPhilippe Mathieu-Daudé gen_load_gpr(b0, a->rt); 45571c49f39SPhilippe Mathieu-Daudé 45671c49f39SPhilippe Mathieu-Daudé gen_load_gpr_hi(t0, a->rt); /* b1 */ 45771c49f39SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32); 45871c49f39SPhilippe Mathieu-Daudé 45971c49f39SPhilippe Mathieu-Daudé gen_load_gpr_hi(t0, a->rs); /* a1 */ 46071c49f39SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32); 46171c49f39SPhilippe Mathieu-Daudé 46271c49f39SPhilippe Mathieu-Daudé tcg_temp_free(t0); 46371c49f39SPhilippe Mathieu-Daudé tcg_temp_free(b0); 46471c49f39SPhilippe Mathieu-Daudé tcg_temp_free(a0); 46571c49f39SPhilippe Mathieu-Daudé 46671c49f39SPhilippe Mathieu-Daudé return true; 46771c49f39SPhilippe Mathieu-Daudé } 46871c49f39SPhilippe Mathieu-Daudé 4690bc69372SPhilippe Mathieu-Daudé static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b) 4700bc69372SPhilippe Mathieu-Daudé { 4710bc69372SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(dl, b, a, 32, 32); 4720bc69372SPhilippe Mathieu-Daudé tcg_gen_shri_i64(b, b, 32); 4730bc69372SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(dh, a, b, 0, 32); 4740bc69372SPhilippe Mathieu-Daudé } 4750bc69372SPhilippe Mathieu-Daudé 476a9ea77f2SPhilippe Mathieu-Daudé static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen) 477a9ea77f2SPhilippe Mathieu-Daudé { 478a9ea77f2SPhilippe Mathieu-Daudé TCGv_i64 ax, bx; 479a9ea77f2SPhilippe Mathieu-Daudé 480a9ea77f2SPhilippe Mathieu-Daudé if (a->rd == 0) { 481a9ea77f2SPhilippe Mathieu-Daudé /* nop */ 482a9ea77f2SPhilippe Mathieu-Daudé return true; 483a9ea77f2SPhilippe Mathieu-Daudé } 484a9ea77f2SPhilippe Mathieu-Daudé 485a9ea77f2SPhilippe Mathieu-Daudé ax = tcg_temp_new_i64(); 486a9ea77f2SPhilippe Mathieu-Daudé bx = tcg_temp_new_i64(); 487a9ea77f2SPhilippe Mathieu-Daudé 488a9ea77f2SPhilippe Mathieu-Daudé gen_load_gpr(ax, a->rs); 489a9ea77f2SPhilippe Mathieu-Daudé gen_load_gpr(bx, a->rt); 490a9ea77f2SPhilippe Mathieu-Daudé 491a9ea77f2SPhilippe Mathieu-Daudé /* Lower half */ 492a9ea77f2SPhilippe Mathieu-Daudé for (int i = 0; i < 64 / (2 * wlen); i++) { 493a9ea77f2SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], 494a9ea77f2SPhilippe Mathieu-Daudé cpu_gpr[a->rd], bx, 2 * wlen * i, wlen); 495a9ea77f2SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], 496a9ea77f2SPhilippe Mathieu-Daudé cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen); 497a9ea77f2SPhilippe Mathieu-Daudé tcg_gen_shri_i64(bx, bx, wlen); 498a9ea77f2SPhilippe Mathieu-Daudé tcg_gen_shri_i64(ax, ax, wlen); 499a9ea77f2SPhilippe Mathieu-Daudé } 500a9ea77f2SPhilippe Mathieu-Daudé /* Upper half */ 501a9ea77f2SPhilippe Mathieu-Daudé for (int i = 0; i < 64 / (2 * wlen); i++) { 502a9ea77f2SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], 503a9ea77f2SPhilippe Mathieu-Daudé cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen); 504a9ea77f2SPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], 505a9ea77f2SPhilippe Mathieu-Daudé cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen); 506a9ea77f2SPhilippe Mathieu-Daudé tcg_gen_shri_i64(bx, bx, wlen); 507a9ea77f2SPhilippe Mathieu-Daudé tcg_gen_shri_i64(ax, ax, wlen); 508a9ea77f2SPhilippe Mathieu-Daudé } 509a9ea77f2SPhilippe Mathieu-Daudé 510a9ea77f2SPhilippe Mathieu-Daudé tcg_temp_free(bx); 511a9ea77f2SPhilippe Mathieu-Daudé tcg_temp_free(ax); 512a9ea77f2SPhilippe Mathieu-Daudé 513a9ea77f2SPhilippe Mathieu-Daudé return true; 514a9ea77f2SPhilippe Mathieu-Daudé } 515a9ea77f2SPhilippe Mathieu-Daudé 516a9ea77f2SPhilippe Mathieu-Daudé /* Parallel Extend Lower from Byte */ 517a9ea77f2SPhilippe Mathieu-Daudé static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a) 518a9ea77f2SPhilippe Mathieu-Daudé { 519a9ea77f2SPhilippe Mathieu-Daudé return trans_PEXTLx(ctx, a, 8); 520a9ea77f2SPhilippe Mathieu-Daudé } 521a9ea77f2SPhilippe Mathieu-Daudé 522a9ea77f2SPhilippe Mathieu-Daudé /* Parallel Extend Lower from Halfword */ 523a9ea77f2SPhilippe Mathieu-Daudé static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a) 524a9ea77f2SPhilippe Mathieu-Daudé { 525a9ea77f2SPhilippe Mathieu-Daudé return trans_PEXTLx(ctx, a, 16); 526a9ea77f2SPhilippe Mathieu-Daudé } 527a9ea77f2SPhilippe Mathieu-Daudé 528a9ea77f2SPhilippe Mathieu-Daudé /* Parallel Extend Lower from Word */ 529a9ea77f2SPhilippe Mathieu-Daudé static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a) 530a9ea77f2SPhilippe Mathieu-Daudé { 531a9ea77f2SPhilippe Mathieu-Daudé TCGv_i64 ax, bx; 532a9ea77f2SPhilippe Mathieu-Daudé 533a9ea77f2SPhilippe Mathieu-Daudé if (a->rd == 0) { 534a9ea77f2SPhilippe Mathieu-Daudé /* nop */ 535a9ea77f2SPhilippe Mathieu-Daudé return true; 536a9ea77f2SPhilippe Mathieu-Daudé } 537a9ea77f2SPhilippe Mathieu-Daudé 538a9ea77f2SPhilippe Mathieu-Daudé ax = tcg_temp_new_i64(); 539a9ea77f2SPhilippe Mathieu-Daudé bx = tcg_temp_new_i64(); 540a9ea77f2SPhilippe Mathieu-Daudé 541a9ea77f2SPhilippe Mathieu-Daudé gen_load_gpr(ax, a->rs); 542a9ea77f2SPhilippe Mathieu-Daudé gen_load_gpr(bx, a->rt); 543a9ea77f2SPhilippe Mathieu-Daudé gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); 544a9ea77f2SPhilippe Mathieu-Daudé 545a9ea77f2SPhilippe Mathieu-Daudé tcg_temp_free(bx); 546a9ea77f2SPhilippe Mathieu-Daudé tcg_temp_free(ax); 547a9ea77f2SPhilippe Mathieu-Daudé 548a9ea77f2SPhilippe Mathieu-Daudé return true; 549a9ea77f2SPhilippe Mathieu-Daudé } 550a9ea77f2SPhilippe Mathieu-Daudé 5510bc69372SPhilippe Mathieu-Daudé /* Parallel Extend Upper from Word */ 5520bc69372SPhilippe Mathieu-Daudé static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a) 5530bc69372SPhilippe Mathieu-Daudé { 5540bc69372SPhilippe Mathieu-Daudé TCGv_i64 ax, bx; 5550bc69372SPhilippe Mathieu-Daudé 5560bc69372SPhilippe Mathieu-Daudé if (a->rd == 0) { 5570bc69372SPhilippe Mathieu-Daudé /* nop */ 5580bc69372SPhilippe Mathieu-Daudé return true; 5590bc69372SPhilippe Mathieu-Daudé } 5600bc69372SPhilippe Mathieu-Daudé 5610bc69372SPhilippe Mathieu-Daudé ax = tcg_temp_new_i64(); 5620bc69372SPhilippe Mathieu-Daudé bx = tcg_temp_new_i64(); 5630bc69372SPhilippe Mathieu-Daudé 5640bc69372SPhilippe Mathieu-Daudé gen_load_gpr_hi(ax, a->rs); 5650bc69372SPhilippe Mathieu-Daudé gen_load_gpr_hi(bx, a->rt); 5660bc69372SPhilippe Mathieu-Daudé gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); 5670bc69372SPhilippe Mathieu-Daudé 5680bc69372SPhilippe Mathieu-Daudé tcg_temp_free(bx); 5690bc69372SPhilippe Mathieu-Daudé tcg_temp_free(ax); 5700bc69372SPhilippe Mathieu-Daudé 5710bc69372SPhilippe Mathieu-Daudé return true; 5720bc69372SPhilippe Mathieu-Daudé } 5730bc69372SPhilippe Mathieu-Daudé 574a2b0a27dSPhilippe Mathieu-Daudé /* 575a2b0a27dSPhilippe Mathieu-Daudé * Others (16 instructions) 576a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 577a2b0a27dSPhilippe Mathieu-Daudé * PCPYH rd, rt Parallel Copy Halfword 578a2b0a27dSPhilippe Mathieu-Daudé * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword 579a2b0a27dSPhilippe Mathieu-Daudé * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword 580a2b0a27dSPhilippe Mathieu-Daudé * PREVH rd, rt Parallel Reverse Halfword 581a2b0a27dSPhilippe Mathieu-Daudé * PINTH rd, rs, rt Parallel Interleave Halfword 582a2b0a27dSPhilippe Mathieu-Daudé * PINTEH rd, rs, rt Parallel Interleave Even Halfword 583a2b0a27dSPhilippe Mathieu-Daudé * PEXEH rd, rt Parallel Exchange Even Halfword 584a2b0a27dSPhilippe Mathieu-Daudé * PEXCH rd, rt Parallel Exchange Center Halfword 585a2b0a27dSPhilippe Mathieu-Daudé * PEXEW rd, rt Parallel Exchange Even Word 586a2b0a27dSPhilippe Mathieu-Daudé * PEXCW rd, rt Parallel Exchange Center Word 587a2b0a27dSPhilippe Mathieu-Daudé * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable 588a2b0a27dSPhilippe Mathieu-Daudé * MFSA rd Move from Shift Amount Register 589a2b0a27dSPhilippe Mathieu-Daudé * MTSA rs Move to Shift Amount Register 590a2b0a27dSPhilippe Mathieu-Daudé * MTSAB rs, immediate Move Byte Count to Shift Amount Register 591a2b0a27dSPhilippe Mathieu-Daudé * MTSAH rs, immediate Move Halfword Count to Shift Amount Register 592a2b0a27dSPhilippe Mathieu-Daudé * PROT3W rd, rt Parallel Rotate 3 Words 593a2b0a27dSPhilippe Mathieu-Daudé */ 594a2b0a27dSPhilippe Mathieu-Daudé 595a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Halfword */ 596a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYH(DisasContext *s, arg_rtype *a) 597a2b0a27dSPhilippe Mathieu-Daudé { 598a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 599a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 600a2b0a27dSPhilippe Mathieu-Daudé return true; 601a2b0a27dSPhilippe Mathieu-Daudé } 602a2b0a27dSPhilippe Mathieu-Daudé 603a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 604a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 605a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 606a2b0a27dSPhilippe Mathieu-Daudé return true; 607a2b0a27dSPhilippe Mathieu-Daudé } 608a2b0a27dSPhilippe Mathieu-Daudé 609a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16); 610a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32); 611a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16); 612a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32); 613a2b0a27dSPhilippe Mathieu-Daudé 614a2b0a27dSPhilippe Mathieu-Daudé return true; 615a2b0a27dSPhilippe Mathieu-Daudé } 616a2b0a27dSPhilippe Mathieu-Daudé 617a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Lower Doubleword */ 618a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) 619a2b0a27dSPhilippe Mathieu-Daudé { 620a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 621a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 622a2b0a27dSPhilippe Mathieu-Daudé return true; 623a2b0a27dSPhilippe Mathieu-Daudé } 624a2b0a27dSPhilippe Mathieu-Daudé 625a2b0a27dSPhilippe Mathieu-Daudé if (a->rs == 0) { 626a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 627a2b0a27dSPhilippe Mathieu-Daudé } else { 628a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]); 629a2b0a27dSPhilippe Mathieu-Daudé } 630a2b0a27dSPhilippe Mathieu-Daudé 631a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 632a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 633a2b0a27dSPhilippe Mathieu-Daudé } else if (a->rd != a->rt) { 634a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); 635a2b0a27dSPhilippe Mathieu-Daudé } 636a2b0a27dSPhilippe Mathieu-Daudé 637a2b0a27dSPhilippe Mathieu-Daudé return true; 638a2b0a27dSPhilippe Mathieu-Daudé } 639a2b0a27dSPhilippe Mathieu-Daudé 640a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Upper Doubleword */ 641a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) 642a2b0a27dSPhilippe Mathieu-Daudé { 643a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 644a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 645a2b0a27dSPhilippe Mathieu-Daudé return true; 646a2b0a27dSPhilippe Mathieu-Daudé } 647a2b0a27dSPhilippe Mathieu-Daudé 648a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr_hi(cpu_gpr[a->rd], a->rs); 649a2b0a27dSPhilippe Mathieu-Daudé 650a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 651a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 652a2b0a27dSPhilippe Mathieu-Daudé } else if (a->rd != a->rt) { 653a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); 654a2b0a27dSPhilippe Mathieu-Daudé } 655a2b0a27dSPhilippe Mathieu-Daudé 656a2b0a27dSPhilippe Mathieu-Daudé return true; 657a2b0a27dSPhilippe Mathieu-Daudé } 658dce4808fSPhilippe Mathieu-Daudé 659dce4808fSPhilippe Mathieu-Daudé /* Parallel Rotate 3 Words Left */ 660dce4808fSPhilippe Mathieu-Daudé static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a) 661dce4808fSPhilippe Mathieu-Daudé { 662dce4808fSPhilippe Mathieu-Daudé TCGv_i64 ax; 663dce4808fSPhilippe Mathieu-Daudé 664dce4808fSPhilippe Mathieu-Daudé if (a->rd == 0) { 665dce4808fSPhilippe Mathieu-Daudé /* nop */ 666dce4808fSPhilippe Mathieu-Daudé return true; 667dce4808fSPhilippe Mathieu-Daudé } 668dce4808fSPhilippe Mathieu-Daudé if (a->rt == 0) { 669dce4808fSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 670dce4808fSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 671dce4808fSPhilippe Mathieu-Daudé return true; 672dce4808fSPhilippe Mathieu-Daudé } 673dce4808fSPhilippe Mathieu-Daudé 674dce4808fSPhilippe Mathieu-Daudé ax = tcg_temp_new_i64(); 675dce4808fSPhilippe Mathieu-Daudé 676dce4808fSPhilippe Mathieu-Daudé tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]); 677dce4808fSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32); 678dce4808fSPhilippe Mathieu-Daudé 679dce4808fSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32); 680dce4808fSPhilippe Mathieu-Daudé tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32); 681dce4808fSPhilippe Mathieu-Daudé 682dce4808fSPhilippe Mathieu-Daudé tcg_temp_free(ax); 683dce4808fSPhilippe Mathieu-Daudé 684dce4808fSPhilippe Mathieu-Daudé return true; 685dce4808fSPhilippe Mathieu-Daudé } 686