1a2b0a27dSPhilippe Mathieu-Daudé /* 2a2b0a27dSPhilippe Mathieu-Daudé * Toshiba TX79-specific instructions translation routines 3a2b0a27dSPhilippe Mathieu-Daudé * 4a2b0a27dSPhilippe Mathieu-Daudé * Copyright (c) 2018 Fredrik Noring 5*2d4ab117SPhilippe Mathieu-Daudé * Copyright (c) 2021 Philippe Mathieu-Daudé 6a2b0a27dSPhilippe Mathieu-Daudé * 7a2b0a27dSPhilippe Mathieu-Daudé * SPDX-License-Identifier: GPL-2.0-or-later 8a2b0a27dSPhilippe Mathieu-Daudé */ 9a2b0a27dSPhilippe Mathieu-Daudé 10a2b0a27dSPhilippe Mathieu-Daudé #include "qemu/osdep.h" 11a2b0a27dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 12a2b0a27dSPhilippe Mathieu-Daudé #include "exec/helper-gen.h" 13a2b0a27dSPhilippe Mathieu-Daudé #include "translate.h" 14a2b0a27dSPhilippe Mathieu-Daudé 15a2b0a27dSPhilippe Mathieu-Daudé /* Include the auto-generated decoder. */ 16a2b0a27dSPhilippe Mathieu-Daudé #include "decode-tx79.c.inc" 17a2b0a27dSPhilippe Mathieu-Daudé 18a2b0a27dSPhilippe Mathieu-Daudé /* 19a2b0a27dSPhilippe Mathieu-Daudé * Overview of the TX79-specific instruction set 20a2b0a27dSPhilippe Mathieu-Daudé * ============================================= 21a2b0a27dSPhilippe Mathieu-Daudé * 22a2b0a27dSPhilippe Mathieu-Daudé * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits 23a2b0a27dSPhilippe Mathieu-Daudé * are only used by the specific quadword (128-bit) LQ/SQ load/store 24a2b0a27dSPhilippe Mathieu-Daudé * instructions and certain multimedia instructions (MMIs). These MMIs 25a2b0a27dSPhilippe Mathieu-Daudé * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit 26a2b0a27dSPhilippe Mathieu-Daudé * or sixteen 8-bit paths. 27a2b0a27dSPhilippe Mathieu-Daudé * 28a2b0a27dSPhilippe Mathieu-Daudé * Reference: 29a2b0a27dSPhilippe Mathieu-Daudé * 30a2b0a27dSPhilippe Mathieu-Daudé * The Toshiba TX System RISC TX79 Core Architecture manual, 31a2b0a27dSPhilippe Mathieu-Daudé * https://wiki.qemu.org/File:C790.pdf 32a2b0a27dSPhilippe Mathieu-Daudé */ 33a2b0a27dSPhilippe Mathieu-Daudé 34a2b0a27dSPhilippe Mathieu-Daudé bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) 35a2b0a27dSPhilippe Mathieu-Daudé { 36a2b0a27dSPhilippe Mathieu-Daudé if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) { 37a2b0a27dSPhilippe Mathieu-Daudé return true; 38a2b0a27dSPhilippe Mathieu-Daudé } 39a2b0a27dSPhilippe Mathieu-Daudé return false; 40a2b0a27dSPhilippe Mathieu-Daudé } 41a2b0a27dSPhilippe Mathieu-Daudé 42a2b0a27dSPhilippe Mathieu-Daudé /* 43a2b0a27dSPhilippe Mathieu-Daudé * Three-Operand Multiply and Multiply-Add (4 instructions) 44a2b0a27dSPhilippe Mathieu-Daudé * -------------------------------------------------------- 45a2b0a27dSPhilippe Mathieu-Daudé * MADD [rd,] rs, rt Multiply/Add 46a2b0a27dSPhilippe Mathieu-Daudé * MADDU [rd,] rs, rt Multiply/Add Unsigned 47a2b0a27dSPhilippe Mathieu-Daudé * MULT [rd,] rs, rt Multiply (3-operand) 48a2b0a27dSPhilippe Mathieu-Daudé * MULTU [rd,] rs, rt Multiply Unsigned (3-operand) 49a2b0a27dSPhilippe Mathieu-Daudé */ 50a2b0a27dSPhilippe Mathieu-Daudé 51a2b0a27dSPhilippe Mathieu-Daudé /* 52a2b0a27dSPhilippe Mathieu-Daudé * Multiply Instructions for Pipeline 1 (10 instructions) 53a2b0a27dSPhilippe Mathieu-Daudé * ------------------------------------------------------ 54a2b0a27dSPhilippe Mathieu-Daudé * MULT1 [rd,] rs, rt Multiply Pipeline 1 55a2b0a27dSPhilippe Mathieu-Daudé * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1 56a2b0a27dSPhilippe Mathieu-Daudé * DIV1 rs, rt Divide Pipeline 1 57a2b0a27dSPhilippe Mathieu-Daudé * DIVU1 rs, rt Divide Unsigned Pipeline 1 58a2b0a27dSPhilippe Mathieu-Daudé * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1 59a2b0a27dSPhilippe Mathieu-Daudé * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1 60a2b0a27dSPhilippe Mathieu-Daudé * MFHI1 rd Move From HI1 Register 61a2b0a27dSPhilippe Mathieu-Daudé * MFLO1 rd Move From LO1 Register 62a2b0a27dSPhilippe Mathieu-Daudé * MTHI1 rs Move To HI1 Register 63a2b0a27dSPhilippe Mathieu-Daudé * MTLO1 rs Move To LO1 Register 64a2b0a27dSPhilippe Mathieu-Daudé */ 65a2b0a27dSPhilippe Mathieu-Daudé 66a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) 67a2b0a27dSPhilippe Mathieu-Daudé { 68a2b0a27dSPhilippe Mathieu-Daudé gen_store_gpr(cpu_HI[1], a->rd); 69a2b0a27dSPhilippe Mathieu-Daudé 70a2b0a27dSPhilippe Mathieu-Daudé return true; 71a2b0a27dSPhilippe Mathieu-Daudé } 72a2b0a27dSPhilippe Mathieu-Daudé 73a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) 74a2b0a27dSPhilippe Mathieu-Daudé { 75a2b0a27dSPhilippe Mathieu-Daudé gen_store_gpr(cpu_LO[1], a->rd); 76a2b0a27dSPhilippe Mathieu-Daudé 77a2b0a27dSPhilippe Mathieu-Daudé return true; 78a2b0a27dSPhilippe Mathieu-Daudé } 79a2b0a27dSPhilippe Mathieu-Daudé 80a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) 81a2b0a27dSPhilippe Mathieu-Daudé { 82a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(cpu_HI[1], a->rs); 83a2b0a27dSPhilippe Mathieu-Daudé 84a2b0a27dSPhilippe Mathieu-Daudé return true; 85a2b0a27dSPhilippe Mathieu-Daudé } 86a2b0a27dSPhilippe Mathieu-Daudé 87a2b0a27dSPhilippe Mathieu-Daudé static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) 88a2b0a27dSPhilippe Mathieu-Daudé { 89a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr(cpu_LO[1], a->rs); 90a2b0a27dSPhilippe Mathieu-Daudé 91a2b0a27dSPhilippe Mathieu-Daudé return true; 92a2b0a27dSPhilippe Mathieu-Daudé } 93a2b0a27dSPhilippe Mathieu-Daudé 94a2b0a27dSPhilippe Mathieu-Daudé /* 95a2b0a27dSPhilippe Mathieu-Daudé * Arithmetic (19 instructions) 96a2b0a27dSPhilippe Mathieu-Daudé * ---------------------------- 97a2b0a27dSPhilippe Mathieu-Daudé * PADDB rd, rs, rt Parallel Add Byte 98a2b0a27dSPhilippe Mathieu-Daudé * PSUBB rd, rs, rt Parallel Subtract Byte 99a2b0a27dSPhilippe Mathieu-Daudé * PADDH rd, rs, rt Parallel Add Halfword 100a2b0a27dSPhilippe Mathieu-Daudé * PSUBH rd, rs, rt Parallel Subtract Halfword 101a2b0a27dSPhilippe Mathieu-Daudé * PADDW rd, rs, rt Parallel Add Word 102a2b0a27dSPhilippe Mathieu-Daudé * PSUBW rd, rs, rt Parallel Subtract Word 103a2b0a27dSPhilippe Mathieu-Daudé * PADSBH rd, rs, rt Parallel Add/Subtract Halfword 104a2b0a27dSPhilippe Mathieu-Daudé * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte 105a2b0a27dSPhilippe Mathieu-Daudé * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte 106a2b0a27dSPhilippe Mathieu-Daudé * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword 107a2b0a27dSPhilippe Mathieu-Daudé * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword 108a2b0a27dSPhilippe Mathieu-Daudé * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word 109a2b0a27dSPhilippe Mathieu-Daudé * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word 110a2b0a27dSPhilippe Mathieu-Daudé * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte 111a2b0a27dSPhilippe Mathieu-Daudé * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte 112a2b0a27dSPhilippe Mathieu-Daudé * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword 113a2b0a27dSPhilippe Mathieu-Daudé * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword 114a2b0a27dSPhilippe Mathieu-Daudé * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word 115a2b0a27dSPhilippe Mathieu-Daudé * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word 116a2b0a27dSPhilippe Mathieu-Daudé */ 117a2b0a27dSPhilippe Mathieu-Daudé 118*2d4ab117SPhilippe Mathieu-Daudé static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a, 119*2d4ab117SPhilippe Mathieu-Daudé void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64)) 120*2d4ab117SPhilippe Mathieu-Daudé { 121*2d4ab117SPhilippe Mathieu-Daudé TCGv_i64 ax, bx; 122*2d4ab117SPhilippe Mathieu-Daudé 123*2d4ab117SPhilippe Mathieu-Daudé if (a->rd == 0) { 124*2d4ab117SPhilippe Mathieu-Daudé /* nop */ 125*2d4ab117SPhilippe Mathieu-Daudé return true; 126*2d4ab117SPhilippe Mathieu-Daudé } 127*2d4ab117SPhilippe Mathieu-Daudé 128*2d4ab117SPhilippe Mathieu-Daudé ax = tcg_temp_new_i64(); 129*2d4ab117SPhilippe Mathieu-Daudé bx = tcg_temp_new_i64(); 130*2d4ab117SPhilippe Mathieu-Daudé 131*2d4ab117SPhilippe Mathieu-Daudé /* Lower half */ 132*2d4ab117SPhilippe Mathieu-Daudé gen_load_gpr(ax, a->rs); 133*2d4ab117SPhilippe Mathieu-Daudé gen_load_gpr(bx, a->rt); 134*2d4ab117SPhilippe Mathieu-Daudé gen_logic_i64(cpu_gpr[a->rd], ax, bx); 135*2d4ab117SPhilippe Mathieu-Daudé 136*2d4ab117SPhilippe Mathieu-Daudé /* Upper half */ 137*2d4ab117SPhilippe Mathieu-Daudé gen_load_gpr_hi(ax, a->rs); 138*2d4ab117SPhilippe Mathieu-Daudé gen_load_gpr_hi(bx, a->rt); 139*2d4ab117SPhilippe Mathieu-Daudé gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); 140*2d4ab117SPhilippe Mathieu-Daudé 141*2d4ab117SPhilippe Mathieu-Daudé tcg_temp_free(bx); 142*2d4ab117SPhilippe Mathieu-Daudé tcg_temp_free(ax); 143*2d4ab117SPhilippe Mathieu-Daudé 144*2d4ab117SPhilippe Mathieu-Daudé return true; 145*2d4ab117SPhilippe Mathieu-Daudé } 146*2d4ab117SPhilippe Mathieu-Daudé 147a2b0a27dSPhilippe Mathieu-Daudé /* 148a2b0a27dSPhilippe Mathieu-Daudé * Min/Max (4 instructions) 149a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 150a2b0a27dSPhilippe Mathieu-Daudé * PMAXH rd, rs, rt Parallel Maximum Halfword 151a2b0a27dSPhilippe Mathieu-Daudé * PMINH rd, rs, rt Parallel Minimum Halfword 152a2b0a27dSPhilippe Mathieu-Daudé * PMAXW rd, rs, rt Parallel Maximum Word 153a2b0a27dSPhilippe Mathieu-Daudé * PMINW rd, rs, rt Parallel Minimum Word 154a2b0a27dSPhilippe Mathieu-Daudé */ 155a2b0a27dSPhilippe Mathieu-Daudé 156a2b0a27dSPhilippe Mathieu-Daudé /* 157a2b0a27dSPhilippe Mathieu-Daudé * Absolute (2 instructions) 158a2b0a27dSPhilippe Mathieu-Daudé * ------------------------- 159a2b0a27dSPhilippe Mathieu-Daudé * PABSH rd, rt Parallel Absolute Halfword 160a2b0a27dSPhilippe Mathieu-Daudé * PABSW rd, rt Parallel Absolute Word 161a2b0a27dSPhilippe Mathieu-Daudé */ 162a2b0a27dSPhilippe Mathieu-Daudé 163a2b0a27dSPhilippe Mathieu-Daudé /* 164a2b0a27dSPhilippe Mathieu-Daudé * Logical (4 instructions) 165a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 166a2b0a27dSPhilippe Mathieu-Daudé * PAND rd, rs, rt Parallel AND 167a2b0a27dSPhilippe Mathieu-Daudé * POR rd, rs, rt Parallel OR 168a2b0a27dSPhilippe Mathieu-Daudé * PXOR rd, rs, rt Parallel XOR 169a2b0a27dSPhilippe Mathieu-Daudé * PNOR rd, rs, rt Parallel NOR 170a2b0a27dSPhilippe Mathieu-Daudé */ 171a2b0a27dSPhilippe Mathieu-Daudé 172*2d4ab117SPhilippe Mathieu-Daudé /* Parallel And */ 173*2d4ab117SPhilippe Mathieu-Daudé static bool trans_PAND(DisasContext *ctx, arg_rtype *a) 174*2d4ab117SPhilippe Mathieu-Daudé { 175*2d4ab117SPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_and_i64); 176*2d4ab117SPhilippe Mathieu-Daudé } 177*2d4ab117SPhilippe Mathieu-Daudé 178*2d4ab117SPhilippe Mathieu-Daudé /* Parallel Or */ 179*2d4ab117SPhilippe Mathieu-Daudé static bool trans_POR(DisasContext *ctx, arg_rtype *a) 180*2d4ab117SPhilippe Mathieu-Daudé { 181*2d4ab117SPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_or_i64); 182*2d4ab117SPhilippe Mathieu-Daudé } 183*2d4ab117SPhilippe Mathieu-Daudé 184*2d4ab117SPhilippe Mathieu-Daudé /* Parallel Exclusive Or */ 185*2d4ab117SPhilippe Mathieu-Daudé static bool trans_PXOR(DisasContext *ctx, arg_rtype *a) 186*2d4ab117SPhilippe Mathieu-Daudé { 187*2d4ab117SPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_xor_i64); 188*2d4ab117SPhilippe Mathieu-Daudé } 189*2d4ab117SPhilippe Mathieu-Daudé 190*2d4ab117SPhilippe Mathieu-Daudé /* Parallel Not Or */ 191*2d4ab117SPhilippe Mathieu-Daudé static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) 192*2d4ab117SPhilippe Mathieu-Daudé { 193*2d4ab117SPhilippe Mathieu-Daudé return trans_parallel_arith(ctx, a, tcg_gen_nor_i64); 194*2d4ab117SPhilippe Mathieu-Daudé } 195*2d4ab117SPhilippe Mathieu-Daudé 196a2b0a27dSPhilippe Mathieu-Daudé /* 197a2b0a27dSPhilippe Mathieu-Daudé * Shift (9 instructions) 198a2b0a27dSPhilippe Mathieu-Daudé * ---------------------- 199a2b0a27dSPhilippe Mathieu-Daudé * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword 200a2b0a27dSPhilippe Mathieu-Daudé * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword 201a2b0a27dSPhilippe Mathieu-Daudé * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword 202a2b0a27dSPhilippe Mathieu-Daudé * PSLLW rd, rt, sa Parallel Shift Left Logical Word 203a2b0a27dSPhilippe Mathieu-Daudé * PSRLW rd, rt, sa Parallel Shift Right Logical Word 204a2b0a27dSPhilippe Mathieu-Daudé * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word 205a2b0a27dSPhilippe Mathieu-Daudé * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word 206a2b0a27dSPhilippe Mathieu-Daudé * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word 207a2b0a27dSPhilippe Mathieu-Daudé * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word 208a2b0a27dSPhilippe Mathieu-Daudé */ 209a2b0a27dSPhilippe Mathieu-Daudé 210a2b0a27dSPhilippe Mathieu-Daudé /* 211a2b0a27dSPhilippe Mathieu-Daudé * Compare (6 instructions) 212a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 213a2b0a27dSPhilippe Mathieu-Daudé * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte 214a2b0a27dSPhilippe Mathieu-Daudé * PCEQB rd, rs, rt Parallel Compare for Equal Byte 215a2b0a27dSPhilippe Mathieu-Daudé * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword 216a2b0a27dSPhilippe Mathieu-Daudé * PCEQH rd, rs, rt Parallel Compare for Equal Halfword 217a2b0a27dSPhilippe Mathieu-Daudé * PCGTW rd, rs, rt Parallel Compare for Greater Than Word 218a2b0a27dSPhilippe Mathieu-Daudé * PCEQW rd, rs, rt Parallel Compare for Equal Word 219a2b0a27dSPhilippe Mathieu-Daudé */ 220a2b0a27dSPhilippe Mathieu-Daudé 221a2b0a27dSPhilippe Mathieu-Daudé /* 222a2b0a27dSPhilippe Mathieu-Daudé * LZC (1 instruction) 223a2b0a27dSPhilippe Mathieu-Daudé * ------------------- 224a2b0a27dSPhilippe Mathieu-Daudé * PLZCW rd, rs Parallel Leading Zero or One Count Word 225a2b0a27dSPhilippe Mathieu-Daudé */ 226a2b0a27dSPhilippe Mathieu-Daudé 227a2b0a27dSPhilippe Mathieu-Daudé /* 228a2b0a27dSPhilippe Mathieu-Daudé * Quadword Load and Store (2 instructions) 229a2b0a27dSPhilippe Mathieu-Daudé * ---------------------------------------- 230a2b0a27dSPhilippe Mathieu-Daudé * LQ rt, offset(base) Load Quadword 231a2b0a27dSPhilippe Mathieu-Daudé * SQ rt, offset(base) Store Quadword 232a2b0a27dSPhilippe Mathieu-Daudé */ 233a2b0a27dSPhilippe Mathieu-Daudé 234a2b0a27dSPhilippe Mathieu-Daudé /* 235a2b0a27dSPhilippe Mathieu-Daudé * Multiply and Divide (19 instructions) 236a2b0a27dSPhilippe Mathieu-Daudé * ------------------------------------- 237a2b0a27dSPhilippe Mathieu-Daudé * PMULTW rd, rs, rt Parallel Multiply Word 238a2b0a27dSPhilippe Mathieu-Daudé * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word 239a2b0a27dSPhilippe Mathieu-Daudé * PDIVW rs, rt Parallel Divide Word 240a2b0a27dSPhilippe Mathieu-Daudé * PDIVUW rs, rt Parallel Divide Unsigned Word 241a2b0a27dSPhilippe Mathieu-Daudé * PMADDW rd, rs, rt Parallel Multiply-Add Word 242a2b0a27dSPhilippe Mathieu-Daudé * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word 243a2b0a27dSPhilippe Mathieu-Daudé * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word 244a2b0a27dSPhilippe Mathieu-Daudé * PMULTH rd, rs, rt Parallel Multiply Halfword 245a2b0a27dSPhilippe Mathieu-Daudé * PMADDH rd, rs, rt Parallel Multiply-Add Halfword 246a2b0a27dSPhilippe Mathieu-Daudé * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword 247a2b0a27dSPhilippe Mathieu-Daudé * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword 248a2b0a27dSPhilippe Mathieu-Daudé * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword 249a2b0a27dSPhilippe Mathieu-Daudé * PDIVBW rs, rt Parallel Divide Broadcast Word 250a2b0a27dSPhilippe Mathieu-Daudé * PMFHI rd Parallel Move From HI Register 251a2b0a27dSPhilippe Mathieu-Daudé * PMFLO rd Parallel Move From LO Register 252a2b0a27dSPhilippe Mathieu-Daudé * PMTHI rs Parallel Move To HI Register 253a2b0a27dSPhilippe Mathieu-Daudé * PMTLO rs Parallel Move To LO Register 254a2b0a27dSPhilippe Mathieu-Daudé * PMFHL rd Parallel Move From HI/LO Register 255a2b0a27dSPhilippe Mathieu-Daudé * PMTHL rs Parallel Move To HI/LO Register 256a2b0a27dSPhilippe Mathieu-Daudé */ 257a2b0a27dSPhilippe Mathieu-Daudé 258a2b0a27dSPhilippe Mathieu-Daudé /* 259a2b0a27dSPhilippe Mathieu-Daudé * Pack/Extend (11 instructions) 260a2b0a27dSPhilippe Mathieu-Daudé * ----------------------------- 261a2b0a27dSPhilippe Mathieu-Daudé * PPAC5 rd, rt Parallel Pack to 5 bits 262a2b0a27dSPhilippe Mathieu-Daudé * PPACB rd, rs, rt Parallel Pack to Byte 263a2b0a27dSPhilippe Mathieu-Daudé * PPACH rd, rs, rt Parallel Pack to Halfword 264a2b0a27dSPhilippe Mathieu-Daudé * PPACW rd, rs, rt Parallel Pack to Word 265a2b0a27dSPhilippe Mathieu-Daudé * PEXT5 rd, rt Parallel Extend Upper from 5 bits 266a2b0a27dSPhilippe Mathieu-Daudé * PEXTUB rd, rs, rt Parallel Extend Upper from Byte 267a2b0a27dSPhilippe Mathieu-Daudé * PEXTLB rd, rs, rt Parallel Extend Lower from Byte 268a2b0a27dSPhilippe Mathieu-Daudé * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword 269a2b0a27dSPhilippe Mathieu-Daudé * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword 270a2b0a27dSPhilippe Mathieu-Daudé * PEXTUW rd, rs, rt Parallel Extend Upper from Word 271a2b0a27dSPhilippe Mathieu-Daudé * PEXTLW rd, rs, rt Parallel Extend Lower from Word 272a2b0a27dSPhilippe Mathieu-Daudé */ 273a2b0a27dSPhilippe Mathieu-Daudé 274a2b0a27dSPhilippe Mathieu-Daudé /* 275a2b0a27dSPhilippe Mathieu-Daudé * Others (16 instructions) 276a2b0a27dSPhilippe Mathieu-Daudé * ------------------------ 277a2b0a27dSPhilippe Mathieu-Daudé * PCPYH rd, rt Parallel Copy Halfword 278a2b0a27dSPhilippe Mathieu-Daudé * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword 279a2b0a27dSPhilippe Mathieu-Daudé * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword 280a2b0a27dSPhilippe Mathieu-Daudé * PREVH rd, rt Parallel Reverse Halfword 281a2b0a27dSPhilippe Mathieu-Daudé * PINTH rd, rs, rt Parallel Interleave Halfword 282a2b0a27dSPhilippe Mathieu-Daudé * PINTEH rd, rs, rt Parallel Interleave Even Halfword 283a2b0a27dSPhilippe Mathieu-Daudé * PEXEH rd, rt Parallel Exchange Even Halfword 284a2b0a27dSPhilippe Mathieu-Daudé * PEXCH rd, rt Parallel Exchange Center Halfword 285a2b0a27dSPhilippe Mathieu-Daudé * PEXEW rd, rt Parallel Exchange Even Word 286a2b0a27dSPhilippe Mathieu-Daudé * PEXCW rd, rt Parallel Exchange Center Word 287a2b0a27dSPhilippe Mathieu-Daudé * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable 288a2b0a27dSPhilippe Mathieu-Daudé * MFSA rd Move from Shift Amount Register 289a2b0a27dSPhilippe Mathieu-Daudé * MTSA rs Move to Shift Amount Register 290a2b0a27dSPhilippe Mathieu-Daudé * MTSAB rs, immediate Move Byte Count to Shift Amount Register 291a2b0a27dSPhilippe Mathieu-Daudé * MTSAH rs, immediate Move Halfword Count to Shift Amount Register 292a2b0a27dSPhilippe Mathieu-Daudé * PROT3W rd, rt Parallel Rotate 3 Words 293a2b0a27dSPhilippe Mathieu-Daudé */ 294a2b0a27dSPhilippe Mathieu-Daudé 295a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Halfword */ 296a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYH(DisasContext *s, arg_rtype *a) 297a2b0a27dSPhilippe Mathieu-Daudé { 298a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 299a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 300a2b0a27dSPhilippe Mathieu-Daudé return true; 301a2b0a27dSPhilippe Mathieu-Daudé } 302a2b0a27dSPhilippe Mathieu-Daudé 303a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 304a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 305a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 306a2b0a27dSPhilippe Mathieu-Daudé return true; 307a2b0a27dSPhilippe Mathieu-Daudé } 308a2b0a27dSPhilippe Mathieu-Daudé 309a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16); 310a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32); 311a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16); 312a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32); 313a2b0a27dSPhilippe Mathieu-Daudé 314a2b0a27dSPhilippe Mathieu-Daudé return true; 315a2b0a27dSPhilippe Mathieu-Daudé } 316a2b0a27dSPhilippe Mathieu-Daudé 317a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Lower Doubleword */ 318a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) 319a2b0a27dSPhilippe Mathieu-Daudé { 320a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 321a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 322a2b0a27dSPhilippe Mathieu-Daudé return true; 323a2b0a27dSPhilippe Mathieu-Daudé } 324a2b0a27dSPhilippe Mathieu-Daudé 325a2b0a27dSPhilippe Mathieu-Daudé if (a->rs == 0) { 326a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 327a2b0a27dSPhilippe Mathieu-Daudé } else { 328a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]); 329a2b0a27dSPhilippe Mathieu-Daudé } 330a2b0a27dSPhilippe Mathieu-Daudé 331a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 332a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr[a->rd], 0); 333a2b0a27dSPhilippe Mathieu-Daudé } else if (a->rd != a->rt) { 334a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); 335a2b0a27dSPhilippe Mathieu-Daudé } 336a2b0a27dSPhilippe Mathieu-Daudé 337a2b0a27dSPhilippe Mathieu-Daudé return true; 338a2b0a27dSPhilippe Mathieu-Daudé } 339a2b0a27dSPhilippe Mathieu-Daudé 340a2b0a27dSPhilippe Mathieu-Daudé /* Parallel Copy Upper Doubleword */ 341a2b0a27dSPhilippe Mathieu-Daudé static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) 342a2b0a27dSPhilippe Mathieu-Daudé { 343a2b0a27dSPhilippe Mathieu-Daudé if (a->rd == 0) { 344a2b0a27dSPhilippe Mathieu-Daudé /* nop */ 345a2b0a27dSPhilippe Mathieu-Daudé return true; 346a2b0a27dSPhilippe Mathieu-Daudé } 347a2b0a27dSPhilippe Mathieu-Daudé 348a2b0a27dSPhilippe Mathieu-Daudé gen_load_gpr_hi(cpu_gpr[a->rd], a->rs); 349a2b0a27dSPhilippe Mathieu-Daudé 350a2b0a27dSPhilippe Mathieu-Daudé if (a->rt == 0) { 351a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); 352a2b0a27dSPhilippe Mathieu-Daudé } else if (a->rd != a->rt) { 353a2b0a27dSPhilippe Mathieu-Daudé tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); 354a2b0a27dSPhilippe Mathieu-Daudé } 355a2b0a27dSPhilippe Mathieu-Daudé 356a2b0a27dSPhilippe Mathieu-Daudé return true; 357a2b0a27dSPhilippe Mathieu-Daudé } 358