1 /* 2 * MIPS SIMD Architecture (MSA) translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * SPDX-License-Identifier: LGPL-2.1-or-later 12 */ 13 #include "qemu/osdep.h" 14 #include "tcg/tcg-op.h" 15 #include "exec/helper-gen.h" 16 #include "translate.h" 17 #include "fpu_helper.h" 18 #include "internal.h" 19 20 static int elm_n(DisasContext *ctx, int x); 21 static int elm_df(DisasContext *ctx, int x); 22 static int bit_m(DisasContext *ctx, int x); 23 static int bit_df(DisasContext *ctx, int x); 24 25 static inline int plus_1(DisasContext *s, int x) 26 { 27 return x + 1; 28 } 29 30 static inline int plus_2(DisasContext *s, int x) 31 { 32 return x + 2; 33 } 34 35 /* Include the auto-generated decoder. */ 36 #include "decode-msa.c.inc" 37 38 static const char msaregnames[][6] = { 39 "w0.d0", "w0.d1", "w1.d0", "w1.d1", 40 "w2.d0", "w2.d1", "w3.d0", "w3.d1", 41 "w4.d0", "w4.d1", "w5.d0", "w5.d1", 42 "w6.d0", "w6.d1", "w7.d0", "w7.d1", 43 "w8.d0", "w8.d1", "w9.d0", "w9.d1", 44 "w10.d0", "w10.d1", "w11.d0", "w11.d1", 45 "w12.d0", "w12.d1", "w13.d0", "w13.d1", 46 "w14.d0", "w14.d1", "w15.d0", "w15.d1", 47 "w16.d0", "w16.d1", "w17.d0", "w17.d1", 48 "w18.d0", "w18.d1", "w19.d0", "w19.d1", 49 "w20.d0", "w20.d1", "w21.d0", "w21.d1", 50 "w22.d0", "w22.d1", "w23.d0", "w23.d1", 51 "w24.d0", "w24.d1", "w25.d0", "w25.d1", 52 "w26.d0", "w26.d1", "w27.d0", "w27.d1", 53 "w28.d0", "w28.d1", "w29.d0", "w29.d1", 54 "w30.d0", "w30.d1", "w31.d0", "w31.d1", 55 }; 56 57 /* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */ 58 struct dfe { 59 int start; 60 int length; 61 uint32_t mask; 62 }; 63 64 /* 65 * Extract immediate from df/{m,n} format (used by ELM & BIT instructions). 66 * Returns the immediate value, or -1 if the format does not match. 67 */ 68 static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s) 69 { 70 for (unsigned i = 0; i < 4; i++) { 71 if (extract32(x, s[i].start, s[i].length) == s[i].mask) { 72 return extract32(x, 0, s[i].start); 73 } 74 } 75 return -1; 76 } 77 78 /* 79 * Extract DataField from df/{m,n} format (used by ELM & BIT instructions). 80 * Returns the DataField, or -1 if the format does not match. 81 */ 82 static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s) 83 { 84 for (unsigned i = 0; i < 4; i++) { 85 if (extract32(x, s[i].start, s[i].length) == s[i].mask) { 86 return i; 87 } 88 } 89 return -1; 90 } 91 92 static const struct dfe df_elm[] = { 93 /* Table 3.26 ELM Instruction Format */ 94 [DF_BYTE] = {4, 2, 0b00}, 95 [DF_HALF] = {3, 3, 0b100}, 96 [DF_WORD] = {2, 4, 0b1100}, 97 [DF_DOUBLE] = {1, 5, 0b11100} 98 }; 99 100 static int elm_n(DisasContext *ctx, int x) 101 { 102 return df_extract_val(ctx, x, df_elm); 103 } 104 105 static int elm_df(DisasContext *ctx, int x) 106 { 107 return df_extract_df(ctx, x, df_elm); 108 } 109 110 static const struct dfe df_bit[] = { 111 /* Table 3.28 BIT Instruction Format */ 112 [DF_BYTE] = {3, 4, 0b1110}, 113 [DF_HALF] = {4, 3, 0b110}, 114 [DF_WORD] = {5, 2, 0b10}, 115 [DF_DOUBLE] = {6, 1, 0b0} 116 }; 117 118 static int bit_m(DisasContext *ctx, int x) 119 { 120 return df_extract_val(ctx, x, df_bit); 121 } 122 123 static int bit_df(DisasContext *ctx, int x) 124 { 125 return df_extract_df(ctx, x, df_bit); 126 } 127 128 static TCGv_i64 msa_wr_d[64]; 129 130 void msa_translate_init(void) 131 { 132 int i; 133 134 for (i = 0; i < 32; i++) { 135 int off; 136 137 /* 138 * The MSA vector registers are mapped on the 139 * scalar floating-point unit (FPU) registers. 140 */ 141 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 142 msa_wr_d[i * 2] = fpu_f64[i]; 143 144 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); 145 msa_wr_d[i * 2 + 1] = 146 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); 147 } 148 } 149 150 /* 151 * Check if MSA is enabled. 152 * This function is always called with MSA available. 153 * If MSA is disabled, raise an exception. 154 */ 155 static inline bool check_msa_enabled(DisasContext *ctx) 156 { 157 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && 158 !(ctx->hflags & MIPS_HFLAG_F64))) { 159 gen_reserved_instruction(ctx); 160 return false; 161 } 162 163 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { 164 generate_exception_end(ctx, EXCP_MSADIS); 165 return false; 166 } 167 return true; 168 } 169 170 typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); 171 typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32); 172 typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 173 typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); 174 175 #define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \ 176 static gen_helper_p##TYPE * const NAME##_tab[4] = { \ 177 gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \ 178 }; \ 179 TRANS(NAME, trans_func, NAME##_tab[a->df]) 180 181 #define TRANS_DF_iv(NAME, trans_func, gen_func) \ 182 TRANS_DF_x(iv, NAME, trans_func, gen_func) 183 184 #define TRANS_DF_ii(NAME, trans_func, gen_func) \ 185 TRANS_DF_x(ii, NAME, trans_func, gen_func) 186 187 #define TRANS_DF_iii(NAME, trans_func, gen_func) \ 188 TRANS_DF_x(iii, NAME, trans_func, gen_func) 189 190 #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ 191 static gen_helper_piii * const NAME##_tab[4] = { \ 192 NULL, gen_func##_h, gen_func##_w, gen_func##_d \ 193 }; \ 194 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 195 { \ 196 return trans_func(ctx, a, NAME##_tab[a->df]); \ 197 } 198 199 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, 200 TCGCond cond) 201 { 202 /* generates tcg ops to check if any element is 0 */ 203 /* Note this function only works with MSA_WRLEN = 128 */ 204 uint64_t eval_zero_or_big = dup_const(df, 1); 205 uint64_t eval_big = eval_zero_or_big << ((8 << df) - 1); 206 TCGv_i64 t0 = tcg_temp_new_i64(); 207 TCGv_i64 t1 = tcg_temp_new_i64(); 208 209 tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); 210 tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); 211 tcg_gen_andi_i64(t0, t0, eval_big); 212 tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); 213 tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); 214 tcg_gen_andi_i64(t1, t1, eval_big); 215 tcg_gen_or_i64(t0, t0, t1); 216 /* if all bits are zero then all elements are not zero */ 217 /* if some bit is non-zero then some element is zero */ 218 tcg_gen_setcondi_i64(cond, t0, t0, 0); 219 tcg_gen_trunc_i64_tl(tresult, t0); 220 } 221 222 static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) 223 { 224 TCGv_i64 t0; 225 226 if (!check_msa_enabled(ctx)) { 227 return true; 228 } 229 230 if (ctx->hflags & MIPS_HFLAG_BMASK) { 231 gen_reserved_instruction(ctx); 232 return true; 233 } 234 t0 = tcg_temp_new_i64(); 235 tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); 236 tcg_gen_setcondi_i64(cond, t0, t0, 0); 237 tcg_gen_trunc_i64_tl(bcond, t0); 238 239 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 240 241 ctx->hflags |= MIPS_HFLAG_BC; 242 ctx->hflags |= MIPS_HFLAG_BDS32; 243 244 return true; 245 } 246 247 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) 248 { 249 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ); 250 } 251 252 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) 253 { 254 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE); 255 } 256 257 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not) 258 { 259 if (!check_msa_enabled(ctx)) { 260 return true; 261 } 262 263 if (ctx->hflags & MIPS_HFLAG_BMASK) { 264 gen_reserved_instruction(ctx); 265 return true; 266 } 267 268 gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE); 269 270 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 271 ctx->hflags |= MIPS_HFLAG_BC; 272 ctx->hflags |= MIPS_HFLAG_BDS32; 273 274 return true; 275 } 276 277 static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a) 278 { 279 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false); 280 } 281 282 static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a) 283 { 284 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); 285 } 286 287 static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a, 288 gen_helper_piii *gen_msa_i8) 289 { 290 if (!check_msa_enabled(ctx)) { 291 return true; 292 } 293 294 gen_msa_i8(cpu_env, 295 tcg_constant_i32(a->wd), 296 tcg_constant_i32(a->ws), 297 tcg_constant_i32(a->sa)); 298 299 return true; 300 } 301 302 TRANS(ANDI, trans_msa_i8, gen_helper_msa_andi_b); 303 TRANS(ORI, trans_msa_i8, gen_helper_msa_ori_b); 304 TRANS(NORI, trans_msa_i8, gen_helper_msa_nori_b); 305 TRANS(XORI, trans_msa_i8, gen_helper_msa_xori_b); 306 TRANS(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b); 307 TRANS(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b); 308 TRANS(BSELI, trans_msa_i8, gen_helper_msa_bseli_b); 309 310 static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) 311 { 312 if (a->df == DF_DOUBLE) { 313 return false; 314 } 315 316 if (!check_msa_enabled(ctx)) { 317 return true; 318 } 319 320 gen_helper_msa_shf_df(cpu_env, 321 tcg_constant_i32(a->df), 322 tcg_constant_i32(a->wd), 323 tcg_constant_i32(a->ws), 324 tcg_constant_i32(a->sa)); 325 326 return true; 327 } 328 329 static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, 330 gen_helper_piiii *gen_msa_i5) 331 { 332 if (!check_msa_enabled(ctx)) { 333 return true; 334 } 335 336 gen_msa_i5(cpu_env, 337 tcg_constant_i32(a->df), 338 tcg_constant_i32(a->wd), 339 tcg_constant_i32(a->ws), 340 tcg_constant_i32(a->sa)); 341 342 return true; 343 } 344 345 TRANS(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df); 346 TRANS(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df); 347 TRANS(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df); 348 TRANS(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df); 349 TRANS(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df); 350 TRANS(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df); 351 TRANS(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df); 352 TRANS(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df); 353 TRANS(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df); 354 TRANS(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df); 355 TRANS(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df); 356 357 static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) 358 { 359 if (!check_msa_enabled(ctx)) { 360 return true; 361 } 362 363 gen_helper_msa_ldi_df(cpu_env, 364 tcg_constant_i32(a->df), 365 tcg_constant_i32(a->wd), 366 tcg_constant_i32(a->sa)); 367 368 return true; 369 } 370 371 static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a, 372 gen_helper_piiii *gen_msa_bit) 373 { 374 if (a->df < 0) { 375 return false; 376 } 377 378 if (!check_msa_enabled(ctx)) { 379 return true; 380 } 381 382 gen_msa_bit(cpu_env, 383 tcg_constant_i32(a->df), 384 tcg_constant_i32(a->wd), 385 tcg_constant_i32(a->ws), 386 tcg_constant_i32(a->m)); 387 388 return true; 389 } 390 391 TRANS(SLLI, trans_msa_bit, gen_helper_msa_slli_df); 392 TRANS(SRAI, trans_msa_bit, gen_helper_msa_srai_df); 393 TRANS(SRLI, trans_msa_bit, gen_helper_msa_srli_df); 394 TRANS(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df); 395 TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df); 396 TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df); 397 TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df); 398 TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df); 399 TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_s_df); 400 TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); 401 TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); 402 TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); 403 404 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, 405 gen_helper_piiii *gen_msa_3rf) 406 { 407 if (!check_msa_enabled(ctx)) { 408 return true; 409 } 410 411 gen_msa_3rf(cpu_env, 412 tcg_constant_i32(a->df), 413 tcg_constant_i32(a->wd), 414 tcg_constant_i32(a->ws), 415 tcg_constant_i32(a->wt)); 416 417 return true; 418 } 419 420 static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, 421 gen_helper_piii *gen_msa_3r) 422 { 423 if (!gen_msa_3r) { 424 return false; 425 } 426 427 if (!check_msa_enabled(ctx)) { 428 return true; 429 } 430 431 gen_msa_3r(cpu_env, 432 tcg_constant_i32(a->wd), 433 tcg_constant_i32(a->ws), 434 tcg_constant_i32(a->wt)); 435 436 return true; 437 } 438 439 TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v); 440 TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v); 441 TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v); 442 TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v); 443 TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); 444 TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); 445 TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); 446 447 TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll); 448 TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra); 449 TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl); 450 TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr); 451 TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset); 452 TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg); 453 TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); 454 TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); 455 456 TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv); 457 TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv); 458 TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s); 459 TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u); 460 TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s); 461 TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u); 462 TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a); 463 TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a); 464 465 TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq); 466 TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s); 467 TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u); 468 TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s); 469 TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u); 470 471 TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a); 472 TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a); 473 TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s); 474 TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u); 475 TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s); 476 TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u); 477 TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s); 478 TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u); 479 480 TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s); 481 TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u); 482 TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u); 483 TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s); 484 TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s); 485 TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u); 486 487 TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv); 488 TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv); 489 TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv); 490 TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s); 491 TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u); 492 TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s); 493 TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u); 494 495 TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); 496 TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); 497 TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); 498 TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u); 499 TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s); 500 TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); 501 502 TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); 503 TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); 504 TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev); 505 TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod); 506 TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl); 507 TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr); 508 TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev); 509 TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod); 510 511 TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); 512 TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar); 513 TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr); 514 TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); 515 TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); 516 TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); 517 TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); 518 519 static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a) 520 { 521 if (!check_msa_enabled(ctx)) { 522 return true; 523 } 524 525 gen_helper_msa_move_v(cpu_env, 526 tcg_constant_i32(a->wd), 527 tcg_constant_i32(a->ws)); 528 529 return true; 530 } 531 532 static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a) 533 { 534 TCGv telm; 535 536 if (!check_msa_enabled(ctx)) { 537 return true; 538 } 539 540 telm = tcg_temp_new(); 541 542 gen_load_gpr(telm, a->ws); 543 gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd)); 544 545 return true; 546 } 547 548 static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a) 549 { 550 TCGv telm; 551 552 if (!check_msa_enabled(ctx)) { 553 return true; 554 } 555 556 telm = tcg_temp_new(); 557 558 gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); 559 gen_store_gpr(telm, a->wd); 560 561 return true; 562 } 563 564 static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, 565 gen_helper_piiii *gen_msa_elm_df) 566 { 567 if (a->df < 0) { 568 return false; 569 } 570 571 if (!check_msa_enabled(ctx)) { 572 return true; 573 } 574 575 gen_msa_elm_df(cpu_env, 576 tcg_constant_i32(a->df), 577 tcg_constant_i32(a->wd), 578 tcg_constant_i32(a->ws), 579 tcg_constant_i32(a->n)); 580 581 return true; 582 } 583 584 TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); 585 TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); 586 TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); 587 588 static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a, 589 gen_helper_piii * const gen_msa_elm[4]) 590 { 591 if (a->df < 0 || !gen_msa_elm[a->df]) { 592 return false; 593 } 594 595 if (!check_msa_enabled(ctx)) { 596 return true; 597 } 598 599 gen_msa_elm[a->df](cpu_env, 600 tcg_constant_i32(a->wd), 601 tcg_constant_i32(a->ws), 602 tcg_constant_i32(a->n)); 603 604 return true; 605 } 606 607 #if defined(TARGET_MIPS64) 608 #define NULL_IF_MIPS32(function) function 609 #else 610 #define NULL_IF_MIPS32(function) NULL 611 #endif 612 613 static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a) 614 { 615 if (a->wd == 0) { 616 /* Treat as NOP. */ 617 return true; 618 } 619 620 static gen_helper_piii * const gen_msa_copy_u[4] = { 621 gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h, 622 NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL 623 }; 624 625 return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); 626 } 627 628 static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a) 629 { 630 if (a->wd == 0) { 631 /* Treat as NOP. */ 632 return true; 633 } 634 635 static gen_helper_piii * const gen_msa_copy_s[4] = { 636 gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h, 637 gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d) 638 }; 639 640 return trans_msa_elm_fn(ctx, a, gen_msa_copy_s); 641 } 642 643 static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a) 644 { 645 static gen_helper_piii * const gen_msa_insert[4] = { 646 gen_helper_msa_insert_b, gen_helper_msa_insert_h, 647 gen_helper_msa_insert_w, NULL_IF_MIPS32(gen_helper_msa_insert_d) 648 }; 649 650 return trans_msa_elm_fn(ctx, a, gen_msa_insert); 651 } 652 653 TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); 654 TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); 655 TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); 656 TRANS(FCUEQ, trans_msa_3rf, gen_helper_msa_fcueq_df); 657 TRANS(FCLT, trans_msa_3rf, gen_helper_msa_fclt_df); 658 TRANS(FCULT, trans_msa_3rf, gen_helper_msa_fcult_df); 659 TRANS(FCLE, trans_msa_3rf, gen_helper_msa_fcle_df); 660 TRANS(FCULE, trans_msa_3rf, gen_helper_msa_fcule_df); 661 TRANS(FSAF, trans_msa_3rf, gen_helper_msa_fsaf_df); 662 TRANS(FSUN, trans_msa_3rf, gen_helper_msa_fsun_df); 663 TRANS(FSEQ, trans_msa_3rf, gen_helper_msa_fseq_df); 664 TRANS(FSUEQ, trans_msa_3rf, gen_helper_msa_fsueq_df); 665 TRANS(FSLT, trans_msa_3rf, gen_helper_msa_fslt_df); 666 TRANS(FSULT, trans_msa_3rf, gen_helper_msa_fsult_df); 667 TRANS(FSLE, trans_msa_3rf, gen_helper_msa_fsle_df); 668 TRANS(FSULE, trans_msa_3rf, gen_helper_msa_fsule_df); 669 670 TRANS(FADD, trans_msa_3rf, gen_helper_msa_fadd_df); 671 TRANS(FSUB, trans_msa_3rf, gen_helper_msa_fsub_df); 672 TRANS(FMUL, trans_msa_3rf, gen_helper_msa_fmul_df); 673 TRANS(FDIV, trans_msa_3rf, gen_helper_msa_fdiv_df); 674 TRANS(FMADD, trans_msa_3rf, gen_helper_msa_fmadd_df); 675 TRANS(FMSUB, trans_msa_3rf, gen_helper_msa_fmsub_df); 676 TRANS(FEXP2, trans_msa_3rf, gen_helper_msa_fexp2_df); 677 TRANS(FEXDO, trans_msa_3rf, gen_helper_msa_fexdo_df); 678 TRANS(FTQ, trans_msa_3rf, gen_helper_msa_ftq_df); 679 TRANS(FMIN, trans_msa_3rf, gen_helper_msa_fmin_df); 680 TRANS(FMIN_A, trans_msa_3rf, gen_helper_msa_fmin_a_df); 681 TRANS(FMAX, trans_msa_3rf, gen_helper_msa_fmax_df); 682 TRANS(FMAX_A, trans_msa_3rf, gen_helper_msa_fmax_a_df); 683 684 TRANS(FCOR, trans_msa_3rf, gen_helper_msa_fcor_df); 685 TRANS(FCUNE, trans_msa_3rf, gen_helper_msa_fcune_df); 686 TRANS(FCNE, trans_msa_3rf, gen_helper_msa_fcne_df); 687 TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); 688 TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); 689 TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); 690 TRANS(FSOR, trans_msa_3rf, gen_helper_msa_fsor_df); 691 TRANS(FSUNE, trans_msa_3rf, gen_helper_msa_fsune_df); 692 TRANS(FSNE, trans_msa_3rf, gen_helper_msa_fsne_df); 693 TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); 694 TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); 695 TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); 696 697 static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, 698 gen_helper_pii *gen_msa_2r) 699 { 700 if (!check_msa_enabled(ctx)) { 701 return true; 702 } 703 704 gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); 705 706 return true; 707 } 708 709 TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt); 710 TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc); 711 TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc); 712 713 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) 714 { 715 if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { 716 /* Double format valid only for MIPS64 */ 717 return false; 718 } 719 720 if (!check_msa_enabled(ctx)) { 721 return true; 722 } 723 724 gen_helper_msa_fill_df(cpu_env, 725 tcg_constant_i32(a->df), 726 tcg_constant_i32(a->wd), 727 tcg_constant_i32(a->ws)); 728 729 return true; 730 } 731 732 static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, 733 gen_helper_piii *gen_msa_2rf) 734 { 735 if (!check_msa_enabled(ctx)) { 736 return true; 737 } 738 739 gen_msa_2rf(cpu_env, 740 tcg_constant_i32(a->df), 741 tcg_constant_i32(a->wd), 742 tcg_constant_i32(a->ws)); 743 744 return true; 745 } 746 747 TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); 748 TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); 749 TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_u_df); 750 TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); 751 TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); 752 TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); 753 TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); 754 TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); 755 TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); 756 TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); 757 TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); 758 TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); 759 TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); 760 TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); 761 TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); 762 TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); 763 764 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, 765 gen_helper_piv *gen_msa_ldst) 766 { 767 TCGv taddr; 768 769 if (!check_msa_enabled(ctx)) { 770 return true; 771 } 772 773 taddr = tcg_temp_new(); 774 775 gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); 776 gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); 777 778 return true; 779 } 780 781 TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld); 782 TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); 783 784 static bool trans_LSA(DisasContext *ctx, arg_r *a) 785 { 786 return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); 787 } 788 789 static bool trans_DLSA(DisasContext *ctx, arg_r *a) 790 { 791 if (TARGET_LONG_BITS != 64) { 792 return false; 793 } 794 return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); 795 } 796