1 #ifndef QEMU_MIPS_DEFS_H 2 #define QEMU_MIPS_DEFS_H 3 4 /* If we want to use host float regs... */ 5 //#define USE_HOST_FLOAT_REGS 6 7 /* Real pages are variable size... */ 8 #define TARGET_PAGE_BITS 12 9 #define MIPS_TLB_MAX 128 10 11 #if defined(TARGET_MIPS64) 12 #define TARGET_LONG_BITS 64 13 #define TARGET_PHYS_ADDR_SPACE_BITS 48 14 #define TARGET_VIRT_ADDR_SPACE_BITS 48 15 #else 16 #define TARGET_LONG_BITS 32 17 #define TARGET_PHYS_ADDR_SPACE_BITS 40 18 # ifdef CONFIG_USER_ONLY 19 # define TARGET_VIRT_ADDR_SPACE_BITS 31 20 # else 21 # define TARGET_VIRT_ADDR_SPACE_BITS 32 22 #endif 23 #endif 24 25 /* Masks used to mark instructions to indicate which ISA level they 26 were introduced in. */ 27 #define ISA_MIPS1 0x00000001 28 #define ISA_MIPS2 0x00000002 29 #define ISA_MIPS3 0x00000004 30 #define ISA_MIPS4 0x00000008 31 #define ISA_MIPS5 0x00000010 32 #define ISA_MIPS32 0x00000020 33 #define ISA_MIPS32R2 0x00000040 34 #define ISA_MIPS64 0x00000080 35 #define ISA_MIPS64R2 0x00000100 36 #define ISA_MIPS32R3 0x00000200 37 #define ISA_MIPS64R3 0x00000400 38 #define ISA_MIPS32R5 0x00000800 39 #define ISA_MIPS64R5 0x00001000 40 #define ISA_MIPS32R6 0x00002000 41 #define ISA_MIPS64R6 0x00004000 42 #define ISA_NANOMIPS32 0x00008000 43 44 /* MIPS ASEs. */ 45 #define ASE_MIPS16 0x00010000 46 #define ASE_MIPS3D 0x00020000 47 #define ASE_MDMX 0x00040000 48 #define ASE_DSP 0x00080000 49 #define ASE_DSPR2 0x00100000 50 #define ASE_MT 0x00200000 51 #define ASE_SMARTMIPS 0x00400000 52 #define ASE_MICROMIPS 0x00800000 53 #define ASE_MSA 0x01000000 54 55 /* Chip specific instructions. */ 56 #define INSN_LOONGSON2E 0x20000000 57 #define INSN_LOONGSON2F 0x40000000 58 #define INSN_VR54XX 0x80000000 59 60 /* MIPS CPU defines. */ 61 #define CPU_MIPS1 (ISA_MIPS1) 62 #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) 63 #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) 64 #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) 65 #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) 66 #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) 67 #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) 68 69 #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) 70 71 /* MIPS Technologies "Release 1" */ 72 #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) 73 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) 74 75 /* MIPS Technologies "Release 2" */ 76 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) 77 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) 78 79 /* MIPS Technologies "Release 3" */ 80 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) 81 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) 82 83 /* MIPS Technologies "Release 5" */ 84 #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) 85 #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) 86 87 /* MIPS Technologies "Release 6" */ 88 #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) 89 #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) 90 91 /* Wave Computing: "nanoMIPS" */ 92 #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) 93 94 /* Strictly follow the architecture standard: 95 - Disallow "special" instruction handling for PMON/SPIM. 96 Note that we still maintain Count/Compare to match the host clock. */ 97 //#define MIPS_STRICT_STANDARD 1 98 99 #endif /* QEMU_MIPS_DEFS_H */ 100