1 /* 2 * MIPS internal definitions and helpers 3 * 4 * This work is licensed under the terms of the GNU GPL, version 2 or later. 5 * See the COPYING file in the top-level directory. 6 */ 7 8 #ifndef MIPS_INTERNAL_H 9 #define MIPS_INTERNAL_H 10 11 #include "exec/memattrs.h" 12 #ifdef CONFIG_TCG 13 #include "tcg/tcg-internal.h" 14 #endif 15 #include "cpu.h" 16 17 /* 18 * MMU types, the first four entries have the same layout as the 19 * CP0C0_MT field. 20 */ 21 enum mips_mmu_types { 22 MMU_TYPE_NONE = 0, 23 MMU_TYPE_R4000 = 1, /* Standard TLB */ 24 MMU_TYPE_BAT = 2, /* Block Address Translation */ 25 MMU_TYPE_FMT = 3, /* Fixed Mapping */ 26 MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */ 27 MMU_TYPE_R3000, 28 MMU_TYPE_R6000, 29 MMU_TYPE_R8000 30 }; 31 32 struct mips_def_t { 33 const char *name; 34 int32_t CP0_PRid; 35 int32_t CP0_Config0; 36 int32_t CP0_Config1; 37 int32_t CP0_Config2; 38 int32_t CP0_Config3; 39 int32_t CP0_Config4; 40 int32_t CP0_Config4_rw_bitmask; 41 int32_t CP0_Config5; 42 int32_t CP0_Config5_rw_bitmask; 43 int32_t CP0_Config6; 44 int32_t CP0_Config6_rw_bitmask; 45 int32_t CP0_Config7; 46 int32_t CP0_Config7_rw_bitmask; 47 target_ulong CP0_LLAddr_rw_bitmask; 48 int CP0_LLAddr_shift; 49 int32_t SYNCI_Step; 50 /* 51 * @CCRes: rate at which the coprocessor 0 counter increments 52 * 53 * The Count register acts as a timer, incrementing at a constant rate, 54 * whether or not an instruction is executed, retired, or any forward 55 * progress is made through the pipeline. The rate at which the counter 56 * increments is implementation dependent, and is a function of the 57 * pipeline clock of the processor, not the issue width of the processor. 58 */ 59 int32_t CCRes; 60 int32_t CP0_Status_rw_bitmask; 61 int32_t CP0_TCStatus_rw_bitmask; 62 int32_t CP0_SRSCtl; 63 int32_t CP1_fcr0; 64 int32_t CP1_fcr31_rw_bitmask; 65 int32_t CP1_fcr31; 66 int32_t MSAIR; 67 int32_t SEGBITS; 68 int32_t PABITS; 69 int32_t CP0_SRSConf0_rw_bitmask; 70 int32_t CP0_SRSConf0; 71 int32_t CP0_SRSConf1_rw_bitmask; 72 int32_t CP0_SRSConf1; 73 int32_t CP0_SRSConf2_rw_bitmask; 74 int32_t CP0_SRSConf2; 75 int32_t CP0_SRSConf3_rw_bitmask; 76 int32_t CP0_SRSConf3; 77 int32_t CP0_SRSConf4_rw_bitmask; 78 int32_t CP0_SRSConf4; 79 int32_t CP0_PageGrain_rw_bitmask; 80 int32_t CP0_PageGrain; 81 target_ulong CP0_EBaseWG_rw_bitmask; 82 uint64_t insn_flags; 83 enum mips_mmu_types mmu_type; 84 int32_t SAARP; 85 }; 86 87 extern const char regnames[32][3]; 88 extern const char fregnames[32][4]; 89 90 extern const struct mips_def_t mips_defs[]; 91 extern const int mips_defs_number; 92 93 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 94 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 95 96 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) 97 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) 98 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) 99 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) 100 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) 101 102 #if !defined(CONFIG_USER_ONLY) 103 104 enum { 105 TLBRET_XI = -6, 106 TLBRET_RI = -5, 107 TLBRET_DIRTY = -4, 108 TLBRET_INVALID = -3, 109 TLBRET_NOMATCH = -2, 110 TLBRET_BADADDR = -1, 111 TLBRET_MATCH = 0 112 }; 113 114 int get_physical_address(CPUMIPSState *env, hwaddr *physical, 115 int *prot, target_ulong real_address, 116 MMUAccessType access_type, int mmu_idx); 117 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 118 119 typedef struct r4k_tlb_t r4k_tlb_t; 120 struct r4k_tlb_t { 121 target_ulong VPN; 122 uint32_t PageMask; 123 uint16_t ASID; 124 uint32_t MMID; 125 unsigned int G:1; 126 unsigned int C0:3; 127 unsigned int C1:3; 128 unsigned int V0:1; 129 unsigned int V1:1; 130 unsigned int D0:1; 131 unsigned int D1:1; 132 unsigned int XI0:1; 133 unsigned int XI1:1; 134 unsigned int RI0:1; 135 unsigned int RI1:1; 136 unsigned int EHINV:1; 137 uint64_t PFN[2]; 138 }; 139 140 struct CPUMIPSTLBContext { 141 uint32_t nb_tlb; 142 uint32_t tlb_in_use; 143 int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot, 144 target_ulong address, MMUAccessType access_type); 145 void (*helper_tlbwi)(CPUMIPSState *env); 146 void (*helper_tlbwr)(CPUMIPSState *env); 147 void (*helper_tlbp)(CPUMIPSState *env); 148 void (*helper_tlbr)(CPUMIPSState *env); 149 void (*helper_tlbinv)(CPUMIPSState *env); 150 void (*helper_tlbinvf)(CPUMIPSState *env); 151 union { 152 struct { 153 r4k_tlb_t tlb[MIPS_TLB_MAX]; 154 } r4k; 155 } mmu; 156 }; 157 158 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); 159 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); 160 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); 161 162 extern const VMStateDescription vmstate_mips_cpu; 163 164 #endif /* !CONFIG_USER_ONLY */ 165 166 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) 167 { 168 return (env->CP0_Status & (1 << CP0St_IE)) && 169 !(env->CP0_Status & (1 << CP0St_EXL)) && 170 !(env->CP0_Status & (1 << CP0St_ERL)) && 171 !(env->hflags & MIPS_HFLAG_DM) && 172 /* 173 * Note that the TCStatus IXMT field is initialized to zero, 174 * and only MT capable cores can set it to one. So we don't 175 * need to check for MT capabilities here. 176 */ 177 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); 178 } 179 180 /* Check if there is pending and not masked out interrupt */ 181 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 182 { 183 int32_t pending; 184 int32_t status; 185 bool r; 186 187 pending = env->CP0_Cause & CP0Ca_IP_mask; 188 status = env->CP0_Status & CP0Ca_IP_mask; 189 190 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 191 /* 192 * A MIPS configured with a vectorizing external interrupt controller 193 * will feed a vector into the Cause pending lines. The core treats 194 * the status lines as a vector level, not as individual masks. 195 */ 196 r = pending > status; 197 } else { 198 /* 199 * A MIPS configured with compatibility or VInt (Vectored Interrupts) 200 * treats the pending lines as individual interrupt lines, the status 201 * lines are individual masks. 202 */ 203 r = (pending & status) != 0; 204 } 205 return r; 206 } 207 208 void msa_reset(CPUMIPSState *env); 209 210 /* cp0_timer.c */ 211 uint32_t cpu_mips_get_count(CPUMIPSState *env); 212 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); 213 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); 214 void cpu_mips_start_count(CPUMIPSState *env); 215 void cpu_mips_stop_count(CPUMIPSState *env); 216 217 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) 218 { 219 env->active_tc.PC = value & ~(target_ulong)1; 220 if (value & 1) { 221 env->hflags |= MIPS_HFLAG_M16; 222 } else { 223 env->hflags &= ~(MIPS_HFLAG_M16); 224 } 225 } 226 227 static inline void restore_pamask(CPUMIPSState *env) 228 { 229 if (env->hflags & MIPS_HFLAG_ELPA) { 230 env->PAMask = (1ULL << env->PABITS) - 1; 231 } else { 232 env->PAMask = PAMASK_BASE; 233 } 234 } 235 236 static inline int mips_vpe_active(CPUMIPSState *env) 237 { 238 int active = 1; 239 240 /* Check that the VPE is enabled. */ 241 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { 242 active = 0; 243 } 244 /* Check that the VPE is activated. */ 245 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { 246 active = 0; 247 } 248 249 /* 250 * Now verify that there are active thread contexts in the VPE. 251 * 252 * This assumes the CPU model will internally reschedule threads 253 * if the active one goes to sleep. If there are no threads available 254 * the active one will be in a sleeping state, and we can turn off 255 * the entire VPE. 256 */ 257 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { 258 /* TC is not activated. */ 259 active = 0; 260 } 261 if (env->active_tc.CP0_TCHalt & 1) { 262 /* TC is in halt state. */ 263 active = 0; 264 } 265 266 return active; 267 } 268 269 static inline int mips_vp_active(CPUMIPSState *env) 270 { 271 CPUState *other_cs = first_cpu; 272 273 /* Check if the VP disabled other VPs (which means the VP is enabled) */ 274 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { 275 return 1; 276 } 277 278 /* Check if the virtual processor is disabled due to a DVP */ 279 CPU_FOREACH(other_cs) { 280 MIPSCPU *other_cpu = MIPS_CPU(other_cs); 281 if ((&other_cpu->env != env) && 282 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { 283 return 0; 284 } 285 } 286 return 1; 287 } 288 289 static inline void compute_hflags(CPUMIPSState *env) 290 { 291 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | 292 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | 293 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 294 MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | 295 MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); 296 if (env->CP0_Status & (1 << CP0St_ERL)) { 297 env->hflags |= MIPS_HFLAG_ERL; 298 } 299 if (!(env->CP0_Status & (1 << CP0St_EXL)) && 300 !(env->CP0_Status & (1 << CP0St_ERL)) && 301 !(env->hflags & MIPS_HFLAG_DM)) { 302 env->hflags |= (env->CP0_Status >> CP0St_KSU) & 303 MIPS_HFLAG_KSU; 304 } 305 #if defined(TARGET_MIPS64) 306 if ((env->insn_flags & ISA_MIPS3) && 307 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || 308 (env->CP0_Status & (1 << CP0St_PX)) || 309 (env->CP0_Status & (1 << CP0St_UX)))) { 310 env->hflags |= MIPS_HFLAG_64; 311 } 312 313 if (!(env->insn_flags & ISA_MIPS3)) { 314 env->hflags |= MIPS_HFLAG_AWRAP; 315 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && 316 !(env->CP0_Status & (1 << CP0St_UX))) { 317 env->hflags |= MIPS_HFLAG_AWRAP; 318 } else if (env->insn_flags & ISA_MIPS_R6) { 319 /* Address wrapping for Supervisor and Kernel is specified in R6 */ 320 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && 321 !(env->CP0_Status & (1 << CP0St_SX))) || 322 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && 323 !(env->CP0_Status & (1 << CP0St_KX)))) { 324 env->hflags |= MIPS_HFLAG_AWRAP; 325 } 326 } 327 #endif 328 if (((env->CP0_Status & (1 << CP0St_CU0)) && 329 !(env->insn_flags & ISA_MIPS_R6)) || 330 !(env->hflags & MIPS_HFLAG_KSU)) { 331 env->hflags |= MIPS_HFLAG_CP0; 332 } 333 if (env->CP0_Status & (1 << CP0St_CU1)) { 334 env->hflags |= MIPS_HFLAG_FPU; 335 } 336 if (env->CP0_Status & (1 << CP0St_FR)) { 337 env->hflags |= MIPS_HFLAG_F64; 338 } 339 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && 340 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { 341 env->hflags |= MIPS_HFLAG_SBRI; 342 } 343 if (env->insn_flags & ASE_DSP_R3) { 344 /* 345 * Our cpu supports DSP R3 ASE, so enable 346 * access to DSP R3 resources. 347 */ 348 if (env->CP0_Status & (1 << CP0St_MX)) { 349 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 350 MIPS_HFLAG_DSP_R3; 351 } 352 } else if (env->insn_flags & ASE_DSP_R2) { 353 /* 354 * Our cpu supports DSP R2 ASE, so enable 355 * access to DSP R2 resources. 356 */ 357 if (env->CP0_Status & (1 << CP0St_MX)) { 358 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; 359 } 360 361 } else if (env->insn_flags & ASE_DSP) { 362 /* 363 * Our cpu supports DSP ASE, so enable 364 * access to DSP resources. 365 */ 366 if (env->CP0_Status & (1 << CP0St_MX)) { 367 env->hflags |= MIPS_HFLAG_DSP; 368 } 369 370 } 371 if (env->insn_flags & ISA_MIPS_R2) { 372 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { 373 env->hflags |= MIPS_HFLAG_COP1X; 374 } 375 } else if (env->insn_flags & ISA_MIPS_R1) { 376 if (env->hflags & MIPS_HFLAG_64) { 377 env->hflags |= MIPS_HFLAG_COP1X; 378 } 379 } else if (env->insn_flags & ISA_MIPS4) { 380 /* 381 * All supported MIPS IV CPUs use the XX (CU3) to enable 382 * and disable the MIPS IV extensions to the MIPS III ISA. 383 * Some other MIPS IV CPUs ignore the bit, so the check here 384 * would be too restrictive for them. 385 */ 386 if (env->CP0_Status & (1U << CP0St_CU3)) { 387 env->hflags |= MIPS_HFLAG_COP1X; 388 } 389 } 390 if (ase_msa_available(env)) { 391 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { 392 env->hflags |= MIPS_HFLAG_MSA; 393 } 394 } 395 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 396 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { 397 env->hflags |= MIPS_HFLAG_FRE; 398 } 399 } 400 if (env->CP0_Config3 & (1 << CP0C3_LPA)) { 401 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { 402 env->hflags |= MIPS_HFLAG_ELPA; 403 } 404 } 405 } 406 407 #endif 408