1 /* 2 * MIPS internal definitions and helpers 3 * 4 * This work is licensed under the terms of the GNU GPL, version 2 or later. 5 * See the COPYING file in the top-level directory. 6 */ 7 8 #ifndef MIPS_INTERNAL_H 9 #define MIPS_INTERNAL_H 10 11 #include "exec/memattrs.h" 12 #ifdef CONFIG_TCG 13 #include "tcg/tcg-internal.h" 14 #endif 15 16 /* 17 * MMU types, the first four entries have the same layout as the 18 * CP0C0_MT field. 19 */ 20 enum mips_mmu_types { 21 MMU_TYPE_NONE = 0, 22 MMU_TYPE_R4000 = 1, /* Standard TLB */ 23 MMU_TYPE_BAT = 2, /* Block Address Translation */ 24 MMU_TYPE_FMT = 3, /* Fixed Mapping */ 25 MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */ 26 MMU_TYPE_R3000, 27 MMU_TYPE_R6000, 28 MMU_TYPE_R8000 29 }; 30 31 struct mips_def_t { 32 const char *name; 33 int32_t CP0_PRid; 34 int32_t CP0_Config0; 35 int32_t CP0_Config1; 36 int32_t CP0_Config2; 37 int32_t CP0_Config3; 38 int32_t CP0_Config4; 39 int32_t CP0_Config4_rw_bitmask; 40 int32_t CP0_Config5; 41 int32_t CP0_Config5_rw_bitmask; 42 int32_t CP0_Config6; 43 int32_t CP0_Config6_rw_bitmask; 44 int32_t CP0_Config7; 45 int32_t CP0_Config7_rw_bitmask; 46 target_ulong CP0_LLAddr_rw_bitmask; 47 int CP0_LLAddr_shift; 48 int32_t SYNCI_Step; 49 int32_t CCRes; 50 int32_t CP0_Status_rw_bitmask; 51 int32_t CP0_TCStatus_rw_bitmask; 52 int32_t CP0_SRSCtl; 53 int32_t CP1_fcr0; 54 int32_t CP1_fcr31_rw_bitmask; 55 int32_t CP1_fcr31; 56 int32_t MSAIR; 57 int32_t SEGBITS; 58 int32_t PABITS; 59 int32_t CP0_SRSConf0_rw_bitmask; 60 int32_t CP0_SRSConf0; 61 int32_t CP0_SRSConf1_rw_bitmask; 62 int32_t CP0_SRSConf1; 63 int32_t CP0_SRSConf2_rw_bitmask; 64 int32_t CP0_SRSConf2; 65 int32_t CP0_SRSConf3_rw_bitmask; 66 int32_t CP0_SRSConf3; 67 int32_t CP0_SRSConf4_rw_bitmask; 68 int32_t CP0_SRSConf4; 69 int32_t CP0_PageGrain_rw_bitmask; 70 int32_t CP0_PageGrain; 71 target_ulong CP0_EBaseWG_rw_bitmask; 72 uint64_t insn_flags; 73 enum mips_mmu_types mmu_type; 74 int32_t SAARP; 75 }; 76 77 extern const char regnames[32][3]; 78 extern const char fregnames[32][4]; 79 80 extern const struct mips_def_t mips_defs[]; 81 extern const int mips_defs_number; 82 83 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 84 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 85 86 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) 87 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) 88 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) 89 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) 90 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) 91 92 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) 93 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) 94 95 #if !defined(CONFIG_USER_ONLY) 96 97 enum { 98 TLBRET_XI = -6, 99 TLBRET_RI = -5, 100 TLBRET_DIRTY = -4, 101 TLBRET_INVALID = -3, 102 TLBRET_NOMATCH = -2, 103 TLBRET_BADADDR = -1, 104 TLBRET_MATCH = 0 105 }; 106 107 int get_physical_address(CPUMIPSState *env, hwaddr *physical, 108 int *prot, target_ulong real_address, 109 MMUAccessType access_type, int mmu_idx); 110 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 111 112 typedef struct r4k_tlb_t r4k_tlb_t; 113 struct r4k_tlb_t { 114 target_ulong VPN; 115 uint32_t PageMask; 116 uint16_t ASID; 117 uint32_t MMID; 118 unsigned int G:1; 119 unsigned int C0:3; 120 unsigned int C1:3; 121 unsigned int V0:1; 122 unsigned int V1:1; 123 unsigned int D0:1; 124 unsigned int D1:1; 125 unsigned int XI0:1; 126 unsigned int XI1:1; 127 unsigned int RI0:1; 128 unsigned int RI1:1; 129 unsigned int EHINV:1; 130 uint64_t PFN[2]; 131 }; 132 133 struct CPUMIPSTLBContext { 134 uint32_t nb_tlb; 135 uint32_t tlb_in_use; 136 int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, 137 target_ulong address, MMUAccessType access_type); 138 void (*helper_tlbwi)(struct CPUMIPSState *env); 139 void (*helper_tlbwr)(struct CPUMIPSState *env); 140 void (*helper_tlbp)(struct CPUMIPSState *env); 141 void (*helper_tlbr)(struct CPUMIPSState *env); 142 void (*helper_tlbinv)(struct CPUMIPSState *env); 143 void (*helper_tlbinvf)(struct CPUMIPSState *env); 144 union { 145 struct { 146 r4k_tlb_t tlb[MIPS_TLB_MAX]; 147 } r4k; 148 } mmu; 149 }; 150 151 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); 152 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); 153 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); 154 155 extern const VMStateDescription vmstate_mips_cpu; 156 157 #endif /* !CONFIG_USER_ONLY */ 158 159 #define cpu_signal_handler cpu_mips_signal_handler 160 161 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) 162 { 163 return (env->CP0_Status & (1 << CP0St_IE)) && 164 !(env->CP0_Status & (1 << CP0St_EXL)) && 165 !(env->CP0_Status & (1 << CP0St_ERL)) && 166 !(env->hflags & MIPS_HFLAG_DM) && 167 /* 168 * Note that the TCStatus IXMT field is initialized to zero, 169 * and only MT capable cores can set it to one. So we don't 170 * need to check for MT capabilities here. 171 */ 172 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); 173 } 174 175 /* Check if there is pending and not masked out interrupt */ 176 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 177 { 178 int32_t pending; 179 int32_t status; 180 bool r; 181 182 pending = env->CP0_Cause & CP0Ca_IP_mask; 183 status = env->CP0_Status & CP0Ca_IP_mask; 184 185 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 186 /* 187 * A MIPS configured with a vectorizing external interrupt controller 188 * will feed a vector into the Cause pending lines. The core treats 189 * the status lines as a vector level, not as individual masks. 190 */ 191 r = pending > status; 192 } else { 193 /* 194 * A MIPS configured with compatibility or VInt (Vectored Interrupts) 195 * treats the pending lines as individual interrupt lines, the status 196 * lines are individual masks. 197 */ 198 r = (pending & status) != 0; 199 } 200 return r; 201 } 202 203 void msa_reset(CPUMIPSState *env); 204 205 /* cp0_timer.c */ 206 uint32_t cpu_mips_get_count(CPUMIPSState *env); 207 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); 208 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); 209 void cpu_mips_start_count(CPUMIPSState *env); 210 void cpu_mips_stop_count(CPUMIPSState *env); 211 212 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) 213 { 214 env->active_tc.PC = value & ~(target_ulong)1; 215 if (value & 1) { 216 env->hflags |= MIPS_HFLAG_M16; 217 } else { 218 env->hflags &= ~(MIPS_HFLAG_M16); 219 } 220 } 221 222 static inline void restore_pamask(CPUMIPSState *env) 223 { 224 if (env->hflags & MIPS_HFLAG_ELPA) { 225 env->PAMask = (1ULL << env->PABITS) - 1; 226 } else { 227 env->PAMask = PAMASK_BASE; 228 } 229 } 230 231 static inline int mips_vpe_active(CPUMIPSState *env) 232 { 233 int active = 1; 234 235 /* Check that the VPE is enabled. */ 236 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { 237 active = 0; 238 } 239 /* Check that the VPE is activated. */ 240 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { 241 active = 0; 242 } 243 244 /* 245 * Now verify that there are active thread contexts in the VPE. 246 * 247 * This assumes the CPU model will internally reschedule threads 248 * if the active one goes to sleep. If there are no threads available 249 * the active one will be in a sleeping state, and we can turn off 250 * the entire VPE. 251 */ 252 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { 253 /* TC is not activated. */ 254 active = 0; 255 } 256 if (env->active_tc.CP0_TCHalt & 1) { 257 /* TC is in halt state. */ 258 active = 0; 259 } 260 261 return active; 262 } 263 264 static inline int mips_vp_active(CPUMIPSState *env) 265 { 266 CPUState *other_cs = first_cpu; 267 268 /* Check if the VP disabled other VPs (which means the VP is enabled) */ 269 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { 270 return 1; 271 } 272 273 /* Check if the virtual processor is disabled due to a DVP */ 274 CPU_FOREACH(other_cs) { 275 MIPSCPU *other_cpu = MIPS_CPU(other_cs); 276 if ((&other_cpu->env != env) && 277 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { 278 return 0; 279 } 280 } 281 return 1; 282 } 283 284 static inline void compute_hflags(CPUMIPSState *env) 285 { 286 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | 287 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | 288 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 289 MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | 290 MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); 291 if (env->CP0_Status & (1 << CP0St_ERL)) { 292 env->hflags |= MIPS_HFLAG_ERL; 293 } 294 if (!(env->CP0_Status & (1 << CP0St_EXL)) && 295 !(env->CP0_Status & (1 << CP0St_ERL)) && 296 !(env->hflags & MIPS_HFLAG_DM)) { 297 env->hflags |= (env->CP0_Status >> CP0St_KSU) & 298 MIPS_HFLAG_KSU; 299 } 300 #if defined(TARGET_MIPS64) 301 if ((env->insn_flags & ISA_MIPS3) && 302 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || 303 (env->CP0_Status & (1 << CP0St_PX)) || 304 (env->CP0_Status & (1 << CP0St_UX)))) { 305 env->hflags |= MIPS_HFLAG_64; 306 } 307 308 if (!(env->insn_flags & ISA_MIPS3)) { 309 env->hflags |= MIPS_HFLAG_AWRAP; 310 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && 311 !(env->CP0_Status & (1 << CP0St_UX))) { 312 env->hflags |= MIPS_HFLAG_AWRAP; 313 } else if (env->insn_flags & ISA_MIPS_R6) { 314 /* Address wrapping for Supervisor and Kernel is specified in R6 */ 315 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && 316 !(env->CP0_Status & (1 << CP0St_SX))) || 317 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && 318 !(env->CP0_Status & (1 << CP0St_KX)))) { 319 env->hflags |= MIPS_HFLAG_AWRAP; 320 } 321 } 322 #endif 323 if (((env->CP0_Status & (1 << CP0St_CU0)) && 324 !(env->insn_flags & ISA_MIPS_R6)) || 325 !(env->hflags & MIPS_HFLAG_KSU)) { 326 env->hflags |= MIPS_HFLAG_CP0; 327 } 328 if (env->CP0_Status & (1 << CP0St_CU1)) { 329 env->hflags |= MIPS_HFLAG_FPU; 330 } 331 if (env->CP0_Status & (1 << CP0St_FR)) { 332 env->hflags |= MIPS_HFLAG_F64; 333 } 334 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && 335 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { 336 env->hflags |= MIPS_HFLAG_SBRI; 337 } 338 if (env->insn_flags & ASE_DSP_R3) { 339 /* 340 * Our cpu supports DSP R3 ASE, so enable 341 * access to DSP R3 resources. 342 */ 343 if (env->CP0_Status & (1 << CP0St_MX)) { 344 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 345 MIPS_HFLAG_DSP_R3; 346 } 347 } else if (env->insn_flags & ASE_DSP_R2) { 348 /* 349 * Our cpu supports DSP R2 ASE, so enable 350 * access to DSP R2 resources. 351 */ 352 if (env->CP0_Status & (1 << CP0St_MX)) { 353 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; 354 } 355 356 } else if (env->insn_flags & ASE_DSP) { 357 /* 358 * Our cpu supports DSP ASE, so enable 359 * access to DSP resources. 360 */ 361 if (env->CP0_Status & (1 << CP0St_MX)) { 362 env->hflags |= MIPS_HFLAG_DSP; 363 } 364 365 } 366 if (env->insn_flags & ISA_MIPS_R2) { 367 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { 368 env->hflags |= MIPS_HFLAG_COP1X; 369 } 370 } else if (env->insn_flags & ISA_MIPS_R1) { 371 if (env->hflags & MIPS_HFLAG_64) { 372 env->hflags |= MIPS_HFLAG_COP1X; 373 } 374 } else if (env->insn_flags & ISA_MIPS4) { 375 /* 376 * All supported MIPS IV CPUs use the XX (CU3) to enable 377 * and disable the MIPS IV extensions to the MIPS III ISA. 378 * Some other MIPS IV CPUs ignore the bit, so the check here 379 * would be too restrictive for them. 380 */ 381 if (env->CP0_Status & (1U << CP0St_CU3)) { 382 env->hflags |= MIPS_HFLAG_COP1X; 383 } 384 } 385 if (ase_msa_available(env)) { 386 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { 387 env->hflags |= MIPS_HFLAG_MSA; 388 } 389 } 390 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 391 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { 392 env->hflags |= MIPS_HFLAG_FRE; 393 } 394 } 395 if (env->CP0_Config3 & (1 << CP0C3_LPA)) { 396 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { 397 env->hflags |= MIPS_HFLAG_ELPA; 398 } 399 } 400 } 401 402 #endif 403