1 /* 2 * MIPS internal definitions and helpers 3 * 4 * This work is licensed under the terms of the GNU GPL, version 2 or later. 5 * See the COPYING file in the top-level directory. 6 */ 7 8 #ifndef MIPS_INTERNAL_H 9 #define MIPS_INTERNAL_H 10 11 #include "exec/memattrs.h" 12 #ifdef CONFIG_TCG 13 #include "tcg/tcg-internal.h" 14 #endif 15 #include "cpu.h" 16 17 /* 18 * MMU types, the first four entries have the same layout as the 19 * CP0C0_MT field. 20 */ 21 enum mips_mmu_types { 22 MMU_TYPE_NONE = 0, 23 MMU_TYPE_R4000 = 1, /* Standard TLB */ 24 MMU_TYPE_BAT = 2, /* Block Address Translation */ 25 MMU_TYPE_FMT = 3, /* Fixed Mapping */ 26 MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */ 27 MMU_TYPE_R3000, 28 MMU_TYPE_R6000, 29 MMU_TYPE_R8000 30 }; 31 32 struct mips_def_t { 33 const char *name; 34 int32_t CP0_PRid; 35 int32_t CP0_Config0; 36 int32_t CP0_Config1; 37 int32_t CP0_Config2; 38 int32_t CP0_Config3; 39 int32_t CP0_Config4; 40 int32_t CP0_Config4_rw_bitmask; 41 int32_t CP0_Config5; 42 int32_t CP0_Config5_rw_bitmask; 43 int32_t CP0_Config6; 44 int32_t CP0_Config6_rw_bitmask; 45 int32_t CP0_Config7; 46 int32_t CP0_Config7_rw_bitmask; 47 target_ulong CP0_LLAddr_rw_bitmask; 48 int CP0_LLAddr_shift; 49 int32_t SYNCI_Step; 50 int32_t CCRes; 51 int32_t CP0_Status_rw_bitmask; 52 int32_t CP0_TCStatus_rw_bitmask; 53 int32_t CP0_SRSCtl; 54 int32_t CP1_fcr0; 55 int32_t CP1_fcr31_rw_bitmask; 56 int32_t CP1_fcr31; 57 int32_t MSAIR; 58 int32_t SEGBITS; 59 int32_t PABITS; 60 int32_t CP0_SRSConf0_rw_bitmask; 61 int32_t CP0_SRSConf0; 62 int32_t CP0_SRSConf1_rw_bitmask; 63 int32_t CP0_SRSConf1; 64 int32_t CP0_SRSConf2_rw_bitmask; 65 int32_t CP0_SRSConf2; 66 int32_t CP0_SRSConf3_rw_bitmask; 67 int32_t CP0_SRSConf3; 68 int32_t CP0_SRSConf4_rw_bitmask; 69 int32_t CP0_SRSConf4; 70 int32_t CP0_PageGrain_rw_bitmask; 71 int32_t CP0_PageGrain; 72 target_ulong CP0_EBaseWG_rw_bitmask; 73 uint64_t insn_flags; 74 enum mips_mmu_types mmu_type; 75 int32_t SAARP; 76 }; 77 78 extern const char regnames[32][3]; 79 extern const char fregnames[32][4]; 80 81 extern const struct mips_def_t mips_defs[]; 82 extern const int mips_defs_number; 83 84 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 85 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 86 87 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) 88 #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) 89 #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) 90 #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) 91 #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) 92 93 #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) 94 #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) 95 96 #if !defined(CONFIG_USER_ONLY) 97 98 enum { 99 TLBRET_XI = -6, 100 TLBRET_RI = -5, 101 TLBRET_DIRTY = -4, 102 TLBRET_INVALID = -3, 103 TLBRET_NOMATCH = -2, 104 TLBRET_BADADDR = -1, 105 TLBRET_MATCH = 0 106 }; 107 108 int get_physical_address(CPUMIPSState *env, hwaddr *physical, 109 int *prot, target_ulong real_address, 110 MMUAccessType access_type, int mmu_idx); 111 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 112 113 typedef struct r4k_tlb_t r4k_tlb_t; 114 struct r4k_tlb_t { 115 target_ulong VPN; 116 uint32_t PageMask; 117 uint16_t ASID; 118 uint32_t MMID; 119 unsigned int G:1; 120 unsigned int C0:3; 121 unsigned int C1:3; 122 unsigned int V0:1; 123 unsigned int V1:1; 124 unsigned int D0:1; 125 unsigned int D1:1; 126 unsigned int XI0:1; 127 unsigned int XI1:1; 128 unsigned int RI0:1; 129 unsigned int RI1:1; 130 unsigned int EHINV:1; 131 uint64_t PFN[2]; 132 }; 133 134 struct CPUMIPSTLBContext { 135 uint32_t nb_tlb; 136 uint32_t tlb_in_use; 137 int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, 138 target_ulong address, MMUAccessType access_type); 139 void (*helper_tlbwi)(struct CPUMIPSState *env); 140 void (*helper_tlbwr)(struct CPUMIPSState *env); 141 void (*helper_tlbp)(struct CPUMIPSState *env); 142 void (*helper_tlbr)(struct CPUMIPSState *env); 143 void (*helper_tlbinv)(struct CPUMIPSState *env); 144 void (*helper_tlbinvf)(struct CPUMIPSState *env); 145 union { 146 struct { 147 r4k_tlb_t tlb[MIPS_TLB_MAX]; 148 } r4k; 149 } mmu; 150 }; 151 152 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); 153 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); 154 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); 155 156 extern const VMStateDescription vmstate_mips_cpu; 157 158 #endif /* !CONFIG_USER_ONLY */ 159 160 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) 161 { 162 return (env->CP0_Status & (1 << CP0St_IE)) && 163 !(env->CP0_Status & (1 << CP0St_EXL)) && 164 !(env->CP0_Status & (1 << CP0St_ERL)) && 165 !(env->hflags & MIPS_HFLAG_DM) && 166 /* 167 * Note that the TCStatus IXMT field is initialized to zero, 168 * and only MT capable cores can set it to one. So we don't 169 * need to check for MT capabilities here. 170 */ 171 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); 172 } 173 174 /* Check if there is pending and not masked out interrupt */ 175 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 176 { 177 int32_t pending; 178 int32_t status; 179 bool r; 180 181 pending = env->CP0_Cause & CP0Ca_IP_mask; 182 status = env->CP0_Status & CP0Ca_IP_mask; 183 184 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 185 /* 186 * A MIPS configured with a vectorizing external interrupt controller 187 * will feed a vector into the Cause pending lines. The core treats 188 * the status lines as a vector level, not as individual masks. 189 */ 190 r = pending > status; 191 } else { 192 /* 193 * A MIPS configured with compatibility or VInt (Vectored Interrupts) 194 * treats the pending lines as individual interrupt lines, the status 195 * lines are individual masks. 196 */ 197 r = (pending & status) != 0; 198 } 199 return r; 200 } 201 202 void msa_reset(CPUMIPSState *env); 203 204 /* cp0_timer.c */ 205 uint32_t cpu_mips_get_count(CPUMIPSState *env); 206 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); 207 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); 208 void cpu_mips_start_count(CPUMIPSState *env); 209 void cpu_mips_stop_count(CPUMIPSState *env); 210 211 static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) 212 { 213 env->active_tc.PC = value & ~(target_ulong)1; 214 if (value & 1) { 215 env->hflags |= MIPS_HFLAG_M16; 216 } else { 217 env->hflags &= ~(MIPS_HFLAG_M16); 218 } 219 } 220 221 static inline void restore_pamask(CPUMIPSState *env) 222 { 223 if (env->hflags & MIPS_HFLAG_ELPA) { 224 env->PAMask = (1ULL << env->PABITS) - 1; 225 } else { 226 env->PAMask = PAMASK_BASE; 227 } 228 } 229 230 static inline int mips_vpe_active(CPUMIPSState *env) 231 { 232 int active = 1; 233 234 /* Check that the VPE is enabled. */ 235 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { 236 active = 0; 237 } 238 /* Check that the VPE is activated. */ 239 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { 240 active = 0; 241 } 242 243 /* 244 * Now verify that there are active thread contexts in the VPE. 245 * 246 * This assumes the CPU model will internally reschedule threads 247 * if the active one goes to sleep. If there are no threads available 248 * the active one will be in a sleeping state, and we can turn off 249 * the entire VPE. 250 */ 251 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { 252 /* TC is not activated. */ 253 active = 0; 254 } 255 if (env->active_tc.CP0_TCHalt & 1) { 256 /* TC is in halt state. */ 257 active = 0; 258 } 259 260 return active; 261 } 262 263 static inline int mips_vp_active(CPUMIPSState *env) 264 { 265 CPUState *other_cs = first_cpu; 266 267 /* Check if the VP disabled other VPs (which means the VP is enabled) */ 268 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { 269 return 1; 270 } 271 272 /* Check if the virtual processor is disabled due to a DVP */ 273 CPU_FOREACH(other_cs) { 274 MIPSCPU *other_cpu = MIPS_CPU(other_cs); 275 if ((&other_cpu->env != env) && 276 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { 277 return 0; 278 } 279 } 280 return 1; 281 } 282 283 static inline void compute_hflags(CPUMIPSState *env) 284 { 285 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | 286 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | 287 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 288 MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | 289 MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); 290 if (env->CP0_Status & (1 << CP0St_ERL)) { 291 env->hflags |= MIPS_HFLAG_ERL; 292 } 293 if (!(env->CP0_Status & (1 << CP0St_EXL)) && 294 !(env->CP0_Status & (1 << CP0St_ERL)) && 295 !(env->hflags & MIPS_HFLAG_DM)) { 296 env->hflags |= (env->CP0_Status >> CP0St_KSU) & 297 MIPS_HFLAG_KSU; 298 } 299 #if defined(TARGET_MIPS64) 300 if ((env->insn_flags & ISA_MIPS3) && 301 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || 302 (env->CP0_Status & (1 << CP0St_PX)) || 303 (env->CP0_Status & (1 << CP0St_UX)))) { 304 env->hflags |= MIPS_HFLAG_64; 305 } 306 307 if (!(env->insn_flags & ISA_MIPS3)) { 308 env->hflags |= MIPS_HFLAG_AWRAP; 309 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && 310 !(env->CP0_Status & (1 << CP0St_UX))) { 311 env->hflags |= MIPS_HFLAG_AWRAP; 312 } else if (env->insn_flags & ISA_MIPS_R6) { 313 /* Address wrapping for Supervisor and Kernel is specified in R6 */ 314 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && 315 !(env->CP0_Status & (1 << CP0St_SX))) || 316 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && 317 !(env->CP0_Status & (1 << CP0St_KX)))) { 318 env->hflags |= MIPS_HFLAG_AWRAP; 319 } 320 } 321 #endif 322 if (((env->CP0_Status & (1 << CP0St_CU0)) && 323 !(env->insn_flags & ISA_MIPS_R6)) || 324 !(env->hflags & MIPS_HFLAG_KSU)) { 325 env->hflags |= MIPS_HFLAG_CP0; 326 } 327 if (env->CP0_Status & (1 << CP0St_CU1)) { 328 env->hflags |= MIPS_HFLAG_FPU; 329 } 330 if (env->CP0_Status & (1 << CP0St_FR)) { 331 env->hflags |= MIPS_HFLAG_F64; 332 } 333 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && 334 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { 335 env->hflags |= MIPS_HFLAG_SBRI; 336 } 337 if (env->insn_flags & ASE_DSP_R3) { 338 /* 339 * Our cpu supports DSP R3 ASE, so enable 340 * access to DSP R3 resources. 341 */ 342 if (env->CP0_Status & (1 << CP0St_MX)) { 343 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 344 MIPS_HFLAG_DSP_R3; 345 } 346 } else if (env->insn_flags & ASE_DSP_R2) { 347 /* 348 * Our cpu supports DSP R2 ASE, so enable 349 * access to DSP R2 resources. 350 */ 351 if (env->CP0_Status & (1 << CP0St_MX)) { 352 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; 353 } 354 355 } else if (env->insn_flags & ASE_DSP) { 356 /* 357 * Our cpu supports DSP ASE, so enable 358 * access to DSP resources. 359 */ 360 if (env->CP0_Status & (1 << CP0St_MX)) { 361 env->hflags |= MIPS_HFLAG_DSP; 362 } 363 364 } 365 if (env->insn_flags & ISA_MIPS_R2) { 366 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { 367 env->hflags |= MIPS_HFLAG_COP1X; 368 } 369 } else if (env->insn_flags & ISA_MIPS_R1) { 370 if (env->hflags & MIPS_HFLAG_64) { 371 env->hflags |= MIPS_HFLAG_COP1X; 372 } 373 } else if (env->insn_flags & ISA_MIPS4) { 374 /* 375 * All supported MIPS IV CPUs use the XX (CU3) to enable 376 * and disable the MIPS IV extensions to the MIPS III ISA. 377 * Some other MIPS IV CPUs ignore the bit, so the check here 378 * would be too restrictive for them. 379 */ 380 if (env->CP0_Status & (1U << CP0St_CU3)) { 381 env->hflags |= MIPS_HFLAG_COP1X; 382 } 383 } 384 if (ase_msa_available(env)) { 385 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { 386 env->hflags |= MIPS_HFLAG_MSA; 387 } 388 } 389 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 390 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { 391 env->hflags |= MIPS_HFLAG_FRE; 392 } 393 } 394 if (env->CP0_Config3 & (1 << CP0C3_LPA)) { 395 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { 396 env->hflags |= MIPS_HFLAG_ELPA; 397 } 398 } 399 } 400 401 #endif 402