1 /* 2 * MIPS internal definitions and helpers 3 * 4 * This work is licensed under the terms of the GNU GPL, version 2 or later. 5 * See the COPYING file in the top-level directory. 6 */ 7 8 #ifndef MIPS_INTERNAL_H 9 #define MIPS_INTERNAL_H 10 11 #include "fpu/softfloat-helpers.h" 12 13 /* 14 * MMU types, the first four entries have the same layout as the 15 * CP0C0_MT field. 16 */ 17 enum mips_mmu_types { 18 MMU_TYPE_NONE, 19 MMU_TYPE_R4000, 20 MMU_TYPE_RESERVED, 21 MMU_TYPE_FMT, 22 MMU_TYPE_R3000, 23 MMU_TYPE_R6000, 24 MMU_TYPE_R8000 25 }; 26 27 struct mips_def_t { 28 const char *name; 29 int32_t CP0_PRid; 30 int32_t CP0_Config0; 31 int32_t CP0_Config1; 32 int32_t CP0_Config2; 33 int32_t CP0_Config3; 34 int32_t CP0_Config4; 35 int32_t CP0_Config4_rw_bitmask; 36 int32_t CP0_Config5; 37 int32_t CP0_Config5_rw_bitmask; 38 int32_t CP0_Config6; 39 int32_t CP0_Config6_rw_bitmask; 40 int32_t CP0_Config7; 41 int32_t CP0_Config7_rw_bitmask; 42 target_ulong CP0_LLAddr_rw_bitmask; 43 int CP0_LLAddr_shift; 44 int32_t SYNCI_Step; 45 int32_t CCRes; 46 int32_t CP0_Status_rw_bitmask; 47 int32_t CP0_TCStatus_rw_bitmask; 48 int32_t CP0_SRSCtl; 49 int32_t CP1_fcr0; 50 int32_t CP1_fcr31_rw_bitmask; 51 int32_t CP1_fcr31; 52 int32_t MSAIR; 53 int32_t SEGBITS; 54 int32_t PABITS; 55 int32_t CP0_SRSConf0_rw_bitmask; 56 int32_t CP0_SRSConf0; 57 int32_t CP0_SRSConf1_rw_bitmask; 58 int32_t CP0_SRSConf1; 59 int32_t CP0_SRSConf2_rw_bitmask; 60 int32_t CP0_SRSConf2; 61 int32_t CP0_SRSConf3_rw_bitmask; 62 int32_t CP0_SRSConf3; 63 int32_t CP0_SRSConf4_rw_bitmask; 64 int32_t CP0_SRSConf4; 65 int32_t CP0_PageGrain_rw_bitmask; 66 int32_t CP0_PageGrain; 67 target_ulong CP0_EBaseWG_rw_bitmask; 68 uint64_t insn_flags; 69 enum mips_mmu_types mmu_type; 70 int32_t SAARP; 71 }; 72 73 extern const struct mips_def_t mips_defs[]; 74 extern const int mips_defs_number; 75 76 enum CPUMIPSMSADataFormat { 77 DF_BYTE = 0, 78 DF_HALF, 79 DF_WORD, 80 DF_DOUBLE 81 }; 82 83 void mips_cpu_do_interrupt(CPUState *cpu); 84 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); 85 void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 86 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 87 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 88 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 89 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 90 MMUAccessType access_type, 91 int mmu_idx, uintptr_t retaddr); 92 93 #if !defined(CONFIG_USER_ONLY) 94 95 typedef struct r4k_tlb_t r4k_tlb_t; 96 struct r4k_tlb_t { 97 target_ulong VPN; 98 uint32_t PageMask; 99 uint16_t ASID; 100 uint32_t MMID; 101 unsigned int G:1; 102 unsigned int C0:3; 103 unsigned int C1:3; 104 unsigned int V0:1; 105 unsigned int V1:1; 106 unsigned int D0:1; 107 unsigned int D1:1; 108 unsigned int XI0:1; 109 unsigned int XI1:1; 110 unsigned int RI0:1; 111 unsigned int RI1:1; 112 unsigned int EHINV:1; 113 uint64_t PFN[2]; 114 }; 115 116 struct CPUMIPSTLBContext { 117 uint32_t nb_tlb; 118 uint32_t tlb_in_use; 119 int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, 120 target_ulong address, int rw, int access_type); 121 void (*helper_tlbwi)(struct CPUMIPSState *env); 122 void (*helper_tlbwr)(struct CPUMIPSState *env); 123 void (*helper_tlbp)(struct CPUMIPSState *env); 124 void (*helper_tlbr)(struct CPUMIPSState *env); 125 void (*helper_tlbinv)(struct CPUMIPSState *env); 126 void (*helper_tlbinvf)(struct CPUMIPSState *env); 127 union { 128 struct { 129 r4k_tlb_t tlb[MIPS_TLB_MAX]; 130 } r4k; 131 } mmu; 132 }; 133 134 int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, 135 target_ulong address, int rw, int access_type); 136 int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, 137 target_ulong address, int rw, int access_type); 138 int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, 139 target_ulong address, int rw, int access_type); 140 void r4k_helper_tlbwi(CPUMIPSState *env); 141 void r4k_helper_tlbwr(CPUMIPSState *env); 142 void r4k_helper_tlbp(CPUMIPSState *env); 143 void r4k_helper_tlbr(CPUMIPSState *env); 144 void r4k_helper_tlbinv(CPUMIPSState *env); 145 void r4k_helper_tlbinvf(CPUMIPSState *env); 146 void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); 147 uint32_t cpu_mips_get_random(CPUMIPSState *env); 148 149 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 150 vaddr addr, unsigned size, 151 MMUAccessType access_type, 152 int mmu_idx, MemTxAttrs attrs, 153 MemTxResult response, uintptr_t retaddr); 154 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, 155 int rw); 156 #endif 157 158 #define cpu_signal_handler cpu_mips_signal_handler 159 160 #ifndef CONFIG_USER_ONLY 161 extern const VMStateDescription vmstate_mips_cpu; 162 #endif 163 164 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) 165 { 166 return (env->CP0_Status & (1 << CP0St_IE)) && 167 !(env->CP0_Status & (1 << CP0St_EXL)) && 168 !(env->CP0_Status & (1 << CP0St_ERL)) && 169 !(env->hflags & MIPS_HFLAG_DM) && 170 /* 171 * Note that the TCStatus IXMT field is initialized to zero, 172 * and only MT capable cores can set it to one. So we don't 173 * need to check for MT capabilities here. 174 */ 175 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); 176 } 177 178 /* Check if there is pending and not masked out interrupt */ 179 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 180 { 181 int32_t pending; 182 int32_t status; 183 bool r; 184 185 pending = env->CP0_Cause & CP0Ca_IP_mask; 186 status = env->CP0_Status & CP0Ca_IP_mask; 187 188 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { 189 /* 190 * A MIPS configured with a vectorizing external interrupt controller 191 * will feed a vector into the Cause pending lines. The core treats 192 * the status lines as a vector level, not as individual masks. 193 */ 194 r = pending > status; 195 } else { 196 /* 197 * A MIPS configured with compatibility or VInt (Vectored Interrupts) 198 * treats the pending lines as individual interrupt lines, the status 199 * lines are individual masks. 200 */ 201 r = (pending & status) != 0; 202 } 203 return r; 204 } 205 206 void mips_tcg_init(void); 207 208 /* TODO QOM'ify CPU reset and remove */ 209 void cpu_state_reset(CPUMIPSState *s); 210 void cpu_mips_realize_env(CPUMIPSState *env); 211 212 /* cp0_timer.c */ 213 uint32_t cpu_mips_get_count(CPUMIPSState *env); 214 void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); 215 void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); 216 void cpu_mips_start_count(CPUMIPSState *env); 217 void cpu_mips_stop_count(CPUMIPSState *env); 218 219 /* helper.c */ 220 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 221 MMUAccessType access_type, int mmu_idx, 222 bool probe, uintptr_t retaddr); 223 224 /* op_helper.c */ 225 uint32_t float_class_s(uint32_t arg, float_status *fst); 226 uint64_t float_class_d(uint64_t arg, float_status *fst); 227 228 extern unsigned int ieee_rm[]; 229 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); 230 231 static inline void restore_rounding_mode(CPUMIPSState *env) 232 { 233 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], 234 &env->active_fpu.fp_status); 235 } 236 237 static inline void restore_flush_mode(CPUMIPSState *env) 238 { 239 set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, 240 &env->active_fpu.fp_status); 241 } 242 243 static inline void restore_snan_bit_mode(CPUMIPSState *env) 244 { 245 set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, 246 &env->active_fpu.fp_status); 247 } 248 249 static inline void restore_fp_status(CPUMIPSState *env) 250 { 251 restore_rounding_mode(env); 252 restore_flush_mode(env); 253 restore_snan_bit_mode(env); 254 } 255 256 static inline void restore_msa_fp_status(CPUMIPSState *env) 257 { 258 float_status *status = &env->active_tc.msa_fp_status; 259 int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; 260 bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; 261 262 set_float_rounding_mode(ieee_rm[rounding_mode], status); 263 set_flush_to_zero(flush_to_zero, status); 264 set_flush_inputs_to_zero(flush_to_zero, status); 265 } 266 267 static inline void restore_pamask(CPUMIPSState *env) 268 { 269 if (env->hflags & MIPS_HFLAG_ELPA) { 270 env->PAMask = (1ULL << env->PABITS) - 1; 271 } else { 272 env->PAMask = PAMASK_BASE; 273 } 274 } 275 276 static inline int mips_vpe_active(CPUMIPSState *env) 277 { 278 int active = 1; 279 280 /* Check that the VPE is enabled. */ 281 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { 282 active = 0; 283 } 284 /* Check that the VPE is activated. */ 285 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { 286 active = 0; 287 } 288 289 /* 290 * Now verify that there are active thread contexts in the VPE. 291 * 292 * This assumes the CPU model will internally reschedule threads 293 * if the active one goes to sleep. If there are no threads available 294 * the active one will be in a sleeping state, and we can turn off 295 * the entire VPE. 296 */ 297 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { 298 /* TC is not activated. */ 299 active = 0; 300 } 301 if (env->active_tc.CP0_TCHalt & 1) { 302 /* TC is in halt state. */ 303 active = 0; 304 } 305 306 return active; 307 } 308 309 static inline int mips_vp_active(CPUMIPSState *env) 310 { 311 CPUState *other_cs = first_cpu; 312 313 /* Check if the VP disabled other VPs (which means the VP is enabled) */ 314 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { 315 return 1; 316 } 317 318 /* Check if the virtual processor is disabled due to a DVP */ 319 CPU_FOREACH(other_cs) { 320 MIPSCPU *other_cpu = MIPS_CPU(other_cs); 321 if ((&other_cpu->env != env) && 322 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { 323 return 0; 324 } 325 } 326 return 1; 327 } 328 329 static inline void compute_hflags(CPUMIPSState *env) 330 { 331 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | 332 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | 333 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 334 MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | 335 MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); 336 if (env->CP0_Status & (1 << CP0St_ERL)) { 337 env->hflags |= MIPS_HFLAG_ERL; 338 } 339 if (!(env->CP0_Status & (1 << CP0St_EXL)) && 340 !(env->CP0_Status & (1 << CP0St_ERL)) && 341 !(env->hflags & MIPS_HFLAG_DM)) { 342 env->hflags |= (env->CP0_Status >> CP0St_KSU) & 343 MIPS_HFLAG_KSU; 344 } 345 #if defined(TARGET_MIPS64) 346 if ((env->insn_flags & ISA_MIPS3) && 347 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || 348 (env->CP0_Status & (1 << CP0St_PX)) || 349 (env->CP0_Status & (1 << CP0St_UX)))) { 350 env->hflags |= MIPS_HFLAG_64; 351 } 352 353 if (!(env->insn_flags & ISA_MIPS3)) { 354 env->hflags |= MIPS_HFLAG_AWRAP; 355 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && 356 !(env->CP0_Status & (1 << CP0St_UX))) { 357 env->hflags |= MIPS_HFLAG_AWRAP; 358 } else if (env->insn_flags & ISA_MIPS64R6) { 359 /* Address wrapping for Supervisor and Kernel is specified in R6 */ 360 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && 361 !(env->CP0_Status & (1 << CP0St_SX))) || 362 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && 363 !(env->CP0_Status & (1 << CP0St_KX)))) { 364 env->hflags |= MIPS_HFLAG_AWRAP; 365 } 366 } 367 #endif 368 if (((env->CP0_Status & (1 << CP0St_CU0)) && 369 !(env->insn_flags & ISA_MIPS32R6)) || 370 !(env->hflags & MIPS_HFLAG_KSU)) { 371 env->hflags |= MIPS_HFLAG_CP0; 372 } 373 if (env->CP0_Status & (1 << CP0St_CU1)) { 374 env->hflags |= MIPS_HFLAG_FPU; 375 } 376 if (env->CP0_Status & (1 << CP0St_FR)) { 377 env->hflags |= MIPS_HFLAG_F64; 378 } 379 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && 380 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { 381 env->hflags |= MIPS_HFLAG_SBRI; 382 } 383 if (env->insn_flags & ASE_DSP_R3) { 384 /* 385 * Our cpu supports DSP R3 ASE, so enable 386 * access to DSP R3 resources. 387 */ 388 if (env->CP0_Status & (1 << CP0St_MX)) { 389 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | 390 MIPS_HFLAG_DSP_R3; 391 } 392 } else if (env->insn_flags & ASE_DSP_R2) { 393 /* 394 * Our cpu supports DSP R2 ASE, so enable 395 * access to DSP R2 resources. 396 */ 397 if (env->CP0_Status & (1 << CP0St_MX)) { 398 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; 399 } 400 401 } else if (env->insn_flags & ASE_DSP) { 402 /* 403 * Our cpu supports DSP ASE, so enable 404 * access to DSP resources. 405 */ 406 if (env->CP0_Status & (1 << CP0St_MX)) { 407 env->hflags |= MIPS_HFLAG_DSP; 408 } 409 410 } 411 if (env->insn_flags & ISA_MIPS32R2) { 412 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { 413 env->hflags |= MIPS_HFLAG_COP1X; 414 } 415 } else if (env->insn_flags & ISA_MIPS32) { 416 if (env->hflags & MIPS_HFLAG_64) { 417 env->hflags |= MIPS_HFLAG_COP1X; 418 } 419 } else if (env->insn_flags & ISA_MIPS4) { 420 /* 421 * All supported MIPS IV CPUs use the XX (CU3) to enable 422 * and disable the MIPS IV extensions to the MIPS III ISA. 423 * Some other MIPS IV CPUs ignore the bit, so the check here 424 * would be too restrictive for them. 425 */ 426 if (env->CP0_Status & (1U << CP0St_CU3)) { 427 env->hflags |= MIPS_HFLAG_COP1X; 428 } 429 } 430 if (env->insn_flags & ASE_MSA) { 431 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { 432 env->hflags |= MIPS_HFLAG_MSA; 433 } 434 } 435 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 436 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { 437 env->hflags |= MIPS_HFLAG_FRE; 438 } 439 } 440 if (env->CP0_Config3 & (1 << CP0C3_LPA)) { 441 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { 442 env->hflags |= MIPS_HFLAG_ELPA; 443 } 444 } 445 } 446 447 void cpu_mips_tlb_flush(CPUMIPSState *env); 448 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); 449 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); 450 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); 451 452 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, 453 int error_code, uintptr_t pc); 454 455 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, 456 uint32_t exception, 457 uintptr_t pc) 458 { 459 do_raise_exception_err(env, exception, 0, pc); 460 } 461 462 #endif 463