1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 #ifndef QEMU_ARM_CPU_QOM_H 21 #define QEMU_ARM_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 #include "qom/object.h" 25 26 struct arm_boot_info; 27 28 #define TYPE_ARM_CPU "arm-cpu" 29 30 OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) 31 32 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU 33 34 typedef struct ARMCPUInfo { 35 const char *name; 36 void (*initfn)(Object *obj); 37 void (*class_init)(ObjectClass *oc, void *data); 38 } ARMCPUInfo; 39 40 void arm_cpu_register(const ARMCPUInfo *info); 41 void aarch64_cpu_register(const ARMCPUInfo *info); 42 43 /** 44 * ARMCPUClass: 45 * @parent_realize: The parent class' realize handler. 46 * @parent_reset: The parent class' reset handler. 47 * 48 * An ARM CPU model. 49 */ 50 struct ARMCPUClass { 51 /*< private >*/ 52 CPUClass parent_class; 53 /*< public >*/ 54 55 const ARMCPUInfo *info; 56 DeviceRealize parent_realize; 57 DeviceReset parent_reset; 58 }; 59 60 61 #define TYPE_AARCH64_CPU "aarch64-cpu" 62 typedef struct AArch64CPUClass AArch64CPUClass; 63 DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, 64 TYPE_AARCH64_CPU) 65 66 struct AArch64CPUClass { 67 /*< private >*/ 68 ARMCPUClass parent_class; 69 /*< public >*/ 70 }; 71 72 void register_cp_regs_for_features(ARMCPU *cpu); 73 void init_cpreg_list(ARMCPU *cpu); 74 75 /* Callback functions for the generic timer's timers. */ 76 void arm_gt_ptimer_cb(void *opaque); 77 void arm_gt_vtimer_cb(void *opaque); 78 void arm_gt_htimer_cb(void *opaque); 79 void arm_gt_stimer_cb(void *opaque); 80 void arm_gt_hvtimer_cb(void *opaque); 81 82 #define ARM_AFF0_SHIFT 0 83 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 84 #define ARM_AFF1_SHIFT 8 85 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 86 #define ARM_AFF2_SHIFT 16 87 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 88 #define ARM_AFF3_SHIFT 32 89 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 90 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 91 92 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) 93 #define ARM64_AFFINITY_MASK \ 94 (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) 95 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 96 97 #endif 98