1 /* 2 * QEMU ARM CPU QOM header (target agnostic) 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 #ifndef QEMU_ARM_CPU_QOM_H 21 #define QEMU_ARM_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 #include "qom/object.h" 25 26 #define TYPE_ARM_CPU "arm-cpu" 27 28 OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) 29 30 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU 31 32 typedef struct ARMCPUInfo { 33 const char *name; 34 void (*initfn)(Object *obj); 35 void (*class_init)(ObjectClass *oc, void *data); 36 } ARMCPUInfo; 37 38 void arm_cpu_register(const ARMCPUInfo *info); 39 void aarch64_cpu_register(const ARMCPUInfo *info); 40 41 /** 42 * ARMCPUClass: 43 * @parent_realize: The parent class' realize handler. 44 * @parent_phases: The parent class' reset phase handlers. 45 * 46 * An ARM CPU model. 47 */ 48 struct ARMCPUClass { 49 CPUClass parent_class; 50 51 const ARMCPUInfo *info; 52 DeviceRealize parent_realize; 53 ResettablePhases parent_phases; 54 }; 55 56 57 #define TYPE_AARCH64_CPU "aarch64-cpu" 58 typedef struct AArch64CPUClass AArch64CPUClass; 59 DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, 60 TYPE_AARCH64_CPU) 61 62 struct AArch64CPUClass { 63 ARMCPUClass parent_class; 64 }; 65 66 void register_cp_regs_for_features(ARMCPU *cpu); 67 void init_cpreg_list(ARMCPU *cpu); 68 69 /* Callback functions for the generic timer's timers. */ 70 void arm_gt_ptimer_cb(void *opaque); 71 void arm_gt_vtimer_cb(void *opaque); 72 void arm_gt_htimer_cb(void *opaque); 73 void arm_gt_stimer_cb(void *opaque); 74 void arm_gt_hvtimer_cb(void *opaque); 75 76 #define ARM_AFF0_SHIFT 0 77 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 78 #define ARM_AFF1_SHIFT 8 79 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 80 #define ARM_AFF2_SHIFT 16 81 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 82 #define ARM_AFF3_SHIFT 32 83 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 84 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 85 86 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) 87 #define ARM64_AFFINITY_MASK \ 88 (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) 89 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 90 91 #endif 92