1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #include "qemu/osdep.h" 4 #include "qemu.h" 5 #include "loader.h" 6 #include "target_elf.h" 7 8 9 const char *get_elf_cpu_model(uint32_t eflags) 10 { 11 return "sh7785"; 12 } 13 14 enum { 15 SH_CPU_HAS_FPU = 0x0001, /* Hardware FPU support */ 16 SH_CPU_HAS_P2_FLUSH_BUG = 0x0002, /* Need to flush the cache in P2 area */ 17 SH_CPU_HAS_MMU_PAGE_ASSOC = 0x0004, /* SH3: TLB way selection bit support */ 18 SH_CPU_HAS_DSP = 0x0008, /* SH-DSP: DSP support */ 19 SH_CPU_HAS_PERF_COUNTER = 0x0010, /* Hardware performance counters */ 20 SH_CPU_HAS_PTEA = 0x0020, /* PTEA register */ 21 SH_CPU_HAS_LLSC = 0x0040, /* movli.l/movco.l */ 22 SH_CPU_HAS_L2_CACHE = 0x0080, /* Secondary cache / URAM */ 23 SH_CPU_HAS_OP32 = 0x0100, /* 32-bit instruction support */ 24 SH_CPU_HAS_PTEAEX = 0x0200, /* PTE ASID Extension support */ 25 }; 26 27 abi_ulong get_elf_hwcap(CPUState *cs) 28 { 29 SuperHCPU *cpu = SUPERH_CPU(cs); 30 abi_ulong hwcap = 0; 31 32 hwcap |= SH_CPU_HAS_FPU; 33 34 if (cpu->env.features & SH_FEATURE_SH4A) { 35 hwcap |= SH_CPU_HAS_LLSC; 36 } 37 38 return hwcap; 39 } 40 41 void elf_core_copy_regs(target_elf_gregset_t *r, const CPUSH4State *env) 42 { 43 for (int i = 0; i < 16; i++) { 44 r->pt.regs[i] = tswapal(env->gregs[i]); 45 } 46 47 r->pt.pc = tswapal(env->pc); 48 r->pt.pr = tswapal(env->pr); 49 r->pt.sr = tswapal(env->sr); 50 r->pt.gbr = tswapal(env->gbr); 51 r->pt.mach = tswapal(env->mach); 52 r->pt.macl = tswapal(env->macl); 53 } 54