1*5706b006SChalapathi V /* 2*5706b006SChalapathi V * QEMU PowerPC N1 chiplet model 3*5706b006SChalapathi V * 4*5706b006SChalapathi V * Copyright (c) 2023, IBM Corporation. 5*5706b006SChalapathi V * 6*5706b006SChalapathi V * SPDX-License-Identifier: GPL-2.0-or-later 7*5706b006SChalapathi V */ 8*5706b006SChalapathi V 9*5706b006SChalapathi V #ifndef PPC_PNV_N1_CHIPLET_H 10*5706b006SChalapathi V #define PPC_PNV_N1_CHIPLET_H 11*5706b006SChalapathi V 12*5706b006SChalapathi V #include "hw/ppc/pnv_nest_pervasive.h" 13*5706b006SChalapathi V 14*5706b006SChalapathi V #define TYPE_PNV_N1_CHIPLET "pnv-N1-chiplet" 15*5706b006SChalapathi V #define PNV_N1_CHIPLET(obj) OBJECT_CHECK(PnvN1Chiplet, (obj), TYPE_PNV_N1_CHIPLET) 16*5706b006SChalapathi V 17*5706b006SChalapathi V typedef struct PnvPbScom { 18*5706b006SChalapathi V uint64_t mode; 19*5706b006SChalapathi V uint64_t hp_mode2_curr; 20*5706b006SChalapathi V } PnvPbScom; 21*5706b006SChalapathi V 22*5706b006SChalapathi V typedef struct PnvN1Chiplet { 23*5706b006SChalapathi V DeviceState parent; 24*5706b006SChalapathi V MemoryRegion xscom_pb_eq_mr; 25*5706b006SChalapathi V MemoryRegion xscom_pb_es_mr; 26*5706b006SChalapathi V PnvNestChipletPervasive nest_pervasive; /* common pervasive chiplet unit */ 27*5706b006SChalapathi V #define PNV_PB_SCOM_EQ_SIZE 8 28*5706b006SChalapathi V PnvPbScom eq[PNV_PB_SCOM_EQ_SIZE]; 29*5706b006SChalapathi V #define PNV_PB_SCOM_ES_SIZE 4 30*5706b006SChalapathi V PnvPbScom es[PNV_PB_SCOM_ES_SIZE]; 31*5706b006SChalapathi V } PnvN1Chiplet; 32*5706b006SChalapathi V #endif /*PPC_PNV_N1_CHIPLET_H */ 33