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5706b006 |
| 23-Jan-2024 |
Chalapathi V <chalapathi.v@linux.ibm.com> |
hw/ppc: Add N1 chiplet model
The N1 chiplet handle the high speed i/o traffic over PCIe and others. The N1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet contro
hw/ppc: Add N1 chiplet model
The N1 chiplet handle the high speed i/o traffic over PCIe and others. The N1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more.
This commit creates a N1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented.
This commit also implement the read/write method for the powerbus scom registers
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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