1*a017f53eSJackson Donaldson /* 2*a017f53eSJackson Donaldson * MAX78000 Global Control Register 3*a017f53eSJackson Donaldson * 4*a017f53eSJackson Donaldson * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com> 5*a017f53eSJackson Donaldson * 6*a017f53eSJackson Donaldson * SPDX-License-Identifier: GPL-2.0-or-later 7*a017f53eSJackson Donaldson */ 8*a017f53eSJackson Donaldson #ifndef HW_MAX78000_GCR_H 9*a017f53eSJackson Donaldson #define HW_MAX78000_GCR_H 10*a017f53eSJackson Donaldson 11*a017f53eSJackson Donaldson #include "hw/sysbus.h" 12*a017f53eSJackson Donaldson #include "qom/object.h" 13*a017f53eSJackson Donaldson 14*a017f53eSJackson Donaldson #define TYPE_MAX78000_GCR "max78000-gcr" 15*a017f53eSJackson Donaldson OBJECT_DECLARE_SIMPLE_TYPE(Max78000GcrState, MAX78000_GCR) 16*a017f53eSJackson Donaldson 17*a017f53eSJackson Donaldson #define SYSCTRL 0x0 18*a017f53eSJackson Donaldson #define RST0 0x4 19*a017f53eSJackson Donaldson #define CLKCTRL 0x8 20*a017f53eSJackson Donaldson #define PM 0xc 21*a017f53eSJackson Donaldson #define PCLKDIV 0x18 22*a017f53eSJackson Donaldson #define PCLKDIS0 0x24 23*a017f53eSJackson Donaldson #define MEMCTRL 0x28 24*a017f53eSJackson Donaldson #define MEMZ 0x2c 25*a017f53eSJackson Donaldson #define SYSST 0x40 26*a017f53eSJackson Donaldson #define RST1 0x44 27*a017f53eSJackson Donaldson #define PCKDIS1 0x48 28*a017f53eSJackson Donaldson #define EVENTEN 0x4c 29*a017f53eSJackson Donaldson #define REVISION 0x50 30*a017f53eSJackson Donaldson #define SYSIE 0x54 31*a017f53eSJackson Donaldson #define ECCERR 0x64 32*a017f53eSJackson Donaldson #define ECCED 0x68 33*a017f53eSJackson Donaldson #define ECCIE 0x6c 34*a017f53eSJackson Donaldson #define ECCADDR 0x70 35*a017f53eSJackson Donaldson 36*a017f53eSJackson Donaldson /* RST0 */ 37*a017f53eSJackson Donaldson #define SYSTEM_RESET (1 << 31) 38*a017f53eSJackson Donaldson #define PERIPHERAL_RESET (1 << 30) 39*a017f53eSJackson Donaldson #define SOFT_RESET (1 << 29) 40*a017f53eSJackson Donaldson #define UART2_RESET (1 << 28) 41*a017f53eSJackson Donaldson 42*a017f53eSJackson Donaldson #define ADC_RESET (1 << 26) 43*a017f53eSJackson Donaldson #define CNN_RESET (1 << 25) 44*a017f53eSJackson Donaldson #define TRNG_RESET (1 << 24) 45*a017f53eSJackson Donaldson 46*a017f53eSJackson Donaldson #define RTC_RESET (1 << 17) 47*a017f53eSJackson Donaldson #define I2C0_RESET (1 << 16) 48*a017f53eSJackson Donaldson 49*a017f53eSJackson Donaldson #define SPI1_RESET (1 << 13) 50*a017f53eSJackson Donaldson #define UART1_RESET (1 << 12) 51*a017f53eSJackson Donaldson #define UART0_RESET (1 << 11) 52*a017f53eSJackson Donaldson 53*a017f53eSJackson Donaldson #define TMR3_RESET (1 << 8) 54*a017f53eSJackson Donaldson #define TMR2_RESET (1 << 7) 55*a017f53eSJackson Donaldson #define TMR1_RESET (1 << 6) 56*a017f53eSJackson Donaldson #define TMR0_RESET (1 << 5) 57*a017f53eSJackson Donaldson 58*a017f53eSJackson Donaldson #define GPIO1_RESET (1 << 3) 59*a017f53eSJackson Donaldson #define GPIO0_RESET (1 << 2) 60*a017f53eSJackson Donaldson #define WDT0_RESET (1 << 1) 61*a017f53eSJackson Donaldson #define DMA_RESET (1 << 0) 62*a017f53eSJackson Donaldson 63*a017f53eSJackson Donaldson /* CLKCTRL */ 64*a017f53eSJackson Donaldson #define SYSCLK_RDY (1 << 13) 65*a017f53eSJackson Donaldson 66*a017f53eSJackson Donaldson /* MEMZ */ 67*a017f53eSJackson Donaldson #define ram0 (1 << 0) 68*a017f53eSJackson Donaldson #define ram1 (1 << 1) 69*a017f53eSJackson Donaldson #define ram2 (1 << 2) 70*a017f53eSJackson Donaldson #define ram3 (1 << 3) 71*a017f53eSJackson Donaldson 72*a017f53eSJackson Donaldson /* RST1 */ 73*a017f53eSJackson Donaldson #define CPU1_RESET (1 << 31) 74*a017f53eSJackson Donaldson 75*a017f53eSJackson Donaldson #define SIMO_RESET (1 << 25) 76*a017f53eSJackson Donaldson #define DVS_RESET (1 << 24) 77*a017f53eSJackson Donaldson 78*a017f53eSJackson Donaldson #define I2C2_RESET (1 << 20) 79*a017f53eSJackson Donaldson #define I2S_RESET (1 << 19) 80*a017f53eSJackson Donaldson 81*a017f53eSJackson Donaldson #define SMPHR_RESET (1 << 16) 82*a017f53eSJackson Donaldson 83*a017f53eSJackson Donaldson #define SPI0_RESET (1 << 11) 84*a017f53eSJackson Donaldson #define AES_RESET (1 << 10) 85*a017f53eSJackson Donaldson #define CRC_RESET (1 << 9) 86*a017f53eSJackson Donaldson 87*a017f53eSJackson Donaldson #define PT_RESET (1 << 1) 88*a017f53eSJackson Donaldson #define I2C1_RESET (1 << 0) 89*a017f53eSJackson Donaldson 90*a017f53eSJackson Donaldson 91*a017f53eSJackson Donaldson #define SYSRAM0_START 0x20000000 92*a017f53eSJackson Donaldson #define SYSRAM1_START 0x20008000 93*a017f53eSJackson Donaldson #define SYSRAM2_START 0x20010000 94*a017f53eSJackson Donaldson #define SYSRAM3_START 0x2001C000 95*a017f53eSJackson Donaldson 96*a017f53eSJackson Donaldson struct Max78000GcrState { 97*a017f53eSJackson Donaldson SysBusDevice parent_obj; 98*a017f53eSJackson Donaldson 99*a017f53eSJackson Donaldson MemoryRegion mmio; 100*a017f53eSJackson Donaldson 101*a017f53eSJackson Donaldson uint32_t sysctrl; 102*a017f53eSJackson Donaldson uint32_t rst0; 103*a017f53eSJackson Donaldson uint32_t clkctrl; 104*a017f53eSJackson Donaldson uint32_t pm; 105*a017f53eSJackson Donaldson uint32_t pclkdiv; 106*a017f53eSJackson Donaldson uint32_t pclkdis0; 107*a017f53eSJackson Donaldson uint32_t memctrl; 108*a017f53eSJackson Donaldson uint32_t memz; 109*a017f53eSJackson Donaldson uint32_t sysst; 110*a017f53eSJackson Donaldson uint32_t rst1; 111*a017f53eSJackson Donaldson uint32_t pckdis1; 112*a017f53eSJackson Donaldson uint32_t eventen; 113*a017f53eSJackson Donaldson uint32_t revision; 114*a017f53eSJackson Donaldson uint32_t sysie; 115*a017f53eSJackson Donaldson uint32_t eccerr; 116*a017f53eSJackson Donaldson uint32_t ecced; 117*a017f53eSJackson Donaldson uint32_t eccie; 118*a017f53eSJackson Donaldson uint32_t eccaddr; 119*a017f53eSJackson Donaldson 120*a017f53eSJackson Donaldson MemoryRegion *sram; 121*a017f53eSJackson Donaldson AddressSpace sram_as; 122*a017f53eSJackson Donaldson 123*a017f53eSJackson Donaldson DeviceState *uart0; 124*a017f53eSJackson Donaldson DeviceState *uart1; 125*a017f53eSJackson Donaldson DeviceState *uart2; 126*a017f53eSJackson Donaldson 127*a017f53eSJackson Donaldson }; 128*a017f53eSJackson Donaldson 129*a017f53eSJackson Donaldson #endif 130