1 /* 2 * MAX78000 Global Control Register 3 * 4 * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 #ifndef HW_MAX78000_GCR_H 9 #define HW_MAX78000_GCR_H 10 11 #include "hw/sysbus.h" 12 #include "qom/object.h" 13 14 #define TYPE_MAX78000_GCR "max78000-gcr" 15 OBJECT_DECLARE_SIMPLE_TYPE(Max78000GcrState, MAX78000_GCR) 16 17 #define SYSCTRL 0x0 18 #define RST0 0x4 19 #define CLKCTRL 0x8 20 #define PM 0xc 21 #define PCLKDIV 0x18 22 #define PCLKDIS0 0x24 23 #define MEMCTRL 0x28 24 #define MEMZ 0x2c 25 #define SYSST 0x40 26 #define RST1 0x44 27 #define PCKDIS1 0x48 28 #define EVENTEN 0x4c 29 #define REVISION 0x50 30 #define SYSIE 0x54 31 #define ECCERR 0x64 32 #define ECCED 0x68 33 #define ECCIE 0x6c 34 #define ECCADDR 0x70 35 36 /* RST0 */ 37 #define SYSTEM_RESET (1 << 31) 38 #define PERIPHERAL_RESET (1 << 30) 39 #define SOFT_RESET (1 << 29) 40 #define UART2_RESET (1 << 28) 41 42 #define ADC_RESET (1 << 26) 43 #define CNN_RESET (1 << 25) 44 #define TRNG_RESET (1 << 24) 45 46 #define RTC_RESET (1 << 17) 47 #define I2C0_RESET (1 << 16) 48 49 #define SPI1_RESET (1 << 13) 50 #define UART1_RESET (1 << 12) 51 #define UART0_RESET (1 << 11) 52 53 #define TMR3_RESET (1 << 8) 54 #define TMR2_RESET (1 << 7) 55 #define TMR1_RESET (1 << 6) 56 #define TMR0_RESET (1 << 5) 57 58 #define GPIO1_RESET (1 << 3) 59 #define GPIO0_RESET (1 << 2) 60 #define WDT0_RESET (1 << 1) 61 #define DMA_RESET (1 << 0) 62 63 /* CLKCTRL */ 64 #define SYSCLK_RDY (1 << 13) 65 66 /* MEMZ */ 67 #define ram0 (1 << 0) 68 #define ram1 (1 << 1) 69 #define ram2 (1 << 2) 70 #define ram3 (1 << 3) 71 72 /* RST1 */ 73 #define CPU1_RESET (1 << 31) 74 75 #define SIMO_RESET (1 << 25) 76 #define DVS_RESET (1 << 24) 77 78 #define I2C2_RESET (1 << 20) 79 #define I2S_RESET (1 << 19) 80 81 #define SMPHR_RESET (1 << 16) 82 83 #define SPI0_RESET (1 << 11) 84 #define AES_RESET (1 << 10) 85 #define CRC_RESET (1 << 9) 86 87 #define PT_RESET (1 << 1) 88 #define I2C1_RESET (1 << 0) 89 90 91 #define SYSRAM0_START 0x20000000 92 #define SYSRAM1_START 0x20008000 93 #define SYSRAM2_START 0x20010000 94 #define SYSRAM3_START 0x2001C000 95 96 struct Max78000GcrState { 97 SysBusDevice parent_obj; 98 99 MemoryRegion mmio; 100 101 uint32_t sysctrl; 102 uint32_t rst0; 103 uint32_t clkctrl; 104 uint32_t pm; 105 uint32_t pclkdiv; 106 uint32_t pclkdis0; 107 uint32_t memctrl; 108 uint32_t memz; 109 uint32_t sysst; 110 uint32_t rst1; 111 uint32_t pckdis1; 112 uint32_t eventen; 113 uint32_t revision; 114 uint32_t sysie; 115 uint32_t eccerr; 116 uint32_t ecced; 117 uint32_t eccie; 118 uint32_t eccaddr; 119 120 MemoryRegion *sram; 121 AddressSpace sram_as; 122 123 DeviceState *uart0; 124 DeviceState *uart1; 125 DeviceState *uart2; 126 DeviceState *trng; 127 DeviceState *aes; 128 129 }; 130 131 #endif 132