1*c46cabd4SAmir Gonnen /* 2*c46cabd4SAmir Gonnen * Vectored Interrupt Controller for nios2 processor 3*c46cabd4SAmir Gonnen * 4*c46cabd4SAmir Gonnen * Copyright (c) 2022 Neuroblade 5*c46cabd4SAmir Gonnen * 6*c46cabd4SAmir Gonnen * Interface: 7*c46cabd4SAmir Gonnen * QOM property "cpu": link to the Nios2 CPU (must be set) 8*c46cabd4SAmir Gonnen * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines 9*c46cabd4SAmir Gonnen * IRQ should be connected to nios2 IRQ0. 10*c46cabd4SAmir Gonnen * 11*c46cabd4SAmir Gonnen * Reference: "Embedded Peripherals IP User Guide 12*c46cabd4SAmir Gonnen * for Intel® Quartus® Prime Design Suite: 21.4" 13*c46cabd4SAmir Gonnen * Chapter 38 "Vectored Interrupt Controller Core" 14*c46cabd4SAmir Gonnen * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html 15*c46cabd4SAmir Gonnen * 16*c46cabd4SAmir Gonnen * Permission is hereby granted, free of charge, to any person obtaining a copy 17*c46cabd4SAmir Gonnen * of this software and associated documentation files (the "Software"), to deal 18*c46cabd4SAmir Gonnen * in the Software without restriction, including without limitation the rights 19*c46cabd4SAmir Gonnen * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 20*c46cabd4SAmir Gonnen * copies of the Software, and to permit persons to whom the Software is 21*c46cabd4SAmir Gonnen * furnished to do so, subject to the following conditions: 22*c46cabd4SAmir Gonnen * 23*c46cabd4SAmir Gonnen * The above copyright notice and this permission notice shall be included in 24*c46cabd4SAmir Gonnen * all copies or substantial portions of the Software. 25*c46cabd4SAmir Gonnen * 26*c46cabd4SAmir Gonnen * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 27*c46cabd4SAmir Gonnen * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 28*c46cabd4SAmir Gonnen * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 29*c46cabd4SAmir Gonnen * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 30*c46cabd4SAmir Gonnen * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 31*c46cabd4SAmir Gonnen * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 32*c46cabd4SAmir Gonnen * THE SOFTWARE. 33*c46cabd4SAmir Gonnen */ 34*c46cabd4SAmir Gonnen 35*c46cabd4SAmir Gonnen #ifndef HW_INTC_NIOS2_VIC 36*c46cabd4SAmir Gonnen #define HW_INTC_NIOS2_VIC 37*c46cabd4SAmir Gonnen 38*c46cabd4SAmir Gonnen #define TYPE_NIOS2_VIC "nios2-vic" 39*c46cabd4SAmir Gonnen OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC) 40*c46cabd4SAmir Gonnen 41*c46cabd4SAmir Gonnen #define NIOS2_VIC_MAX_IRQ 32 42*c46cabd4SAmir Gonnen 43*c46cabd4SAmir Gonnen struct Nios2VIC { 44*c46cabd4SAmir Gonnen /*< private >*/ 45*c46cabd4SAmir Gonnen SysBusDevice parent_obj; 46*c46cabd4SAmir Gonnen 47*c46cabd4SAmir Gonnen /*< public >*/ 48*c46cabd4SAmir Gonnen qemu_irq output_int; 49*c46cabd4SAmir Gonnen 50*c46cabd4SAmir Gonnen /* properties */ 51*c46cabd4SAmir Gonnen CPUState *cpu; 52*c46cabd4SAmir Gonnen MemoryRegion csr; 53*c46cabd4SAmir Gonnen 54*c46cabd4SAmir Gonnen uint32_t int_config[NIOS2_VIC_MAX_IRQ]; 55*c46cabd4SAmir Gonnen uint32_t vic_config; 56*c46cabd4SAmir Gonnen uint32_t int_raw_status; 57*c46cabd4SAmir Gonnen uint32_t int_enable; 58*c46cabd4SAmir Gonnen uint32_t sw_int; 59*c46cabd4SAmir Gonnen uint32_t vic_status; 60*c46cabd4SAmir Gonnen uint32_t vec_tbl_base; 61*c46cabd4SAmir Gonnen uint32_t vec_tbl_addr; 62*c46cabd4SAmir Gonnen }; 63*c46cabd4SAmir Gonnen 64*c46cabd4SAmir Gonnen #endif /* HW_INTC_NIOS2_VIC */ 65