1 /* 2 * Vectored Interrupt Controller for nios2 processor 3 * 4 * Copyright (c) 2022 Neuroblade 5 * 6 * Interface: 7 * QOM property "cpu": link to the Nios2 CPU (must be set) 8 * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines 9 * IRQ should be connected to nios2 IRQ0. 10 * 11 * Reference: "Embedded Peripherals IP User Guide 12 * for Intel® Quartus® Prime Design Suite: 21.4" 13 * Chapter 38 "Vectored Interrupt Controller Core" 14 * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a copy 17 * of this software and associated documentation files (the "Software"), to deal 18 * in the Software without restriction, including without limitation the rights 19 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 20 * copies of the Software, and to permit persons to whom the Software is 21 * furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice shall be included in 24 * all copies or substantial portions of the Software. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 27 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 28 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 29 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 30 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 31 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 32 * THE SOFTWARE. 33 */ 34 35 #ifndef HW_INTC_NIOS2_VIC_H 36 #define HW_INTC_NIOS2_VIC_H 37 38 #include "hw/sysbus.h" 39 40 #define TYPE_NIOS2_VIC "nios2-vic" 41 OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC) 42 43 #define NIOS2_VIC_MAX_IRQ 32 44 45 struct Nios2VIC { 46 /*< private >*/ 47 SysBusDevice parent_obj; 48 49 /*< public >*/ 50 qemu_irq output_int; 51 52 /* properties */ 53 CPUState *cpu; 54 MemoryRegion csr; 55 56 uint32_t int_config[NIOS2_VIC_MAX_IRQ]; 57 uint32_t vic_config; 58 uint32_t int_raw_status; 59 uint32_t int_enable; 60 uint32_t sw_int; 61 uint32_t vic_status; 62 uint32_t vec_tbl_base; 63 uint32_t vec_tbl_addr; 64 }; 65 66 #endif /* HW_INTC_NIOS2_VIC_H */ 67