1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 #include "hw/registerfields.h" 5 6 typedef struct QEMU_PACKED NvmeBar { 7 uint64_t cap; 8 uint32_t vs; 9 uint32_t intms; 10 uint32_t intmc; 11 uint32_t cc; 12 uint8_t rsvd24[4]; 13 uint32_t csts; 14 uint32_t nssr; 15 uint32_t aqa; 16 uint64_t asq; 17 uint64_t acq; 18 uint32_t cmbloc; 19 uint32_t cmbsz; 20 uint32_t bpinfo; 21 uint32_t bprsel; 22 uint64_t bpmbl; 23 uint64_t cmbmsc; 24 uint32_t cmbsts; 25 uint8_t rsvd92[3492]; 26 uint32_t pmrcap; 27 uint32_t pmrctl; 28 uint32_t pmrsts; 29 uint32_t pmrebs; 30 uint32_t pmrswtp; 31 uint32_t pmrmscl; 32 uint32_t pmrmscu; 33 uint8_t css[484]; 34 } NvmeBar; 35 36 enum NvmeBarRegs { 37 NVME_REG_CAP = offsetof(NvmeBar, cap), 38 NVME_REG_VS = offsetof(NvmeBar, vs), 39 NVME_REG_INTMS = offsetof(NvmeBar, intms), 40 NVME_REG_INTMC = offsetof(NvmeBar, intmc), 41 NVME_REG_CC = offsetof(NvmeBar, cc), 42 NVME_REG_CSTS = offsetof(NvmeBar, csts), 43 NVME_REG_NSSR = offsetof(NvmeBar, nssr), 44 NVME_REG_AQA = offsetof(NvmeBar, aqa), 45 NVME_REG_ASQ = offsetof(NvmeBar, asq), 46 NVME_REG_ACQ = offsetof(NvmeBar, acq), 47 NVME_REG_CMBLOC = offsetof(NvmeBar, cmbloc), 48 NVME_REG_CMBSZ = offsetof(NvmeBar, cmbsz), 49 NVME_REG_BPINFO = offsetof(NvmeBar, bpinfo), 50 NVME_REG_BPRSEL = offsetof(NvmeBar, bprsel), 51 NVME_REG_BPMBL = offsetof(NvmeBar, bpmbl), 52 NVME_REG_CMBMSC = offsetof(NvmeBar, cmbmsc), 53 NVME_REG_CMBSTS = offsetof(NvmeBar, cmbsts), 54 NVME_REG_PMRCAP = offsetof(NvmeBar, pmrcap), 55 NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl), 56 NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts), 57 NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs), 58 NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp), 59 NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl), 60 NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu), 61 }; 62 63 typedef struct QEMU_PACKED NvmeEndGrpLog { 64 uint8_t critical_warning; 65 uint8_t rsvd[2]; 66 uint8_t avail_spare; 67 uint8_t avail_spare_thres; 68 uint8_t percet_used; 69 uint8_t rsvd1[26]; 70 uint64_t end_estimate[2]; 71 uint64_t data_units_read[2]; 72 uint64_t data_units_written[2]; 73 uint64_t media_units_written[2]; 74 uint64_t host_read_commands[2]; 75 uint64_t host_write_commands[2]; 76 uint64_t media_integrity_errors[2]; 77 uint64_t no_err_info_log_entries[2]; 78 uint8_t rsvd2[352]; 79 } NvmeEndGrpLog; 80 81 enum NvmeCapShift { 82 CAP_MQES_SHIFT = 0, 83 CAP_CQR_SHIFT = 16, 84 CAP_AMS_SHIFT = 17, 85 CAP_TO_SHIFT = 24, 86 CAP_DSTRD_SHIFT = 32, 87 CAP_NSSRS_SHIFT = 36, 88 CAP_CSS_SHIFT = 37, 89 CAP_MPSMIN_SHIFT = 48, 90 CAP_MPSMAX_SHIFT = 52, 91 CAP_PMRS_SHIFT = 56, 92 CAP_CMBS_SHIFT = 57, 93 }; 94 95 enum NvmeCapMask { 96 CAP_MQES_MASK = 0xffff, 97 CAP_CQR_MASK = 0x1, 98 CAP_AMS_MASK = 0x3, 99 CAP_TO_MASK = 0xff, 100 CAP_DSTRD_MASK = 0xf, 101 CAP_NSSRS_MASK = 0x1, 102 CAP_CSS_MASK = 0xff, 103 CAP_MPSMIN_MASK = 0xf, 104 CAP_MPSMAX_MASK = 0xf, 105 CAP_PMRS_MASK = 0x1, 106 CAP_CMBS_MASK = 0x1, 107 }; 108 109 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 110 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 111 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 112 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 113 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 114 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 115 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 116 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 117 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 118 #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) 119 #define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK) 120 121 #define NVME_CAP_SET_MQES(cap, val) \ 122 ((cap) |= (uint64_t)((val) & CAP_MQES_MASK) << CAP_MQES_SHIFT) 123 #define NVME_CAP_SET_CQR(cap, val) \ 124 ((cap) |= (uint64_t)((val) & CAP_CQR_MASK) << CAP_CQR_SHIFT) 125 #define NVME_CAP_SET_AMS(cap, val) \ 126 ((cap) |= (uint64_t)((val) & CAP_AMS_MASK) << CAP_AMS_SHIFT) 127 #define NVME_CAP_SET_TO(cap, val) \ 128 ((cap) |= (uint64_t)((val) & CAP_TO_MASK) << CAP_TO_SHIFT) 129 #define NVME_CAP_SET_DSTRD(cap, val) \ 130 ((cap) |= (uint64_t)((val) & CAP_DSTRD_MASK) << CAP_DSTRD_SHIFT) 131 #define NVME_CAP_SET_NSSRS(cap, val) \ 132 ((cap) |= (uint64_t)((val) & CAP_NSSRS_MASK) << CAP_NSSRS_SHIFT) 133 #define NVME_CAP_SET_CSS(cap, val) \ 134 ((cap) |= (uint64_t)((val) & CAP_CSS_MASK) << CAP_CSS_SHIFT) 135 #define NVME_CAP_SET_MPSMIN(cap, val) \ 136 ((cap) |= (uint64_t)((val) & CAP_MPSMIN_MASK) << CAP_MPSMIN_SHIFT) 137 #define NVME_CAP_SET_MPSMAX(cap, val) \ 138 ((cap) |= (uint64_t)((val) & CAP_MPSMAX_MASK) << CAP_MPSMAX_SHIFT) 139 #define NVME_CAP_SET_PMRS(cap, val) \ 140 ((cap) |= (uint64_t)((val) & CAP_PMRS_MASK) << CAP_PMRS_SHIFT) 141 #define NVME_CAP_SET_CMBS(cap, val) \ 142 ((cap) |= (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT) 143 144 enum NvmeCapCss { 145 NVME_CAP_CSS_NVM = 1 << 0, 146 NVME_CAP_CSS_CSI_SUPP = 1 << 6, 147 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 148 }; 149 150 enum NvmeCcShift { 151 CC_EN_SHIFT = 0, 152 CC_CSS_SHIFT = 4, 153 CC_MPS_SHIFT = 7, 154 CC_AMS_SHIFT = 11, 155 CC_SHN_SHIFT = 14, 156 CC_IOSQES_SHIFT = 16, 157 CC_IOCQES_SHIFT = 20, 158 }; 159 160 enum NvmeCcMask { 161 CC_EN_MASK = 0x1, 162 CC_CSS_MASK = 0x7, 163 CC_MPS_MASK = 0xf, 164 CC_AMS_MASK = 0x7, 165 CC_SHN_MASK = 0x3, 166 CC_IOSQES_MASK = 0xf, 167 CC_IOCQES_MASK = 0xf, 168 }; 169 170 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 171 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 172 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 173 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 174 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 175 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 176 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 177 178 enum NvmeCcCss { 179 NVME_CC_CSS_NVM = 0x0, 180 NVME_CC_CSS_CSI = 0x6, 181 NVME_CC_CSS_ADMIN_ONLY = 0x7, 182 }; 183 184 #define NVME_SET_CC_EN(cc, val) \ 185 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 186 #define NVME_SET_CC_CSS(cc, val) \ 187 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 188 #define NVME_SET_CC_MPS(cc, val) \ 189 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 190 #define NVME_SET_CC_AMS(cc, val) \ 191 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 192 #define NVME_SET_CC_SHN(cc, val) \ 193 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 194 #define NVME_SET_CC_IOSQES(cc, val) \ 195 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 196 #define NVME_SET_CC_IOCQES(cc, val) \ 197 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 198 199 enum NvmeCstsShift { 200 CSTS_RDY_SHIFT = 0, 201 CSTS_CFS_SHIFT = 1, 202 CSTS_SHST_SHIFT = 2, 203 CSTS_NSSRO_SHIFT = 4, 204 }; 205 206 enum NvmeCstsMask { 207 CSTS_RDY_MASK = 0x1, 208 CSTS_CFS_MASK = 0x1, 209 CSTS_SHST_MASK = 0x3, 210 CSTS_NSSRO_MASK = 0x1, 211 }; 212 213 enum NvmeCsts { 214 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 215 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 216 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 217 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 218 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 219 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 220 }; 221 222 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 223 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 224 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 225 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 226 227 enum NvmeAqaShift { 228 AQA_ASQS_SHIFT = 0, 229 AQA_ACQS_SHIFT = 16, 230 }; 231 232 enum NvmeAqaMask { 233 AQA_ASQS_MASK = 0xfff, 234 AQA_ACQS_MASK = 0xfff, 235 }; 236 237 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 238 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 239 240 enum NvmeCmblocShift { 241 CMBLOC_BIR_SHIFT = 0, 242 CMBLOC_CQMMS_SHIFT = 3, 243 CMBLOC_CQPDS_SHIFT = 4, 244 CMBLOC_CDPMLS_SHIFT = 5, 245 CMBLOC_CDPCILS_SHIFT = 6, 246 CMBLOC_CDMMMS_SHIFT = 7, 247 CMBLOC_CQDA_SHIFT = 8, 248 CMBLOC_OFST_SHIFT = 12, 249 }; 250 251 enum NvmeCmblocMask { 252 CMBLOC_BIR_MASK = 0x7, 253 CMBLOC_CQMMS_MASK = 0x1, 254 CMBLOC_CQPDS_MASK = 0x1, 255 CMBLOC_CDPMLS_MASK = 0x1, 256 CMBLOC_CDPCILS_MASK = 0x1, 257 CMBLOC_CDMMMS_MASK = 0x1, 258 CMBLOC_CQDA_MASK = 0x1, 259 CMBLOC_OFST_MASK = 0xfffff, 260 }; 261 262 #define NVME_CMBLOC_BIR(cmbloc) \ 263 ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK) 264 #define NVME_CMBLOC_CQMMS(cmbloc) \ 265 ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK) 266 #define NVME_CMBLOC_CQPDS(cmbloc) \ 267 ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK) 268 #define NVME_CMBLOC_CDPMLS(cmbloc) \ 269 ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK) 270 #define NVME_CMBLOC_CDPCILS(cmbloc) \ 271 ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK) 272 #define NVME_CMBLOC_CDMMMS(cmbloc) \ 273 ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK) 274 #define NVME_CMBLOC_CQDA(cmbloc) \ 275 ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK) 276 #define NVME_CMBLOC_OFST(cmbloc) \ 277 ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK) 278 279 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 280 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 281 #define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \ 282 (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT) 283 #define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \ 284 (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT) 285 #define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \ 286 (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT) 287 #define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \ 288 (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT) 289 #define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \ 290 (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT) 291 #define NVME_CMBLOC_SET_CQDA(cmbloc, val) \ 292 (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT) 293 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 294 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 295 296 #define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \ 297 (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT) 298 299 enum NvmeCmbszShift { 300 CMBSZ_SQS_SHIFT = 0, 301 CMBSZ_CQS_SHIFT = 1, 302 CMBSZ_LISTS_SHIFT = 2, 303 CMBSZ_RDS_SHIFT = 3, 304 CMBSZ_WDS_SHIFT = 4, 305 CMBSZ_SZU_SHIFT = 8, 306 CMBSZ_SZ_SHIFT = 12, 307 }; 308 309 enum NvmeCmbszMask { 310 CMBSZ_SQS_MASK = 0x1, 311 CMBSZ_CQS_MASK = 0x1, 312 CMBSZ_LISTS_MASK = 0x1, 313 CMBSZ_RDS_MASK = 0x1, 314 CMBSZ_WDS_MASK = 0x1, 315 CMBSZ_SZU_MASK = 0xf, 316 CMBSZ_SZ_MASK = 0xfffff, 317 }; 318 319 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 320 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 321 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 322 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 323 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 324 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 325 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 326 327 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 328 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 329 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 330 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 331 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 332 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 333 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 334 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 335 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 336 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 337 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 338 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 339 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 340 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 341 342 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 343 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 344 345 enum NvmeCmbmscShift { 346 CMBMSC_CRE_SHIFT = 0, 347 CMBMSC_CMSE_SHIFT = 1, 348 CMBMSC_CBA_SHIFT = 12, 349 }; 350 351 enum NvmeCmbmscMask { 352 CMBMSC_CRE_MASK = 0x1, 353 CMBMSC_CMSE_MASK = 0x1, 354 CMBMSC_CBA_MASK = ((1ULL << 52) - 1), 355 }; 356 357 #define NVME_CMBMSC_CRE(cmbmsc) \ 358 ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK) 359 #define NVME_CMBMSC_CMSE(cmbmsc) \ 360 ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK) 361 #define NVME_CMBMSC_CBA(cmbmsc) \ 362 ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK) 363 364 365 #define NVME_CMBMSC_SET_CRE(cmbmsc, val) \ 366 (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT) 367 #define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \ 368 (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT) 369 #define NVME_CMBMSC_SET_CBA(cmbmsc, val) \ 370 (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT) 371 372 enum NvmeCmbstsShift { 373 CMBSTS_CBAI_SHIFT = 0, 374 }; 375 enum NvmeCmbstsMask { 376 CMBSTS_CBAI_MASK = 0x1, 377 }; 378 379 #define NVME_CMBSTS_CBAI(cmbsts) \ 380 ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK) 381 382 #define NVME_CMBSTS_SET_CBAI(cmbsts, val) \ 383 (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT) 384 385 enum NvmePmrcapShift { 386 PMRCAP_RDS_SHIFT = 3, 387 PMRCAP_WDS_SHIFT = 4, 388 PMRCAP_BIR_SHIFT = 5, 389 PMRCAP_PMRTU_SHIFT = 8, 390 PMRCAP_PMRWBM_SHIFT = 10, 391 PMRCAP_PMRTO_SHIFT = 16, 392 PMRCAP_CMSS_SHIFT = 24, 393 }; 394 395 enum NvmePmrcapMask { 396 PMRCAP_RDS_MASK = 0x1, 397 PMRCAP_WDS_MASK = 0x1, 398 PMRCAP_BIR_MASK = 0x7, 399 PMRCAP_PMRTU_MASK = 0x3, 400 PMRCAP_PMRWBM_MASK = 0xf, 401 PMRCAP_PMRTO_MASK = 0xff, 402 PMRCAP_CMSS_MASK = 0x1, 403 }; 404 405 #define NVME_PMRCAP_RDS(pmrcap) \ 406 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 407 #define NVME_PMRCAP_WDS(pmrcap) \ 408 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 409 #define NVME_PMRCAP_BIR(pmrcap) \ 410 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 411 #define NVME_PMRCAP_PMRTU(pmrcap) \ 412 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 413 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 414 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 415 #define NVME_PMRCAP_PMRTO(pmrcap) \ 416 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 417 #define NVME_PMRCAP_CMSS(pmrcap) \ 418 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 419 420 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 421 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 422 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 423 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 424 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 425 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 426 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 427 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 428 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 429 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 430 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 431 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 432 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 433 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 434 435 enum NvmePmrctlShift { 436 PMRCTL_EN_SHIFT = 0, 437 }; 438 439 enum NvmePmrctlMask { 440 PMRCTL_EN_MASK = 0x1, 441 }; 442 443 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 444 445 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 446 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 447 448 enum NvmePmrstsShift { 449 PMRSTS_ERR_SHIFT = 0, 450 PMRSTS_NRDY_SHIFT = 8, 451 PMRSTS_HSTS_SHIFT = 9, 452 PMRSTS_CBAI_SHIFT = 12, 453 }; 454 455 enum NvmePmrstsMask { 456 PMRSTS_ERR_MASK = 0xff, 457 PMRSTS_NRDY_MASK = 0x1, 458 PMRSTS_HSTS_MASK = 0x7, 459 PMRSTS_CBAI_MASK = 0x1, 460 }; 461 462 #define NVME_PMRSTS_ERR(pmrsts) \ 463 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 464 #define NVME_PMRSTS_NRDY(pmrsts) \ 465 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 466 #define NVME_PMRSTS_HSTS(pmrsts) \ 467 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 468 #define NVME_PMRSTS_CBAI(pmrsts) \ 469 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 470 471 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 472 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 473 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 474 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 475 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 476 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 477 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 478 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 479 480 enum NvmePmrebsShift { 481 PMREBS_PMRSZU_SHIFT = 0, 482 PMREBS_RBB_SHIFT = 4, 483 PMREBS_PMRWBZ_SHIFT = 8, 484 }; 485 486 enum NvmePmrebsMask { 487 PMREBS_PMRSZU_MASK = 0xf, 488 PMREBS_RBB_MASK = 0x1, 489 PMREBS_PMRWBZ_MASK = 0xffffff, 490 }; 491 492 #define NVME_PMREBS_PMRSZU(pmrebs) \ 493 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 494 #define NVME_PMREBS_RBB(pmrebs) \ 495 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 496 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 497 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 498 499 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 500 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 501 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 502 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 503 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 504 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 505 506 enum NvmePmrswtpShift { 507 PMRSWTP_PMRSWTU_SHIFT = 0, 508 PMRSWTP_PMRSWTV_SHIFT = 8, 509 }; 510 511 enum NvmePmrswtpMask { 512 PMRSWTP_PMRSWTU_MASK = 0xf, 513 PMRSWTP_PMRSWTV_MASK = 0xffffff, 514 }; 515 516 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 517 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 518 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 519 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 520 521 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 522 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 523 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 524 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 525 526 enum NvmePmrmsclShift { 527 PMRMSCL_CMSE_SHIFT = 1, 528 PMRMSCL_CBA_SHIFT = 12, 529 }; 530 531 enum NvmePmrmsclMask { 532 PMRMSCL_CMSE_MASK = 0x1, 533 PMRMSCL_CBA_MASK = 0xfffff, 534 }; 535 536 #define NVME_PMRMSCL_CMSE(pmrmscl) \ 537 ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK) 538 #define NVME_PMRMSCL_CBA(pmrmscl) \ 539 ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK) 540 541 #define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \ 542 (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT) 543 #define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \ 544 (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT) 545 546 enum NvmeSglDescriptorType { 547 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 548 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 549 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 550 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 551 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 552 553 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 554 }; 555 556 enum NvmeSglDescriptorSubtype { 557 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 558 }; 559 560 typedef struct QEMU_PACKED NvmeSglDescriptor { 561 uint64_t addr; 562 uint32_t len; 563 uint8_t rsvd[3]; 564 uint8_t type; 565 } NvmeSglDescriptor; 566 567 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 568 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 569 570 typedef union NvmeCmdDptr { 571 struct { 572 uint64_t prp1; 573 uint64_t prp2; 574 }; 575 576 NvmeSglDescriptor sgl; 577 } NvmeCmdDptr; 578 579 enum NvmePsdt { 580 NVME_PSDT_PRP = 0x0, 581 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 582 NVME_PSDT_SGL_MPTR_SGL = 0x2, 583 }; 584 585 typedef struct QEMU_PACKED NvmeCmd { 586 uint8_t opcode; 587 uint8_t flags; 588 uint16_t cid; 589 uint32_t nsid; 590 uint64_t res1; 591 uint64_t mptr; 592 NvmeCmdDptr dptr; 593 uint32_t cdw10; 594 uint32_t cdw11; 595 uint32_t cdw12; 596 uint32_t cdw13; 597 uint32_t cdw14; 598 uint32_t cdw15; 599 } NvmeCmd; 600 601 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 602 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 603 604 enum NvmeAdminCommands { 605 NVME_ADM_CMD_DELETE_SQ = 0x00, 606 NVME_ADM_CMD_CREATE_SQ = 0x01, 607 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 608 NVME_ADM_CMD_DELETE_CQ = 0x04, 609 NVME_ADM_CMD_CREATE_CQ = 0x05, 610 NVME_ADM_CMD_IDENTIFY = 0x06, 611 NVME_ADM_CMD_ABORT = 0x08, 612 NVME_ADM_CMD_SET_FEATURES = 0x09, 613 NVME_ADM_CMD_GET_FEATURES = 0x0a, 614 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 615 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 616 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 617 NVME_ADM_CMD_NS_ATTACHMENT = 0x15, 618 NVME_ADM_CMD_DIRECTIVE_SEND = 0x19, 619 NVME_ADM_CMD_VIRT_MNGMT = 0x1c, 620 NVME_ADM_CMD_DIRECTIVE_RECV = 0x1a, 621 NVME_ADM_CMD_DBBUF_CONFIG = 0x7c, 622 NVME_ADM_CMD_FORMAT_NVM = 0x80, 623 NVME_ADM_CMD_SECURITY_SEND = 0x81, 624 NVME_ADM_CMD_SECURITY_RECV = 0x82, 625 }; 626 627 enum NvmeIoCommands { 628 NVME_CMD_FLUSH = 0x00, 629 NVME_CMD_WRITE = 0x01, 630 NVME_CMD_READ = 0x02, 631 NVME_CMD_WRITE_UNCOR = 0x04, 632 NVME_CMD_COMPARE = 0x05, 633 NVME_CMD_WRITE_ZEROES = 0x08, 634 NVME_CMD_DSM = 0x09, 635 NVME_CMD_VERIFY = 0x0c, 636 NVME_CMD_IO_MGMT_RECV = 0x12, 637 NVME_CMD_COPY = 0x19, 638 NVME_CMD_IO_MGMT_SEND = 0x1d, 639 NVME_CMD_ZONE_MGMT_SEND = 0x79, 640 NVME_CMD_ZONE_MGMT_RECV = 0x7a, 641 NVME_CMD_ZONE_APPEND = 0x7d, 642 }; 643 644 typedef struct QEMU_PACKED NvmeDeleteQ { 645 uint8_t opcode; 646 uint8_t flags; 647 uint16_t cid; 648 uint32_t rsvd1[9]; 649 uint16_t qid; 650 uint16_t rsvd10; 651 uint32_t rsvd11[5]; 652 } NvmeDeleteQ; 653 654 typedef struct QEMU_PACKED NvmeCreateCq { 655 uint8_t opcode; 656 uint8_t flags; 657 uint16_t cid; 658 uint32_t rsvd1[5]; 659 uint64_t prp1; 660 uint64_t rsvd8; 661 uint16_t cqid; 662 uint16_t qsize; 663 uint16_t cq_flags; 664 uint16_t irq_vector; 665 uint32_t rsvd12[4]; 666 } NvmeCreateCq; 667 668 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 669 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 670 671 enum NvmeFlagsCq { 672 NVME_CQ_PC = 1, 673 NVME_CQ_IEN = 2, 674 }; 675 676 typedef struct QEMU_PACKED NvmeCreateSq { 677 uint8_t opcode; 678 uint8_t flags; 679 uint16_t cid; 680 uint32_t rsvd1[5]; 681 uint64_t prp1; 682 uint64_t rsvd8; 683 uint16_t sqid; 684 uint16_t qsize; 685 uint16_t sq_flags; 686 uint16_t cqid; 687 uint32_t rsvd12[4]; 688 } NvmeCreateSq; 689 690 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 691 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 692 693 enum NvmeFlagsSq { 694 NVME_SQ_PC = 1, 695 696 NVME_SQ_PRIO_URGENT = 0, 697 NVME_SQ_PRIO_HIGH = 1, 698 NVME_SQ_PRIO_NORMAL = 2, 699 NVME_SQ_PRIO_LOW = 3, 700 }; 701 702 typedef struct QEMU_PACKED NvmeIdentify { 703 uint8_t opcode; 704 uint8_t flags; 705 uint16_t cid; 706 uint32_t nsid; 707 uint64_t rsvd2[2]; 708 uint64_t prp1; 709 uint64_t prp2; 710 uint8_t cns; 711 uint8_t rsvd10; 712 uint16_t ctrlid; 713 uint16_t nvmsetid; 714 uint8_t rsvd11; 715 uint8_t csi; 716 uint32_t rsvd12[4]; 717 } NvmeIdentify; 718 719 typedef struct QEMU_PACKED NvmeRwCmd { 720 uint8_t opcode; 721 uint8_t flags; 722 uint16_t cid; 723 uint32_t nsid; 724 uint32_t cdw2; 725 uint32_t cdw3; 726 uint64_t mptr; 727 NvmeCmdDptr dptr; 728 uint64_t slba; 729 uint16_t nlb; 730 uint16_t control; 731 uint8_t dsmgmt; 732 uint8_t rsvd; 733 uint16_t dspec; 734 uint32_t reftag; 735 uint16_t apptag; 736 uint16_t appmask; 737 } NvmeRwCmd; 738 739 enum { 740 NVME_RW_LR = 1 << 15, 741 NVME_RW_FUA = 1 << 14, 742 NVME_RW_DSM_FREQ_UNSPEC = 0, 743 NVME_RW_DSM_FREQ_TYPICAL = 1, 744 NVME_RW_DSM_FREQ_RARE = 2, 745 NVME_RW_DSM_FREQ_READS = 3, 746 NVME_RW_DSM_FREQ_WRITES = 4, 747 NVME_RW_DSM_FREQ_RW = 5, 748 NVME_RW_DSM_FREQ_ONCE = 6, 749 NVME_RW_DSM_FREQ_PREFETCH = 7, 750 NVME_RW_DSM_FREQ_TEMP = 8, 751 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 752 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 753 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 754 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 755 NVME_RW_DSM_SEQ_REQ = 1 << 6, 756 NVME_RW_DSM_COMPRESSED = 1 << 7, 757 NVME_RW_PIREMAP = 1 << 9, 758 NVME_RW_PRINFO_PRACT = 1 << 13, 759 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 760 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 761 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 762 NVME_RW_PRINFO_PRCHK_MASK = 7 << 10, 763 }; 764 765 #define NVME_RW_PRINFO(control) ((control >> 10) & 0xf) 766 767 enum { 768 NVME_PRINFO_PRACT = 1 << 3, 769 NVME_PRINFO_PRCHK_GUARD = 1 << 2, 770 NVME_PRINFO_PRCHK_APP = 1 << 1, 771 NVME_PRINFO_PRCHK_REF = 1 << 0, 772 NVME_PRINFO_PRCHK_MASK = 7 << 0, 773 }; 774 775 typedef struct QEMU_PACKED NvmeDsmCmd { 776 uint8_t opcode; 777 uint8_t flags; 778 uint16_t cid; 779 uint32_t nsid; 780 uint64_t rsvd2[2]; 781 NvmeCmdDptr dptr; 782 uint32_t nr; 783 uint32_t attributes; 784 uint32_t rsvd12[4]; 785 } NvmeDsmCmd; 786 787 enum { 788 NVME_DSMGMT_IDR = 1 << 0, 789 NVME_DSMGMT_IDW = 1 << 1, 790 NVME_DSMGMT_AD = 1 << 2, 791 }; 792 793 typedef struct QEMU_PACKED NvmeDsmRange { 794 uint32_t cattr; 795 uint32_t nlb; 796 uint64_t slba; 797 } NvmeDsmRange; 798 799 enum { 800 NVME_COPY_FORMAT_0 = 0x0, 801 NVME_COPY_FORMAT_1 = 0x1, 802 NVME_COPY_FORMAT_2 = 0x2, 803 NVME_COPY_FORMAT_3 = 0x3, 804 }; 805 806 typedef struct QEMU_PACKED NvmeCopyCmd { 807 uint8_t opcode; 808 uint8_t flags; 809 uint16_t cid; 810 uint32_t nsid; 811 uint32_t cdw2; 812 uint32_t cdw3; 813 uint32_t rsvd2[2]; 814 NvmeCmdDptr dptr; 815 uint64_t sdlba; 816 uint8_t nr; 817 uint8_t control[3]; 818 uint16_t rsvd13; 819 uint16_t dspec; 820 uint32_t reftag; 821 uint16_t apptag; 822 uint16_t appmask; 823 } NvmeCopyCmd; 824 825 typedef struct QEMU_PACKED NvmeCopySourceRangeFormat0_2 { 826 uint32_t sparams; 827 uint8_t rsvd4[4]; 828 uint64_t slba; 829 uint16_t nlb; 830 uint8_t rsvd18[4]; 831 uint16_t sopt; 832 uint32_t reftag; 833 uint16_t apptag; 834 uint16_t appmask; 835 } NvmeCopySourceRangeFormat0_2; 836 837 typedef struct QEMU_PACKED NvmeCopySourceRangeFormat1_3 { 838 uint32_t sparams; 839 uint8_t rsvd4[4]; 840 uint64_t slba; 841 uint16_t nlb; 842 uint8_t rsvd18[4]; 843 uint16_t sopt; 844 uint8_t rsvd24[2]; 845 uint8_t sr[10]; 846 uint16_t apptag; 847 uint16_t appmask; 848 } NvmeCopySourceRangeFormat1_3; 849 850 enum NvmeAsyncEventRequest { 851 NVME_AER_TYPE_ERROR = 0, 852 NVME_AER_TYPE_SMART = 1, 853 NVME_AER_TYPE_NOTICE = 2, 854 NVME_AER_TYPE_IO_SPECIFIC = 6, 855 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 856 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 857 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 858 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 859 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 860 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 861 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 862 NVME_AER_INFO_SMART_RELIABILITY = 0, 863 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 864 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 865 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED = 0, 866 }; 867 868 typedef struct QEMU_PACKED NvmeAerResult { 869 uint8_t event_type; 870 uint8_t event_info; 871 uint8_t log_page; 872 uint8_t resv; 873 } NvmeAerResult; 874 875 typedef struct QEMU_PACKED NvmeZonedResult { 876 uint64_t slba; 877 } NvmeZonedResult; 878 879 typedef struct QEMU_PACKED NvmeCqe { 880 uint32_t result; 881 uint32_t dw1; 882 uint16_t sq_head; 883 uint16_t sq_id; 884 uint16_t cid; 885 uint16_t status; 886 } NvmeCqe; 887 888 enum NvmeStatusCodes { 889 NVME_SUCCESS = 0x0000, 890 NVME_INVALID_OPCODE = 0x0001, 891 NVME_INVALID_FIELD = 0x0002, 892 NVME_CID_CONFLICT = 0x0003, 893 NVME_DATA_TRAS_ERROR = 0x0004, 894 NVME_POWER_LOSS_ABORT = 0x0005, 895 NVME_INTERNAL_DEV_ERROR = 0x0006, 896 NVME_CMD_ABORT_REQ = 0x0007, 897 NVME_CMD_ABORT_SQ_DEL = 0x0008, 898 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 899 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 900 NVME_INVALID_NSID = 0x000b, 901 NVME_CMD_SEQ_ERROR = 0x000c, 902 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 903 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 904 NVME_DATA_SGL_LEN_INVALID = 0x000f, 905 NVME_MD_SGL_LEN_INVALID = 0x0010, 906 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 907 NVME_INVALID_USE_OF_CMB = 0x0012, 908 NVME_INVALID_PRP_OFFSET = 0x0013, 909 NVME_CMD_SET_CMB_REJECTED = 0x002b, 910 NVME_INVALID_CMD_SET = 0x002c, 911 NVME_FDP_DISABLED = 0x0029, 912 NVME_INVALID_PHID_LIST = 0x002a, 913 NVME_LBA_RANGE = 0x0080, 914 NVME_CAP_EXCEEDED = 0x0081, 915 NVME_NS_NOT_READY = 0x0082, 916 NVME_NS_RESV_CONFLICT = 0x0083, 917 NVME_FORMAT_IN_PROGRESS = 0x0084, 918 NVME_INVALID_CQID = 0x0100, 919 NVME_INVALID_QID = 0x0101, 920 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 921 NVME_ACL_EXCEEDED = 0x0103, 922 NVME_RESERVED = 0x0104, 923 NVME_AER_LIMIT_EXCEEDED = 0x0105, 924 NVME_INVALID_FW_SLOT = 0x0106, 925 NVME_INVALID_FW_IMAGE = 0x0107, 926 NVME_INVALID_IRQ_VECTOR = 0x0108, 927 NVME_INVALID_LOG_ID = 0x0109, 928 NVME_INVALID_FORMAT = 0x010a, 929 NVME_FW_REQ_RESET = 0x010b, 930 NVME_INVALID_QUEUE_DEL = 0x010c, 931 NVME_FID_NOT_SAVEABLE = 0x010d, 932 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 933 NVME_FEAT_NOT_NS_SPEC = 0x010f, 934 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 935 NVME_NS_ALREADY_ATTACHED = 0x0118, 936 NVME_NS_PRIVATE = 0x0119, 937 NVME_NS_NOT_ATTACHED = 0x011a, 938 NVME_NS_CTRL_LIST_INVALID = 0x011c, 939 NVME_INVALID_CTRL_ID = 0x011f, 940 NVME_INVALID_SEC_CTRL_STATE = 0x0120, 941 NVME_INVALID_NUM_RESOURCES = 0x0121, 942 NVME_INVALID_RESOURCE_ID = 0x0122, 943 NVME_CONFLICTING_ATTRS = 0x0180, 944 NVME_INVALID_PROT_INFO = 0x0181, 945 NVME_WRITE_TO_RO = 0x0182, 946 NVME_CMD_SIZE_LIMIT = 0x0183, 947 NVME_CMD_INCOMP_NS_OR_FMT = 0x0185, 948 NVME_CMD_OVERLAP_IO_RANGE = 0x0187, 949 NVME_INVALID_ZONE_OP = 0x01b6, 950 NVME_NOZRWA = 0x01b7, 951 NVME_ZONE_BOUNDARY_ERROR = 0x01b8, 952 NVME_ZONE_FULL = 0x01b9, 953 NVME_ZONE_READ_ONLY = 0x01ba, 954 NVME_ZONE_OFFLINE = 0x01bb, 955 NVME_ZONE_INVALID_WRITE = 0x01bc, 956 NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, 957 NVME_ZONE_TOO_MANY_OPEN = 0x01be, 958 NVME_ZONE_INVAL_TRANSITION = 0x01bf, 959 NVME_WRITE_FAULT = 0x0280, 960 NVME_UNRECOVERED_READ = 0x0281, 961 NVME_E2E_GUARD_ERROR = 0x0282, 962 NVME_E2E_APP_ERROR = 0x0283, 963 NVME_E2E_REF_ERROR = 0x0284, 964 NVME_CMP_FAILURE = 0x0285, 965 NVME_ACCESS_DENIED = 0x0286, 966 NVME_DULB = 0x0287, 967 NVME_E2E_STORAGE_TAG_ERROR = 0x0288, 968 NVME_MORE = 0x2000, 969 NVME_DNR = 0x4000, 970 NVME_NO_COMPLETE = 0xffff, 971 }; 972 973 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 974 uint8_t afi; 975 uint8_t reserved1[7]; 976 uint8_t frs1[8]; 977 uint8_t frs2[8]; 978 uint8_t frs3[8]; 979 uint8_t frs4[8]; 980 uint8_t frs5[8]; 981 uint8_t frs6[8]; 982 uint8_t frs7[8]; 983 uint8_t reserved2[448]; 984 } NvmeFwSlotInfoLog; 985 986 typedef struct QEMU_PACKED NvmeErrorLog { 987 uint64_t error_count; 988 uint16_t sqid; 989 uint16_t cid; 990 uint16_t status_field; 991 uint16_t param_error_location; 992 uint64_t lba; 993 uint32_t nsid; 994 uint8_t vs; 995 uint8_t resv[35]; 996 } NvmeErrorLog; 997 998 typedef struct QEMU_PACKED NvmeSmartLog { 999 uint8_t critical_warning; 1000 uint16_t temperature; 1001 uint8_t available_spare; 1002 uint8_t available_spare_threshold; 1003 uint8_t percentage_used; 1004 uint8_t reserved1[26]; 1005 uint64_t data_units_read[2]; 1006 uint64_t data_units_written[2]; 1007 uint64_t host_read_commands[2]; 1008 uint64_t host_write_commands[2]; 1009 uint64_t controller_busy_time[2]; 1010 uint64_t power_cycles[2]; 1011 uint64_t power_on_hours[2]; 1012 uint64_t unsafe_shutdowns[2]; 1013 uint64_t media_errors[2]; 1014 uint64_t number_of_error_log_entries[2]; 1015 uint8_t reserved2[320]; 1016 } NvmeSmartLog; 1017 1018 #define NVME_SMART_WARN_MAX 6 1019 enum NvmeSmartWarn { 1020 NVME_SMART_SPARE = 1 << 0, 1021 NVME_SMART_TEMPERATURE = 1 << 1, 1022 NVME_SMART_RELIABILITY = 1 << 2, 1023 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 1024 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 1025 NVME_SMART_PMR_UNRELIABLE = 1 << 5, 1026 }; 1027 1028 typedef struct NvmeEffectsLog { 1029 uint32_t acs[256]; 1030 uint32_t iocs[256]; 1031 uint8_t resv[2048]; 1032 } NvmeEffectsLog; 1033 1034 enum { 1035 NVME_CMD_EFF_CSUPP = 1 << 0, 1036 NVME_CMD_EFF_LBCC = 1 << 1, 1037 NVME_CMD_EFF_NCC = 1 << 2, 1038 NVME_CMD_EFF_NIC = 1 << 3, 1039 NVME_CMD_EFF_CCC = 1 << 4, 1040 NVME_CMD_EFF_CSE_MASK = 3 << 16, 1041 NVME_CMD_EFF_UUID_SEL = 1 << 19, 1042 }; 1043 1044 enum NvmeLogIdentifier { 1045 NVME_LOG_ERROR_INFO = 0x01, 1046 NVME_LOG_SMART_INFO = 0x02, 1047 NVME_LOG_FW_SLOT_INFO = 0x03, 1048 NVME_LOG_CHANGED_NSLIST = 0x04, 1049 NVME_LOG_CMD_EFFECTS = 0x05, 1050 NVME_LOG_ENDGRP = 0x09, 1051 NVME_LOG_FDP_CONFS = 0x20, 1052 NVME_LOG_FDP_RUH_USAGE = 0x21, 1053 NVME_LOG_FDP_STATS = 0x22, 1054 NVME_LOG_FDP_EVENTS = 0x23, 1055 }; 1056 1057 typedef struct QEMU_PACKED NvmePSD { 1058 uint16_t mp; 1059 uint16_t reserved; 1060 uint32_t enlat; 1061 uint32_t exlat; 1062 uint8_t rrt; 1063 uint8_t rrl; 1064 uint8_t rwt; 1065 uint8_t rwl; 1066 uint8_t resv[16]; 1067 } NvmePSD; 1068 1069 #define NVME_CONTROLLER_LIST_SIZE 2048 1070 #define NVME_IDENTIFY_DATA_SIZE 4096 1071 1072 enum NvmeIdCns { 1073 NVME_ID_CNS_NS = 0x00, 1074 NVME_ID_CNS_CTRL = 0x01, 1075 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 1076 NVME_ID_CNS_NS_DESCR_LIST = 0x03, 1077 NVME_ID_CNS_CS_NS = 0x05, 1078 NVME_ID_CNS_CS_CTRL = 0x06, 1079 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 1080 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 1081 NVME_ID_CNS_NS_PRESENT = 0x11, 1082 NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12, 1083 NVME_ID_CNS_CTRL_LIST = 0x13, 1084 NVME_ID_CNS_PRIMARY_CTRL_CAP = 0x14, 1085 NVME_ID_CNS_SECONDARY_CTRL_LIST = 0x15, 1086 NVME_ID_CNS_ENDURANCE_GROUP_LIST = 0x19, 1087 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 1088 NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 1089 NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 1090 }; 1091 1092 typedef struct QEMU_PACKED NvmeIdCtrl { 1093 uint16_t vid; 1094 uint16_t ssvid; 1095 uint8_t sn[20]; 1096 uint8_t mn[40]; 1097 uint8_t fr[8]; 1098 uint8_t rab; 1099 uint8_t ieee[3]; 1100 uint8_t cmic; 1101 uint8_t mdts; 1102 uint16_t cntlid; 1103 uint32_t ver; 1104 uint32_t rtd3r; 1105 uint32_t rtd3e; 1106 uint32_t oaes; 1107 uint32_t ctratt; 1108 uint8_t rsvd100[11]; 1109 uint8_t cntrltype; 1110 uint8_t fguid[16]; 1111 uint8_t rsvd128[128]; 1112 uint16_t oacs; 1113 uint8_t acl; 1114 uint8_t aerl; 1115 uint8_t frmw; 1116 uint8_t lpa; 1117 uint8_t elpe; 1118 uint8_t npss; 1119 uint8_t avscc; 1120 uint8_t apsta; 1121 uint16_t wctemp; 1122 uint16_t cctemp; 1123 uint16_t mtfa; 1124 uint32_t hmpre; 1125 uint32_t hmmin; 1126 uint8_t tnvmcap[16]; 1127 uint8_t unvmcap[16]; 1128 uint32_t rpmbs; 1129 uint16_t edstt; 1130 uint8_t dsto; 1131 uint8_t fwug; 1132 uint16_t kas; 1133 uint16_t hctma; 1134 uint16_t mntmt; 1135 uint16_t mxtmt; 1136 uint32_t sanicap; 1137 uint8_t rsvd332[6]; 1138 uint16_t nsetidmax; 1139 uint16_t endgidmax; 1140 uint8_t rsvd342[170]; 1141 uint8_t sqes; 1142 uint8_t cqes; 1143 uint16_t maxcmd; 1144 uint32_t nn; 1145 uint16_t oncs; 1146 uint16_t fuses; 1147 uint8_t fna; 1148 uint8_t vwc; 1149 uint16_t awun; 1150 uint16_t awupf; 1151 uint8_t nvscc; 1152 uint8_t rsvd531; 1153 uint16_t acwu; 1154 uint16_t ocfs; 1155 uint32_t sgls; 1156 uint8_t rsvd540[228]; 1157 uint8_t subnqn[256]; 1158 uint8_t rsvd1024[1024]; 1159 NvmePSD psd[32]; 1160 uint8_t vs[1024]; 1161 } NvmeIdCtrl; 1162 1163 typedef struct NvmeIdCtrlZoned { 1164 uint8_t zasl; 1165 uint8_t rsvd1[4095]; 1166 } NvmeIdCtrlZoned; 1167 1168 typedef struct NvmeIdCtrlNvm { 1169 uint8_t vsl; 1170 uint8_t wzsl; 1171 uint8_t wusl; 1172 uint8_t dmrl; 1173 uint32_t dmrsl; 1174 uint64_t dmsl; 1175 uint8_t rsvd16[4080]; 1176 } NvmeIdCtrlNvm; 1177 1178 enum NvmeIdCtrlOaes { 1179 NVME_OAES_NS_ATTR = 1 << 8, 1180 }; 1181 1182 enum NvmeIdCtrlCtratt { 1183 NVME_CTRATT_ENDGRPS = 1 << 4, 1184 NVME_CTRATT_ELBAS = 1 << 15, 1185 NVME_CTRATT_MEM = 1 << 16, 1186 NVME_CTRATT_FDPS = 1 << 19, 1187 }; 1188 1189 enum NvmeIdCtrlOacs { 1190 NVME_OACS_SECURITY = 1 << 0, 1191 NVME_OACS_FORMAT = 1 << 1, 1192 NVME_OACS_FW = 1 << 2, 1193 NVME_OACS_NS_MGMT = 1 << 3, 1194 NVME_OACS_DIRECTIVES = 1 << 5, 1195 NVME_OACS_DBBUF = 1 << 8, 1196 }; 1197 1198 enum NvmeIdCtrlOncs { 1199 NVME_ONCS_COMPARE = 1 << 0, 1200 NVME_ONCS_WRITE_UNCORR = 1 << 1, 1201 NVME_ONCS_DSM = 1 << 2, 1202 NVME_ONCS_WRITE_ZEROES = 1 << 3, 1203 NVME_ONCS_FEATURES = 1 << 4, 1204 NVME_ONCS_RESRVATIONS = 1 << 5, 1205 NVME_ONCS_TIMESTAMP = 1 << 6, 1206 NVME_ONCS_VERIFY = 1 << 7, 1207 NVME_ONCS_COPY = 1 << 8, 1208 NVME_ONCS_NVMCSA = 1 << 9, 1209 NVME_ONCS_NVMAFC = 1 << 10, 1210 }; 1211 1212 enum NvmeIdCtrlOcfs { 1213 NVME_OCFS_COPY_FORMAT_0 = 1 << NVME_COPY_FORMAT_0, 1214 NVME_OCFS_COPY_FORMAT_1 = 1 << NVME_COPY_FORMAT_1, 1215 NVME_OCFS_COPY_FORMAT_2 = 1 << NVME_COPY_FORMAT_2, 1216 NVME_OCFS_COPY_FORMAT_3 = 1 << NVME_COPY_FORMAT_3, 1217 }; 1218 1219 enum NvmeIdctrlVwc { 1220 NVME_VWC_PRESENT = 1 << 0, 1221 NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1, 1222 NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1, 1223 NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1, 1224 NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1, 1225 }; 1226 1227 enum NvmeIdCtrlFrmw { 1228 NVME_FRMW_SLOT1_RO = 1 << 0, 1229 }; 1230 1231 enum NvmeIdCtrlLpa { 1232 NVME_LPA_NS_SMART = 1 << 0, 1233 NVME_LPA_CSE = 1 << 1, 1234 NVME_LPA_EXTENDED = 1 << 2, 1235 }; 1236 1237 enum NvmeIdCtrlCmic { 1238 NVME_CMIC_MULTI_CTRL = 1 << 1, 1239 }; 1240 1241 enum NvmeNsAttachmentOperation { 1242 NVME_NS_ATTACHMENT_ATTACH = 0x0, 1243 NVME_NS_ATTACHMENT_DETACH = 0x1, 1244 }; 1245 1246 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 1247 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 1248 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 1249 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 1250 1251 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 1252 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 1253 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 1254 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 1255 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 1256 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 1257 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 1258 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 1259 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 1260 1261 #define NVME_ARB_AB(arb) (arb & 0x7) 1262 #define NVME_ARB_AB_NOLIMIT 0x7 1263 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 1264 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 1265 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 1266 1267 #define NVME_INTC_THR(intc) (intc & 0xff) 1268 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 1269 1270 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 1271 1272 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 1273 #define NVME_TEMP_THSEL_OVER 0x0 1274 #define NVME_TEMP_THSEL_UNDER 0x1 1275 1276 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 1277 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 1278 1279 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 1280 1281 #define NVME_AEC_SMART(aec) (aec & 0xff) 1282 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 1283 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 1284 #define NVME_AEC_ENDGRP_NOTICE(aec) ((aec >> 14) & 0x1) 1285 1286 #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 1287 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 1288 1289 #define NVME_ID_CTRL_CTRATT_MEM(ctratt) (ctratt & NVME_CTRATT_MEM) 1290 1291 enum NvmeFeatureIds { 1292 NVME_ARBITRATION = 0x1, 1293 NVME_POWER_MANAGEMENT = 0x2, 1294 NVME_LBA_RANGE_TYPE = 0x3, 1295 NVME_TEMPERATURE_THRESHOLD = 0x4, 1296 NVME_ERROR_RECOVERY = 0x5, 1297 NVME_VOLATILE_WRITE_CACHE = 0x6, 1298 NVME_NUMBER_OF_QUEUES = 0x7, 1299 NVME_INTERRUPT_COALESCING = 0x8, 1300 NVME_INTERRUPT_VECTOR_CONF = 0x9, 1301 NVME_WRITE_ATOMICITY = 0xa, 1302 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 1303 NVME_TIMESTAMP = 0xe, 1304 NVME_HOST_BEHAVIOR_SUPPORT = 0x16, 1305 NVME_COMMAND_SET_PROFILE = 0x19, 1306 NVME_FDP_MODE = 0x1d, 1307 NVME_FDP_EVENTS = 0x1e, 1308 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 1309 NVME_FID_MAX = 0x100, 1310 }; 1311 1312 typedef enum NvmeFeatureCap { 1313 NVME_FEAT_CAP_SAVE = 1 << 0, 1314 NVME_FEAT_CAP_NS = 1 << 1, 1315 NVME_FEAT_CAP_CHANGE = 1 << 2, 1316 } NvmeFeatureCap; 1317 1318 typedef enum NvmeGetFeatureSelect { 1319 NVME_GETFEAT_SELECT_CURRENT = 0x0, 1320 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 1321 NVME_GETFEAT_SELECT_SAVED = 0x2, 1322 NVME_GETFEAT_SELECT_CAP = 0x3, 1323 } NvmeGetFeatureSelect; 1324 1325 #define NVME_GETSETFEAT_FID_MASK 0xff 1326 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 1327 1328 #define NVME_GETFEAT_SELECT_SHIFT 8 1329 #define NVME_GETFEAT_SELECT_MASK 0x7 1330 #define NVME_GETFEAT_SELECT(dw10) \ 1331 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 1332 1333 #define NVME_SETFEAT_SAVE_SHIFT 31 1334 #define NVME_SETFEAT_SAVE_MASK 0x1 1335 #define NVME_SETFEAT_SAVE(dw10) \ 1336 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 1337 1338 typedef struct QEMU_PACKED NvmeRangeType { 1339 uint8_t type; 1340 uint8_t attributes; 1341 uint8_t rsvd2[14]; 1342 uint64_t slba; 1343 uint64_t nlb; 1344 uint8_t guid[16]; 1345 uint8_t rsvd48[16]; 1346 } NvmeRangeType; 1347 1348 typedef struct NvmeHostBehaviorSupport { 1349 uint8_t acre; 1350 uint8_t etdas; 1351 uint8_t lbafee; 1352 uint8_t rsvd3; 1353 uint16_t cdfe; 1354 uint8_t rsvd6[506]; 1355 } NvmeHostBehaviorSupport; 1356 1357 typedef struct QEMU_PACKED NvmeLBAF { 1358 uint16_t ms; 1359 uint8_t ds; 1360 uint8_t rp; 1361 } NvmeLBAF; 1362 1363 typedef struct QEMU_PACKED NvmeLBAFE { 1364 uint64_t zsze; 1365 uint8_t zdes; 1366 uint8_t rsvd9[7]; 1367 } NvmeLBAFE; 1368 1369 #define NVME_NSID_BROADCAST 0xffffffff 1370 #define NVME_MAX_NLBAF 64 1371 1372 typedef struct QEMU_PACKED NvmeIdNs { 1373 uint64_t nsze; 1374 uint64_t ncap; 1375 uint64_t nuse; 1376 uint8_t nsfeat; 1377 uint8_t nlbaf; 1378 uint8_t flbas; 1379 uint8_t mc; 1380 uint8_t dpc; 1381 uint8_t dps; 1382 uint8_t nmic; 1383 uint8_t rescap; 1384 uint8_t fpi; 1385 uint8_t dlfeat; 1386 uint16_t nawun; 1387 uint16_t nawupf; 1388 uint16_t nacwu; 1389 uint16_t nabsn; 1390 uint16_t nabo; 1391 uint16_t nabspf; 1392 uint16_t noiob; 1393 uint8_t nvmcap[16]; 1394 uint16_t npwg; 1395 uint16_t npwa; 1396 uint16_t npdg; 1397 uint16_t npda; 1398 uint16_t nows; 1399 uint16_t mssrl; 1400 uint32_t mcl; 1401 uint8_t msrc; 1402 uint8_t rsvd81[18]; 1403 uint8_t nsattr; 1404 uint16_t nvmsetid; 1405 uint16_t endgid; 1406 uint8_t nguid[16]; 1407 uint64_t eui64; 1408 NvmeLBAF lbaf[NVME_MAX_NLBAF]; 1409 uint8_t vs[3712]; 1410 } NvmeIdNs; 1411 1412 #define NVME_ID_NS_NVM_ELBAF_PIF(elbaf) (((elbaf) >> 7) & 0x3) 1413 1414 typedef struct QEMU_PACKED NvmeIdNsNvm { 1415 uint64_t lbstm; 1416 uint8_t pic; 1417 uint8_t rsvd9[3]; 1418 uint32_t elbaf[NVME_MAX_NLBAF]; 1419 uint8_t rsvd268[3828]; 1420 } NvmeIdNsNvm; 1421 1422 typedef struct QEMU_PACKED NvmeIdNsDescr { 1423 uint8_t nidt; 1424 uint8_t nidl; 1425 uint8_t rsvd2[2]; 1426 } NvmeIdNsDescr; 1427 1428 enum NvmeNsIdentifierLength { 1429 NVME_NIDL_EUI64 = 8, 1430 NVME_NIDL_NGUID = 16, 1431 NVME_NIDL_UUID = 16, 1432 NVME_NIDL_CSI = 1, 1433 }; 1434 1435 enum NvmeNsIdentifierType { 1436 NVME_NIDT_EUI64 = 0x01, 1437 NVME_NIDT_NGUID = 0x02, 1438 NVME_NIDT_UUID = 0x03, 1439 NVME_NIDT_CSI = 0x04, 1440 }; 1441 1442 enum NvmeIdNsNmic { 1443 NVME_NMIC_NS_SHARED = 1 << 0, 1444 }; 1445 1446 enum NvmeCsi { 1447 NVME_CSI_NVM = 0x00, 1448 NVME_CSI_ZONED = 0x02, 1449 }; 1450 1451 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1452 1453 typedef struct QEMU_PACKED NvmeIdNsZoned { 1454 uint16_t zoc; 1455 uint16_t ozcs; 1456 uint32_t mar; 1457 uint32_t mor; 1458 uint32_t rrl; 1459 uint32_t frl; 1460 uint8_t rsvd12[24]; 1461 uint32_t numzrwa; 1462 uint16_t zrwafg; 1463 uint16_t zrwas; 1464 uint8_t zrwacap; 1465 uint8_t rsvd53[2763]; 1466 NvmeLBAFE lbafe[16]; 1467 uint8_t rsvd3072[768]; 1468 uint8_t vs[256]; 1469 } NvmeIdNsZoned; 1470 1471 enum NvmeIdNsZonedOzcs { 1472 NVME_ID_NS_ZONED_OZCS_RAZB = 1 << 0, 1473 NVME_ID_NS_ZONED_OZCS_ZRWASUP = 1 << 1, 1474 }; 1475 1476 enum NvmeIdNsZonedZrwacap { 1477 NVME_ID_NS_ZONED_ZRWACAP_EXPFLUSHSUP = 1 << 0, 1478 }; 1479 1480 /*Deallocate Logical Block Features*/ 1481 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1482 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1483 1484 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1485 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1486 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1487 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1488 1489 1490 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1491 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1492 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1493 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1494 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1495 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1496 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1497 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1498 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1499 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1500 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1501 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1502 1503 enum NvmeIdNsDps { 1504 NVME_ID_NS_DPS_TYPE_NONE = 0, 1505 NVME_ID_NS_DPS_TYPE_1 = 1, 1506 NVME_ID_NS_DPS_TYPE_2 = 2, 1507 NVME_ID_NS_DPS_TYPE_3 = 3, 1508 NVME_ID_NS_DPS_TYPE_MASK = 0x7, 1509 NVME_ID_NS_DPS_FIRST_EIGHT = 8, 1510 }; 1511 1512 enum NvmeIdNsFlbas { 1513 NVME_ID_NS_FLBAS_EXTENDED = 1 << 4, 1514 }; 1515 1516 enum NvmeIdNsMc { 1517 NVME_ID_NS_MC_EXTENDED = 1 << 0, 1518 NVME_ID_NS_MC_SEPARATE = 1 << 1, 1519 }; 1520 1521 #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK) 1522 1523 enum NvmePIFormat { 1524 NVME_PI_GUARD_16 = 0, 1525 NVME_PI_GUARD_64 = 2, 1526 }; 1527 1528 typedef union NvmeDifTuple { 1529 struct { 1530 uint16_t guard; 1531 uint16_t apptag; 1532 uint32_t reftag; 1533 } g16; 1534 1535 struct { 1536 uint64_t guard; 1537 uint16_t apptag; 1538 uint8_t sr[6]; 1539 } g64; 1540 } NvmeDifTuple; 1541 1542 enum NvmeZoneAttr { 1543 NVME_ZA_FINISHED_BY_CTLR = 1 << 0, 1544 NVME_ZA_FINISH_RECOMMENDED = 1 << 1, 1545 NVME_ZA_RESET_RECOMMENDED = 1 << 2, 1546 NVME_ZA_ZRWA_VALID = 1 << 3, 1547 NVME_ZA_ZD_EXT_VALID = 1 << 7, 1548 }; 1549 1550 typedef struct QEMU_PACKED NvmeZoneReportHeader { 1551 uint64_t nr_zones; 1552 uint8_t rsvd[56]; 1553 } NvmeZoneReportHeader; 1554 1555 enum NvmeZoneReceiveAction { 1556 NVME_ZONE_REPORT = 0, 1557 NVME_ZONE_REPORT_EXTENDED = 1, 1558 }; 1559 1560 enum NvmeZoneReportType { 1561 NVME_ZONE_REPORT_ALL = 0, 1562 NVME_ZONE_REPORT_EMPTY = 1, 1563 NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, 1564 NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, 1565 NVME_ZONE_REPORT_CLOSED = 4, 1566 NVME_ZONE_REPORT_FULL = 5, 1567 NVME_ZONE_REPORT_READ_ONLY = 6, 1568 NVME_ZONE_REPORT_OFFLINE = 7, 1569 }; 1570 1571 enum NvmeZoneType { 1572 NVME_ZONE_TYPE_RESERVED = 0x00, 1573 NVME_ZONE_TYPE_SEQ_WRITE = 0x02, 1574 }; 1575 1576 typedef struct QEMU_PACKED NvmeZoneSendCmd { 1577 uint8_t opcode; 1578 uint8_t flags; 1579 uint16_t cid; 1580 uint32_t nsid; 1581 uint32_t rsvd8[4]; 1582 NvmeCmdDptr dptr; 1583 uint64_t slba; 1584 uint32_t rsvd48; 1585 uint8_t zsa; 1586 uint8_t zsflags; 1587 uint8_t rsvd54[2]; 1588 uint32_t rsvd56[2]; 1589 } NvmeZoneSendCmd; 1590 1591 enum NvmeZoneSendAction { 1592 NVME_ZONE_ACTION_RSD = 0x00, 1593 NVME_ZONE_ACTION_CLOSE = 0x01, 1594 NVME_ZONE_ACTION_FINISH = 0x02, 1595 NVME_ZONE_ACTION_OPEN = 0x03, 1596 NVME_ZONE_ACTION_RESET = 0x04, 1597 NVME_ZONE_ACTION_OFFLINE = 0x05, 1598 NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, 1599 NVME_ZONE_ACTION_ZRWA_FLUSH = 0x11, 1600 }; 1601 1602 enum { 1603 NVME_ZSFLAG_SELECT_ALL = 1 << 0, 1604 NVME_ZSFLAG_ZRWA_ALLOC = 1 << 1, 1605 }; 1606 1607 typedef struct QEMU_PACKED NvmeZoneDescr { 1608 uint8_t zt; 1609 uint8_t zs; 1610 uint8_t za; 1611 uint8_t rsvd3[5]; 1612 uint64_t zcap; 1613 uint64_t zslba; 1614 uint64_t wp; 1615 uint8_t rsvd32[32]; 1616 } NvmeZoneDescr; 1617 1618 typedef enum NvmeZoneState { 1619 NVME_ZONE_STATE_RESERVED = 0x00, 1620 NVME_ZONE_STATE_EMPTY = 0x01, 1621 NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, 1622 NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, 1623 NVME_ZONE_STATE_CLOSED = 0x04, 1624 NVME_ZONE_STATE_READ_ONLY = 0x0d, 1625 NVME_ZONE_STATE_FULL = 0x0e, 1626 NVME_ZONE_STATE_OFFLINE = 0x0f, 1627 } NvmeZoneState; 1628 1629 typedef struct QEMU_PACKED NvmePriCtrlCap { 1630 uint16_t cntlid; 1631 uint16_t portid; 1632 uint8_t crt; 1633 uint8_t rsvd5[27]; 1634 uint32_t vqfrt; 1635 uint32_t vqrfa; 1636 uint16_t vqrfap; 1637 uint16_t vqprt; 1638 uint16_t vqfrsm; 1639 uint16_t vqgran; 1640 uint8_t rsvd48[16]; 1641 uint32_t vifrt; 1642 uint32_t virfa; 1643 uint16_t virfap; 1644 uint16_t viprt; 1645 uint16_t vifrsm; 1646 uint16_t vigran; 1647 uint8_t rsvd80[4016]; 1648 } NvmePriCtrlCap; 1649 1650 typedef enum NvmePriCtrlCapCrt { 1651 NVME_CRT_VQ = 1 << 0, 1652 NVME_CRT_VI = 1 << 1, 1653 } NvmePriCtrlCapCrt; 1654 1655 typedef struct QEMU_PACKED NvmeSecCtrlEntry { 1656 uint16_t scid; 1657 uint16_t pcid; 1658 uint8_t scs; 1659 uint8_t rsvd5[3]; 1660 uint16_t vfn; 1661 uint16_t nvq; 1662 uint16_t nvi; 1663 uint8_t rsvd14[18]; 1664 } NvmeSecCtrlEntry; 1665 1666 typedef struct QEMU_PACKED NvmeSecCtrlList { 1667 uint8_t numcntl; 1668 uint8_t rsvd1[31]; 1669 NvmeSecCtrlEntry sec[127]; 1670 } NvmeSecCtrlList; 1671 1672 typedef enum NvmeVirtMngmtAction { 1673 NVME_VIRT_MNGMT_ACTION_PRM_ALLOC = 0x01, 1674 NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE = 0x07, 1675 NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN = 0x08, 1676 NVME_VIRT_MNGMT_ACTION_SEC_ONLINE = 0x09, 1677 } NvmeVirtMngmtAction; 1678 1679 typedef enum NvmeVirtualResourceType { 1680 NVME_VIRT_RES_QUEUE = 0x00, 1681 NVME_VIRT_RES_INTERRUPT = 0x01, 1682 } NvmeVirtualResourceType; 1683 1684 typedef struct NvmeDirectiveIdentify { 1685 uint8_t supported; 1686 uint8_t unused1[31]; 1687 uint8_t enabled; 1688 uint8_t unused33[31]; 1689 uint8_t persistent; 1690 uint8_t unused65[31]; 1691 uint8_t rsvd64[4000]; 1692 } NvmeDirectiveIdentify; 1693 1694 enum NvmeDirectiveTypes { 1695 NVME_DIRECTIVE_IDENTIFY = 0x0, 1696 NVME_DIRECTIVE_DATA_PLACEMENT = 0x2, 1697 }; 1698 1699 enum NvmeDirectiveOperations { 1700 NVME_DIRECTIVE_RETURN_PARAMS = 0x1, 1701 }; 1702 1703 typedef struct QEMU_PACKED NvmeFdpConfsHdr { 1704 uint16_t num_confs; 1705 uint8_t version; 1706 uint8_t rsvd3; 1707 uint32_t size; 1708 uint8_t rsvd8[8]; 1709 } NvmeFdpConfsHdr; 1710 1711 REG8(FDPA, 0x0) 1712 FIELD(FDPA, RGIF, 0, 4) 1713 FIELD(FDPA, VWC, 4, 1) 1714 FIELD(FDPA, VALID, 7, 1); 1715 1716 typedef struct QEMU_PACKED NvmeFdpDescrHdr { 1717 uint16_t descr_size; 1718 uint8_t fdpa; 1719 uint8_t vss; 1720 uint32_t nrg; 1721 uint16_t nruh; 1722 uint16_t maxpids; 1723 uint32_t nnss; 1724 uint64_t runs; 1725 uint32_t erutl; 1726 uint8_t rsvd28[36]; 1727 } NvmeFdpDescrHdr; 1728 1729 enum NvmeRuhType { 1730 NVME_RUHT_INITIALLY_ISOLATED = 1, 1731 NVME_RUHT_PERSISTENTLY_ISOLATED = 2, 1732 }; 1733 1734 typedef struct QEMU_PACKED NvmeRuhDescr { 1735 uint8_t ruht; 1736 uint8_t rsvd1[3]; 1737 } NvmeRuhDescr; 1738 1739 typedef struct QEMU_PACKED NvmeRuhuLog { 1740 uint16_t nruh; 1741 uint8_t rsvd2[6]; 1742 } NvmeRuhuLog; 1743 1744 enum NvmeRuhAttributes { 1745 NVME_RUHA_UNUSED = 0, 1746 NVME_RUHA_HOST = 1, 1747 NVME_RUHA_CTRL = 2, 1748 }; 1749 1750 typedef struct QEMU_PACKED NvmeRuhuDescr { 1751 uint8_t ruha; 1752 uint8_t rsvd1[7]; 1753 } NvmeRuhuDescr; 1754 1755 typedef struct QEMU_PACKED NvmeFdpStatsLog { 1756 uint64_t hbmw[2]; 1757 uint64_t mbmw[2]; 1758 uint64_t mbe[2]; 1759 uint8_t rsvd48[16]; 1760 } NvmeFdpStatsLog; 1761 1762 typedef struct QEMU_PACKED NvmeFdpEventsLog { 1763 uint32_t num_events; 1764 uint8_t rsvd4[60]; 1765 } NvmeFdpEventsLog; 1766 1767 enum NvmeFdpEventType { 1768 FDP_EVT_RU_NOT_FULLY_WRITTEN = 0x0, 1769 FDP_EVT_RU_ATL_EXCEEDED = 0x1, 1770 FDP_EVT_CTRL_RESET_RUH = 0x2, 1771 FDP_EVT_INVALID_PID = 0x3, 1772 FDP_EVT_MEDIA_REALLOC = 0x80, 1773 FDP_EVT_RUH_IMPLICIT_RU_CHANGE = 0x81, 1774 }; 1775 1776 enum NvmeFdpEventFlags { 1777 FDPEF_PIV = 1 << 0, 1778 FDPEF_NSIDV = 1 << 1, 1779 FDPEF_LV = 1 << 2, 1780 }; 1781 1782 typedef struct QEMU_PACKED NvmeFdpEvent { 1783 uint8_t type; 1784 uint8_t flags; 1785 uint16_t pid; 1786 uint64_t timestamp; 1787 uint32_t nsid; 1788 uint64_t type_specific[2]; 1789 uint16_t rgid; 1790 uint8_t ruhid; 1791 uint8_t rsvd35[5]; 1792 uint64_t vendor[3]; 1793 } NvmeFdpEvent; 1794 1795 typedef struct QEMU_PACKED NvmePhidList { 1796 uint16_t nnruhd; 1797 uint8_t rsvd2[6]; 1798 } NvmePhidList; 1799 1800 typedef struct QEMU_PACKED NvmePhidDescr { 1801 uint8_t ruht; 1802 uint8_t rsvd1; 1803 uint16_t ruhid; 1804 } NvmePhidDescr; 1805 1806 REG32(FEAT_FDP, 0x0) 1807 FIELD(FEAT_FDP, FDPE, 0, 1) 1808 FIELD(FEAT_FDP, CONF_NDX, 8, 8); 1809 1810 typedef struct QEMU_PACKED NvmeFdpEventDescr { 1811 uint8_t evt; 1812 uint8_t evta; 1813 } NvmeFdpEventDescr; 1814 1815 REG32(NVME_IOMR, 0x0) 1816 FIELD(NVME_IOMR, MO, 0, 8) 1817 FIELD(NVME_IOMR, MOS, 16, 16); 1818 1819 enum NvmeIomr2Mo { 1820 NVME_IOMR_MO_NOP = 0x0, 1821 NVME_IOMR_MO_RUH_STATUS = 0x1, 1822 NVME_IOMR_MO_VENDOR_SPECIFIC = 0x255, 1823 }; 1824 1825 typedef struct QEMU_PACKED NvmeRuhStatus { 1826 uint8_t rsvd0[14]; 1827 uint16_t nruhsd; 1828 } NvmeRuhStatus; 1829 1830 typedef struct QEMU_PACKED NvmeRuhStatusDescr { 1831 uint16_t pid; 1832 uint16_t ruhid; 1833 uint32_t earutr; 1834 uint64_t ruamw; 1835 uint8_t rsvd16[16]; 1836 } NvmeRuhStatusDescr; 1837 1838 REG32(NVME_IOMS, 0x0) 1839 FIELD(NVME_IOMS, MO, 0, 8) 1840 FIELD(NVME_IOMS, MOS, 16, 16); 1841 1842 enum NvmeIoms2Mo { 1843 NVME_IOMS_MO_NOP = 0x0, 1844 NVME_IOMS_MO_RUH_UPDATE = 0x1, 1845 }; 1846 1847 static inline void _nvme_check_size(void) 1848 { 1849 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1850 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1851 QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); 1852 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1853 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1854 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat0_2) != 32); 1855 QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat1_3) != 40); 1856 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1857 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1858 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1859 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1860 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1861 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1862 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1863 QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64); 1864 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1865 QEMU_BUILD_BUG_ON(sizeof(NvmeHostBehaviorSupport) != 512); 1866 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1867 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1868 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1869 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1870 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1871 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); 1872 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096); 1873 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); 1874 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); 1875 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1876 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) != 4096); 1877 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); 1878 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1879 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1880 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); 1881 QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 16); 1882 QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) != 4096); 1883 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32); 1884 QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096); 1885 QEMU_BUILD_BUG_ON(sizeof(NvmeEndGrpLog) != 512); 1886 QEMU_BUILD_BUG_ON(sizeof(NvmeDirectiveIdentify) != 4096); 1887 } 1888 #endif 1889