1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint32_t rsvd1; 11 uint32_t csts; 12 uint32_t nssrc; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint8_t padding[3520]; /* not used by QEMU */ 19 uint32_t pmrcap; 20 uint32_t pmrctl; 21 uint32_t pmrsts; 22 uint32_t pmrebs; 23 uint32_t pmrswtp; 24 uint64_t pmrmsc; 25 uint8_t reserved[484]; 26 } NvmeBar; 27 28 enum NvmeCapShift { 29 CAP_MQES_SHIFT = 0, 30 CAP_CQR_SHIFT = 16, 31 CAP_AMS_SHIFT = 17, 32 CAP_TO_SHIFT = 24, 33 CAP_DSTRD_SHIFT = 32, 34 CAP_NSSRS_SHIFT = 36, 35 CAP_CSS_SHIFT = 37, 36 CAP_MPSMIN_SHIFT = 48, 37 CAP_MPSMAX_SHIFT = 52, 38 CAP_PMR_SHIFT = 56, 39 }; 40 41 enum NvmeCapMask { 42 CAP_MQES_MASK = 0xffff, 43 CAP_CQR_MASK = 0x1, 44 CAP_AMS_MASK = 0x3, 45 CAP_TO_MASK = 0xff, 46 CAP_DSTRD_MASK = 0xf, 47 CAP_NSSRS_MASK = 0x1, 48 CAP_CSS_MASK = 0xff, 49 CAP_MPSMIN_MASK = 0xf, 50 CAP_MPSMAX_MASK = 0xf, 51 CAP_PMR_MASK = 0x1, 52 }; 53 54 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 55 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 56 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 57 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 58 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 59 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 60 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 61 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 62 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 63 64 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 65 << CAP_MQES_SHIFT) 66 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 67 << CAP_CQR_SHIFT) 68 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 69 << CAP_AMS_SHIFT) 70 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 71 << CAP_TO_SHIFT) 72 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 73 << CAP_DSTRD_SHIFT) 74 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 75 << CAP_NSSRS_SHIFT) 76 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 77 << CAP_CSS_SHIFT) 78 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 79 << CAP_MPSMIN_SHIFT) 80 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 81 << CAP_MPSMAX_SHIFT) 82 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ 83 << CAP_PMR_SHIFT) 84 85 enum NvmeCapCss { 86 NVME_CAP_CSS_NVM = 1 << 0, 87 NVME_CAP_CSS_CSI_SUPP = 1 << 6, 88 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 89 }; 90 91 enum NvmeCcShift { 92 CC_EN_SHIFT = 0, 93 CC_CSS_SHIFT = 4, 94 CC_MPS_SHIFT = 7, 95 CC_AMS_SHIFT = 11, 96 CC_SHN_SHIFT = 14, 97 CC_IOSQES_SHIFT = 16, 98 CC_IOCQES_SHIFT = 20, 99 }; 100 101 enum NvmeCcMask { 102 CC_EN_MASK = 0x1, 103 CC_CSS_MASK = 0x7, 104 CC_MPS_MASK = 0xf, 105 CC_AMS_MASK = 0x7, 106 CC_SHN_MASK = 0x3, 107 CC_IOSQES_MASK = 0xf, 108 CC_IOCQES_MASK = 0xf, 109 }; 110 111 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 112 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 113 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 114 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 115 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 116 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 117 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 118 119 enum NvmeCcCss { 120 NVME_CC_CSS_NVM = 0x0, 121 NVME_CC_CSS_CSI = 0x6, 122 NVME_CC_CSS_ADMIN_ONLY = 0x7, 123 }; 124 125 #define NVME_SET_CC_EN(cc, val) \ 126 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 127 #define NVME_SET_CC_CSS(cc, val) \ 128 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 129 #define NVME_SET_CC_MPS(cc, val) \ 130 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 131 #define NVME_SET_CC_AMS(cc, val) \ 132 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 133 #define NVME_SET_CC_SHN(cc, val) \ 134 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 135 #define NVME_SET_CC_IOSQES(cc, val) \ 136 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 137 #define NVME_SET_CC_IOCQES(cc, val) \ 138 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 139 140 enum NvmeCstsShift { 141 CSTS_RDY_SHIFT = 0, 142 CSTS_CFS_SHIFT = 1, 143 CSTS_SHST_SHIFT = 2, 144 CSTS_NSSRO_SHIFT = 4, 145 }; 146 147 enum NvmeCstsMask { 148 CSTS_RDY_MASK = 0x1, 149 CSTS_CFS_MASK = 0x1, 150 CSTS_SHST_MASK = 0x3, 151 CSTS_NSSRO_MASK = 0x1, 152 }; 153 154 enum NvmeCsts { 155 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 156 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 157 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 158 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 159 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 160 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 161 }; 162 163 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 164 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 165 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 166 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 167 168 enum NvmeAqaShift { 169 AQA_ASQS_SHIFT = 0, 170 AQA_ACQS_SHIFT = 16, 171 }; 172 173 enum NvmeAqaMask { 174 AQA_ASQS_MASK = 0xfff, 175 AQA_ACQS_MASK = 0xfff, 176 }; 177 178 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 179 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 180 181 enum NvmeCmblocShift { 182 CMBLOC_BIR_SHIFT = 0, 183 CMBLOC_OFST_SHIFT = 12, 184 }; 185 186 enum NvmeCmblocMask { 187 CMBLOC_BIR_MASK = 0x7, 188 CMBLOC_OFST_MASK = 0xfffff, 189 }; 190 191 #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ 192 CMBLOC_BIR_MASK) 193 #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ 194 CMBLOC_OFST_MASK) 195 196 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 197 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 198 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 199 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 200 201 enum NvmeCmbszShift { 202 CMBSZ_SQS_SHIFT = 0, 203 CMBSZ_CQS_SHIFT = 1, 204 CMBSZ_LISTS_SHIFT = 2, 205 CMBSZ_RDS_SHIFT = 3, 206 CMBSZ_WDS_SHIFT = 4, 207 CMBSZ_SZU_SHIFT = 8, 208 CMBSZ_SZ_SHIFT = 12, 209 }; 210 211 enum NvmeCmbszMask { 212 CMBSZ_SQS_MASK = 0x1, 213 CMBSZ_CQS_MASK = 0x1, 214 CMBSZ_LISTS_MASK = 0x1, 215 CMBSZ_RDS_MASK = 0x1, 216 CMBSZ_WDS_MASK = 0x1, 217 CMBSZ_SZU_MASK = 0xf, 218 CMBSZ_SZ_MASK = 0xfffff, 219 }; 220 221 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 222 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 223 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 224 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 225 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 226 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 227 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 228 229 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 230 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 231 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 232 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 233 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 234 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 235 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 236 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 237 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 238 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 239 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 240 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 241 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 242 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 243 244 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 245 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 246 247 enum NvmePmrcapShift { 248 PMRCAP_RDS_SHIFT = 3, 249 PMRCAP_WDS_SHIFT = 4, 250 PMRCAP_BIR_SHIFT = 5, 251 PMRCAP_PMRTU_SHIFT = 8, 252 PMRCAP_PMRWBM_SHIFT = 10, 253 PMRCAP_PMRTO_SHIFT = 16, 254 PMRCAP_CMSS_SHIFT = 24, 255 }; 256 257 enum NvmePmrcapMask { 258 PMRCAP_RDS_MASK = 0x1, 259 PMRCAP_WDS_MASK = 0x1, 260 PMRCAP_BIR_MASK = 0x7, 261 PMRCAP_PMRTU_MASK = 0x3, 262 PMRCAP_PMRWBM_MASK = 0xf, 263 PMRCAP_PMRTO_MASK = 0xff, 264 PMRCAP_CMSS_MASK = 0x1, 265 }; 266 267 #define NVME_PMRCAP_RDS(pmrcap) \ 268 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 269 #define NVME_PMRCAP_WDS(pmrcap) \ 270 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 271 #define NVME_PMRCAP_BIR(pmrcap) \ 272 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 273 #define NVME_PMRCAP_PMRTU(pmrcap) \ 274 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 275 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 276 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 277 #define NVME_PMRCAP_PMRTO(pmrcap) \ 278 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 279 #define NVME_PMRCAP_CMSS(pmrcap) \ 280 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 281 282 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 283 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 284 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 285 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 286 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 287 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 288 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 289 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 290 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 291 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 292 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 293 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 294 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 295 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 296 297 enum NvmePmrctlShift { 298 PMRCTL_EN_SHIFT = 0, 299 }; 300 301 enum NvmePmrctlMask { 302 PMRCTL_EN_MASK = 0x1, 303 }; 304 305 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 306 307 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 308 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 309 310 enum NvmePmrstsShift { 311 PMRSTS_ERR_SHIFT = 0, 312 PMRSTS_NRDY_SHIFT = 8, 313 PMRSTS_HSTS_SHIFT = 9, 314 PMRSTS_CBAI_SHIFT = 12, 315 }; 316 317 enum NvmePmrstsMask { 318 PMRSTS_ERR_MASK = 0xff, 319 PMRSTS_NRDY_MASK = 0x1, 320 PMRSTS_HSTS_MASK = 0x7, 321 PMRSTS_CBAI_MASK = 0x1, 322 }; 323 324 #define NVME_PMRSTS_ERR(pmrsts) \ 325 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 326 #define NVME_PMRSTS_NRDY(pmrsts) \ 327 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 328 #define NVME_PMRSTS_HSTS(pmrsts) \ 329 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 330 #define NVME_PMRSTS_CBAI(pmrsts) \ 331 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 332 333 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 334 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 335 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 336 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 337 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 338 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 339 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 340 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 341 342 enum NvmePmrebsShift { 343 PMREBS_PMRSZU_SHIFT = 0, 344 PMREBS_RBB_SHIFT = 4, 345 PMREBS_PMRWBZ_SHIFT = 8, 346 }; 347 348 enum NvmePmrebsMask { 349 PMREBS_PMRSZU_MASK = 0xf, 350 PMREBS_RBB_MASK = 0x1, 351 PMREBS_PMRWBZ_MASK = 0xffffff, 352 }; 353 354 #define NVME_PMREBS_PMRSZU(pmrebs) \ 355 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 356 #define NVME_PMREBS_RBB(pmrebs) \ 357 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 358 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 359 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 360 361 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 362 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 363 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 364 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 365 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 366 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 367 368 enum NvmePmrswtpShift { 369 PMRSWTP_PMRSWTU_SHIFT = 0, 370 PMRSWTP_PMRSWTV_SHIFT = 8, 371 }; 372 373 enum NvmePmrswtpMask { 374 PMRSWTP_PMRSWTU_MASK = 0xf, 375 PMRSWTP_PMRSWTV_MASK = 0xffffff, 376 }; 377 378 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 379 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 380 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 381 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 382 383 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 384 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 385 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 386 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 387 388 enum NvmePmrmscShift { 389 PMRMSC_CMSE_SHIFT = 1, 390 PMRMSC_CBA_SHIFT = 12, 391 }; 392 393 enum NvmePmrmscMask { 394 PMRMSC_CMSE_MASK = 0x1, 395 PMRMSC_CBA_MASK = 0xfffffffffffff, 396 }; 397 398 #define NVME_PMRMSC_CMSE(pmrmsc) \ 399 ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 400 #define NVME_PMRMSC_CBA(pmrmsc) \ 401 ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 402 403 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 404 (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 405 #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 406 (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 407 408 enum NvmeSglDescriptorType { 409 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 410 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 411 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 412 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 413 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 414 415 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 416 }; 417 418 enum NvmeSglDescriptorSubtype { 419 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 420 }; 421 422 typedef struct QEMU_PACKED NvmeSglDescriptor { 423 uint64_t addr; 424 uint32_t len; 425 uint8_t rsvd[3]; 426 uint8_t type; 427 } NvmeSglDescriptor; 428 429 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 430 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 431 432 typedef union NvmeCmdDptr { 433 struct { 434 uint64_t prp1; 435 uint64_t prp2; 436 }; 437 438 NvmeSglDescriptor sgl; 439 } NvmeCmdDptr; 440 441 enum NvmePsdt { 442 NVME_PSDT_PRP = 0x0, 443 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 444 NVME_PSDT_SGL_MPTR_SGL = 0x2, 445 }; 446 447 typedef struct QEMU_PACKED NvmeCmd { 448 uint8_t opcode; 449 uint8_t flags; 450 uint16_t cid; 451 uint32_t nsid; 452 uint64_t res1; 453 uint64_t mptr; 454 NvmeCmdDptr dptr; 455 uint32_t cdw10; 456 uint32_t cdw11; 457 uint32_t cdw12; 458 uint32_t cdw13; 459 uint32_t cdw14; 460 uint32_t cdw15; 461 } NvmeCmd; 462 463 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 464 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 465 466 enum NvmeAdminCommands { 467 NVME_ADM_CMD_DELETE_SQ = 0x00, 468 NVME_ADM_CMD_CREATE_SQ = 0x01, 469 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 470 NVME_ADM_CMD_DELETE_CQ = 0x04, 471 NVME_ADM_CMD_CREATE_CQ = 0x05, 472 NVME_ADM_CMD_IDENTIFY = 0x06, 473 NVME_ADM_CMD_ABORT = 0x08, 474 NVME_ADM_CMD_SET_FEATURES = 0x09, 475 NVME_ADM_CMD_GET_FEATURES = 0x0a, 476 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 477 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 478 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 479 NVME_ADM_CMD_FORMAT_NVM = 0x80, 480 NVME_ADM_CMD_SECURITY_SEND = 0x81, 481 NVME_ADM_CMD_SECURITY_RECV = 0x82, 482 }; 483 484 enum NvmeIoCommands { 485 NVME_CMD_FLUSH = 0x00, 486 NVME_CMD_WRITE = 0x01, 487 NVME_CMD_READ = 0x02, 488 NVME_CMD_WRITE_UNCOR = 0x04, 489 NVME_CMD_COMPARE = 0x05, 490 NVME_CMD_WRITE_ZEROES = 0x08, 491 NVME_CMD_DSM = 0x09, 492 NVME_CMD_ZONE_MGMT_SEND = 0x79, 493 NVME_CMD_ZONE_MGMT_RECV = 0x7a, 494 NVME_CMD_ZONE_APPEND = 0x7d, 495 }; 496 497 typedef struct QEMU_PACKED NvmeDeleteQ { 498 uint8_t opcode; 499 uint8_t flags; 500 uint16_t cid; 501 uint32_t rsvd1[9]; 502 uint16_t qid; 503 uint16_t rsvd10; 504 uint32_t rsvd11[5]; 505 } NvmeDeleteQ; 506 507 typedef struct QEMU_PACKED NvmeCreateCq { 508 uint8_t opcode; 509 uint8_t flags; 510 uint16_t cid; 511 uint32_t rsvd1[5]; 512 uint64_t prp1; 513 uint64_t rsvd8; 514 uint16_t cqid; 515 uint16_t qsize; 516 uint16_t cq_flags; 517 uint16_t irq_vector; 518 uint32_t rsvd12[4]; 519 } NvmeCreateCq; 520 521 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 522 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 523 524 enum NvmeFlagsCq { 525 NVME_CQ_PC = 1, 526 NVME_CQ_IEN = 2, 527 }; 528 529 typedef struct QEMU_PACKED NvmeCreateSq { 530 uint8_t opcode; 531 uint8_t flags; 532 uint16_t cid; 533 uint32_t rsvd1[5]; 534 uint64_t prp1; 535 uint64_t rsvd8; 536 uint16_t sqid; 537 uint16_t qsize; 538 uint16_t sq_flags; 539 uint16_t cqid; 540 uint32_t rsvd12[4]; 541 } NvmeCreateSq; 542 543 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 544 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 545 546 enum NvmeFlagsSq { 547 NVME_SQ_PC = 1, 548 549 NVME_SQ_PRIO_URGENT = 0, 550 NVME_SQ_PRIO_HIGH = 1, 551 NVME_SQ_PRIO_NORMAL = 2, 552 NVME_SQ_PRIO_LOW = 3, 553 }; 554 555 typedef struct QEMU_PACKED NvmeIdentify { 556 uint8_t opcode; 557 uint8_t flags; 558 uint16_t cid; 559 uint32_t nsid; 560 uint64_t rsvd2[2]; 561 uint64_t prp1; 562 uint64_t prp2; 563 uint8_t cns; 564 uint8_t rsvd10; 565 uint16_t ctrlid; 566 uint16_t nvmsetid; 567 uint8_t rsvd11; 568 uint8_t csi; 569 uint32_t rsvd12[4]; 570 } NvmeIdentify; 571 572 typedef struct QEMU_PACKED NvmeRwCmd { 573 uint8_t opcode; 574 uint8_t flags; 575 uint16_t cid; 576 uint32_t nsid; 577 uint64_t rsvd2; 578 uint64_t mptr; 579 NvmeCmdDptr dptr; 580 uint64_t slba; 581 uint16_t nlb; 582 uint16_t control; 583 uint32_t dsmgmt; 584 uint32_t reftag; 585 uint16_t apptag; 586 uint16_t appmask; 587 } NvmeRwCmd; 588 589 enum { 590 NVME_RW_LR = 1 << 15, 591 NVME_RW_FUA = 1 << 14, 592 NVME_RW_DSM_FREQ_UNSPEC = 0, 593 NVME_RW_DSM_FREQ_TYPICAL = 1, 594 NVME_RW_DSM_FREQ_RARE = 2, 595 NVME_RW_DSM_FREQ_READS = 3, 596 NVME_RW_DSM_FREQ_WRITES = 4, 597 NVME_RW_DSM_FREQ_RW = 5, 598 NVME_RW_DSM_FREQ_ONCE = 6, 599 NVME_RW_DSM_FREQ_PREFETCH = 7, 600 NVME_RW_DSM_FREQ_TEMP = 8, 601 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 602 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 603 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 604 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 605 NVME_RW_DSM_SEQ_REQ = 1 << 6, 606 NVME_RW_DSM_COMPRESSED = 1 << 7, 607 NVME_RW_PRINFO_PRACT = 1 << 13, 608 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 609 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 610 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 611 }; 612 613 typedef struct QEMU_PACKED NvmeDsmCmd { 614 uint8_t opcode; 615 uint8_t flags; 616 uint16_t cid; 617 uint32_t nsid; 618 uint64_t rsvd2[2]; 619 NvmeCmdDptr dptr; 620 uint32_t nr; 621 uint32_t attributes; 622 uint32_t rsvd12[4]; 623 } NvmeDsmCmd; 624 625 enum { 626 NVME_DSMGMT_IDR = 1 << 0, 627 NVME_DSMGMT_IDW = 1 << 1, 628 NVME_DSMGMT_AD = 1 << 2, 629 }; 630 631 typedef struct QEMU_PACKED NvmeDsmRange { 632 uint32_t cattr; 633 uint32_t nlb; 634 uint64_t slba; 635 } NvmeDsmRange; 636 637 enum NvmeAsyncEventRequest { 638 NVME_AER_TYPE_ERROR = 0, 639 NVME_AER_TYPE_SMART = 1, 640 NVME_AER_TYPE_IO_SPECIFIC = 6, 641 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 642 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 643 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 644 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 645 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 646 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 647 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 648 NVME_AER_INFO_SMART_RELIABILITY = 0, 649 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 650 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 651 }; 652 653 typedef struct QEMU_PACKED NvmeAerResult { 654 uint8_t event_type; 655 uint8_t event_info; 656 uint8_t log_page; 657 uint8_t resv; 658 } NvmeAerResult; 659 660 typedef struct QEMU_PACKED NvmeZonedResult { 661 uint64_t slba; 662 } NvmeZonedResult; 663 664 typedef struct QEMU_PACKED NvmeCqe { 665 uint32_t result; 666 uint32_t dw1; 667 uint16_t sq_head; 668 uint16_t sq_id; 669 uint16_t cid; 670 uint16_t status; 671 } NvmeCqe; 672 673 enum NvmeStatusCodes { 674 NVME_SUCCESS = 0x0000, 675 NVME_INVALID_OPCODE = 0x0001, 676 NVME_INVALID_FIELD = 0x0002, 677 NVME_CID_CONFLICT = 0x0003, 678 NVME_DATA_TRAS_ERROR = 0x0004, 679 NVME_POWER_LOSS_ABORT = 0x0005, 680 NVME_INTERNAL_DEV_ERROR = 0x0006, 681 NVME_CMD_ABORT_REQ = 0x0007, 682 NVME_CMD_ABORT_SQ_DEL = 0x0008, 683 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 684 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 685 NVME_INVALID_NSID = 0x000b, 686 NVME_CMD_SEQ_ERROR = 0x000c, 687 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 688 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 689 NVME_DATA_SGL_LEN_INVALID = 0x000f, 690 NVME_MD_SGL_LEN_INVALID = 0x0010, 691 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 692 NVME_INVALID_USE_OF_CMB = 0x0012, 693 NVME_INVALID_PRP_OFFSET = 0x0013, 694 NVME_CMD_SET_CMB_REJECTED = 0x002b, 695 NVME_INVALID_CMD_SET = 0x002c, 696 NVME_LBA_RANGE = 0x0080, 697 NVME_CAP_EXCEEDED = 0x0081, 698 NVME_NS_NOT_READY = 0x0082, 699 NVME_NS_RESV_CONFLICT = 0x0083, 700 NVME_INVALID_CQID = 0x0100, 701 NVME_INVALID_QID = 0x0101, 702 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 703 NVME_ACL_EXCEEDED = 0x0103, 704 NVME_RESERVED = 0x0104, 705 NVME_AER_LIMIT_EXCEEDED = 0x0105, 706 NVME_INVALID_FW_SLOT = 0x0106, 707 NVME_INVALID_FW_IMAGE = 0x0107, 708 NVME_INVALID_IRQ_VECTOR = 0x0108, 709 NVME_INVALID_LOG_ID = 0x0109, 710 NVME_INVALID_FORMAT = 0x010a, 711 NVME_FW_REQ_RESET = 0x010b, 712 NVME_INVALID_QUEUE_DEL = 0x010c, 713 NVME_FID_NOT_SAVEABLE = 0x010d, 714 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 715 NVME_FEAT_NOT_NS_SPEC = 0x010f, 716 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 717 NVME_CONFLICTING_ATTRS = 0x0180, 718 NVME_INVALID_PROT_INFO = 0x0181, 719 NVME_WRITE_TO_RO = 0x0182, 720 NVME_ZONE_BOUNDARY_ERROR = 0x01b8, 721 NVME_ZONE_FULL = 0x01b9, 722 NVME_ZONE_READ_ONLY = 0x01ba, 723 NVME_ZONE_OFFLINE = 0x01bb, 724 NVME_ZONE_INVALID_WRITE = 0x01bc, 725 NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, 726 NVME_ZONE_TOO_MANY_OPEN = 0x01be, 727 NVME_ZONE_INVAL_TRANSITION = 0x01bf, 728 NVME_WRITE_FAULT = 0x0280, 729 NVME_UNRECOVERED_READ = 0x0281, 730 NVME_E2E_GUARD_ERROR = 0x0282, 731 NVME_E2E_APP_ERROR = 0x0283, 732 NVME_E2E_REF_ERROR = 0x0284, 733 NVME_CMP_FAILURE = 0x0285, 734 NVME_ACCESS_DENIED = 0x0286, 735 NVME_DULB = 0x0287, 736 NVME_MORE = 0x2000, 737 NVME_DNR = 0x4000, 738 NVME_NO_COMPLETE = 0xffff, 739 }; 740 741 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 742 uint8_t afi; 743 uint8_t reserved1[7]; 744 uint8_t frs1[8]; 745 uint8_t frs2[8]; 746 uint8_t frs3[8]; 747 uint8_t frs4[8]; 748 uint8_t frs5[8]; 749 uint8_t frs6[8]; 750 uint8_t frs7[8]; 751 uint8_t reserved2[448]; 752 } NvmeFwSlotInfoLog; 753 754 typedef struct QEMU_PACKED NvmeErrorLog { 755 uint64_t error_count; 756 uint16_t sqid; 757 uint16_t cid; 758 uint16_t status_field; 759 uint16_t param_error_location; 760 uint64_t lba; 761 uint32_t nsid; 762 uint8_t vs; 763 uint8_t resv[35]; 764 } NvmeErrorLog; 765 766 typedef struct QEMU_PACKED NvmeSmartLog { 767 uint8_t critical_warning; 768 uint16_t temperature; 769 uint8_t available_spare; 770 uint8_t available_spare_threshold; 771 uint8_t percentage_used; 772 uint8_t reserved1[26]; 773 uint64_t data_units_read[2]; 774 uint64_t data_units_written[2]; 775 uint64_t host_read_commands[2]; 776 uint64_t host_write_commands[2]; 777 uint64_t controller_busy_time[2]; 778 uint64_t power_cycles[2]; 779 uint64_t power_on_hours[2]; 780 uint64_t unsafe_shutdowns[2]; 781 uint64_t media_errors[2]; 782 uint64_t number_of_error_log_entries[2]; 783 uint8_t reserved2[320]; 784 } NvmeSmartLog; 785 786 enum NvmeSmartWarn { 787 NVME_SMART_SPARE = 1 << 0, 788 NVME_SMART_TEMPERATURE = 1 << 1, 789 NVME_SMART_RELIABILITY = 1 << 2, 790 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 791 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 792 NVME_SMART_PMR_UNRELIABLE = 1 << 5, 793 }; 794 795 typedef struct NvmeEffectsLog { 796 uint32_t acs[256]; 797 uint32_t iocs[256]; 798 uint8_t resv[2048]; 799 } NvmeEffectsLog; 800 801 enum { 802 NVME_CMD_EFF_CSUPP = 1 << 0, 803 NVME_CMD_EFF_LBCC = 1 << 1, 804 NVME_CMD_EFF_NCC = 1 << 2, 805 NVME_CMD_EFF_NIC = 1 << 3, 806 NVME_CMD_EFF_CCC = 1 << 4, 807 NVME_CMD_EFF_CSE_MASK = 3 << 16, 808 NVME_CMD_EFF_UUID_SEL = 1 << 19, 809 }; 810 811 enum NvmeLogIdentifier { 812 NVME_LOG_ERROR_INFO = 0x01, 813 NVME_LOG_SMART_INFO = 0x02, 814 NVME_LOG_FW_SLOT_INFO = 0x03, 815 NVME_LOG_CMD_EFFECTS = 0x05, 816 }; 817 818 typedef struct QEMU_PACKED NvmePSD { 819 uint16_t mp; 820 uint16_t reserved; 821 uint32_t enlat; 822 uint32_t exlat; 823 uint8_t rrt; 824 uint8_t rrl; 825 uint8_t rwt; 826 uint8_t rwl; 827 uint8_t resv[16]; 828 } NvmePSD; 829 830 #define NVME_IDENTIFY_DATA_SIZE 4096 831 832 enum NvmeIdCns { 833 NVME_ID_CNS_NS = 0x00, 834 NVME_ID_CNS_CTRL = 0x01, 835 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 836 NVME_ID_CNS_NS_DESCR_LIST = 0x03, 837 NVME_ID_CNS_CS_NS = 0x05, 838 NVME_ID_CNS_CS_CTRL = 0x06, 839 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 840 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 841 NVME_ID_CNS_NS_PRESENT = 0x11, 842 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 843 NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 844 NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 845 }; 846 847 typedef struct QEMU_PACKED NvmeIdCtrl { 848 uint16_t vid; 849 uint16_t ssvid; 850 uint8_t sn[20]; 851 uint8_t mn[40]; 852 uint8_t fr[8]; 853 uint8_t rab; 854 uint8_t ieee[3]; 855 uint8_t cmic; 856 uint8_t mdts; 857 uint16_t cntlid; 858 uint32_t ver; 859 uint32_t rtd3r; 860 uint32_t rtd3e; 861 uint32_t oaes; 862 uint32_t ctratt; 863 uint8_t rsvd100[12]; 864 uint8_t fguid[16]; 865 uint8_t rsvd128[128]; 866 uint16_t oacs; 867 uint8_t acl; 868 uint8_t aerl; 869 uint8_t frmw; 870 uint8_t lpa; 871 uint8_t elpe; 872 uint8_t npss; 873 uint8_t avscc; 874 uint8_t apsta; 875 uint16_t wctemp; 876 uint16_t cctemp; 877 uint16_t mtfa; 878 uint32_t hmpre; 879 uint32_t hmmin; 880 uint8_t tnvmcap[16]; 881 uint8_t unvmcap[16]; 882 uint32_t rpmbs; 883 uint16_t edstt; 884 uint8_t dsto; 885 uint8_t fwug; 886 uint16_t kas; 887 uint16_t hctma; 888 uint16_t mntmt; 889 uint16_t mxtmt; 890 uint32_t sanicap; 891 uint8_t rsvd332[180]; 892 uint8_t sqes; 893 uint8_t cqes; 894 uint16_t maxcmd; 895 uint32_t nn; 896 uint16_t oncs; 897 uint16_t fuses; 898 uint8_t fna; 899 uint8_t vwc; 900 uint16_t awun; 901 uint16_t awupf; 902 uint8_t nvscc; 903 uint8_t rsvd531; 904 uint16_t acwu; 905 uint8_t rsvd534[2]; 906 uint32_t sgls; 907 uint8_t rsvd540[228]; 908 uint8_t subnqn[256]; 909 uint8_t rsvd1024[1024]; 910 NvmePSD psd[32]; 911 uint8_t vs[1024]; 912 } NvmeIdCtrl; 913 914 typedef struct NvmeIdCtrlZoned { 915 uint8_t zasl; 916 uint8_t rsvd1[4095]; 917 } NvmeIdCtrlZoned; 918 919 enum NvmeIdCtrlOacs { 920 NVME_OACS_SECURITY = 1 << 0, 921 NVME_OACS_FORMAT = 1 << 1, 922 NVME_OACS_FW = 1 << 2, 923 }; 924 925 enum NvmeIdCtrlOncs { 926 NVME_ONCS_COMPARE = 1 << 0, 927 NVME_ONCS_WRITE_UNCORR = 1 << 1, 928 NVME_ONCS_DSM = 1 << 2, 929 NVME_ONCS_WRITE_ZEROES = 1 << 3, 930 NVME_ONCS_FEATURES = 1 << 4, 931 NVME_ONCS_RESRVATIONS = 1 << 5, 932 NVME_ONCS_TIMESTAMP = 1 << 6, 933 }; 934 935 enum NvmeIdCtrlFrmw { 936 NVME_FRMW_SLOT1_RO = 1 << 0, 937 }; 938 939 enum NvmeIdCtrlLpa { 940 NVME_LPA_NS_SMART = 1 << 0, 941 NVME_LPA_CSE = 1 << 1, 942 NVME_LPA_EXTENDED = 1 << 2, 943 }; 944 945 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 946 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 947 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 948 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 949 950 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 951 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 952 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 953 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 954 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 955 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 956 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 957 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 958 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 959 960 #define NVME_ARB_AB(arb) (arb & 0x7) 961 #define NVME_ARB_AB_NOLIMIT 0x7 962 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 963 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 964 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 965 966 #define NVME_INTC_THR(intc) (intc & 0xff) 967 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 968 969 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 970 971 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 972 #define NVME_TEMP_THSEL_OVER 0x0 973 #define NVME_TEMP_THSEL_UNDER 0x1 974 975 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 976 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 977 978 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 979 980 #define NVME_AEC_SMART(aec) (aec & 0xff) 981 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 982 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 983 984 #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 985 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 986 987 enum NvmeFeatureIds { 988 NVME_ARBITRATION = 0x1, 989 NVME_POWER_MANAGEMENT = 0x2, 990 NVME_LBA_RANGE_TYPE = 0x3, 991 NVME_TEMPERATURE_THRESHOLD = 0x4, 992 NVME_ERROR_RECOVERY = 0x5, 993 NVME_VOLATILE_WRITE_CACHE = 0x6, 994 NVME_NUMBER_OF_QUEUES = 0x7, 995 NVME_INTERRUPT_COALESCING = 0x8, 996 NVME_INTERRUPT_VECTOR_CONF = 0x9, 997 NVME_WRITE_ATOMICITY = 0xa, 998 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 999 NVME_TIMESTAMP = 0xe, 1000 NVME_COMMAND_SET_PROFILE = 0x19, 1001 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 1002 NVME_FID_MAX = 0x100, 1003 }; 1004 1005 typedef enum NvmeFeatureCap { 1006 NVME_FEAT_CAP_SAVE = 1 << 0, 1007 NVME_FEAT_CAP_NS = 1 << 1, 1008 NVME_FEAT_CAP_CHANGE = 1 << 2, 1009 } NvmeFeatureCap; 1010 1011 typedef enum NvmeGetFeatureSelect { 1012 NVME_GETFEAT_SELECT_CURRENT = 0x0, 1013 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 1014 NVME_GETFEAT_SELECT_SAVED = 0x2, 1015 NVME_GETFEAT_SELECT_CAP = 0x3, 1016 } NvmeGetFeatureSelect; 1017 1018 #define NVME_GETSETFEAT_FID_MASK 0xff 1019 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 1020 1021 #define NVME_GETFEAT_SELECT_SHIFT 8 1022 #define NVME_GETFEAT_SELECT_MASK 0x7 1023 #define NVME_GETFEAT_SELECT(dw10) \ 1024 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 1025 1026 #define NVME_SETFEAT_SAVE_SHIFT 31 1027 #define NVME_SETFEAT_SAVE_MASK 0x1 1028 #define NVME_SETFEAT_SAVE(dw10) \ 1029 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 1030 1031 typedef struct QEMU_PACKED NvmeRangeType { 1032 uint8_t type; 1033 uint8_t attributes; 1034 uint8_t rsvd2[14]; 1035 uint64_t slba; 1036 uint64_t nlb; 1037 uint8_t guid[16]; 1038 uint8_t rsvd48[16]; 1039 } NvmeRangeType; 1040 1041 typedef struct QEMU_PACKED NvmeLBAF { 1042 uint16_t ms; 1043 uint8_t ds; 1044 uint8_t rp; 1045 } NvmeLBAF; 1046 1047 typedef struct QEMU_PACKED NvmeLBAFE { 1048 uint64_t zsze; 1049 uint8_t zdes; 1050 uint8_t rsvd9[7]; 1051 } NvmeLBAFE; 1052 1053 #define NVME_NSID_BROADCAST 0xffffffff 1054 1055 typedef struct QEMU_PACKED NvmeIdNs { 1056 uint64_t nsze; 1057 uint64_t ncap; 1058 uint64_t nuse; 1059 uint8_t nsfeat; 1060 uint8_t nlbaf; 1061 uint8_t flbas; 1062 uint8_t mc; 1063 uint8_t dpc; 1064 uint8_t dps; 1065 uint8_t nmic; 1066 uint8_t rescap; 1067 uint8_t fpi; 1068 uint8_t dlfeat; 1069 uint16_t nawun; 1070 uint16_t nawupf; 1071 uint16_t nacwu; 1072 uint16_t nabsn; 1073 uint16_t nabo; 1074 uint16_t nabspf; 1075 uint16_t noiob; 1076 uint8_t nvmcap[16]; 1077 uint16_t npwg; 1078 uint16_t npwa; 1079 uint16_t npdg; 1080 uint16_t npda; 1081 uint16_t nows; 1082 uint8_t rsvd74[30]; 1083 uint8_t nguid[16]; 1084 uint64_t eui64; 1085 NvmeLBAF lbaf[16]; 1086 uint8_t rsvd192[192]; 1087 uint8_t vs[3712]; 1088 } NvmeIdNs; 1089 1090 typedef struct QEMU_PACKED NvmeIdNsDescr { 1091 uint8_t nidt; 1092 uint8_t nidl; 1093 uint8_t rsvd2[2]; 1094 } NvmeIdNsDescr; 1095 1096 enum NvmeNsIdentifierLength { 1097 NVME_NIDL_EUI64 = 8, 1098 NVME_NIDL_NGUID = 16, 1099 NVME_NIDL_UUID = 16, 1100 NVME_NIDL_CSI = 1, 1101 }; 1102 1103 enum NvmeNsIdentifierType { 1104 NVME_NIDT_EUI64 = 0x01, 1105 NVME_NIDT_NGUID = 0x02, 1106 NVME_NIDT_UUID = 0x03, 1107 NVME_NIDT_CSI = 0x04, 1108 }; 1109 1110 enum NvmeCsi { 1111 NVME_CSI_NVM = 0x00, 1112 NVME_CSI_ZONED = 0x02, 1113 }; 1114 1115 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1116 1117 typedef struct QEMU_PACKED NvmeIdNsZoned { 1118 uint16_t zoc; 1119 uint16_t ozcs; 1120 uint32_t mar; 1121 uint32_t mor; 1122 uint32_t rrl; 1123 uint32_t frl; 1124 uint8_t rsvd20[2796]; 1125 NvmeLBAFE lbafe[16]; 1126 uint8_t rsvd3072[768]; 1127 uint8_t vs[256]; 1128 } NvmeIdNsZoned; 1129 1130 /*Deallocate Logical Block Features*/ 1131 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1132 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1133 1134 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1135 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1136 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1137 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1138 1139 1140 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1141 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1142 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1143 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1144 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1145 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1146 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1147 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1148 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1149 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1150 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1151 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1152 1153 enum NvmeIdNsDps { 1154 DPS_TYPE_NONE = 0, 1155 DPS_TYPE_1 = 1, 1156 DPS_TYPE_2 = 2, 1157 DPS_TYPE_3 = 3, 1158 DPS_TYPE_MASK = 0x7, 1159 DPS_FIRST_EIGHT = 8, 1160 }; 1161 1162 enum NvmeZoneAttr { 1163 NVME_ZA_FINISHED_BY_CTLR = 1 << 0, 1164 NVME_ZA_FINISH_RECOMMENDED = 1 << 1, 1165 NVME_ZA_RESET_RECOMMENDED = 1 << 2, 1166 NVME_ZA_ZD_EXT_VALID = 1 << 7, 1167 }; 1168 1169 typedef struct QEMU_PACKED NvmeZoneReportHeader { 1170 uint64_t nr_zones; 1171 uint8_t rsvd[56]; 1172 } NvmeZoneReportHeader; 1173 1174 enum NvmeZoneReceiveAction { 1175 NVME_ZONE_REPORT = 0, 1176 NVME_ZONE_REPORT_EXTENDED = 1, 1177 }; 1178 1179 enum NvmeZoneReportType { 1180 NVME_ZONE_REPORT_ALL = 0, 1181 NVME_ZONE_REPORT_EMPTY = 1, 1182 NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, 1183 NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, 1184 NVME_ZONE_REPORT_CLOSED = 4, 1185 NVME_ZONE_REPORT_FULL = 5, 1186 NVME_ZONE_REPORT_READ_ONLY = 6, 1187 NVME_ZONE_REPORT_OFFLINE = 7, 1188 }; 1189 1190 enum NvmeZoneType { 1191 NVME_ZONE_TYPE_RESERVED = 0x00, 1192 NVME_ZONE_TYPE_SEQ_WRITE = 0x02, 1193 }; 1194 1195 enum NvmeZoneSendAction { 1196 NVME_ZONE_ACTION_RSD = 0x00, 1197 NVME_ZONE_ACTION_CLOSE = 0x01, 1198 NVME_ZONE_ACTION_FINISH = 0x02, 1199 NVME_ZONE_ACTION_OPEN = 0x03, 1200 NVME_ZONE_ACTION_RESET = 0x04, 1201 NVME_ZONE_ACTION_OFFLINE = 0x05, 1202 NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, 1203 }; 1204 1205 typedef struct QEMU_PACKED NvmeZoneDescr { 1206 uint8_t zt; 1207 uint8_t zs; 1208 uint8_t za; 1209 uint8_t rsvd3[5]; 1210 uint64_t zcap; 1211 uint64_t zslba; 1212 uint64_t wp; 1213 uint8_t rsvd32[32]; 1214 } NvmeZoneDescr; 1215 1216 typedef enum NvmeZoneState { 1217 NVME_ZONE_STATE_RESERVED = 0x00, 1218 NVME_ZONE_STATE_EMPTY = 0x01, 1219 NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, 1220 NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, 1221 NVME_ZONE_STATE_CLOSED = 0x04, 1222 NVME_ZONE_STATE_READ_ONLY = 0x0D, 1223 NVME_ZONE_STATE_FULL = 0x0E, 1224 NVME_ZONE_STATE_OFFLINE = 0x0F, 1225 } NvmeZoneState; 1226 1227 static inline void _nvme_check_size(void) 1228 { 1229 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1230 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1231 QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); 1232 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1233 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1234 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1235 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1236 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1237 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1238 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1239 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1240 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1241 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1242 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1243 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1244 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1245 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1246 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1247 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); 1248 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); 1249 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); 1250 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1251 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); 1252 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1253 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1254 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); 1255 } 1256 #endif 1257