1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint32_t rsvd1; 11 uint32_t csts; 12 uint32_t nssrc; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint8_t padding[3520]; /* not used by QEMU */ 19 uint32_t pmrcap; 20 uint32_t pmrctl; 21 uint32_t pmrsts; 22 uint32_t pmrebs; 23 uint32_t pmrswtp; 24 uint64_t pmrmsc; 25 uint8_t reserved[484]; 26 } NvmeBar; 27 28 enum NvmeCapShift { 29 CAP_MQES_SHIFT = 0, 30 CAP_CQR_SHIFT = 16, 31 CAP_AMS_SHIFT = 17, 32 CAP_TO_SHIFT = 24, 33 CAP_DSTRD_SHIFT = 32, 34 CAP_NSSRS_SHIFT = 36, 35 CAP_CSS_SHIFT = 37, 36 CAP_MPSMIN_SHIFT = 48, 37 CAP_MPSMAX_SHIFT = 52, 38 CAP_PMR_SHIFT = 56, 39 }; 40 41 enum NvmeCapMask { 42 CAP_MQES_MASK = 0xffff, 43 CAP_CQR_MASK = 0x1, 44 CAP_AMS_MASK = 0x3, 45 CAP_TO_MASK = 0xff, 46 CAP_DSTRD_MASK = 0xf, 47 CAP_NSSRS_MASK = 0x1, 48 CAP_CSS_MASK = 0xff, 49 CAP_MPSMIN_MASK = 0xf, 50 CAP_MPSMAX_MASK = 0xf, 51 CAP_PMR_MASK = 0x1, 52 }; 53 54 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 55 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 56 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 57 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 58 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 59 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 60 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 61 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 62 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 63 #define NVME_CAP_PMR(cap) (((cap) >> CAP_PMR_SHIFT) & CAP_PMR_MASK) 64 65 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 66 << CAP_MQES_SHIFT) 67 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 68 << CAP_CQR_SHIFT) 69 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 70 << CAP_AMS_SHIFT) 71 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 72 << CAP_TO_SHIFT) 73 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 74 << CAP_DSTRD_SHIFT) 75 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 76 << CAP_NSSRS_SHIFT) 77 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 78 << CAP_CSS_SHIFT) 79 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 80 << CAP_MPSMIN_SHIFT) 81 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 82 << CAP_MPSMAX_SHIFT) 83 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ 84 << CAP_PMR_SHIFT) 85 86 enum NvmeCapCss { 87 NVME_CAP_CSS_NVM = 1 << 0, 88 NVME_CAP_CSS_CSI_SUPP = 1 << 6, 89 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 90 }; 91 92 enum NvmeCcShift { 93 CC_EN_SHIFT = 0, 94 CC_CSS_SHIFT = 4, 95 CC_MPS_SHIFT = 7, 96 CC_AMS_SHIFT = 11, 97 CC_SHN_SHIFT = 14, 98 CC_IOSQES_SHIFT = 16, 99 CC_IOCQES_SHIFT = 20, 100 }; 101 102 enum NvmeCcMask { 103 CC_EN_MASK = 0x1, 104 CC_CSS_MASK = 0x7, 105 CC_MPS_MASK = 0xf, 106 CC_AMS_MASK = 0x7, 107 CC_SHN_MASK = 0x3, 108 CC_IOSQES_MASK = 0xf, 109 CC_IOCQES_MASK = 0xf, 110 }; 111 112 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 113 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 114 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 115 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 116 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 117 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 118 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 119 120 enum NvmeCcCss { 121 NVME_CC_CSS_NVM = 0x0, 122 NVME_CC_CSS_CSI = 0x6, 123 NVME_CC_CSS_ADMIN_ONLY = 0x7, 124 }; 125 126 #define NVME_SET_CC_EN(cc, val) \ 127 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 128 #define NVME_SET_CC_CSS(cc, val) \ 129 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 130 #define NVME_SET_CC_MPS(cc, val) \ 131 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 132 #define NVME_SET_CC_AMS(cc, val) \ 133 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 134 #define NVME_SET_CC_SHN(cc, val) \ 135 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 136 #define NVME_SET_CC_IOSQES(cc, val) \ 137 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 138 #define NVME_SET_CC_IOCQES(cc, val) \ 139 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 140 141 enum NvmeCstsShift { 142 CSTS_RDY_SHIFT = 0, 143 CSTS_CFS_SHIFT = 1, 144 CSTS_SHST_SHIFT = 2, 145 CSTS_NSSRO_SHIFT = 4, 146 }; 147 148 enum NvmeCstsMask { 149 CSTS_RDY_MASK = 0x1, 150 CSTS_CFS_MASK = 0x1, 151 CSTS_SHST_MASK = 0x3, 152 CSTS_NSSRO_MASK = 0x1, 153 }; 154 155 enum NvmeCsts { 156 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 157 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 158 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 159 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 160 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 161 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 162 }; 163 164 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 165 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 166 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 167 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 168 169 enum NvmeAqaShift { 170 AQA_ASQS_SHIFT = 0, 171 AQA_ACQS_SHIFT = 16, 172 }; 173 174 enum NvmeAqaMask { 175 AQA_ASQS_MASK = 0xfff, 176 AQA_ACQS_MASK = 0xfff, 177 }; 178 179 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 180 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 181 182 enum NvmeCmblocShift { 183 CMBLOC_BIR_SHIFT = 0, 184 CMBLOC_OFST_SHIFT = 12, 185 }; 186 187 enum NvmeCmblocMask { 188 CMBLOC_BIR_MASK = 0x7, 189 CMBLOC_OFST_MASK = 0xfffff, 190 }; 191 192 #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ 193 CMBLOC_BIR_MASK) 194 #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ 195 CMBLOC_OFST_MASK) 196 197 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 198 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 199 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 200 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 201 202 enum NvmeCmbszShift { 203 CMBSZ_SQS_SHIFT = 0, 204 CMBSZ_CQS_SHIFT = 1, 205 CMBSZ_LISTS_SHIFT = 2, 206 CMBSZ_RDS_SHIFT = 3, 207 CMBSZ_WDS_SHIFT = 4, 208 CMBSZ_SZU_SHIFT = 8, 209 CMBSZ_SZ_SHIFT = 12, 210 }; 211 212 enum NvmeCmbszMask { 213 CMBSZ_SQS_MASK = 0x1, 214 CMBSZ_CQS_MASK = 0x1, 215 CMBSZ_LISTS_MASK = 0x1, 216 CMBSZ_RDS_MASK = 0x1, 217 CMBSZ_WDS_MASK = 0x1, 218 CMBSZ_SZU_MASK = 0xf, 219 CMBSZ_SZ_MASK = 0xfffff, 220 }; 221 222 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 223 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 224 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 225 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 226 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 227 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 228 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 229 230 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 231 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 232 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 233 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 234 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 235 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 236 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 237 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 238 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 239 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 240 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 241 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 242 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 243 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 244 245 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 246 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 247 248 enum NvmePmrcapShift { 249 PMRCAP_RDS_SHIFT = 3, 250 PMRCAP_WDS_SHIFT = 4, 251 PMRCAP_BIR_SHIFT = 5, 252 PMRCAP_PMRTU_SHIFT = 8, 253 PMRCAP_PMRWBM_SHIFT = 10, 254 PMRCAP_PMRTO_SHIFT = 16, 255 PMRCAP_CMSS_SHIFT = 24, 256 }; 257 258 enum NvmePmrcapMask { 259 PMRCAP_RDS_MASK = 0x1, 260 PMRCAP_WDS_MASK = 0x1, 261 PMRCAP_BIR_MASK = 0x7, 262 PMRCAP_PMRTU_MASK = 0x3, 263 PMRCAP_PMRWBM_MASK = 0xf, 264 PMRCAP_PMRTO_MASK = 0xff, 265 PMRCAP_CMSS_MASK = 0x1, 266 }; 267 268 #define NVME_PMRCAP_RDS(pmrcap) \ 269 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 270 #define NVME_PMRCAP_WDS(pmrcap) \ 271 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 272 #define NVME_PMRCAP_BIR(pmrcap) \ 273 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 274 #define NVME_PMRCAP_PMRTU(pmrcap) \ 275 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 276 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 277 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 278 #define NVME_PMRCAP_PMRTO(pmrcap) \ 279 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 280 #define NVME_PMRCAP_CMSS(pmrcap) \ 281 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 282 283 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 284 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 285 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 286 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 287 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 288 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 289 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 290 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 291 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 292 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 293 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 294 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 295 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 296 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 297 298 enum NvmePmrctlShift { 299 PMRCTL_EN_SHIFT = 0, 300 }; 301 302 enum NvmePmrctlMask { 303 PMRCTL_EN_MASK = 0x1, 304 }; 305 306 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 307 308 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 309 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 310 311 enum NvmePmrstsShift { 312 PMRSTS_ERR_SHIFT = 0, 313 PMRSTS_NRDY_SHIFT = 8, 314 PMRSTS_HSTS_SHIFT = 9, 315 PMRSTS_CBAI_SHIFT = 12, 316 }; 317 318 enum NvmePmrstsMask { 319 PMRSTS_ERR_MASK = 0xff, 320 PMRSTS_NRDY_MASK = 0x1, 321 PMRSTS_HSTS_MASK = 0x7, 322 PMRSTS_CBAI_MASK = 0x1, 323 }; 324 325 #define NVME_PMRSTS_ERR(pmrsts) \ 326 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 327 #define NVME_PMRSTS_NRDY(pmrsts) \ 328 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 329 #define NVME_PMRSTS_HSTS(pmrsts) \ 330 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 331 #define NVME_PMRSTS_CBAI(pmrsts) \ 332 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 333 334 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 335 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 336 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 337 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 338 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 339 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 340 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 341 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 342 343 enum NvmePmrebsShift { 344 PMREBS_PMRSZU_SHIFT = 0, 345 PMREBS_RBB_SHIFT = 4, 346 PMREBS_PMRWBZ_SHIFT = 8, 347 }; 348 349 enum NvmePmrebsMask { 350 PMREBS_PMRSZU_MASK = 0xf, 351 PMREBS_RBB_MASK = 0x1, 352 PMREBS_PMRWBZ_MASK = 0xffffff, 353 }; 354 355 #define NVME_PMREBS_PMRSZU(pmrebs) \ 356 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 357 #define NVME_PMREBS_RBB(pmrebs) \ 358 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 359 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 360 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 361 362 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 363 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 364 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 365 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 366 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 367 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 368 369 enum NvmePmrswtpShift { 370 PMRSWTP_PMRSWTU_SHIFT = 0, 371 PMRSWTP_PMRSWTV_SHIFT = 8, 372 }; 373 374 enum NvmePmrswtpMask { 375 PMRSWTP_PMRSWTU_MASK = 0xf, 376 PMRSWTP_PMRSWTV_MASK = 0xffffff, 377 }; 378 379 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 380 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 381 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 382 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 383 384 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 385 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 386 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 387 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 388 389 enum NvmePmrmscShift { 390 PMRMSC_CMSE_SHIFT = 1, 391 PMRMSC_CBA_SHIFT = 12, 392 }; 393 394 enum NvmePmrmscMask { 395 PMRMSC_CMSE_MASK = 0x1, 396 PMRMSC_CBA_MASK = 0xfffffffffffff, 397 }; 398 399 #define NVME_PMRMSC_CMSE(pmrmsc) \ 400 ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 401 #define NVME_PMRMSC_CBA(pmrmsc) \ 402 ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 403 404 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 405 (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 406 #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 407 (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 408 409 enum NvmeSglDescriptorType { 410 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 411 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 412 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 413 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 414 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 415 416 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 417 }; 418 419 enum NvmeSglDescriptorSubtype { 420 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 421 }; 422 423 typedef struct QEMU_PACKED NvmeSglDescriptor { 424 uint64_t addr; 425 uint32_t len; 426 uint8_t rsvd[3]; 427 uint8_t type; 428 } NvmeSglDescriptor; 429 430 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 431 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 432 433 typedef union NvmeCmdDptr { 434 struct { 435 uint64_t prp1; 436 uint64_t prp2; 437 }; 438 439 NvmeSglDescriptor sgl; 440 } NvmeCmdDptr; 441 442 enum NvmePsdt { 443 NVME_PSDT_PRP = 0x0, 444 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 445 NVME_PSDT_SGL_MPTR_SGL = 0x2, 446 }; 447 448 typedef struct QEMU_PACKED NvmeCmd { 449 uint8_t opcode; 450 uint8_t flags; 451 uint16_t cid; 452 uint32_t nsid; 453 uint64_t res1; 454 uint64_t mptr; 455 NvmeCmdDptr dptr; 456 uint32_t cdw10; 457 uint32_t cdw11; 458 uint32_t cdw12; 459 uint32_t cdw13; 460 uint32_t cdw14; 461 uint32_t cdw15; 462 } NvmeCmd; 463 464 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 465 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 466 467 enum NvmeAdminCommands { 468 NVME_ADM_CMD_DELETE_SQ = 0x00, 469 NVME_ADM_CMD_CREATE_SQ = 0x01, 470 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 471 NVME_ADM_CMD_DELETE_CQ = 0x04, 472 NVME_ADM_CMD_CREATE_CQ = 0x05, 473 NVME_ADM_CMD_IDENTIFY = 0x06, 474 NVME_ADM_CMD_ABORT = 0x08, 475 NVME_ADM_CMD_SET_FEATURES = 0x09, 476 NVME_ADM_CMD_GET_FEATURES = 0x0a, 477 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 478 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 479 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 480 NVME_ADM_CMD_FORMAT_NVM = 0x80, 481 NVME_ADM_CMD_SECURITY_SEND = 0x81, 482 NVME_ADM_CMD_SECURITY_RECV = 0x82, 483 }; 484 485 enum NvmeIoCommands { 486 NVME_CMD_FLUSH = 0x00, 487 NVME_CMD_WRITE = 0x01, 488 NVME_CMD_READ = 0x02, 489 NVME_CMD_WRITE_UNCOR = 0x04, 490 NVME_CMD_COMPARE = 0x05, 491 NVME_CMD_WRITE_ZEROES = 0x08, 492 NVME_CMD_DSM = 0x09, 493 NVME_CMD_ZONE_MGMT_SEND = 0x79, 494 NVME_CMD_ZONE_MGMT_RECV = 0x7a, 495 NVME_CMD_ZONE_APPEND = 0x7d, 496 }; 497 498 typedef struct QEMU_PACKED NvmeDeleteQ { 499 uint8_t opcode; 500 uint8_t flags; 501 uint16_t cid; 502 uint32_t rsvd1[9]; 503 uint16_t qid; 504 uint16_t rsvd10; 505 uint32_t rsvd11[5]; 506 } NvmeDeleteQ; 507 508 typedef struct QEMU_PACKED NvmeCreateCq { 509 uint8_t opcode; 510 uint8_t flags; 511 uint16_t cid; 512 uint32_t rsvd1[5]; 513 uint64_t prp1; 514 uint64_t rsvd8; 515 uint16_t cqid; 516 uint16_t qsize; 517 uint16_t cq_flags; 518 uint16_t irq_vector; 519 uint32_t rsvd12[4]; 520 } NvmeCreateCq; 521 522 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 523 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 524 525 enum NvmeFlagsCq { 526 NVME_CQ_PC = 1, 527 NVME_CQ_IEN = 2, 528 }; 529 530 typedef struct QEMU_PACKED NvmeCreateSq { 531 uint8_t opcode; 532 uint8_t flags; 533 uint16_t cid; 534 uint32_t rsvd1[5]; 535 uint64_t prp1; 536 uint64_t rsvd8; 537 uint16_t sqid; 538 uint16_t qsize; 539 uint16_t sq_flags; 540 uint16_t cqid; 541 uint32_t rsvd12[4]; 542 } NvmeCreateSq; 543 544 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 545 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 546 547 enum NvmeFlagsSq { 548 NVME_SQ_PC = 1, 549 550 NVME_SQ_PRIO_URGENT = 0, 551 NVME_SQ_PRIO_HIGH = 1, 552 NVME_SQ_PRIO_NORMAL = 2, 553 NVME_SQ_PRIO_LOW = 3, 554 }; 555 556 typedef struct QEMU_PACKED NvmeIdentify { 557 uint8_t opcode; 558 uint8_t flags; 559 uint16_t cid; 560 uint32_t nsid; 561 uint64_t rsvd2[2]; 562 uint64_t prp1; 563 uint64_t prp2; 564 uint8_t cns; 565 uint8_t rsvd10; 566 uint16_t ctrlid; 567 uint16_t nvmsetid; 568 uint8_t rsvd11; 569 uint8_t csi; 570 uint32_t rsvd12[4]; 571 } NvmeIdentify; 572 573 typedef struct QEMU_PACKED NvmeRwCmd { 574 uint8_t opcode; 575 uint8_t flags; 576 uint16_t cid; 577 uint32_t nsid; 578 uint64_t rsvd2; 579 uint64_t mptr; 580 NvmeCmdDptr dptr; 581 uint64_t slba; 582 uint16_t nlb; 583 uint16_t control; 584 uint32_t dsmgmt; 585 uint32_t reftag; 586 uint16_t apptag; 587 uint16_t appmask; 588 } NvmeRwCmd; 589 590 enum { 591 NVME_RW_LR = 1 << 15, 592 NVME_RW_FUA = 1 << 14, 593 NVME_RW_DSM_FREQ_UNSPEC = 0, 594 NVME_RW_DSM_FREQ_TYPICAL = 1, 595 NVME_RW_DSM_FREQ_RARE = 2, 596 NVME_RW_DSM_FREQ_READS = 3, 597 NVME_RW_DSM_FREQ_WRITES = 4, 598 NVME_RW_DSM_FREQ_RW = 5, 599 NVME_RW_DSM_FREQ_ONCE = 6, 600 NVME_RW_DSM_FREQ_PREFETCH = 7, 601 NVME_RW_DSM_FREQ_TEMP = 8, 602 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 603 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 604 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 605 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 606 NVME_RW_DSM_SEQ_REQ = 1 << 6, 607 NVME_RW_DSM_COMPRESSED = 1 << 7, 608 NVME_RW_PRINFO_PRACT = 1 << 13, 609 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 610 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 611 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 612 }; 613 614 typedef struct QEMU_PACKED NvmeDsmCmd { 615 uint8_t opcode; 616 uint8_t flags; 617 uint16_t cid; 618 uint32_t nsid; 619 uint64_t rsvd2[2]; 620 NvmeCmdDptr dptr; 621 uint32_t nr; 622 uint32_t attributes; 623 uint32_t rsvd12[4]; 624 } NvmeDsmCmd; 625 626 enum { 627 NVME_DSMGMT_IDR = 1 << 0, 628 NVME_DSMGMT_IDW = 1 << 1, 629 NVME_DSMGMT_AD = 1 << 2, 630 }; 631 632 typedef struct QEMU_PACKED NvmeDsmRange { 633 uint32_t cattr; 634 uint32_t nlb; 635 uint64_t slba; 636 } NvmeDsmRange; 637 638 enum NvmeAsyncEventRequest { 639 NVME_AER_TYPE_ERROR = 0, 640 NVME_AER_TYPE_SMART = 1, 641 NVME_AER_TYPE_IO_SPECIFIC = 6, 642 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 643 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 644 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 645 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 646 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 647 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 648 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 649 NVME_AER_INFO_SMART_RELIABILITY = 0, 650 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 651 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 652 }; 653 654 typedef struct QEMU_PACKED NvmeAerResult { 655 uint8_t event_type; 656 uint8_t event_info; 657 uint8_t log_page; 658 uint8_t resv; 659 } NvmeAerResult; 660 661 typedef struct QEMU_PACKED NvmeZonedResult { 662 uint64_t slba; 663 } NvmeZonedResult; 664 665 typedef struct QEMU_PACKED NvmeCqe { 666 uint32_t result; 667 uint32_t dw1; 668 uint16_t sq_head; 669 uint16_t sq_id; 670 uint16_t cid; 671 uint16_t status; 672 } NvmeCqe; 673 674 enum NvmeStatusCodes { 675 NVME_SUCCESS = 0x0000, 676 NVME_INVALID_OPCODE = 0x0001, 677 NVME_INVALID_FIELD = 0x0002, 678 NVME_CID_CONFLICT = 0x0003, 679 NVME_DATA_TRAS_ERROR = 0x0004, 680 NVME_POWER_LOSS_ABORT = 0x0005, 681 NVME_INTERNAL_DEV_ERROR = 0x0006, 682 NVME_CMD_ABORT_REQ = 0x0007, 683 NVME_CMD_ABORT_SQ_DEL = 0x0008, 684 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 685 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 686 NVME_INVALID_NSID = 0x000b, 687 NVME_CMD_SEQ_ERROR = 0x000c, 688 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 689 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 690 NVME_DATA_SGL_LEN_INVALID = 0x000f, 691 NVME_MD_SGL_LEN_INVALID = 0x0010, 692 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 693 NVME_INVALID_USE_OF_CMB = 0x0012, 694 NVME_INVALID_PRP_OFFSET = 0x0013, 695 NVME_CMD_SET_CMB_REJECTED = 0x002b, 696 NVME_INVALID_CMD_SET = 0x002c, 697 NVME_LBA_RANGE = 0x0080, 698 NVME_CAP_EXCEEDED = 0x0081, 699 NVME_NS_NOT_READY = 0x0082, 700 NVME_NS_RESV_CONFLICT = 0x0083, 701 NVME_INVALID_CQID = 0x0100, 702 NVME_INVALID_QID = 0x0101, 703 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 704 NVME_ACL_EXCEEDED = 0x0103, 705 NVME_RESERVED = 0x0104, 706 NVME_AER_LIMIT_EXCEEDED = 0x0105, 707 NVME_INVALID_FW_SLOT = 0x0106, 708 NVME_INVALID_FW_IMAGE = 0x0107, 709 NVME_INVALID_IRQ_VECTOR = 0x0108, 710 NVME_INVALID_LOG_ID = 0x0109, 711 NVME_INVALID_FORMAT = 0x010a, 712 NVME_FW_REQ_RESET = 0x010b, 713 NVME_INVALID_QUEUE_DEL = 0x010c, 714 NVME_FID_NOT_SAVEABLE = 0x010d, 715 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 716 NVME_FEAT_NOT_NS_SPEC = 0x010f, 717 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 718 NVME_CONFLICTING_ATTRS = 0x0180, 719 NVME_INVALID_PROT_INFO = 0x0181, 720 NVME_WRITE_TO_RO = 0x0182, 721 NVME_ZONE_BOUNDARY_ERROR = 0x01b8, 722 NVME_ZONE_FULL = 0x01b9, 723 NVME_ZONE_READ_ONLY = 0x01ba, 724 NVME_ZONE_OFFLINE = 0x01bb, 725 NVME_ZONE_INVALID_WRITE = 0x01bc, 726 NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, 727 NVME_ZONE_TOO_MANY_OPEN = 0x01be, 728 NVME_ZONE_INVAL_TRANSITION = 0x01bf, 729 NVME_WRITE_FAULT = 0x0280, 730 NVME_UNRECOVERED_READ = 0x0281, 731 NVME_E2E_GUARD_ERROR = 0x0282, 732 NVME_E2E_APP_ERROR = 0x0283, 733 NVME_E2E_REF_ERROR = 0x0284, 734 NVME_CMP_FAILURE = 0x0285, 735 NVME_ACCESS_DENIED = 0x0286, 736 NVME_DULB = 0x0287, 737 NVME_MORE = 0x2000, 738 NVME_DNR = 0x4000, 739 NVME_NO_COMPLETE = 0xffff, 740 }; 741 742 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 743 uint8_t afi; 744 uint8_t reserved1[7]; 745 uint8_t frs1[8]; 746 uint8_t frs2[8]; 747 uint8_t frs3[8]; 748 uint8_t frs4[8]; 749 uint8_t frs5[8]; 750 uint8_t frs6[8]; 751 uint8_t frs7[8]; 752 uint8_t reserved2[448]; 753 } NvmeFwSlotInfoLog; 754 755 typedef struct QEMU_PACKED NvmeErrorLog { 756 uint64_t error_count; 757 uint16_t sqid; 758 uint16_t cid; 759 uint16_t status_field; 760 uint16_t param_error_location; 761 uint64_t lba; 762 uint32_t nsid; 763 uint8_t vs; 764 uint8_t resv[35]; 765 } NvmeErrorLog; 766 767 typedef struct QEMU_PACKED NvmeSmartLog { 768 uint8_t critical_warning; 769 uint16_t temperature; 770 uint8_t available_spare; 771 uint8_t available_spare_threshold; 772 uint8_t percentage_used; 773 uint8_t reserved1[26]; 774 uint64_t data_units_read[2]; 775 uint64_t data_units_written[2]; 776 uint64_t host_read_commands[2]; 777 uint64_t host_write_commands[2]; 778 uint64_t controller_busy_time[2]; 779 uint64_t power_cycles[2]; 780 uint64_t power_on_hours[2]; 781 uint64_t unsafe_shutdowns[2]; 782 uint64_t media_errors[2]; 783 uint64_t number_of_error_log_entries[2]; 784 uint8_t reserved2[320]; 785 } NvmeSmartLog; 786 787 #define NVME_SMART_WARN_MAX 6 788 enum NvmeSmartWarn { 789 NVME_SMART_SPARE = 1 << 0, 790 NVME_SMART_TEMPERATURE = 1 << 1, 791 NVME_SMART_RELIABILITY = 1 << 2, 792 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 793 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 794 NVME_SMART_PMR_UNRELIABLE = 1 << 5, 795 }; 796 797 typedef struct NvmeEffectsLog { 798 uint32_t acs[256]; 799 uint32_t iocs[256]; 800 uint8_t resv[2048]; 801 } NvmeEffectsLog; 802 803 enum { 804 NVME_CMD_EFF_CSUPP = 1 << 0, 805 NVME_CMD_EFF_LBCC = 1 << 1, 806 NVME_CMD_EFF_NCC = 1 << 2, 807 NVME_CMD_EFF_NIC = 1 << 3, 808 NVME_CMD_EFF_CCC = 1 << 4, 809 NVME_CMD_EFF_CSE_MASK = 3 << 16, 810 NVME_CMD_EFF_UUID_SEL = 1 << 19, 811 }; 812 813 enum NvmeLogIdentifier { 814 NVME_LOG_ERROR_INFO = 0x01, 815 NVME_LOG_SMART_INFO = 0x02, 816 NVME_LOG_FW_SLOT_INFO = 0x03, 817 NVME_LOG_CMD_EFFECTS = 0x05, 818 }; 819 820 typedef struct QEMU_PACKED NvmePSD { 821 uint16_t mp; 822 uint16_t reserved; 823 uint32_t enlat; 824 uint32_t exlat; 825 uint8_t rrt; 826 uint8_t rrl; 827 uint8_t rwt; 828 uint8_t rwl; 829 uint8_t resv[16]; 830 } NvmePSD; 831 832 #define NVME_IDENTIFY_DATA_SIZE 4096 833 834 enum NvmeIdCns { 835 NVME_ID_CNS_NS = 0x00, 836 NVME_ID_CNS_CTRL = 0x01, 837 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 838 NVME_ID_CNS_NS_DESCR_LIST = 0x03, 839 NVME_ID_CNS_CS_NS = 0x05, 840 NVME_ID_CNS_CS_CTRL = 0x06, 841 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 842 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 843 NVME_ID_CNS_NS_PRESENT = 0x11, 844 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 845 NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 846 NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 847 }; 848 849 typedef struct QEMU_PACKED NvmeIdCtrl { 850 uint16_t vid; 851 uint16_t ssvid; 852 uint8_t sn[20]; 853 uint8_t mn[40]; 854 uint8_t fr[8]; 855 uint8_t rab; 856 uint8_t ieee[3]; 857 uint8_t cmic; 858 uint8_t mdts; 859 uint16_t cntlid; 860 uint32_t ver; 861 uint32_t rtd3r; 862 uint32_t rtd3e; 863 uint32_t oaes; 864 uint32_t ctratt; 865 uint8_t rsvd100[12]; 866 uint8_t fguid[16]; 867 uint8_t rsvd128[128]; 868 uint16_t oacs; 869 uint8_t acl; 870 uint8_t aerl; 871 uint8_t frmw; 872 uint8_t lpa; 873 uint8_t elpe; 874 uint8_t npss; 875 uint8_t avscc; 876 uint8_t apsta; 877 uint16_t wctemp; 878 uint16_t cctemp; 879 uint16_t mtfa; 880 uint32_t hmpre; 881 uint32_t hmmin; 882 uint8_t tnvmcap[16]; 883 uint8_t unvmcap[16]; 884 uint32_t rpmbs; 885 uint16_t edstt; 886 uint8_t dsto; 887 uint8_t fwug; 888 uint16_t kas; 889 uint16_t hctma; 890 uint16_t mntmt; 891 uint16_t mxtmt; 892 uint32_t sanicap; 893 uint8_t rsvd332[180]; 894 uint8_t sqes; 895 uint8_t cqes; 896 uint16_t maxcmd; 897 uint32_t nn; 898 uint16_t oncs; 899 uint16_t fuses; 900 uint8_t fna; 901 uint8_t vwc; 902 uint16_t awun; 903 uint16_t awupf; 904 uint8_t nvscc; 905 uint8_t rsvd531; 906 uint16_t acwu; 907 uint8_t rsvd534[2]; 908 uint32_t sgls; 909 uint8_t rsvd540[228]; 910 uint8_t subnqn[256]; 911 uint8_t rsvd1024[1024]; 912 NvmePSD psd[32]; 913 uint8_t vs[1024]; 914 } NvmeIdCtrl; 915 916 typedef struct NvmeIdCtrlZoned { 917 uint8_t zasl; 918 uint8_t rsvd1[4095]; 919 } NvmeIdCtrlZoned; 920 921 enum NvmeIdCtrlOacs { 922 NVME_OACS_SECURITY = 1 << 0, 923 NVME_OACS_FORMAT = 1 << 1, 924 NVME_OACS_FW = 1 << 2, 925 }; 926 927 enum NvmeIdCtrlOncs { 928 NVME_ONCS_COMPARE = 1 << 0, 929 NVME_ONCS_WRITE_UNCORR = 1 << 1, 930 NVME_ONCS_DSM = 1 << 2, 931 NVME_ONCS_WRITE_ZEROES = 1 << 3, 932 NVME_ONCS_FEATURES = 1 << 4, 933 NVME_ONCS_RESRVATIONS = 1 << 5, 934 NVME_ONCS_TIMESTAMP = 1 << 6, 935 }; 936 937 enum NvmeIdCtrlFrmw { 938 NVME_FRMW_SLOT1_RO = 1 << 0, 939 }; 940 941 enum NvmeIdCtrlLpa { 942 NVME_LPA_NS_SMART = 1 << 0, 943 NVME_LPA_CSE = 1 << 1, 944 NVME_LPA_EXTENDED = 1 << 2, 945 }; 946 947 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 948 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 949 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 950 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 951 952 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 953 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 954 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 955 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 956 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 957 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 958 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 959 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 960 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 961 962 #define NVME_ARB_AB(arb) (arb & 0x7) 963 #define NVME_ARB_AB_NOLIMIT 0x7 964 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 965 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 966 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 967 968 #define NVME_INTC_THR(intc) (intc & 0xff) 969 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 970 971 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 972 973 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 974 #define NVME_TEMP_THSEL_OVER 0x0 975 #define NVME_TEMP_THSEL_UNDER 0x1 976 977 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 978 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 979 980 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 981 982 #define NVME_AEC_SMART(aec) (aec & 0xff) 983 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 984 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 985 986 #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 987 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 988 989 enum NvmeFeatureIds { 990 NVME_ARBITRATION = 0x1, 991 NVME_POWER_MANAGEMENT = 0x2, 992 NVME_LBA_RANGE_TYPE = 0x3, 993 NVME_TEMPERATURE_THRESHOLD = 0x4, 994 NVME_ERROR_RECOVERY = 0x5, 995 NVME_VOLATILE_WRITE_CACHE = 0x6, 996 NVME_NUMBER_OF_QUEUES = 0x7, 997 NVME_INTERRUPT_COALESCING = 0x8, 998 NVME_INTERRUPT_VECTOR_CONF = 0x9, 999 NVME_WRITE_ATOMICITY = 0xa, 1000 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 1001 NVME_TIMESTAMP = 0xe, 1002 NVME_COMMAND_SET_PROFILE = 0x19, 1003 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 1004 NVME_FID_MAX = 0x100, 1005 }; 1006 1007 typedef enum NvmeFeatureCap { 1008 NVME_FEAT_CAP_SAVE = 1 << 0, 1009 NVME_FEAT_CAP_NS = 1 << 1, 1010 NVME_FEAT_CAP_CHANGE = 1 << 2, 1011 } NvmeFeatureCap; 1012 1013 typedef enum NvmeGetFeatureSelect { 1014 NVME_GETFEAT_SELECT_CURRENT = 0x0, 1015 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 1016 NVME_GETFEAT_SELECT_SAVED = 0x2, 1017 NVME_GETFEAT_SELECT_CAP = 0x3, 1018 } NvmeGetFeatureSelect; 1019 1020 #define NVME_GETSETFEAT_FID_MASK 0xff 1021 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 1022 1023 #define NVME_GETFEAT_SELECT_SHIFT 8 1024 #define NVME_GETFEAT_SELECT_MASK 0x7 1025 #define NVME_GETFEAT_SELECT(dw10) \ 1026 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 1027 1028 #define NVME_SETFEAT_SAVE_SHIFT 31 1029 #define NVME_SETFEAT_SAVE_MASK 0x1 1030 #define NVME_SETFEAT_SAVE(dw10) \ 1031 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 1032 1033 typedef struct QEMU_PACKED NvmeRangeType { 1034 uint8_t type; 1035 uint8_t attributes; 1036 uint8_t rsvd2[14]; 1037 uint64_t slba; 1038 uint64_t nlb; 1039 uint8_t guid[16]; 1040 uint8_t rsvd48[16]; 1041 } NvmeRangeType; 1042 1043 typedef struct QEMU_PACKED NvmeLBAF { 1044 uint16_t ms; 1045 uint8_t ds; 1046 uint8_t rp; 1047 } NvmeLBAF; 1048 1049 typedef struct QEMU_PACKED NvmeLBAFE { 1050 uint64_t zsze; 1051 uint8_t zdes; 1052 uint8_t rsvd9[7]; 1053 } NvmeLBAFE; 1054 1055 #define NVME_NSID_BROADCAST 0xffffffff 1056 1057 typedef struct QEMU_PACKED NvmeIdNs { 1058 uint64_t nsze; 1059 uint64_t ncap; 1060 uint64_t nuse; 1061 uint8_t nsfeat; 1062 uint8_t nlbaf; 1063 uint8_t flbas; 1064 uint8_t mc; 1065 uint8_t dpc; 1066 uint8_t dps; 1067 uint8_t nmic; 1068 uint8_t rescap; 1069 uint8_t fpi; 1070 uint8_t dlfeat; 1071 uint16_t nawun; 1072 uint16_t nawupf; 1073 uint16_t nacwu; 1074 uint16_t nabsn; 1075 uint16_t nabo; 1076 uint16_t nabspf; 1077 uint16_t noiob; 1078 uint8_t nvmcap[16]; 1079 uint16_t npwg; 1080 uint16_t npwa; 1081 uint16_t npdg; 1082 uint16_t npda; 1083 uint16_t nows; 1084 uint8_t rsvd74[30]; 1085 uint8_t nguid[16]; 1086 uint64_t eui64; 1087 NvmeLBAF lbaf[16]; 1088 uint8_t rsvd192[192]; 1089 uint8_t vs[3712]; 1090 } NvmeIdNs; 1091 1092 typedef struct QEMU_PACKED NvmeIdNsDescr { 1093 uint8_t nidt; 1094 uint8_t nidl; 1095 uint8_t rsvd2[2]; 1096 } NvmeIdNsDescr; 1097 1098 enum NvmeNsIdentifierLength { 1099 NVME_NIDL_EUI64 = 8, 1100 NVME_NIDL_NGUID = 16, 1101 NVME_NIDL_UUID = 16, 1102 NVME_NIDL_CSI = 1, 1103 }; 1104 1105 enum NvmeNsIdentifierType { 1106 NVME_NIDT_EUI64 = 0x01, 1107 NVME_NIDT_NGUID = 0x02, 1108 NVME_NIDT_UUID = 0x03, 1109 NVME_NIDT_CSI = 0x04, 1110 }; 1111 1112 enum NvmeCsi { 1113 NVME_CSI_NVM = 0x00, 1114 NVME_CSI_ZONED = 0x02, 1115 }; 1116 1117 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1118 1119 typedef struct QEMU_PACKED NvmeIdNsZoned { 1120 uint16_t zoc; 1121 uint16_t ozcs; 1122 uint32_t mar; 1123 uint32_t mor; 1124 uint32_t rrl; 1125 uint32_t frl; 1126 uint8_t rsvd20[2796]; 1127 NvmeLBAFE lbafe[16]; 1128 uint8_t rsvd3072[768]; 1129 uint8_t vs[256]; 1130 } NvmeIdNsZoned; 1131 1132 /*Deallocate Logical Block Features*/ 1133 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1134 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1135 1136 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1137 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1138 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1139 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1140 1141 1142 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1143 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1144 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1145 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1146 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1147 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1148 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1149 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1150 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1151 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1152 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1153 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1154 1155 enum NvmeIdNsDps { 1156 DPS_TYPE_NONE = 0, 1157 DPS_TYPE_1 = 1, 1158 DPS_TYPE_2 = 2, 1159 DPS_TYPE_3 = 3, 1160 DPS_TYPE_MASK = 0x7, 1161 DPS_FIRST_EIGHT = 8, 1162 }; 1163 1164 enum NvmeZoneAttr { 1165 NVME_ZA_FINISHED_BY_CTLR = 1 << 0, 1166 NVME_ZA_FINISH_RECOMMENDED = 1 << 1, 1167 NVME_ZA_RESET_RECOMMENDED = 1 << 2, 1168 NVME_ZA_ZD_EXT_VALID = 1 << 7, 1169 }; 1170 1171 typedef struct QEMU_PACKED NvmeZoneReportHeader { 1172 uint64_t nr_zones; 1173 uint8_t rsvd[56]; 1174 } NvmeZoneReportHeader; 1175 1176 enum NvmeZoneReceiveAction { 1177 NVME_ZONE_REPORT = 0, 1178 NVME_ZONE_REPORT_EXTENDED = 1, 1179 }; 1180 1181 enum NvmeZoneReportType { 1182 NVME_ZONE_REPORT_ALL = 0, 1183 NVME_ZONE_REPORT_EMPTY = 1, 1184 NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, 1185 NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, 1186 NVME_ZONE_REPORT_CLOSED = 4, 1187 NVME_ZONE_REPORT_FULL = 5, 1188 NVME_ZONE_REPORT_READ_ONLY = 6, 1189 NVME_ZONE_REPORT_OFFLINE = 7, 1190 }; 1191 1192 enum NvmeZoneType { 1193 NVME_ZONE_TYPE_RESERVED = 0x00, 1194 NVME_ZONE_TYPE_SEQ_WRITE = 0x02, 1195 }; 1196 1197 enum NvmeZoneSendAction { 1198 NVME_ZONE_ACTION_RSD = 0x00, 1199 NVME_ZONE_ACTION_CLOSE = 0x01, 1200 NVME_ZONE_ACTION_FINISH = 0x02, 1201 NVME_ZONE_ACTION_OPEN = 0x03, 1202 NVME_ZONE_ACTION_RESET = 0x04, 1203 NVME_ZONE_ACTION_OFFLINE = 0x05, 1204 NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, 1205 }; 1206 1207 typedef struct QEMU_PACKED NvmeZoneDescr { 1208 uint8_t zt; 1209 uint8_t zs; 1210 uint8_t za; 1211 uint8_t rsvd3[5]; 1212 uint64_t zcap; 1213 uint64_t zslba; 1214 uint64_t wp; 1215 uint8_t rsvd32[32]; 1216 } NvmeZoneDescr; 1217 1218 typedef enum NvmeZoneState { 1219 NVME_ZONE_STATE_RESERVED = 0x00, 1220 NVME_ZONE_STATE_EMPTY = 0x01, 1221 NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, 1222 NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, 1223 NVME_ZONE_STATE_CLOSED = 0x04, 1224 NVME_ZONE_STATE_READ_ONLY = 0x0D, 1225 NVME_ZONE_STATE_FULL = 0x0E, 1226 NVME_ZONE_STATE_OFFLINE = 0x0F, 1227 } NvmeZoneState; 1228 1229 static inline void _nvme_check_size(void) 1230 { 1231 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1232 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1233 QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); 1234 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1235 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1236 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1237 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1238 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1239 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1240 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1241 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1242 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1243 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1244 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1245 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1246 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1247 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1248 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1249 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); 1250 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); 1251 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); 1252 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1253 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); 1254 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1255 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1256 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); 1257 } 1258 #endif 1259