1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint32_t rsvd1; 11 uint32_t csts; 12 uint32_t nssrc; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint8_t padding[3520]; /* not used by QEMU */ 19 uint32_t pmrcap; 20 uint32_t pmrctl; 21 uint32_t pmrsts; 22 uint32_t pmrebs; 23 uint32_t pmrswtp; 24 uint64_t pmrmsc; 25 uint8_t reserved[484]; 26 } NvmeBar; 27 28 enum NvmeCapShift { 29 CAP_MQES_SHIFT = 0, 30 CAP_CQR_SHIFT = 16, 31 CAP_AMS_SHIFT = 17, 32 CAP_TO_SHIFT = 24, 33 CAP_DSTRD_SHIFT = 32, 34 CAP_NSSRS_SHIFT = 36, 35 CAP_CSS_SHIFT = 37, 36 CAP_MPSMIN_SHIFT = 48, 37 CAP_MPSMAX_SHIFT = 52, 38 CAP_PMR_SHIFT = 56, 39 }; 40 41 enum NvmeCapMask { 42 CAP_MQES_MASK = 0xffff, 43 CAP_CQR_MASK = 0x1, 44 CAP_AMS_MASK = 0x3, 45 CAP_TO_MASK = 0xff, 46 CAP_DSTRD_MASK = 0xf, 47 CAP_NSSRS_MASK = 0x1, 48 CAP_CSS_MASK = 0xff, 49 CAP_MPSMIN_MASK = 0xf, 50 CAP_MPSMAX_MASK = 0xf, 51 CAP_PMR_MASK = 0x1, 52 }; 53 54 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 55 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 56 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 57 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 58 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 59 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 60 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 61 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 62 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 63 64 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 65 << CAP_MQES_SHIFT) 66 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 67 << CAP_CQR_SHIFT) 68 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 69 << CAP_AMS_SHIFT) 70 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 71 << CAP_TO_SHIFT) 72 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 73 << CAP_DSTRD_SHIFT) 74 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 75 << CAP_NSSRS_SHIFT) 76 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 77 << CAP_CSS_SHIFT) 78 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 79 << CAP_MPSMIN_SHIFT) 80 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 81 << CAP_MPSMAX_SHIFT) 82 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ 83 << CAP_PMR_SHIFT) 84 85 enum NvmeCapCss { 86 NVME_CAP_CSS_NVM = 1 << 0, 87 NVME_CAP_CSS_CSI_SUPP = 1 << 6, 88 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 89 }; 90 91 enum NvmeCcShift { 92 CC_EN_SHIFT = 0, 93 CC_CSS_SHIFT = 4, 94 CC_MPS_SHIFT = 7, 95 CC_AMS_SHIFT = 11, 96 CC_SHN_SHIFT = 14, 97 CC_IOSQES_SHIFT = 16, 98 CC_IOCQES_SHIFT = 20, 99 }; 100 101 enum NvmeCcMask { 102 CC_EN_MASK = 0x1, 103 CC_CSS_MASK = 0x7, 104 CC_MPS_MASK = 0xf, 105 CC_AMS_MASK = 0x7, 106 CC_SHN_MASK = 0x3, 107 CC_IOSQES_MASK = 0xf, 108 CC_IOCQES_MASK = 0xf, 109 }; 110 111 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 112 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 113 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 114 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 115 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 116 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 117 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 118 119 enum NvmeCcCss { 120 NVME_CC_CSS_NVM = 0x0, 121 NVME_CC_CSS_CSI = 0x6, 122 NVME_CC_CSS_ADMIN_ONLY = 0x7, 123 }; 124 125 #define NVME_SET_CC_EN(cc, val) \ 126 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 127 #define NVME_SET_CC_CSS(cc, val) \ 128 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 129 #define NVME_SET_CC_MPS(cc, val) \ 130 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 131 #define NVME_SET_CC_AMS(cc, val) \ 132 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 133 #define NVME_SET_CC_SHN(cc, val) \ 134 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 135 #define NVME_SET_CC_IOSQES(cc, val) \ 136 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 137 #define NVME_SET_CC_IOCQES(cc, val) \ 138 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 139 140 enum NvmeCstsShift { 141 CSTS_RDY_SHIFT = 0, 142 CSTS_CFS_SHIFT = 1, 143 CSTS_SHST_SHIFT = 2, 144 CSTS_NSSRO_SHIFT = 4, 145 }; 146 147 enum NvmeCstsMask { 148 CSTS_RDY_MASK = 0x1, 149 CSTS_CFS_MASK = 0x1, 150 CSTS_SHST_MASK = 0x3, 151 CSTS_NSSRO_MASK = 0x1, 152 }; 153 154 enum NvmeCsts { 155 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 156 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 157 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 158 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 159 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 160 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 161 }; 162 163 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 164 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 165 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 166 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 167 168 enum NvmeAqaShift { 169 AQA_ASQS_SHIFT = 0, 170 AQA_ACQS_SHIFT = 16, 171 }; 172 173 enum NvmeAqaMask { 174 AQA_ASQS_MASK = 0xfff, 175 AQA_ACQS_MASK = 0xfff, 176 }; 177 178 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 179 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 180 181 enum NvmeCmblocShift { 182 CMBLOC_BIR_SHIFT = 0, 183 CMBLOC_OFST_SHIFT = 12, 184 }; 185 186 enum NvmeCmblocMask { 187 CMBLOC_BIR_MASK = 0x7, 188 CMBLOC_OFST_MASK = 0xfffff, 189 }; 190 191 #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ 192 CMBLOC_BIR_MASK) 193 #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ 194 CMBLOC_OFST_MASK) 195 196 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 197 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 198 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 199 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 200 201 enum NvmeCmbszShift { 202 CMBSZ_SQS_SHIFT = 0, 203 CMBSZ_CQS_SHIFT = 1, 204 CMBSZ_LISTS_SHIFT = 2, 205 CMBSZ_RDS_SHIFT = 3, 206 CMBSZ_WDS_SHIFT = 4, 207 CMBSZ_SZU_SHIFT = 8, 208 CMBSZ_SZ_SHIFT = 12, 209 }; 210 211 enum NvmeCmbszMask { 212 CMBSZ_SQS_MASK = 0x1, 213 CMBSZ_CQS_MASK = 0x1, 214 CMBSZ_LISTS_MASK = 0x1, 215 CMBSZ_RDS_MASK = 0x1, 216 CMBSZ_WDS_MASK = 0x1, 217 CMBSZ_SZU_MASK = 0xf, 218 CMBSZ_SZ_MASK = 0xfffff, 219 }; 220 221 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 222 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 223 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 224 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 225 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 226 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 227 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 228 229 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 230 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 231 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 232 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 233 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 234 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 235 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 236 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 237 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 238 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 239 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 240 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 241 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 242 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 243 244 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 245 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 246 247 enum NvmePmrcapShift { 248 PMRCAP_RDS_SHIFT = 3, 249 PMRCAP_WDS_SHIFT = 4, 250 PMRCAP_BIR_SHIFT = 5, 251 PMRCAP_PMRTU_SHIFT = 8, 252 PMRCAP_PMRWBM_SHIFT = 10, 253 PMRCAP_PMRTO_SHIFT = 16, 254 PMRCAP_CMSS_SHIFT = 24, 255 }; 256 257 enum NvmePmrcapMask { 258 PMRCAP_RDS_MASK = 0x1, 259 PMRCAP_WDS_MASK = 0x1, 260 PMRCAP_BIR_MASK = 0x7, 261 PMRCAP_PMRTU_MASK = 0x3, 262 PMRCAP_PMRWBM_MASK = 0xf, 263 PMRCAP_PMRTO_MASK = 0xff, 264 PMRCAP_CMSS_MASK = 0x1, 265 }; 266 267 #define NVME_PMRCAP_RDS(pmrcap) \ 268 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 269 #define NVME_PMRCAP_WDS(pmrcap) \ 270 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 271 #define NVME_PMRCAP_BIR(pmrcap) \ 272 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 273 #define NVME_PMRCAP_PMRTU(pmrcap) \ 274 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 275 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 276 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 277 #define NVME_PMRCAP_PMRTO(pmrcap) \ 278 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 279 #define NVME_PMRCAP_CMSS(pmrcap) \ 280 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 281 282 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 283 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 284 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 285 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 286 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 287 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 288 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 289 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 290 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 291 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 292 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 293 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 294 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 295 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 296 297 enum NvmePmrctlShift { 298 PMRCTL_EN_SHIFT = 0, 299 }; 300 301 enum NvmePmrctlMask { 302 PMRCTL_EN_MASK = 0x1, 303 }; 304 305 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 306 307 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 308 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 309 310 enum NvmePmrstsShift { 311 PMRSTS_ERR_SHIFT = 0, 312 PMRSTS_NRDY_SHIFT = 8, 313 PMRSTS_HSTS_SHIFT = 9, 314 PMRSTS_CBAI_SHIFT = 12, 315 }; 316 317 enum NvmePmrstsMask { 318 PMRSTS_ERR_MASK = 0xff, 319 PMRSTS_NRDY_MASK = 0x1, 320 PMRSTS_HSTS_MASK = 0x7, 321 PMRSTS_CBAI_MASK = 0x1, 322 }; 323 324 #define NVME_PMRSTS_ERR(pmrsts) \ 325 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 326 #define NVME_PMRSTS_NRDY(pmrsts) \ 327 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 328 #define NVME_PMRSTS_HSTS(pmrsts) \ 329 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 330 #define NVME_PMRSTS_CBAI(pmrsts) \ 331 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 332 333 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 334 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 335 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 336 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 337 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 338 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 339 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 340 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 341 342 enum NvmePmrebsShift { 343 PMREBS_PMRSZU_SHIFT = 0, 344 PMREBS_RBB_SHIFT = 4, 345 PMREBS_PMRWBZ_SHIFT = 8, 346 }; 347 348 enum NvmePmrebsMask { 349 PMREBS_PMRSZU_MASK = 0xf, 350 PMREBS_RBB_MASK = 0x1, 351 PMREBS_PMRWBZ_MASK = 0xffffff, 352 }; 353 354 #define NVME_PMREBS_PMRSZU(pmrebs) \ 355 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 356 #define NVME_PMREBS_RBB(pmrebs) \ 357 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 358 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 359 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 360 361 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 362 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 363 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 364 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 365 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 366 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 367 368 enum NvmePmrswtpShift { 369 PMRSWTP_PMRSWTU_SHIFT = 0, 370 PMRSWTP_PMRSWTV_SHIFT = 8, 371 }; 372 373 enum NvmePmrswtpMask { 374 PMRSWTP_PMRSWTU_MASK = 0xf, 375 PMRSWTP_PMRSWTV_MASK = 0xffffff, 376 }; 377 378 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 379 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 380 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 381 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 382 383 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 384 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 385 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 386 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 387 388 enum NvmePmrmscShift { 389 PMRMSC_CMSE_SHIFT = 1, 390 PMRMSC_CBA_SHIFT = 12, 391 }; 392 393 enum NvmePmrmscMask { 394 PMRMSC_CMSE_MASK = 0x1, 395 PMRMSC_CBA_MASK = 0xfffffffffffff, 396 }; 397 398 #define NVME_PMRMSC_CMSE(pmrmsc) \ 399 ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 400 #define NVME_PMRMSC_CBA(pmrmsc) \ 401 ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 402 403 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 404 (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 405 #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 406 (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 407 408 enum NvmeSglDescriptorType { 409 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 410 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 411 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 412 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 413 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 414 415 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 416 }; 417 418 enum NvmeSglDescriptorSubtype { 419 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 420 }; 421 422 typedef struct QEMU_PACKED NvmeSglDescriptor { 423 uint64_t addr; 424 uint32_t len; 425 uint8_t rsvd[3]; 426 uint8_t type; 427 } NvmeSglDescriptor; 428 429 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 430 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 431 432 typedef union NvmeCmdDptr { 433 struct { 434 uint64_t prp1; 435 uint64_t prp2; 436 }; 437 438 NvmeSglDescriptor sgl; 439 } NvmeCmdDptr; 440 441 enum NvmePsdt { 442 NVME_PSDT_PRP = 0x0, 443 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 444 NVME_PSDT_SGL_MPTR_SGL = 0x2, 445 }; 446 447 typedef struct QEMU_PACKED NvmeCmd { 448 uint8_t opcode; 449 uint8_t flags; 450 uint16_t cid; 451 uint32_t nsid; 452 uint64_t res1; 453 uint64_t mptr; 454 NvmeCmdDptr dptr; 455 uint32_t cdw10; 456 uint32_t cdw11; 457 uint32_t cdw12; 458 uint32_t cdw13; 459 uint32_t cdw14; 460 uint32_t cdw15; 461 } NvmeCmd; 462 463 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 464 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 465 466 enum NvmeAdminCommands { 467 NVME_ADM_CMD_DELETE_SQ = 0x00, 468 NVME_ADM_CMD_CREATE_SQ = 0x01, 469 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 470 NVME_ADM_CMD_DELETE_CQ = 0x04, 471 NVME_ADM_CMD_CREATE_CQ = 0x05, 472 NVME_ADM_CMD_IDENTIFY = 0x06, 473 NVME_ADM_CMD_ABORT = 0x08, 474 NVME_ADM_CMD_SET_FEATURES = 0x09, 475 NVME_ADM_CMD_GET_FEATURES = 0x0a, 476 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 477 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 478 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 479 NVME_ADM_CMD_FORMAT_NVM = 0x80, 480 NVME_ADM_CMD_SECURITY_SEND = 0x81, 481 NVME_ADM_CMD_SECURITY_RECV = 0x82, 482 }; 483 484 enum NvmeIoCommands { 485 NVME_CMD_FLUSH = 0x00, 486 NVME_CMD_WRITE = 0x01, 487 NVME_CMD_READ = 0x02, 488 NVME_CMD_WRITE_UNCOR = 0x04, 489 NVME_CMD_COMPARE = 0x05, 490 NVME_CMD_WRITE_ZEROES = 0x08, 491 NVME_CMD_DSM = 0x09, 492 }; 493 494 typedef struct QEMU_PACKED NvmeDeleteQ { 495 uint8_t opcode; 496 uint8_t flags; 497 uint16_t cid; 498 uint32_t rsvd1[9]; 499 uint16_t qid; 500 uint16_t rsvd10; 501 uint32_t rsvd11[5]; 502 } NvmeDeleteQ; 503 504 typedef struct QEMU_PACKED NvmeCreateCq { 505 uint8_t opcode; 506 uint8_t flags; 507 uint16_t cid; 508 uint32_t rsvd1[5]; 509 uint64_t prp1; 510 uint64_t rsvd8; 511 uint16_t cqid; 512 uint16_t qsize; 513 uint16_t cq_flags; 514 uint16_t irq_vector; 515 uint32_t rsvd12[4]; 516 } NvmeCreateCq; 517 518 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 519 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 520 521 enum NvmeFlagsCq { 522 NVME_CQ_PC = 1, 523 NVME_CQ_IEN = 2, 524 }; 525 526 typedef struct QEMU_PACKED NvmeCreateSq { 527 uint8_t opcode; 528 uint8_t flags; 529 uint16_t cid; 530 uint32_t rsvd1[5]; 531 uint64_t prp1; 532 uint64_t rsvd8; 533 uint16_t sqid; 534 uint16_t qsize; 535 uint16_t sq_flags; 536 uint16_t cqid; 537 uint32_t rsvd12[4]; 538 } NvmeCreateSq; 539 540 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 541 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 542 543 enum NvmeFlagsSq { 544 NVME_SQ_PC = 1, 545 546 NVME_SQ_PRIO_URGENT = 0, 547 NVME_SQ_PRIO_HIGH = 1, 548 NVME_SQ_PRIO_NORMAL = 2, 549 NVME_SQ_PRIO_LOW = 3, 550 }; 551 552 typedef struct QEMU_PACKED NvmeIdentify { 553 uint8_t opcode; 554 uint8_t flags; 555 uint16_t cid; 556 uint32_t nsid; 557 uint64_t rsvd2[2]; 558 uint64_t prp1; 559 uint64_t prp2; 560 uint8_t cns; 561 uint8_t rsvd10; 562 uint16_t ctrlid; 563 uint16_t nvmsetid; 564 uint8_t rsvd11; 565 uint8_t csi; 566 uint32_t rsvd12[4]; 567 } NvmeIdentify; 568 569 typedef struct QEMU_PACKED NvmeRwCmd { 570 uint8_t opcode; 571 uint8_t flags; 572 uint16_t cid; 573 uint32_t nsid; 574 uint64_t rsvd2; 575 uint64_t mptr; 576 NvmeCmdDptr dptr; 577 uint64_t slba; 578 uint16_t nlb; 579 uint16_t control; 580 uint32_t dsmgmt; 581 uint32_t reftag; 582 uint16_t apptag; 583 uint16_t appmask; 584 } NvmeRwCmd; 585 586 enum { 587 NVME_RW_LR = 1 << 15, 588 NVME_RW_FUA = 1 << 14, 589 NVME_RW_DSM_FREQ_UNSPEC = 0, 590 NVME_RW_DSM_FREQ_TYPICAL = 1, 591 NVME_RW_DSM_FREQ_RARE = 2, 592 NVME_RW_DSM_FREQ_READS = 3, 593 NVME_RW_DSM_FREQ_WRITES = 4, 594 NVME_RW_DSM_FREQ_RW = 5, 595 NVME_RW_DSM_FREQ_ONCE = 6, 596 NVME_RW_DSM_FREQ_PREFETCH = 7, 597 NVME_RW_DSM_FREQ_TEMP = 8, 598 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 599 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 600 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 601 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 602 NVME_RW_DSM_SEQ_REQ = 1 << 6, 603 NVME_RW_DSM_COMPRESSED = 1 << 7, 604 NVME_RW_PRINFO_PRACT = 1 << 13, 605 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 606 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 607 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 608 }; 609 610 typedef struct QEMU_PACKED NvmeDsmCmd { 611 uint8_t opcode; 612 uint8_t flags; 613 uint16_t cid; 614 uint32_t nsid; 615 uint64_t rsvd2[2]; 616 NvmeCmdDptr dptr; 617 uint32_t nr; 618 uint32_t attributes; 619 uint32_t rsvd12[4]; 620 } NvmeDsmCmd; 621 622 enum { 623 NVME_DSMGMT_IDR = 1 << 0, 624 NVME_DSMGMT_IDW = 1 << 1, 625 NVME_DSMGMT_AD = 1 << 2, 626 }; 627 628 typedef struct QEMU_PACKED NvmeDsmRange { 629 uint32_t cattr; 630 uint32_t nlb; 631 uint64_t slba; 632 } NvmeDsmRange; 633 634 enum NvmeAsyncEventRequest { 635 NVME_AER_TYPE_ERROR = 0, 636 NVME_AER_TYPE_SMART = 1, 637 NVME_AER_TYPE_IO_SPECIFIC = 6, 638 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 639 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 640 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 641 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 642 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 643 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 644 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 645 NVME_AER_INFO_SMART_RELIABILITY = 0, 646 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 647 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 648 }; 649 650 typedef struct QEMU_PACKED NvmeAerResult { 651 uint8_t event_type; 652 uint8_t event_info; 653 uint8_t log_page; 654 uint8_t resv; 655 } NvmeAerResult; 656 657 typedef struct QEMU_PACKED NvmeCqe { 658 uint32_t result; 659 uint32_t rsvd; 660 uint16_t sq_head; 661 uint16_t sq_id; 662 uint16_t cid; 663 uint16_t status; 664 } NvmeCqe; 665 666 enum NvmeStatusCodes { 667 NVME_SUCCESS = 0x0000, 668 NVME_INVALID_OPCODE = 0x0001, 669 NVME_INVALID_FIELD = 0x0002, 670 NVME_CID_CONFLICT = 0x0003, 671 NVME_DATA_TRAS_ERROR = 0x0004, 672 NVME_POWER_LOSS_ABORT = 0x0005, 673 NVME_INTERNAL_DEV_ERROR = 0x0006, 674 NVME_CMD_ABORT_REQ = 0x0007, 675 NVME_CMD_ABORT_SQ_DEL = 0x0008, 676 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 677 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 678 NVME_INVALID_NSID = 0x000b, 679 NVME_CMD_SEQ_ERROR = 0x000c, 680 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 681 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 682 NVME_DATA_SGL_LEN_INVALID = 0x000f, 683 NVME_MD_SGL_LEN_INVALID = 0x0010, 684 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 685 NVME_INVALID_USE_OF_CMB = 0x0012, 686 NVME_INVALID_PRP_OFFSET = 0x0013, 687 NVME_CMD_SET_CMB_REJECTED = 0x002b, 688 NVME_LBA_RANGE = 0x0080, 689 NVME_CAP_EXCEEDED = 0x0081, 690 NVME_NS_NOT_READY = 0x0082, 691 NVME_NS_RESV_CONFLICT = 0x0083, 692 NVME_INVALID_CQID = 0x0100, 693 NVME_INVALID_QID = 0x0101, 694 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 695 NVME_ACL_EXCEEDED = 0x0103, 696 NVME_RESERVED = 0x0104, 697 NVME_AER_LIMIT_EXCEEDED = 0x0105, 698 NVME_INVALID_FW_SLOT = 0x0106, 699 NVME_INVALID_FW_IMAGE = 0x0107, 700 NVME_INVALID_IRQ_VECTOR = 0x0108, 701 NVME_INVALID_LOG_ID = 0x0109, 702 NVME_INVALID_FORMAT = 0x010a, 703 NVME_FW_REQ_RESET = 0x010b, 704 NVME_INVALID_QUEUE_DEL = 0x010c, 705 NVME_FID_NOT_SAVEABLE = 0x010d, 706 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 707 NVME_FEAT_NOT_NS_SPEC = 0x010f, 708 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 709 NVME_CONFLICTING_ATTRS = 0x0180, 710 NVME_INVALID_PROT_INFO = 0x0181, 711 NVME_WRITE_TO_RO = 0x0182, 712 NVME_WRITE_FAULT = 0x0280, 713 NVME_UNRECOVERED_READ = 0x0281, 714 NVME_E2E_GUARD_ERROR = 0x0282, 715 NVME_E2E_APP_ERROR = 0x0283, 716 NVME_E2E_REF_ERROR = 0x0284, 717 NVME_CMP_FAILURE = 0x0285, 718 NVME_ACCESS_DENIED = 0x0286, 719 NVME_DULB = 0x0287, 720 NVME_MORE = 0x2000, 721 NVME_DNR = 0x4000, 722 NVME_NO_COMPLETE = 0xffff, 723 }; 724 725 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 726 uint8_t afi; 727 uint8_t reserved1[7]; 728 uint8_t frs1[8]; 729 uint8_t frs2[8]; 730 uint8_t frs3[8]; 731 uint8_t frs4[8]; 732 uint8_t frs5[8]; 733 uint8_t frs6[8]; 734 uint8_t frs7[8]; 735 uint8_t reserved2[448]; 736 } NvmeFwSlotInfoLog; 737 738 typedef struct QEMU_PACKED NvmeErrorLog { 739 uint64_t error_count; 740 uint16_t sqid; 741 uint16_t cid; 742 uint16_t status_field; 743 uint16_t param_error_location; 744 uint64_t lba; 745 uint32_t nsid; 746 uint8_t vs; 747 uint8_t resv[35]; 748 } NvmeErrorLog; 749 750 typedef struct QEMU_PACKED NvmeSmartLog { 751 uint8_t critical_warning; 752 uint16_t temperature; 753 uint8_t available_spare; 754 uint8_t available_spare_threshold; 755 uint8_t percentage_used; 756 uint8_t reserved1[26]; 757 uint64_t data_units_read[2]; 758 uint64_t data_units_written[2]; 759 uint64_t host_read_commands[2]; 760 uint64_t host_write_commands[2]; 761 uint64_t controller_busy_time[2]; 762 uint64_t power_cycles[2]; 763 uint64_t power_on_hours[2]; 764 uint64_t unsafe_shutdowns[2]; 765 uint64_t media_errors[2]; 766 uint64_t number_of_error_log_entries[2]; 767 uint8_t reserved2[320]; 768 } NvmeSmartLog; 769 770 enum NvmeSmartWarn { 771 NVME_SMART_SPARE = 1 << 0, 772 NVME_SMART_TEMPERATURE = 1 << 1, 773 NVME_SMART_RELIABILITY = 1 << 2, 774 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 775 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 776 }; 777 778 typedef struct NvmeEffectsLog { 779 uint32_t acs[256]; 780 uint32_t iocs[256]; 781 uint8_t resv[2048]; 782 } NvmeEffectsLog; 783 784 enum { 785 NVME_CMD_EFF_CSUPP = 1 << 0, 786 NVME_CMD_EFF_LBCC = 1 << 1, 787 NVME_CMD_EFF_NCC = 1 << 2, 788 NVME_CMD_EFF_NIC = 1 << 3, 789 NVME_CMD_EFF_CCC = 1 << 4, 790 NVME_CMD_EFF_CSE_MASK = 3 << 16, 791 NVME_CMD_EFF_UUID_SEL = 1 << 19, 792 }; 793 794 enum NvmeLogIdentifier { 795 NVME_LOG_ERROR_INFO = 0x01, 796 NVME_LOG_SMART_INFO = 0x02, 797 NVME_LOG_FW_SLOT_INFO = 0x03, 798 NVME_LOG_CMD_EFFECTS = 0x05, 799 }; 800 801 typedef struct QEMU_PACKED NvmePSD { 802 uint16_t mp; 803 uint16_t reserved; 804 uint32_t enlat; 805 uint32_t exlat; 806 uint8_t rrt; 807 uint8_t rrl; 808 uint8_t rwt; 809 uint8_t rwl; 810 uint8_t resv[16]; 811 } NvmePSD; 812 813 #define NVME_IDENTIFY_DATA_SIZE 4096 814 815 enum NvmeIdCns { 816 NVME_ID_CNS_NS = 0x00, 817 NVME_ID_CNS_CTRL = 0x01, 818 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 819 NVME_ID_CNS_NS_DESCR_LIST = 0x03, 820 NVME_ID_CNS_CS_NS = 0x05, 821 NVME_ID_CNS_CS_CTRL = 0x06, 822 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 823 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 824 NVME_ID_CNS_NS_PRESENT = 0x11, 825 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 826 NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 827 NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 828 }; 829 830 typedef struct QEMU_PACKED NvmeIdCtrl { 831 uint16_t vid; 832 uint16_t ssvid; 833 uint8_t sn[20]; 834 uint8_t mn[40]; 835 uint8_t fr[8]; 836 uint8_t rab; 837 uint8_t ieee[3]; 838 uint8_t cmic; 839 uint8_t mdts; 840 uint16_t cntlid; 841 uint32_t ver; 842 uint32_t rtd3r; 843 uint32_t rtd3e; 844 uint32_t oaes; 845 uint32_t ctratt; 846 uint8_t rsvd100[12]; 847 uint8_t fguid[16]; 848 uint8_t rsvd128[128]; 849 uint16_t oacs; 850 uint8_t acl; 851 uint8_t aerl; 852 uint8_t frmw; 853 uint8_t lpa; 854 uint8_t elpe; 855 uint8_t npss; 856 uint8_t avscc; 857 uint8_t apsta; 858 uint16_t wctemp; 859 uint16_t cctemp; 860 uint16_t mtfa; 861 uint32_t hmpre; 862 uint32_t hmmin; 863 uint8_t tnvmcap[16]; 864 uint8_t unvmcap[16]; 865 uint32_t rpmbs; 866 uint16_t edstt; 867 uint8_t dsto; 868 uint8_t fwug; 869 uint16_t kas; 870 uint16_t hctma; 871 uint16_t mntmt; 872 uint16_t mxtmt; 873 uint32_t sanicap; 874 uint8_t rsvd332[180]; 875 uint8_t sqes; 876 uint8_t cqes; 877 uint16_t maxcmd; 878 uint32_t nn; 879 uint16_t oncs; 880 uint16_t fuses; 881 uint8_t fna; 882 uint8_t vwc; 883 uint16_t awun; 884 uint16_t awupf; 885 uint8_t nvscc; 886 uint8_t rsvd531; 887 uint16_t acwu; 888 uint8_t rsvd534[2]; 889 uint32_t sgls; 890 uint8_t rsvd540[228]; 891 uint8_t subnqn[256]; 892 uint8_t rsvd1024[1024]; 893 NvmePSD psd[32]; 894 uint8_t vs[1024]; 895 } NvmeIdCtrl; 896 897 enum NvmeIdCtrlOacs { 898 NVME_OACS_SECURITY = 1 << 0, 899 NVME_OACS_FORMAT = 1 << 1, 900 NVME_OACS_FW = 1 << 2, 901 }; 902 903 enum NvmeIdCtrlOncs { 904 NVME_ONCS_COMPARE = 1 << 0, 905 NVME_ONCS_WRITE_UNCORR = 1 << 1, 906 NVME_ONCS_DSM = 1 << 2, 907 NVME_ONCS_WRITE_ZEROES = 1 << 3, 908 NVME_ONCS_FEATURES = 1 << 4, 909 NVME_ONCS_RESRVATIONS = 1 << 5, 910 NVME_ONCS_TIMESTAMP = 1 << 6, 911 }; 912 913 enum NvmeIdCtrlFrmw { 914 NVME_FRMW_SLOT1_RO = 1 << 0, 915 }; 916 917 enum NvmeIdCtrlLpa { 918 NVME_LPA_NS_SMART = 1 << 0, 919 NVME_LPA_CSE = 1 << 1, 920 NVME_LPA_EXTENDED = 1 << 2, 921 }; 922 923 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 924 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 925 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 926 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 927 928 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 929 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 930 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 931 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 932 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 933 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 934 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 935 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 936 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 937 938 #define NVME_ARB_AB(arb) (arb & 0x7) 939 #define NVME_ARB_AB_NOLIMIT 0x7 940 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 941 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 942 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 943 944 #define NVME_INTC_THR(intc) (intc & 0xff) 945 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 946 947 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 948 949 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 950 #define NVME_TEMP_THSEL_OVER 0x0 951 #define NVME_TEMP_THSEL_UNDER 0x1 952 953 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 954 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 955 956 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 957 958 #define NVME_AEC_SMART(aec) (aec & 0xff) 959 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 960 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 961 962 #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 963 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 964 965 enum NvmeFeatureIds { 966 NVME_ARBITRATION = 0x1, 967 NVME_POWER_MANAGEMENT = 0x2, 968 NVME_LBA_RANGE_TYPE = 0x3, 969 NVME_TEMPERATURE_THRESHOLD = 0x4, 970 NVME_ERROR_RECOVERY = 0x5, 971 NVME_VOLATILE_WRITE_CACHE = 0x6, 972 NVME_NUMBER_OF_QUEUES = 0x7, 973 NVME_INTERRUPT_COALESCING = 0x8, 974 NVME_INTERRUPT_VECTOR_CONF = 0x9, 975 NVME_WRITE_ATOMICITY = 0xa, 976 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 977 NVME_TIMESTAMP = 0xe, 978 NVME_COMMAND_SET_PROFILE = 0x19, 979 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 980 NVME_FID_MAX = 0x100, 981 }; 982 983 typedef enum NvmeFeatureCap { 984 NVME_FEAT_CAP_SAVE = 1 << 0, 985 NVME_FEAT_CAP_NS = 1 << 1, 986 NVME_FEAT_CAP_CHANGE = 1 << 2, 987 } NvmeFeatureCap; 988 989 typedef enum NvmeGetFeatureSelect { 990 NVME_GETFEAT_SELECT_CURRENT = 0x0, 991 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 992 NVME_GETFEAT_SELECT_SAVED = 0x2, 993 NVME_GETFEAT_SELECT_CAP = 0x3, 994 } NvmeGetFeatureSelect; 995 996 #define NVME_GETSETFEAT_FID_MASK 0xff 997 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 998 999 #define NVME_GETFEAT_SELECT_SHIFT 8 1000 #define NVME_GETFEAT_SELECT_MASK 0x7 1001 #define NVME_GETFEAT_SELECT(dw10) \ 1002 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 1003 1004 #define NVME_SETFEAT_SAVE_SHIFT 31 1005 #define NVME_SETFEAT_SAVE_MASK 0x1 1006 #define NVME_SETFEAT_SAVE(dw10) \ 1007 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 1008 1009 typedef struct QEMU_PACKED NvmeRangeType { 1010 uint8_t type; 1011 uint8_t attributes; 1012 uint8_t rsvd2[14]; 1013 uint64_t slba; 1014 uint64_t nlb; 1015 uint8_t guid[16]; 1016 uint8_t rsvd48[16]; 1017 } NvmeRangeType; 1018 1019 typedef struct QEMU_PACKED NvmeLBAF { 1020 uint16_t ms; 1021 uint8_t ds; 1022 uint8_t rp; 1023 } NvmeLBAF; 1024 1025 #define NVME_NSID_BROADCAST 0xffffffff 1026 1027 typedef struct QEMU_PACKED NvmeIdNs { 1028 uint64_t nsze; 1029 uint64_t ncap; 1030 uint64_t nuse; 1031 uint8_t nsfeat; 1032 uint8_t nlbaf; 1033 uint8_t flbas; 1034 uint8_t mc; 1035 uint8_t dpc; 1036 uint8_t dps; 1037 uint8_t nmic; 1038 uint8_t rescap; 1039 uint8_t fpi; 1040 uint8_t dlfeat; 1041 uint16_t nawun; 1042 uint16_t nawupf; 1043 uint16_t nacwu; 1044 uint16_t nabsn; 1045 uint16_t nabo; 1046 uint16_t nabspf; 1047 uint16_t noiob; 1048 uint8_t nvmcap[16]; 1049 uint16_t npwg; 1050 uint16_t npwa; 1051 uint16_t npdg; 1052 uint16_t npda; 1053 uint16_t nows; 1054 uint8_t rsvd74[30]; 1055 uint8_t nguid[16]; 1056 uint64_t eui64; 1057 NvmeLBAF lbaf[16]; 1058 uint8_t rsvd192[192]; 1059 uint8_t vs[3712]; 1060 } NvmeIdNs; 1061 1062 typedef struct QEMU_PACKED NvmeIdNsDescr { 1063 uint8_t nidt; 1064 uint8_t nidl; 1065 uint8_t rsvd2[2]; 1066 } NvmeIdNsDescr; 1067 1068 enum NvmeNsIdentifierLength { 1069 NVME_NIDL_EUI64 = 8, 1070 NVME_NIDL_NGUID = 16, 1071 NVME_NIDL_UUID = 16, 1072 NVME_NIDL_CSI = 1, 1073 }; 1074 1075 enum NvmeNsIdentifierType { 1076 NVME_NIDT_EUI64 = 0x01, 1077 NVME_NIDT_NGUID = 0x02, 1078 NVME_NIDT_UUID = 0x03, 1079 NVME_NIDT_CSI = 0x04, 1080 }; 1081 1082 enum NvmeCsi { 1083 NVME_CSI_NVM = 0x00, 1084 }; 1085 1086 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1087 1088 /*Deallocate Logical Block Features*/ 1089 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1090 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1091 1092 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1093 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1094 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1095 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1096 1097 1098 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1099 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1100 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1101 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1102 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1103 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1104 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1105 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1106 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1107 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1108 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1109 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1110 1111 enum NvmeIdNsDps { 1112 DPS_TYPE_NONE = 0, 1113 DPS_TYPE_1 = 1, 1114 DPS_TYPE_2 = 2, 1115 DPS_TYPE_3 = 3, 1116 DPS_TYPE_MASK = 0x7, 1117 DPS_FIRST_EIGHT = 8, 1118 }; 1119 1120 static inline void _nvme_check_size(void) 1121 { 1122 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1123 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1124 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1125 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1126 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1127 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1128 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1129 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1130 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1131 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1132 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1133 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1134 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1135 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1136 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1137 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1138 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1139 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1140 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1141 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1142 } 1143 #endif 1144