1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint32_t rsvd1; 11 uint32_t csts; 12 uint32_t nssrc; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint8_t padding[3520]; /* not used by QEMU */ 19 uint32_t pmrcap; 20 uint32_t pmrctl; 21 uint32_t pmrsts; 22 uint32_t pmrebs; 23 uint32_t pmrswtp; 24 uint64_t pmrmsc; 25 uint8_t reserved[484]; 26 } NvmeBar; 27 28 enum NvmeCapShift { 29 CAP_MQES_SHIFT = 0, 30 CAP_CQR_SHIFT = 16, 31 CAP_AMS_SHIFT = 17, 32 CAP_TO_SHIFT = 24, 33 CAP_DSTRD_SHIFT = 32, 34 CAP_NSSRS_SHIFT = 36, 35 CAP_CSS_SHIFT = 37, 36 CAP_MPSMIN_SHIFT = 48, 37 CAP_MPSMAX_SHIFT = 52, 38 CAP_PMRS_SHIFT = 56, 39 CAP_CMBS_SHIFT = 57, 40 }; 41 42 enum NvmeCapMask { 43 CAP_MQES_MASK = 0xffff, 44 CAP_CQR_MASK = 0x1, 45 CAP_AMS_MASK = 0x3, 46 CAP_TO_MASK = 0xff, 47 CAP_DSTRD_MASK = 0xf, 48 CAP_NSSRS_MASK = 0x1, 49 CAP_CSS_MASK = 0xff, 50 CAP_MPSMIN_MASK = 0xf, 51 CAP_MPSMAX_MASK = 0xf, 52 CAP_PMRS_MASK = 0x1, 53 CAP_CMBS_MASK = 0x1, 54 }; 55 56 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 57 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 58 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 59 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 60 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 61 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 62 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 63 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 64 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 65 #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) 66 67 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 68 << CAP_MQES_SHIFT) 69 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 70 << CAP_CQR_SHIFT) 71 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 72 << CAP_AMS_SHIFT) 73 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 74 << CAP_TO_SHIFT) 75 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 76 << CAP_DSTRD_SHIFT) 77 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 78 << CAP_NSSRS_SHIFT) 79 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 80 << CAP_CSS_SHIFT) 81 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 82 << CAP_MPSMIN_SHIFT) 83 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 84 << CAP_MPSMAX_SHIFT) 85 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMRS_MASK) \ 86 << CAP_PMRS_SHIFT) 87 #define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMBS_MASK) \ 88 << CAP_CMBS_SHIFT) 89 90 enum NvmeCapCss { 91 NVME_CAP_CSS_NVM = 1 << 0, 92 NVME_CAP_CSS_CSI_SUPP = 1 << 6, 93 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 94 }; 95 96 enum NvmeCcShift { 97 CC_EN_SHIFT = 0, 98 CC_CSS_SHIFT = 4, 99 CC_MPS_SHIFT = 7, 100 CC_AMS_SHIFT = 11, 101 CC_SHN_SHIFT = 14, 102 CC_IOSQES_SHIFT = 16, 103 CC_IOCQES_SHIFT = 20, 104 }; 105 106 enum NvmeCcMask { 107 CC_EN_MASK = 0x1, 108 CC_CSS_MASK = 0x7, 109 CC_MPS_MASK = 0xf, 110 CC_AMS_MASK = 0x7, 111 CC_SHN_MASK = 0x3, 112 CC_IOSQES_MASK = 0xf, 113 CC_IOCQES_MASK = 0xf, 114 }; 115 116 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 117 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 118 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 119 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 120 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 121 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 122 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 123 124 enum NvmeCcCss { 125 NVME_CC_CSS_NVM = 0x0, 126 NVME_CC_CSS_CSI = 0x6, 127 NVME_CC_CSS_ADMIN_ONLY = 0x7, 128 }; 129 130 #define NVME_SET_CC_EN(cc, val) \ 131 (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 132 #define NVME_SET_CC_CSS(cc, val) \ 133 (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 134 #define NVME_SET_CC_MPS(cc, val) \ 135 (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 136 #define NVME_SET_CC_AMS(cc, val) \ 137 (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 138 #define NVME_SET_CC_SHN(cc, val) \ 139 (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 140 #define NVME_SET_CC_IOSQES(cc, val) \ 141 (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 142 #define NVME_SET_CC_IOCQES(cc, val) \ 143 (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 144 145 enum NvmeCstsShift { 146 CSTS_RDY_SHIFT = 0, 147 CSTS_CFS_SHIFT = 1, 148 CSTS_SHST_SHIFT = 2, 149 CSTS_NSSRO_SHIFT = 4, 150 }; 151 152 enum NvmeCstsMask { 153 CSTS_RDY_MASK = 0x1, 154 CSTS_CFS_MASK = 0x1, 155 CSTS_SHST_MASK = 0x3, 156 CSTS_NSSRO_MASK = 0x1, 157 }; 158 159 enum NvmeCsts { 160 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 161 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 162 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 163 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 164 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 165 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 166 }; 167 168 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 169 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 170 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 171 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 172 173 enum NvmeAqaShift { 174 AQA_ASQS_SHIFT = 0, 175 AQA_ACQS_SHIFT = 16, 176 }; 177 178 enum NvmeAqaMask { 179 AQA_ASQS_MASK = 0xfff, 180 AQA_ACQS_MASK = 0xfff, 181 }; 182 183 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 184 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 185 186 enum NvmeCmblocShift { 187 CMBLOC_BIR_SHIFT = 0, 188 CMBLOC_OFST_SHIFT = 12, 189 }; 190 191 enum NvmeCmblocMask { 192 CMBLOC_BIR_MASK = 0x7, 193 CMBLOC_OFST_MASK = 0xfffff, 194 }; 195 196 #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ 197 CMBLOC_BIR_MASK) 198 #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ 199 CMBLOC_OFST_MASK) 200 201 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 202 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 203 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 204 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 205 206 enum NvmeCmbszShift { 207 CMBSZ_SQS_SHIFT = 0, 208 CMBSZ_CQS_SHIFT = 1, 209 CMBSZ_LISTS_SHIFT = 2, 210 CMBSZ_RDS_SHIFT = 3, 211 CMBSZ_WDS_SHIFT = 4, 212 CMBSZ_SZU_SHIFT = 8, 213 CMBSZ_SZ_SHIFT = 12, 214 }; 215 216 enum NvmeCmbszMask { 217 CMBSZ_SQS_MASK = 0x1, 218 CMBSZ_CQS_MASK = 0x1, 219 CMBSZ_LISTS_MASK = 0x1, 220 CMBSZ_RDS_MASK = 0x1, 221 CMBSZ_WDS_MASK = 0x1, 222 CMBSZ_SZU_MASK = 0xf, 223 CMBSZ_SZ_MASK = 0xfffff, 224 }; 225 226 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 227 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 228 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 229 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 230 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 231 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 232 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 233 234 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 235 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 236 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 237 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 238 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 239 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 240 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 241 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 242 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 243 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 244 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 245 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 246 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 247 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 248 249 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 250 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 251 252 enum NvmePmrcapShift { 253 PMRCAP_RDS_SHIFT = 3, 254 PMRCAP_WDS_SHIFT = 4, 255 PMRCAP_BIR_SHIFT = 5, 256 PMRCAP_PMRTU_SHIFT = 8, 257 PMRCAP_PMRWBM_SHIFT = 10, 258 PMRCAP_PMRTO_SHIFT = 16, 259 PMRCAP_CMSS_SHIFT = 24, 260 }; 261 262 enum NvmePmrcapMask { 263 PMRCAP_RDS_MASK = 0x1, 264 PMRCAP_WDS_MASK = 0x1, 265 PMRCAP_BIR_MASK = 0x7, 266 PMRCAP_PMRTU_MASK = 0x3, 267 PMRCAP_PMRWBM_MASK = 0xf, 268 PMRCAP_PMRTO_MASK = 0xff, 269 PMRCAP_CMSS_MASK = 0x1, 270 }; 271 272 #define NVME_PMRCAP_RDS(pmrcap) \ 273 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 274 #define NVME_PMRCAP_WDS(pmrcap) \ 275 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 276 #define NVME_PMRCAP_BIR(pmrcap) \ 277 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 278 #define NVME_PMRCAP_PMRTU(pmrcap) \ 279 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 280 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 281 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 282 #define NVME_PMRCAP_PMRTO(pmrcap) \ 283 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 284 #define NVME_PMRCAP_CMSS(pmrcap) \ 285 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 286 287 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 288 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 289 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 290 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 291 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 292 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 293 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 294 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 295 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 296 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 297 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 298 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 299 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 300 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 301 302 enum NvmePmrctlShift { 303 PMRCTL_EN_SHIFT = 0, 304 }; 305 306 enum NvmePmrctlMask { 307 PMRCTL_EN_MASK = 0x1, 308 }; 309 310 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 311 312 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 313 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 314 315 enum NvmePmrstsShift { 316 PMRSTS_ERR_SHIFT = 0, 317 PMRSTS_NRDY_SHIFT = 8, 318 PMRSTS_HSTS_SHIFT = 9, 319 PMRSTS_CBAI_SHIFT = 12, 320 }; 321 322 enum NvmePmrstsMask { 323 PMRSTS_ERR_MASK = 0xff, 324 PMRSTS_NRDY_MASK = 0x1, 325 PMRSTS_HSTS_MASK = 0x7, 326 PMRSTS_CBAI_MASK = 0x1, 327 }; 328 329 #define NVME_PMRSTS_ERR(pmrsts) \ 330 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 331 #define NVME_PMRSTS_NRDY(pmrsts) \ 332 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 333 #define NVME_PMRSTS_HSTS(pmrsts) \ 334 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 335 #define NVME_PMRSTS_CBAI(pmrsts) \ 336 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 337 338 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 339 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 340 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 341 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 342 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 343 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 344 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 345 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 346 347 enum NvmePmrebsShift { 348 PMREBS_PMRSZU_SHIFT = 0, 349 PMREBS_RBB_SHIFT = 4, 350 PMREBS_PMRWBZ_SHIFT = 8, 351 }; 352 353 enum NvmePmrebsMask { 354 PMREBS_PMRSZU_MASK = 0xf, 355 PMREBS_RBB_MASK = 0x1, 356 PMREBS_PMRWBZ_MASK = 0xffffff, 357 }; 358 359 #define NVME_PMREBS_PMRSZU(pmrebs) \ 360 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 361 #define NVME_PMREBS_RBB(pmrebs) \ 362 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 363 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 364 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 365 366 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 367 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 368 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 369 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 370 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 371 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 372 373 enum NvmePmrswtpShift { 374 PMRSWTP_PMRSWTU_SHIFT = 0, 375 PMRSWTP_PMRSWTV_SHIFT = 8, 376 }; 377 378 enum NvmePmrswtpMask { 379 PMRSWTP_PMRSWTU_MASK = 0xf, 380 PMRSWTP_PMRSWTV_MASK = 0xffffff, 381 }; 382 383 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 384 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 385 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 386 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 387 388 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 389 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 390 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 391 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 392 393 enum NvmePmrmscShift { 394 PMRMSC_CMSE_SHIFT = 1, 395 PMRMSC_CBA_SHIFT = 12, 396 }; 397 398 enum NvmePmrmscMask { 399 PMRMSC_CMSE_MASK = 0x1, 400 PMRMSC_CBA_MASK = 0xfffffffffffff, 401 }; 402 403 #define NVME_PMRMSC_CMSE(pmrmsc) \ 404 ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 405 #define NVME_PMRMSC_CBA(pmrmsc) \ 406 ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 407 408 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 409 (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 410 #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 411 (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 412 413 enum NvmeSglDescriptorType { 414 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 415 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 416 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 417 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 418 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 419 420 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 421 }; 422 423 enum NvmeSglDescriptorSubtype { 424 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 425 }; 426 427 typedef struct QEMU_PACKED NvmeSglDescriptor { 428 uint64_t addr; 429 uint32_t len; 430 uint8_t rsvd[3]; 431 uint8_t type; 432 } NvmeSglDescriptor; 433 434 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 435 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 436 437 typedef union NvmeCmdDptr { 438 struct { 439 uint64_t prp1; 440 uint64_t prp2; 441 }; 442 443 NvmeSglDescriptor sgl; 444 } NvmeCmdDptr; 445 446 enum NvmePsdt { 447 NVME_PSDT_PRP = 0x0, 448 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 449 NVME_PSDT_SGL_MPTR_SGL = 0x2, 450 }; 451 452 typedef struct QEMU_PACKED NvmeCmd { 453 uint8_t opcode; 454 uint8_t flags; 455 uint16_t cid; 456 uint32_t nsid; 457 uint64_t res1; 458 uint64_t mptr; 459 NvmeCmdDptr dptr; 460 uint32_t cdw10; 461 uint32_t cdw11; 462 uint32_t cdw12; 463 uint32_t cdw13; 464 uint32_t cdw14; 465 uint32_t cdw15; 466 } NvmeCmd; 467 468 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 469 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 470 471 enum NvmeAdminCommands { 472 NVME_ADM_CMD_DELETE_SQ = 0x00, 473 NVME_ADM_CMD_CREATE_SQ = 0x01, 474 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 475 NVME_ADM_CMD_DELETE_CQ = 0x04, 476 NVME_ADM_CMD_CREATE_CQ = 0x05, 477 NVME_ADM_CMD_IDENTIFY = 0x06, 478 NVME_ADM_CMD_ABORT = 0x08, 479 NVME_ADM_CMD_SET_FEATURES = 0x09, 480 NVME_ADM_CMD_GET_FEATURES = 0x0a, 481 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 482 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 483 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 484 NVME_ADM_CMD_FORMAT_NVM = 0x80, 485 NVME_ADM_CMD_SECURITY_SEND = 0x81, 486 NVME_ADM_CMD_SECURITY_RECV = 0x82, 487 }; 488 489 enum NvmeIoCommands { 490 NVME_CMD_FLUSH = 0x00, 491 NVME_CMD_WRITE = 0x01, 492 NVME_CMD_READ = 0x02, 493 NVME_CMD_WRITE_UNCOR = 0x04, 494 NVME_CMD_COMPARE = 0x05, 495 NVME_CMD_WRITE_ZEROES = 0x08, 496 NVME_CMD_DSM = 0x09, 497 NVME_CMD_ZONE_MGMT_SEND = 0x79, 498 NVME_CMD_ZONE_MGMT_RECV = 0x7a, 499 NVME_CMD_ZONE_APPEND = 0x7d, 500 }; 501 502 typedef struct QEMU_PACKED NvmeDeleteQ { 503 uint8_t opcode; 504 uint8_t flags; 505 uint16_t cid; 506 uint32_t rsvd1[9]; 507 uint16_t qid; 508 uint16_t rsvd10; 509 uint32_t rsvd11[5]; 510 } NvmeDeleteQ; 511 512 typedef struct QEMU_PACKED NvmeCreateCq { 513 uint8_t opcode; 514 uint8_t flags; 515 uint16_t cid; 516 uint32_t rsvd1[5]; 517 uint64_t prp1; 518 uint64_t rsvd8; 519 uint16_t cqid; 520 uint16_t qsize; 521 uint16_t cq_flags; 522 uint16_t irq_vector; 523 uint32_t rsvd12[4]; 524 } NvmeCreateCq; 525 526 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 527 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 528 529 enum NvmeFlagsCq { 530 NVME_CQ_PC = 1, 531 NVME_CQ_IEN = 2, 532 }; 533 534 typedef struct QEMU_PACKED NvmeCreateSq { 535 uint8_t opcode; 536 uint8_t flags; 537 uint16_t cid; 538 uint32_t rsvd1[5]; 539 uint64_t prp1; 540 uint64_t rsvd8; 541 uint16_t sqid; 542 uint16_t qsize; 543 uint16_t sq_flags; 544 uint16_t cqid; 545 uint32_t rsvd12[4]; 546 } NvmeCreateSq; 547 548 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 549 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 550 551 enum NvmeFlagsSq { 552 NVME_SQ_PC = 1, 553 554 NVME_SQ_PRIO_URGENT = 0, 555 NVME_SQ_PRIO_HIGH = 1, 556 NVME_SQ_PRIO_NORMAL = 2, 557 NVME_SQ_PRIO_LOW = 3, 558 }; 559 560 typedef struct QEMU_PACKED NvmeIdentify { 561 uint8_t opcode; 562 uint8_t flags; 563 uint16_t cid; 564 uint32_t nsid; 565 uint64_t rsvd2[2]; 566 uint64_t prp1; 567 uint64_t prp2; 568 uint8_t cns; 569 uint8_t rsvd10; 570 uint16_t ctrlid; 571 uint16_t nvmsetid; 572 uint8_t rsvd11; 573 uint8_t csi; 574 uint32_t rsvd12[4]; 575 } NvmeIdentify; 576 577 typedef struct QEMU_PACKED NvmeRwCmd { 578 uint8_t opcode; 579 uint8_t flags; 580 uint16_t cid; 581 uint32_t nsid; 582 uint64_t rsvd2; 583 uint64_t mptr; 584 NvmeCmdDptr dptr; 585 uint64_t slba; 586 uint16_t nlb; 587 uint16_t control; 588 uint32_t dsmgmt; 589 uint32_t reftag; 590 uint16_t apptag; 591 uint16_t appmask; 592 } NvmeRwCmd; 593 594 enum { 595 NVME_RW_LR = 1 << 15, 596 NVME_RW_FUA = 1 << 14, 597 NVME_RW_DSM_FREQ_UNSPEC = 0, 598 NVME_RW_DSM_FREQ_TYPICAL = 1, 599 NVME_RW_DSM_FREQ_RARE = 2, 600 NVME_RW_DSM_FREQ_READS = 3, 601 NVME_RW_DSM_FREQ_WRITES = 4, 602 NVME_RW_DSM_FREQ_RW = 5, 603 NVME_RW_DSM_FREQ_ONCE = 6, 604 NVME_RW_DSM_FREQ_PREFETCH = 7, 605 NVME_RW_DSM_FREQ_TEMP = 8, 606 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 607 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 608 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 609 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 610 NVME_RW_DSM_SEQ_REQ = 1 << 6, 611 NVME_RW_DSM_COMPRESSED = 1 << 7, 612 NVME_RW_PRINFO_PRACT = 1 << 13, 613 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 614 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 615 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 616 }; 617 618 typedef struct QEMU_PACKED NvmeDsmCmd { 619 uint8_t opcode; 620 uint8_t flags; 621 uint16_t cid; 622 uint32_t nsid; 623 uint64_t rsvd2[2]; 624 NvmeCmdDptr dptr; 625 uint32_t nr; 626 uint32_t attributes; 627 uint32_t rsvd12[4]; 628 } NvmeDsmCmd; 629 630 enum { 631 NVME_DSMGMT_IDR = 1 << 0, 632 NVME_DSMGMT_IDW = 1 << 1, 633 NVME_DSMGMT_AD = 1 << 2, 634 }; 635 636 typedef struct QEMU_PACKED NvmeDsmRange { 637 uint32_t cattr; 638 uint32_t nlb; 639 uint64_t slba; 640 } NvmeDsmRange; 641 642 enum NvmeAsyncEventRequest { 643 NVME_AER_TYPE_ERROR = 0, 644 NVME_AER_TYPE_SMART = 1, 645 NVME_AER_TYPE_IO_SPECIFIC = 6, 646 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 647 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 648 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 649 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 650 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 651 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 652 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 653 NVME_AER_INFO_SMART_RELIABILITY = 0, 654 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 655 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 656 }; 657 658 typedef struct QEMU_PACKED NvmeAerResult { 659 uint8_t event_type; 660 uint8_t event_info; 661 uint8_t log_page; 662 uint8_t resv; 663 } NvmeAerResult; 664 665 typedef struct QEMU_PACKED NvmeZonedResult { 666 uint64_t slba; 667 } NvmeZonedResult; 668 669 typedef struct QEMU_PACKED NvmeCqe { 670 uint32_t result; 671 uint32_t dw1; 672 uint16_t sq_head; 673 uint16_t sq_id; 674 uint16_t cid; 675 uint16_t status; 676 } NvmeCqe; 677 678 enum NvmeStatusCodes { 679 NVME_SUCCESS = 0x0000, 680 NVME_INVALID_OPCODE = 0x0001, 681 NVME_INVALID_FIELD = 0x0002, 682 NVME_CID_CONFLICT = 0x0003, 683 NVME_DATA_TRAS_ERROR = 0x0004, 684 NVME_POWER_LOSS_ABORT = 0x0005, 685 NVME_INTERNAL_DEV_ERROR = 0x0006, 686 NVME_CMD_ABORT_REQ = 0x0007, 687 NVME_CMD_ABORT_SQ_DEL = 0x0008, 688 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 689 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 690 NVME_INVALID_NSID = 0x000b, 691 NVME_CMD_SEQ_ERROR = 0x000c, 692 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 693 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 694 NVME_DATA_SGL_LEN_INVALID = 0x000f, 695 NVME_MD_SGL_LEN_INVALID = 0x0010, 696 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 697 NVME_INVALID_USE_OF_CMB = 0x0012, 698 NVME_INVALID_PRP_OFFSET = 0x0013, 699 NVME_CMD_SET_CMB_REJECTED = 0x002b, 700 NVME_INVALID_CMD_SET = 0x002c, 701 NVME_LBA_RANGE = 0x0080, 702 NVME_CAP_EXCEEDED = 0x0081, 703 NVME_NS_NOT_READY = 0x0082, 704 NVME_NS_RESV_CONFLICT = 0x0083, 705 NVME_INVALID_CQID = 0x0100, 706 NVME_INVALID_QID = 0x0101, 707 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 708 NVME_ACL_EXCEEDED = 0x0103, 709 NVME_RESERVED = 0x0104, 710 NVME_AER_LIMIT_EXCEEDED = 0x0105, 711 NVME_INVALID_FW_SLOT = 0x0106, 712 NVME_INVALID_FW_IMAGE = 0x0107, 713 NVME_INVALID_IRQ_VECTOR = 0x0108, 714 NVME_INVALID_LOG_ID = 0x0109, 715 NVME_INVALID_FORMAT = 0x010a, 716 NVME_FW_REQ_RESET = 0x010b, 717 NVME_INVALID_QUEUE_DEL = 0x010c, 718 NVME_FID_NOT_SAVEABLE = 0x010d, 719 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 720 NVME_FEAT_NOT_NS_SPEC = 0x010f, 721 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 722 NVME_CONFLICTING_ATTRS = 0x0180, 723 NVME_INVALID_PROT_INFO = 0x0181, 724 NVME_WRITE_TO_RO = 0x0182, 725 NVME_ZONE_BOUNDARY_ERROR = 0x01b8, 726 NVME_ZONE_FULL = 0x01b9, 727 NVME_ZONE_READ_ONLY = 0x01ba, 728 NVME_ZONE_OFFLINE = 0x01bb, 729 NVME_ZONE_INVALID_WRITE = 0x01bc, 730 NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, 731 NVME_ZONE_TOO_MANY_OPEN = 0x01be, 732 NVME_ZONE_INVAL_TRANSITION = 0x01bf, 733 NVME_WRITE_FAULT = 0x0280, 734 NVME_UNRECOVERED_READ = 0x0281, 735 NVME_E2E_GUARD_ERROR = 0x0282, 736 NVME_E2E_APP_ERROR = 0x0283, 737 NVME_E2E_REF_ERROR = 0x0284, 738 NVME_CMP_FAILURE = 0x0285, 739 NVME_ACCESS_DENIED = 0x0286, 740 NVME_DULB = 0x0287, 741 NVME_MORE = 0x2000, 742 NVME_DNR = 0x4000, 743 NVME_NO_COMPLETE = 0xffff, 744 }; 745 746 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 747 uint8_t afi; 748 uint8_t reserved1[7]; 749 uint8_t frs1[8]; 750 uint8_t frs2[8]; 751 uint8_t frs3[8]; 752 uint8_t frs4[8]; 753 uint8_t frs5[8]; 754 uint8_t frs6[8]; 755 uint8_t frs7[8]; 756 uint8_t reserved2[448]; 757 } NvmeFwSlotInfoLog; 758 759 typedef struct QEMU_PACKED NvmeErrorLog { 760 uint64_t error_count; 761 uint16_t sqid; 762 uint16_t cid; 763 uint16_t status_field; 764 uint16_t param_error_location; 765 uint64_t lba; 766 uint32_t nsid; 767 uint8_t vs; 768 uint8_t resv[35]; 769 } NvmeErrorLog; 770 771 typedef struct QEMU_PACKED NvmeSmartLog { 772 uint8_t critical_warning; 773 uint16_t temperature; 774 uint8_t available_spare; 775 uint8_t available_spare_threshold; 776 uint8_t percentage_used; 777 uint8_t reserved1[26]; 778 uint64_t data_units_read[2]; 779 uint64_t data_units_written[2]; 780 uint64_t host_read_commands[2]; 781 uint64_t host_write_commands[2]; 782 uint64_t controller_busy_time[2]; 783 uint64_t power_cycles[2]; 784 uint64_t power_on_hours[2]; 785 uint64_t unsafe_shutdowns[2]; 786 uint64_t media_errors[2]; 787 uint64_t number_of_error_log_entries[2]; 788 uint8_t reserved2[320]; 789 } NvmeSmartLog; 790 791 #define NVME_SMART_WARN_MAX 6 792 enum NvmeSmartWarn { 793 NVME_SMART_SPARE = 1 << 0, 794 NVME_SMART_TEMPERATURE = 1 << 1, 795 NVME_SMART_RELIABILITY = 1 << 2, 796 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 797 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 798 NVME_SMART_PMR_UNRELIABLE = 1 << 5, 799 }; 800 801 typedef struct NvmeEffectsLog { 802 uint32_t acs[256]; 803 uint32_t iocs[256]; 804 uint8_t resv[2048]; 805 } NvmeEffectsLog; 806 807 enum { 808 NVME_CMD_EFF_CSUPP = 1 << 0, 809 NVME_CMD_EFF_LBCC = 1 << 1, 810 NVME_CMD_EFF_NCC = 1 << 2, 811 NVME_CMD_EFF_NIC = 1 << 3, 812 NVME_CMD_EFF_CCC = 1 << 4, 813 NVME_CMD_EFF_CSE_MASK = 3 << 16, 814 NVME_CMD_EFF_UUID_SEL = 1 << 19, 815 }; 816 817 enum NvmeLogIdentifier { 818 NVME_LOG_ERROR_INFO = 0x01, 819 NVME_LOG_SMART_INFO = 0x02, 820 NVME_LOG_FW_SLOT_INFO = 0x03, 821 NVME_LOG_CMD_EFFECTS = 0x05, 822 }; 823 824 typedef struct QEMU_PACKED NvmePSD { 825 uint16_t mp; 826 uint16_t reserved; 827 uint32_t enlat; 828 uint32_t exlat; 829 uint8_t rrt; 830 uint8_t rrl; 831 uint8_t rwt; 832 uint8_t rwl; 833 uint8_t resv[16]; 834 } NvmePSD; 835 836 #define NVME_IDENTIFY_DATA_SIZE 4096 837 838 enum NvmeIdCns { 839 NVME_ID_CNS_NS = 0x00, 840 NVME_ID_CNS_CTRL = 0x01, 841 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 842 NVME_ID_CNS_NS_DESCR_LIST = 0x03, 843 NVME_ID_CNS_CS_NS = 0x05, 844 NVME_ID_CNS_CS_CTRL = 0x06, 845 NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 846 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 847 NVME_ID_CNS_NS_PRESENT = 0x11, 848 NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 849 NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 850 NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 851 }; 852 853 typedef struct QEMU_PACKED NvmeIdCtrl { 854 uint16_t vid; 855 uint16_t ssvid; 856 uint8_t sn[20]; 857 uint8_t mn[40]; 858 uint8_t fr[8]; 859 uint8_t rab; 860 uint8_t ieee[3]; 861 uint8_t cmic; 862 uint8_t mdts; 863 uint16_t cntlid; 864 uint32_t ver; 865 uint32_t rtd3r; 866 uint32_t rtd3e; 867 uint32_t oaes; 868 uint32_t ctratt; 869 uint8_t rsvd100[12]; 870 uint8_t fguid[16]; 871 uint8_t rsvd128[128]; 872 uint16_t oacs; 873 uint8_t acl; 874 uint8_t aerl; 875 uint8_t frmw; 876 uint8_t lpa; 877 uint8_t elpe; 878 uint8_t npss; 879 uint8_t avscc; 880 uint8_t apsta; 881 uint16_t wctemp; 882 uint16_t cctemp; 883 uint16_t mtfa; 884 uint32_t hmpre; 885 uint32_t hmmin; 886 uint8_t tnvmcap[16]; 887 uint8_t unvmcap[16]; 888 uint32_t rpmbs; 889 uint16_t edstt; 890 uint8_t dsto; 891 uint8_t fwug; 892 uint16_t kas; 893 uint16_t hctma; 894 uint16_t mntmt; 895 uint16_t mxtmt; 896 uint32_t sanicap; 897 uint8_t rsvd332[180]; 898 uint8_t sqes; 899 uint8_t cqes; 900 uint16_t maxcmd; 901 uint32_t nn; 902 uint16_t oncs; 903 uint16_t fuses; 904 uint8_t fna; 905 uint8_t vwc; 906 uint16_t awun; 907 uint16_t awupf; 908 uint8_t nvscc; 909 uint8_t rsvd531; 910 uint16_t acwu; 911 uint8_t rsvd534[2]; 912 uint32_t sgls; 913 uint8_t rsvd540[228]; 914 uint8_t subnqn[256]; 915 uint8_t rsvd1024[1024]; 916 NvmePSD psd[32]; 917 uint8_t vs[1024]; 918 } NvmeIdCtrl; 919 920 typedef struct NvmeIdCtrlZoned { 921 uint8_t zasl; 922 uint8_t rsvd1[4095]; 923 } NvmeIdCtrlZoned; 924 925 enum NvmeIdCtrlOacs { 926 NVME_OACS_SECURITY = 1 << 0, 927 NVME_OACS_FORMAT = 1 << 1, 928 NVME_OACS_FW = 1 << 2, 929 }; 930 931 enum NvmeIdCtrlOncs { 932 NVME_ONCS_COMPARE = 1 << 0, 933 NVME_ONCS_WRITE_UNCORR = 1 << 1, 934 NVME_ONCS_DSM = 1 << 2, 935 NVME_ONCS_WRITE_ZEROES = 1 << 3, 936 NVME_ONCS_FEATURES = 1 << 4, 937 NVME_ONCS_RESRVATIONS = 1 << 5, 938 NVME_ONCS_TIMESTAMP = 1 << 6, 939 }; 940 941 enum NvmeIdCtrlFrmw { 942 NVME_FRMW_SLOT1_RO = 1 << 0, 943 }; 944 945 enum NvmeIdCtrlLpa { 946 NVME_LPA_NS_SMART = 1 << 0, 947 NVME_LPA_CSE = 1 << 1, 948 NVME_LPA_EXTENDED = 1 << 2, 949 }; 950 951 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 952 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 953 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 954 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 955 956 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 957 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 958 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 959 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 960 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 961 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 962 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 963 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 964 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 965 966 #define NVME_ARB_AB(arb) (arb & 0x7) 967 #define NVME_ARB_AB_NOLIMIT 0x7 968 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 969 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 970 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 971 972 #define NVME_INTC_THR(intc) (intc & 0xff) 973 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 974 975 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 976 977 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 978 #define NVME_TEMP_THSEL_OVER 0x0 979 #define NVME_TEMP_THSEL_UNDER 0x1 980 981 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 982 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 983 984 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 985 986 #define NVME_AEC_SMART(aec) (aec & 0xff) 987 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 988 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 989 990 #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 991 #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 992 993 enum NvmeFeatureIds { 994 NVME_ARBITRATION = 0x1, 995 NVME_POWER_MANAGEMENT = 0x2, 996 NVME_LBA_RANGE_TYPE = 0x3, 997 NVME_TEMPERATURE_THRESHOLD = 0x4, 998 NVME_ERROR_RECOVERY = 0x5, 999 NVME_VOLATILE_WRITE_CACHE = 0x6, 1000 NVME_NUMBER_OF_QUEUES = 0x7, 1001 NVME_INTERRUPT_COALESCING = 0x8, 1002 NVME_INTERRUPT_VECTOR_CONF = 0x9, 1003 NVME_WRITE_ATOMICITY = 0xa, 1004 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 1005 NVME_TIMESTAMP = 0xe, 1006 NVME_COMMAND_SET_PROFILE = 0x19, 1007 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 1008 NVME_FID_MAX = 0x100, 1009 }; 1010 1011 typedef enum NvmeFeatureCap { 1012 NVME_FEAT_CAP_SAVE = 1 << 0, 1013 NVME_FEAT_CAP_NS = 1 << 1, 1014 NVME_FEAT_CAP_CHANGE = 1 << 2, 1015 } NvmeFeatureCap; 1016 1017 typedef enum NvmeGetFeatureSelect { 1018 NVME_GETFEAT_SELECT_CURRENT = 0x0, 1019 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 1020 NVME_GETFEAT_SELECT_SAVED = 0x2, 1021 NVME_GETFEAT_SELECT_CAP = 0x3, 1022 } NvmeGetFeatureSelect; 1023 1024 #define NVME_GETSETFEAT_FID_MASK 0xff 1025 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 1026 1027 #define NVME_GETFEAT_SELECT_SHIFT 8 1028 #define NVME_GETFEAT_SELECT_MASK 0x7 1029 #define NVME_GETFEAT_SELECT(dw10) \ 1030 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 1031 1032 #define NVME_SETFEAT_SAVE_SHIFT 31 1033 #define NVME_SETFEAT_SAVE_MASK 0x1 1034 #define NVME_SETFEAT_SAVE(dw10) \ 1035 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 1036 1037 typedef struct QEMU_PACKED NvmeRangeType { 1038 uint8_t type; 1039 uint8_t attributes; 1040 uint8_t rsvd2[14]; 1041 uint64_t slba; 1042 uint64_t nlb; 1043 uint8_t guid[16]; 1044 uint8_t rsvd48[16]; 1045 } NvmeRangeType; 1046 1047 typedef struct QEMU_PACKED NvmeLBAF { 1048 uint16_t ms; 1049 uint8_t ds; 1050 uint8_t rp; 1051 } NvmeLBAF; 1052 1053 typedef struct QEMU_PACKED NvmeLBAFE { 1054 uint64_t zsze; 1055 uint8_t zdes; 1056 uint8_t rsvd9[7]; 1057 } NvmeLBAFE; 1058 1059 #define NVME_NSID_BROADCAST 0xffffffff 1060 1061 typedef struct QEMU_PACKED NvmeIdNs { 1062 uint64_t nsze; 1063 uint64_t ncap; 1064 uint64_t nuse; 1065 uint8_t nsfeat; 1066 uint8_t nlbaf; 1067 uint8_t flbas; 1068 uint8_t mc; 1069 uint8_t dpc; 1070 uint8_t dps; 1071 uint8_t nmic; 1072 uint8_t rescap; 1073 uint8_t fpi; 1074 uint8_t dlfeat; 1075 uint16_t nawun; 1076 uint16_t nawupf; 1077 uint16_t nacwu; 1078 uint16_t nabsn; 1079 uint16_t nabo; 1080 uint16_t nabspf; 1081 uint16_t noiob; 1082 uint8_t nvmcap[16]; 1083 uint16_t npwg; 1084 uint16_t npwa; 1085 uint16_t npdg; 1086 uint16_t npda; 1087 uint16_t nows; 1088 uint8_t rsvd74[30]; 1089 uint8_t nguid[16]; 1090 uint64_t eui64; 1091 NvmeLBAF lbaf[16]; 1092 uint8_t rsvd192[192]; 1093 uint8_t vs[3712]; 1094 } NvmeIdNs; 1095 1096 typedef struct QEMU_PACKED NvmeIdNsDescr { 1097 uint8_t nidt; 1098 uint8_t nidl; 1099 uint8_t rsvd2[2]; 1100 } NvmeIdNsDescr; 1101 1102 enum NvmeNsIdentifierLength { 1103 NVME_NIDL_EUI64 = 8, 1104 NVME_NIDL_NGUID = 16, 1105 NVME_NIDL_UUID = 16, 1106 NVME_NIDL_CSI = 1, 1107 }; 1108 1109 enum NvmeNsIdentifierType { 1110 NVME_NIDT_EUI64 = 0x01, 1111 NVME_NIDT_NGUID = 0x02, 1112 NVME_NIDT_UUID = 0x03, 1113 NVME_NIDT_CSI = 0x04, 1114 }; 1115 1116 enum NvmeCsi { 1117 NVME_CSI_NVM = 0x00, 1118 NVME_CSI_ZONED = 0x02, 1119 }; 1120 1121 #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1122 1123 typedef struct QEMU_PACKED NvmeIdNsZoned { 1124 uint16_t zoc; 1125 uint16_t ozcs; 1126 uint32_t mar; 1127 uint32_t mor; 1128 uint32_t rrl; 1129 uint32_t frl; 1130 uint8_t rsvd20[2796]; 1131 NvmeLBAFE lbafe[16]; 1132 uint8_t rsvd3072[768]; 1133 uint8_t vs[256]; 1134 } NvmeIdNsZoned; 1135 1136 /*Deallocate Logical Block Features*/ 1137 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1138 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1139 1140 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1141 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1142 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1143 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1144 1145 1146 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1147 #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1148 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1149 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1150 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1151 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1152 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1153 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1154 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1155 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1156 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1157 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1158 1159 enum NvmeIdNsDps { 1160 DPS_TYPE_NONE = 0, 1161 DPS_TYPE_1 = 1, 1162 DPS_TYPE_2 = 2, 1163 DPS_TYPE_3 = 3, 1164 DPS_TYPE_MASK = 0x7, 1165 DPS_FIRST_EIGHT = 8, 1166 }; 1167 1168 enum NvmeZoneAttr { 1169 NVME_ZA_FINISHED_BY_CTLR = 1 << 0, 1170 NVME_ZA_FINISH_RECOMMENDED = 1 << 1, 1171 NVME_ZA_RESET_RECOMMENDED = 1 << 2, 1172 NVME_ZA_ZD_EXT_VALID = 1 << 7, 1173 }; 1174 1175 typedef struct QEMU_PACKED NvmeZoneReportHeader { 1176 uint64_t nr_zones; 1177 uint8_t rsvd[56]; 1178 } NvmeZoneReportHeader; 1179 1180 enum NvmeZoneReceiveAction { 1181 NVME_ZONE_REPORT = 0, 1182 NVME_ZONE_REPORT_EXTENDED = 1, 1183 }; 1184 1185 enum NvmeZoneReportType { 1186 NVME_ZONE_REPORT_ALL = 0, 1187 NVME_ZONE_REPORT_EMPTY = 1, 1188 NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, 1189 NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, 1190 NVME_ZONE_REPORT_CLOSED = 4, 1191 NVME_ZONE_REPORT_FULL = 5, 1192 NVME_ZONE_REPORT_READ_ONLY = 6, 1193 NVME_ZONE_REPORT_OFFLINE = 7, 1194 }; 1195 1196 enum NvmeZoneType { 1197 NVME_ZONE_TYPE_RESERVED = 0x00, 1198 NVME_ZONE_TYPE_SEQ_WRITE = 0x02, 1199 }; 1200 1201 enum NvmeZoneSendAction { 1202 NVME_ZONE_ACTION_RSD = 0x00, 1203 NVME_ZONE_ACTION_CLOSE = 0x01, 1204 NVME_ZONE_ACTION_FINISH = 0x02, 1205 NVME_ZONE_ACTION_OPEN = 0x03, 1206 NVME_ZONE_ACTION_RESET = 0x04, 1207 NVME_ZONE_ACTION_OFFLINE = 0x05, 1208 NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, 1209 }; 1210 1211 typedef struct QEMU_PACKED NvmeZoneDescr { 1212 uint8_t zt; 1213 uint8_t zs; 1214 uint8_t za; 1215 uint8_t rsvd3[5]; 1216 uint64_t zcap; 1217 uint64_t zslba; 1218 uint64_t wp; 1219 uint8_t rsvd32[32]; 1220 } NvmeZoneDescr; 1221 1222 typedef enum NvmeZoneState { 1223 NVME_ZONE_STATE_RESERVED = 0x00, 1224 NVME_ZONE_STATE_EMPTY = 0x01, 1225 NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, 1226 NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, 1227 NVME_ZONE_STATE_CLOSED = 0x04, 1228 NVME_ZONE_STATE_READ_ONLY = 0x0D, 1229 NVME_ZONE_STATE_FULL = 0x0E, 1230 NVME_ZONE_STATE_OFFLINE = 0x0F, 1231 } NvmeZoneState; 1232 1233 static inline void _nvme_check_size(void) 1234 { 1235 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1236 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1237 QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); 1238 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1239 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1240 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1241 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1242 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1243 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1244 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1245 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1246 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1247 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1248 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1249 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1250 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1251 QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1252 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1253 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); 1254 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); 1255 QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); 1256 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1257 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); 1258 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1259 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1260 QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); 1261 } 1262 #endif 1263