1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint32_t rsvd1; 11 uint32_t csts; 12 uint32_t nssrc; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint8_t padding[3520]; /* not used by QEMU */ 19 uint32_t pmrcap; 20 uint32_t pmrctl; 21 uint32_t pmrsts; 22 uint32_t pmrebs; 23 uint32_t pmrswtp; 24 uint64_t pmrmsc; 25 uint8_t reserved[484]; 26 } NvmeBar; 27 28 enum NvmeCapShift { 29 CAP_MQES_SHIFT = 0, 30 CAP_CQR_SHIFT = 16, 31 CAP_AMS_SHIFT = 17, 32 CAP_TO_SHIFT = 24, 33 CAP_DSTRD_SHIFT = 32, 34 CAP_NSSRS_SHIFT = 36, 35 CAP_CSS_SHIFT = 37, 36 CAP_MPSMIN_SHIFT = 48, 37 CAP_MPSMAX_SHIFT = 52, 38 CAP_PMR_SHIFT = 56, 39 }; 40 41 enum NvmeCapMask { 42 CAP_MQES_MASK = 0xffff, 43 CAP_CQR_MASK = 0x1, 44 CAP_AMS_MASK = 0x3, 45 CAP_TO_MASK = 0xff, 46 CAP_DSTRD_MASK = 0xf, 47 CAP_NSSRS_MASK = 0x1, 48 CAP_CSS_MASK = 0xff, 49 CAP_MPSMIN_MASK = 0xf, 50 CAP_MPSMAX_MASK = 0xf, 51 CAP_PMR_MASK = 0x1, 52 }; 53 54 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 55 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 56 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 57 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 58 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 59 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 60 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 61 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 62 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 63 64 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 65 << CAP_MQES_SHIFT) 66 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 67 << CAP_CQR_SHIFT) 68 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 69 << CAP_AMS_SHIFT) 70 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 71 << CAP_TO_SHIFT) 72 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 73 << CAP_DSTRD_SHIFT) 74 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 75 << CAP_NSSRS_SHIFT) 76 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 77 << CAP_CSS_SHIFT) 78 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 79 << CAP_MPSMIN_SHIFT) 80 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 81 << CAP_MPSMAX_SHIFT) 82 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ 83 << CAP_PMR_SHIFT) 84 85 enum NvmeCapCss { 86 NVME_CAP_CSS_NVM = 1 << 0, 87 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 88 }; 89 90 enum NvmeCcShift { 91 CC_EN_SHIFT = 0, 92 CC_CSS_SHIFT = 4, 93 CC_MPS_SHIFT = 7, 94 CC_AMS_SHIFT = 11, 95 CC_SHN_SHIFT = 14, 96 CC_IOSQES_SHIFT = 16, 97 CC_IOCQES_SHIFT = 20, 98 }; 99 100 enum NvmeCcMask { 101 CC_EN_MASK = 0x1, 102 CC_CSS_MASK = 0x7, 103 CC_MPS_MASK = 0xf, 104 CC_AMS_MASK = 0x7, 105 CC_SHN_MASK = 0x3, 106 CC_IOSQES_MASK = 0xf, 107 CC_IOCQES_MASK = 0xf, 108 }; 109 110 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 111 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 112 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 113 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 114 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 115 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 116 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 117 118 enum NvmeCstsShift { 119 CSTS_RDY_SHIFT = 0, 120 CSTS_CFS_SHIFT = 1, 121 CSTS_SHST_SHIFT = 2, 122 CSTS_NSSRO_SHIFT = 4, 123 }; 124 125 enum NvmeCstsMask { 126 CSTS_RDY_MASK = 0x1, 127 CSTS_CFS_MASK = 0x1, 128 CSTS_SHST_MASK = 0x3, 129 CSTS_NSSRO_MASK = 0x1, 130 }; 131 132 enum NvmeCsts { 133 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 134 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 135 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 136 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 137 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 138 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 139 }; 140 141 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 142 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 143 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 144 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 145 146 enum NvmeAqaShift { 147 AQA_ASQS_SHIFT = 0, 148 AQA_ACQS_SHIFT = 16, 149 }; 150 151 enum NvmeAqaMask { 152 AQA_ASQS_MASK = 0xfff, 153 AQA_ACQS_MASK = 0xfff, 154 }; 155 156 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 157 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 158 159 enum NvmeCmblocShift { 160 CMBLOC_BIR_SHIFT = 0, 161 CMBLOC_OFST_SHIFT = 12, 162 }; 163 164 enum NvmeCmblocMask { 165 CMBLOC_BIR_MASK = 0x7, 166 CMBLOC_OFST_MASK = 0xfffff, 167 }; 168 169 #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ 170 CMBLOC_BIR_MASK) 171 #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ 172 CMBLOC_OFST_MASK) 173 174 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 175 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 176 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 177 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 178 179 enum NvmeCmbszShift { 180 CMBSZ_SQS_SHIFT = 0, 181 CMBSZ_CQS_SHIFT = 1, 182 CMBSZ_LISTS_SHIFT = 2, 183 CMBSZ_RDS_SHIFT = 3, 184 CMBSZ_WDS_SHIFT = 4, 185 CMBSZ_SZU_SHIFT = 8, 186 CMBSZ_SZ_SHIFT = 12, 187 }; 188 189 enum NvmeCmbszMask { 190 CMBSZ_SQS_MASK = 0x1, 191 CMBSZ_CQS_MASK = 0x1, 192 CMBSZ_LISTS_MASK = 0x1, 193 CMBSZ_RDS_MASK = 0x1, 194 CMBSZ_WDS_MASK = 0x1, 195 CMBSZ_SZU_MASK = 0xf, 196 CMBSZ_SZ_MASK = 0xfffff, 197 }; 198 199 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 200 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 201 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 202 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 203 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 204 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 205 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 206 207 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 208 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 209 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 210 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 211 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 212 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 213 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 214 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 215 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 216 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 217 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 218 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 219 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 220 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 221 222 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 223 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 224 225 enum NvmePmrcapShift { 226 PMRCAP_RDS_SHIFT = 3, 227 PMRCAP_WDS_SHIFT = 4, 228 PMRCAP_BIR_SHIFT = 5, 229 PMRCAP_PMRTU_SHIFT = 8, 230 PMRCAP_PMRWBM_SHIFT = 10, 231 PMRCAP_PMRTO_SHIFT = 16, 232 PMRCAP_CMSS_SHIFT = 24, 233 }; 234 235 enum NvmePmrcapMask { 236 PMRCAP_RDS_MASK = 0x1, 237 PMRCAP_WDS_MASK = 0x1, 238 PMRCAP_BIR_MASK = 0x7, 239 PMRCAP_PMRTU_MASK = 0x3, 240 PMRCAP_PMRWBM_MASK = 0xf, 241 PMRCAP_PMRTO_MASK = 0xff, 242 PMRCAP_CMSS_MASK = 0x1, 243 }; 244 245 #define NVME_PMRCAP_RDS(pmrcap) \ 246 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 247 #define NVME_PMRCAP_WDS(pmrcap) \ 248 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 249 #define NVME_PMRCAP_BIR(pmrcap) \ 250 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 251 #define NVME_PMRCAP_PMRTU(pmrcap) \ 252 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 253 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 254 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 255 #define NVME_PMRCAP_PMRTO(pmrcap) \ 256 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 257 #define NVME_PMRCAP_CMSS(pmrcap) \ 258 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 259 260 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 261 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 262 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 263 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 264 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 265 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 266 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 267 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 268 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 269 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 270 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 271 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 272 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 273 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 274 275 enum NvmePmrctlShift { 276 PMRCTL_EN_SHIFT = 0, 277 }; 278 279 enum NvmePmrctlMask { 280 PMRCTL_EN_MASK = 0x1, 281 }; 282 283 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 284 285 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 286 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 287 288 enum NvmePmrstsShift { 289 PMRSTS_ERR_SHIFT = 0, 290 PMRSTS_NRDY_SHIFT = 8, 291 PMRSTS_HSTS_SHIFT = 9, 292 PMRSTS_CBAI_SHIFT = 12, 293 }; 294 295 enum NvmePmrstsMask { 296 PMRSTS_ERR_MASK = 0xff, 297 PMRSTS_NRDY_MASK = 0x1, 298 PMRSTS_HSTS_MASK = 0x7, 299 PMRSTS_CBAI_MASK = 0x1, 300 }; 301 302 #define NVME_PMRSTS_ERR(pmrsts) \ 303 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 304 #define NVME_PMRSTS_NRDY(pmrsts) \ 305 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 306 #define NVME_PMRSTS_HSTS(pmrsts) \ 307 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 308 #define NVME_PMRSTS_CBAI(pmrsts) \ 309 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 310 311 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 312 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 313 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 314 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 315 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 316 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 317 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 318 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 319 320 enum NvmePmrebsShift { 321 PMREBS_PMRSZU_SHIFT = 0, 322 PMREBS_RBB_SHIFT = 4, 323 PMREBS_PMRWBZ_SHIFT = 8, 324 }; 325 326 enum NvmePmrebsMask { 327 PMREBS_PMRSZU_MASK = 0xf, 328 PMREBS_RBB_MASK = 0x1, 329 PMREBS_PMRWBZ_MASK = 0xffffff, 330 }; 331 332 #define NVME_PMREBS_PMRSZU(pmrebs) \ 333 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 334 #define NVME_PMREBS_RBB(pmrebs) \ 335 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 336 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 337 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 338 339 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 340 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 341 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 342 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 343 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 344 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 345 346 enum NvmePmrswtpShift { 347 PMRSWTP_PMRSWTU_SHIFT = 0, 348 PMRSWTP_PMRSWTV_SHIFT = 8, 349 }; 350 351 enum NvmePmrswtpMask { 352 PMRSWTP_PMRSWTU_MASK = 0xf, 353 PMRSWTP_PMRSWTV_MASK = 0xffffff, 354 }; 355 356 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 357 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 358 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 359 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 360 361 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 362 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 363 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 364 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 365 366 enum NvmePmrmscShift { 367 PMRMSC_CMSE_SHIFT = 1, 368 PMRMSC_CBA_SHIFT = 12, 369 }; 370 371 enum NvmePmrmscMask { 372 PMRMSC_CMSE_MASK = 0x1, 373 PMRMSC_CBA_MASK = 0xfffffffffffff, 374 }; 375 376 #define NVME_PMRMSC_CMSE(pmrmsc) \ 377 ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 378 #define NVME_PMRMSC_CBA(pmrmsc) \ 379 ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 380 381 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 382 (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 383 #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 384 (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 385 386 enum NvmeSglDescriptorType { 387 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 388 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 389 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 390 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 391 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 392 393 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 394 }; 395 396 enum NvmeSglDescriptorSubtype { 397 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 398 }; 399 400 typedef struct QEMU_PACKED NvmeSglDescriptor { 401 uint64_t addr; 402 uint32_t len; 403 uint8_t rsvd[3]; 404 uint8_t type; 405 } NvmeSglDescriptor; 406 407 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 408 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 409 410 typedef union NvmeCmdDptr { 411 struct { 412 uint64_t prp1; 413 uint64_t prp2; 414 }; 415 416 NvmeSglDescriptor sgl; 417 } NvmeCmdDptr; 418 419 enum NvmePsdt { 420 NVME_PSDT_PRP = 0x0, 421 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 422 NVME_PSDT_SGL_MPTR_SGL = 0x2, 423 }; 424 425 typedef struct QEMU_PACKED NvmeCmd { 426 uint8_t opcode; 427 uint8_t flags; 428 uint16_t cid; 429 uint32_t nsid; 430 uint64_t res1; 431 uint64_t mptr; 432 NvmeCmdDptr dptr; 433 uint32_t cdw10; 434 uint32_t cdw11; 435 uint32_t cdw12; 436 uint32_t cdw13; 437 uint32_t cdw14; 438 uint32_t cdw15; 439 } NvmeCmd; 440 441 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 442 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 443 444 enum NvmeAdminCommands { 445 NVME_ADM_CMD_DELETE_SQ = 0x00, 446 NVME_ADM_CMD_CREATE_SQ = 0x01, 447 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 448 NVME_ADM_CMD_DELETE_CQ = 0x04, 449 NVME_ADM_CMD_CREATE_CQ = 0x05, 450 NVME_ADM_CMD_IDENTIFY = 0x06, 451 NVME_ADM_CMD_ABORT = 0x08, 452 NVME_ADM_CMD_SET_FEATURES = 0x09, 453 NVME_ADM_CMD_GET_FEATURES = 0x0a, 454 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 455 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 456 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 457 NVME_ADM_CMD_FORMAT_NVM = 0x80, 458 NVME_ADM_CMD_SECURITY_SEND = 0x81, 459 NVME_ADM_CMD_SECURITY_RECV = 0x82, 460 }; 461 462 enum NvmeIoCommands { 463 NVME_CMD_FLUSH = 0x00, 464 NVME_CMD_WRITE = 0x01, 465 NVME_CMD_READ = 0x02, 466 NVME_CMD_WRITE_UNCOR = 0x04, 467 NVME_CMD_COMPARE = 0x05, 468 NVME_CMD_WRITE_ZEROES = 0x08, 469 NVME_CMD_DSM = 0x09, 470 }; 471 472 typedef struct QEMU_PACKED NvmeDeleteQ { 473 uint8_t opcode; 474 uint8_t flags; 475 uint16_t cid; 476 uint32_t rsvd1[9]; 477 uint16_t qid; 478 uint16_t rsvd10; 479 uint32_t rsvd11[5]; 480 } NvmeDeleteQ; 481 482 typedef struct QEMU_PACKED NvmeCreateCq { 483 uint8_t opcode; 484 uint8_t flags; 485 uint16_t cid; 486 uint32_t rsvd1[5]; 487 uint64_t prp1; 488 uint64_t rsvd8; 489 uint16_t cqid; 490 uint16_t qsize; 491 uint16_t cq_flags; 492 uint16_t irq_vector; 493 uint32_t rsvd12[4]; 494 } NvmeCreateCq; 495 496 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 497 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 498 499 typedef struct QEMU_PACKED NvmeCreateSq { 500 uint8_t opcode; 501 uint8_t flags; 502 uint16_t cid; 503 uint32_t rsvd1[5]; 504 uint64_t prp1; 505 uint64_t rsvd8; 506 uint16_t sqid; 507 uint16_t qsize; 508 uint16_t sq_flags; 509 uint16_t cqid; 510 uint32_t rsvd12[4]; 511 } NvmeCreateSq; 512 513 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 514 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 515 516 enum NvmeQueueFlags { 517 NVME_Q_PC = 1, 518 NVME_Q_PRIO_URGENT = 0, 519 NVME_Q_PRIO_HIGH = 1, 520 NVME_Q_PRIO_NORMAL = 2, 521 NVME_Q_PRIO_LOW = 3, 522 }; 523 524 typedef struct QEMU_PACKED NvmeIdentify { 525 uint8_t opcode; 526 uint8_t flags; 527 uint16_t cid; 528 uint32_t nsid; 529 uint64_t rsvd2[2]; 530 uint64_t prp1; 531 uint64_t prp2; 532 uint32_t cns; 533 uint32_t rsvd11[5]; 534 } NvmeIdentify; 535 536 typedef struct QEMU_PACKED NvmeRwCmd { 537 uint8_t opcode; 538 uint8_t flags; 539 uint16_t cid; 540 uint32_t nsid; 541 uint64_t rsvd2; 542 uint64_t mptr; 543 NvmeCmdDptr dptr; 544 uint64_t slba; 545 uint16_t nlb; 546 uint16_t control; 547 uint32_t dsmgmt; 548 uint32_t reftag; 549 uint16_t apptag; 550 uint16_t appmask; 551 } NvmeRwCmd; 552 553 enum { 554 NVME_RW_LR = 1 << 15, 555 NVME_RW_FUA = 1 << 14, 556 NVME_RW_DSM_FREQ_UNSPEC = 0, 557 NVME_RW_DSM_FREQ_TYPICAL = 1, 558 NVME_RW_DSM_FREQ_RARE = 2, 559 NVME_RW_DSM_FREQ_READS = 3, 560 NVME_RW_DSM_FREQ_WRITES = 4, 561 NVME_RW_DSM_FREQ_RW = 5, 562 NVME_RW_DSM_FREQ_ONCE = 6, 563 NVME_RW_DSM_FREQ_PREFETCH = 7, 564 NVME_RW_DSM_FREQ_TEMP = 8, 565 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 566 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 567 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 568 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 569 NVME_RW_DSM_SEQ_REQ = 1 << 6, 570 NVME_RW_DSM_COMPRESSED = 1 << 7, 571 NVME_RW_PRINFO_PRACT = 1 << 13, 572 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 573 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 574 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 575 }; 576 577 typedef struct QEMU_PACKED NvmeDsmCmd { 578 uint8_t opcode; 579 uint8_t flags; 580 uint16_t cid; 581 uint32_t nsid; 582 uint64_t rsvd2[2]; 583 NvmeCmdDptr dptr; 584 uint32_t nr; 585 uint32_t attributes; 586 uint32_t rsvd12[4]; 587 } NvmeDsmCmd; 588 589 enum { 590 NVME_DSMGMT_IDR = 1 << 0, 591 NVME_DSMGMT_IDW = 1 << 1, 592 NVME_DSMGMT_AD = 1 << 2, 593 }; 594 595 typedef struct QEMU_PACKED NvmeDsmRange { 596 uint32_t cattr; 597 uint32_t nlb; 598 uint64_t slba; 599 } NvmeDsmRange; 600 601 enum NvmeAsyncEventRequest { 602 NVME_AER_TYPE_ERROR = 0, 603 NVME_AER_TYPE_SMART = 1, 604 NVME_AER_TYPE_IO_SPECIFIC = 6, 605 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 606 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 607 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 608 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 609 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 610 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 611 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 612 NVME_AER_INFO_SMART_RELIABILITY = 0, 613 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 614 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 615 }; 616 617 typedef struct QEMU_PACKED NvmeAerResult { 618 uint8_t event_type; 619 uint8_t event_info; 620 uint8_t log_page; 621 uint8_t resv; 622 } NvmeAerResult; 623 624 typedef struct QEMU_PACKED NvmeCqe { 625 uint32_t result; 626 uint32_t rsvd; 627 uint16_t sq_head; 628 uint16_t sq_id; 629 uint16_t cid; 630 uint16_t status; 631 } NvmeCqe; 632 633 enum NvmeStatusCodes { 634 NVME_SUCCESS = 0x0000, 635 NVME_INVALID_OPCODE = 0x0001, 636 NVME_INVALID_FIELD = 0x0002, 637 NVME_CID_CONFLICT = 0x0003, 638 NVME_DATA_TRAS_ERROR = 0x0004, 639 NVME_POWER_LOSS_ABORT = 0x0005, 640 NVME_INTERNAL_DEV_ERROR = 0x0006, 641 NVME_CMD_ABORT_REQ = 0x0007, 642 NVME_CMD_ABORT_SQ_DEL = 0x0008, 643 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 644 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 645 NVME_INVALID_NSID = 0x000b, 646 NVME_CMD_SEQ_ERROR = 0x000c, 647 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 648 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 649 NVME_DATA_SGL_LEN_INVALID = 0x000f, 650 NVME_MD_SGL_LEN_INVALID = 0x0010, 651 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 652 NVME_INVALID_USE_OF_CMB = 0x0012, 653 NVME_LBA_RANGE = 0x0080, 654 NVME_CAP_EXCEEDED = 0x0081, 655 NVME_NS_NOT_READY = 0x0082, 656 NVME_NS_RESV_CONFLICT = 0x0083, 657 NVME_INVALID_CQID = 0x0100, 658 NVME_INVALID_QID = 0x0101, 659 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 660 NVME_ACL_EXCEEDED = 0x0103, 661 NVME_RESERVED = 0x0104, 662 NVME_AER_LIMIT_EXCEEDED = 0x0105, 663 NVME_INVALID_FW_SLOT = 0x0106, 664 NVME_INVALID_FW_IMAGE = 0x0107, 665 NVME_INVALID_IRQ_VECTOR = 0x0108, 666 NVME_INVALID_LOG_ID = 0x0109, 667 NVME_INVALID_FORMAT = 0x010a, 668 NVME_FW_REQ_RESET = 0x010b, 669 NVME_INVALID_QUEUE_DEL = 0x010c, 670 NVME_FID_NOT_SAVEABLE = 0x010d, 671 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 672 NVME_FEAT_NOT_NS_SPEC = 0x010f, 673 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 674 NVME_CONFLICTING_ATTRS = 0x0180, 675 NVME_INVALID_PROT_INFO = 0x0181, 676 NVME_WRITE_TO_RO = 0x0182, 677 NVME_WRITE_FAULT = 0x0280, 678 NVME_UNRECOVERED_READ = 0x0281, 679 NVME_E2E_GUARD_ERROR = 0x0282, 680 NVME_E2E_APP_ERROR = 0x0283, 681 NVME_E2E_REF_ERROR = 0x0284, 682 NVME_CMP_FAILURE = 0x0285, 683 NVME_ACCESS_DENIED = 0x0286, 684 NVME_MORE = 0x2000, 685 NVME_DNR = 0x4000, 686 NVME_NO_COMPLETE = 0xffff, 687 }; 688 689 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 690 uint8_t afi; 691 uint8_t reserved1[7]; 692 uint8_t frs1[8]; 693 uint8_t frs2[8]; 694 uint8_t frs3[8]; 695 uint8_t frs4[8]; 696 uint8_t frs5[8]; 697 uint8_t frs6[8]; 698 uint8_t frs7[8]; 699 uint8_t reserved2[448]; 700 } NvmeFwSlotInfoLog; 701 702 typedef struct QEMU_PACKED NvmeErrorLog { 703 uint64_t error_count; 704 uint16_t sqid; 705 uint16_t cid; 706 uint16_t status_field; 707 uint16_t param_error_location; 708 uint64_t lba; 709 uint32_t nsid; 710 uint8_t vs; 711 uint8_t resv[35]; 712 } NvmeErrorLog; 713 714 typedef struct QEMU_PACKED NvmeSmartLog { 715 uint8_t critical_warning; 716 uint16_t temperature; 717 uint8_t available_spare; 718 uint8_t available_spare_threshold; 719 uint8_t percentage_used; 720 uint8_t reserved1[26]; 721 uint64_t data_units_read[2]; 722 uint64_t data_units_written[2]; 723 uint64_t host_read_commands[2]; 724 uint64_t host_write_commands[2]; 725 uint64_t controller_busy_time[2]; 726 uint64_t power_cycles[2]; 727 uint64_t power_on_hours[2]; 728 uint64_t unsafe_shutdowns[2]; 729 uint64_t media_errors[2]; 730 uint64_t number_of_error_log_entries[2]; 731 uint8_t reserved2[320]; 732 } NvmeSmartLog; 733 734 enum NvmeSmartWarn { 735 NVME_SMART_SPARE = 1 << 0, 736 NVME_SMART_TEMPERATURE = 1 << 1, 737 NVME_SMART_RELIABILITY = 1 << 2, 738 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 739 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 740 }; 741 742 enum NvmeLogIdentifier { 743 NVME_LOG_ERROR_INFO = 0x01, 744 NVME_LOG_SMART_INFO = 0x02, 745 NVME_LOG_FW_SLOT_INFO = 0x03, 746 }; 747 748 typedef struct QEMU_PACKED NvmePSD { 749 uint16_t mp; 750 uint16_t reserved; 751 uint32_t enlat; 752 uint32_t exlat; 753 uint8_t rrt; 754 uint8_t rrl; 755 uint8_t rwt; 756 uint8_t rwl; 757 uint8_t resv[16]; 758 } NvmePSD; 759 760 #define NVME_IDENTIFY_DATA_SIZE 4096 761 762 enum { 763 NVME_ID_CNS_NS = 0x0, 764 NVME_ID_CNS_CTRL = 0x1, 765 NVME_ID_CNS_NS_ACTIVE_LIST = 0x2, 766 NVME_ID_CNS_NS_DESCR_LIST = 0x3, 767 }; 768 769 typedef struct QEMU_PACKED NvmeIdCtrl { 770 uint16_t vid; 771 uint16_t ssvid; 772 uint8_t sn[20]; 773 uint8_t mn[40]; 774 uint8_t fr[8]; 775 uint8_t rab; 776 uint8_t ieee[3]; 777 uint8_t cmic; 778 uint8_t mdts; 779 uint16_t cntlid; 780 uint32_t ver; 781 uint32_t rtd3r; 782 uint32_t rtd3e; 783 uint32_t oaes; 784 uint32_t ctratt; 785 uint8_t rsvd100[12]; 786 uint8_t fguid[16]; 787 uint8_t rsvd128[128]; 788 uint16_t oacs; 789 uint8_t acl; 790 uint8_t aerl; 791 uint8_t frmw; 792 uint8_t lpa; 793 uint8_t elpe; 794 uint8_t npss; 795 uint8_t avscc; 796 uint8_t apsta; 797 uint16_t wctemp; 798 uint16_t cctemp; 799 uint16_t mtfa; 800 uint32_t hmpre; 801 uint32_t hmmin; 802 uint8_t tnvmcap[16]; 803 uint8_t unvmcap[16]; 804 uint32_t rpmbs; 805 uint16_t edstt; 806 uint8_t dsto; 807 uint8_t fwug; 808 uint16_t kas; 809 uint16_t hctma; 810 uint16_t mntmt; 811 uint16_t mxtmt; 812 uint32_t sanicap; 813 uint8_t rsvd332[180]; 814 uint8_t sqes; 815 uint8_t cqes; 816 uint16_t maxcmd; 817 uint32_t nn; 818 uint16_t oncs; 819 uint16_t fuses; 820 uint8_t fna; 821 uint8_t vwc; 822 uint16_t awun; 823 uint16_t awupf; 824 uint8_t nvscc; 825 uint8_t rsvd531; 826 uint16_t acwu; 827 uint8_t rsvd534[2]; 828 uint32_t sgls; 829 uint8_t rsvd540[228]; 830 uint8_t subnqn[256]; 831 uint8_t rsvd1024[1024]; 832 NvmePSD psd[32]; 833 uint8_t vs[1024]; 834 } NvmeIdCtrl; 835 836 enum NvmeIdCtrlOacs { 837 NVME_OACS_SECURITY = 1 << 0, 838 NVME_OACS_FORMAT = 1 << 1, 839 NVME_OACS_FW = 1 << 2, 840 }; 841 842 enum NvmeIdCtrlOncs { 843 NVME_ONCS_COMPARE = 1 << 0, 844 NVME_ONCS_WRITE_UNCORR = 1 << 1, 845 NVME_ONCS_DSM = 1 << 2, 846 NVME_ONCS_WRITE_ZEROES = 1 << 3, 847 NVME_ONCS_FEATURES = 1 << 4, 848 NVME_ONCS_RESRVATIONS = 1 << 5, 849 NVME_ONCS_TIMESTAMP = 1 << 6, 850 }; 851 852 enum NvmeIdCtrlFrmw { 853 NVME_FRMW_SLOT1_RO = 1 << 0, 854 }; 855 856 enum NvmeIdCtrlLpa { 857 NVME_LPA_NS_SMART = 1 << 0, 858 NVME_LPA_EXTENDED = 1 << 2, 859 }; 860 861 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 862 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 863 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 864 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 865 866 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 867 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 868 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 869 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 870 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 871 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 872 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 873 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 874 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 875 876 #define NVME_ARB_AB(arb) (arb & 0x7) 877 #define NVME_ARB_AB_NOLIMIT 0x7 878 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 879 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 880 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 881 882 #define NVME_INTC_THR(intc) (intc & 0xff) 883 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 884 885 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 886 887 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 888 #define NVME_TEMP_THSEL_OVER 0x0 889 #define NVME_TEMP_THSEL_UNDER 0x1 890 891 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 892 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 893 894 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 895 896 #define NVME_AEC_SMART(aec) (aec & 0xff) 897 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 898 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 899 900 enum NvmeFeatureIds { 901 NVME_ARBITRATION = 0x1, 902 NVME_POWER_MANAGEMENT = 0x2, 903 NVME_LBA_RANGE_TYPE = 0x3, 904 NVME_TEMPERATURE_THRESHOLD = 0x4, 905 NVME_ERROR_RECOVERY = 0x5, 906 NVME_VOLATILE_WRITE_CACHE = 0x6, 907 NVME_NUMBER_OF_QUEUES = 0x7, 908 NVME_INTERRUPT_COALESCING = 0x8, 909 NVME_INTERRUPT_VECTOR_CONF = 0x9, 910 NVME_WRITE_ATOMICITY = 0xa, 911 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 912 NVME_TIMESTAMP = 0xe, 913 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 914 NVME_FID_MAX = 0x100, 915 }; 916 917 typedef enum NvmeFeatureCap { 918 NVME_FEAT_CAP_SAVE = 1 << 0, 919 NVME_FEAT_CAP_NS = 1 << 1, 920 NVME_FEAT_CAP_CHANGE = 1 << 2, 921 } NvmeFeatureCap; 922 923 typedef enum NvmeGetFeatureSelect { 924 NVME_GETFEAT_SELECT_CURRENT = 0x0, 925 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 926 NVME_GETFEAT_SELECT_SAVED = 0x2, 927 NVME_GETFEAT_SELECT_CAP = 0x3, 928 } NvmeGetFeatureSelect; 929 930 #define NVME_GETSETFEAT_FID_MASK 0xff 931 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 932 933 #define NVME_GETFEAT_SELECT_SHIFT 8 934 #define NVME_GETFEAT_SELECT_MASK 0x7 935 #define NVME_GETFEAT_SELECT(dw10) \ 936 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 937 938 #define NVME_SETFEAT_SAVE_SHIFT 31 939 #define NVME_SETFEAT_SAVE_MASK 0x1 940 #define NVME_SETFEAT_SAVE(dw10) \ 941 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 942 943 typedef struct QEMU_PACKED NvmeRangeType { 944 uint8_t type; 945 uint8_t attributes; 946 uint8_t rsvd2[14]; 947 uint64_t slba; 948 uint64_t nlb; 949 uint8_t guid[16]; 950 uint8_t rsvd48[16]; 951 } NvmeRangeType; 952 953 typedef struct QEMU_PACKED NvmeLBAF { 954 uint16_t ms; 955 uint8_t ds; 956 uint8_t rp; 957 } NvmeLBAF; 958 959 #define NVME_NSID_BROADCAST 0xffffffff 960 961 typedef struct QEMU_PACKED NvmeIdNs { 962 uint64_t nsze; 963 uint64_t ncap; 964 uint64_t nuse; 965 uint8_t nsfeat; 966 uint8_t nlbaf; 967 uint8_t flbas; 968 uint8_t mc; 969 uint8_t dpc; 970 uint8_t dps; 971 uint8_t nmic; 972 uint8_t rescap; 973 uint8_t fpi; 974 uint8_t dlfeat; 975 uint16_t nawun; 976 uint16_t nawupf; 977 uint16_t nacwu; 978 uint16_t nabsn; 979 uint16_t nabo; 980 uint16_t nabspf; 981 uint16_t noiob; 982 uint8_t nvmcap[16]; 983 uint8_t rsvd64[40]; 984 uint8_t nguid[16]; 985 uint64_t eui64; 986 NvmeLBAF lbaf[16]; 987 uint8_t rsvd192[192]; 988 uint8_t vs[3712]; 989 } NvmeIdNs; 990 991 typedef struct QEMU_PACKED NvmeIdNsDescr { 992 uint8_t nidt; 993 uint8_t nidl; 994 uint8_t rsvd2[2]; 995 } NvmeIdNsDescr; 996 997 enum { 998 NVME_NIDT_EUI64_LEN = 8, 999 NVME_NIDT_NGUID_LEN = 16, 1000 NVME_NIDT_UUID_LEN = 16, 1001 }; 1002 1003 enum NvmeNsIdentifierType { 1004 NVME_NIDT_EUI64 = 0x1, 1005 NVME_NIDT_NGUID = 0x2, 1006 NVME_NIDT_UUID = 0x3, 1007 }; 1008 1009 /*Deallocate Logical Block Features*/ 1010 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1011 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1012 1013 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1014 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1015 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1016 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1017 1018 1019 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1020 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1021 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1022 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1023 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1024 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1025 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1026 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1027 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1028 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1029 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1030 1031 enum NvmeIdNsDps { 1032 DPS_TYPE_NONE = 0, 1033 DPS_TYPE_1 = 1, 1034 DPS_TYPE_2 = 2, 1035 DPS_TYPE_3 = 3, 1036 DPS_TYPE_MASK = 0x7, 1037 DPS_FIRST_EIGHT = 8, 1038 }; 1039 1040 static inline void _nvme_check_size(void) 1041 { 1042 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1043 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1044 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1045 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1046 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1047 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1048 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1049 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1050 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1051 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1052 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1053 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1054 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1055 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1056 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1057 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1058 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1059 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1060 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1061 } 1062 #endif 1063