1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint32_t rsvd1; 11 uint32_t csts; 12 uint32_t nssrc; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint8_t padding[3520]; /* not used by QEMU */ 19 uint32_t pmrcap; 20 uint32_t pmrctl; 21 uint32_t pmrsts; 22 uint32_t pmrebs; 23 uint32_t pmrswtp; 24 uint64_t pmrmsc; 25 uint8_t reserved[484]; 26 } NvmeBar; 27 28 enum NvmeCapShift { 29 CAP_MQES_SHIFT = 0, 30 CAP_CQR_SHIFT = 16, 31 CAP_AMS_SHIFT = 17, 32 CAP_TO_SHIFT = 24, 33 CAP_DSTRD_SHIFT = 32, 34 CAP_NSSRS_SHIFT = 36, 35 CAP_CSS_SHIFT = 37, 36 CAP_MPSMIN_SHIFT = 48, 37 CAP_MPSMAX_SHIFT = 52, 38 CAP_PMR_SHIFT = 56, 39 }; 40 41 enum NvmeCapMask { 42 CAP_MQES_MASK = 0xffff, 43 CAP_CQR_MASK = 0x1, 44 CAP_AMS_MASK = 0x3, 45 CAP_TO_MASK = 0xff, 46 CAP_DSTRD_MASK = 0xf, 47 CAP_NSSRS_MASK = 0x1, 48 CAP_CSS_MASK = 0xff, 49 CAP_MPSMIN_MASK = 0xf, 50 CAP_MPSMAX_MASK = 0xf, 51 CAP_PMR_MASK = 0x1, 52 }; 53 54 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 55 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 56 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 57 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 58 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 59 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 60 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 61 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 62 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 63 64 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 65 << CAP_MQES_SHIFT) 66 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 67 << CAP_CQR_SHIFT) 68 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 69 << CAP_AMS_SHIFT) 70 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 71 << CAP_TO_SHIFT) 72 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 73 << CAP_DSTRD_SHIFT) 74 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 75 << CAP_NSSRS_SHIFT) 76 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 77 << CAP_CSS_SHIFT) 78 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 79 << CAP_MPSMIN_SHIFT) 80 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 81 << CAP_MPSMAX_SHIFT) 82 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ 83 << CAP_PMR_SHIFT) 84 85 enum NvmeCcShift { 86 CC_EN_SHIFT = 0, 87 CC_CSS_SHIFT = 4, 88 CC_MPS_SHIFT = 7, 89 CC_AMS_SHIFT = 11, 90 CC_SHN_SHIFT = 14, 91 CC_IOSQES_SHIFT = 16, 92 CC_IOCQES_SHIFT = 20, 93 }; 94 95 enum NvmeCcMask { 96 CC_EN_MASK = 0x1, 97 CC_CSS_MASK = 0x7, 98 CC_MPS_MASK = 0xf, 99 CC_AMS_MASK = 0x7, 100 CC_SHN_MASK = 0x3, 101 CC_IOSQES_MASK = 0xf, 102 CC_IOCQES_MASK = 0xf, 103 }; 104 105 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 106 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 107 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 108 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 109 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 110 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 111 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 112 113 enum NvmeCstsShift { 114 CSTS_RDY_SHIFT = 0, 115 CSTS_CFS_SHIFT = 1, 116 CSTS_SHST_SHIFT = 2, 117 CSTS_NSSRO_SHIFT = 4, 118 }; 119 120 enum NvmeCstsMask { 121 CSTS_RDY_MASK = 0x1, 122 CSTS_CFS_MASK = 0x1, 123 CSTS_SHST_MASK = 0x3, 124 CSTS_NSSRO_MASK = 0x1, 125 }; 126 127 enum NvmeCsts { 128 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 129 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 130 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 131 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 132 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 133 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 134 }; 135 136 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 137 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 138 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 139 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 140 141 enum NvmeAqaShift { 142 AQA_ASQS_SHIFT = 0, 143 AQA_ACQS_SHIFT = 16, 144 }; 145 146 enum NvmeAqaMask { 147 AQA_ASQS_MASK = 0xfff, 148 AQA_ACQS_MASK = 0xfff, 149 }; 150 151 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 152 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 153 154 enum NvmeCmblocShift { 155 CMBLOC_BIR_SHIFT = 0, 156 CMBLOC_OFST_SHIFT = 12, 157 }; 158 159 enum NvmeCmblocMask { 160 CMBLOC_BIR_MASK = 0x7, 161 CMBLOC_OFST_MASK = 0xfffff, 162 }; 163 164 #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ 165 CMBLOC_BIR_MASK) 166 #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ 167 CMBLOC_OFST_MASK) 168 169 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 170 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 171 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 172 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 173 174 enum NvmeCmbszShift { 175 CMBSZ_SQS_SHIFT = 0, 176 CMBSZ_CQS_SHIFT = 1, 177 CMBSZ_LISTS_SHIFT = 2, 178 CMBSZ_RDS_SHIFT = 3, 179 CMBSZ_WDS_SHIFT = 4, 180 CMBSZ_SZU_SHIFT = 8, 181 CMBSZ_SZ_SHIFT = 12, 182 }; 183 184 enum NvmeCmbszMask { 185 CMBSZ_SQS_MASK = 0x1, 186 CMBSZ_CQS_MASK = 0x1, 187 CMBSZ_LISTS_MASK = 0x1, 188 CMBSZ_RDS_MASK = 0x1, 189 CMBSZ_WDS_MASK = 0x1, 190 CMBSZ_SZU_MASK = 0xf, 191 CMBSZ_SZ_MASK = 0xfffff, 192 }; 193 194 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 195 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 196 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 197 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 198 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 199 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 200 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 201 202 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 203 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 204 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 205 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 206 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 207 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 208 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 209 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 210 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 211 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 212 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 213 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 214 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 215 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 216 217 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 218 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 219 220 enum NvmePmrcapShift { 221 PMRCAP_RDS_SHIFT = 3, 222 PMRCAP_WDS_SHIFT = 4, 223 PMRCAP_BIR_SHIFT = 5, 224 PMRCAP_PMRTU_SHIFT = 8, 225 PMRCAP_PMRWBM_SHIFT = 10, 226 PMRCAP_PMRTO_SHIFT = 16, 227 PMRCAP_CMSS_SHIFT = 24, 228 }; 229 230 enum NvmePmrcapMask { 231 PMRCAP_RDS_MASK = 0x1, 232 PMRCAP_WDS_MASK = 0x1, 233 PMRCAP_BIR_MASK = 0x7, 234 PMRCAP_PMRTU_MASK = 0x3, 235 PMRCAP_PMRWBM_MASK = 0xf, 236 PMRCAP_PMRTO_MASK = 0xff, 237 PMRCAP_CMSS_MASK = 0x1, 238 }; 239 240 #define NVME_PMRCAP_RDS(pmrcap) \ 241 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 242 #define NVME_PMRCAP_WDS(pmrcap) \ 243 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 244 #define NVME_PMRCAP_BIR(pmrcap) \ 245 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 246 #define NVME_PMRCAP_PMRTU(pmrcap) \ 247 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 248 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 249 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 250 #define NVME_PMRCAP_PMRTO(pmrcap) \ 251 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 252 #define NVME_PMRCAP_CMSS(pmrcap) \ 253 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 254 255 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 256 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 257 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 258 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 259 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 260 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 261 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 262 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 263 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 264 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 265 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 266 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 267 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 268 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 269 270 enum NvmePmrctlShift { 271 PMRCTL_EN_SHIFT = 0, 272 }; 273 274 enum NvmePmrctlMask { 275 PMRCTL_EN_MASK = 0x1, 276 }; 277 278 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 279 280 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 281 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 282 283 enum NvmePmrstsShift { 284 PMRSTS_ERR_SHIFT = 0, 285 PMRSTS_NRDY_SHIFT = 8, 286 PMRSTS_HSTS_SHIFT = 9, 287 PMRSTS_CBAI_SHIFT = 12, 288 }; 289 290 enum NvmePmrstsMask { 291 PMRSTS_ERR_MASK = 0xff, 292 PMRSTS_NRDY_MASK = 0x1, 293 PMRSTS_HSTS_MASK = 0x7, 294 PMRSTS_CBAI_MASK = 0x1, 295 }; 296 297 #define NVME_PMRSTS_ERR(pmrsts) \ 298 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 299 #define NVME_PMRSTS_NRDY(pmrsts) \ 300 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 301 #define NVME_PMRSTS_HSTS(pmrsts) \ 302 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 303 #define NVME_PMRSTS_CBAI(pmrsts) \ 304 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 305 306 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 307 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 308 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 309 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 310 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 311 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 312 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 313 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 314 315 enum NvmePmrebsShift { 316 PMREBS_PMRSZU_SHIFT = 0, 317 PMREBS_RBB_SHIFT = 4, 318 PMREBS_PMRWBZ_SHIFT = 8, 319 }; 320 321 enum NvmePmrebsMask { 322 PMREBS_PMRSZU_MASK = 0xf, 323 PMREBS_RBB_MASK = 0x1, 324 PMREBS_PMRWBZ_MASK = 0xffffff, 325 }; 326 327 #define NVME_PMREBS_PMRSZU(pmrebs) \ 328 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 329 #define NVME_PMREBS_RBB(pmrebs) \ 330 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 331 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 332 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 333 334 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 335 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 336 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 337 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 338 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 339 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 340 341 enum NvmePmrswtpShift { 342 PMRSWTP_PMRSWTU_SHIFT = 0, 343 PMRSWTP_PMRSWTV_SHIFT = 8, 344 }; 345 346 enum NvmePmrswtpMask { 347 PMRSWTP_PMRSWTU_MASK = 0xf, 348 PMRSWTP_PMRSWTV_MASK = 0xffffff, 349 }; 350 351 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 352 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 353 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 354 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 355 356 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 357 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 358 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 359 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 360 361 enum NvmePmrmscShift { 362 PMRMSC_CMSE_SHIFT = 1, 363 PMRMSC_CBA_SHIFT = 12, 364 }; 365 366 enum NvmePmrmscMask { 367 PMRMSC_CMSE_MASK = 0x1, 368 PMRMSC_CBA_MASK = 0xfffffffffffff, 369 }; 370 371 #define NVME_PMRMSC_CMSE(pmrmsc) \ 372 ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 373 #define NVME_PMRMSC_CBA(pmrmsc) \ 374 ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 375 376 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 377 (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 378 #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 379 (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 380 381 typedef struct QEMU_PACKED NvmeCmd { 382 uint8_t opcode; 383 uint8_t fuse; 384 uint16_t cid; 385 uint32_t nsid; 386 uint64_t res1; 387 uint64_t mptr; 388 uint64_t prp1; 389 uint64_t prp2; 390 uint32_t cdw10; 391 uint32_t cdw11; 392 uint32_t cdw12; 393 uint32_t cdw13; 394 uint32_t cdw14; 395 uint32_t cdw15; 396 } NvmeCmd; 397 398 enum NvmeAdminCommands { 399 NVME_ADM_CMD_DELETE_SQ = 0x00, 400 NVME_ADM_CMD_CREATE_SQ = 0x01, 401 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 402 NVME_ADM_CMD_DELETE_CQ = 0x04, 403 NVME_ADM_CMD_CREATE_CQ = 0x05, 404 NVME_ADM_CMD_IDENTIFY = 0x06, 405 NVME_ADM_CMD_ABORT = 0x08, 406 NVME_ADM_CMD_SET_FEATURES = 0x09, 407 NVME_ADM_CMD_GET_FEATURES = 0x0a, 408 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 409 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 410 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 411 NVME_ADM_CMD_FORMAT_NVM = 0x80, 412 NVME_ADM_CMD_SECURITY_SEND = 0x81, 413 NVME_ADM_CMD_SECURITY_RECV = 0x82, 414 }; 415 416 enum NvmeIoCommands { 417 NVME_CMD_FLUSH = 0x00, 418 NVME_CMD_WRITE = 0x01, 419 NVME_CMD_READ = 0x02, 420 NVME_CMD_WRITE_UNCOR = 0x04, 421 NVME_CMD_COMPARE = 0x05, 422 NVME_CMD_WRITE_ZEROS = 0x08, 423 NVME_CMD_DSM = 0x09, 424 }; 425 426 typedef struct QEMU_PACKED NvmeDeleteQ { 427 uint8_t opcode; 428 uint8_t flags; 429 uint16_t cid; 430 uint32_t rsvd1[9]; 431 uint16_t qid; 432 uint16_t rsvd10; 433 uint32_t rsvd11[5]; 434 } NvmeDeleteQ; 435 436 typedef struct QEMU_PACKED NvmeCreateCq { 437 uint8_t opcode; 438 uint8_t flags; 439 uint16_t cid; 440 uint32_t rsvd1[5]; 441 uint64_t prp1; 442 uint64_t rsvd8; 443 uint16_t cqid; 444 uint16_t qsize; 445 uint16_t cq_flags; 446 uint16_t irq_vector; 447 uint32_t rsvd12[4]; 448 } NvmeCreateCq; 449 450 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 451 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 452 453 typedef struct QEMU_PACKED NvmeCreateSq { 454 uint8_t opcode; 455 uint8_t flags; 456 uint16_t cid; 457 uint32_t rsvd1[5]; 458 uint64_t prp1; 459 uint64_t rsvd8; 460 uint16_t sqid; 461 uint16_t qsize; 462 uint16_t sq_flags; 463 uint16_t cqid; 464 uint32_t rsvd12[4]; 465 } NvmeCreateSq; 466 467 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 468 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 469 470 enum NvmeQueueFlags { 471 NVME_Q_PC = 1, 472 NVME_Q_PRIO_URGENT = 0, 473 NVME_Q_PRIO_HIGH = 1, 474 NVME_Q_PRIO_NORMAL = 2, 475 NVME_Q_PRIO_LOW = 3, 476 }; 477 478 typedef struct QEMU_PACKED NvmeIdentify { 479 uint8_t opcode; 480 uint8_t flags; 481 uint16_t cid; 482 uint32_t nsid; 483 uint64_t rsvd2[2]; 484 uint64_t prp1; 485 uint64_t prp2; 486 uint32_t cns; 487 uint32_t rsvd11[5]; 488 } NvmeIdentify; 489 490 typedef struct QEMU_PACKED NvmeRwCmd { 491 uint8_t opcode; 492 uint8_t flags; 493 uint16_t cid; 494 uint32_t nsid; 495 uint64_t rsvd2; 496 uint64_t mptr; 497 uint64_t prp1; 498 uint64_t prp2; 499 uint64_t slba; 500 uint16_t nlb; 501 uint16_t control; 502 uint32_t dsmgmt; 503 uint32_t reftag; 504 uint16_t apptag; 505 uint16_t appmask; 506 } NvmeRwCmd; 507 508 enum { 509 NVME_RW_LR = 1 << 15, 510 NVME_RW_FUA = 1 << 14, 511 NVME_RW_DSM_FREQ_UNSPEC = 0, 512 NVME_RW_DSM_FREQ_TYPICAL = 1, 513 NVME_RW_DSM_FREQ_RARE = 2, 514 NVME_RW_DSM_FREQ_READS = 3, 515 NVME_RW_DSM_FREQ_WRITES = 4, 516 NVME_RW_DSM_FREQ_RW = 5, 517 NVME_RW_DSM_FREQ_ONCE = 6, 518 NVME_RW_DSM_FREQ_PREFETCH = 7, 519 NVME_RW_DSM_FREQ_TEMP = 8, 520 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 521 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 522 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 523 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 524 NVME_RW_DSM_SEQ_REQ = 1 << 6, 525 NVME_RW_DSM_COMPRESSED = 1 << 7, 526 NVME_RW_PRINFO_PRACT = 1 << 13, 527 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 528 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 529 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 530 }; 531 532 typedef struct QEMU_PACKED NvmeDsmCmd { 533 uint8_t opcode; 534 uint8_t flags; 535 uint16_t cid; 536 uint32_t nsid; 537 uint64_t rsvd2[2]; 538 uint64_t prp1; 539 uint64_t prp2; 540 uint32_t nr; 541 uint32_t attributes; 542 uint32_t rsvd12[4]; 543 } NvmeDsmCmd; 544 545 enum { 546 NVME_DSMGMT_IDR = 1 << 0, 547 NVME_DSMGMT_IDW = 1 << 1, 548 NVME_DSMGMT_AD = 1 << 2, 549 }; 550 551 typedef struct QEMU_PACKED NvmeDsmRange { 552 uint32_t cattr; 553 uint32_t nlb; 554 uint64_t slba; 555 } NvmeDsmRange; 556 557 enum NvmeAsyncEventRequest { 558 NVME_AER_TYPE_ERROR = 0, 559 NVME_AER_TYPE_SMART = 1, 560 NVME_AER_TYPE_IO_SPECIFIC = 6, 561 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 562 NVME_AER_INFO_ERR_INVALID_SQ = 0, 563 NVME_AER_INFO_ERR_INVALID_DB = 1, 564 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 565 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 566 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 567 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 568 NVME_AER_INFO_SMART_RELIABILITY = 0, 569 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 570 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 571 }; 572 573 typedef struct QEMU_PACKED NvmeAerResult { 574 uint8_t event_type; 575 uint8_t event_info; 576 uint8_t log_page; 577 uint8_t resv; 578 } NvmeAerResult; 579 580 typedef struct QEMU_PACKED NvmeCqe { 581 uint32_t result; 582 uint32_t rsvd; 583 uint16_t sq_head; 584 uint16_t sq_id; 585 uint16_t cid; 586 uint16_t status; 587 } NvmeCqe; 588 589 enum NvmeStatusCodes { 590 NVME_SUCCESS = 0x0000, 591 NVME_INVALID_OPCODE = 0x0001, 592 NVME_INVALID_FIELD = 0x0002, 593 NVME_CID_CONFLICT = 0x0003, 594 NVME_DATA_TRAS_ERROR = 0x0004, 595 NVME_POWER_LOSS_ABORT = 0x0005, 596 NVME_INTERNAL_DEV_ERROR = 0x0006, 597 NVME_CMD_ABORT_REQ = 0x0007, 598 NVME_CMD_ABORT_SQ_DEL = 0x0008, 599 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 600 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 601 NVME_INVALID_NSID = 0x000b, 602 NVME_CMD_SEQ_ERROR = 0x000c, 603 NVME_LBA_RANGE = 0x0080, 604 NVME_CAP_EXCEEDED = 0x0081, 605 NVME_NS_NOT_READY = 0x0082, 606 NVME_NS_RESV_CONFLICT = 0x0083, 607 NVME_INVALID_CQID = 0x0100, 608 NVME_INVALID_QID = 0x0101, 609 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 610 NVME_ACL_EXCEEDED = 0x0103, 611 NVME_RESERVED = 0x0104, 612 NVME_AER_LIMIT_EXCEEDED = 0x0105, 613 NVME_INVALID_FW_SLOT = 0x0106, 614 NVME_INVALID_FW_IMAGE = 0x0107, 615 NVME_INVALID_IRQ_VECTOR = 0x0108, 616 NVME_INVALID_LOG_ID = 0x0109, 617 NVME_INVALID_FORMAT = 0x010a, 618 NVME_FW_REQ_RESET = 0x010b, 619 NVME_INVALID_QUEUE_DEL = 0x010c, 620 NVME_FID_NOT_SAVEABLE = 0x010d, 621 NVME_FID_NOT_NSID_SPEC = 0x010f, 622 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 623 NVME_CONFLICTING_ATTRS = 0x0180, 624 NVME_INVALID_PROT_INFO = 0x0181, 625 NVME_WRITE_TO_RO = 0x0182, 626 NVME_WRITE_FAULT = 0x0280, 627 NVME_UNRECOVERED_READ = 0x0281, 628 NVME_E2E_GUARD_ERROR = 0x0282, 629 NVME_E2E_APP_ERROR = 0x0283, 630 NVME_E2E_REF_ERROR = 0x0284, 631 NVME_CMP_FAILURE = 0x0285, 632 NVME_ACCESS_DENIED = 0x0286, 633 NVME_MORE = 0x2000, 634 NVME_DNR = 0x4000, 635 NVME_NO_COMPLETE = 0xffff, 636 }; 637 638 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 639 uint8_t afi; 640 uint8_t reserved1[7]; 641 uint8_t frs1[8]; 642 uint8_t frs2[8]; 643 uint8_t frs3[8]; 644 uint8_t frs4[8]; 645 uint8_t frs5[8]; 646 uint8_t frs6[8]; 647 uint8_t frs7[8]; 648 uint8_t reserved2[448]; 649 } NvmeFwSlotInfoLog; 650 651 typedef struct QEMU_PACKED NvmeErrorLog { 652 uint64_t error_count; 653 uint16_t sqid; 654 uint16_t cid; 655 uint16_t status_field; 656 uint16_t param_error_location; 657 uint64_t lba; 658 uint32_t nsid; 659 uint8_t vs; 660 uint8_t resv[35]; 661 } NvmeErrorLog; 662 663 typedef struct QEMU_PACKED NvmeSmartLog { 664 uint8_t critical_warning; 665 uint8_t temperature[2]; 666 uint8_t available_spare; 667 uint8_t available_spare_threshold; 668 uint8_t percentage_used; 669 uint8_t reserved1[26]; 670 uint64_t data_units_read[2]; 671 uint64_t data_units_written[2]; 672 uint64_t host_read_commands[2]; 673 uint64_t host_write_commands[2]; 674 uint64_t controller_busy_time[2]; 675 uint64_t power_cycles[2]; 676 uint64_t power_on_hours[2]; 677 uint64_t unsafe_shutdowns[2]; 678 uint64_t media_errors[2]; 679 uint64_t number_of_error_log_entries[2]; 680 uint8_t reserved2[320]; 681 } NvmeSmartLog; 682 683 enum NvmeSmartWarn { 684 NVME_SMART_SPARE = 1 << 0, 685 NVME_SMART_TEMPERATURE = 1 << 1, 686 NVME_SMART_RELIABILITY = 1 << 2, 687 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 688 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 689 }; 690 691 enum LogIdentifier { 692 NVME_LOG_ERROR_INFO = 0x01, 693 NVME_LOG_SMART_INFO = 0x02, 694 NVME_LOG_FW_SLOT_INFO = 0x03, 695 }; 696 697 typedef struct QEMU_PACKED NvmePSD { 698 uint16_t mp; 699 uint16_t reserved; 700 uint32_t enlat; 701 uint32_t exlat; 702 uint8_t rrt; 703 uint8_t rrl; 704 uint8_t rwt; 705 uint8_t rwl; 706 uint8_t resv[16]; 707 } NvmePSD; 708 709 #define NVME_IDENTIFY_DATA_SIZE 4096 710 711 enum { 712 NVME_ID_CNS_NS = 0x0, 713 NVME_ID_CNS_CTRL = 0x1, 714 NVME_ID_CNS_NS_ACTIVE_LIST = 0x2, 715 }; 716 717 typedef struct QEMU_PACKED NvmeIdCtrl { 718 uint16_t vid; 719 uint16_t ssvid; 720 uint8_t sn[20]; 721 uint8_t mn[40]; 722 uint8_t fr[8]; 723 uint8_t rab; 724 uint8_t ieee[3]; 725 uint8_t cmic; 726 uint8_t mdts; 727 uint8_t rsvd255[178]; 728 uint16_t oacs; 729 uint8_t acl; 730 uint8_t aerl; 731 uint8_t frmw; 732 uint8_t lpa; 733 uint8_t elpe; 734 uint8_t npss; 735 uint8_t rsvd511[248]; 736 uint8_t sqes; 737 uint8_t cqes; 738 uint16_t rsvd515; 739 uint32_t nn; 740 uint16_t oncs; 741 uint16_t fuses; 742 uint8_t fna; 743 uint8_t vwc; 744 uint16_t awun; 745 uint16_t awupf; 746 uint8_t rsvd703[174]; 747 uint8_t rsvd2047[1344]; 748 NvmePSD psd[32]; 749 uint8_t vs[1024]; 750 } NvmeIdCtrl; 751 752 enum NvmeIdCtrlOacs { 753 NVME_OACS_SECURITY = 1 << 0, 754 NVME_OACS_FORMAT = 1 << 1, 755 NVME_OACS_FW = 1 << 2, 756 }; 757 758 enum NvmeIdCtrlOncs { 759 NVME_ONCS_COMPARE = 1 << 0, 760 NVME_ONCS_WRITE_UNCORR = 1 << 1, 761 NVME_ONCS_DSM = 1 << 2, 762 NVME_ONCS_WRITE_ZEROS = 1 << 3, 763 NVME_ONCS_FEATURES = 1 << 4, 764 NVME_ONCS_RESRVATIONS = 1 << 5, 765 NVME_ONCS_TIMESTAMP = 1 << 6, 766 }; 767 768 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 769 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 770 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 771 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 772 773 typedef struct NvmeFeatureVal { 774 uint32_t arbitration; 775 uint32_t power_mgmt; 776 uint32_t temp_thresh; 777 uint32_t err_rec; 778 uint32_t volatile_wc; 779 uint32_t num_queues; 780 uint32_t int_coalescing; 781 uint32_t *int_vector_config; 782 uint32_t write_atomicity; 783 uint32_t async_config; 784 uint32_t sw_prog_marker; 785 } NvmeFeatureVal; 786 787 #define NVME_ARB_AB(arb) (arb & 0x7) 788 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 789 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 790 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 791 792 #define NVME_INTC_THR(intc) (intc & 0xff) 793 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 794 795 enum NvmeFeatureIds { 796 NVME_ARBITRATION = 0x1, 797 NVME_POWER_MANAGEMENT = 0x2, 798 NVME_LBA_RANGE_TYPE = 0x3, 799 NVME_TEMPERATURE_THRESHOLD = 0x4, 800 NVME_ERROR_RECOVERY = 0x5, 801 NVME_VOLATILE_WRITE_CACHE = 0x6, 802 NVME_NUMBER_OF_QUEUES = 0x7, 803 NVME_INTERRUPT_COALESCING = 0x8, 804 NVME_INTERRUPT_VECTOR_CONF = 0x9, 805 NVME_WRITE_ATOMICITY = 0xa, 806 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 807 NVME_TIMESTAMP = 0xe, 808 NVME_SOFTWARE_PROGRESS_MARKER = 0x80 809 }; 810 811 typedef struct QEMU_PACKED NvmeRangeType { 812 uint8_t type; 813 uint8_t attributes; 814 uint8_t rsvd2[14]; 815 uint64_t slba; 816 uint64_t nlb; 817 uint8_t guid[16]; 818 uint8_t rsvd48[16]; 819 } NvmeRangeType; 820 821 typedef struct QEMU_PACKED NvmeLBAF { 822 uint16_t ms; 823 uint8_t ds; 824 uint8_t rp; 825 } NvmeLBAF; 826 827 typedef struct QEMU_PACKED NvmeIdNs { 828 uint64_t nsze; 829 uint64_t ncap; 830 uint64_t nuse; 831 uint8_t nsfeat; 832 uint8_t nlbaf; 833 uint8_t flbas; 834 uint8_t mc; 835 uint8_t dpc; 836 uint8_t dps; 837 838 uint8_t nmic; 839 uint8_t rescap; 840 uint8_t fpi; 841 uint8_t dlfeat; 842 843 uint8_t res34[94]; 844 NvmeLBAF lbaf[16]; 845 uint8_t res192[192]; 846 uint8_t vs[3712]; 847 } NvmeIdNs; 848 849 850 /*Deallocate Logical Block Features*/ 851 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 852 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 853 854 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 855 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 856 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 857 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 858 859 860 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 861 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 862 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 863 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 864 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 865 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 866 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 867 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 868 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 869 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 870 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 871 872 enum NvmeIdNsDps { 873 DPS_TYPE_NONE = 0, 874 DPS_TYPE_1 = 1, 875 DPS_TYPE_2 = 2, 876 DPS_TYPE_3 = 3, 877 DPS_TYPE_MASK = 0x7, 878 DPS_FIRST_EIGHT = 8, 879 }; 880 881 static inline void _nvme_check_size(void) 882 { 883 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 884 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 885 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 886 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 887 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 888 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 889 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 890 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 891 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 892 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 893 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 894 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 895 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 896 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 897 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 898 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 899 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 900 } 901 #endif 902