1a3d9a352SFam Zheng #ifndef BLOCK_NVME_H 2a3d9a352SFam Zheng #define BLOCK_NVME_H 3a3d9a352SFam Zheng 4e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeBar { 5a3d9a352SFam Zheng uint64_t cap; 6a3d9a352SFam Zheng uint32_t vs; 7a3d9a352SFam Zheng uint32_t intms; 8a3d9a352SFam Zheng uint32_t intmc; 9a3d9a352SFam Zheng uint32_t cc; 10a3d9a352SFam Zheng uint32_t rsvd1; 11a3d9a352SFam Zheng uint32_t csts; 12a3d9a352SFam Zheng uint32_t nssrc; 13a3d9a352SFam Zheng uint32_t aqa; 14a3d9a352SFam Zheng uint64_t asq; 15a3d9a352SFam Zheng uint64_t acq; 16a3d9a352SFam Zheng uint32_t cmbloc; 17a3d9a352SFam Zheng uint32_t cmbsz; 186cf94132SAndrzej Jakowski uint8_t padding[3520]; /* not used by QEMU */ 196cf94132SAndrzej Jakowski uint32_t pmrcap; 206cf94132SAndrzej Jakowski uint32_t pmrctl; 216cf94132SAndrzej Jakowski uint32_t pmrsts; 226cf94132SAndrzej Jakowski uint32_t pmrebs; 236cf94132SAndrzej Jakowski uint32_t pmrswtp; 24af4a367dSPhilippe Mathieu-Daudé uint64_t pmrmsc; 25*74e18435SPhilippe Mathieu-Daudé uint8_t reserved[484]; 26a3d9a352SFam Zheng } NvmeBar; 27a3d9a352SFam Zheng 28a3d9a352SFam Zheng enum NvmeCapShift { 29a3d9a352SFam Zheng CAP_MQES_SHIFT = 0, 30a3d9a352SFam Zheng CAP_CQR_SHIFT = 16, 31a3d9a352SFam Zheng CAP_AMS_SHIFT = 17, 32a3d9a352SFam Zheng CAP_TO_SHIFT = 24, 33a3d9a352SFam Zheng CAP_DSTRD_SHIFT = 32, 34407d22ebSKlaus Jensen CAP_NSSRS_SHIFT = 36, 35a3d9a352SFam Zheng CAP_CSS_SHIFT = 37, 36a3d9a352SFam Zheng CAP_MPSMIN_SHIFT = 48, 37a3d9a352SFam Zheng CAP_MPSMAX_SHIFT = 52, 386cf94132SAndrzej Jakowski CAP_PMR_SHIFT = 56, 39a3d9a352SFam Zheng }; 40a3d9a352SFam Zheng 41a3d9a352SFam Zheng enum NvmeCapMask { 42a3d9a352SFam Zheng CAP_MQES_MASK = 0xffff, 43a3d9a352SFam Zheng CAP_CQR_MASK = 0x1, 44a3d9a352SFam Zheng CAP_AMS_MASK = 0x3, 45a3d9a352SFam Zheng CAP_TO_MASK = 0xff, 46a3d9a352SFam Zheng CAP_DSTRD_MASK = 0xf, 47a3d9a352SFam Zheng CAP_NSSRS_MASK = 0x1, 48a3d9a352SFam Zheng CAP_CSS_MASK = 0xff, 49a3d9a352SFam Zheng CAP_MPSMIN_MASK = 0xf, 50a3d9a352SFam Zheng CAP_MPSMAX_MASK = 0xf, 516cf94132SAndrzej Jakowski CAP_PMR_MASK = 0x1, 52a3d9a352SFam Zheng }; 53a3d9a352SFam Zheng 54a3d9a352SFam Zheng #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 55a3d9a352SFam Zheng #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 56a3d9a352SFam Zheng #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 57a3d9a352SFam Zheng #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 58a3d9a352SFam Zheng #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 59a3d9a352SFam Zheng #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 60a3d9a352SFam Zheng #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 61a3d9a352SFam Zheng #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 62a3d9a352SFam Zheng #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 63a3d9a352SFam Zheng 64a3d9a352SFam Zheng #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 65a3d9a352SFam Zheng << CAP_MQES_SHIFT) 66a3d9a352SFam Zheng #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 67a3d9a352SFam Zheng << CAP_CQR_SHIFT) 68a3d9a352SFam Zheng #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 69a3d9a352SFam Zheng << CAP_AMS_SHIFT) 70a3d9a352SFam Zheng #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 71a3d9a352SFam Zheng << CAP_TO_SHIFT) 72a3d9a352SFam Zheng #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 73a3d9a352SFam Zheng << CAP_DSTRD_SHIFT) 74a3d9a352SFam Zheng #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 75a3d9a352SFam Zheng << CAP_NSSRS_SHIFT) 76a3d9a352SFam Zheng #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 77a3d9a352SFam Zheng << CAP_CSS_SHIFT) 78a3d9a352SFam Zheng #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 79a3d9a352SFam Zheng << CAP_MPSMIN_SHIFT) 80a3d9a352SFam Zheng #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 81a3d9a352SFam Zheng << CAP_MPSMAX_SHIFT) 826cf94132SAndrzej Jakowski #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ 836cf94132SAndrzej Jakowski << CAP_PMR_SHIFT) 84a3d9a352SFam Zheng 85a3d9a352SFam Zheng enum NvmeCcShift { 86a3d9a352SFam Zheng CC_EN_SHIFT = 0, 87a3d9a352SFam Zheng CC_CSS_SHIFT = 4, 88a3d9a352SFam Zheng CC_MPS_SHIFT = 7, 89a3d9a352SFam Zheng CC_AMS_SHIFT = 11, 90a3d9a352SFam Zheng CC_SHN_SHIFT = 14, 91a3d9a352SFam Zheng CC_IOSQES_SHIFT = 16, 92a3d9a352SFam Zheng CC_IOCQES_SHIFT = 20, 93a3d9a352SFam Zheng }; 94a3d9a352SFam Zheng 95a3d9a352SFam Zheng enum NvmeCcMask { 96a3d9a352SFam Zheng CC_EN_MASK = 0x1, 97a3d9a352SFam Zheng CC_CSS_MASK = 0x7, 98a3d9a352SFam Zheng CC_MPS_MASK = 0xf, 99a3d9a352SFam Zheng CC_AMS_MASK = 0x7, 100a3d9a352SFam Zheng CC_SHN_MASK = 0x3, 101a3d9a352SFam Zheng CC_IOSQES_MASK = 0xf, 102a3d9a352SFam Zheng CC_IOCQES_MASK = 0xf, 103a3d9a352SFam Zheng }; 104a3d9a352SFam Zheng 105a3d9a352SFam Zheng #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 106a3d9a352SFam Zheng #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 107a3d9a352SFam Zheng #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 108a3d9a352SFam Zheng #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 109a3d9a352SFam Zheng #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 110a3d9a352SFam Zheng #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 111a3d9a352SFam Zheng #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 112a3d9a352SFam Zheng 113a3d9a352SFam Zheng enum NvmeCstsShift { 114a3d9a352SFam Zheng CSTS_RDY_SHIFT = 0, 115a3d9a352SFam Zheng CSTS_CFS_SHIFT = 1, 116a3d9a352SFam Zheng CSTS_SHST_SHIFT = 2, 117a3d9a352SFam Zheng CSTS_NSSRO_SHIFT = 4, 118a3d9a352SFam Zheng }; 119a3d9a352SFam Zheng 120a3d9a352SFam Zheng enum NvmeCstsMask { 121a3d9a352SFam Zheng CSTS_RDY_MASK = 0x1, 122a3d9a352SFam Zheng CSTS_CFS_MASK = 0x1, 123a3d9a352SFam Zheng CSTS_SHST_MASK = 0x3, 124a3d9a352SFam Zheng CSTS_NSSRO_MASK = 0x1, 125a3d9a352SFam Zheng }; 126a3d9a352SFam Zheng 127a3d9a352SFam Zheng enum NvmeCsts { 128a3d9a352SFam Zheng NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 129a3d9a352SFam Zheng NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 130a3d9a352SFam Zheng NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 131a3d9a352SFam Zheng NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 132a3d9a352SFam Zheng NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 133a3d9a352SFam Zheng NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 134a3d9a352SFam Zheng }; 135a3d9a352SFam Zheng 136a3d9a352SFam Zheng #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 137a3d9a352SFam Zheng #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 138a3d9a352SFam Zheng #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 139a3d9a352SFam Zheng #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 140a3d9a352SFam Zheng 141a3d9a352SFam Zheng enum NvmeAqaShift { 142a3d9a352SFam Zheng AQA_ASQS_SHIFT = 0, 143a3d9a352SFam Zheng AQA_ACQS_SHIFT = 16, 144a3d9a352SFam Zheng }; 145a3d9a352SFam Zheng 146a3d9a352SFam Zheng enum NvmeAqaMask { 147a3d9a352SFam Zheng AQA_ASQS_MASK = 0xfff, 148a3d9a352SFam Zheng AQA_ACQS_MASK = 0xfff, 149a3d9a352SFam Zheng }; 150a3d9a352SFam Zheng 151a3d9a352SFam Zheng #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 152a3d9a352SFam Zheng #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 153a3d9a352SFam Zheng 154a3d9a352SFam Zheng enum NvmeCmblocShift { 155a3d9a352SFam Zheng CMBLOC_BIR_SHIFT = 0, 156a3d9a352SFam Zheng CMBLOC_OFST_SHIFT = 12, 157a3d9a352SFam Zheng }; 158a3d9a352SFam Zheng 159a3d9a352SFam Zheng enum NvmeCmblocMask { 160a3d9a352SFam Zheng CMBLOC_BIR_MASK = 0x7, 161a3d9a352SFam Zheng CMBLOC_OFST_MASK = 0xfffff, 162a3d9a352SFam Zheng }; 163a3d9a352SFam Zheng 164a3d9a352SFam Zheng #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ 165a3d9a352SFam Zheng CMBLOC_BIR_MASK) 166a3d9a352SFam Zheng #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ 167a3d9a352SFam Zheng CMBLOC_OFST_MASK) 168a3d9a352SFam Zheng 169a3d9a352SFam Zheng #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 170a3d9a352SFam Zheng (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 171a3d9a352SFam Zheng #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 172a3d9a352SFam Zheng (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 173a3d9a352SFam Zheng 174a3d9a352SFam Zheng enum NvmeCmbszShift { 175a3d9a352SFam Zheng CMBSZ_SQS_SHIFT = 0, 176a3d9a352SFam Zheng CMBSZ_CQS_SHIFT = 1, 177a3d9a352SFam Zheng CMBSZ_LISTS_SHIFT = 2, 178a3d9a352SFam Zheng CMBSZ_RDS_SHIFT = 3, 179a3d9a352SFam Zheng CMBSZ_WDS_SHIFT = 4, 180a3d9a352SFam Zheng CMBSZ_SZU_SHIFT = 8, 181a3d9a352SFam Zheng CMBSZ_SZ_SHIFT = 12, 182a3d9a352SFam Zheng }; 183a3d9a352SFam Zheng 184a3d9a352SFam Zheng enum NvmeCmbszMask { 185a3d9a352SFam Zheng CMBSZ_SQS_MASK = 0x1, 186a3d9a352SFam Zheng CMBSZ_CQS_MASK = 0x1, 187a3d9a352SFam Zheng CMBSZ_LISTS_MASK = 0x1, 188a3d9a352SFam Zheng CMBSZ_RDS_MASK = 0x1, 189a3d9a352SFam Zheng CMBSZ_WDS_MASK = 0x1, 190a3d9a352SFam Zheng CMBSZ_SZU_MASK = 0xf, 191a3d9a352SFam Zheng CMBSZ_SZ_MASK = 0xfffff, 192a3d9a352SFam Zheng }; 193a3d9a352SFam Zheng 194a3d9a352SFam Zheng #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 195a3d9a352SFam Zheng #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 196a3d9a352SFam Zheng #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 197a3d9a352SFam Zheng #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 198a3d9a352SFam Zheng #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 199a3d9a352SFam Zheng #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 200a3d9a352SFam Zheng #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 201a3d9a352SFam Zheng 202a3d9a352SFam Zheng #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 203a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 204a3d9a352SFam Zheng #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 205a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 206a3d9a352SFam Zheng #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 207a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 208a3d9a352SFam Zheng #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 209a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 210a3d9a352SFam Zheng #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 211a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 212a3d9a352SFam Zheng #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 213a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 214a3d9a352SFam Zheng #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 215a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 216a3d9a352SFam Zheng 217a3d9a352SFam Zheng #define NVME_CMBSZ_GETSIZE(cmbsz) \ 218a3d9a352SFam Zheng (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 219a3d9a352SFam Zheng 2206cf94132SAndrzej Jakowski enum NvmePmrcapShift { 2216cf94132SAndrzej Jakowski PMRCAP_RDS_SHIFT = 3, 2226cf94132SAndrzej Jakowski PMRCAP_WDS_SHIFT = 4, 2236cf94132SAndrzej Jakowski PMRCAP_BIR_SHIFT = 5, 2246cf94132SAndrzej Jakowski PMRCAP_PMRTU_SHIFT = 8, 2256cf94132SAndrzej Jakowski PMRCAP_PMRWBM_SHIFT = 10, 2266cf94132SAndrzej Jakowski PMRCAP_PMRTO_SHIFT = 16, 2276cf94132SAndrzej Jakowski PMRCAP_CMSS_SHIFT = 24, 2286cf94132SAndrzej Jakowski }; 2296cf94132SAndrzej Jakowski 2306cf94132SAndrzej Jakowski enum NvmePmrcapMask { 2316cf94132SAndrzej Jakowski PMRCAP_RDS_MASK = 0x1, 2326cf94132SAndrzej Jakowski PMRCAP_WDS_MASK = 0x1, 2336cf94132SAndrzej Jakowski PMRCAP_BIR_MASK = 0x7, 2346cf94132SAndrzej Jakowski PMRCAP_PMRTU_MASK = 0x3, 2356cf94132SAndrzej Jakowski PMRCAP_PMRWBM_MASK = 0xf, 2366cf94132SAndrzej Jakowski PMRCAP_PMRTO_MASK = 0xff, 2376cf94132SAndrzej Jakowski PMRCAP_CMSS_MASK = 0x1, 2386cf94132SAndrzej Jakowski }; 2396cf94132SAndrzej Jakowski 2406cf94132SAndrzej Jakowski #define NVME_PMRCAP_RDS(pmrcap) \ 2416cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 2426cf94132SAndrzej Jakowski #define NVME_PMRCAP_WDS(pmrcap) \ 2436cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 2446cf94132SAndrzej Jakowski #define NVME_PMRCAP_BIR(pmrcap) \ 2456cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 2466cf94132SAndrzej Jakowski #define NVME_PMRCAP_PMRTU(pmrcap) \ 2476cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 2486cf94132SAndrzej Jakowski #define NVME_PMRCAP_PMRWBM(pmrcap) \ 2496cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 2506cf94132SAndrzej Jakowski #define NVME_PMRCAP_PMRTO(pmrcap) \ 2516cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 2526cf94132SAndrzej Jakowski #define NVME_PMRCAP_CMSS(pmrcap) \ 2536cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 2546cf94132SAndrzej Jakowski 2556cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 2566cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 2576cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 2586cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 2596cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 2606cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 2616cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 2626cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 2636cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 2646cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 2656cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 2666cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 2676cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 2686cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 2696cf94132SAndrzej Jakowski 2706cf94132SAndrzej Jakowski enum NvmePmrctlShift { 2716cf94132SAndrzej Jakowski PMRCTL_EN_SHIFT = 0, 2726cf94132SAndrzej Jakowski }; 2736cf94132SAndrzej Jakowski 2746cf94132SAndrzej Jakowski enum NvmePmrctlMask { 2756cf94132SAndrzej Jakowski PMRCTL_EN_MASK = 0x1, 2766cf94132SAndrzej Jakowski }; 2776cf94132SAndrzej Jakowski 2786cf94132SAndrzej Jakowski #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 2796cf94132SAndrzej Jakowski 2806cf94132SAndrzej Jakowski #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 2816cf94132SAndrzej Jakowski (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 2826cf94132SAndrzej Jakowski 2836cf94132SAndrzej Jakowski enum NvmePmrstsShift { 2846cf94132SAndrzej Jakowski PMRSTS_ERR_SHIFT = 0, 2856cf94132SAndrzej Jakowski PMRSTS_NRDY_SHIFT = 8, 2866cf94132SAndrzej Jakowski PMRSTS_HSTS_SHIFT = 9, 2876cf94132SAndrzej Jakowski PMRSTS_CBAI_SHIFT = 12, 2886cf94132SAndrzej Jakowski }; 2896cf94132SAndrzej Jakowski 2906cf94132SAndrzej Jakowski enum NvmePmrstsMask { 2916cf94132SAndrzej Jakowski PMRSTS_ERR_MASK = 0xff, 2926cf94132SAndrzej Jakowski PMRSTS_NRDY_MASK = 0x1, 2936cf94132SAndrzej Jakowski PMRSTS_HSTS_MASK = 0x7, 2946cf94132SAndrzej Jakowski PMRSTS_CBAI_MASK = 0x1, 2956cf94132SAndrzej Jakowski }; 2966cf94132SAndrzej Jakowski 2976cf94132SAndrzej Jakowski #define NVME_PMRSTS_ERR(pmrsts) \ 2986cf94132SAndrzej Jakowski ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 2996cf94132SAndrzej Jakowski #define NVME_PMRSTS_NRDY(pmrsts) \ 3006cf94132SAndrzej Jakowski ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 3016cf94132SAndrzej Jakowski #define NVME_PMRSTS_HSTS(pmrsts) \ 3026cf94132SAndrzej Jakowski ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 3036cf94132SAndrzej Jakowski #define NVME_PMRSTS_CBAI(pmrsts) \ 3046cf94132SAndrzej Jakowski ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 3056cf94132SAndrzej Jakowski 3066cf94132SAndrzej Jakowski #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 3076cf94132SAndrzej Jakowski (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 3086cf94132SAndrzej Jakowski #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 3096cf94132SAndrzej Jakowski (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 3106cf94132SAndrzej Jakowski #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 3116cf94132SAndrzej Jakowski (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 3126cf94132SAndrzej Jakowski #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 3136cf94132SAndrzej Jakowski (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 3146cf94132SAndrzej Jakowski 3156cf94132SAndrzej Jakowski enum NvmePmrebsShift { 3166cf94132SAndrzej Jakowski PMREBS_PMRSZU_SHIFT = 0, 3176cf94132SAndrzej Jakowski PMREBS_RBB_SHIFT = 4, 3186cf94132SAndrzej Jakowski PMREBS_PMRWBZ_SHIFT = 8, 3196cf94132SAndrzej Jakowski }; 3206cf94132SAndrzej Jakowski 3216cf94132SAndrzej Jakowski enum NvmePmrebsMask { 3226cf94132SAndrzej Jakowski PMREBS_PMRSZU_MASK = 0xf, 3236cf94132SAndrzej Jakowski PMREBS_RBB_MASK = 0x1, 3246cf94132SAndrzej Jakowski PMREBS_PMRWBZ_MASK = 0xffffff, 3256cf94132SAndrzej Jakowski }; 3266cf94132SAndrzej Jakowski 3276cf94132SAndrzej Jakowski #define NVME_PMREBS_PMRSZU(pmrebs) \ 3286cf94132SAndrzej Jakowski ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 3296cf94132SAndrzej Jakowski #define NVME_PMREBS_RBB(pmrebs) \ 3306cf94132SAndrzej Jakowski ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 3316cf94132SAndrzej Jakowski #define NVME_PMREBS_PMRWBZ(pmrebs) \ 3326cf94132SAndrzej Jakowski ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 3336cf94132SAndrzej Jakowski 3346cf94132SAndrzej Jakowski #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 3356cf94132SAndrzej Jakowski (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 3366cf94132SAndrzej Jakowski #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 3376cf94132SAndrzej Jakowski (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 3386cf94132SAndrzej Jakowski #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 3396cf94132SAndrzej Jakowski (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 3406cf94132SAndrzej Jakowski 3416cf94132SAndrzej Jakowski enum NvmePmrswtpShift { 3426cf94132SAndrzej Jakowski PMRSWTP_PMRSWTU_SHIFT = 0, 3436cf94132SAndrzej Jakowski PMRSWTP_PMRSWTV_SHIFT = 8, 3446cf94132SAndrzej Jakowski }; 3456cf94132SAndrzej Jakowski 3466cf94132SAndrzej Jakowski enum NvmePmrswtpMask { 3476cf94132SAndrzej Jakowski PMRSWTP_PMRSWTU_MASK = 0xf, 3486cf94132SAndrzej Jakowski PMRSWTP_PMRSWTV_MASK = 0xffffff, 3496cf94132SAndrzej Jakowski }; 3506cf94132SAndrzej Jakowski 3516cf94132SAndrzej Jakowski #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 3526cf94132SAndrzej Jakowski ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 3536cf94132SAndrzej Jakowski #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 3546cf94132SAndrzej Jakowski ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 3556cf94132SAndrzej Jakowski 3566cf94132SAndrzej Jakowski #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 3576cf94132SAndrzej Jakowski (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 3586cf94132SAndrzej Jakowski #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 3596cf94132SAndrzej Jakowski (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 3606cf94132SAndrzej Jakowski 3616cf94132SAndrzej Jakowski enum NvmePmrmscShift { 3626cf94132SAndrzej Jakowski PMRMSC_CMSE_SHIFT = 1, 3636cf94132SAndrzej Jakowski PMRMSC_CBA_SHIFT = 12, 3646cf94132SAndrzej Jakowski }; 3656cf94132SAndrzej Jakowski 3666cf94132SAndrzej Jakowski enum NvmePmrmscMask { 3676cf94132SAndrzej Jakowski PMRMSC_CMSE_MASK = 0x1, 3686cf94132SAndrzej Jakowski PMRMSC_CBA_MASK = 0xfffffffffffff, 3696cf94132SAndrzej Jakowski }; 3706cf94132SAndrzej Jakowski 3716cf94132SAndrzej Jakowski #define NVME_PMRMSC_CMSE(pmrmsc) \ 3726cf94132SAndrzej Jakowski ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 3736cf94132SAndrzej Jakowski #define NVME_PMRMSC_CBA(pmrmsc) \ 3746cf94132SAndrzej Jakowski ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 3756cf94132SAndrzej Jakowski 3766cf94132SAndrzej Jakowski #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 3776cf94132SAndrzej Jakowski (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 3786cf94132SAndrzej Jakowski #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 3796cf94132SAndrzej Jakowski (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 3806cf94132SAndrzej Jakowski 381e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeCmd { 382a3d9a352SFam Zheng uint8_t opcode; 383a3d9a352SFam Zheng uint8_t fuse; 384a3d9a352SFam Zheng uint16_t cid; 385a3d9a352SFam Zheng uint32_t nsid; 386a3d9a352SFam Zheng uint64_t res1; 387a3d9a352SFam Zheng uint64_t mptr; 388a3d9a352SFam Zheng uint64_t prp1; 389a3d9a352SFam Zheng uint64_t prp2; 390a3d9a352SFam Zheng uint32_t cdw10; 391a3d9a352SFam Zheng uint32_t cdw11; 392a3d9a352SFam Zheng uint32_t cdw12; 393a3d9a352SFam Zheng uint32_t cdw13; 394a3d9a352SFam Zheng uint32_t cdw14; 395a3d9a352SFam Zheng uint32_t cdw15; 396a3d9a352SFam Zheng } NvmeCmd; 397a3d9a352SFam Zheng 398a3d9a352SFam Zheng enum NvmeAdminCommands { 399a3d9a352SFam Zheng NVME_ADM_CMD_DELETE_SQ = 0x00, 400a3d9a352SFam Zheng NVME_ADM_CMD_CREATE_SQ = 0x01, 401a3d9a352SFam Zheng NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 402a3d9a352SFam Zheng NVME_ADM_CMD_DELETE_CQ = 0x04, 403a3d9a352SFam Zheng NVME_ADM_CMD_CREATE_CQ = 0x05, 404a3d9a352SFam Zheng NVME_ADM_CMD_IDENTIFY = 0x06, 405a3d9a352SFam Zheng NVME_ADM_CMD_ABORT = 0x08, 406a3d9a352SFam Zheng NVME_ADM_CMD_SET_FEATURES = 0x09, 407a3d9a352SFam Zheng NVME_ADM_CMD_GET_FEATURES = 0x0a, 408a3d9a352SFam Zheng NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 409a3d9a352SFam Zheng NVME_ADM_CMD_ACTIVATE_FW = 0x10, 410a3d9a352SFam Zheng NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 411a3d9a352SFam Zheng NVME_ADM_CMD_FORMAT_NVM = 0x80, 412a3d9a352SFam Zheng NVME_ADM_CMD_SECURITY_SEND = 0x81, 413a3d9a352SFam Zheng NVME_ADM_CMD_SECURITY_RECV = 0x82, 414a3d9a352SFam Zheng }; 415a3d9a352SFam Zheng 416a3d9a352SFam Zheng enum NvmeIoCommands { 417a3d9a352SFam Zheng NVME_CMD_FLUSH = 0x00, 418a3d9a352SFam Zheng NVME_CMD_WRITE = 0x01, 419a3d9a352SFam Zheng NVME_CMD_READ = 0x02, 420a3d9a352SFam Zheng NVME_CMD_WRITE_UNCOR = 0x04, 421a3d9a352SFam Zheng NVME_CMD_COMPARE = 0x05, 422a3d9a352SFam Zheng NVME_CMD_WRITE_ZEROS = 0x08, 423a3d9a352SFam Zheng NVME_CMD_DSM = 0x09, 424a3d9a352SFam Zheng }; 425a3d9a352SFam Zheng 426e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeDeleteQ { 427a3d9a352SFam Zheng uint8_t opcode; 428a3d9a352SFam Zheng uint8_t flags; 429a3d9a352SFam Zheng uint16_t cid; 430a3d9a352SFam Zheng uint32_t rsvd1[9]; 431a3d9a352SFam Zheng uint16_t qid; 432a3d9a352SFam Zheng uint16_t rsvd10; 433a3d9a352SFam Zheng uint32_t rsvd11[5]; 434a3d9a352SFam Zheng } NvmeDeleteQ; 435a3d9a352SFam Zheng 436e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeCreateCq { 437a3d9a352SFam Zheng uint8_t opcode; 438a3d9a352SFam Zheng uint8_t flags; 439a3d9a352SFam Zheng uint16_t cid; 440a3d9a352SFam Zheng uint32_t rsvd1[5]; 441a3d9a352SFam Zheng uint64_t prp1; 442a3d9a352SFam Zheng uint64_t rsvd8; 443a3d9a352SFam Zheng uint16_t cqid; 444a3d9a352SFam Zheng uint16_t qsize; 445a3d9a352SFam Zheng uint16_t cq_flags; 446a3d9a352SFam Zheng uint16_t irq_vector; 447a3d9a352SFam Zheng uint32_t rsvd12[4]; 448a3d9a352SFam Zheng } NvmeCreateCq; 449a3d9a352SFam Zheng 450a3d9a352SFam Zheng #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 451a3d9a352SFam Zheng #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 452a3d9a352SFam Zheng 453e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeCreateSq { 454a3d9a352SFam Zheng uint8_t opcode; 455a3d9a352SFam Zheng uint8_t flags; 456a3d9a352SFam Zheng uint16_t cid; 457a3d9a352SFam Zheng uint32_t rsvd1[5]; 458a3d9a352SFam Zheng uint64_t prp1; 459a3d9a352SFam Zheng uint64_t rsvd8; 460a3d9a352SFam Zheng uint16_t sqid; 461a3d9a352SFam Zheng uint16_t qsize; 462a3d9a352SFam Zheng uint16_t sq_flags; 463a3d9a352SFam Zheng uint16_t cqid; 464a3d9a352SFam Zheng uint32_t rsvd12[4]; 465a3d9a352SFam Zheng } NvmeCreateSq; 466a3d9a352SFam Zheng 467a3d9a352SFam Zheng #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 468a3d9a352SFam Zheng #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 469a3d9a352SFam Zheng 470a3d9a352SFam Zheng enum NvmeQueueFlags { 471a3d9a352SFam Zheng NVME_Q_PC = 1, 472a3d9a352SFam Zheng NVME_Q_PRIO_URGENT = 0, 473a3d9a352SFam Zheng NVME_Q_PRIO_HIGH = 1, 474a3d9a352SFam Zheng NVME_Q_PRIO_NORMAL = 2, 475a3d9a352SFam Zheng NVME_Q_PRIO_LOW = 3, 476a3d9a352SFam Zheng }; 477a3d9a352SFam Zheng 478e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeIdentify { 479a3d9a352SFam Zheng uint8_t opcode; 480a3d9a352SFam Zheng uint8_t flags; 481a3d9a352SFam Zheng uint16_t cid; 482a3d9a352SFam Zheng uint32_t nsid; 483a3d9a352SFam Zheng uint64_t rsvd2[2]; 484a3d9a352SFam Zheng uint64_t prp1; 485a3d9a352SFam Zheng uint64_t prp2; 486a3d9a352SFam Zheng uint32_t cns; 487a3d9a352SFam Zheng uint32_t rsvd11[5]; 488a3d9a352SFam Zheng } NvmeIdentify; 489a3d9a352SFam Zheng 490e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeRwCmd { 491a3d9a352SFam Zheng uint8_t opcode; 492a3d9a352SFam Zheng uint8_t flags; 493a3d9a352SFam Zheng uint16_t cid; 494a3d9a352SFam Zheng uint32_t nsid; 495a3d9a352SFam Zheng uint64_t rsvd2; 496a3d9a352SFam Zheng uint64_t mptr; 497a3d9a352SFam Zheng uint64_t prp1; 498a3d9a352SFam Zheng uint64_t prp2; 499a3d9a352SFam Zheng uint64_t slba; 500a3d9a352SFam Zheng uint16_t nlb; 501a3d9a352SFam Zheng uint16_t control; 502a3d9a352SFam Zheng uint32_t dsmgmt; 503a3d9a352SFam Zheng uint32_t reftag; 504a3d9a352SFam Zheng uint16_t apptag; 505a3d9a352SFam Zheng uint16_t appmask; 506a3d9a352SFam Zheng } NvmeRwCmd; 507a3d9a352SFam Zheng 508a3d9a352SFam Zheng enum { 509a3d9a352SFam Zheng NVME_RW_LR = 1 << 15, 510a3d9a352SFam Zheng NVME_RW_FUA = 1 << 14, 511a3d9a352SFam Zheng NVME_RW_DSM_FREQ_UNSPEC = 0, 512a3d9a352SFam Zheng NVME_RW_DSM_FREQ_TYPICAL = 1, 513a3d9a352SFam Zheng NVME_RW_DSM_FREQ_RARE = 2, 514a3d9a352SFam Zheng NVME_RW_DSM_FREQ_READS = 3, 515a3d9a352SFam Zheng NVME_RW_DSM_FREQ_WRITES = 4, 516a3d9a352SFam Zheng NVME_RW_DSM_FREQ_RW = 5, 517a3d9a352SFam Zheng NVME_RW_DSM_FREQ_ONCE = 6, 518a3d9a352SFam Zheng NVME_RW_DSM_FREQ_PREFETCH = 7, 519a3d9a352SFam Zheng NVME_RW_DSM_FREQ_TEMP = 8, 520a3d9a352SFam Zheng NVME_RW_DSM_LATENCY_NONE = 0 << 4, 521a3d9a352SFam Zheng NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 522a3d9a352SFam Zheng NVME_RW_DSM_LATENCY_NORM = 2 << 4, 523a3d9a352SFam Zheng NVME_RW_DSM_LATENCY_LOW = 3 << 4, 524a3d9a352SFam Zheng NVME_RW_DSM_SEQ_REQ = 1 << 6, 525a3d9a352SFam Zheng NVME_RW_DSM_COMPRESSED = 1 << 7, 526a3d9a352SFam Zheng NVME_RW_PRINFO_PRACT = 1 << 13, 527a3d9a352SFam Zheng NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 528a3d9a352SFam Zheng NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 529a3d9a352SFam Zheng NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 530a3d9a352SFam Zheng }; 531a3d9a352SFam Zheng 532e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeDsmCmd { 533a3d9a352SFam Zheng uint8_t opcode; 534a3d9a352SFam Zheng uint8_t flags; 535a3d9a352SFam Zheng uint16_t cid; 536a3d9a352SFam Zheng uint32_t nsid; 537a3d9a352SFam Zheng uint64_t rsvd2[2]; 538a3d9a352SFam Zheng uint64_t prp1; 539a3d9a352SFam Zheng uint64_t prp2; 540a3d9a352SFam Zheng uint32_t nr; 541a3d9a352SFam Zheng uint32_t attributes; 542a3d9a352SFam Zheng uint32_t rsvd12[4]; 543a3d9a352SFam Zheng } NvmeDsmCmd; 544a3d9a352SFam Zheng 545a3d9a352SFam Zheng enum { 546a3d9a352SFam Zheng NVME_DSMGMT_IDR = 1 << 0, 547a3d9a352SFam Zheng NVME_DSMGMT_IDW = 1 << 1, 548a3d9a352SFam Zheng NVME_DSMGMT_AD = 1 << 2, 549a3d9a352SFam Zheng }; 550a3d9a352SFam Zheng 551e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeDsmRange { 552a3d9a352SFam Zheng uint32_t cattr; 553a3d9a352SFam Zheng uint32_t nlb; 554a3d9a352SFam Zheng uint64_t slba; 555a3d9a352SFam Zheng } NvmeDsmRange; 556a3d9a352SFam Zheng 557a3d9a352SFam Zheng enum NvmeAsyncEventRequest { 558a3d9a352SFam Zheng NVME_AER_TYPE_ERROR = 0, 559a3d9a352SFam Zheng NVME_AER_TYPE_SMART = 1, 560a3d9a352SFam Zheng NVME_AER_TYPE_IO_SPECIFIC = 6, 561a3d9a352SFam Zheng NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 562a3d9a352SFam Zheng NVME_AER_INFO_ERR_INVALID_SQ = 0, 563a3d9a352SFam Zheng NVME_AER_INFO_ERR_INVALID_DB = 1, 564a3d9a352SFam Zheng NVME_AER_INFO_ERR_DIAG_FAIL = 2, 565a3d9a352SFam Zheng NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 566a3d9a352SFam Zheng NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 567a3d9a352SFam Zheng NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 568a3d9a352SFam Zheng NVME_AER_INFO_SMART_RELIABILITY = 0, 569a3d9a352SFam Zheng NVME_AER_INFO_SMART_TEMP_THRESH = 1, 570a3d9a352SFam Zheng NVME_AER_INFO_SMART_SPARE_THRESH = 2, 571a3d9a352SFam Zheng }; 572a3d9a352SFam Zheng 573e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeAerResult { 574a3d9a352SFam Zheng uint8_t event_type; 575a3d9a352SFam Zheng uint8_t event_info; 576a3d9a352SFam Zheng uint8_t log_page; 577a3d9a352SFam Zheng uint8_t resv; 578a3d9a352SFam Zheng } NvmeAerResult; 579a3d9a352SFam Zheng 580e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeCqe { 581a3d9a352SFam Zheng uint32_t result; 582a3d9a352SFam Zheng uint32_t rsvd; 583a3d9a352SFam Zheng uint16_t sq_head; 584a3d9a352SFam Zheng uint16_t sq_id; 585a3d9a352SFam Zheng uint16_t cid; 586a3d9a352SFam Zheng uint16_t status; 587a3d9a352SFam Zheng } NvmeCqe; 588a3d9a352SFam Zheng 589a3d9a352SFam Zheng enum NvmeStatusCodes { 590a3d9a352SFam Zheng NVME_SUCCESS = 0x0000, 591a3d9a352SFam Zheng NVME_INVALID_OPCODE = 0x0001, 592a3d9a352SFam Zheng NVME_INVALID_FIELD = 0x0002, 593a3d9a352SFam Zheng NVME_CID_CONFLICT = 0x0003, 594a3d9a352SFam Zheng NVME_DATA_TRAS_ERROR = 0x0004, 595a3d9a352SFam Zheng NVME_POWER_LOSS_ABORT = 0x0005, 596a3d9a352SFam Zheng NVME_INTERNAL_DEV_ERROR = 0x0006, 597a3d9a352SFam Zheng NVME_CMD_ABORT_REQ = 0x0007, 598a3d9a352SFam Zheng NVME_CMD_ABORT_SQ_DEL = 0x0008, 599a3d9a352SFam Zheng NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 600a3d9a352SFam Zheng NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 601a3d9a352SFam Zheng NVME_INVALID_NSID = 0x000b, 602a3d9a352SFam Zheng NVME_CMD_SEQ_ERROR = 0x000c, 603a3d9a352SFam Zheng NVME_LBA_RANGE = 0x0080, 604a3d9a352SFam Zheng NVME_CAP_EXCEEDED = 0x0081, 605a3d9a352SFam Zheng NVME_NS_NOT_READY = 0x0082, 606a3d9a352SFam Zheng NVME_NS_RESV_CONFLICT = 0x0083, 607a3d9a352SFam Zheng NVME_INVALID_CQID = 0x0100, 608a3d9a352SFam Zheng NVME_INVALID_QID = 0x0101, 609a3d9a352SFam Zheng NVME_MAX_QSIZE_EXCEEDED = 0x0102, 610a3d9a352SFam Zheng NVME_ACL_EXCEEDED = 0x0103, 611a3d9a352SFam Zheng NVME_RESERVED = 0x0104, 612a3d9a352SFam Zheng NVME_AER_LIMIT_EXCEEDED = 0x0105, 613a3d9a352SFam Zheng NVME_INVALID_FW_SLOT = 0x0106, 614a3d9a352SFam Zheng NVME_INVALID_FW_IMAGE = 0x0107, 615a3d9a352SFam Zheng NVME_INVALID_IRQ_VECTOR = 0x0108, 616a3d9a352SFam Zheng NVME_INVALID_LOG_ID = 0x0109, 617a3d9a352SFam Zheng NVME_INVALID_FORMAT = 0x010a, 618a3d9a352SFam Zheng NVME_FW_REQ_RESET = 0x010b, 619a3d9a352SFam Zheng NVME_INVALID_QUEUE_DEL = 0x010c, 620a3d9a352SFam Zheng NVME_FID_NOT_SAVEABLE = 0x010d, 621a3d9a352SFam Zheng NVME_FID_NOT_NSID_SPEC = 0x010f, 622a3d9a352SFam Zheng NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 623a3d9a352SFam Zheng NVME_CONFLICTING_ATTRS = 0x0180, 624a3d9a352SFam Zheng NVME_INVALID_PROT_INFO = 0x0181, 625a3d9a352SFam Zheng NVME_WRITE_TO_RO = 0x0182, 626a3d9a352SFam Zheng NVME_WRITE_FAULT = 0x0280, 627a3d9a352SFam Zheng NVME_UNRECOVERED_READ = 0x0281, 628a3d9a352SFam Zheng NVME_E2E_GUARD_ERROR = 0x0282, 629a3d9a352SFam Zheng NVME_E2E_APP_ERROR = 0x0283, 630a3d9a352SFam Zheng NVME_E2E_REF_ERROR = 0x0284, 631a3d9a352SFam Zheng NVME_CMP_FAILURE = 0x0285, 632a3d9a352SFam Zheng NVME_ACCESS_DENIED = 0x0286, 633a3d9a352SFam Zheng NVME_MORE = 0x2000, 634a3d9a352SFam Zheng NVME_DNR = 0x4000, 635a3d9a352SFam Zheng NVME_NO_COMPLETE = 0xffff, 636a3d9a352SFam Zheng }; 637a3d9a352SFam Zheng 638e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 639a3d9a352SFam Zheng uint8_t afi; 640a3d9a352SFam Zheng uint8_t reserved1[7]; 641a3d9a352SFam Zheng uint8_t frs1[8]; 642a3d9a352SFam Zheng uint8_t frs2[8]; 643a3d9a352SFam Zheng uint8_t frs3[8]; 644a3d9a352SFam Zheng uint8_t frs4[8]; 645a3d9a352SFam Zheng uint8_t frs5[8]; 646a3d9a352SFam Zheng uint8_t frs6[8]; 647a3d9a352SFam Zheng uint8_t frs7[8]; 648a3d9a352SFam Zheng uint8_t reserved2[448]; 649a3d9a352SFam Zheng } NvmeFwSlotInfoLog; 650a3d9a352SFam Zheng 651e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeErrorLog { 652a3d9a352SFam Zheng uint64_t error_count; 653a3d9a352SFam Zheng uint16_t sqid; 654a3d9a352SFam Zheng uint16_t cid; 655a3d9a352SFam Zheng uint16_t status_field; 656a3d9a352SFam Zheng uint16_t param_error_location; 657a3d9a352SFam Zheng uint64_t lba; 658a3d9a352SFam Zheng uint32_t nsid; 659a3d9a352SFam Zheng uint8_t vs; 660a3d9a352SFam Zheng uint8_t resv[35]; 661a3d9a352SFam Zheng } NvmeErrorLog; 662a3d9a352SFam Zheng 663e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeSmartLog { 664a3d9a352SFam Zheng uint8_t critical_warning; 665a3d9a352SFam Zheng uint8_t temperature[2]; 666a3d9a352SFam Zheng uint8_t available_spare; 667a3d9a352SFam Zheng uint8_t available_spare_threshold; 668a3d9a352SFam Zheng uint8_t percentage_used; 669a3d9a352SFam Zheng uint8_t reserved1[26]; 670a3d9a352SFam Zheng uint64_t data_units_read[2]; 671a3d9a352SFam Zheng uint64_t data_units_written[2]; 672a3d9a352SFam Zheng uint64_t host_read_commands[2]; 673a3d9a352SFam Zheng uint64_t host_write_commands[2]; 674a3d9a352SFam Zheng uint64_t controller_busy_time[2]; 675a3d9a352SFam Zheng uint64_t power_cycles[2]; 676a3d9a352SFam Zheng uint64_t power_on_hours[2]; 677a3d9a352SFam Zheng uint64_t unsafe_shutdowns[2]; 678a3d9a352SFam Zheng uint64_t media_errors[2]; 679a3d9a352SFam Zheng uint64_t number_of_error_log_entries[2]; 680a3d9a352SFam Zheng uint8_t reserved2[320]; 681a3d9a352SFam Zheng } NvmeSmartLog; 682a3d9a352SFam Zheng 683a3d9a352SFam Zheng enum NvmeSmartWarn { 684a3d9a352SFam Zheng NVME_SMART_SPARE = 1 << 0, 685a3d9a352SFam Zheng NVME_SMART_TEMPERATURE = 1 << 1, 686a3d9a352SFam Zheng NVME_SMART_RELIABILITY = 1 << 2, 687a3d9a352SFam Zheng NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 688a3d9a352SFam Zheng NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 689a3d9a352SFam Zheng }; 690a3d9a352SFam Zheng 691a3d9a352SFam Zheng enum LogIdentifier { 692a3d9a352SFam Zheng NVME_LOG_ERROR_INFO = 0x01, 693a3d9a352SFam Zheng NVME_LOG_SMART_INFO = 0x02, 694a3d9a352SFam Zheng NVME_LOG_FW_SLOT_INFO = 0x03, 695a3d9a352SFam Zheng }; 696a3d9a352SFam Zheng 697e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmePSD { 698a3d9a352SFam Zheng uint16_t mp; 699a3d9a352SFam Zheng uint16_t reserved; 700a3d9a352SFam Zheng uint32_t enlat; 701a3d9a352SFam Zheng uint32_t exlat; 702a3d9a352SFam Zheng uint8_t rrt; 703a3d9a352SFam Zheng uint8_t rrl; 704a3d9a352SFam Zheng uint8_t rwt; 705a3d9a352SFam Zheng uint8_t rwl; 706a3d9a352SFam Zheng uint8_t resv[16]; 707a3d9a352SFam Zheng } NvmePSD; 708a3d9a352SFam Zheng 7093e829fd4SKlaus Jensen #define NVME_IDENTIFY_DATA_SIZE 4096 7103e829fd4SKlaus Jensen 7113e829fd4SKlaus Jensen enum { 7123e829fd4SKlaus Jensen NVME_ID_CNS_NS = 0x0, 7133e829fd4SKlaus Jensen NVME_ID_CNS_CTRL = 0x1, 7143e829fd4SKlaus Jensen NVME_ID_CNS_NS_ACTIVE_LIST = 0x2, 7153e829fd4SKlaus Jensen }; 7163e829fd4SKlaus Jensen 717e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeIdCtrl { 718a3d9a352SFam Zheng uint16_t vid; 719a3d9a352SFam Zheng uint16_t ssvid; 720a3d9a352SFam Zheng uint8_t sn[20]; 721a3d9a352SFam Zheng uint8_t mn[40]; 722a3d9a352SFam Zheng uint8_t fr[8]; 723a3d9a352SFam Zheng uint8_t rab; 724a3d9a352SFam Zheng uint8_t ieee[3]; 725a3d9a352SFam Zheng uint8_t cmic; 726a3d9a352SFam Zheng uint8_t mdts; 727a3d9a352SFam Zheng uint8_t rsvd255[178]; 728a3d9a352SFam Zheng uint16_t oacs; 729a3d9a352SFam Zheng uint8_t acl; 730a3d9a352SFam Zheng uint8_t aerl; 731a3d9a352SFam Zheng uint8_t frmw; 732a3d9a352SFam Zheng uint8_t lpa; 733a3d9a352SFam Zheng uint8_t elpe; 734a3d9a352SFam Zheng uint8_t npss; 735a3d9a352SFam Zheng uint8_t rsvd511[248]; 736a3d9a352SFam Zheng uint8_t sqes; 737a3d9a352SFam Zheng uint8_t cqes; 738a3d9a352SFam Zheng uint16_t rsvd515; 739a3d9a352SFam Zheng uint32_t nn; 740a3d9a352SFam Zheng uint16_t oncs; 741a3d9a352SFam Zheng uint16_t fuses; 742a3d9a352SFam Zheng uint8_t fna; 743a3d9a352SFam Zheng uint8_t vwc; 744a3d9a352SFam Zheng uint16_t awun; 745a3d9a352SFam Zheng uint16_t awupf; 746a3d9a352SFam Zheng uint8_t rsvd703[174]; 747a3d9a352SFam Zheng uint8_t rsvd2047[1344]; 748a3d9a352SFam Zheng NvmePSD psd[32]; 749a3d9a352SFam Zheng uint8_t vs[1024]; 750a3d9a352SFam Zheng } NvmeIdCtrl; 751a3d9a352SFam Zheng 752a3d9a352SFam Zheng enum NvmeIdCtrlOacs { 753a3d9a352SFam Zheng NVME_OACS_SECURITY = 1 << 0, 754a3d9a352SFam Zheng NVME_OACS_FORMAT = 1 << 1, 755a3d9a352SFam Zheng NVME_OACS_FW = 1 << 2, 756a3d9a352SFam Zheng }; 757a3d9a352SFam Zheng 758a3d9a352SFam Zheng enum NvmeIdCtrlOncs { 759a3d9a352SFam Zheng NVME_ONCS_COMPARE = 1 << 0, 760a3d9a352SFam Zheng NVME_ONCS_WRITE_UNCORR = 1 << 1, 761a3d9a352SFam Zheng NVME_ONCS_DSM = 1 << 2, 762a3d9a352SFam Zheng NVME_ONCS_WRITE_ZEROS = 1 << 3, 763a3d9a352SFam Zheng NVME_ONCS_FEATURES = 1 << 4, 764a3d9a352SFam Zheng NVME_ONCS_RESRVATIONS = 1 << 5, 7653036a626SKenneth Heitke NVME_ONCS_TIMESTAMP = 1 << 6, 766a3d9a352SFam Zheng }; 767a3d9a352SFam Zheng 768a3d9a352SFam Zheng #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 769a3d9a352SFam Zheng #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 770a3d9a352SFam Zheng #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 771a3d9a352SFam Zheng #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 772a3d9a352SFam Zheng 773a3d9a352SFam Zheng typedef struct NvmeFeatureVal { 774a3d9a352SFam Zheng uint32_t arbitration; 775a3d9a352SFam Zheng uint32_t power_mgmt; 776a3d9a352SFam Zheng uint32_t temp_thresh; 777a3d9a352SFam Zheng uint32_t err_rec; 778a3d9a352SFam Zheng uint32_t volatile_wc; 779a3d9a352SFam Zheng uint32_t num_queues; 780a3d9a352SFam Zheng uint32_t int_coalescing; 781a3d9a352SFam Zheng uint32_t *int_vector_config; 782a3d9a352SFam Zheng uint32_t write_atomicity; 783a3d9a352SFam Zheng uint32_t async_config; 784a3d9a352SFam Zheng uint32_t sw_prog_marker; 785a3d9a352SFam Zheng } NvmeFeatureVal; 786a3d9a352SFam Zheng 787a3d9a352SFam Zheng #define NVME_ARB_AB(arb) (arb & 0x7) 788a3d9a352SFam Zheng #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 789a3d9a352SFam Zheng #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 790a3d9a352SFam Zheng #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 791a3d9a352SFam Zheng 792a3d9a352SFam Zheng #define NVME_INTC_THR(intc) (intc & 0xff) 793a3d9a352SFam Zheng #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 794a3d9a352SFam Zheng 795a3d9a352SFam Zheng enum NvmeFeatureIds { 796a3d9a352SFam Zheng NVME_ARBITRATION = 0x1, 797a3d9a352SFam Zheng NVME_POWER_MANAGEMENT = 0x2, 798a3d9a352SFam Zheng NVME_LBA_RANGE_TYPE = 0x3, 799a3d9a352SFam Zheng NVME_TEMPERATURE_THRESHOLD = 0x4, 800a3d9a352SFam Zheng NVME_ERROR_RECOVERY = 0x5, 801a3d9a352SFam Zheng NVME_VOLATILE_WRITE_CACHE = 0x6, 802a3d9a352SFam Zheng NVME_NUMBER_OF_QUEUES = 0x7, 803a3d9a352SFam Zheng NVME_INTERRUPT_COALESCING = 0x8, 804a3d9a352SFam Zheng NVME_INTERRUPT_VECTOR_CONF = 0x9, 805a3d9a352SFam Zheng NVME_WRITE_ATOMICITY = 0xa, 806a3d9a352SFam Zheng NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 8073036a626SKenneth Heitke NVME_TIMESTAMP = 0xe, 808a3d9a352SFam Zheng NVME_SOFTWARE_PROGRESS_MARKER = 0x80 809a3d9a352SFam Zheng }; 810a3d9a352SFam Zheng 811e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeRangeType { 812a3d9a352SFam Zheng uint8_t type; 813a3d9a352SFam Zheng uint8_t attributes; 814a3d9a352SFam Zheng uint8_t rsvd2[14]; 815a3d9a352SFam Zheng uint64_t slba; 816a3d9a352SFam Zheng uint64_t nlb; 817a3d9a352SFam Zheng uint8_t guid[16]; 818a3d9a352SFam Zheng uint8_t rsvd48[16]; 819a3d9a352SFam Zheng } NvmeRangeType; 820a3d9a352SFam Zheng 821e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeLBAF { 822a3d9a352SFam Zheng uint16_t ms; 823a3d9a352SFam Zheng uint8_t ds; 824a3d9a352SFam Zheng uint8_t rp; 825a3d9a352SFam Zheng } NvmeLBAF; 826a3d9a352SFam Zheng 827e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeIdNs { 828a3d9a352SFam Zheng uint64_t nsze; 829a3d9a352SFam Zheng uint64_t ncap; 830a3d9a352SFam Zheng uint64_t nuse; 831a3d9a352SFam Zheng uint8_t nsfeat; 832a3d9a352SFam Zheng uint8_t nlbaf; 833a3d9a352SFam Zheng uint8_t flbas; 834a3d9a352SFam Zheng uint8_t mc; 835a3d9a352SFam Zheng uint8_t dpc; 836a3d9a352SFam Zheng uint8_t dps; 837e0dd95e3SMaxim Levitsky 838e0dd95e3SMaxim Levitsky uint8_t nmic; 839e0dd95e3SMaxim Levitsky uint8_t rescap; 840e0dd95e3SMaxim Levitsky uint8_t fpi; 841e0dd95e3SMaxim Levitsky uint8_t dlfeat; 842e0dd95e3SMaxim Levitsky 843e0dd95e3SMaxim Levitsky uint8_t res34[94]; 844a3d9a352SFam Zheng NvmeLBAF lbaf[16]; 845a3d9a352SFam Zheng uint8_t res192[192]; 846a3d9a352SFam Zheng uint8_t vs[3712]; 847a3d9a352SFam Zheng } NvmeIdNs; 848a3d9a352SFam Zheng 849e0dd95e3SMaxim Levitsky 850e0dd95e3SMaxim Levitsky /*Deallocate Logical Block Features*/ 851e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 852e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 853e0dd95e3SMaxim Levitsky 854e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 855e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 856e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 857e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 858e0dd95e3SMaxim Levitsky 859e0dd95e3SMaxim Levitsky 860a3d9a352SFam Zheng #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 861a3d9a352SFam Zheng #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 862a3d9a352SFam Zheng #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 863a3d9a352SFam Zheng #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 864a3d9a352SFam Zheng #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 865a3d9a352SFam Zheng #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 866a3d9a352SFam Zheng #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 867a3d9a352SFam Zheng #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 868a3d9a352SFam Zheng #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 869a3d9a352SFam Zheng #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 870a3d9a352SFam Zheng #define NVME_ID_NS_DPC_TYPE_MASK 0x7 871a3d9a352SFam Zheng 872a3d9a352SFam Zheng enum NvmeIdNsDps { 873a3d9a352SFam Zheng DPS_TYPE_NONE = 0, 874a3d9a352SFam Zheng DPS_TYPE_1 = 1, 875a3d9a352SFam Zheng DPS_TYPE_2 = 2, 876a3d9a352SFam Zheng DPS_TYPE_3 = 3, 877a3d9a352SFam Zheng DPS_TYPE_MASK = 0x7, 878a3d9a352SFam Zheng DPS_FIRST_EIGHT = 8, 879a3d9a352SFam Zheng }; 880a3d9a352SFam Zheng 881a3d9a352SFam Zheng static inline void _nvme_check_size(void) 882a3d9a352SFam Zheng { 883*74e18435SPhilippe Mathieu-Daudé QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 884a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 885a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 886a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 887a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 888a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 889a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 890a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 891a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 892a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 893a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 894a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 895a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 896a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 897a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 898a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 899a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 900a3d9a352SFam Zheng } 901a3d9a352SFam Zheng #endif 902