1a3d9a352SFam Zheng #ifndef BLOCK_NVME_H 2a3d9a352SFam Zheng #define BLOCK_NVME_H 3a3d9a352SFam Zheng 4e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeBar { 5a3d9a352SFam Zheng uint64_t cap; 6a3d9a352SFam Zheng uint32_t vs; 7a3d9a352SFam Zheng uint32_t intms; 8a3d9a352SFam Zheng uint32_t intmc; 9a3d9a352SFam Zheng uint32_t cc; 109a31c615SGollu Appalanaidu uint8_t rsvd24[4]; 11a3d9a352SFam Zheng uint32_t csts; 12a3d9a352SFam Zheng uint32_t nssrc; 13a3d9a352SFam Zheng uint32_t aqa; 14a3d9a352SFam Zheng uint64_t asq; 15a3d9a352SFam Zheng uint64_t acq; 16a3d9a352SFam Zheng uint32_t cmbloc; 17a3d9a352SFam Zheng uint32_t cmbsz; 18f4319477SPadmakar Kalghatgi uint32_t bpinfo; 19f4319477SPadmakar Kalghatgi uint32_t bprsel; 20f4319477SPadmakar Kalghatgi uint64_t bpmbl; 21f4319477SPadmakar Kalghatgi uint64_t cmbmsc; 22f4319477SPadmakar Kalghatgi uint32_t cmbsts; 23f4319477SPadmakar Kalghatgi uint8_t rsvd92[3492]; 246cf94132SAndrzej Jakowski uint32_t pmrcap; 256cf94132SAndrzej Jakowski uint32_t pmrctl; 266cf94132SAndrzej Jakowski uint32_t pmrsts; 276cf94132SAndrzej Jakowski uint32_t pmrebs; 286cf94132SAndrzej Jakowski uint32_t pmrswtp; 29af4a367dSPhilippe Mathieu-Daudé uint64_t pmrmsc; 30f4319477SPadmakar Kalghatgi uint8_t css[484]; 31a3d9a352SFam Zheng } NvmeBar; 32a3d9a352SFam Zheng 33a3d9a352SFam Zheng enum NvmeCapShift { 34a3d9a352SFam Zheng CAP_MQES_SHIFT = 0, 35a3d9a352SFam Zheng CAP_CQR_SHIFT = 16, 36a3d9a352SFam Zheng CAP_AMS_SHIFT = 17, 37a3d9a352SFam Zheng CAP_TO_SHIFT = 24, 38a3d9a352SFam Zheng CAP_DSTRD_SHIFT = 32, 39407d22ebSKlaus Jensen CAP_NSSRS_SHIFT = 36, 40a3d9a352SFam Zheng CAP_CSS_SHIFT = 37, 41a3d9a352SFam Zheng CAP_MPSMIN_SHIFT = 48, 42a3d9a352SFam Zheng CAP_MPSMAX_SHIFT = 52, 438e9e8b48SKlaus Jensen CAP_PMRS_SHIFT = 56, 448e9e8b48SKlaus Jensen CAP_CMBS_SHIFT = 57, 45a3d9a352SFam Zheng }; 46a3d9a352SFam Zheng 47a3d9a352SFam Zheng enum NvmeCapMask { 48a3d9a352SFam Zheng CAP_MQES_MASK = 0xffff, 49a3d9a352SFam Zheng CAP_CQR_MASK = 0x1, 50a3d9a352SFam Zheng CAP_AMS_MASK = 0x3, 51a3d9a352SFam Zheng CAP_TO_MASK = 0xff, 52a3d9a352SFam Zheng CAP_DSTRD_MASK = 0xf, 53a3d9a352SFam Zheng CAP_NSSRS_MASK = 0x1, 54a3d9a352SFam Zheng CAP_CSS_MASK = 0xff, 55a3d9a352SFam Zheng CAP_MPSMIN_MASK = 0xf, 56a3d9a352SFam Zheng CAP_MPSMAX_MASK = 0xf, 578e9e8b48SKlaus Jensen CAP_PMRS_MASK = 0x1, 588e9e8b48SKlaus Jensen CAP_CMBS_MASK = 0x1, 59a3d9a352SFam Zheng }; 60a3d9a352SFam Zheng 61a3d9a352SFam Zheng #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 62a3d9a352SFam Zheng #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 63a3d9a352SFam Zheng #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 64a3d9a352SFam Zheng #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 65a3d9a352SFam Zheng #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 66a3d9a352SFam Zheng #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 67a3d9a352SFam Zheng #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 68a3d9a352SFam Zheng #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 69a3d9a352SFam Zheng #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 708e9e8b48SKlaus Jensen #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) 71f4319477SPadmakar Kalghatgi #define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK) 72a3d9a352SFam Zheng 73a3d9a352SFam Zheng #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 74a3d9a352SFam Zheng << CAP_MQES_SHIFT) 75a3d9a352SFam Zheng #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 76a3d9a352SFam Zheng << CAP_CQR_SHIFT) 77a3d9a352SFam Zheng #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 78a3d9a352SFam Zheng << CAP_AMS_SHIFT) 79a3d9a352SFam Zheng #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 80a3d9a352SFam Zheng << CAP_TO_SHIFT) 81a3d9a352SFam Zheng #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 82a3d9a352SFam Zheng << CAP_DSTRD_SHIFT) 83a3d9a352SFam Zheng #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 84a3d9a352SFam Zheng << CAP_NSSRS_SHIFT) 85a3d9a352SFam Zheng #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 86a3d9a352SFam Zheng << CAP_CSS_SHIFT) 87a3d9a352SFam Zheng #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 88a3d9a352SFam Zheng << CAP_MPSMIN_SHIFT) 89a3d9a352SFam Zheng #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 90a3d9a352SFam Zheng << CAP_MPSMAX_SHIFT) 918e9e8b48SKlaus Jensen #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMRS_MASK) \ 928e9e8b48SKlaus Jensen << CAP_PMRS_SHIFT) 938e9e8b48SKlaus Jensen #define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMBS_MASK) \ 948e9e8b48SKlaus Jensen << CAP_CMBS_SHIFT) 95a3d9a352SFam Zheng 96492f9a8dSKeith Busch enum NvmeCapCss { 97492f9a8dSKeith Busch NVME_CAP_CSS_NVM = 1 << 0, 98141354d5SNiklas Cassel NVME_CAP_CSS_CSI_SUPP = 1 << 6, 998c5cea85SKeith Busch NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 100492f9a8dSKeith Busch }; 101492f9a8dSKeith Busch 102a3d9a352SFam Zheng enum NvmeCcShift { 103a3d9a352SFam Zheng CC_EN_SHIFT = 0, 104a3d9a352SFam Zheng CC_CSS_SHIFT = 4, 105a3d9a352SFam Zheng CC_MPS_SHIFT = 7, 106a3d9a352SFam Zheng CC_AMS_SHIFT = 11, 107a3d9a352SFam Zheng CC_SHN_SHIFT = 14, 108a3d9a352SFam Zheng CC_IOSQES_SHIFT = 16, 109a3d9a352SFam Zheng CC_IOCQES_SHIFT = 20, 110a3d9a352SFam Zheng }; 111a3d9a352SFam Zheng 112a3d9a352SFam Zheng enum NvmeCcMask { 113a3d9a352SFam Zheng CC_EN_MASK = 0x1, 114a3d9a352SFam Zheng CC_CSS_MASK = 0x7, 115a3d9a352SFam Zheng CC_MPS_MASK = 0xf, 116a3d9a352SFam Zheng CC_AMS_MASK = 0x7, 117a3d9a352SFam Zheng CC_SHN_MASK = 0x3, 118a3d9a352SFam Zheng CC_IOSQES_MASK = 0xf, 119a3d9a352SFam Zheng CC_IOCQES_MASK = 0xf, 120a3d9a352SFam Zheng }; 121a3d9a352SFam Zheng 122a3d9a352SFam Zheng #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 123a3d9a352SFam Zheng #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 124a3d9a352SFam Zheng #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 125a3d9a352SFam Zheng #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 126a3d9a352SFam Zheng #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 127a3d9a352SFam Zheng #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 128a3d9a352SFam Zheng #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 129a3d9a352SFam Zheng 1301b48e461SKlaus Jensen enum NvmeCcCss { 1311b48e461SKlaus Jensen NVME_CC_CSS_NVM = 0x0, 132141354d5SNiklas Cassel NVME_CC_CSS_CSI = 0x6, 1331b48e461SKlaus Jensen NVME_CC_CSS_ADMIN_ONLY = 0x7, 1341b48e461SKlaus Jensen }; 1351b48e461SKlaus Jensen 136141354d5SNiklas Cassel #define NVME_SET_CC_EN(cc, val) \ 137141354d5SNiklas Cassel (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) 138141354d5SNiklas Cassel #define NVME_SET_CC_CSS(cc, val) \ 139141354d5SNiklas Cassel (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) 140141354d5SNiklas Cassel #define NVME_SET_CC_MPS(cc, val) \ 141141354d5SNiklas Cassel (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) 142141354d5SNiklas Cassel #define NVME_SET_CC_AMS(cc, val) \ 143141354d5SNiklas Cassel (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) 144141354d5SNiklas Cassel #define NVME_SET_CC_SHN(cc, val) \ 145141354d5SNiklas Cassel (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) 146141354d5SNiklas Cassel #define NVME_SET_CC_IOSQES(cc, val) \ 147141354d5SNiklas Cassel (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) 148141354d5SNiklas Cassel #define NVME_SET_CC_IOCQES(cc, val) \ 149141354d5SNiklas Cassel (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) 150141354d5SNiklas Cassel 151a3d9a352SFam Zheng enum NvmeCstsShift { 152a3d9a352SFam Zheng CSTS_RDY_SHIFT = 0, 153a3d9a352SFam Zheng CSTS_CFS_SHIFT = 1, 154a3d9a352SFam Zheng CSTS_SHST_SHIFT = 2, 155a3d9a352SFam Zheng CSTS_NSSRO_SHIFT = 4, 156a3d9a352SFam Zheng }; 157a3d9a352SFam Zheng 158a3d9a352SFam Zheng enum NvmeCstsMask { 159a3d9a352SFam Zheng CSTS_RDY_MASK = 0x1, 160a3d9a352SFam Zheng CSTS_CFS_MASK = 0x1, 161a3d9a352SFam Zheng CSTS_SHST_MASK = 0x3, 162a3d9a352SFam Zheng CSTS_NSSRO_MASK = 0x1, 163a3d9a352SFam Zheng }; 164a3d9a352SFam Zheng 165a3d9a352SFam Zheng enum NvmeCsts { 166a3d9a352SFam Zheng NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 167a3d9a352SFam Zheng NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 168a3d9a352SFam Zheng NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 169a3d9a352SFam Zheng NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 170a3d9a352SFam Zheng NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 171a3d9a352SFam Zheng NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 172a3d9a352SFam Zheng }; 173a3d9a352SFam Zheng 174a3d9a352SFam Zheng #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 175a3d9a352SFam Zheng #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 176a3d9a352SFam Zheng #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 177a3d9a352SFam Zheng #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 178a3d9a352SFam Zheng 179a3d9a352SFam Zheng enum NvmeAqaShift { 180a3d9a352SFam Zheng AQA_ASQS_SHIFT = 0, 181a3d9a352SFam Zheng AQA_ACQS_SHIFT = 16, 182a3d9a352SFam Zheng }; 183a3d9a352SFam Zheng 184a3d9a352SFam Zheng enum NvmeAqaMask { 185a3d9a352SFam Zheng AQA_ASQS_MASK = 0xfff, 186a3d9a352SFam Zheng AQA_ACQS_MASK = 0xfff, 187a3d9a352SFam Zheng }; 188a3d9a352SFam Zheng 189a3d9a352SFam Zheng #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 190a3d9a352SFam Zheng #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 191a3d9a352SFam Zheng 192a3d9a352SFam Zheng enum NvmeCmblocShift { 193a3d9a352SFam Zheng CMBLOC_BIR_SHIFT = 0, 194f4319477SPadmakar Kalghatgi CMBLOC_CQMMS_SHIFT = 3, 195f4319477SPadmakar Kalghatgi CMBLOC_CQPDS_SHIFT = 4, 196f4319477SPadmakar Kalghatgi CMBLOC_CDPMLS_SHIFT = 5, 197f4319477SPadmakar Kalghatgi CMBLOC_CDPCILS_SHIFT = 6, 198f4319477SPadmakar Kalghatgi CMBLOC_CDMMMS_SHIFT = 7, 199f4319477SPadmakar Kalghatgi CMBLOC_CQDA_SHIFT = 8, 200a3d9a352SFam Zheng CMBLOC_OFST_SHIFT = 12, 201a3d9a352SFam Zheng }; 202a3d9a352SFam Zheng 203a3d9a352SFam Zheng enum NvmeCmblocMask { 204a3d9a352SFam Zheng CMBLOC_BIR_MASK = 0x7, 205f4319477SPadmakar Kalghatgi CMBLOC_CQMMS_MASK = 0x1, 206f4319477SPadmakar Kalghatgi CMBLOC_CQPDS_MASK = 0x1, 207f4319477SPadmakar Kalghatgi CMBLOC_CDPMLS_MASK = 0x1, 208f4319477SPadmakar Kalghatgi CMBLOC_CDPCILS_MASK = 0x1, 209f4319477SPadmakar Kalghatgi CMBLOC_CDMMMS_MASK = 0x1, 210f4319477SPadmakar Kalghatgi CMBLOC_CQDA_MASK = 0x1, 211a3d9a352SFam Zheng CMBLOC_OFST_MASK = 0xfffff, 212a3d9a352SFam Zheng }; 213a3d9a352SFam Zheng 214f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_BIR(cmbloc) \ 215f4319477SPadmakar Kalghatgi ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK) 216f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_CQMMS(cmbloc) \ 217f4319477SPadmakar Kalghatgi ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK) 218f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_CQPDS(cmbloc) \ 219f4319477SPadmakar Kalghatgi ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK) 220f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_CDPMLS(cmbloc) \ 221f4319477SPadmakar Kalghatgi ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK) 222f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_CDPCILS(cmbloc) \ 223f4319477SPadmakar Kalghatgi ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK) 224f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_CDMMMS(cmbloc) \ 225f4319477SPadmakar Kalghatgi ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK) 226f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_CQDA(cmbloc) \ 227f4319477SPadmakar Kalghatgi ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK) 228f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_OFST(cmbloc) \ 229f4319477SPadmakar Kalghatgi ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK) 230a3d9a352SFam Zheng 231a3d9a352SFam Zheng #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 232a3d9a352SFam Zheng (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 233f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \ 234f4319477SPadmakar Kalghatgi (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT) 235f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \ 236f4319477SPadmakar Kalghatgi (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT) 237f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \ 238f4319477SPadmakar Kalghatgi (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT) 239f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \ 240f4319477SPadmakar Kalghatgi (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT) 241f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \ 242f4319477SPadmakar Kalghatgi (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT) 243f4319477SPadmakar Kalghatgi #define NVME_CMBLOC_SET_CQDA(cmbloc, val) \ 244f4319477SPadmakar Kalghatgi (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT) 245a3d9a352SFam Zheng #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 246a3d9a352SFam Zheng (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 247a3d9a352SFam Zheng 248f4319477SPadmakar Kalghatgi #define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \ 249f4319477SPadmakar Kalghatgi (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT) 250f4319477SPadmakar Kalghatgi 251a3d9a352SFam Zheng enum NvmeCmbszShift { 252a3d9a352SFam Zheng CMBSZ_SQS_SHIFT = 0, 253a3d9a352SFam Zheng CMBSZ_CQS_SHIFT = 1, 254a3d9a352SFam Zheng CMBSZ_LISTS_SHIFT = 2, 255a3d9a352SFam Zheng CMBSZ_RDS_SHIFT = 3, 256a3d9a352SFam Zheng CMBSZ_WDS_SHIFT = 4, 257a3d9a352SFam Zheng CMBSZ_SZU_SHIFT = 8, 258a3d9a352SFam Zheng CMBSZ_SZ_SHIFT = 12, 259a3d9a352SFam Zheng }; 260a3d9a352SFam Zheng 261a3d9a352SFam Zheng enum NvmeCmbszMask { 262a3d9a352SFam Zheng CMBSZ_SQS_MASK = 0x1, 263a3d9a352SFam Zheng CMBSZ_CQS_MASK = 0x1, 264a3d9a352SFam Zheng CMBSZ_LISTS_MASK = 0x1, 265a3d9a352SFam Zheng CMBSZ_RDS_MASK = 0x1, 266a3d9a352SFam Zheng CMBSZ_WDS_MASK = 0x1, 267a3d9a352SFam Zheng CMBSZ_SZU_MASK = 0xf, 268a3d9a352SFam Zheng CMBSZ_SZ_MASK = 0xfffff, 269a3d9a352SFam Zheng }; 270a3d9a352SFam Zheng 271a3d9a352SFam Zheng #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 272a3d9a352SFam Zheng #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 273a3d9a352SFam Zheng #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 274a3d9a352SFam Zheng #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 275a3d9a352SFam Zheng #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 276a3d9a352SFam Zheng #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 277a3d9a352SFam Zheng #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 278a3d9a352SFam Zheng 279a3d9a352SFam Zheng #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 280a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 281a3d9a352SFam Zheng #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 282a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 283a3d9a352SFam Zheng #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 284a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 285a3d9a352SFam Zheng #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 286a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 287a3d9a352SFam Zheng #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 288a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 289a3d9a352SFam Zheng #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 290a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 291a3d9a352SFam Zheng #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 292a3d9a352SFam Zheng (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 293a3d9a352SFam Zheng 294a3d9a352SFam Zheng #define NVME_CMBSZ_GETSIZE(cmbsz) \ 295a3d9a352SFam Zheng (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 296a3d9a352SFam Zheng 297f4319477SPadmakar Kalghatgi enum NvmeCmbmscShift { 298f4319477SPadmakar Kalghatgi CMBMSC_CRE_SHIFT = 0, 299f4319477SPadmakar Kalghatgi CMBMSC_CMSE_SHIFT = 1, 300f4319477SPadmakar Kalghatgi CMBMSC_CBA_SHIFT = 12, 301f4319477SPadmakar Kalghatgi }; 302f4319477SPadmakar Kalghatgi 303f4319477SPadmakar Kalghatgi enum NvmeCmbmscMask { 304f4319477SPadmakar Kalghatgi CMBMSC_CRE_MASK = 0x1, 305f4319477SPadmakar Kalghatgi CMBMSC_CMSE_MASK = 0x1, 306f4319477SPadmakar Kalghatgi CMBMSC_CBA_MASK = ((1ULL << 52) - 1), 307f4319477SPadmakar Kalghatgi }; 308f4319477SPadmakar Kalghatgi 309f4319477SPadmakar Kalghatgi #define NVME_CMBMSC_CRE(cmbmsc) \ 310f4319477SPadmakar Kalghatgi ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK) 311f4319477SPadmakar Kalghatgi #define NVME_CMBMSC_CMSE(cmbmsc) \ 312f4319477SPadmakar Kalghatgi ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK) 313f4319477SPadmakar Kalghatgi #define NVME_CMBMSC_CBA(cmbmsc) \ 314f4319477SPadmakar Kalghatgi ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK) 315f4319477SPadmakar Kalghatgi 316f4319477SPadmakar Kalghatgi 317f4319477SPadmakar Kalghatgi #define NVME_CMBMSC_SET_CRE(cmbmsc, val) \ 318f4319477SPadmakar Kalghatgi (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT) 319f4319477SPadmakar Kalghatgi #define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \ 320f4319477SPadmakar Kalghatgi (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT) 321f4319477SPadmakar Kalghatgi #define NVME_CMBMSC_SET_CBA(cmbmsc, val) \ 322f4319477SPadmakar Kalghatgi (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT) 323f4319477SPadmakar Kalghatgi 324f4319477SPadmakar Kalghatgi enum NvmeCmbstsShift { 325f4319477SPadmakar Kalghatgi CMBSTS_CBAI_SHIFT = 0, 326f4319477SPadmakar Kalghatgi }; 327f4319477SPadmakar Kalghatgi enum NvmeCmbstsMask { 328f4319477SPadmakar Kalghatgi CMBSTS_CBAI_MASK = 0x1, 329f4319477SPadmakar Kalghatgi }; 330f4319477SPadmakar Kalghatgi 331f4319477SPadmakar Kalghatgi #define NVME_CMBSTS_CBAI(cmbsts) \ 332f4319477SPadmakar Kalghatgi ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK) 333f4319477SPadmakar Kalghatgi 334f4319477SPadmakar Kalghatgi #define NVME_CMBSTS_SET_CBAI(cmbsts, val) \ 335f4319477SPadmakar Kalghatgi (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT) 336f4319477SPadmakar Kalghatgi 3376cf94132SAndrzej Jakowski enum NvmePmrcapShift { 3386cf94132SAndrzej Jakowski PMRCAP_RDS_SHIFT = 3, 3396cf94132SAndrzej Jakowski PMRCAP_WDS_SHIFT = 4, 3406cf94132SAndrzej Jakowski PMRCAP_BIR_SHIFT = 5, 3416cf94132SAndrzej Jakowski PMRCAP_PMRTU_SHIFT = 8, 3426cf94132SAndrzej Jakowski PMRCAP_PMRWBM_SHIFT = 10, 3436cf94132SAndrzej Jakowski PMRCAP_PMRTO_SHIFT = 16, 3446cf94132SAndrzej Jakowski PMRCAP_CMSS_SHIFT = 24, 3456cf94132SAndrzej Jakowski }; 3466cf94132SAndrzej Jakowski 3476cf94132SAndrzej Jakowski enum NvmePmrcapMask { 3486cf94132SAndrzej Jakowski PMRCAP_RDS_MASK = 0x1, 3496cf94132SAndrzej Jakowski PMRCAP_WDS_MASK = 0x1, 3506cf94132SAndrzej Jakowski PMRCAP_BIR_MASK = 0x7, 3516cf94132SAndrzej Jakowski PMRCAP_PMRTU_MASK = 0x3, 3526cf94132SAndrzej Jakowski PMRCAP_PMRWBM_MASK = 0xf, 3536cf94132SAndrzej Jakowski PMRCAP_PMRTO_MASK = 0xff, 3546cf94132SAndrzej Jakowski PMRCAP_CMSS_MASK = 0x1, 3556cf94132SAndrzej Jakowski }; 3566cf94132SAndrzej Jakowski 3576cf94132SAndrzej Jakowski #define NVME_PMRCAP_RDS(pmrcap) \ 3586cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 3596cf94132SAndrzej Jakowski #define NVME_PMRCAP_WDS(pmrcap) \ 3606cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 3616cf94132SAndrzej Jakowski #define NVME_PMRCAP_BIR(pmrcap) \ 3626cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 3636cf94132SAndrzej Jakowski #define NVME_PMRCAP_PMRTU(pmrcap) \ 3646cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 3656cf94132SAndrzej Jakowski #define NVME_PMRCAP_PMRWBM(pmrcap) \ 3666cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 3676cf94132SAndrzej Jakowski #define NVME_PMRCAP_PMRTO(pmrcap) \ 3686cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 3696cf94132SAndrzej Jakowski #define NVME_PMRCAP_CMSS(pmrcap) \ 3706cf94132SAndrzej Jakowski ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 3716cf94132SAndrzej Jakowski 3726cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 3736cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 3746cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 3756cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 3766cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 3776cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 3786cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 3796cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 3806cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 3816cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 3826cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 3836cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 3846cf94132SAndrzej Jakowski #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 3856cf94132SAndrzej Jakowski (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 3866cf94132SAndrzej Jakowski 3876cf94132SAndrzej Jakowski enum NvmePmrctlShift { 3886cf94132SAndrzej Jakowski PMRCTL_EN_SHIFT = 0, 3896cf94132SAndrzej Jakowski }; 3906cf94132SAndrzej Jakowski 3916cf94132SAndrzej Jakowski enum NvmePmrctlMask { 3926cf94132SAndrzej Jakowski PMRCTL_EN_MASK = 0x1, 3936cf94132SAndrzej Jakowski }; 3946cf94132SAndrzej Jakowski 3956cf94132SAndrzej Jakowski #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 3966cf94132SAndrzej Jakowski 3976cf94132SAndrzej Jakowski #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 3986cf94132SAndrzej Jakowski (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 3996cf94132SAndrzej Jakowski 4006cf94132SAndrzej Jakowski enum NvmePmrstsShift { 4016cf94132SAndrzej Jakowski PMRSTS_ERR_SHIFT = 0, 4026cf94132SAndrzej Jakowski PMRSTS_NRDY_SHIFT = 8, 4036cf94132SAndrzej Jakowski PMRSTS_HSTS_SHIFT = 9, 4046cf94132SAndrzej Jakowski PMRSTS_CBAI_SHIFT = 12, 4056cf94132SAndrzej Jakowski }; 4066cf94132SAndrzej Jakowski 4076cf94132SAndrzej Jakowski enum NvmePmrstsMask { 4086cf94132SAndrzej Jakowski PMRSTS_ERR_MASK = 0xff, 4096cf94132SAndrzej Jakowski PMRSTS_NRDY_MASK = 0x1, 4106cf94132SAndrzej Jakowski PMRSTS_HSTS_MASK = 0x7, 4116cf94132SAndrzej Jakowski PMRSTS_CBAI_MASK = 0x1, 4126cf94132SAndrzej Jakowski }; 4136cf94132SAndrzej Jakowski 4146cf94132SAndrzej Jakowski #define NVME_PMRSTS_ERR(pmrsts) \ 4156cf94132SAndrzej Jakowski ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 4166cf94132SAndrzej Jakowski #define NVME_PMRSTS_NRDY(pmrsts) \ 4176cf94132SAndrzej Jakowski ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 4186cf94132SAndrzej Jakowski #define NVME_PMRSTS_HSTS(pmrsts) \ 4196cf94132SAndrzej Jakowski ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 4206cf94132SAndrzej Jakowski #define NVME_PMRSTS_CBAI(pmrsts) \ 4216cf94132SAndrzej Jakowski ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 4226cf94132SAndrzej Jakowski 4236cf94132SAndrzej Jakowski #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 4246cf94132SAndrzej Jakowski (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 4256cf94132SAndrzej Jakowski #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 4266cf94132SAndrzej Jakowski (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 4276cf94132SAndrzej Jakowski #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 4286cf94132SAndrzej Jakowski (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 4296cf94132SAndrzej Jakowski #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 4306cf94132SAndrzej Jakowski (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 4316cf94132SAndrzej Jakowski 4326cf94132SAndrzej Jakowski enum NvmePmrebsShift { 4336cf94132SAndrzej Jakowski PMREBS_PMRSZU_SHIFT = 0, 4346cf94132SAndrzej Jakowski PMREBS_RBB_SHIFT = 4, 4356cf94132SAndrzej Jakowski PMREBS_PMRWBZ_SHIFT = 8, 4366cf94132SAndrzej Jakowski }; 4376cf94132SAndrzej Jakowski 4386cf94132SAndrzej Jakowski enum NvmePmrebsMask { 4396cf94132SAndrzej Jakowski PMREBS_PMRSZU_MASK = 0xf, 4406cf94132SAndrzej Jakowski PMREBS_RBB_MASK = 0x1, 4416cf94132SAndrzej Jakowski PMREBS_PMRWBZ_MASK = 0xffffff, 4426cf94132SAndrzej Jakowski }; 4436cf94132SAndrzej Jakowski 4446cf94132SAndrzej Jakowski #define NVME_PMREBS_PMRSZU(pmrebs) \ 4456cf94132SAndrzej Jakowski ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 4466cf94132SAndrzej Jakowski #define NVME_PMREBS_RBB(pmrebs) \ 4476cf94132SAndrzej Jakowski ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 4486cf94132SAndrzej Jakowski #define NVME_PMREBS_PMRWBZ(pmrebs) \ 4496cf94132SAndrzej Jakowski ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 4506cf94132SAndrzej Jakowski 4516cf94132SAndrzej Jakowski #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 4526cf94132SAndrzej Jakowski (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 4536cf94132SAndrzej Jakowski #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 4546cf94132SAndrzej Jakowski (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 4556cf94132SAndrzej Jakowski #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 4566cf94132SAndrzej Jakowski (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 4576cf94132SAndrzej Jakowski 4586cf94132SAndrzej Jakowski enum NvmePmrswtpShift { 4596cf94132SAndrzej Jakowski PMRSWTP_PMRSWTU_SHIFT = 0, 4606cf94132SAndrzej Jakowski PMRSWTP_PMRSWTV_SHIFT = 8, 4616cf94132SAndrzej Jakowski }; 4626cf94132SAndrzej Jakowski 4636cf94132SAndrzej Jakowski enum NvmePmrswtpMask { 4646cf94132SAndrzej Jakowski PMRSWTP_PMRSWTU_MASK = 0xf, 4656cf94132SAndrzej Jakowski PMRSWTP_PMRSWTV_MASK = 0xffffff, 4666cf94132SAndrzej Jakowski }; 4676cf94132SAndrzej Jakowski 4686cf94132SAndrzej Jakowski #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 4696cf94132SAndrzej Jakowski ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 4706cf94132SAndrzej Jakowski #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 4716cf94132SAndrzej Jakowski ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 4726cf94132SAndrzej Jakowski 4736cf94132SAndrzej Jakowski #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 4746cf94132SAndrzej Jakowski (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 4756cf94132SAndrzej Jakowski #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 4766cf94132SAndrzej Jakowski (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 4776cf94132SAndrzej Jakowski 4786cf94132SAndrzej Jakowski enum NvmePmrmscShift { 4796cf94132SAndrzej Jakowski PMRMSC_CMSE_SHIFT = 1, 4806cf94132SAndrzej Jakowski PMRMSC_CBA_SHIFT = 12, 4816cf94132SAndrzej Jakowski }; 4826cf94132SAndrzej Jakowski 4836cf94132SAndrzej Jakowski enum NvmePmrmscMask { 4846cf94132SAndrzej Jakowski PMRMSC_CMSE_MASK = 0x1, 4856cf94132SAndrzej Jakowski PMRMSC_CBA_MASK = 0xfffffffffffff, 4866cf94132SAndrzej Jakowski }; 4876cf94132SAndrzej Jakowski 4886cf94132SAndrzej Jakowski #define NVME_PMRMSC_CMSE(pmrmsc) \ 4896cf94132SAndrzej Jakowski ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 4906cf94132SAndrzej Jakowski #define NVME_PMRMSC_CBA(pmrmsc) \ 4916cf94132SAndrzej Jakowski ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 4926cf94132SAndrzej Jakowski 4936cf94132SAndrzej Jakowski #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 4946cf94132SAndrzej Jakowski (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 4956cf94132SAndrzej Jakowski #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 4966cf94132SAndrzej Jakowski (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 4976cf94132SAndrzej Jakowski 498c26f2173SKlaus Jensen enum NvmeSglDescriptorType { 499c26f2173SKlaus Jensen NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 500c26f2173SKlaus Jensen NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 501c26f2173SKlaus Jensen NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 502c26f2173SKlaus Jensen NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 503c26f2173SKlaus Jensen NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 504c26f2173SKlaus Jensen 505c26f2173SKlaus Jensen NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 506c26f2173SKlaus Jensen }; 507c26f2173SKlaus Jensen 508c26f2173SKlaus Jensen enum NvmeSglDescriptorSubtype { 509c26f2173SKlaus Jensen NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 510c26f2173SKlaus Jensen }; 511c26f2173SKlaus Jensen 512c26f2173SKlaus Jensen typedef struct QEMU_PACKED NvmeSglDescriptor { 513c26f2173SKlaus Jensen uint64_t addr; 514c26f2173SKlaus Jensen uint32_t len; 515c26f2173SKlaus Jensen uint8_t rsvd[3]; 516c26f2173SKlaus Jensen uint8_t type; 517c26f2173SKlaus Jensen } NvmeSglDescriptor; 518c26f2173SKlaus Jensen 519c26f2173SKlaus Jensen #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 520c26f2173SKlaus Jensen #define NVME_SGL_SUBTYPE(type) (type & 0xf) 521c26f2173SKlaus Jensen 522c26f2173SKlaus Jensen typedef union NvmeCmdDptr { 523c26f2173SKlaus Jensen struct { 524c26f2173SKlaus Jensen uint64_t prp1; 525c26f2173SKlaus Jensen uint64_t prp2; 526c26f2173SKlaus Jensen }; 527c26f2173SKlaus Jensen 528c26f2173SKlaus Jensen NvmeSglDescriptor sgl; 529c26f2173SKlaus Jensen } NvmeCmdDptr; 530c26f2173SKlaus Jensen 531c26f2173SKlaus Jensen enum NvmePsdt { 532cba0a8a3SKlaus Jensen NVME_PSDT_PRP = 0x0, 533cba0a8a3SKlaus Jensen NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 534cba0a8a3SKlaus Jensen NVME_PSDT_SGL_MPTR_SGL = 0x2, 535c26f2173SKlaus Jensen }; 536c26f2173SKlaus Jensen 537e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeCmd { 538a3d9a352SFam Zheng uint8_t opcode; 539c26f2173SKlaus Jensen uint8_t flags; 540a3d9a352SFam Zheng uint16_t cid; 541a3d9a352SFam Zheng uint32_t nsid; 542a3d9a352SFam Zheng uint64_t res1; 543a3d9a352SFam Zheng uint64_t mptr; 544c26f2173SKlaus Jensen NvmeCmdDptr dptr; 545a3d9a352SFam Zheng uint32_t cdw10; 546a3d9a352SFam Zheng uint32_t cdw11; 547a3d9a352SFam Zheng uint32_t cdw12; 548a3d9a352SFam Zheng uint32_t cdw13; 549a3d9a352SFam Zheng uint32_t cdw14; 550a3d9a352SFam Zheng uint32_t cdw15; 551a3d9a352SFam Zheng } NvmeCmd; 552a3d9a352SFam Zheng 553c26f2173SKlaus Jensen #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 554c26f2173SKlaus Jensen #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 555c26f2173SKlaus Jensen 556a3d9a352SFam Zheng enum NvmeAdminCommands { 557a3d9a352SFam Zheng NVME_ADM_CMD_DELETE_SQ = 0x00, 558a3d9a352SFam Zheng NVME_ADM_CMD_CREATE_SQ = 0x01, 559a3d9a352SFam Zheng NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 560a3d9a352SFam Zheng NVME_ADM_CMD_DELETE_CQ = 0x04, 561a3d9a352SFam Zheng NVME_ADM_CMD_CREATE_CQ = 0x05, 562a3d9a352SFam Zheng NVME_ADM_CMD_IDENTIFY = 0x06, 563a3d9a352SFam Zheng NVME_ADM_CMD_ABORT = 0x08, 564a3d9a352SFam Zheng NVME_ADM_CMD_SET_FEATURES = 0x09, 565a3d9a352SFam Zheng NVME_ADM_CMD_GET_FEATURES = 0x0a, 566a3d9a352SFam Zheng NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 567a3d9a352SFam Zheng NVME_ADM_CMD_ACTIVATE_FW = 0x10, 568a3d9a352SFam Zheng NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 569645ce1a7SMinwoo Im NVME_ADM_CMD_NS_ATTACHMENT = 0x15, 570a3d9a352SFam Zheng NVME_ADM_CMD_FORMAT_NVM = 0x80, 571a3d9a352SFam Zheng NVME_ADM_CMD_SECURITY_SEND = 0x81, 572a3d9a352SFam Zheng NVME_ADM_CMD_SECURITY_RECV = 0x82, 573a3d9a352SFam Zheng }; 574a3d9a352SFam Zheng 575a3d9a352SFam Zheng enum NvmeIoCommands { 576a3d9a352SFam Zheng NVME_CMD_FLUSH = 0x00, 577a3d9a352SFam Zheng NVME_CMD_WRITE = 0x01, 578a3d9a352SFam Zheng NVME_CMD_READ = 0x02, 579a3d9a352SFam Zheng NVME_CMD_WRITE_UNCOR = 0x04, 580a3d9a352SFam Zheng NVME_CMD_COMPARE = 0x05, 58169265150SKlaus Jensen NVME_CMD_WRITE_ZEROES = 0x08, 582a3d9a352SFam Zheng NVME_CMD_DSM = 0x09, 5833e1da158SGollu Appalanaidu NVME_CMD_VERIFY = 0x0c, 5843862efffSKlaus Jensen NVME_CMD_COPY = 0x19, 585e9ba46eeSDmitry Fomichev NVME_CMD_ZONE_MGMT_SEND = 0x79, 586e9ba46eeSDmitry Fomichev NVME_CMD_ZONE_MGMT_RECV = 0x7a, 587e9ba46eeSDmitry Fomichev NVME_CMD_ZONE_APPEND = 0x7d, 588a3d9a352SFam Zheng }; 589a3d9a352SFam Zheng 590e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeDeleteQ { 591a3d9a352SFam Zheng uint8_t opcode; 592a3d9a352SFam Zheng uint8_t flags; 593a3d9a352SFam Zheng uint16_t cid; 594a3d9a352SFam Zheng uint32_t rsvd1[9]; 595a3d9a352SFam Zheng uint16_t qid; 596a3d9a352SFam Zheng uint16_t rsvd10; 597a3d9a352SFam Zheng uint32_t rsvd11[5]; 598a3d9a352SFam Zheng } NvmeDeleteQ; 599a3d9a352SFam Zheng 600e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeCreateCq { 601a3d9a352SFam Zheng uint8_t opcode; 602a3d9a352SFam Zheng uint8_t flags; 603a3d9a352SFam Zheng uint16_t cid; 604a3d9a352SFam Zheng uint32_t rsvd1[5]; 605a3d9a352SFam Zheng uint64_t prp1; 606a3d9a352SFam Zheng uint64_t rsvd8; 607a3d9a352SFam Zheng uint16_t cqid; 608a3d9a352SFam Zheng uint16_t qsize; 609a3d9a352SFam Zheng uint16_t cq_flags; 610a3d9a352SFam Zheng uint16_t irq_vector; 611a3d9a352SFam Zheng uint32_t rsvd12[4]; 612a3d9a352SFam Zheng } NvmeCreateCq; 613a3d9a352SFam Zheng 614a3d9a352SFam Zheng #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 615a3d9a352SFam Zheng #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 616a3d9a352SFam Zheng 61754248d4dSPhilippe Mathieu-Daudé enum NvmeFlagsCq { 61854248d4dSPhilippe Mathieu-Daudé NVME_CQ_PC = 1, 61954248d4dSPhilippe Mathieu-Daudé NVME_CQ_IEN = 2, 62054248d4dSPhilippe Mathieu-Daudé }; 62154248d4dSPhilippe Mathieu-Daudé 622e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeCreateSq { 623a3d9a352SFam Zheng uint8_t opcode; 624a3d9a352SFam Zheng uint8_t flags; 625a3d9a352SFam Zheng uint16_t cid; 626a3d9a352SFam Zheng uint32_t rsvd1[5]; 627a3d9a352SFam Zheng uint64_t prp1; 628a3d9a352SFam Zheng uint64_t rsvd8; 629a3d9a352SFam Zheng uint16_t sqid; 630a3d9a352SFam Zheng uint16_t qsize; 631a3d9a352SFam Zheng uint16_t sq_flags; 632a3d9a352SFam Zheng uint16_t cqid; 633a3d9a352SFam Zheng uint32_t rsvd12[4]; 634a3d9a352SFam Zheng } NvmeCreateSq; 635a3d9a352SFam Zheng 636a3d9a352SFam Zheng #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 637a3d9a352SFam Zheng #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 638a3d9a352SFam Zheng 63954248d4dSPhilippe Mathieu-Daudé enum NvmeFlagsSq { 64054248d4dSPhilippe Mathieu-Daudé NVME_SQ_PC = 1, 64154248d4dSPhilippe Mathieu-Daudé 64254248d4dSPhilippe Mathieu-Daudé NVME_SQ_PRIO_URGENT = 0, 64354248d4dSPhilippe Mathieu-Daudé NVME_SQ_PRIO_HIGH = 1, 64454248d4dSPhilippe Mathieu-Daudé NVME_SQ_PRIO_NORMAL = 2, 64554248d4dSPhilippe Mathieu-Daudé NVME_SQ_PRIO_LOW = 3, 646a3d9a352SFam Zheng }; 647a3d9a352SFam Zheng 648e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeIdentify { 649a3d9a352SFam Zheng uint8_t opcode; 650a3d9a352SFam Zheng uint8_t flags; 651a3d9a352SFam Zheng uint16_t cid; 652a3d9a352SFam Zheng uint32_t nsid; 653a3d9a352SFam Zheng uint64_t rsvd2[2]; 654a3d9a352SFam Zheng uint64_t prp1; 655a3d9a352SFam Zheng uint64_t prp2; 656141354d5SNiklas Cassel uint8_t cns; 657141354d5SNiklas Cassel uint8_t rsvd10; 658141354d5SNiklas Cassel uint16_t ctrlid; 659141354d5SNiklas Cassel uint16_t nvmsetid; 660141354d5SNiklas Cassel uint8_t rsvd11; 661141354d5SNiklas Cassel uint8_t csi; 662141354d5SNiklas Cassel uint32_t rsvd12[4]; 663a3d9a352SFam Zheng } NvmeIdentify; 664a3d9a352SFam Zheng 665e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeRwCmd { 666a3d9a352SFam Zheng uint8_t opcode; 667a3d9a352SFam Zheng uint8_t flags; 668a3d9a352SFam Zheng uint16_t cid; 669a3d9a352SFam Zheng uint32_t nsid; 670a3d9a352SFam Zheng uint64_t rsvd2; 671a3d9a352SFam Zheng uint64_t mptr; 672c26f2173SKlaus Jensen NvmeCmdDptr dptr; 673a3d9a352SFam Zheng uint64_t slba; 674a3d9a352SFam Zheng uint16_t nlb; 675a3d9a352SFam Zheng uint16_t control; 676a3d9a352SFam Zheng uint32_t dsmgmt; 677a3d9a352SFam Zheng uint32_t reftag; 678a3d9a352SFam Zheng uint16_t apptag; 679a3d9a352SFam Zheng uint16_t appmask; 680a3d9a352SFam Zheng } NvmeRwCmd; 681a3d9a352SFam Zheng 682a3d9a352SFam Zheng enum { 683a3d9a352SFam Zheng NVME_RW_LR = 1 << 15, 684a3d9a352SFam Zheng NVME_RW_FUA = 1 << 14, 685a3d9a352SFam Zheng NVME_RW_DSM_FREQ_UNSPEC = 0, 686a3d9a352SFam Zheng NVME_RW_DSM_FREQ_TYPICAL = 1, 687a3d9a352SFam Zheng NVME_RW_DSM_FREQ_RARE = 2, 688a3d9a352SFam Zheng NVME_RW_DSM_FREQ_READS = 3, 689a3d9a352SFam Zheng NVME_RW_DSM_FREQ_WRITES = 4, 690a3d9a352SFam Zheng NVME_RW_DSM_FREQ_RW = 5, 691a3d9a352SFam Zheng NVME_RW_DSM_FREQ_ONCE = 6, 692a3d9a352SFam Zheng NVME_RW_DSM_FREQ_PREFETCH = 7, 693a3d9a352SFam Zheng NVME_RW_DSM_FREQ_TEMP = 8, 694a3d9a352SFam Zheng NVME_RW_DSM_LATENCY_NONE = 0 << 4, 695a3d9a352SFam Zheng NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 696a3d9a352SFam Zheng NVME_RW_DSM_LATENCY_NORM = 2 << 4, 697a3d9a352SFam Zheng NVME_RW_DSM_LATENCY_LOW = 3 << 4, 698a3d9a352SFam Zheng NVME_RW_DSM_SEQ_REQ = 1 << 6, 699a3d9a352SFam Zheng NVME_RW_DSM_COMPRESSED = 1 << 7, 700146f720cSKlaus Jensen NVME_RW_PIREMAP = 1 << 9, 701a3d9a352SFam Zheng NVME_RW_PRINFO_PRACT = 1 << 13, 702a3d9a352SFam Zheng NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 703a3d9a352SFam Zheng NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 704a3d9a352SFam Zheng NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 705146f720cSKlaus Jensen NVME_RW_PRINFO_PRCHK_MASK = 7 << 10, 706146f720cSKlaus Jensen 707a3d9a352SFam Zheng }; 708a3d9a352SFam Zheng 709146f720cSKlaus Jensen #define NVME_RW_PRINFO(control) ((control >> 10) & 0xf) 710146f720cSKlaus Jensen 711*2a132309SKlaus Jensen enum { 712*2a132309SKlaus Jensen NVME_PRINFO_PRACT = 1 << 3, 713*2a132309SKlaus Jensen NVME_PRINFO_PRCHK_GUARD = 1 << 2, 714*2a132309SKlaus Jensen NVME_PRINFO_PRCHK_APP = 1 << 1, 715*2a132309SKlaus Jensen NVME_PRINFO_PRCHK_REF = 1 << 0, 716*2a132309SKlaus Jensen NVME_PRINFO_PRCHK_MASK = 7 << 0, 717*2a132309SKlaus Jensen }; 718*2a132309SKlaus Jensen 719e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeDsmCmd { 720a3d9a352SFam Zheng uint8_t opcode; 721a3d9a352SFam Zheng uint8_t flags; 722a3d9a352SFam Zheng uint16_t cid; 723a3d9a352SFam Zheng uint32_t nsid; 724a3d9a352SFam Zheng uint64_t rsvd2[2]; 725c26f2173SKlaus Jensen NvmeCmdDptr dptr; 726a3d9a352SFam Zheng uint32_t nr; 727a3d9a352SFam Zheng uint32_t attributes; 728a3d9a352SFam Zheng uint32_t rsvd12[4]; 729a3d9a352SFam Zheng } NvmeDsmCmd; 730a3d9a352SFam Zheng 731a3d9a352SFam Zheng enum { 732a3d9a352SFam Zheng NVME_DSMGMT_IDR = 1 << 0, 733a3d9a352SFam Zheng NVME_DSMGMT_IDW = 1 << 1, 734a3d9a352SFam Zheng NVME_DSMGMT_AD = 1 << 2, 735a3d9a352SFam Zheng }; 736a3d9a352SFam Zheng 737e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeDsmRange { 738a3d9a352SFam Zheng uint32_t cattr; 739a3d9a352SFam Zheng uint32_t nlb; 740a3d9a352SFam Zheng uint64_t slba; 741a3d9a352SFam Zheng } NvmeDsmRange; 742a3d9a352SFam Zheng 7433862efffSKlaus Jensen enum { 7443862efffSKlaus Jensen NVME_COPY_FORMAT_0 = 0x0, 7453862efffSKlaus Jensen }; 7463862efffSKlaus Jensen 7473862efffSKlaus Jensen typedef struct QEMU_PACKED NvmeCopyCmd { 7483862efffSKlaus Jensen uint8_t opcode; 7493862efffSKlaus Jensen uint8_t flags; 7503862efffSKlaus Jensen uint16_t cid; 7513862efffSKlaus Jensen uint32_t nsid; 7523862efffSKlaus Jensen uint32_t rsvd2[4]; 7533862efffSKlaus Jensen NvmeCmdDptr dptr; 7543862efffSKlaus Jensen uint64_t sdlba; 7553862efffSKlaus Jensen uint8_t nr; 7563862efffSKlaus Jensen uint8_t control[3]; 7573862efffSKlaus Jensen uint16_t rsvd13; 7583862efffSKlaus Jensen uint16_t dspec; 7593862efffSKlaus Jensen uint32_t reftag; 7603862efffSKlaus Jensen uint16_t apptag; 7613862efffSKlaus Jensen uint16_t appmask; 7623862efffSKlaus Jensen } NvmeCopyCmd; 7633862efffSKlaus Jensen 7643862efffSKlaus Jensen typedef struct QEMU_PACKED NvmeCopySourceRange { 7653862efffSKlaus Jensen uint8_t rsvd0[8]; 7663862efffSKlaus Jensen uint64_t slba; 7673862efffSKlaus Jensen uint16_t nlb; 7683862efffSKlaus Jensen uint8_t rsvd18[6]; 7693862efffSKlaus Jensen uint32_t reftag; 7703862efffSKlaus Jensen uint16_t apptag; 7713862efffSKlaus Jensen uint16_t appmask; 7723862efffSKlaus Jensen } NvmeCopySourceRange; 7733862efffSKlaus Jensen 774a3d9a352SFam Zheng enum NvmeAsyncEventRequest { 775a3d9a352SFam Zheng NVME_AER_TYPE_ERROR = 0, 776a3d9a352SFam Zheng NVME_AER_TYPE_SMART = 1, 777f432fdfaSMinwoo Im NVME_AER_TYPE_NOTICE = 2, 778a3d9a352SFam Zheng NVME_AER_TYPE_IO_SPECIFIC = 6, 779a3d9a352SFam Zheng NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 7805d5a5330SKlaus Jensen NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 7815d5a5330SKlaus Jensen NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 782a3d9a352SFam Zheng NVME_AER_INFO_ERR_DIAG_FAIL = 2, 783a3d9a352SFam Zheng NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 784a3d9a352SFam Zheng NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 785a3d9a352SFam Zheng NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 786a3d9a352SFam Zheng NVME_AER_INFO_SMART_RELIABILITY = 0, 787a3d9a352SFam Zheng NVME_AER_INFO_SMART_TEMP_THRESH = 1, 788a3d9a352SFam Zheng NVME_AER_INFO_SMART_SPARE_THRESH = 2, 789f432fdfaSMinwoo Im NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED = 0, 790a3d9a352SFam Zheng }; 791a3d9a352SFam Zheng 792e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeAerResult { 793a3d9a352SFam Zheng uint8_t event_type; 794a3d9a352SFam Zheng uint8_t event_info; 795a3d9a352SFam Zheng uint8_t log_page; 796a3d9a352SFam Zheng uint8_t resv; 797a3d9a352SFam Zheng } NvmeAerResult; 798a3d9a352SFam Zheng 799e9ba46eeSDmitry Fomichev typedef struct QEMU_PACKED NvmeZonedResult { 800e9ba46eeSDmitry Fomichev uint64_t slba; 801e9ba46eeSDmitry Fomichev } NvmeZonedResult; 802e9ba46eeSDmitry Fomichev 803e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeCqe { 804a3d9a352SFam Zheng uint32_t result; 805e9ba46eeSDmitry Fomichev uint32_t dw1; 806a3d9a352SFam Zheng uint16_t sq_head; 807a3d9a352SFam Zheng uint16_t sq_id; 808a3d9a352SFam Zheng uint16_t cid; 809a3d9a352SFam Zheng uint16_t status; 810a3d9a352SFam Zheng } NvmeCqe; 811a3d9a352SFam Zheng 812a3d9a352SFam Zheng enum NvmeStatusCodes { 813a3d9a352SFam Zheng NVME_SUCCESS = 0x0000, 814a3d9a352SFam Zheng NVME_INVALID_OPCODE = 0x0001, 815a3d9a352SFam Zheng NVME_INVALID_FIELD = 0x0002, 816a3d9a352SFam Zheng NVME_CID_CONFLICT = 0x0003, 817a3d9a352SFam Zheng NVME_DATA_TRAS_ERROR = 0x0004, 818a3d9a352SFam Zheng NVME_POWER_LOSS_ABORT = 0x0005, 819a3d9a352SFam Zheng NVME_INTERNAL_DEV_ERROR = 0x0006, 820a3d9a352SFam Zheng NVME_CMD_ABORT_REQ = 0x0007, 821a3d9a352SFam Zheng NVME_CMD_ABORT_SQ_DEL = 0x0008, 822a3d9a352SFam Zheng NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 823a3d9a352SFam Zheng NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 824a3d9a352SFam Zheng NVME_INVALID_NSID = 0x000b, 825a3d9a352SFam Zheng NVME_CMD_SEQ_ERROR = 0x000c, 826c26f2173SKlaus Jensen NVME_INVALID_SGL_SEG_DESCR = 0x000d, 827c26f2173SKlaus Jensen NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 828c26f2173SKlaus Jensen NVME_DATA_SGL_LEN_INVALID = 0x000f, 829c26f2173SKlaus Jensen NVME_MD_SGL_LEN_INVALID = 0x0010, 830c26f2173SKlaus Jensen NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 831c26f2173SKlaus Jensen NVME_INVALID_USE_OF_CMB = 0x0012, 83228fee5b5SGollu Appalanaidu NVME_INVALID_PRP_OFFSET = 0x0013, 833141354d5SNiklas Cassel NVME_CMD_SET_CMB_REJECTED = 0x002b, 834e9ba46eeSDmitry Fomichev NVME_INVALID_CMD_SET = 0x002c, 835a3d9a352SFam Zheng NVME_LBA_RANGE = 0x0080, 836a3d9a352SFam Zheng NVME_CAP_EXCEEDED = 0x0081, 837a3d9a352SFam Zheng NVME_NS_NOT_READY = 0x0082, 838a3d9a352SFam Zheng NVME_NS_RESV_CONFLICT = 0x0083, 839dc04d25eSMinwoo Im NVME_FORMAT_IN_PROGRESS = 0x0084, 840a3d9a352SFam Zheng NVME_INVALID_CQID = 0x0100, 841a3d9a352SFam Zheng NVME_INVALID_QID = 0x0101, 842a3d9a352SFam Zheng NVME_MAX_QSIZE_EXCEEDED = 0x0102, 843a3d9a352SFam Zheng NVME_ACL_EXCEEDED = 0x0103, 844a3d9a352SFam Zheng NVME_RESERVED = 0x0104, 845a3d9a352SFam Zheng NVME_AER_LIMIT_EXCEEDED = 0x0105, 846a3d9a352SFam Zheng NVME_INVALID_FW_SLOT = 0x0106, 847a3d9a352SFam Zheng NVME_INVALID_FW_IMAGE = 0x0107, 848a3d9a352SFam Zheng NVME_INVALID_IRQ_VECTOR = 0x0108, 849a3d9a352SFam Zheng NVME_INVALID_LOG_ID = 0x0109, 850a3d9a352SFam Zheng NVME_INVALID_FORMAT = 0x010a, 851a3d9a352SFam Zheng NVME_FW_REQ_RESET = 0x010b, 852a3d9a352SFam Zheng NVME_INVALID_QUEUE_DEL = 0x010c, 853a3d9a352SFam Zheng NVME_FID_NOT_SAVEABLE = 0x010d, 8541302e48eSKlaus Jensen NVME_FEAT_NOT_CHANGEABLE = 0x010e, 8557c46310dSKlaus Jensen NVME_FEAT_NOT_NS_SPEC = 0x010f, 856a3d9a352SFam Zheng NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 857645ce1a7SMinwoo Im NVME_NS_ALREADY_ATTACHED = 0x0118, 858e5489356SKlaus Jensen NVME_NS_PRIVATE = 0x0119, 859312c3531SGollu Appalanaidu NVME_NS_NOT_ATTACHED = 0x011a, 860312c3531SGollu Appalanaidu NVME_NS_CTRL_LIST_INVALID = 0x011c, 861a3d9a352SFam Zheng NVME_CONFLICTING_ATTRS = 0x0180, 862a3d9a352SFam Zheng NVME_INVALID_PROT_INFO = 0x0181, 863a3d9a352SFam Zheng NVME_WRITE_TO_RO = 0x0182, 8643862efffSKlaus Jensen NVME_CMD_SIZE_LIMIT = 0x0183, 865e9ba46eeSDmitry Fomichev NVME_ZONE_BOUNDARY_ERROR = 0x01b8, 866e9ba46eeSDmitry Fomichev NVME_ZONE_FULL = 0x01b9, 867e9ba46eeSDmitry Fomichev NVME_ZONE_READ_ONLY = 0x01ba, 868e9ba46eeSDmitry Fomichev NVME_ZONE_OFFLINE = 0x01bb, 869e9ba46eeSDmitry Fomichev NVME_ZONE_INVALID_WRITE = 0x01bc, 870e9ba46eeSDmitry Fomichev NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, 871e9ba46eeSDmitry Fomichev NVME_ZONE_TOO_MANY_OPEN = 0x01be, 872e9ba46eeSDmitry Fomichev NVME_ZONE_INVAL_TRANSITION = 0x01bf, 873a3d9a352SFam Zheng NVME_WRITE_FAULT = 0x0280, 874a3d9a352SFam Zheng NVME_UNRECOVERED_READ = 0x0281, 875a3d9a352SFam Zheng NVME_E2E_GUARD_ERROR = 0x0282, 876a3d9a352SFam Zheng NVME_E2E_APP_ERROR = 0x0283, 877a3d9a352SFam Zheng NVME_E2E_REF_ERROR = 0x0284, 878a3d9a352SFam Zheng NVME_CMP_FAILURE = 0x0285, 879a3d9a352SFam Zheng NVME_ACCESS_DENIED = 0x0286, 88054064e51SKlaus Jensen NVME_DULB = 0x0287, 881a3d9a352SFam Zheng NVME_MORE = 0x2000, 882a3d9a352SFam Zheng NVME_DNR = 0x4000, 883a3d9a352SFam Zheng NVME_NO_COMPLETE = 0xffff, 884a3d9a352SFam Zheng }; 885a3d9a352SFam Zheng 886e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 887a3d9a352SFam Zheng uint8_t afi; 888a3d9a352SFam Zheng uint8_t reserved1[7]; 889a3d9a352SFam Zheng uint8_t frs1[8]; 890a3d9a352SFam Zheng uint8_t frs2[8]; 891a3d9a352SFam Zheng uint8_t frs3[8]; 892a3d9a352SFam Zheng uint8_t frs4[8]; 893a3d9a352SFam Zheng uint8_t frs5[8]; 894a3d9a352SFam Zheng uint8_t frs6[8]; 895a3d9a352SFam Zheng uint8_t frs7[8]; 896a3d9a352SFam Zheng uint8_t reserved2[448]; 897a3d9a352SFam Zheng } NvmeFwSlotInfoLog; 898a3d9a352SFam Zheng 899e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeErrorLog { 900a3d9a352SFam Zheng uint64_t error_count; 901a3d9a352SFam Zheng uint16_t sqid; 902a3d9a352SFam Zheng uint16_t cid; 903a3d9a352SFam Zheng uint16_t status_field; 904a3d9a352SFam Zheng uint16_t param_error_location; 905a3d9a352SFam Zheng uint64_t lba; 906a3d9a352SFam Zheng uint32_t nsid; 907a3d9a352SFam Zheng uint8_t vs; 908a3d9a352SFam Zheng uint8_t resv[35]; 909a3d9a352SFam Zheng } NvmeErrorLog; 910a3d9a352SFam Zheng 911e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeSmartLog { 912a3d9a352SFam Zheng uint8_t critical_warning; 91394a7897cSKlaus Jensen uint16_t temperature; 914a3d9a352SFam Zheng uint8_t available_spare; 915a3d9a352SFam Zheng uint8_t available_spare_threshold; 916a3d9a352SFam Zheng uint8_t percentage_used; 917a3d9a352SFam Zheng uint8_t reserved1[26]; 918a3d9a352SFam Zheng uint64_t data_units_read[2]; 919a3d9a352SFam Zheng uint64_t data_units_written[2]; 920a3d9a352SFam Zheng uint64_t host_read_commands[2]; 921a3d9a352SFam Zheng uint64_t host_write_commands[2]; 922a3d9a352SFam Zheng uint64_t controller_busy_time[2]; 923a3d9a352SFam Zheng uint64_t power_cycles[2]; 924a3d9a352SFam Zheng uint64_t power_on_hours[2]; 925a3d9a352SFam Zheng uint64_t unsafe_shutdowns[2]; 926a3d9a352SFam Zheng uint64_t media_errors[2]; 927a3d9a352SFam Zheng uint64_t number_of_error_log_entries[2]; 928a3d9a352SFam Zheng uint8_t reserved2[320]; 929a3d9a352SFam Zheng } NvmeSmartLog; 930a3d9a352SFam Zheng 931c62720f1Szhenwei pi #define NVME_SMART_WARN_MAX 6 932a3d9a352SFam Zheng enum NvmeSmartWarn { 933a3d9a352SFam Zheng NVME_SMART_SPARE = 1 << 0, 934a3d9a352SFam Zheng NVME_SMART_TEMPERATURE = 1 << 1, 935a3d9a352SFam Zheng NVME_SMART_RELIABILITY = 1 << 2, 936a3d9a352SFam Zheng NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 937a3d9a352SFam Zheng NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 938c6d1b5c1Szhenwei pi NVME_SMART_PMR_UNRELIABLE = 1 << 5, 939a3d9a352SFam Zheng }; 940a3d9a352SFam Zheng 94162e8faa4SDmitry Fomichev typedef struct NvmeEffectsLog { 94262e8faa4SDmitry Fomichev uint32_t acs[256]; 94362e8faa4SDmitry Fomichev uint32_t iocs[256]; 94462e8faa4SDmitry Fomichev uint8_t resv[2048]; 94562e8faa4SDmitry Fomichev } NvmeEffectsLog; 94662e8faa4SDmitry Fomichev 94762e8faa4SDmitry Fomichev enum { 94862e8faa4SDmitry Fomichev NVME_CMD_EFF_CSUPP = 1 << 0, 94962e8faa4SDmitry Fomichev NVME_CMD_EFF_LBCC = 1 << 1, 95062e8faa4SDmitry Fomichev NVME_CMD_EFF_NCC = 1 << 2, 95162e8faa4SDmitry Fomichev NVME_CMD_EFF_NIC = 1 << 3, 95262e8faa4SDmitry Fomichev NVME_CMD_EFF_CCC = 1 << 4, 95362e8faa4SDmitry Fomichev NVME_CMD_EFF_CSE_MASK = 3 << 16, 95462e8faa4SDmitry Fomichev NVME_CMD_EFF_UUID_SEL = 1 << 19, 95562e8faa4SDmitry Fomichev }; 95662e8faa4SDmitry Fomichev 957c26f2173SKlaus Jensen enum NvmeLogIdentifier { 958a3d9a352SFam Zheng NVME_LOG_ERROR_INFO = 0x01, 959a3d9a352SFam Zheng NVME_LOG_SMART_INFO = 0x02, 960a3d9a352SFam Zheng NVME_LOG_FW_SLOT_INFO = 0x03, 961f432fdfaSMinwoo Im NVME_LOG_CHANGED_NSLIST = 0x04, 96262e8faa4SDmitry Fomichev NVME_LOG_CMD_EFFECTS = 0x05, 963a3d9a352SFam Zheng }; 964a3d9a352SFam Zheng 965e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmePSD { 966a3d9a352SFam Zheng uint16_t mp; 967a3d9a352SFam Zheng uint16_t reserved; 968a3d9a352SFam Zheng uint32_t enlat; 969a3d9a352SFam Zheng uint32_t exlat; 970a3d9a352SFam Zheng uint8_t rrt; 971a3d9a352SFam Zheng uint8_t rrl; 972a3d9a352SFam Zheng uint8_t rwt; 973a3d9a352SFam Zheng uint8_t rwl; 974a3d9a352SFam Zheng uint8_t resv[16]; 975a3d9a352SFam Zheng } NvmePSD; 976a3d9a352SFam Zheng 977645ce1a7SMinwoo Im #define NVME_CONTROLLER_LIST_SIZE 2048 9783e829fd4SKlaus Jensen #define NVME_IDENTIFY_DATA_SIZE 4096 9793e829fd4SKlaus Jensen 980141354d5SNiklas Cassel enum NvmeIdCns { 981141354d5SNiklas Cassel NVME_ID_CNS_NS = 0x00, 982141354d5SNiklas Cassel NVME_ID_CNS_CTRL = 0x01, 983141354d5SNiklas Cassel NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 984141354d5SNiklas Cassel NVME_ID_CNS_NS_DESCR_LIST = 0x03, 985141354d5SNiklas Cassel NVME_ID_CNS_CS_NS = 0x05, 986141354d5SNiklas Cassel NVME_ID_CNS_CS_CTRL = 0x06, 987141354d5SNiklas Cassel NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, 988922e6f4eSNiklas Cassel NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 989922e6f4eSNiklas Cassel NVME_ID_CNS_NS_PRESENT = 0x11, 99023fb7dfeSMinwoo Im NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12, 991922e6f4eSNiklas Cassel NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, 992922e6f4eSNiklas Cassel NVME_ID_CNS_CS_NS_PRESENT = 0x1b, 993141354d5SNiklas Cassel NVME_ID_CNS_IO_COMMAND_SET = 0x1c, 9943e829fd4SKlaus Jensen }; 9953e829fd4SKlaus Jensen 996e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeIdCtrl { 997a3d9a352SFam Zheng uint16_t vid; 998a3d9a352SFam Zheng uint16_t ssvid; 999a3d9a352SFam Zheng uint8_t sn[20]; 1000a3d9a352SFam Zheng uint8_t mn[40]; 1001a3d9a352SFam Zheng uint8_t fr[8]; 1002a3d9a352SFam Zheng uint8_t rab; 1003a3d9a352SFam Zheng uint8_t ieee[3]; 1004a3d9a352SFam Zheng uint8_t cmic; 1005a3d9a352SFam Zheng uint8_t mdts; 1006c26f2173SKlaus Jensen uint16_t cntlid; 1007c26f2173SKlaus Jensen uint32_t ver; 1008c26f2173SKlaus Jensen uint32_t rtd3r; 1009c26f2173SKlaus Jensen uint32_t rtd3e; 1010c26f2173SKlaus Jensen uint32_t oaes; 1011c26f2173SKlaus Jensen uint32_t ctratt; 1012c2a3640dSKlaus Jensen uint8_t rsvd100[11]; 1013c2a3640dSKlaus Jensen uint8_t cntrltype; 1014c26f2173SKlaus Jensen uint8_t fguid[16]; 1015c26f2173SKlaus Jensen uint8_t rsvd128[128]; 1016a3d9a352SFam Zheng uint16_t oacs; 1017a3d9a352SFam Zheng uint8_t acl; 1018a3d9a352SFam Zheng uint8_t aerl; 1019a3d9a352SFam Zheng uint8_t frmw; 1020a3d9a352SFam Zheng uint8_t lpa; 1021a3d9a352SFam Zheng uint8_t elpe; 1022a3d9a352SFam Zheng uint8_t npss; 1023c26f2173SKlaus Jensen uint8_t avscc; 1024c26f2173SKlaus Jensen uint8_t apsta; 1025c26f2173SKlaus Jensen uint16_t wctemp; 1026c26f2173SKlaus Jensen uint16_t cctemp; 1027c26f2173SKlaus Jensen uint16_t mtfa; 1028c26f2173SKlaus Jensen uint32_t hmpre; 1029c26f2173SKlaus Jensen uint32_t hmmin; 1030c26f2173SKlaus Jensen uint8_t tnvmcap[16]; 1031c26f2173SKlaus Jensen uint8_t unvmcap[16]; 1032c26f2173SKlaus Jensen uint32_t rpmbs; 1033c26f2173SKlaus Jensen uint16_t edstt; 1034c26f2173SKlaus Jensen uint8_t dsto; 1035c26f2173SKlaus Jensen uint8_t fwug; 1036c26f2173SKlaus Jensen uint16_t kas; 1037c26f2173SKlaus Jensen uint16_t hctma; 1038c26f2173SKlaus Jensen uint16_t mntmt; 1039c26f2173SKlaus Jensen uint16_t mxtmt; 1040c26f2173SKlaus Jensen uint32_t sanicap; 1041c26f2173SKlaus Jensen uint8_t rsvd332[180]; 1042a3d9a352SFam Zheng uint8_t sqes; 1043a3d9a352SFam Zheng uint8_t cqes; 1044c26f2173SKlaus Jensen uint16_t maxcmd; 1045a3d9a352SFam Zheng uint32_t nn; 1046a3d9a352SFam Zheng uint16_t oncs; 1047a3d9a352SFam Zheng uint16_t fuses; 1048a3d9a352SFam Zheng uint8_t fna; 1049a3d9a352SFam Zheng uint8_t vwc; 1050a3d9a352SFam Zheng uint16_t awun; 1051a3d9a352SFam Zheng uint16_t awupf; 1052c26f2173SKlaus Jensen uint8_t nvscc; 1053c26f2173SKlaus Jensen uint8_t rsvd531; 1054c26f2173SKlaus Jensen uint16_t acwu; 10553862efffSKlaus Jensen uint16_t ocfs; 1056c26f2173SKlaus Jensen uint32_t sgls; 1057c26f2173SKlaus Jensen uint8_t rsvd540[228]; 1058c26f2173SKlaus Jensen uint8_t subnqn[256]; 1059c26f2173SKlaus Jensen uint8_t rsvd1024[1024]; 1060a3d9a352SFam Zheng NvmePSD psd[32]; 1061a3d9a352SFam Zheng uint8_t vs[1024]; 1062a3d9a352SFam Zheng } NvmeIdCtrl; 1063a3d9a352SFam Zheng 1064e9ba46eeSDmitry Fomichev typedef struct NvmeIdCtrlZoned { 1065e9ba46eeSDmitry Fomichev uint8_t zasl; 1066e9ba46eeSDmitry Fomichev uint8_t rsvd1[4095]; 1067e9ba46eeSDmitry Fomichev } NvmeIdCtrlZoned; 1068e9ba46eeSDmitry Fomichev 106967ce28a1SGollu Appalanaidu typedef struct NvmeIdCtrlNvm { 107067ce28a1SGollu Appalanaidu uint8_t vsl; 107167ce28a1SGollu Appalanaidu uint8_t wzsl; 107267ce28a1SGollu Appalanaidu uint8_t wusl; 107367ce28a1SGollu Appalanaidu uint8_t dmrl; 107467ce28a1SGollu Appalanaidu uint32_t dmrsl; 107567ce28a1SGollu Appalanaidu uint64_t dmsl; 107667ce28a1SGollu Appalanaidu uint8_t rsvd16[4080]; 107767ce28a1SGollu Appalanaidu } NvmeIdCtrlNvm; 107867ce28a1SGollu Appalanaidu 1079f432fdfaSMinwoo Im enum NvmeIdCtrlOaes { 1080f432fdfaSMinwoo Im NVME_OAES_NS_ATTR = 1 << 8, 1081f432fdfaSMinwoo Im }; 1082f432fdfaSMinwoo Im 1083a3d9a352SFam Zheng enum NvmeIdCtrlOacs { 1084a3d9a352SFam Zheng NVME_OACS_SECURITY = 1 << 0, 1085a3d9a352SFam Zheng NVME_OACS_FORMAT = 1 << 1, 1086a3d9a352SFam Zheng NVME_OACS_FW = 1 << 2, 1087645ce1a7SMinwoo Im NVME_OACS_NS_MGMT = 1 << 3, 1088a3d9a352SFam Zheng }; 1089a3d9a352SFam Zheng 1090a3d9a352SFam Zheng enum NvmeIdCtrlOncs { 1091a3d9a352SFam Zheng NVME_ONCS_COMPARE = 1 << 0, 1092a3d9a352SFam Zheng NVME_ONCS_WRITE_UNCORR = 1 << 1, 1093a3d9a352SFam Zheng NVME_ONCS_DSM = 1 << 2, 109469265150SKlaus Jensen NVME_ONCS_WRITE_ZEROES = 1 << 3, 1095a3d9a352SFam Zheng NVME_ONCS_FEATURES = 1 << 4, 1096a3d9a352SFam Zheng NVME_ONCS_RESRVATIONS = 1 << 5, 10973036a626SKenneth Heitke NVME_ONCS_TIMESTAMP = 1 << 6, 10983e1da158SGollu Appalanaidu NVME_ONCS_VERIFY = 1 << 7, 10993862efffSKlaus Jensen NVME_ONCS_COPY = 1 << 8, 11003862efffSKlaus Jensen }; 11013862efffSKlaus Jensen 11023862efffSKlaus Jensen enum NvmeIdCtrlOcfs { 11033862efffSKlaus Jensen NVME_OCFS_COPY_FORMAT_0 = 1 << 0, 1104a3d9a352SFam Zheng }; 1105a3d9a352SFam Zheng 1106c9497328SGollu Appalanaidu enum NvmeIdctrlVwc { 1107c9497328SGollu Appalanaidu NVME_VWC_PRESENT = 1 << 0, 1108c9497328SGollu Appalanaidu NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1, 1109c9497328SGollu Appalanaidu NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1, 1110c9497328SGollu Appalanaidu NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1, 1111c9497328SGollu Appalanaidu NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1, 1112c9497328SGollu Appalanaidu }; 1113c9497328SGollu Appalanaidu 111442a42e46SKlaus Jensen enum NvmeIdCtrlFrmw { 111542a42e46SKlaus Jensen NVME_FRMW_SLOT1_RO = 1 << 0, 111642a42e46SKlaus Jensen }; 111742a42e46SKlaus Jensen 111894a7897cSKlaus Jensen enum NvmeIdCtrlLpa { 11192fbbecc5SKeith Busch NVME_LPA_NS_SMART = 1 << 0, 112062e8faa4SDmitry Fomichev NVME_LPA_CSE = 1 << 1, 112194a7897cSKlaus Jensen NVME_LPA_EXTENDED = 1 << 2, 112294a7897cSKlaus Jensen }; 112394a7897cSKlaus Jensen 112466b7e9beSMinwoo Im enum NvmeIdCtrlCmic { 112566b7e9beSMinwoo Im NVME_CMIC_MULTI_CTRL = 1 << 1, 112666b7e9beSMinwoo Im }; 112766b7e9beSMinwoo Im 1128a3d9a352SFam Zheng #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 1129a3d9a352SFam Zheng #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 1130a3d9a352SFam Zheng #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 1131a3d9a352SFam Zheng #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 1132a3d9a352SFam Zheng 1133c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 1134c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 1135c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 1136c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 1137c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 1138c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 1139c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 1140c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 1141c26f2173SKlaus Jensen #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 1142c26f2173SKlaus Jensen 1143a3d9a352SFam Zheng #define NVME_ARB_AB(arb) (arb & 0x7) 11441302e48eSKlaus Jensen #define NVME_ARB_AB_NOLIMIT 0x7 1145a3d9a352SFam Zheng #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 1146a3d9a352SFam Zheng #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 1147a3d9a352SFam Zheng #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 1148a3d9a352SFam Zheng 1149a3d9a352SFam Zheng #define NVME_INTC_THR(intc) (intc & 0xff) 1150a3d9a352SFam Zheng #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 1151a3d9a352SFam Zheng 11521302e48eSKlaus Jensen #define NVME_INTVC_NOCOALESCING (0x1 << 16) 11531302e48eSKlaus Jensen 1154c26f2173SKlaus Jensen #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 1155c26f2173SKlaus Jensen #define NVME_TEMP_THSEL_OVER 0x0 1156c26f2173SKlaus Jensen #define NVME_TEMP_THSEL_UNDER 0x1 1157c26f2173SKlaus Jensen 1158c26f2173SKlaus Jensen #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 1159c26f2173SKlaus Jensen #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 1160c26f2173SKlaus Jensen 1161c26f2173SKlaus Jensen #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 1162c26f2173SKlaus Jensen 11635d5a5330SKlaus Jensen #define NVME_AEC_SMART(aec) (aec & 0xff) 11645d5a5330SKlaus Jensen #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 11655d5a5330SKlaus Jensen #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 11665d5a5330SKlaus Jensen 116754064e51SKlaus Jensen #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) 116854064e51SKlaus Jensen #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) 116954064e51SKlaus Jensen 1170a3d9a352SFam Zheng enum NvmeFeatureIds { 1171a3d9a352SFam Zheng NVME_ARBITRATION = 0x1, 1172a3d9a352SFam Zheng NVME_POWER_MANAGEMENT = 0x2, 1173a3d9a352SFam Zheng NVME_LBA_RANGE_TYPE = 0x3, 1174a3d9a352SFam Zheng NVME_TEMPERATURE_THRESHOLD = 0x4, 1175a3d9a352SFam Zheng NVME_ERROR_RECOVERY = 0x5, 1176a3d9a352SFam Zheng NVME_VOLATILE_WRITE_CACHE = 0x6, 1177a3d9a352SFam Zheng NVME_NUMBER_OF_QUEUES = 0x7, 1178a3d9a352SFam Zheng NVME_INTERRUPT_COALESCING = 0x8, 1179a3d9a352SFam Zheng NVME_INTERRUPT_VECTOR_CONF = 0x9, 1180a3d9a352SFam Zheng NVME_WRITE_ATOMICITY = 0xa, 1181a3d9a352SFam Zheng NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 11823036a626SKenneth Heitke NVME_TIMESTAMP = 0xe, 1183141354d5SNiklas Cassel NVME_COMMAND_SET_PROFILE = 0x19, 11841302e48eSKlaus Jensen NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 11851302e48eSKlaus Jensen NVME_FID_MAX = 0x100, 1186a3d9a352SFam Zheng }; 1187a3d9a352SFam Zheng 11887c46310dSKlaus Jensen typedef enum NvmeFeatureCap { 11897c46310dSKlaus Jensen NVME_FEAT_CAP_SAVE = 1 << 0, 11907c46310dSKlaus Jensen NVME_FEAT_CAP_NS = 1 << 1, 11917c46310dSKlaus Jensen NVME_FEAT_CAP_CHANGE = 1 << 2, 11927c46310dSKlaus Jensen } NvmeFeatureCap; 11937c46310dSKlaus Jensen 11947c46310dSKlaus Jensen typedef enum NvmeGetFeatureSelect { 11957c46310dSKlaus Jensen NVME_GETFEAT_SELECT_CURRENT = 0x0, 11967c46310dSKlaus Jensen NVME_GETFEAT_SELECT_DEFAULT = 0x1, 11977c46310dSKlaus Jensen NVME_GETFEAT_SELECT_SAVED = 0x2, 11987c46310dSKlaus Jensen NVME_GETFEAT_SELECT_CAP = 0x3, 11997c46310dSKlaus Jensen } NvmeGetFeatureSelect; 12007c46310dSKlaus Jensen 12011302e48eSKlaus Jensen #define NVME_GETSETFEAT_FID_MASK 0xff 12021302e48eSKlaus Jensen #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 12031302e48eSKlaus Jensen 12047c46310dSKlaus Jensen #define NVME_GETFEAT_SELECT_SHIFT 8 12057c46310dSKlaus Jensen #define NVME_GETFEAT_SELECT_MASK 0x7 12067c46310dSKlaus Jensen #define NVME_GETFEAT_SELECT(dw10) \ 12077c46310dSKlaus Jensen ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 12087c46310dSKlaus Jensen 12097c46310dSKlaus Jensen #define NVME_SETFEAT_SAVE_SHIFT 31 12107c46310dSKlaus Jensen #define NVME_SETFEAT_SAVE_MASK 0x1 12117c46310dSKlaus Jensen #define NVME_SETFEAT_SAVE(dw10) \ 12127c46310dSKlaus Jensen ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 12137c46310dSKlaus Jensen 1214e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeRangeType { 1215a3d9a352SFam Zheng uint8_t type; 1216a3d9a352SFam Zheng uint8_t attributes; 1217a3d9a352SFam Zheng uint8_t rsvd2[14]; 1218a3d9a352SFam Zheng uint64_t slba; 1219a3d9a352SFam Zheng uint64_t nlb; 1220a3d9a352SFam Zheng uint8_t guid[16]; 1221a3d9a352SFam Zheng uint8_t rsvd48[16]; 1222a3d9a352SFam Zheng } NvmeRangeType; 1223a3d9a352SFam Zheng 1224e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeLBAF { 1225a3d9a352SFam Zheng uint16_t ms; 1226a3d9a352SFam Zheng uint8_t ds; 1227a3d9a352SFam Zheng uint8_t rp; 1228a3d9a352SFam Zheng } NvmeLBAF; 1229a3d9a352SFam Zheng 1230e9ba46eeSDmitry Fomichev typedef struct QEMU_PACKED NvmeLBAFE { 1231e9ba46eeSDmitry Fomichev uint64_t zsze; 1232e9ba46eeSDmitry Fomichev uint8_t zdes; 1233e9ba46eeSDmitry Fomichev uint8_t rsvd9[7]; 1234e9ba46eeSDmitry Fomichev } NvmeLBAFE; 1235e9ba46eeSDmitry Fomichev 12367c46310dSKlaus Jensen #define NVME_NSID_BROADCAST 0xffffffff 12377c46310dSKlaus Jensen 1238e989738fSPhilippe Mathieu-Daudé typedef struct QEMU_PACKED NvmeIdNs { 1239a3d9a352SFam Zheng uint64_t nsze; 1240a3d9a352SFam Zheng uint64_t ncap; 1241a3d9a352SFam Zheng uint64_t nuse; 1242a3d9a352SFam Zheng uint8_t nsfeat; 1243a3d9a352SFam Zheng uint8_t nlbaf; 1244a3d9a352SFam Zheng uint8_t flbas; 1245a3d9a352SFam Zheng uint8_t mc; 1246a3d9a352SFam Zheng uint8_t dpc; 1247a3d9a352SFam Zheng uint8_t dps; 1248e0dd95e3SMaxim Levitsky uint8_t nmic; 1249e0dd95e3SMaxim Levitsky uint8_t rescap; 1250e0dd95e3SMaxim Levitsky uint8_t fpi; 1251e0dd95e3SMaxim Levitsky uint8_t dlfeat; 1252c26f2173SKlaus Jensen uint16_t nawun; 1253c26f2173SKlaus Jensen uint16_t nawupf; 1254c26f2173SKlaus Jensen uint16_t nacwu; 1255c26f2173SKlaus Jensen uint16_t nabsn; 1256c26f2173SKlaus Jensen uint16_t nabo; 1257c26f2173SKlaus Jensen uint16_t nabspf; 1258c26f2173SKlaus Jensen uint16_t noiob; 1259c26f2173SKlaus Jensen uint8_t nvmcap[16]; 12606fd704a5SKlaus Jensen uint16_t npwg; 12616fd704a5SKlaus Jensen uint16_t npwa; 12626fd704a5SKlaus Jensen uint16_t npdg; 12636fd704a5SKlaus Jensen uint16_t npda; 12646fd704a5SKlaus Jensen uint16_t nows; 12653862efffSKlaus Jensen uint16_t mssrl; 12663862efffSKlaus Jensen uint32_t mcl; 12673862efffSKlaus Jensen uint8_t msrc; 12683862efffSKlaus Jensen uint8_t rsvd81[23]; 1269c26f2173SKlaus Jensen uint8_t nguid[16]; 1270c26f2173SKlaus Jensen uint64_t eui64; 1271a3d9a352SFam Zheng NvmeLBAF lbaf[16]; 1272c26f2173SKlaus Jensen uint8_t rsvd192[192]; 1273a3d9a352SFam Zheng uint8_t vs[3712]; 1274a3d9a352SFam Zheng } NvmeIdNs; 1275a3d9a352SFam Zheng 1276c26f2173SKlaus Jensen typedef struct QEMU_PACKED NvmeIdNsDescr { 1277c26f2173SKlaus Jensen uint8_t nidt; 1278c26f2173SKlaus Jensen uint8_t nidl; 1279c26f2173SKlaus Jensen uint8_t rsvd2[2]; 1280c26f2173SKlaus Jensen } NvmeIdNsDescr; 1281c26f2173SKlaus Jensen 1282141354d5SNiklas Cassel enum NvmeNsIdentifierLength { 1283141354d5SNiklas Cassel NVME_NIDL_EUI64 = 8, 1284141354d5SNiklas Cassel NVME_NIDL_NGUID = 16, 1285141354d5SNiklas Cassel NVME_NIDL_UUID = 16, 1286141354d5SNiklas Cassel NVME_NIDL_CSI = 1, 1287c26f2173SKlaus Jensen }; 1288c26f2173SKlaus Jensen 1289c26f2173SKlaus Jensen enum NvmeNsIdentifierType { 1290141354d5SNiklas Cassel NVME_NIDT_EUI64 = 0x01, 1291141354d5SNiklas Cassel NVME_NIDT_NGUID = 0x02, 1292141354d5SNiklas Cassel NVME_NIDT_UUID = 0x03, 1293141354d5SNiklas Cassel NVME_NIDT_CSI = 0x04, 1294c26f2173SKlaus Jensen }; 1295e0dd95e3SMaxim Levitsky 1296adc36b8dSMinwoo Im enum NvmeIdNsNmic { 1297adc36b8dSMinwoo Im NVME_NMIC_NS_SHARED = 1 << 0, 1298adc36b8dSMinwoo Im }; 1299adc36b8dSMinwoo Im 1300141354d5SNiklas Cassel enum NvmeCsi { 1301141354d5SNiklas Cassel NVME_CSI_NVM = 0x00, 1302e9ba46eeSDmitry Fomichev NVME_CSI_ZONED = 0x02, 1303141354d5SNiklas Cassel }; 1304141354d5SNiklas Cassel 1305141354d5SNiklas Cassel #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) 1306141354d5SNiklas Cassel 1307e9ba46eeSDmitry Fomichev typedef struct QEMU_PACKED NvmeIdNsZoned { 1308e9ba46eeSDmitry Fomichev uint16_t zoc; 1309e9ba46eeSDmitry Fomichev uint16_t ozcs; 1310e9ba46eeSDmitry Fomichev uint32_t mar; 1311e9ba46eeSDmitry Fomichev uint32_t mor; 1312e9ba46eeSDmitry Fomichev uint32_t rrl; 1313e9ba46eeSDmitry Fomichev uint32_t frl; 1314e9ba46eeSDmitry Fomichev uint8_t rsvd20[2796]; 1315e9ba46eeSDmitry Fomichev NvmeLBAFE lbafe[16]; 1316e9ba46eeSDmitry Fomichev uint8_t rsvd3072[768]; 1317e9ba46eeSDmitry Fomichev uint8_t vs[256]; 1318e9ba46eeSDmitry Fomichev } NvmeIdNsZoned; 1319e9ba46eeSDmitry Fomichev 1320e0dd95e3SMaxim Levitsky /*Deallocate Logical Block Features*/ 1321e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1322e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1323e0dd95e3SMaxim Levitsky 1324e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1325e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1326e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1327e0dd95e3SMaxim Levitsky #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1328e0dd95e3SMaxim Levitsky 1329e0dd95e3SMaxim Levitsky 1330a3d9a352SFam Zheng #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 133154064e51SKlaus Jensen #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) 1332a3d9a352SFam Zheng #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1333a3d9a352SFam Zheng #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1334a3d9a352SFam Zheng #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1335a3d9a352SFam Zheng #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1336a3d9a352SFam Zheng #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1337a3d9a352SFam Zheng #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1338a3d9a352SFam Zheng #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1339a3d9a352SFam Zheng #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1340a3d9a352SFam Zheng #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1341a3d9a352SFam Zheng #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1342a3d9a352SFam Zheng 1343a3d9a352SFam Zheng enum NvmeIdNsDps { 1344146f720cSKlaus Jensen NVME_ID_NS_DPS_TYPE_NONE = 0, 1345146f720cSKlaus Jensen NVME_ID_NS_DPS_TYPE_1 = 1, 1346146f720cSKlaus Jensen NVME_ID_NS_DPS_TYPE_2 = 2, 1347146f720cSKlaus Jensen NVME_ID_NS_DPS_TYPE_3 = 3, 1348146f720cSKlaus Jensen NVME_ID_NS_DPS_TYPE_MASK = 0x7, 1349146f720cSKlaus Jensen NVME_ID_NS_DPS_FIRST_EIGHT = 8, 1350a3d9a352SFam Zheng }; 1351a3d9a352SFam Zheng 135218de1526SGollu Appalanaidu enum NvmeIdNsFlbas { 135318de1526SGollu Appalanaidu NVME_ID_NS_FLBAS_EXTENDED = 1 << 4, 135418de1526SGollu Appalanaidu }; 135518de1526SGollu Appalanaidu 135618de1526SGollu Appalanaidu enum NvmeIdNsMc { 135718de1526SGollu Appalanaidu NVME_ID_NS_MC_EXTENDED = 1 << 0, 135818de1526SGollu Appalanaidu NVME_ID_NS_MC_SEPARATE = 1 << 1, 135918de1526SGollu Appalanaidu }; 136018de1526SGollu Appalanaidu 1361146f720cSKlaus Jensen #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK) 1362146f720cSKlaus Jensen 1363146f720cSKlaus Jensen typedef struct NvmeDifTuple { 1364146f720cSKlaus Jensen uint16_t guard; 1365146f720cSKlaus Jensen uint16_t apptag; 1366146f720cSKlaus Jensen uint32_t reftag; 1367146f720cSKlaus Jensen } NvmeDifTuple; 1368146f720cSKlaus Jensen 1369e9ba46eeSDmitry Fomichev enum NvmeZoneAttr { 1370e9ba46eeSDmitry Fomichev NVME_ZA_FINISHED_BY_CTLR = 1 << 0, 1371e9ba46eeSDmitry Fomichev NVME_ZA_FINISH_RECOMMENDED = 1 << 1, 1372e9ba46eeSDmitry Fomichev NVME_ZA_RESET_RECOMMENDED = 1 << 2, 1373e9ba46eeSDmitry Fomichev NVME_ZA_ZD_EXT_VALID = 1 << 7, 1374e9ba46eeSDmitry Fomichev }; 1375e9ba46eeSDmitry Fomichev 1376e9ba46eeSDmitry Fomichev typedef struct QEMU_PACKED NvmeZoneReportHeader { 1377e9ba46eeSDmitry Fomichev uint64_t nr_zones; 1378e9ba46eeSDmitry Fomichev uint8_t rsvd[56]; 1379e9ba46eeSDmitry Fomichev } NvmeZoneReportHeader; 1380e9ba46eeSDmitry Fomichev 1381e9ba46eeSDmitry Fomichev enum NvmeZoneReceiveAction { 1382e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT = 0, 1383e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_EXTENDED = 1, 1384e9ba46eeSDmitry Fomichev }; 1385e9ba46eeSDmitry Fomichev 1386e9ba46eeSDmitry Fomichev enum NvmeZoneReportType { 1387e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_ALL = 0, 1388e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_EMPTY = 1, 1389e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, 1390e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, 1391e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_CLOSED = 4, 1392e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_FULL = 5, 1393e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_READ_ONLY = 6, 1394e9ba46eeSDmitry Fomichev NVME_ZONE_REPORT_OFFLINE = 7, 1395e9ba46eeSDmitry Fomichev }; 1396e9ba46eeSDmitry Fomichev 1397e9ba46eeSDmitry Fomichev enum NvmeZoneType { 1398e9ba46eeSDmitry Fomichev NVME_ZONE_TYPE_RESERVED = 0x00, 1399e9ba46eeSDmitry Fomichev NVME_ZONE_TYPE_SEQ_WRITE = 0x02, 1400e9ba46eeSDmitry Fomichev }; 1401e9ba46eeSDmitry Fomichev 1402e9ba46eeSDmitry Fomichev enum NvmeZoneSendAction { 1403e9ba46eeSDmitry Fomichev NVME_ZONE_ACTION_RSD = 0x00, 1404e9ba46eeSDmitry Fomichev NVME_ZONE_ACTION_CLOSE = 0x01, 1405e9ba46eeSDmitry Fomichev NVME_ZONE_ACTION_FINISH = 0x02, 1406e9ba46eeSDmitry Fomichev NVME_ZONE_ACTION_OPEN = 0x03, 1407e9ba46eeSDmitry Fomichev NVME_ZONE_ACTION_RESET = 0x04, 1408e9ba46eeSDmitry Fomichev NVME_ZONE_ACTION_OFFLINE = 0x05, 1409e9ba46eeSDmitry Fomichev NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, 1410e9ba46eeSDmitry Fomichev }; 1411e9ba46eeSDmitry Fomichev 1412e9ba46eeSDmitry Fomichev typedef struct QEMU_PACKED NvmeZoneDescr { 1413e9ba46eeSDmitry Fomichev uint8_t zt; 1414e9ba46eeSDmitry Fomichev uint8_t zs; 1415e9ba46eeSDmitry Fomichev uint8_t za; 1416e9ba46eeSDmitry Fomichev uint8_t rsvd3[5]; 1417e9ba46eeSDmitry Fomichev uint64_t zcap; 1418e9ba46eeSDmitry Fomichev uint64_t zslba; 1419e9ba46eeSDmitry Fomichev uint64_t wp; 1420e9ba46eeSDmitry Fomichev uint8_t rsvd32[32]; 1421e9ba46eeSDmitry Fomichev } NvmeZoneDescr; 1422e9ba46eeSDmitry Fomichev 1423b05fde28SKlaus Jensen typedef enum NvmeZoneState { 1424e9ba46eeSDmitry Fomichev NVME_ZONE_STATE_RESERVED = 0x00, 1425e9ba46eeSDmitry Fomichev NVME_ZONE_STATE_EMPTY = 0x01, 1426e9ba46eeSDmitry Fomichev NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, 1427e9ba46eeSDmitry Fomichev NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, 1428e9ba46eeSDmitry Fomichev NVME_ZONE_STATE_CLOSED = 0x04, 1429312c3531SGollu Appalanaidu NVME_ZONE_STATE_READ_ONLY = 0x0d, 1430312c3531SGollu Appalanaidu NVME_ZONE_STATE_FULL = 0x0e, 1431312c3531SGollu Appalanaidu NVME_ZONE_STATE_OFFLINE = 0x0f, 1432b05fde28SKlaus Jensen } NvmeZoneState; 1433e9ba46eeSDmitry Fomichev 1434a3d9a352SFam Zheng static inline void _nvme_check_size(void) 1435a3d9a352SFam Zheng { 143674e18435SPhilippe Mathieu-Daudé QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1437a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1438e9ba46eeSDmitry Fomichev QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); 1439a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1440a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 14413862efffSKlaus Jensen QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRange) != 32); 1442a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1443a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1444a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1445a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1446a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1447a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1448a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 14493862efffSKlaus Jensen QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64); 1450a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1451a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1452a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1453a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 145462e8faa4SDmitry Fomichev QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); 1455a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1456e9ba46eeSDmitry Fomichev QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); 145767ce28a1SGollu Appalanaidu QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096); 1458e9ba46eeSDmitry Fomichev QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); 1459e9ba46eeSDmitry Fomichev QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); 1460a3d9a352SFam Zheng QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1461e9ba46eeSDmitry Fomichev QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); 1462c26f2173SKlaus Jensen QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1463c26f2173SKlaus Jensen QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1464e9ba46eeSDmitry Fomichev QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); 1465146f720cSKlaus Jensen QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 8); 1466a3d9a352SFam Zheng } 1467a3d9a352SFam Zheng #endif 1468