1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/block/flash.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "qemu/error-report.h" 32 #include "qapi/error.h" 33 #include "qemu/units.h" 34 #include "trace.h" 35 36 #include "hw/irq.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ssi/aspeed_smc.h" 39 40 /* CE Type Setting Register */ 41 #define R_CONF (0x00 / 4) 42 #define CONF_LEGACY_DISABLE (1 << 31) 43 #define CONF_ENABLE_W4 20 44 #define CONF_ENABLE_W3 19 45 #define CONF_ENABLE_W2 18 46 #define CONF_ENABLE_W1 17 47 #define CONF_ENABLE_W0 16 48 #define CONF_FLASH_TYPE4 8 49 #define CONF_FLASH_TYPE3 6 50 #define CONF_FLASH_TYPE2 4 51 #define CONF_FLASH_TYPE1 2 52 #define CONF_FLASH_TYPE0 0 53 #define CONF_FLASH_TYPE_NOR 0x0 54 #define CONF_FLASH_TYPE_NAND 0x1 55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */ 56 57 /* CE Control Register */ 58 #define R_CE_CTRL (0x04 / 4) 59 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */ 60 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */ 61 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */ 62 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */ 63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */ 64 65 /* Interrupt Control and Status Register */ 66 #define R_INTR_CTRL (0x08 / 4) 67 #define INTR_CTRL_DMA_STATUS (1 << 11) 68 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10) 69 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9) 70 #define INTR_CTRL_DMA_EN (1 << 3) 71 #define INTR_CTRL_CMD_ABORT_EN (1 << 2) 72 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) 73 74 /* Command Control Register */ 75 #define R_CE_CMD_CTRL (0x0C / 4) 76 #define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4 77 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0 78 79 #define aspeed_smc_addr_byte_enabled(s, i) \ 80 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i))))) 81 #define aspeed_smc_data_byte_enabled(s, i) \ 82 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i))))) 83 84 /* CEx Control Register */ 85 #define R_CTRL0 (0x10 / 4) 86 #define CTRL_IO_QPI (1 << 31) 87 #define CTRL_IO_QUAD_DATA (1 << 30) 88 #define CTRL_IO_DUAL_DATA (1 << 29) 89 #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ 90 #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */ 91 #define CTRL_CMD_SHIFT 16 92 #define CTRL_CMD_MASK 0xff 93 #define CTRL_DUMMY_HIGH_SHIFT 14 94 #define CTRL_AST2400_SPI_4BYTE (1 << 13) 95 #define CE_CTRL_CLOCK_FREQ_SHIFT 8 96 #define CE_CTRL_CLOCK_FREQ_MASK 0xf 97 #define CE_CTRL_CLOCK_FREQ(div) \ 98 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 99 #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 100 #define CTRL_CE_STOP_ACTIVE (1 << 2) 101 #define CTRL_CMD_MODE_MASK 0x3 102 #define CTRL_READMODE 0x0 103 #define CTRL_FREADMODE 0x1 104 #define CTRL_WRITEMODE 0x2 105 #define CTRL_USERMODE 0x3 106 #define R_CTRL1 (0x14 / 4) 107 #define R_CTRL2 (0x18 / 4) 108 #define R_CTRL3 (0x1C / 4) 109 #define R_CTRL4 (0x20 / 4) 110 111 /* CEx Segment Address Register */ 112 #define R_SEG_ADDR0 (0x30 / 4) 113 #define SEG_END_SHIFT 24 /* 8MB units */ 114 #define SEG_END_MASK 0xff 115 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */ 116 #define SEG_START_MASK 0xff 117 #define R_SEG_ADDR1 (0x34 / 4) 118 #define R_SEG_ADDR2 (0x38 / 4) 119 #define R_SEG_ADDR3 (0x3C / 4) 120 #define R_SEG_ADDR4 (0x40 / 4) 121 122 /* Misc Control Register #1 */ 123 #define R_MISC_CTRL1 (0x50 / 4) 124 125 /* SPI dummy cycle data */ 126 #define R_DUMMY_DATA (0x54 / 4) 127 128 /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */ 129 #define R_FMC_WDT2_CTRL (0x64 / 4) 130 #define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */ 131 #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5) 132 #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */ 133 #define FMC_WDT2_CTRL_EN BIT(0) 134 135 /* DMA Control/Status Register */ 136 #define R_DMA_CTRL (0x80 / 4) 137 #define DMA_CTRL_REQUEST (1 << 31) 138 #define DMA_CTRL_GRANT (1 << 30) 139 #define DMA_CTRL_DELAY_MASK 0xf 140 #define DMA_CTRL_DELAY_SHIFT 8 141 #define DMA_CTRL_FREQ_MASK 0xf 142 #define DMA_CTRL_FREQ_SHIFT 4 143 #define DMA_CTRL_CALIB (1 << 3) 144 #define DMA_CTRL_CKSUM (1 << 2) 145 #define DMA_CTRL_WRITE (1 << 1) 146 #define DMA_CTRL_ENABLE (1 << 0) 147 148 /* DMA Flash Side Address */ 149 #define R_DMA_FLASH_ADDR (0x84 / 4) 150 151 /* DMA DRAM Side Address */ 152 #define R_DMA_DRAM_ADDR (0x88 / 4) 153 154 /* DMA Length Register */ 155 #define R_DMA_LEN (0x8C / 4) 156 157 /* Checksum Calculation Result */ 158 #define R_DMA_CHECKSUM (0x90 / 4) 159 160 /* Read Timing Compensation Register */ 161 #define R_TIMINGS (0x94 / 4) 162 163 /* SPI controller registers and bits (AST2400) */ 164 #define R_SPI_CONF (0x00 / 4) 165 #define SPI_CONF_ENABLE_W0 0 166 #define R_SPI_CTRL0 (0x4 / 4) 167 #define R_SPI_MISC_CTRL (0x10 / 4) 168 #define R_SPI_TIMINGS (0x14 / 4) 169 170 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4) 171 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4) 172 173 /* 174 * DMA DRAM addresses should be 4 bytes aligned and the valid address 175 * range is 0x40000000 - 0x5FFFFFFF (AST2400) 176 * 0x80000000 - 0xBFFFFFFF (AST2500) 177 * 178 * DMA flash addresses should be 4 bytes aligned and the valid address 179 * range is 0x20000000 - 0x2FFFFFFF. 180 * 181 * DMA length is from 4 bytes to 32MB (AST2500) 182 * 0: 4 bytes 183 * 0x1FFFFFC: 32M bytes 184 * 185 * DMA length is from 1 byte to 32MB (AST2600, AST10x0) 186 * 0: 1 byte 187 * 0x1FFFFFF: 32M bytes 188 */ 189 #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask) 190 #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask) 191 #define DMA_LENGTH(val) ((val) & 0x01FFFFFF) 192 193 /* Flash opcodes. */ 194 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ 195 196 #define SNOOP_OFF 0xFF 197 #define SNOOP_START 0x0 198 199 /* 200 * Default segments mapping addresses and size for each peripheral per 201 * controller. These can be changed when board is initialized with the 202 * Segment Address Registers. 203 */ 204 static const AspeedSegments aspeed_2500_spi1_segments[]; 205 static const AspeedSegments aspeed_2500_spi2_segments[]; 206 207 #define ASPEED_SMC_FEATURE_DMA 0x1 208 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 209 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4 210 211 static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc) 212 { 213 return !!(asc->features & ASPEED_SMC_FEATURE_DMA); 214 } 215 216 static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc) 217 { 218 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL); 219 } 220 221 #define aspeed_smc_error(fmt, ...) \ 222 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__) 223 224 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, 225 const AspeedSegments *new, 226 int cs) 227 { 228 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 229 AspeedSegments seg; 230 int i; 231 232 for (i = 0; i < asc->cs_num_max; i++) { 233 if (i == cs) { 234 continue; 235 } 236 237 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); 238 239 if (new->addr + new->size > seg.addr && 240 new->addr < seg.addr + seg.size) { 241 aspeed_smc_error("new segment CS%d [ 0x%" 242 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " 243 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 244 cs, new->addr, new->addr + new->size, 245 i, seg.addr, seg.addr + seg.size); 246 return true; 247 } 248 } 249 return false; 250 } 251 252 static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs, 253 uint64_t regval) 254 { 255 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 256 AspeedSMCFlash *fl = &s->flashes[cs]; 257 AspeedSegments seg; 258 259 asc->reg_to_segment(s, regval, &seg); 260 261 memory_region_transaction_begin(); 262 memory_region_set_size(&fl->mmio, seg.size); 263 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base); 264 memory_region_set_enabled(&fl->mmio, !!seg.size); 265 memory_region_transaction_commit(); 266 267 if (asc->segment_addr_mask) { 268 regval &= asc->segment_addr_mask; 269 } 270 271 s->regs[R_SEG_ADDR0 + cs] = regval; 272 } 273 274 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, 275 uint64_t new) 276 { 277 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 278 AspeedSegments seg; 279 280 asc->reg_to_segment(s, new, &seg); 281 282 trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size); 283 284 /* The start address of CS0 is read-only */ 285 if (cs == 0 && seg.addr != asc->flash_window_base) { 286 aspeed_smc_error("Tried to change CS0 start address to 0x%" 287 HWADDR_PRIx, seg.addr); 288 seg.addr = asc->flash_window_base; 289 new = asc->segment_to_reg(s, &seg); 290 } 291 292 /* 293 * The end address of the AST2500 spi controllers is also 294 * read-only. 295 */ 296 if ((asc->segments == aspeed_2500_spi1_segments || 297 asc->segments == aspeed_2500_spi2_segments) && 298 cs == asc->cs_num_max && 299 seg.addr + seg.size != asc->segments[cs].addr + 300 asc->segments[cs].size) { 301 aspeed_smc_error("Tried to change CS%d end address to 0x%" 302 HWADDR_PRIx, cs, seg.addr + seg.size); 303 seg.size = asc->segments[cs].addr + asc->segments[cs].size - 304 seg.addr; 305 new = asc->segment_to_reg(s, &seg); 306 } 307 308 /* Keep the segment in the overall flash window */ 309 if (seg.size && 310 (seg.addr + seg.size <= asc->flash_window_base || 311 seg.addr > asc->flash_window_base + asc->flash_window_size)) { 312 aspeed_smc_error("new segment for CS%d is invalid : " 313 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 314 cs, seg.addr, seg.addr + seg.size); 315 return; 316 } 317 318 /* Check start address vs. alignment */ 319 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) { 320 aspeed_smc_error("new segment for CS%d is not " 321 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 322 cs, seg.addr, seg.addr + seg.size); 323 } 324 325 /* And segments should not overlap (in the specs) */ 326 aspeed_smc_flash_overlap(s, &seg, cs); 327 328 /* All should be fine now to move the region */ 329 aspeed_smc_flash_set_segment_region(s, cs, new); 330 } 331 332 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, 333 unsigned size) 334 { 335 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size); 336 return 0; 337 } 338 339 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, 340 uint64_t data, unsigned size) 341 { 342 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64, 343 addr, size, data); 344 } 345 346 static const MemoryRegionOps aspeed_smc_flash_default_ops = { 347 .read = aspeed_smc_flash_default_read, 348 .write = aspeed_smc_flash_default_write, 349 .endianness = DEVICE_LITTLE_ENDIAN, 350 .valid = { 351 .min_access_size = 1, 352 .max_access_size = 4, 353 }, 354 }; 355 356 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl) 357 { 358 const AspeedSMCState *s = fl->controller; 359 360 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; 361 } 362 363 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl) 364 { 365 const AspeedSMCState *s = fl->controller; 366 367 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs)); 368 } 369 370 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl) 371 { 372 const AspeedSMCState *s = fl->controller; 373 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; 374 375 /* 376 * In read mode, the default SPI command is READ (0x3). In other 377 * modes, the command should necessarily be defined 378 * 379 * TODO: add support for READ4 (0x13) on AST2600 380 */ 381 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) { 382 cmd = SPI_OP_READ; 383 } 384 385 if (!cmd) { 386 aspeed_smc_error("no command defined for mode %d", 387 aspeed_smc_flash_mode(fl)); 388 } 389 390 return cmd; 391 } 392 393 static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl) 394 { 395 const AspeedSMCState *s = fl->controller; 396 AspeedSMCClass *asc = fl->asc; 397 398 if (asc->addr_width) { 399 return asc->addr_width(s); 400 } else { 401 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3; 402 } 403 } 404 405 static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect) 406 { 407 AspeedSMCState *s = fl->controller; 408 409 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : ""); 410 411 qemu_set_irq(s->cs_lines[fl->cs], unselect); 412 } 413 414 static void aspeed_smc_flash_select(AspeedSMCFlash *fl) 415 { 416 aspeed_smc_flash_do_select(fl, false); 417 } 418 419 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl) 420 { 421 aspeed_smc_flash_do_select(fl, true); 422 } 423 424 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, 425 uint32_t addr) 426 { 427 const AspeedSMCState *s = fl->controller; 428 AspeedSMCClass *asc = fl->asc; 429 AspeedSegments seg; 430 431 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg); 432 if ((addr % seg.size) != addr) { 433 aspeed_smc_error("invalid address 0x%08x for CS%d segment : " 434 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 435 addr, fl->cs, seg.addr, seg.addr + seg.size); 436 addr %= seg.size; 437 } 438 439 return addr; 440 } 441 442 static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl) 443 { 444 const AspeedSMCState *s = fl->controller; 445 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs]; 446 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; 447 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; 448 uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8; 449 450 if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) { 451 dummies /= 2; 452 } 453 454 return dummies; 455 } 456 457 static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) 458 { 459 const AspeedSMCState *s = fl->controller; 460 uint8_t cmd = aspeed_smc_flash_cmd(fl); 461 int i = aspeed_smc_flash_addr_width(fl); 462 463 /* Flash access can not exceed CS segment */ 464 addr = aspeed_smc_check_segment_addr(fl, addr); 465 466 ssi_transfer(s->spi, cmd); 467 while (i--) { 468 if (aspeed_smc_addr_byte_enabled(s, i)) { 469 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); 470 } 471 } 472 473 /* 474 * Use fake transfers to model dummy bytes. The value should 475 * be configured to some non-zero value in fast read mode and 476 * zero in read mode. But, as the HW allows inconsistent 477 * settings, let's check for fast read mode. 478 */ 479 if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { 480 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { 481 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); 482 } 483 } 484 } 485 486 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) 487 { 488 AspeedSMCFlash *fl = opaque; 489 AspeedSMCState *s = fl->controller; 490 uint64_t ret = 0; 491 int i; 492 493 switch (aspeed_smc_flash_mode(fl)) { 494 case CTRL_USERMODE: 495 for (i = 0; i < size; i++) { 496 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); 497 } 498 break; 499 case CTRL_READMODE: 500 case CTRL_FREADMODE: 501 aspeed_smc_flash_select(fl); 502 aspeed_smc_flash_setup(fl, addr); 503 504 for (i = 0; i < size; i++) { 505 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); 506 } 507 508 aspeed_smc_flash_unselect(fl); 509 break; 510 default: 511 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); 512 } 513 514 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret, 515 aspeed_smc_flash_mode(fl)); 516 return ret; 517 } 518 519 /* 520 * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a 521 * common include header. 522 */ 523 typedef enum { 524 READ = 0x3, READ_4 = 0x13, 525 FAST_READ = 0xb, FAST_READ_4 = 0x0c, 526 DOR = 0x3b, DOR_4 = 0x3c, 527 QOR = 0x6b, QOR_4 = 0x6c, 528 DIOR = 0xbb, DIOR_4 = 0xbc, 529 QIOR = 0xeb, QIOR_4 = 0xec, 530 531 PP = 0x2, PP_4 = 0x12, 532 DPP = 0xa2, 533 QPP = 0x32, QPP_4 = 0x34, 534 } FlashCMD; 535 536 static int aspeed_smc_num_dummies(uint8_t command) 537 { 538 switch (command) { /* check for dummies */ 539 case READ: /* no dummy bytes/cycles */ 540 case PP: 541 case DPP: 542 case QPP: 543 case READ_4: 544 case PP_4: 545 case QPP_4: 546 return 0; 547 case FAST_READ: 548 case DOR: 549 case QOR: 550 case FAST_READ_4: 551 case DOR_4: 552 case QOR_4: 553 return 1; 554 case DIOR: 555 case DIOR_4: 556 return 2; 557 case QIOR: 558 case QIOR_4: 559 return 4; 560 default: 561 return -1; 562 } 563 } 564 565 static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data, 566 unsigned size) 567 { 568 AspeedSMCState *s = fl->controller; 569 uint8_t addr_width = aspeed_smc_flash_addr_width(fl); 570 571 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies, 572 (uint8_t) data & 0xff); 573 574 if (s->snoop_index == SNOOP_OFF) { 575 return false; /* Do nothing */ 576 577 } else if (s->snoop_index == SNOOP_START) { 578 uint8_t cmd = data & 0xff; 579 int ndummies = aspeed_smc_num_dummies(cmd); 580 581 /* 582 * No dummy cycles are expected with the current command. Turn 583 * off snooping and let the transfer proceed normally. 584 */ 585 if (ndummies <= 0) { 586 s->snoop_index = SNOOP_OFF; 587 return false; 588 } 589 590 s->snoop_dummies = ndummies * 8; 591 592 } else if (s->snoop_index >= addr_width + 1) { 593 594 /* The SPI transfer has reached the dummy cycles sequence */ 595 for (; s->snoop_dummies; s->snoop_dummies--) { 596 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); 597 } 598 599 /* If no more dummy cycles are expected, turn off snooping */ 600 if (!s->snoop_dummies) { 601 s->snoop_index = SNOOP_OFF; 602 } else { 603 s->snoop_index += size; 604 } 605 606 /* 607 * Dummy cycles have been faked already. Ignore the current 608 * SPI transfer 609 */ 610 return true; 611 } 612 613 s->snoop_index += size; 614 return false; 615 } 616 617 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, 618 unsigned size) 619 { 620 AspeedSMCFlash *fl = opaque; 621 AspeedSMCState *s = fl->controller; 622 int i; 623 624 trace_aspeed_smc_flash_write(fl->cs, addr, size, data, 625 aspeed_smc_flash_mode(fl)); 626 627 if (!aspeed_smc_is_writable(fl)) { 628 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); 629 return; 630 } 631 632 switch (aspeed_smc_flash_mode(fl)) { 633 case CTRL_USERMODE: 634 if (aspeed_smc_do_snoop(fl, data, size)) { 635 break; 636 } 637 638 for (i = 0; i < size; i++) { 639 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); 640 } 641 break; 642 case CTRL_WRITEMODE: 643 aspeed_smc_flash_select(fl); 644 aspeed_smc_flash_setup(fl, addr); 645 646 for (i = 0; i < size; i++) { 647 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); 648 } 649 650 aspeed_smc_flash_unselect(fl); 651 break; 652 default: 653 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); 654 } 655 } 656 657 static const MemoryRegionOps aspeed_smc_flash_ops = { 658 .read = aspeed_smc_flash_read, 659 .write = aspeed_smc_flash_write, 660 .endianness = DEVICE_LITTLE_ENDIAN, 661 .valid = { 662 .min_access_size = 1, 663 .max_access_size = 4, 664 }, 665 }; 666 667 static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value) 668 { 669 AspeedSMCState *s = fl->controller; 670 bool unselect; 671 672 /* User mode selects the CS, other modes unselect */ 673 unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE; 674 675 /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ 676 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) && 677 value & CTRL_CE_STOP_ACTIVE) { 678 unselect = true; 679 } 680 681 s->regs[s->r_ctrl0 + fl->cs] = value; 682 683 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; 684 685 aspeed_smc_flash_do_select(fl, unselect); 686 } 687 688 static void aspeed_smc_reset(DeviceState *d) 689 { 690 AspeedSMCState *s = ASPEED_SMC(d); 691 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 692 int i; 693 694 if (asc->resets) { 695 memcpy(s->regs, asc->resets, sizeof s->regs); 696 } else { 697 memset(s->regs, 0, sizeof s->regs); 698 } 699 700 for (i = 0; i < asc->cs_num_max; i++) { 701 DeviceState *dev = ssi_get_cs(s->spi, i); 702 if (dev) { 703 Object *o = OBJECT(dev); 704 705 if (!object_dynamic_cast(o, TYPE_M25P80)) { 706 warn_report("Aspeed SMC %s.%d : Invalid %s device type", 707 BUS(s->spi)->name, i, object_get_typename(o)); 708 continue; 709 } 710 711 qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 712 qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line); 713 } 714 } 715 716 /* Unselect all peripherals */ 717 for (i = 0; i < asc->cs_num_max; ++i) { 718 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; 719 qemu_set_irq(s->cs_lines[i], true); 720 } 721 722 /* setup the default segment register values and regions for all */ 723 for (i = 0; i < asc->cs_num_max; ++i) { 724 aspeed_smc_flash_set_segment_region(s, i, 725 asc->segment_to_reg(s, &asc->segments[i])); 726 } 727 728 s->snoop_index = SNOOP_OFF; 729 s->snoop_dummies = 0; 730 } 731 732 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) 733 { 734 AspeedSMCState *s = ASPEED_SMC(opaque); 735 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque); 736 737 addr >>= 2; 738 739 if (addr == s->r_conf || 740 (addr >= s->r_timings && 741 addr < s->r_timings + asc->nregs_timings) || 742 addr == s->r_ce_ctrl || 743 addr == R_CE_CMD_CTRL || 744 addr == R_INTR_CTRL || 745 addr == R_DUMMY_DATA || 746 (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) || 747 (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) || 748 (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) || 749 (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) || 750 (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) || 751 (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) || 752 (addr >= R_SEG_ADDR0 && 753 addr < R_SEG_ADDR0 + asc->cs_num_max) || 754 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) { 755 756 trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); 757 758 return s->regs[addr]; 759 } else { 760 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", 761 __func__, addr); 762 return -1; 763 } 764 } 765 766 static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) 767 { 768 /* HCLK/1 .. HCLK/16 */ 769 const uint8_t hclk_divisors[] = { 770 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 771 }; 772 int i; 773 774 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { 775 if (hclk_mask == hclk_divisors[i]) { 776 return i + 1; 777 } 778 } 779 780 aspeed_smc_error("invalid HCLK mask %x", hclk_mask); 781 return 0; 782 } 783 784 /* 785 * When doing calibration, the SPI clock rate in the CE0 Control 786 * Register and the read delay cycles in the Read Timing Compensation 787 * Register are set using bit[11:4] of the DMA Control Register. 788 */ 789 static void aspeed_smc_dma_calibration(AspeedSMCState *s) 790 { 791 uint8_t delay = 792 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; 793 uint8_t hclk_mask = 794 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; 795 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask); 796 uint32_t hclk_shift = (hclk_div - 1) << 2; 797 uint8_t cs; 798 799 /* 800 * The Read Timing Compensation Register values apply to all CS on 801 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays 802 */ 803 if (hclk_div && hclk_div < 6) { 804 s->regs[s->r_timings] &= ~(0xf << hclk_shift); 805 s->regs[s->r_timings] |= delay << hclk_shift; 806 } 807 808 /* 809 * TODO: compute the CS from the DMA address and the segment 810 * registers. This is not really a problem for now because the 811 * Timing Register values apply to all CS and software uses CS0 to 812 * do calibration. 813 */ 814 cs = 0; 815 s->regs[s->r_ctrl0 + cs] &= 816 ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); 817 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); 818 } 819 820 /* 821 * Emulate read errors in the DMA Checksum Register for high 822 * frequencies and optimistic settings of the Read Timing Compensation 823 * Register. This will help in tuning the SPI timing calibration 824 * algorithm. 825 */ 826 static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) 827 { 828 uint8_t delay = 829 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; 830 uint8_t hclk_mask = 831 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; 832 833 /* 834 * Typical values of a palmetto-bmc machine. 835 */ 836 switch (aspeed_smc_hclk_divisor(hclk_mask)) { 837 case 4 ... 16: 838 return false; 839 case 3: /* at least one HCLK cycle delay */ 840 return (delay & 0x7) < 1; 841 case 2: /* at least two HCLK cycle delay */ 842 return (delay & 0x7) < 2; 843 case 1: /* (> 100MHz) is above the max freq of the controller */ 844 return true; 845 default: 846 g_assert_not_reached(); 847 } 848 } 849 850 static uint32_t aspeed_smc_dma_len(AspeedSMCState *s) 851 { 852 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 853 854 return QEMU_ALIGN_UP(s->regs[R_DMA_LEN] + asc->dma_start_length, 4); 855 } 856 857 /* 858 * Accumulate the result of the reads to provide a checksum that will 859 * be used to validate the read timing settings. 860 */ 861 static void aspeed_smc_dma_checksum(AspeedSMCState *s) 862 { 863 MemTxResult result; 864 uint32_t dma_len; 865 uint32_t data; 866 867 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { 868 aspeed_smc_error("invalid direction for DMA checksum"); 869 return; 870 } 871 872 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { 873 aspeed_smc_dma_calibration(s); 874 } 875 876 dma_len = aspeed_smc_dma_len(s); 877 878 while (dma_len) { 879 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 880 MEMTXATTRS_UNSPECIFIED, &result); 881 if (result != MEMTX_OK) { 882 aspeed_smc_error("Flash read failed @%08x", 883 s->regs[R_DMA_FLASH_ADDR]); 884 return; 885 } 886 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); 887 888 /* 889 * When the DMA is on-going, the DMA registers are updated 890 * with the current working addresses and length. 891 */ 892 s->regs[R_DMA_CHECKSUM] += data; 893 s->regs[R_DMA_FLASH_ADDR] += 4; 894 dma_len -= 4; 895 s->regs[R_DMA_LEN] = dma_len; 896 } 897 898 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { 899 s->regs[R_DMA_CHECKSUM] = 0xbadc0de; 900 } 901 902 } 903 904 static void aspeed_smc_dma_rw(AspeedSMCState *s) 905 { 906 MemTxResult result; 907 uint32_t dma_len; 908 uint32_t data; 909 910 dma_len = aspeed_smc_dma_len(s); 911 912 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? 913 "write" : "read", 914 s->regs[R_DMA_FLASH_ADDR], 915 s->regs[R_DMA_DRAM_ADDR], 916 dma_len); 917 while (dma_len) { 918 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { 919 data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], 920 MEMTXATTRS_UNSPECIFIED, &result); 921 if (result != MEMTX_OK) { 922 aspeed_smc_error("DRAM read failed @%08x", 923 s->regs[R_DMA_DRAM_ADDR]); 924 return; 925 } 926 927 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 928 data, MEMTXATTRS_UNSPECIFIED, &result); 929 if (result != MEMTX_OK) { 930 aspeed_smc_error("Flash write failed @%08x", 931 s->regs[R_DMA_FLASH_ADDR]); 932 return; 933 } 934 } else { 935 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 936 MEMTXATTRS_UNSPECIFIED, &result); 937 if (result != MEMTX_OK) { 938 aspeed_smc_error("Flash read failed @%08x", 939 s->regs[R_DMA_FLASH_ADDR]); 940 return; 941 } 942 943 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], 944 data, MEMTXATTRS_UNSPECIFIED, &result); 945 if (result != MEMTX_OK) { 946 aspeed_smc_error("DRAM write failed @%08x", 947 s->regs[R_DMA_DRAM_ADDR]); 948 return; 949 } 950 } 951 952 /* 953 * When the DMA is on-going, the DMA registers are updated 954 * with the current working addresses and length. 955 */ 956 s->regs[R_DMA_FLASH_ADDR] += 4; 957 s->regs[R_DMA_DRAM_ADDR] += 4; 958 dma_len -= 4; 959 s->regs[R_DMA_LEN] = dma_len; 960 s->regs[R_DMA_CHECKSUM] += data; 961 } 962 } 963 964 static void aspeed_smc_dma_stop(AspeedSMCState *s) 965 { 966 /* 967 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the 968 * engine is idle 969 */ 970 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; 971 s->regs[R_DMA_CHECKSUM] = 0; 972 973 /* 974 * Lower the DMA irq in any case. The IRQ control register could 975 * have been cleared before disabling the DMA. 976 */ 977 qemu_irq_lower(s->irq); 978 } 979 980 /* 981 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA 982 * can start even if the result of the previous was not collected. 983 */ 984 static bool aspeed_smc_dma_in_progress(AspeedSMCState *s) 985 { 986 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && 987 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); 988 } 989 990 static void aspeed_smc_dma_done(AspeedSMCState *s) 991 { 992 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; 993 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { 994 qemu_irq_raise(s->irq); 995 } 996 } 997 998 static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) 999 { 1000 if (!(dma_ctrl & DMA_CTRL_ENABLE)) { 1001 s->regs[R_DMA_CTRL] = dma_ctrl; 1002 1003 aspeed_smc_dma_stop(s); 1004 return; 1005 } 1006 1007 if (aspeed_smc_dma_in_progress(s)) { 1008 aspeed_smc_error("DMA in progress !"); 1009 return; 1010 } 1011 1012 s->regs[R_DMA_CTRL] = dma_ctrl; 1013 1014 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { 1015 aspeed_smc_dma_checksum(s); 1016 } else { 1017 aspeed_smc_dma_rw(s); 1018 } 1019 1020 aspeed_smc_dma_done(s); 1021 } 1022 1023 static inline bool aspeed_smc_dma_granted(AspeedSMCState *s) 1024 { 1025 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1026 1027 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { 1028 return true; 1029 } 1030 1031 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { 1032 aspeed_smc_error("DMA not granted"); 1033 return false; 1034 } 1035 1036 return true; 1037 } 1038 1039 static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) 1040 { 1041 /* Preserve DMA bits */ 1042 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1043 1044 if (dma_ctrl == 0xAEED0000) { 1045 /* automatically grant request */ 1046 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1047 return; 1048 } 1049 1050 /* clear request */ 1051 if (dma_ctrl == 0xDEEA0000) { 1052 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1053 return; 1054 } 1055 1056 if (!aspeed_smc_dma_granted(s)) { 1057 aspeed_smc_error("DMA not granted"); 1058 return; 1059 } 1060 1061 aspeed_smc_dma_ctrl(s, dma_ctrl); 1062 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1063 } 1064 1065 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, 1066 unsigned int size) 1067 { 1068 AspeedSMCState *s = ASPEED_SMC(opaque); 1069 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1070 uint32_t value = data; 1071 1072 trace_aspeed_smc_write(addr, size, data); 1073 1074 addr >>= 2; 1075 1076 if (addr == s->r_conf || 1077 (addr >= s->r_timings && 1078 addr < s->r_timings + asc->nregs_timings) || 1079 addr == s->r_ce_ctrl) { 1080 s->regs[addr] = value; 1081 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) { 1082 int cs = addr - s->r_ctrl0; 1083 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); 1084 } else if (addr >= R_SEG_ADDR0 && 1085 addr < R_SEG_ADDR0 + asc->cs_num_max) { 1086 int cs = addr - R_SEG_ADDR0; 1087 1088 if (value != s->regs[R_SEG_ADDR0 + cs]) { 1089 aspeed_smc_flash_set_segment(s, cs, value); 1090 } 1091 } else if (addr == R_CE_CMD_CTRL) { 1092 s->regs[addr] = value & 0xff; 1093 } else if (addr == R_DUMMY_DATA) { 1094 s->regs[addr] = value & 0xff; 1095 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) { 1096 s->regs[addr] = value & FMC_WDT2_CTRL_EN; 1097 } else if (addr == R_INTR_CTRL) { 1098 s->regs[addr] = value; 1099 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) { 1100 asc->dma_ctrl(s, value); 1101 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR && 1102 aspeed_smc_dma_granted(s)) { 1103 s->regs[addr] = DMA_DRAM_ADDR(asc, value); 1104 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR && 1105 aspeed_smc_dma_granted(s)) { 1106 s->regs[addr] = DMA_FLASH_ADDR(asc, value); 1107 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN && 1108 aspeed_smc_dma_granted(s)) { 1109 s->regs[addr] = DMA_LENGTH(value); 1110 } else { 1111 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", 1112 __func__, addr); 1113 return; 1114 } 1115 } 1116 1117 static const MemoryRegionOps aspeed_smc_ops = { 1118 .read = aspeed_smc_read, 1119 .write = aspeed_smc_write, 1120 .endianness = DEVICE_LITTLE_ENDIAN, 1121 }; 1122 1123 static void aspeed_smc_instance_init(Object *obj) 1124 { 1125 AspeedSMCState *s = ASPEED_SMC(obj); 1126 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1127 int i; 1128 1129 for (i = 0; i < asc->cs_num_max; i++) { 1130 object_initialize_child(obj, "flash[*]", &s->flashes[i], 1131 TYPE_ASPEED_SMC_FLASH); 1132 } 1133 } 1134 1135 /* 1136 * Initialize the custom address spaces for DMAs 1137 */ 1138 static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp) 1139 { 1140 if (!s->dram_mr) { 1141 error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set"); 1142 return; 1143 } 1144 1145 address_space_init(&s->flash_as, &s->mmio_flash, 1146 TYPE_ASPEED_SMC ".dma-flash"); 1147 address_space_init(&s->dram_as, s->dram_mr, 1148 TYPE_ASPEED_SMC ".dma-dram"); 1149 } 1150 1151 static void aspeed_smc_realize(DeviceState *dev, Error **errp) 1152 { 1153 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1154 AspeedSMCState *s = ASPEED_SMC(dev); 1155 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1156 int i; 1157 hwaddr offset = 0; 1158 1159 /* keep a copy under AspeedSMCState to speed up accesses */ 1160 s->r_conf = asc->r_conf; 1161 s->r_ce_ctrl = asc->r_ce_ctrl; 1162 s->r_ctrl0 = asc->r_ctrl0; 1163 s->r_timings = asc->r_timings; 1164 s->conf_enable_w0 = asc->conf_enable_w0; 1165 1166 /* DMA irq. Keep it first for the initialization in the SoC */ 1167 sysbus_init_irq(sbd, &s->irq); 1168 1169 s->spi = ssi_create_bus(dev, NULL); 1170 1171 /* Setup cs_lines for peripherals */ 1172 s->cs_lines = g_new0(qemu_irq, asc->cs_num_max); 1173 qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max); 1174 1175 /* The memory region for the controller registers */ 1176 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, 1177 TYPE_ASPEED_SMC, asc->nregs * 4); 1178 sysbus_init_mmio(sbd, &s->mmio); 1179 1180 /* 1181 * The container memory region representing the address space 1182 * window in which the flash modules are mapped. The size and 1183 * address depends on the SoC model and controller type. 1184 */ 1185 memory_region_init(&s->mmio_flash_container, OBJECT(s), 1186 TYPE_ASPEED_SMC ".container", 1187 asc->flash_window_size); 1188 sysbus_init_mmio(sbd, &s->mmio_flash_container); 1189 1190 memory_region_init_io(&s->mmio_flash, OBJECT(s), 1191 &aspeed_smc_flash_default_ops, s, 1192 TYPE_ASPEED_SMC ".flash", 1193 asc->flash_window_size); 1194 memory_region_add_subregion(&s->mmio_flash_container, 0x0, 1195 &s->mmio_flash); 1196 1197 /* 1198 * Let's create a sub memory region for each possible peripheral. All 1199 * have a configurable memory segment in the overall flash mapping 1200 * window of the controller but, there is not necessarily a flash 1201 * module behind to handle the memory accesses. This depends on 1202 * the board configuration. 1203 */ 1204 for (i = 0; i < asc->cs_num_max; ++i) { 1205 AspeedSMCFlash *fl = &s->flashes[i]; 1206 1207 if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s), 1208 errp)) { 1209 return; 1210 } 1211 if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) { 1212 return; 1213 } 1214 if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) { 1215 return; 1216 } 1217 1218 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); 1219 offset += asc->segments[i].size; 1220 } 1221 1222 /* DMA support */ 1223 if (aspeed_smc_has_dma(asc)) { 1224 aspeed_smc_dma_setup(s, errp); 1225 } 1226 } 1227 1228 static const VMStateDescription vmstate_aspeed_smc = { 1229 .name = "aspeed.smc", 1230 .version_id = 2, 1231 .minimum_version_id = 2, 1232 .fields = (const VMStateField[]) { 1233 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), 1234 VMSTATE_UINT8(snoop_index, AspeedSMCState), 1235 VMSTATE_UINT8(snoop_dummies, AspeedSMCState), 1236 VMSTATE_END_OF_LIST() 1237 } 1238 }; 1239 1240 static Property aspeed_smc_properties[] = { 1241 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), 1242 DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0), 1243 DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, 1244 TYPE_MEMORY_REGION, MemoryRegion *), 1245 DEFINE_PROP_END_OF_LIST(), 1246 }; 1247 1248 static void aspeed_smc_class_init(ObjectClass *klass, void *data) 1249 { 1250 DeviceClass *dc = DEVICE_CLASS(klass); 1251 1252 dc->realize = aspeed_smc_realize; 1253 dc->reset = aspeed_smc_reset; 1254 device_class_set_props(dc, aspeed_smc_properties); 1255 dc->vmsd = &vmstate_aspeed_smc; 1256 } 1257 1258 static const TypeInfo aspeed_smc_info = { 1259 .name = TYPE_ASPEED_SMC, 1260 .parent = TYPE_SYS_BUS_DEVICE, 1261 .instance_init = aspeed_smc_instance_init, 1262 .instance_size = sizeof(AspeedSMCState), 1263 .class_size = sizeof(AspeedSMCClass), 1264 .class_init = aspeed_smc_class_init, 1265 .abstract = true, 1266 }; 1267 1268 static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp) 1269 { 1270 AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev); 1271 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs); 1272 1273 if (!s->controller) { 1274 error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set"); 1275 return; 1276 } 1277 1278 s->asc = ASPEED_SMC_GET_CLASS(s->controller); 1279 1280 /* 1281 * Use the default segment value to size the memory region. This 1282 * can be changed by FW at runtime. 1283 */ 1284 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops, 1285 s, name, s->asc->segments[s->cs].size); 1286 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); 1287 } 1288 1289 static Property aspeed_smc_flash_properties[] = { 1290 DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0), 1291 DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC, 1292 AspeedSMCState *), 1293 DEFINE_PROP_END_OF_LIST(), 1294 }; 1295 1296 static void aspeed_smc_flash_class_init(ObjectClass *klass, void *data) 1297 { 1298 DeviceClass *dc = DEVICE_CLASS(klass); 1299 1300 dc->desc = "Aspeed SMC Flash device region"; 1301 dc->realize = aspeed_smc_flash_realize; 1302 device_class_set_props(dc, aspeed_smc_flash_properties); 1303 } 1304 1305 static const TypeInfo aspeed_smc_flash_info = { 1306 .name = TYPE_ASPEED_SMC_FLASH, 1307 .parent = TYPE_SYS_BUS_DEVICE, 1308 .instance_size = sizeof(AspeedSMCFlash), 1309 .class_init = aspeed_smc_flash_class_init, 1310 }; 1311 1312 /* 1313 * The Segment Registers of the AST2400 and AST2500 have a 8MB 1314 * unit. The address range of a flash SPI peripheral is encoded with 1315 * absolute addresses which should be part of the overall controller 1316 * window. 1317 */ 1318 static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, 1319 const AspeedSegments *seg) 1320 { 1321 uint32_t reg = 0; 1322 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; 1323 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT; 1324 return reg; 1325 } 1326 1327 static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, 1328 uint32_t reg, AspeedSegments *seg) 1329 { 1330 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; 1331 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; 1332 } 1333 1334 static const AspeedSegments aspeed_2400_smc_segments[] = { 1335 { 0x10000000, 32 * MiB }, 1336 }; 1337 1338 static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data) 1339 { 1340 DeviceClass *dc = DEVICE_CLASS(klass); 1341 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1342 1343 dc->desc = "Aspeed 2400 SMC Controller"; 1344 asc->r_conf = R_CONF; 1345 asc->r_ce_ctrl = R_CE_CTRL; 1346 asc->r_ctrl0 = R_CTRL0; 1347 asc->r_timings = R_TIMINGS; 1348 asc->nregs_timings = 1; 1349 asc->conf_enable_w0 = CONF_ENABLE_W0; 1350 asc->cs_num_max = 1; 1351 asc->segments = aspeed_2400_smc_segments; 1352 asc->flash_window_base = 0x10000000; 1353 asc->flash_window_size = 0x6000000; 1354 asc->features = 0x0; 1355 asc->nregs = ASPEED_SMC_R_SMC_MAX; 1356 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1357 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1358 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1359 } 1360 1361 static const TypeInfo aspeed_2400_smc_info = { 1362 .name = "aspeed.smc-ast2400", 1363 .parent = TYPE_ASPEED_SMC, 1364 .class_init = aspeed_2400_smc_class_init, 1365 }; 1366 1367 static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = { 1368 /* 1369 * CE0 and CE1 types are HW strapped in SCU70. Do it here to 1370 * simplify the model. 1371 */ 1372 [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0, 1373 }; 1374 1375 static const AspeedSegments aspeed_2400_fmc_segments[] = { 1376 { 0x20000000, 64 * MiB }, /* start address is readonly */ 1377 { 0x24000000, 32 * MiB }, 1378 { 0x26000000, 32 * MiB }, 1379 { 0x28000000, 32 * MiB }, 1380 { 0x2A000000, 32 * MiB } 1381 }; 1382 1383 static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data) 1384 { 1385 DeviceClass *dc = DEVICE_CLASS(klass); 1386 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1387 1388 dc->desc = "Aspeed 2400 FMC Controller"; 1389 asc->r_conf = R_CONF; 1390 asc->r_ce_ctrl = R_CE_CTRL; 1391 asc->r_ctrl0 = R_CTRL0; 1392 asc->r_timings = R_TIMINGS; 1393 asc->nregs_timings = 1; 1394 asc->conf_enable_w0 = CONF_ENABLE_W0; 1395 asc->cs_num_max = 5; 1396 asc->segments = aspeed_2400_fmc_segments; 1397 asc->segment_addr_mask = 0xffff0000; 1398 asc->resets = aspeed_2400_fmc_resets; 1399 asc->flash_window_base = 0x20000000; 1400 asc->flash_window_size = 0x10000000; 1401 asc->features = ASPEED_SMC_FEATURE_DMA; 1402 asc->dma_flash_mask = 0x0FFFFFFC; 1403 asc->dma_dram_mask = 0x1FFFFFFC; 1404 asc->dma_start_length = 4; 1405 asc->nregs = ASPEED_SMC_R_MAX; 1406 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1407 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1408 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1409 } 1410 1411 static const TypeInfo aspeed_2400_fmc_info = { 1412 .name = "aspeed.fmc-ast2400", 1413 .parent = TYPE_ASPEED_SMC, 1414 .class_init = aspeed_2400_fmc_class_init, 1415 }; 1416 1417 static const AspeedSegments aspeed_2400_spi1_segments[] = { 1418 { 0x30000000, 64 * MiB }, 1419 }; 1420 1421 static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s) 1422 { 1423 return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3; 1424 } 1425 1426 static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data) 1427 { 1428 DeviceClass *dc = DEVICE_CLASS(klass); 1429 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1430 1431 dc->desc = "Aspeed 2400 SPI1 Controller"; 1432 asc->r_conf = R_SPI_CONF; 1433 asc->r_ce_ctrl = 0xff; 1434 asc->r_ctrl0 = R_SPI_CTRL0; 1435 asc->r_timings = R_SPI_TIMINGS; 1436 asc->nregs_timings = 1; 1437 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0; 1438 asc->cs_num_max = 1; 1439 asc->segments = aspeed_2400_spi1_segments; 1440 asc->flash_window_base = 0x30000000; 1441 asc->flash_window_size = 0x10000000; 1442 asc->features = 0x0; 1443 asc->nregs = ASPEED_SMC_R_SPI_MAX; 1444 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1445 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1446 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1447 asc->addr_width = aspeed_2400_spi1_addr_width; 1448 } 1449 1450 static const TypeInfo aspeed_2400_spi1_info = { 1451 .name = "aspeed.spi1-ast2400", 1452 .parent = TYPE_ASPEED_SMC, 1453 .class_init = aspeed_2400_spi1_class_init, 1454 }; 1455 1456 static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = { 1457 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | 1458 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), 1459 }; 1460 1461 static const AspeedSegments aspeed_2500_fmc_segments[] = { 1462 { 0x20000000, 128 * MiB }, /* start address is readonly */ 1463 { 0x28000000, 32 * MiB }, 1464 { 0x2A000000, 32 * MiB }, 1465 }; 1466 1467 static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data) 1468 { 1469 DeviceClass *dc = DEVICE_CLASS(klass); 1470 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1471 1472 dc->desc = "Aspeed 2500 FMC Controller"; 1473 asc->r_conf = R_CONF; 1474 asc->r_ce_ctrl = R_CE_CTRL; 1475 asc->r_ctrl0 = R_CTRL0; 1476 asc->r_timings = R_TIMINGS; 1477 asc->nregs_timings = 1; 1478 asc->conf_enable_w0 = CONF_ENABLE_W0; 1479 asc->cs_num_max = 3; 1480 asc->segments = aspeed_2500_fmc_segments; 1481 asc->segment_addr_mask = 0xffff0000; 1482 asc->resets = aspeed_2500_fmc_resets; 1483 asc->flash_window_base = 0x20000000; 1484 asc->flash_window_size = 0x10000000; 1485 asc->features = ASPEED_SMC_FEATURE_DMA; 1486 asc->dma_flash_mask = 0x0FFFFFFC; 1487 asc->dma_dram_mask = 0x3FFFFFFC; 1488 asc->dma_start_length = 4; 1489 asc->nregs = ASPEED_SMC_R_MAX; 1490 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1491 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1492 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1493 } 1494 1495 static const TypeInfo aspeed_2500_fmc_info = { 1496 .name = "aspeed.fmc-ast2500", 1497 .parent = TYPE_ASPEED_SMC, 1498 .class_init = aspeed_2500_fmc_class_init, 1499 }; 1500 1501 static const AspeedSegments aspeed_2500_spi1_segments[] = { 1502 { 0x30000000, 32 * MiB }, /* start address is readonly */ 1503 { 0x32000000, 96 * MiB }, /* end address is readonly */ 1504 }; 1505 1506 static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data) 1507 { 1508 DeviceClass *dc = DEVICE_CLASS(klass); 1509 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1510 1511 dc->desc = "Aspeed 2500 SPI1 Controller"; 1512 asc->r_conf = R_CONF; 1513 asc->r_ce_ctrl = R_CE_CTRL; 1514 asc->r_ctrl0 = R_CTRL0; 1515 asc->r_timings = R_TIMINGS; 1516 asc->nregs_timings = 1; 1517 asc->conf_enable_w0 = CONF_ENABLE_W0; 1518 asc->cs_num_max = 2; 1519 asc->segments = aspeed_2500_spi1_segments; 1520 asc->segment_addr_mask = 0xffff0000; 1521 asc->flash_window_base = 0x30000000; 1522 asc->flash_window_size = 0x8000000; 1523 asc->features = 0x0; 1524 asc->nregs = ASPEED_SMC_R_MAX; 1525 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1526 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1527 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1528 } 1529 1530 static const TypeInfo aspeed_2500_spi1_info = { 1531 .name = "aspeed.spi1-ast2500", 1532 .parent = TYPE_ASPEED_SMC, 1533 .class_init = aspeed_2500_spi1_class_init, 1534 }; 1535 1536 static const AspeedSegments aspeed_2500_spi2_segments[] = { 1537 { 0x38000000, 32 * MiB }, /* start address is readonly */ 1538 { 0x3A000000, 96 * MiB }, /* end address is readonly */ 1539 }; 1540 1541 static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data) 1542 { 1543 DeviceClass *dc = DEVICE_CLASS(klass); 1544 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1545 1546 dc->desc = "Aspeed 2500 SPI2 Controller"; 1547 asc->r_conf = R_CONF; 1548 asc->r_ce_ctrl = R_CE_CTRL; 1549 asc->r_ctrl0 = R_CTRL0; 1550 asc->r_timings = R_TIMINGS; 1551 asc->nregs_timings = 1; 1552 asc->conf_enable_w0 = CONF_ENABLE_W0; 1553 asc->cs_num_max = 2; 1554 asc->segments = aspeed_2500_spi2_segments; 1555 asc->segment_addr_mask = 0xffff0000; 1556 asc->flash_window_base = 0x38000000; 1557 asc->flash_window_size = 0x8000000; 1558 asc->features = 0x0; 1559 asc->nregs = ASPEED_SMC_R_MAX; 1560 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1561 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1562 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1563 } 1564 1565 static const TypeInfo aspeed_2500_spi2_info = { 1566 .name = "aspeed.spi2-ast2500", 1567 .parent = TYPE_ASPEED_SMC, 1568 .class_init = aspeed_2500_spi2_class_init, 1569 }; 1570 1571 /* 1572 * The Segment Registers of the AST2600 have a 1MB unit. The address 1573 * range of a flash SPI peripheral is encoded with offsets in the overall 1574 * controller window. The previous SoC AST2400 and AST2500 used 1575 * absolute addresses. Only bits [27:20] are relevant and the end 1576 * address is an upper bound limit. 1577 */ 1578 #define AST2600_SEG_ADDR_MASK 0x0ff00000 1579 1580 static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, 1581 const AspeedSegments *seg) 1582 { 1583 uint32_t reg = 0; 1584 1585 /* Disabled segments have a nil register */ 1586 if (!seg->size) { 1587 return 0; 1588 } 1589 1590 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ 1591 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ 1592 return reg; 1593 } 1594 1595 static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, 1596 uint32_t reg, AspeedSegments *seg) 1597 { 1598 uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; 1599 uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; 1600 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1601 1602 if (reg) { 1603 seg->addr = asc->flash_window_base + start_offset; 1604 seg->size = end_offset + MiB - start_offset; 1605 } else { 1606 seg->addr = asc->flash_window_base; 1607 seg->size = 0; 1608 } 1609 } 1610 1611 static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = { 1612 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | 1613 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 | 1614 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2), 1615 }; 1616 1617 static const AspeedSegments aspeed_2600_fmc_segments[] = { 1618 { 0x0, 128 * MiB }, /* start address is readonly */ 1619 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ 1620 { 0x0, 0 }, /* disabled */ 1621 }; 1622 1623 static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data) 1624 { 1625 DeviceClass *dc = DEVICE_CLASS(klass); 1626 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1627 1628 dc->desc = "Aspeed 2600 FMC Controller"; 1629 asc->r_conf = R_CONF; 1630 asc->r_ce_ctrl = R_CE_CTRL; 1631 asc->r_ctrl0 = R_CTRL0; 1632 asc->r_timings = R_TIMINGS; 1633 asc->nregs_timings = 1; 1634 asc->conf_enable_w0 = CONF_ENABLE_W0; 1635 asc->cs_num_max = 3; 1636 asc->segments = aspeed_2600_fmc_segments; 1637 asc->segment_addr_mask = 0x0ff00ff0; 1638 asc->resets = aspeed_2600_fmc_resets; 1639 asc->flash_window_base = 0x20000000; 1640 asc->flash_window_size = 0x10000000; 1641 asc->features = ASPEED_SMC_FEATURE_DMA | 1642 ASPEED_SMC_FEATURE_WDT_CONTROL; 1643 asc->dma_flash_mask = 0x0FFFFFFC; 1644 asc->dma_dram_mask = 0x3FFFFFFC; 1645 asc->dma_start_length = 1; 1646 asc->nregs = ASPEED_SMC_R_MAX; 1647 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1648 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1649 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1650 } 1651 1652 static const TypeInfo aspeed_2600_fmc_info = { 1653 .name = "aspeed.fmc-ast2600", 1654 .parent = TYPE_ASPEED_SMC, 1655 .class_init = aspeed_2600_fmc_class_init, 1656 }; 1657 1658 static const AspeedSegments aspeed_2600_spi1_segments[] = { 1659 { 0x0, 128 * MiB }, /* start address is readonly */ 1660 { 0x0, 0 }, /* disabled */ 1661 }; 1662 1663 static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data) 1664 { 1665 DeviceClass *dc = DEVICE_CLASS(klass); 1666 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1667 1668 dc->desc = "Aspeed 2600 SPI1 Controller"; 1669 asc->r_conf = R_CONF; 1670 asc->r_ce_ctrl = R_CE_CTRL; 1671 asc->r_ctrl0 = R_CTRL0; 1672 asc->r_timings = R_TIMINGS; 1673 asc->nregs_timings = 2; 1674 asc->conf_enable_w0 = CONF_ENABLE_W0; 1675 asc->cs_num_max = 2; 1676 asc->segments = aspeed_2600_spi1_segments; 1677 asc->segment_addr_mask = 0x0ff00ff0; 1678 asc->flash_window_base = 0x30000000; 1679 asc->flash_window_size = 0x10000000; 1680 asc->features = ASPEED_SMC_FEATURE_DMA | 1681 ASPEED_SMC_FEATURE_DMA_GRANT; 1682 asc->dma_flash_mask = 0x0FFFFFFC; 1683 asc->dma_dram_mask = 0x3FFFFFFC; 1684 asc->dma_start_length = 1; 1685 asc->nregs = ASPEED_SMC_R_MAX; 1686 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1687 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1688 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1689 } 1690 1691 static const TypeInfo aspeed_2600_spi1_info = { 1692 .name = "aspeed.spi1-ast2600", 1693 .parent = TYPE_ASPEED_SMC, 1694 .class_init = aspeed_2600_spi1_class_init, 1695 }; 1696 1697 static const AspeedSegments aspeed_2600_spi2_segments[] = { 1698 { 0x0, 128 * MiB }, /* start address is readonly */ 1699 { 0x0, 0 }, /* disabled */ 1700 { 0x0, 0 }, /* disabled */ 1701 }; 1702 1703 static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data) 1704 { 1705 DeviceClass *dc = DEVICE_CLASS(klass); 1706 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1707 1708 dc->desc = "Aspeed 2600 SPI2 Controller"; 1709 asc->r_conf = R_CONF; 1710 asc->r_ce_ctrl = R_CE_CTRL; 1711 asc->r_ctrl0 = R_CTRL0; 1712 asc->r_timings = R_TIMINGS; 1713 asc->nregs_timings = 3; 1714 asc->conf_enable_w0 = CONF_ENABLE_W0; 1715 asc->cs_num_max = 3; 1716 asc->segments = aspeed_2600_spi2_segments; 1717 asc->segment_addr_mask = 0x0ff00ff0; 1718 asc->flash_window_base = 0x50000000; 1719 asc->flash_window_size = 0x10000000; 1720 asc->features = ASPEED_SMC_FEATURE_DMA | 1721 ASPEED_SMC_FEATURE_DMA_GRANT; 1722 asc->dma_flash_mask = 0x0FFFFFFC; 1723 asc->dma_dram_mask = 0x3FFFFFFC; 1724 asc->dma_start_length = 1; 1725 asc->nregs = ASPEED_SMC_R_MAX; 1726 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1727 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1728 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1729 } 1730 1731 static const TypeInfo aspeed_2600_spi2_info = { 1732 .name = "aspeed.spi2-ast2600", 1733 .parent = TYPE_ASPEED_SMC, 1734 .class_init = aspeed_2600_spi2_class_init, 1735 }; 1736 1737 /* 1738 * The FMC Segment Registers of the AST1030 have a 512KB unit. 1739 * Only bits [27:19] are used for decoding. 1740 */ 1741 #define AST1030_SEG_ADDR_MASK 0x0ff80000 1742 1743 static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s, 1744 const AspeedSegments *seg) 1745 { 1746 uint32_t reg = 0; 1747 1748 /* Disabled segments have a nil register */ 1749 if (!seg->size) { 1750 return 0; 1751 } 1752 1753 reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */ 1754 reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */ 1755 return reg; 1756 } 1757 1758 static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s, 1759 uint32_t reg, AspeedSegments *seg) 1760 { 1761 uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK; 1762 uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK; 1763 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1764 1765 if (reg) { 1766 seg->addr = asc->flash_window_base + start_offset; 1767 seg->size = end_offset + (512 * KiB) - start_offset; 1768 } else { 1769 seg->addr = asc->flash_window_base; 1770 seg->size = 0; 1771 } 1772 } 1773 1774 static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = { 1775 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | 1776 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), 1777 }; 1778 1779 static const AspeedSegments aspeed_1030_fmc_segments[] = { 1780 { 0x0, 128 * MiB }, /* start address is readonly */ 1781 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ 1782 { 0x0, 0 }, /* disabled */ 1783 }; 1784 1785 static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data) 1786 { 1787 DeviceClass *dc = DEVICE_CLASS(klass); 1788 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1789 1790 dc->desc = "Aspeed 1030 FMC Controller"; 1791 asc->r_conf = R_CONF; 1792 asc->r_ce_ctrl = R_CE_CTRL; 1793 asc->r_ctrl0 = R_CTRL0; 1794 asc->r_timings = R_TIMINGS; 1795 asc->nregs_timings = 2; 1796 asc->conf_enable_w0 = CONF_ENABLE_W0; 1797 asc->cs_num_max = 2; 1798 asc->segments = aspeed_1030_fmc_segments; 1799 asc->segment_addr_mask = 0x0ff80ff8; 1800 asc->resets = aspeed_1030_fmc_resets; 1801 asc->flash_window_base = 0x80000000; 1802 asc->flash_window_size = 0x10000000; 1803 asc->features = ASPEED_SMC_FEATURE_DMA; 1804 asc->dma_flash_mask = 0x0FFFFFFC; 1805 asc->dma_dram_mask = 0x000BFFFC; 1806 asc->dma_start_length = 1; 1807 asc->nregs = ASPEED_SMC_R_MAX; 1808 asc->segment_to_reg = aspeed_1030_smc_segment_to_reg; 1809 asc->reg_to_segment = aspeed_1030_smc_reg_to_segment; 1810 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1811 } 1812 1813 static const TypeInfo aspeed_1030_fmc_info = { 1814 .name = "aspeed.fmc-ast1030", 1815 .parent = TYPE_ASPEED_SMC, 1816 .class_init = aspeed_1030_fmc_class_init, 1817 }; 1818 1819 static const AspeedSegments aspeed_1030_spi1_segments[] = { 1820 { 0x0, 128 * MiB }, /* start address is readonly */ 1821 { 0x0, 0 }, /* disabled */ 1822 }; 1823 1824 static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data) 1825 { 1826 DeviceClass *dc = DEVICE_CLASS(klass); 1827 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1828 1829 dc->desc = "Aspeed 1030 SPI1 Controller"; 1830 asc->r_conf = R_CONF; 1831 asc->r_ce_ctrl = R_CE_CTRL; 1832 asc->r_ctrl0 = R_CTRL0; 1833 asc->r_timings = R_TIMINGS; 1834 asc->nregs_timings = 2; 1835 asc->conf_enable_w0 = CONF_ENABLE_W0; 1836 asc->cs_num_max = 2; 1837 asc->segments = aspeed_1030_spi1_segments; 1838 asc->segment_addr_mask = 0x0ff00ff0; 1839 asc->flash_window_base = 0x90000000; 1840 asc->flash_window_size = 0x10000000; 1841 asc->features = ASPEED_SMC_FEATURE_DMA; 1842 asc->dma_flash_mask = 0x0FFFFFFC; 1843 asc->dma_dram_mask = 0x000BFFFC; 1844 asc->dma_start_length = 1; 1845 asc->nregs = ASPEED_SMC_R_MAX; 1846 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1847 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1848 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1849 } 1850 1851 static const TypeInfo aspeed_1030_spi1_info = { 1852 .name = "aspeed.spi1-ast1030", 1853 .parent = TYPE_ASPEED_SMC, 1854 .class_init = aspeed_1030_spi1_class_init, 1855 }; 1856 static const AspeedSegments aspeed_1030_spi2_segments[] = { 1857 { 0x0, 128 * MiB }, /* start address is readonly */ 1858 { 0x0, 0 }, /* disabled */ 1859 }; 1860 1861 static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data) 1862 { 1863 DeviceClass *dc = DEVICE_CLASS(klass); 1864 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1865 1866 dc->desc = "Aspeed 1030 SPI2 Controller"; 1867 asc->r_conf = R_CONF; 1868 asc->r_ce_ctrl = R_CE_CTRL; 1869 asc->r_ctrl0 = R_CTRL0; 1870 asc->r_timings = R_TIMINGS; 1871 asc->nregs_timings = 2; 1872 asc->conf_enable_w0 = CONF_ENABLE_W0; 1873 asc->cs_num_max = 2; 1874 asc->segments = aspeed_1030_spi2_segments; 1875 asc->segment_addr_mask = 0x0ff00ff0; 1876 asc->flash_window_base = 0xb0000000; 1877 asc->flash_window_size = 0x10000000; 1878 asc->features = ASPEED_SMC_FEATURE_DMA; 1879 asc->dma_flash_mask = 0x0FFFFFFC; 1880 asc->dma_dram_mask = 0x000BFFFC; 1881 asc->dma_start_length = 1; 1882 asc->nregs = ASPEED_SMC_R_MAX; 1883 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1884 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1885 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1886 } 1887 1888 static const TypeInfo aspeed_1030_spi2_info = { 1889 .name = "aspeed.spi2-ast1030", 1890 .parent = TYPE_ASPEED_SMC, 1891 .class_init = aspeed_1030_spi2_class_init, 1892 }; 1893 1894 static void aspeed_smc_register_types(void) 1895 { 1896 type_register_static(&aspeed_smc_flash_info); 1897 type_register_static(&aspeed_smc_info); 1898 type_register_static(&aspeed_2400_smc_info); 1899 type_register_static(&aspeed_2400_fmc_info); 1900 type_register_static(&aspeed_2400_spi1_info); 1901 type_register_static(&aspeed_2500_fmc_info); 1902 type_register_static(&aspeed_2500_spi1_info); 1903 type_register_static(&aspeed_2500_spi2_info); 1904 type_register_static(&aspeed_2600_fmc_info); 1905 type_register_static(&aspeed_2600_spi1_info); 1906 type_register_static(&aspeed_2600_spi2_info); 1907 type_register_static(&aspeed_1030_fmc_info); 1908 type_register_static(&aspeed_1030_spi1_info); 1909 type_register_static(&aspeed_1030_spi2_info); 1910 } 1911 1912 type_init(aspeed_smc_register_types) 1913