1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "migration/vmstate.h" 28 #include "qemu/log.h" 29 #include "qemu/module.h" 30 #include "qemu/error-report.h" 31 #include "qapi/error.h" 32 #include "qemu/units.h" 33 #include "trace.h" 34 35 #include "hw/irq.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/ssi/aspeed_smc.h" 38 39 /* CE Type Setting Register */ 40 #define R_CONF (0x00 / 4) 41 #define CONF_LEGACY_DISABLE (1 << 31) 42 #define CONF_ENABLE_W4 20 43 #define CONF_ENABLE_W3 19 44 #define CONF_ENABLE_W2 18 45 #define CONF_ENABLE_W1 17 46 #define CONF_ENABLE_W0 16 47 #define CONF_FLASH_TYPE4 8 48 #define CONF_FLASH_TYPE3 6 49 #define CONF_FLASH_TYPE2 4 50 #define CONF_FLASH_TYPE1 2 51 #define CONF_FLASH_TYPE0 0 52 #define CONF_FLASH_TYPE_NOR 0x0 53 #define CONF_FLASH_TYPE_NAND 0x1 54 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */ 55 56 /* CE Control Register */ 57 #define R_CE_CTRL (0x04 / 4) 58 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */ 59 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */ 60 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */ 61 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */ 62 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */ 63 64 /* Interrupt Control and Status Register */ 65 #define R_INTR_CTRL (0x08 / 4) 66 #define INTR_CTRL_DMA_STATUS (1 << 11) 67 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10) 68 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9) 69 #define INTR_CTRL_DMA_EN (1 << 3) 70 #define INTR_CTRL_CMD_ABORT_EN (1 << 2) 71 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) 72 73 /* Command Control Register */ 74 #define R_CE_CMD_CTRL (0x0C / 4) 75 #define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4 76 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0 77 78 #define aspeed_smc_addr_byte_enabled(s, i) \ 79 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i))))) 80 #define aspeed_smc_data_byte_enabled(s, i) \ 81 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i))))) 82 83 /* CEx Control Register */ 84 #define R_CTRL0 (0x10 / 4) 85 #define CTRL_IO_QPI (1 << 31) 86 #define CTRL_IO_QUAD_DATA (1 << 30) 87 #define CTRL_IO_DUAL_DATA (1 << 29) 88 #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ 89 #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */ 90 #define CTRL_CMD_SHIFT 16 91 #define CTRL_CMD_MASK 0xff 92 #define CTRL_DUMMY_HIGH_SHIFT 14 93 #define CTRL_AST2400_SPI_4BYTE (1 << 13) 94 #define CE_CTRL_CLOCK_FREQ_SHIFT 8 95 #define CE_CTRL_CLOCK_FREQ_MASK 0xf 96 #define CE_CTRL_CLOCK_FREQ(div) \ 97 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 98 #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 99 #define CTRL_CE_STOP_ACTIVE (1 << 2) 100 #define CTRL_CMD_MODE_MASK 0x3 101 #define CTRL_READMODE 0x0 102 #define CTRL_FREADMODE 0x1 103 #define CTRL_WRITEMODE 0x2 104 #define CTRL_USERMODE 0x3 105 #define R_CTRL1 (0x14 / 4) 106 #define R_CTRL2 (0x18 / 4) 107 #define R_CTRL3 (0x1C / 4) 108 #define R_CTRL4 (0x20 / 4) 109 110 /* CEx Segment Address Register */ 111 #define R_SEG_ADDR0 (0x30 / 4) 112 #define SEG_END_SHIFT 24 /* 8MB units */ 113 #define SEG_END_MASK 0xff 114 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */ 115 #define SEG_START_MASK 0xff 116 #define R_SEG_ADDR1 (0x34 / 4) 117 #define R_SEG_ADDR2 (0x38 / 4) 118 #define R_SEG_ADDR3 (0x3C / 4) 119 #define R_SEG_ADDR4 (0x40 / 4) 120 121 /* Misc Control Register #1 */ 122 #define R_MISC_CTRL1 (0x50 / 4) 123 124 /* SPI dummy cycle data */ 125 #define R_DUMMY_DATA (0x54 / 4) 126 127 /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */ 128 #define R_FMC_WDT2_CTRL (0x64 / 4) 129 #define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */ 130 #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5) 131 #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */ 132 #define FMC_WDT2_CTRL_EN BIT(0) 133 134 /* DMA Control/Status Register */ 135 #define R_DMA_CTRL (0x80 / 4) 136 #define DMA_CTRL_REQUEST (1 << 31) 137 #define DMA_CTRL_GRANT (1 << 30) 138 #define DMA_CTRL_DELAY_MASK 0xf 139 #define DMA_CTRL_DELAY_SHIFT 8 140 #define DMA_CTRL_FREQ_MASK 0xf 141 #define DMA_CTRL_FREQ_SHIFT 4 142 #define DMA_CTRL_CALIB (1 << 3) 143 #define DMA_CTRL_CKSUM (1 << 2) 144 #define DMA_CTRL_WRITE (1 << 1) 145 #define DMA_CTRL_ENABLE (1 << 0) 146 147 /* DMA Flash Side Address */ 148 #define R_DMA_FLASH_ADDR (0x84 / 4) 149 150 /* DMA DRAM Side Address */ 151 #define R_DMA_DRAM_ADDR (0x88 / 4) 152 153 /* DMA Length Register */ 154 #define R_DMA_LEN (0x8C / 4) 155 156 /* Checksum Calculation Result */ 157 #define R_DMA_CHECKSUM (0x90 / 4) 158 159 /* Read Timing Compensation Register */ 160 #define R_TIMINGS (0x94 / 4) 161 162 /* SPI controller registers and bits (AST2400) */ 163 #define R_SPI_CONF (0x00 / 4) 164 #define SPI_CONF_ENABLE_W0 0 165 #define R_SPI_CTRL0 (0x4 / 4) 166 #define R_SPI_MISC_CTRL (0x10 / 4) 167 #define R_SPI_TIMINGS (0x14 / 4) 168 169 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4) 170 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4) 171 172 /* 173 * DMA DRAM addresses should be 4 bytes aligned and the valid address 174 * range is 0x40000000 - 0x5FFFFFFF (AST2400) 175 * 0x80000000 - 0xBFFFFFFF (AST2500) 176 * 177 * DMA flash addresses should be 4 bytes aligned and the valid address 178 * range is 0x20000000 - 0x2FFFFFFF. 179 * 180 * DMA length is from 4 bytes to 32MB 181 * 0: 4 bytes 182 * 0x7FFFFF: 32M bytes 183 */ 184 #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask) 185 #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask) 186 #define DMA_LENGTH(val) ((val) & 0x01FFFFFC) 187 188 /* Flash opcodes. */ 189 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ 190 191 #define SNOOP_OFF 0xFF 192 #define SNOOP_START 0x0 193 194 /* 195 * Default segments mapping addresses and size for each peripheral per 196 * controller. These can be changed when board is initialized with the 197 * Segment Address Registers. 198 */ 199 static const AspeedSegments aspeed_2400_fmc_segments[]; 200 static const AspeedSegments aspeed_2400_spi1_segments[]; 201 static const AspeedSegments aspeed_2500_fmc_segments[]; 202 static const AspeedSegments aspeed_2500_spi1_segments[]; 203 static const AspeedSegments aspeed_2500_spi2_segments[]; 204 static const AspeedSegments aspeed_2600_fmc_segments[]; 205 206 #define ASPEED_SMC_FEATURE_DMA 0x1 207 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 208 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4 209 210 static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc) 211 { 212 return !!(asc->features & ASPEED_SMC_FEATURE_DMA); 213 } 214 215 static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc) 216 { 217 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL); 218 } 219 220 #define aspeed_smc_error(fmt, ...) \ 221 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__) 222 223 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, 224 const AspeedSegments *new, 225 int cs) 226 { 227 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 228 AspeedSegments seg; 229 int i; 230 231 for (i = 0; i < asc->max_peripherals; i++) { 232 if (i == cs) { 233 continue; 234 } 235 236 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); 237 238 if (new->addr + new->size > seg.addr && 239 new->addr < seg.addr + seg.size) { 240 aspeed_smc_error("new segment CS%d [ 0x%" 241 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " 242 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 243 cs, new->addr, new->addr + new->size, 244 i, seg.addr, seg.addr + seg.size); 245 return true; 246 } 247 } 248 return false; 249 } 250 251 static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs, 252 uint64_t regval) 253 { 254 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 255 AspeedSMCFlash *fl = &s->flashes[cs]; 256 AspeedSegments seg; 257 258 asc->reg_to_segment(s, regval, &seg); 259 260 memory_region_transaction_begin(); 261 memory_region_set_size(&fl->mmio, seg.size); 262 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base); 263 memory_region_set_enabled(&fl->mmio, !!seg.size); 264 memory_region_transaction_commit(); 265 266 s->regs[R_SEG_ADDR0 + cs] = regval; 267 } 268 269 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, 270 uint64_t new) 271 { 272 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 273 AspeedSegments seg; 274 275 asc->reg_to_segment(s, new, &seg); 276 277 trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size); 278 279 /* The start address of CS0 is read-only */ 280 if (cs == 0 && seg.addr != asc->flash_window_base) { 281 aspeed_smc_error("Tried to change CS0 start address to 0x%" 282 HWADDR_PRIx, seg.addr); 283 seg.addr = asc->flash_window_base; 284 new = asc->segment_to_reg(s, &seg); 285 } 286 287 /* 288 * The end address of the AST2500 spi controllers is also 289 * read-only. 290 */ 291 if ((asc->segments == aspeed_2500_spi1_segments || 292 asc->segments == aspeed_2500_spi2_segments) && 293 cs == asc->max_peripherals && 294 seg.addr + seg.size != asc->segments[cs].addr + 295 asc->segments[cs].size) { 296 aspeed_smc_error("Tried to change CS%d end address to 0x%" 297 HWADDR_PRIx, cs, seg.addr + seg.size); 298 seg.size = asc->segments[cs].addr + asc->segments[cs].size - 299 seg.addr; 300 new = asc->segment_to_reg(s, &seg); 301 } 302 303 /* Keep the segment in the overall flash window */ 304 if (seg.size && 305 (seg.addr + seg.size <= asc->flash_window_base || 306 seg.addr > asc->flash_window_base + asc->flash_window_size)) { 307 aspeed_smc_error("new segment for CS%d is invalid : " 308 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 309 cs, seg.addr, seg.addr + seg.size); 310 return; 311 } 312 313 /* Check start address vs. alignment */ 314 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) { 315 aspeed_smc_error("new segment for CS%d is not " 316 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 317 cs, seg.addr, seg.addr + seg.size); 318 } 319 320 /* And segments should not overlap (in the specs) */ 321 aspeed_smc_flash_overlap(s, &seg, cs); 322 323 /* All should be fine now to move the region */ 324 aspeed_smc_flash_set_segment_region(s, cs, new); 325 } 326 327 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, 328 unsigned size) 329 { 330 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u" PRIx64, addr, size); 331 return 0; 332 } 333 334 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, 335 uint64_t data, unsigned size) 336 { 337 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64, 338 addr, size, data); 339 } 340 341 static const MemoryRegionOps aspeed_smc_flash_default_ops = { 342 .read = aspeed_smc_flash_default_read, 343 .write = aspeed_smc_flash_default_write, 344 .endianness = DEVICE_LITTLE_ENDIAN, 345 .valid = { 346 .min_access_size = 1, 347 .max_access_size = 4, 348 }, 349 }; 350 351 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl) 352 { 353 const AspeedSMCState *s = fl->controller; 354 355 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; 356 } 357 358 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl) 359 { 360 const AspeedSMCState *s = fl->controller; 361 362 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs)); 363 } 364 365 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl) 366 { 367 const AspeedSMCState *s = fl->controller; 368 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; 369 370 /* 371 * In read mode, the default SPI command is READ (0x3). In other 372 * modes, the command should necessarily be defined 373 * 374 * TODO: add support for READ4 (0x13) on AST2600 375 */ 376 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) { 377 cmd = SPI_OP_READ; 378 } 379 380 if (!cmd) { 381 aspeed_smc_error("no command defined for mode %d", 382 aspeed_smc_flash_mode(fl)); 383 } 384 385 return cmd; 386 } 387 388 static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl) 389 { 390 const AspeedSMCState *s = fl->controller; 391 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 392 393 if (asc->segments == aspeed_2400_spi1_segments) { 394 return s->regs[s->r_ctrl0] & CTRL_AST2400_SPI_4BYTE; 395 } else { 396 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)); 397 } 398 } 399 400 static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect) 401 { 402 AspeedSMCState *s = fl->controller; 403 404 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : ""); 405 406 qemu_set_irq(s->cs_lines[fl->cs], unselect); 407 } 408 409 static void aspeed_smc_flash_select(AspeedSMCFlash *fl) 410 { 411 aspeed_smc_flash_do_select(fl, false); 412 } 413 414 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl) 415 { 416 aspeed_smc_flash_do_select(fl, true); 417 } 418 419 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, 420 uint32_t addr) 421 { 422 const AspeedSMCState *s = fl->controller; 423 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 424 AspeedSegments seg; 425 426 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg); 427 if ((addr % seg.size) != addr) { 428 aspeed_smc_error("invalid address 0x%08x for CS%d segment : " 429 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", 430 addr, fl->cs, seg.addr, seg.addr + seg.size); 431 addr %= seg.size; 432 } 433 434 return addr; 435 } 436 437 static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl) 438 { 439 const AspeedSMCState *s = fl->controller; 440 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs]; 441 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; 442 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; 443 uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8; 444 445 if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) { 446 dummies /= 2; 447 } 448 449 return dummies; 450 } 451 452 static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) 453 { 454 const AspeedSMCState *s = fl->controller; 455 uint8_t cmd = aspeed_smc_flash_cmd(fl); 456 int i = aspeed_smc_flash_is_4byte(fl) ? 4 : 3; 457 458 /* Flash access can not exceed CS segment */ 459 addr = aspeed_smc_check_segment_addr(fl, addr); 460 461 ssi_transfer(s->spi, cmd); 462 while (i--) { 463 if (aspeed_smc_addr_byte_enabled(s, i)) { 464 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); 465 } 466 } 467 468 /* 469 * Use fake transfers to model dummy bytes. The value should 470 * be configured to some non-zero value in fast read mode and 471 * zero in read mode. But, as the HW allows inconsistent 472 * settings, let's check for fast read mode. 473 */ 474 if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { 475 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { 476 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); 477 } 478 } 479 } 480 481 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) 482 { 483 AspeedSMCFlash *fl = opaque; 484 AspeedSMCState *s = fl->controller; 485 uint64_t ret = 0; 486 int i; 487 488 switch (aspeed_smc_flash_mode(fl)) { 489 case CTRL_USERMODE: 490 for (i = 0; i < size; i++) { 491 ret |= ssi_transfer(s->spi, 0x0) << (8 * i); 492 } 493 break; 494 case CTRL_READMODE: 495 case CTRL_FREADMODE: 496 aspeed_smc_flash_select(fl); 497 aspeed_smc_flash_setup(fl, addr); 498 499 for (i = 0; i < size; i++) { 500 ret |= ssi_transfer(s->spi, 0x0) << (8 * i); 501 } 502 503 aspeed_smc_flash_unselect(fl); 504 break; 505 default: 506 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); 507 } 508 509 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret, 510 aspeed_smc_flash_mode(fl)); 511 return ret; 512 } 513 514 /* 515 * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a 516 * common include header. 517 */ 518 typedef enum { 519 READ = 0x3, READ_4 = 0x13, 520 FAST_READ = 0xb, FAST_READ_4 = 0x0c, 521 DOR = 0x3b, DOR_4 = 0x3c, 522 QOR = 0x6b, QOR_4 = 0x6c, 523 DIOR = 0xbb, DIOR_4 = 0xbc, 524 QIOR = 0xeb, QIOR_4 = 0xec, 525 526 PP = 0x2, PP_4 = 0x12, 527 DPP = 0xa2, 528 QPP = 0x32, QPP_4 = 0x34, 529 } FlashCMD; 530 531 static int aspeed_smc_num_dummies(uint8_t command) 532 { 533 switch (command) { /* check for dummies */ 534 case READ: /* no dummy bytes/cycles */ 535 case PP: 536 case DPP: 537 case QPP: 538 case READ_4: 539 case PP_4: 540 case QPP_4: 541 return 0; 542 case FAST_READ: 543 case DOR: 544 case QOR: 545 case FAST_READ_4: 546 case DOR_4: 547 case QOR_4: 548 return 1; 549 case DIOR: 550 case DIOR_4: 551 return 2; 552 case QIOR: 553 case QIOR_4: 554 return 4; 555 default: 556 return -1; 557 } 558 } 559 560 static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data, 561 unsigned size) 562 { 563 AspeedSMCState *s = fl->controller; 564 uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3; 565 566 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies, 567 (uint8_t) data & 0xff); 568 569 if (s->snoop_index == SNOOP_OFF) { 570 return false; /* Do nothing */ 571 572 } else if (s->snoop_index == SNOOP_START) { 573 uint8_t cmd = data & 0xff; 574 int ndummies = aspeed_smc_num_dummies(cmd); 575 576 /* 577 * No dummy cycles are expected with the current command. Turn 578 * off snooping and let the transfer proceed normally. 579 */ 580 if (ndummies <= 0) { 581 s->snoop_index = SNOOP_OFF; 582 return false; 583 } 584 585 s->snoop_dummies = ndummies * 8; 586 587 } else if (s->snoop_index >= addr_width + 1) { 588 589 /* The SPI transfer has reached the dummy cycles sequence */ 590 for (; s->snoop_dummies; s->snoop_dummies--) { 591 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); 592 } 593 594 /* If no more dummy cycles are expected, turn off snooping */ 595 if (!s->snoop_dummies) { 596 s->snoop_index = SNOOP_OFF; 597 } else { 598 s->snoop_index += size; 599 } 600 601 /* 602 * Dummy cycles have been faked already. Ignore the current 603 * SPI transfer 604 */ 605 return true; 606 } 607 608 s->snoop_index += size; 609 return false; 610 } 611 612 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, 613 unsigned size) 614 { 615 AspeedSMCFlash *fl = opaque; 616 AspeedSMCState *s = fl->controller; 617 int i; 618 619 trace_aspeed_smc_flash_write(fl->cs, addr, size, data, 620 aspeed_smc_flash_mode(fl)); 621 622 if (!aspeed_smc_is_writable(fl)) { 623 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); 624 return; 625 } 626 627 switch (aspeed_smc_flash_mode(fl)) { 628 case CTRL_USERMODE: 629 if (aspeed_smc_do_snoop(fl, data, size)) { 630 break; 631 } 632 633 for (i = 0; i < size; i++) { 634 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); 635 } 636 break; 637 case CTRL_WRITEMODE: 638 aspeed_smc_flash_select(fl); 639 aspeed_smc_flash_setup(fl, addr); 640 641 for (i = 0; i < size; i++) { 642 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); 643 } 644 645 aspeed_smc_flash_unselect(fl); 646 break; 647 default: 648 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); 649 } 650 } 651 652 static const MemoryRegionOps aspeed_smc_flash_ops = { 653 .read = aspeed_smc_flash_read, 654 .write = aspeed_smc_flash_write, 655 .endianness = DEVICE_LITTLE_ENDIAN, 656 .valid = { 657 .min_access_size = 1, 658 .max_access_size = 4, 659 }, 660 }; 661 662 static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value) 663 { 664 AspeedSMCState *s = fl->controller; 665 bool unselect; 666 667 /* User mode selects the CS, other modes unselect */ 668 unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE; 669 670 /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ 671 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) && 672 value & CTRL_CE_STOP_ACTIVE) { 673 unselect = true; 674 } 675 676 s->regs[s->r_ctrl0 + fl->cs] = value; 677 678 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; 679 680 aspeed_smc_flash_do_select(fl, unselect); 681 } 682 683 static void aspeed_smc_reset(DeviceState *d) 684 { 685 AspeedSMCState *s = ASPEED_SMC(d); 686 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 687 int i; 688 689 memset(s->regs, 0, sizeof s->regs); 690 691 /* Unselect all peripherals */ 692 for (i = 0; i < s->num_cs; ++i) { 693 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; 694 qemu_set_irq(s->cs_lines[i], true); 695 } 696 697 /* setup the default segment register values and regions for all */ 698 for (i = 0; i < asc->max_peripherals; ++i) { 699 aspeed_smc_flash_set_segment_region(s, i, 700 asc->segment_to_reg(s, &asc->segments[i])); 701 } 702 703 /* HW strapping flash type for the AST2600 controllers */ 704 if (asc->segments == aspeed_2600_fmc_segments) { 705 /* flash type is fixed to SPI for all */ 706 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); 707 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1); 708 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2); 709 } 710 711 /* HW strapping flash type for FMC controllers */ 712 if (asc->segments == aspeed_2500_fmc_segments) { 713 /* flash type is fixed to SPI for CE0 and CE1 */ 714 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); 715 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1); 716 } 717 718 /* HW strapping for AST2400 FMC controllers (SCU70). Let's use the 719 * configuration of the palmetto-bmc machine */ 720 if (asc->segments == aspeed_2400_fmc_segments) { 721 s->regs[s->r_conf] |= (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); 722 } 723 724 s->snoop_index = SNOOP_OFF; 725 s->snoop_dummies = 0; 726 } 727 728 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) 729 { 730 AspeedSMCState *s = ASPEED_SMC(opaque); 731 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque); 732 733 addr >>= 2; 734 735 if (addr == s->r_conf || 736 (addr >= s->r_timings && 737 addr < s->r_timings + asc->nregs_timings) || 738 addr == s->r_ce_ctrl || 739 addr == R_CE_CMD_CTRL || 740 addr == R_INTR_CTRL || 741 addr == R_DUMMY_DATA || 742 (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) || 743 (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) || 744 (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) || 745 (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) || 746 (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) || 747 (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) || 748 (addr >= R_SEG_ADDR0 && 749 addr < R_SEG_ADDR0 + asc->max_peripherals) || 750 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->max_peripherals)) { 751 752 trace_aspeed_smc_read(addr, size, s->regs[addr]); 753 754 return s->regs[addr]; 755 } else { 756 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", 757 __func__, addr); 758 return -1; 759 } 760 } 761 762 static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) 763 { 764 /* HCLK/1 .. HCLK/16 */ 765 const uint8_t hclk_divisors[] = { 766 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 767 }; 768 int i; 769 770 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { 771 if (hclk_mask == hclk_divisors[i]) { 772 return i + 1; 773 } 774 } 775 776 aspeed_smc_error("invalid HCLK mask %x", hclk_mask); 777 return 0; 778 } 779 780 /* 781 * When doing calibration, the SPI clock rate in the CE0 Control 782 * Register and the read delay cycles in the Read Timing Compensation 783 * Register are set using bit[11:4] of the DMA Control Register. 784 */ 785 static void aspeed_smc_dma_calibration(AspeedSMCState *s) 786 { 787 uint8_t delay = 788 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; 789 uint8_t hclk_mask = 790 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; 791 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask); 792 uint32_t hclk_shift = (hclk_div - 1) << 2; 793 uint8_t cs; 794 795 /* 796 * The Read Timing Compensation Register values apply to all CS on 797 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays 798 */ 799 if (hclk_div && hclk_div < 6) { 800 s->regs[s->r_timings] &= ~(0xf << hclk_shift); 801 s->regs[s->r_timings] |= delay << hclk_shift; 802 } 803 804 /* 805 * TODO: compute the CS from the DMA address and the segment 806 * registers. This is not really a problem for now because the 807 * Timing Register values apply to all CS and software uses CS0 to 808 * do calibration. 809 */ 810 cs = 0; 811 s->regs[s->r_ctrl0 + cs] &= 812 ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); 813 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); 814 } 815 816 /* 817 * Emulate read errors in the DMA Checksum Register for high 818 * frequencies and optimistic settings of the Read Timing Compensation 819 * Register. This will help in tuning the SPI timing calibration 820 * algorithm. 821 */ 822 static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) 823 { 824 uint8_t delay = 825 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; 826 uint8_t hclk_mask = 827 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; 828 829 /* 830 * Typical values of a palmetto-bmc machine. 831 */ 832 switch (aspeed_smc_hclk_divisor(hclk_mask)) { 833 case 4 ... 16: 834 return false; 835 case 3: /* at least one HCLK cycle delay */ 836 return (delay & 0x7) < 1; 837 case 2: /* at least two HCLK cycle delay */ 838 return (delay & 0x7) < 2; 839 case 1: /* (> 100MHz) is above the max freq of the controller */ 840 return true; 841 default: 842 g_assert_not_reached(); 843 } 844 } 845 846 /* 847 * Accumulate the result of the reads to provide a checksum that will 848 * be used to validate the read timing settings. 849 */ 850 static void aspeed_smc_dma_checksum(AspeedSMCState *s) 851 { 852 MemTxResult result; 853 uint32_t data; 854 855 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { 856 aspeed_smc_error("invalid direction for DMA checksum"); 857 return; 858 } 859 860 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { 861 aspeed_smc_dma_calibration(s); 862 } 863 864 while (s->regs[R_DMA_LEN]) { 865 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 866 MEMTXATTRS_UNSPECIFIED, &result); 867 if (result != MEMTX_OK) { 868 aspeed_smc_error("Flash read failed @%08x", 869 s->regs[R_DMA_FLASH_ADDR]); 870 return; 871 } 872 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); 873 874 /* 875 * When the DMA is on-going, the DMA registers are updated 876 * with the current working addresses and length. 877 */ 878 s->regs[R_DMA_CHECKSUM] += data; 879 s->regs[R_DMA_FLASH_ADDR] += 4; 880 s->regs[R_DMA_LEN] -= 4; 881 } 882 883 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { 884 s->regs[R_DMA_CHECKSUM] = 0xbadc0de; 885 } 886 887 } 888 889 static void aspeed_smc_dma_rw(AspeedSMCState *s) 890 { 891 MemTxResult result; 892 uint32_t data; 893 894 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? 895 "write" : "read", 896 s->regs[R_DMA_FLASH_ADDR], 897 s->regs[R_DMA_DRAM_ADDR], 898 s->regs[R_DMA_LEN]); 899 while (s->regs[R_DMA_LEN]) { 900 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { 901 data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], 902 MEMTXATTRS_UNSPECIFIED, &result); 903 if (result != MEMTX_OK) { 904 aspeed_smc_error("DRAM read failed @%08x", 905 s->regs[R_DMA_DRAM_ADDR]); 906 return; 907 } 908 909 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 910 data, MEMTXATTRS_UNSPECIFIED, &result); 911 if (result != MEMTX_OK) { 912 aspeed_smc_error("Flash write failed @%08x", 913 s->regs[R_DMA_FLASH_ADDR]); 914 return; 915 } 916 } else { 917 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], 918 MEMTXATTRS_UNSPECIFIED, &result); 919 if (result != MEMTX_OK) { 920 aspeed_smc_error("Flash read failed @%08x", 921 s->regs[R_DMA_FLASH_ADDR]); 922 return; 923 } 924 925 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], 926 data, MEMTXATTRS_UNSPECIFIED, &result); 927 if (result != MEMTX_OK) { 928 aspeed_smc_error("DRAM write failed @%08x", 929 s->regs[R_DMA_DRAM_ADDR]); 930 return; 931 } 932 } 933 934 /* 935 * When the DMA is on-going, the DMA registers are updated 936 * with the current working addresses and length. 937 */ 938 s->regs[R_DMA_FLASH_ADDR] += 4; 939 s->regs[R_DMA_DRAM_ADDR] += 4; 940 s->regs[R_DMA_LEN] -= 4; 941 s->regs[R_DMA_CHECKSUM] += data; 942 } 943 } 944 945 static void aspeed_smc_dma_stop(AspeedSMCState *s) 946 { 947 /* 948 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the 949 * engine is idle 950 */ 951 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; 952 s->regs[R_DMA_CHECKSUM] = 0; 953 954 /* 955 * Lower the DMA irq in any case. The IRQ control register could 956 * have been cleared before disabling the DMA. 957 */ 958 qemu_irq_lower(s->irq); 959 } 960 961 /* 962 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA 963 * can start even if the result of the previous was not collected. 964 */ 965 static bool aspeed_smc_dma_in_progress(AspeedSMCState *s) 966 { 967 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && 968 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); 969 } 970 971 static void aspeed_smc_dma_done(AspeedSMCState *s) 972 { 973 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; 974 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { 975 qemu_irq_raise(s->irq); 976 } 977 } 978 979 static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) 980 { 981 if (!(dma_ctrl & DMA_CTRL_ENABLE)) { 982 s->regs[R_DMA_CTRL] = dma_ctrl; 983 984 aspeed_smc_dma_stop(s); 985 return; 986 } 987 988 if (aspeed_smc_dma_in_progress(s)) { 989 aspeed_smc_error("DMA in progress !"); 990 return; 991 } 992 993 s->regs[R_DMA_CTRL] = dma_ctrl; 994 995 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { 996 aspeed_smc_dma_checksum(s); 997 } else { 998 aspeed_smc_dma_rw(s); 999 } 1000 1001 aspeed_smc_dma_done(s); 1002 } 1003 1004 static inline bool aspeed_smc_dma_granted(AspeedSMCState *s) 1005 { 1006 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1007 1008 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { 1009 return true; 1010 } 1011 1012 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { 1013 aspeed_smc_error("DMA not granted"); 1014 return false; 1015 } 1016 1017 return true; 1018 } 1019 1020 static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) 1021 { 1022 /* Preserve DMA bits */ 1023 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1024 1025 if (dma_ctrl == 0xAEED0000) { 1026 /* automatically grant request */ 1027 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1028 return; 1029 } 1030 1031 /* clear request */ 1032 if (dma_ctrl == 0xDEEA0000) { 1033 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1034 return; 1035 } 1036 1037 if (!aspeed_smc_dma_granted(s)) { 1038 aspeed_smc_error("DMA not granted"); 1039 return; 1040 } 1041 1042 aspeed_smc_dma_ctrl(s, dma_ctrl); 1043 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); 1044 } 1045 1046 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, 1047 unsigned int size) 1048 { 1049 AspeedSMCState *s = ASPEED_SMC(opaque); 1050 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1051 uint32_t value = data; 1052 1053 addr >>= 2; 1054 1055 trace_aspeed_smc_write(addr, size, data); 1056 1057 if (addr == s->r_conf || 1058 (addr >= s->r_timings && 1059 addr < s->r_timings + asc->nregs_timings) || 1060 addr == s->r_ce_ctrl) { 1061 s->regs[addr] = value; 1062 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { 1063 int cs = addr - s->r_ctrl0; 1064 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); 1065 } else if (addr >= R_SEG_ADDR0 && 1066 addr < R_SEG_ADDR0 + asc->max_peripherals) { 1067 int cs = addr - R_SEG_ADDR0; 1068 1069 if (value != s->regs[R_SEG_ADDR0 + cs]) { 1070 aspeed_smc_flash_set_segment(s, cs, value); 1071 } 1072 } else if (addr == R_CE_CMD_CTRL) { 1073 s->regs[addr] = value & 0xff; 1074 } else if (addr == R_DUMMY_DATA) { 1075 s->regs[addr] = value & 0xff; 1076 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) { 1077 s->regs[addr] = value & FMC_WDT2_CTRL_EN; 1078 } else if (addr == R_INTR_CTRL) { 1079 s->regs[addr] = value; 1080 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) { 1081 asc->dma_ctrl(s, value); 1082 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR && 1083 aspeed_smc_dma_granted(s)) { 1084 s->regs[addr] = DMA_DRAM_ADDR(asc, value); 1085 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR && 1086 aspeed_smc_dma_granted(s)) { 1087 s->regs[addr] = DMA_FLASH_ADDR(asc, value); 1088 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN && 1089 aspeed_smc_dma_granted(s)) { 1090 s->regs[addr] = DMA_LENGTH(value); 1091 } else { 1092 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", 1093 __func__, addr); 1094 return; 1095 } 1096 } 1097 1098 static const MemoryRegionOps aspeed_smc_ops = { 1099 .read = aspeed_smc_read, 1100 .write = aspeed_smc_write, 1101 .endianness = DEVICE_LITTLE_ENDIAN, 1102 }; 1103 1104 /* 1105 * Initialize the custom address spaces for DMAs 1106 */ 1107 static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp) 1108 { 1109 if (!s->dram_mr) { 1110 error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set"); 1111 return; 1112 } 1113 1114 address_space_init(&s->flash_as, &s->mmio_flash, 1115 TYPE_ASPEED_SMC ".dma-flash"); 1116 address_space_init(&s->dram_as, s->dram_mr, 1117 TYPE_ASPEED_SMC ".dma-dram"); 1118 } 1119 1120 static void aspeed_smc_realize(DeviceState *dev, Error **errp) 1121 { 1122 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1123 AspeedSMCState *s = ASPEED_SMC(dev); 1124 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1125 int i; 1126 char name[32]; 1127 hwaddr offset = 0; 1128 1129 /* keep a copy under AspeedSMCState to speed up accesses */ 1130 s->r_conf = asc->r_conf; 1131 s->r_ce_ctrl = asc->r_ce_ctrl; 1132 s->r_ctrl0 = asc->r_ctrl0; 1133 s->r_timings = asc->r_timings; 1134 s->conf_enable_w0 = asc->conf_enable_w0; 1135 1136 /* Enforce some real HW limits */ 1137 if (s->num_cs > asc->max_peripherals) { 1138 aspeed_smc_error("num_cs cannot exceed: %d", asc->max_peripherals); 1139 s->num_cs = asc->max_peripherals; 1140 } 1141 1142 /* DMA irq. Keep it first for the initialization in the SoC */ 1143 sysbus_init_irq(sbd, &s->irq); 1144 1145 s->spi = ssi_create_bus(dev, "spi"); 1146 1147 /* Setup cs_lines for peripherals */ 1148 s->cs_lines = g_new0(qemu_irq, s->num_cs); 1149 1150 for (i = 0; i < s->num_cs; ++i) { 1151 sysbus_init_irq(sbd, &s->cs_lines[i]); 1152 } 1153 1154 /* The memory region for the controller registers */ 1155 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, 1156 TYPE_ASPEED_SMC, asc->nregs * 4); 1157 sysbus_init_mmio(sbd, &s->mmio); 1158 1159 /* 1160 * The container memory region representing the address space 1161 * window in which the flash modules are mapped. The size and 1162 * address depends on the SoC model and controller type. 1163 */ 1164 memory_region_init_io(&s->mmio_flash, OBJECT(s), 1165 &aspeed_smc_flash_default_ops, s, 1166 TYPE_ASPEED_SMC ".flash", 1167 asc->flash_window_size); 1168 memory_region_init_alias(&s->mmio_flash_alias, OBJECT(s), 1169 TYPE_ASPEED_SMC ".flash", 1170 &s->mmio_flash, 0, asc->flash_window_size); 1171 sysbus_init_mmio(sbd, &s->mmio_flash_alias); 1172 1173 s->flashes = g_new0(AspeedSMCFlash, asc->max_peripherals); 1174 1175 /* 1176 * Let's create a sub memory region for each possible peripheral. All 1177 * have a configurable memory segment in the overall flash mapping 1178 * window of the controller but, there is not necessarily a flash 1179 * module behind to handle the memory accesses. This depends on 1180 * the board configuration. 1181 */ 1182 for (i = 0; i < asc->max_peripherals; ++i) { 1183 AspeedSMCFlash *fl = &s->flashes[i]; 1184 1185 snprintf(name, sizeof(name), TYPE_ASPEED_SMC ".flash.%d", i); 1186 1187 fl->cs = i; 1188 fl->controller = s; 1189 memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_ops, 1190 fl, name, asc->segments[i].size); 1191 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); 1192 offset += asc->segments[i].size; 1193 } 1194 1195 /* DMA support */ 1196 if (aspeed_smc_has_dma(asc)) { 1197 aspeed_smc_dma_setup(s, errp); 1198 } 1199 } 1200 1201 static const VMStateDescription vmstate_aspeed_smc = { 1202 .name = "aspeed.smc", 1203 .version_id = 2, 1204 .minimum_version_id = 2, 1205 .fields = (VMStateField[]) { 1206 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), 1207 VMSTATE_UINT8(snoop_index, AspeedSMCState), 1208 VMSTATE_UINT8(snoop_dummies, AspeedSMCState), 1209 VMSTATE_END_OF_LIST() 1210 } 1211 }; 1212 1213 static Property aspeed_smc_properties[] = { 1214 DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), 1215 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), 1216 DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, 1217 TYPE_MEMORY_REGION, MemoryRegion *), 1218 DEFINE_PROP_END_OF_LIST(), 1219 }; 1220 1221 static void aspeed_smc_class_init(ObjectClass *klass, void *data) 1222 { 1223 DeviceClass *dc = DEVICE_CLASS(klass); 1224 1225 dc->realize = aspeed_smc_realize; 1226 dc->reset = aspeed_smc_reset; 1227 device_class_set_props(dc, aspeed_smc_properties); 1228 dc->vmsd = &vmstate_aspeed_smc; 1229 } 1230 1231 static const TypeInfo aspeed_smc_info = { 1232 .name = TYPE_ASPEED_SMC, 1233 .parent = TYPE_SYS_BUS_DEVICE, 1234 .instance_size = sizeof(AspeedSMCState), 1235 .class_size = sizeof(AspeedSMCClass), 1236 .class_init = aspeed_smc_class_init, 1237 .abstract = true, 1238 }; 1239 1240 1241 /* 1242 * The Segment Registers of the AST2400 and AST2500 have a 8MB 1243 * unit. The address range of a flash SPI peripheral is encoded with 1244 * absolute addresses which should be part of the overall controller 1245 * window. 1246 */ 1247 static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, 1248 const AspeedSegments *seg) 1249 { 1250 uint32_t reg = 0; 1251 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; 1252 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT; 1253 return reg; 1254 } 1255 1256 static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, 1257 uint32_t reg, AspeedSegments *seg) 1258 { 1259 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; 1260 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; 1261 } 1262 1263 static const AspeedSegments aspeed_2400_smc_segments[] = { 1264 { 0x10000000, 32 * MiB }, 1265 }; 1266 1267 static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data) 1268 { 1269 DeviceClass *dc = DEVICE_CLASS(klass); 1270 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1271 1272 dc->desc = "Aspeed 2400 SMC Controller"; 1273 asc->r_conf = R_CONF; 1274 asc->r_ce_ctrl = R_CE_CTRL; 1275 asc->r_ctrl0 = R_CTRL0; 1276 asc->r_timings = R_TIMINGS; 1277 asc->nregs_timings = 1; 1278 asc->conf_enable_w0 = CONF_ENABLE_W0; 1279 asc->max_peripherals = 1; 1280 asc->segments = aspeed_2400_smc_segments; 1281 asc->flash_window_base = 0x10000000; 1282 asc->flash_window_size = 0x6000000; 1283 asc->features = 0x0; 1284 asc->nregs = ASPEED_SMC_R_SMC_MAX; 1285 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1286 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1287 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1288 } 1289 1290 static const TypeInfo aspeed_2400_smc_info = { 1291 .name = "aspeed.smc-ast2400", 1292 .parent = TYPE_ASPEED_SMC, 1293 .class_init = aspeed_2400_smc_class_init, 1294 }; 1295 1296 static const AspeedSegments aspeed_2400_fmc_segments[] = { 1297 { 0x20000000, 64 * MiB }, /* start address is readonly */ 1298 { 0x24000000, 32 * MiB }, 1299 { 0x26000000, 32 * MiB }, 1300 { 0x28000000, 32 * MiB }, 1301 { 0x2A000000, 32 * MiB } 1302 }; 1303 1304 static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data) 1305 { 1306 DeviceClass *dc = DEVICE_CLASS(klass); 1307 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1308 1309 dc->desc = "Aspeed 2400 FMC Controller"; 1310 asc->r_conf = R_CONF; 1311 asc->r_ce_ctrl = R_CE_CTRL; 1312 asc->r_ctrl0 = R_CTRL0; 1313 asc->r_timings = R_TIMINGS; 1314 asc->nregs_timings = 1; 1315 asc->conf_enable_w0 = CONF_ENABLE_W0; 1316 asc->max_peripherals = 5; 1317 asc->segments = aspeed_2400_fmc_segments; 1318 asc->flash_window_base = 0x20000000; 1319 asc->flash_window_size = 0x10000000; 1320 asc->features = ASPEED_SMC_FEATURE_DMA; 1321 asc->dma_flash_mask = 0x0FFFFFFC; 1322 asc->dma_dram_mask = 0x1FFFFFFC; 1323 asc->nregs = ASPEED_SMC_R_MAX; 1324 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1325 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1326 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1327 } 1328 1329 static const TypeInfo aspeed_2400_fmc_info = { 1330 .name = "aspeed.fmc-ast2400", 1331 .parent = TYPE_ASPEED_SMC, 1332 .class_init = aspeed_2400_fmc_class_init, 1333 }; 1334 1335 static const AspeedSegments aspeed_2400_spi1_segments[] = { 1336 { 0x30000000, 64 * MiB }, 1337 }; 1338 1339 static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data) 1340 { 1341 DeviceClass *dc = DEVICE_CLASS(klass); 1342 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1343 1344 dc->desc = "Aspeed 2400 SPI1 Controller"; 1345 asc->r_conf = R_SPI_CONF; 1346 asc->r_ce_ctrl = 0xff; 1347 asc->r_ctrl0 = R_SPI_CTRL0; 1348 asc->r_timings = R_SPI_TIMINGS; 1349 asc->nregs_timings = 1; 1350 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0; 1351 asc->max_peripherals = 1; 1352 asc->segments = aspeed_2400_spi1_segments; 1353 asc->flash_window_base = 0x30000000; 1354 asc->flash_window_size = 0x10000000; 1355 asc->features = 0x0; 1356 asc->nregs = ASPEED_SMC_R_SPI_MAX; 1357 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1358 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1359 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1360 } 1361 1362 static const TypeInfo aspeed_2400_spi1_info = { 1363 .name = "aspeed.spi1-ast2400", 1364 .parent = TYPE_ASPEED_SMC, 1365 .class_init = aspeed_2400_spi1_class_init, 1366 }; 1367 1368 static const AspeedSegments aspeed_2500_fmc_segments[] = { 1369 { 0x20000000, 128 * MiB }, /* start address is readonly */ 1370 { 0x28000000, 32 * MiB }, 1371 { 0x2A000000, 32 * MiB }, 1372 }; 1373 1374 static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data) 1375 { 1376 DeviceClass *dc = DEVICE_CLASS(klass); 1377 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1378 1379 dc->desc = "Aspeed 2600 FMC Controller"; 1380 asc->r_conf = R_CONF; 1381 asc->r_ce_ctrl = R_CE_CTRL; 1382 asc->r_ctrl0 = R_CTRL0; 1383 asc->r_timings = R_TIMINGS; 1384 asc->nregs_timings = 1; 1385 asc->conf_enable_w0 = CONF_ENABLE_W0; 1386 asc->max_peripherals = 3; 1387 asc->segments = aspeed_2500_fmc_segments; 1388 asc->flash_window_base = 0x20000000; 1389 asc->flash_window_size = 0x10000000; 1390 asc->features = ASPEED_SMC_FEATURE_DMA; 1391 asc->dma_flash_mask = 0x0FFFFFFC; 1392 asc->dma_dram_mask = 0x3FFFFFFC; 1393 asc->nregs = ASPEED_SMC_R_MAX; 1394 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1395 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1396 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1397 } 1398 1399 static const TypeInfo aspeed_2500_fmc_info = { 1400 .name = "aspeed.fmc-ast2500", 1401 .parent = TYPE_ASPEED_SMC, 1402 .class_init = aspeed_2500_fmc_class_init, 1403 }; 1404 1405 static const AspeedSegments aspeed_2500_spi1_segments[] = { 1406 { 0x30000000, 32 * MiB }, /* start address is readonly */ 1407 { 0x32000000, 96 * MiB }, /* end address is readonly */ 1408 }; 1409 1410 static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data) 1411 { 1412 DeviceClass *dc = DEVICE_CLASS(klass); 1413 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1414 1415 dc->desc = "Aspeed 2600 SPI1 Controller"; 1416 asc->r_conf = R_CONF; 1417 asc->r_ce_ctrl = R_CE_CTRL; 1418 asc->r_ctrl0 = R_CTRL0; 1419 asc->r_timings = R_TIMINGS; 1420 asc->nregs_timings = 1; 1421 asc->conf_enable_w0 = CONF_ENABLE_W0; 1422 asc->max_peripherals = 2; 1423 asc->segments = aspeed_2500_spi1_segments; 1424 asc->flash_window_base = 0x30000000; 1425 asc->flash_window_size = 0x8000000; 1426 asc->features = 0x0; 1427 asc->nregs = ASPEED_SMC_R_MAX; 1428 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1429 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1430 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1431 } 1432 1433 static const TypeInfo aspeed_2500_spi1_info = { 1434 .name = "aspeed.spi1-ast2500", 1435 .parent = TYPE_ASPEED_SMC, 1436 .class_init = aspeed_2500_spi1_class_init, 1437 }; 1438 1439 static const AspeedSegments aspeed_2500_spi2_segments[] = { 1440 { 0x38000000, 32 * MiB }, /* start address is readonly */ 1441 { 0x3A000000, 96 * MiB }, /* end address is readonly */ 1442 }; 1443 1444 static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data) 1445 { 1446 DeviceClass *dc = DEVICE_CLASS(klass); 1447 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1448 1449 dc->desc = "Aspeed 2600 SPI2 Controller"; 1450 asc->r_conf = R_CONF; 1451 asc->r_ce_ctrl = R_CE_CTRL; 1452 asc->r_ctrl0 = R_CTRL0; 1453 asc->r_timings = R_TIMINGS; 1454 asc->nregs_timings = 1; 1455 asc->conf_enable_w0 = CONF_ENABLE_W0; 1456 asc->max_peripherals = 2; 1457 asc->segments = aspeed_2500_spi2_segments; 1458 asc->flash_window_base = 0x38000000; 1459 asc->flash_window_size = 0x8000000; 1460 asc->features = 0x0; 1461 asc->nregs = ASPEED_SMC_R_MAX; 1462 asc->segment_to_reg = aspeed_smc_segment_to_reg; 1463 asc->reg_to_segment = aspeed_smc_reg_to_segment; 1464 asc->dma_ctrl = aspeed_smc_dma_ctrl; 1465 } 1466 1467 static const TypeInfo aspeed_2500_spi2_info = { 1468 .name = "aspeed.spi2-ast2500", 1469 .parent = TYPE_ASPEED_SMC, 1470 .class_init = aspeed_2500_spi2_class_init, 1471 }; 1472 1473 /* 1474 * The Segment Registers of the AST2600 have a 1MB unit. The address 1475 * range of a flash SPI peripheral is encoded with offsets in the overall 1476 * controller window. The previous SoC AST2400 and AST2500 used 1477 * absolute addresses. Only bits [27:20] are relevant and the end 1478 * address is an upper bound limit. 1479 */ 1480 #define AST2600_SEG_ADDR_MASK 0x0ff00000 1481 1482 static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, 1483 const AspeedSegments *seg) 1484 { 1485 uint32_t reg = 0; 1486 1487 /* Disabled segments have a nil register */ 1488 if (!seg->size) { 1489 return 0; 1490 } 1491 1492 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ 1493 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ 1494 return reg; 1495 } 1496 1497 static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, 1498 uint32_t reg, AspeedSegments *seg) 1499 { 1500 uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; 1501 uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; 1502 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); 1503 1504 if (reg) { 1505 seg->addr = asc->flash_window_base + start_offset; 1506 seg->size = end_offset + MiB - start_offset; 1507 } else { 1508 seg->addr = asc->flash_window_base; 1509 seg->size = 0; 1510 } 1511 } 1512 1513 static const AspeedSegments aspeed_2600_fmc_segments[] = { 1514 { 0x0, 128 * MiB }, /* start address is readonly */ 1515 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ 1516 { 0x0, 0 }, /* disabled */ 1517 }; 1518 1519 static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data) 1520 { 1521 DeviceClass *dc = DEVICE_CLASS(klass); 1522 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1523 1524 dc->desc = "Aspeed 2600 FMC Controller"; 1525 asc->r_conf = R_CONF; 1526 asc->r_ce_ctrl = R_CE_CTRL; 1527 asc->r_ctrl0 = R_CTRL0; 1528 asc->r_timings = R_TIMINGS; 1529 asc->nregs_timings = 1; 1530 asc->conf_enable_w0 = CONF_ENABLE_W0; 1531 asc->max_peripherals = 3; 1532 asc->segments = aspeed_2600_fmc_segments; 1533 asc->flash_window_base = 0x20000000; 1534 asc->flash_window_size = 0x10000000; 1535 asc->features = ASPEED_SMC_FEATURE_DMA | 1536 ASPEED_SMC_FEATURE_WDT_CONTROL; 1537 asc->dma_flash_mask = 0x0FFFFFFC; 1538 asc->dma_dram_mask = 0x3FFFFFFC; 1539 asc->nregs = ASPEED_SMC_R_MAX; 1540 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1541 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1542 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1543 } 1544 1545 static const TypeInfo aspeed_2600_fmc_info = { 1546 .name = "aspeed.fmc-ast2600", 1547 .parent = TYPE_ASPEED_SMC, 1548 .class_init = aspeed_2600_fmc_class_init, 1549 }; 1550 1551 static const AspeedSegments aspeed_2600_spi1_segments[] = { 1552 { 0x0, 128 * MiB }, /* start address is readonly */ 1553 { 0x0, 0 }, /* disabled */ 1554 }; 1555 1556 static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data) 1557 { 1558 DeviceClass *dc = DEVICE_CLASS(klass); 1559 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1560 1561 dc->desc = "Aspeed 2600 SPI1 Controller"; 1562 asc->r_conf = R_CONF; 1563 asc->r_ce_ctrl = R_CE_CTRL; 1564 asc->r_ctrl0 = R_CTRL0; 1565 asc->r_timings = R_TIMINGS; 1566 asc->nregs_timings = 2; 1567 asc->conf_enable_w0 = CONF_ENABLE_W0; 1568 asc->max_peripherals = 2; 1569 asc->segments = aspeed_2600_spi1_segments; 1570 asc->flash_window_base = 0x30000000; 1571 asc->flash_window_size = 0x10000000; 1572 asc->features = ASPEED_SMC_FEATURE_DMA | 1573 ASPEED_SMC_FEATURE_DMA_GRANT; 1574 asc->dma_flash_mask = 0x0FFFFFFC; 1575 asc->dma_dram_mask = 0x3FFFFFFC; 1576 asc->nregs = ASPEED_SMC_R_MAX; 1577 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1578 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1579 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1580 } 1581 1582 static const TypeInfo aspeed_2600_spi1_info = { 1583 .name = "aspeed.spi1-ast2600", 1584 .parent = TYPE_ASPEED_SMC, 1585 .class_init = aspeed_2600_spi1_class_init, 1586 }; 1587 1588 static const AspeedSegments aspeed_2600_spi2_segments[] = { 1589 { 0x0, 128 * MiB }, /* start address is readonly */ 1590 { 0x0, 0 }, /* disabled */ 1591 { 0x0, 0 }, /* disabled */ 1592 }; 1593 1594 static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data) 1595 { 1596 DeviceClass *dc = DEVICE_CLASS(klass); 1597 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); 1598 1599 dc->desc = "Aspeed 2600 SPI2 Controller"; 1600 asc->r_conf = R_CONF; 1601 asc->r_ce_ctrl = R_CE_CTRL; 1602 asc->r_ctrl0 = R_CTRL0; 1603 asc->r_timings = R_TIMINGS; 1604 asc->nregs_timings = 3; 1605 asc->conf_enable_w0 = CONF_ENABLE_W0; 1606 asc->max_peripherals = 3; 1607 asc->segments = aspeed_2600_spi2_segments; 1608 asc->flash_window_base = 0x50000000; 1609 asc->flash_window_size = 0x10000000; 1610 asc->features = ASPEED_SMC_FEATURE_DMA | 1611 ASPEED_SMC_FEATURE_DMA_GRANT; 1612 asc->dma_flash_mask = 0x0FFFFFFC; 1613 asc->dma_dram_mask = 0x3FFFFFFC; 1614 asc->nregs = ASPEED_SMC_R_MAX; 1615 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; 1616 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; 1617 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; 1618 } 1619 1620 static const TypeInfo aspeed_2600_spi2_info = { 1621 .name = "aspeed.spi2-ast2600", 1622 .parent = TYPE_ASPEED_SMC, 1623 .class_init = aspeed_2600_spi2_class_init, 1624 }; 1625 1626 static void aspeed_smc_register_types(void) 1627 { 1628 type_register_static(&aspeed_smc_info); 1629 type_register_static(&aspeed_2400_smc_info); 1630 type_register_static(&aspeed_2400_fmc_info); 1631 type_register_static(&aspeed_2400_spi1_info); 1632 type_register_static(&aspeed_2500_fmc_info); 1633 type_register_static(&aspeed_2500_spi1_info); 1634 type_register_static(&aspeed_2500_spi2_info); 1635 type_register_static(&aspeed_2600_fmc_info); 1636 type_register_static(&aspeed_2600_spi1_info); 1637 type_register_static(&aspeed_2600_spi2_info); 1638 } 1639 1640 type_init(aspeed_smc_register_types) 1641