1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "sysemu/cpus.h" 15 #include "sysemu/dma.h" 16 #include "monitor/monitor.h" 17 #include "hw/ppc/fdt.h" 18 #include "hw/ppc/pnv.h" 19 #include "hw/ppc/pnv_core.h" 20 #include "hw/ppc/pnv_xscom.h" 21 #include "hw/ppc/xive2.h" 22 #include "hw/ppc/pnv_xive.h" 23 #include "hw/ppc/xive_regs.h" 24 #include "hw/ppc/xive2_regs.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/qdev-properties.h" 27 #include "sysemu/reset.h" 28 29 #include <libfdt.h> 30 31 #include "pnv_xive2_regs.h" 32 33 #undef XIVE2_DEBUG 34 35 /* 36 * Virtual structures table (VST) 37 */ 38 #define SBE_PER_BYTE 4 39 40 typedef struct XiveVstInfo { 41 const char *name; 42 uint32_t size; 43 uint32_t max_blocks; 44 } XiveVstInfo; 45 46 static const XiveVstInfo vst_infos[] = { 47 48 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 }, 49 [VST_ESB] = { "ESB", 1, 16 }, 50 [VST_END] = { "ENDT", sizeof(Xive2End), 16 }, 51 52 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 }, 53 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 }, 54 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 }, 55 56 [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */ 57 [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */ 58 59 /* 60 * This table contains the backing store pages for the interrupt 61 * fifos of the VC sub-engine in case of overflow. 62 * 63 * 0 - IPI, 64 * 1 - HWD, 65 * 2 - NxC, 66 * 3 - INT, 67 * 4 - OS-Queue, 68 * 5 - Pool-Queue, 69 * 6 - Hard-Queue 70 */ 71 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT }, 72 }; 73 74 #define xive2_error(xive, fmt, ...) \ 75 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \ 76 (xive)->chip->chip_id, ## __VA_ARGS__); 77 78 /* 79 * QEMU version of the GETFIELD/SETFIELD macros 80 * 81 * TODO: It might be better to use the existing extract64() and 82 * deposit64() but this means that all the register definitions will 83 * change and become incompatible with the ones found in skiboot. 84 * 85 * Keep it as it is for now until we find a common ground. 86 */ 87 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 88 { 89 return (word & mask) >> ctz64(mask); 90 } 91 92 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 93 uint64_t value) 94 { 95 return (word & ~mask) | ((value << ctz64(mask)) & mask); 96 } 97 98 /* 99 * TODO: Document block id override 100 */ 101 static uint32_t pnv_xive2_block_id(PnvXive2 *xive) 102 { 103 uint8_t blk = xive->chip->chip_id; 104 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; 105 106 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) { 107 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val); 108 } 109 110 return blk; 111 } 112 113 /* 114 * Remote access to controllers. HW uses MMIOs. For now, a simple scan 115 * of the chips is good enough. 116 * 117 * TODO: Block scope support 118 */ 119 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk) 120 { 121 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 122 int i; 123 124 for (i = 0; i < pnv->num_chips; i++) { 125 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 126 PnvXive2 *xive = &chip10->xive; 127 128 if (pnv_xive2_block_id(xive) == blk) { 129 return xive; 130 } 131 } 132 return NULL; 133 } 134 135 /* 136 * VST accessors for ESB, EAT, ENDT, NVP 137 * 138 * Indirect VST tables are arrays of VSDs pointing to a page (of same 139 * size). Each page is a direct VST table. 140 */ 141 142 #define XIVE_VSD_SIZE 8 143 144 /* Indirect page size can be 4K, 64K, 2M, 16M. */ 145 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift) 146 { 147 return page_shift == 12 || page_shift == 16 || 148 page_shift == 21 || page_shift == 24; 149 } 150 151 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type, 152 uint64_t vsd, uint32_t idx) 153 { 154 const XiveVstInfo *info = &vst_infos[type]; 155 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 156 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 157 uint32_t idx_max; 158 159 idx_max = vst_tsize / info->size - 1; 160 if (idx > idx_max) { 161 #ifdef XIVE2_DEBUG 162 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?", 163 info->name, idx, idx_max); 164 #endif 165 return 0; 166 } 167 168 return vst_addr + idx * info->size; 169 } 170 171 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type, 172 uint64_t vsd, uint32_t idx) 173 { 174 const XiveVstInfo *info = &vst_infos[type]; 175 uint64_t vsd_addr; 176 uint32_t vsd_idx; 177 uint32_t page_shift; 178 uint32_t vst_per_page; 179 180 /* Get the page size of the indirect table. */ 181 vsd_addr = vsd & VSD_ADDRESS_MASK; 182 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 183 184 if (!(vsd & VSD_ADDRESS_MASK)) { 185 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 186 return 0; 187 } 188 189 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 190 191 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 192 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 193 page_shift); 194 return 0; 195 } 196 197 vst_per_page = (1ull << page_shift) / info->size; 198 vsd_idx = idx / vst_per_page; 199 200 /* Load the VSD we are looking for, if not already done */ 201 if (vsd_idx) { 202 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE; 203 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, 204 MEMTXATTRS_UNSPECIFIED); 205 206 if (!(vsd & VSD_ADDRESS_MASK)) { 207 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); 208 return 0; 209 } 210 211 /* 212 * Check that the pages have a consistent size across the 213 * indirect table 214 */ 215 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) { 216 xive2_error(xive, "VST: %s entry %x indirect page size differ !?", 217 info->name, idx); 218 return 0; 219 } 220 } 221 222 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); 223 } 224 225 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk, 226 uint32_t idx) 227 { 228 const XiveVstInfo *info = &vst_infos[type]; 229 uint64_t vsd; 230 231 if (blk >= info->max_blocks) { 232 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?", 233 blk, info->name, idx); 234 return 0; 235 } 236 237 vsd = xive->vsds[type][blk]; 238 239 /* Remote VST access */ 240 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { 241 xive = pnv_xive2_get_remote(blk); 242 243 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0; 244 } 245 246 if (VSD_INDIRECT & vsd) { 247 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx); 248 } 249 250 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx); 251 } 252 253 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, 254 uint32_t idx, void *data) 255 { 256 const XiveVstInfo *info = &vst_infos[type]; 257 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 258 259 if (!addr) { 260 return -1; 261 } 262 263 cpu_physical_memory_read(addr, data, info->size); 264 return 0; 265 } 266 267 #define XIVE_VST_WORD_ALL -1 268 269 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, 270 uint32_t idx, void *data, uint32_t word_number) 271 { 272 const XiveVstInfo *info = &vst_infos[type]; 273 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); 274 275 if (!addr) { 276 return -1; 277 } 278 279 if (word_number == XIVE_VST_WORD_ALL) { 280 cpu_physical_memory_write(addr, data, info->size); 281 } else { 282 cpu_physical_memory_write(addr + word_number * 4, 283 data + word_number * 4, 4); 284 } 285 return 0; 286 } 287 288 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 289 uint8_t *pq) 290 { 291 PnvXive2 *xive = PNV_XIVE2(xrtr); 292 293 if (pnv_xive2_block_id(xive) != blk) { 294 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 295 return -1; 296 } 297 298 *pq = xive_source_esb_get(&xive->ipi_source, idx); 299 return 0; 300 } 301 302 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 303 uint8_t *pq) 304 { 305 PnvXive2 *xive = PNV_XIVE2(xrtr); 306 307 if (pnv_xive2_block_id(xive) != blk) { 308 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 309 return -1; 310 } 311 312 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); 313 return 0; 314 } 315 316 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 317 Xive2End *end) 318 { 319 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end); 320 } 321 322 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 323 Xive2End *end, uint8_t word_number) 324 { 325 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end, 326 word_number); 327 } 328 329 static int pnv_xive2_end_update(PnvXive2 *xive) 330 { 331 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 332 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 333 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 334 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 335 int i; 336 uint64_t endc_watch[4]; 337 338 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 339 endc_watch[i] = 340 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]); 341 } 342 343 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch, 344 XIVE_VST_WORD_ALL); 345 } 346 347 static void pnv_xive2_end_cache_load(PnvXive2 *xive) 348 { 349 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, 350 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 351 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX, 352 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]); 353 uint64_t endc_watch[4] = { 0 }; 354 int i; 355 356 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) { 357 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx); 358 } 359 360 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) { 361 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] = 362 be64_to_cpu(endc_watch[i]); 363 } 364 } 365 366 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 367 Xive2Nvp *nvp) 368 { 369 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp); 370 } 371 372 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 373 Xive2Nvp *nvp, uint8_t word_number) 374 { 375 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp, 376 word_number); 377 } 378 379 static int pnv_xive2_nvp_update(PnvXive2 *xive) 380 { 381 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 382 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 383 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 384 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 385 int i; 386 uint64_t nxc_watch[4]; 387 388 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 389 nxc_watch[i] = 390 cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]); 391 } 392 393 return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch, 394 XIVE_VST_WORD_ALL); 395 } 396 397 static void pnv_xive2_nvp_cache_load(PnvXive2 *xive) 398 { 399 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, 400 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 401 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX, 402 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]); 403 uint64_t nxc_watch[4] = { 0 }; 404 int i; 405 406 if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) { 407 xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx); 408 } 409 410 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) { 411 xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] = 412 be64_to_cpu(nxc_watch[i]); 413 } 414 } 415 416 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx, 417 Xive2Eas *eas) 418 { 419 PnvXive2 *xive = PNV_XIVE2(xrtr); 420 421 if (pnv_xive2_block_id(xive) != blk) { 422 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx)); 423 return -1; 424 } 425 426 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas); 427 } 428 429 static uint32_t pnv_xive2_get_config(Xive2Router *xrtr) 430 { 431 PnvXive2 *xive = PNV_XIVE2(xrtr); 432 uint32_t cfg = 0; 433 434 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { 435 cfg |= XIVE2_GEN1_TIMA_OS; 436 } 437 438 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { 439 cfg |= XIVE2_VP_SAVE_RESTORE; 440 } 441 442 if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE, 443 xive->cq_regs[CQ_XIVE_CFG >> 3]) == CQ_XIVE_CFG_THREADID_8BITS) { 444 cfg |= XIVE2_THREADID_8BITS; 445 } 446 447 return cfg; 448 } 449 450 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu) 451 { 452 int pir = ppc_cpu_pir(cpu); 453 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); 454 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1; 455 uint32_t bit = pir & 0x3f; 456 457 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); 458 } 459 460 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format, 461 uint8_t nvt_blk, uint32_t nvt_idx, 462 bool cam_ignore, uint8_t priority, 463 uint32_t logic_serv, XiveTCTXMatch *match) 464 { 465 PnvXive2 *xive = PNV_XIVE2(xptr); 466 PnvChip *chip = xive->chip; 467 int count = 0; 468 int i, j; 469 bool gen1_tima_os = 470 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 471 472 for (i = 0; i < chip->nr_cores; i++) { 473 PnvCore *pc = chip->cores[i]; 474 CPUCore *cc = CPU_CORE(pc); 475 476 for (j = 0; j < cc->nr_threads; j++) { 477 PowerPCCPU *cpu = pc->threads[j]; 478 XiveTCTX *tctx; 479 int ring; 480 481 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 482 continue; 483 } 484 485 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 486 487 if (gen1_tima_os) { 488 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk, 489 nvt_idx, cam_ignore, 490 logic_serv); 491 } else { 492 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk, 493 nvt_idx, cam_ignore, 494 logic_serv); 495 } 496 497 /* 498 * Save the context and follow on to catch duplicates, 499 * that we don't support yet. 500 */ 501 if (ring != -1) { 502 if (match->tctx) { 503 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a " 504 "thread context NVT %x/%x\n", 505 nvt_blk, nvt_idx); 506 return false; 507 } 508 509 match->ring = ring; 510 match->tctx = tctx; 511 count++; 512 } 513 } 514 } 515 516 return count; 517 } 518 519 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) 520 { 521 return pnv_xive2_block_id(PNV_XIVE2(xrtr)); 522 } 523 524 /* 525 * The TIMA MMIO space is shared among the chips and to identify the 526 * chip from which the access is being done, we extract the chip id 527 * from the PIR. 528 */ 529 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu) 530 { 531 int pir = ppc_cpu_pir(cpu); 532 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; 533 PnvXive2 *xive = PNV_XIVE2(xptr); 534 535 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 536 xive2_error(xive, "IC: CPU %x is not enabled", pir); 537 } 538 return xive; 539 } 540 541 /* 542 * The internal sources of the interrupt controller have no knowledge 543 * of the XIVE2 chip on which they reside. Encode the block id in the 544 * source interrupt number before forwarding the source event 545 * notification to the Router. This is required on a multichip system. 546 */ 547 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked) 548 { 549 PnvXive2 *xive = PNV_XIVE2(xn); 550 uint8_t blk = pnv_xive2_block_id(xive); 551 552 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked); 553 } 554 555 /* 556 * Set Translation Tables 557 * 558 * TODO add support for multiple sets 559 */ 560 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val) 561 { 562 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); 563 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT, 564 xive->cq_regs[CQ_TAR >> 3]); 565 566 switch (tsel) { 567 case CQ_TAR_NVPG: 568 case CQ_TAR_ESB: 569 case CQ_TAR_END: 570 xive->tables[tsel][entry] = val; 571 break; 572 default: 573 xive2_error(xive, "IC: unsupported table %d", tsel); 574 return -1; 575 } 576 577 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { 578 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, 579 xive->cq_regs[CQ_TAR >> 3], ++entry); 580 } 581 582 return 0; 583 } 584 /* 585 * Virtual Structure Tables (VST) configuration 586 */ 587 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type, 588 uint8_t blk, uint64_t vsd) 589 { 590 Xive2EndSource *end_xsrc = &xive->end_source; 591 XiveSource *xsrc = &xive->ipi_source; 592 const XiveVstInfo *info = &vst_infos[type]; 593 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 594 uint64_t vst_tsize = 1ull << page_shift; 595 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 596 597 /* Basic checks */ 598 599 if (VSD_INDIRECT & vsd) { 600 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 601 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 602 page_shift); 603 return; 604 } 605 } 606 607 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) { 608 xive2_error(xive, "VST: %s table address 0x%"PRIx64 609 " is not aligned with page shift %d", 610 info->name, vst_addr, page_shift); 611 return; 612 } 613 614 /* Record the table configuration (in SRAM on HW) */ 615 xive->vsds[type][blk] = vsd; 616 617 /* Now tune the models with the configuration provided by the FW */ 618 619 switch (type) { 620 case VST_ESB: 621 /* 622 * Backing store pages for the source PQ bits. The model does 623 * not use these PQ bits backed in RAM because the XiveSource 624 * model has its own. 625 * 626 * If the table is direct, we can compute the number of PQ 627 * entries provisioned by FW (such as skiboot) and resize the 628 * ESB window accordingly. 629 */ 630 if (!(VSD_INDIRECT & vsd)) { 631 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE 632 * (1ull << xsrc->esb_shift)); 633 } 634 635 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); 636 break; 637 638 case VST_EAS: /* Nothing to be done */ 639 break; 640 641 case VST_END: 642 /* 643 * Backing store pages for the END. 644 */ 645 if (!(VSD_INDIRECT & vsd)) { 646 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) 647 * (1ull << end_xsrc->esb_shift)); 648 } 649 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); 650 break; 651 652 case VST_NVP: /* Not modeled */ 653 case VST_NVG: /* Not modeled */ 654 case VST_NVC: /* Not modeled */ 655 case VST_IC: /* Not modeled */ 656 case VST_SYNC: /* Not modeled */ 657 case VST_ERQ: /* Not modeled */ 658 break; 659 660 default: 661 g_assert_not_reached(); 662 } 663 } 664 665 /* 666 * Both PC and VC sub-engines are configured as each use the Virtual 667 * Structure Tables 668 */ 669 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd) 670 { 671 uint8_t mode = GETFIELD(VSD_MODE, vsd); 672 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT, 673 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 674 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS, 675 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); 676 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK; 677 678 if (type > VST_ERQ) { 679 xive2_error(xive, "VST: invalid table type %d", type); 680 return; 681 } 682 683 if (blk >= vst_infos[type].max_blocks) { 684 xive2_error(xive, "VST: invalid block id %d for" 685 " %s table", blk, vst_infos[type].name); 686 return; 687 } 688 689 if (!vst_addr) { 690 xive2_error(xive, "VST: invalid %s table address", 691 vst_infos[type].name); 692 return; 693 } 694 695 switch (mode) { 696 case VSD_MODE_FORWARD: 697 xive->vsds[type][blk] = vsd; 698 break; 699 700 case VSD_MODE_EXCLUSIVE: 701 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd); 702 break; 703 704 default: 705 xive2_error(xive, "VST: unsupported table mode %d", mode); 706 return; 707 } 708 } 709 710 /* 711 * MMIO handlers 712 */ 713 714 715 /* 716 * IC BAR layout 717 * 718 * Page 0: Internal CQ register accesses (reads & writes) 719 * Page 1: Internal PC register accesses (reads & writes) 720 * Page 2: Internal VC register accesses (reads & writes) 721 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes) 722 * Page 4: Notify Port page (writes only, w/data), 723 * Page 5: Reserved 724 * Page 6: Sync Poll page (writes only, dataless) 725 * Page 7: Sync Inject page (writes only, dataless) 726 * Page 8: LSI Trigger page (writes only, dataless) 727 * Page 9: LSI SB Management page (reads & writes dataless) 728 * Pages 10-255: Reserved 729 * Pages 256-383: Direct mapped Thread Context Area (reads & writes) 730 * covering the 128 threads in P10. 731 * Pages 384-511: Reserved 732 */ 733 typedef struct PnvXive2Region { 734 const char *name; 735 uint32_t pgoff; 736 uint32_t pgsize; 737 const MemoryRegionOps *ops; 738 } PnvXive2Region; 739 740 static const MemoryRegionOps pnv_xive2_ic_cq_ops; 741 static const MemoryRegionOps pnv_xive2_ic_pc_ops; 742 static const MemoryRegionOps pnv_xive2_ic_vc_ops; 743 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops; 744 static const MemoryRegionOps pnv_xive2_ic_notify_ops; 745 static const MemoryRegionOps pnv_xive2_ic_sync_ops; 746 static const MemoryRegionOps pnv_xive2_ic_lsi_ops; 747 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops; 748 749 /* 512 pages. 4K: 2M range, 64K: 32M range */ 750 static const PnvXive2Region pnv_xive2_ic_regions[] = { 751 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops }, 752 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops }, 753 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops }, 754 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops }, 755 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops }, 756 /* page 5 reserved */ 757 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops }, 758 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops }, 759 /* pages 10-255 reserved */ 760 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops }, 761 /* pages 384-511 reserved */ 762 }; 763 764 /* 765 * CQ operations 766 */ 767 768 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset, 769 unsigned size) 770 { 771 PnvXive2 *xive = PNV_XIVE2(opaque); 772 uint32_t reg = offset >> 3; 773 uint64_t val = 0; 774 775 switch (offset) { 776 case CQ_XIVE_CAP: /* Set at reset */ 777 case CQ_XIVE_CFG: 778 val = xive->cq_regs[reg]; 779 break; 780 case CQ_MSGSND: /* TODO check the #cores of the machine */ 781 val = 0xffffffff00000000; 782 break; 783 case CQ_CFG_PB_GEN: 784 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */ 785 break; 786 default: 787 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset); 788 } 789 790 return val; 791 } 792 793 static uint64_t pnv_xive2_bar_size(uint64_t val) 794 { 795 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24); 796 } 797 798 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset, 799 uint64_t val, unsigned size) 800 { 801 PnvXive2 *xive = PNV_XIVE2(opaque); 802 MemoryRegion *sysmem = get_system_memory(); 803 uint32_t reg = offset >> 3; 804 int i; 805 806 switch (offset) { 807 case CQ_XIVE_CFG: 808 case CQ_RST_CTL: /* TODO: reset all BARs */ 809 break; 810 811 case CQ_IC_BAR: 812 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; 813 if (!(val & CQ_IC_BAR_VALID)) { 814 xive->ic_base = 0; 815 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { 816 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 817 memory_region_del_subregion(&xive->ic_mmio, 818 &xive->ic_mmios[i]); 819 } 820 memory_region_del_subregion(sysmem, &xive->ic_mmio); 821 } 822 } else { 823 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); 824 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { 825 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 826 memory_region_add_subregion(&xive->ic_mmio, 827 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, 828 &xive->ic_mmios[i]); 829 } 830 memory_region_add_subregion(sysmem, xive->ic_base, 831 &xive->ic_mmio); 832 } 833 } 834 break; 835 836 case CQ_TM_BAR: 837 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; 838 if (!(val & CQ_TM_BAR_VALID)) { 839 xive->tm_base = 0; 840 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { 841 memory_region_del_subregion(sysmem, &xive->tm_mmio); 842 } 843 } else { 844 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); 845 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { 846 memory_region_add_subregion(sysmem, xive->tm_base, 847 &xive->tm_mmio); 848 } 849 } 850 break; 851 852 case CQ_ESB_BAR: 853 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; 854 if (!(val & CQ_BAR_VALID)) { 855 xive->esb_base = 0; 856 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 857 memory_region_del_subregion(sysmem, &xive->esb_mmio); 858 } 859 } else { 860 xive->esb_base = val & CQ_BAR_ADDR; 861 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 862 memory_region_set_size(&xive->esb_mmio, 863 pnv_xive2_bar_size(val)); 864 memory_region_add_subregion(sysmem, xive->esb_base, 865 &xive->esb_mmio); 866 } 867 } 868 break; 869 870 case CQ_END_BAR: 871 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; 872 if (!(val & CQ_BAR_VALID)) { 873 xive->end_base = 0; 874 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 875 memory_region_del_subregion(sysmem, &xive->end_mmio); 876 } 877 } else { 878 xive->end_base = val & CQ_BAR_ADDR; 879 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 880 memory_region_set_size(&xive->end_mmio, 881 pnv_xive2_bar_size(val)); 882 memory_region_add_subregion(sysmem, xive->end_base, 883 &xive->end_mmio); 884 } 885 } 886 break; 887 888 case CQ_NVC_BAR: 889 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; 890 if (!(val & CQ_BAR_VALID)) { 891 xive->nvc_base = 0; 892 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 893 memory_region_del_subregion(sysmem, &xive->nvc_mmio); 894 } 895 } else { 896 xive->nvc_base = val & CQ_BAR_ADDR; 897 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 898 memory_region_set_size(&xive->nvc_mmio, 899 pnv_xive2_bar_size(val)); 900 memory_region_add_subregion(sysmem, xive->nvc_base, 901 &xive->nvc_mmio); 902 } 903 } 904 break; 905 906 case CQ_NVPG_BAR: 907 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; 908 if (!(val & CQ_BAR_VALID)) { 909 xive->nvpg_base = 0; 910 if (xive->cq_regs[reg] & CQ_BAR_VALID) { 911 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); 912 } 913 } else { 914 xive->nvpg_base = val & CQ_BAR_ADDR; 915 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { 916 memory_region_set_size(&xive->nvpg_mmio, 917 pnv_xive2_bar_size(val)); 918 memory_region_add_subregion(sysmem, xive->nvpg_base, 919 &xive->nvpg_mmio); 920 } 921 } 922 break; 923 924 case CQ_TAR: /* Set Translation Table Address */ 925 break; 926 case CQ_TDR: /* Set Translation Table Data */ 927 pnv_xive2_stt_set_data(xive, val); 928 break; 929 case CQ_FIRMASK_OR: /* FIR error reporting */ 930 break; 931 default: 932 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset); 933 return; 934 } 935 936 xive->cq_regs[reg] = val; 937 } 938 939 static const MemoryRegionOps pnv_xive2_ic_cq_ops = { 940 .read = pnv_xive2_ic_cq_read, 941 .write = pnv_xive2_ic_cq_write, 942 .endianness = DEVICE_BIG_ENDIAN, 943 .valid = { 944 .min_access_size = 8, 945 .max_access_size = 8, 946 }, 947 .impl = { 948 .min_access_size = 8, 949 .max_access_size = 8, 950 }, 951 }; 952 953 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, 954 unsigned size) 955 { 956 PnvXive2 *xive = PNV_XIVE2(opaque); 957 uint64_t val = 0; 958 uint32_t reg = offset >> 3; 959 960 switch (offset) { 961 /* 962 * VSD table settings. 963 */ 964 case VC_VSD_TABLE_ADDR: 965 case VC_VSD_TABLE_DATA: 966 val = xive->vc_regs[reg]; 967 break; 968 969 /* 970 * ESB cache updates (not modeled) 971 */ 972 case VC_ESBC_FLUSH_CTRL: 973 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; 974 val = xive->vc_regs[reg]; 975 break; 976 977 /* 978 * EAS cache updates (not modeled) 979 */ 980 case VC_EASC_FLUSH_CTRL: 981 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; 982 val = xive->vc_regs[reg]; 983 break; 984 985 /* 986 * END cache updates 987 */ 988 case VC_ENDC_WATCH0_SPEC: 989 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); 990 val = xive->vc_regs[reg]; 991 break; 992 993 case VC_ENDC_WATCH0_DATA0: 994 /* 995 * Load DATA registers from cache with data requested by the 996 * SPEC register 997 */ 998 pnv_xive2_end_cache_load(xive); 999 val = xive->vc_regs[reg]; 1000 break; 1001 1002 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1003 val = xive->vc_regs[reg]; 1004 break; 1005 1006 case VC_ENDC_FLUSH_CTRL: 1007 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; 1008 val = xive->vc_regs[reg]; 1009 break; 1010 1011 /* 1012 * Indirect invalidation 1013 */ 1014 case VC_AT_MACRO_KILL_MASK: 1015 val = xive->vc_regs[reg]; 1016 break; 1017 1018 case VC_AT_MACRO_KILL: 1019 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; 1020 val = xive->vc_regs[reg]; 1021 break; 1022 1023 /* 1024 * Interrupt fifo overflow in memory backing store (Not modeled) 1025 */ 1026 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1027 val = xive->vc_regs[reg]; 1028 break; 1029 1030 /* 1031 * Synchronisation 1032 */ 1033 case VC_ENDC_SYNC_DONE: 1034 val = VC_ENDC_SYNC_POLL_DONE; 1035 break; 1036 default: 1037 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset); 1038 } 1039 1040 return val; 1041 } 1042 1043 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset, 1044 uint64_t val, unsigned size) 1045 { 1046 PnvXive2 *xive = PNV_XIVE2(opaque); 1047 uint32_t reg = offset >> 3; 1048 1049 switch (offset) { 1050 /* 1051 * VSD table settings. 1052 */ 1053 case VC_VSD_TABLE_ADDR: 1054 break; 1055 case VC_VSD_TABLE_DATA: 1056 pnv_xive2_vst_set_data(xive, val); 1057 break; 1058 1059 /* 1060 * ESB cache updates (not modeled) 1061 */ 1062 /* case VC_ESBC_FLUSH_CTRL: */ 1063 case VC_ESBC_FLUSH_POLL: 1064 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; 1065 /* ESB update */ 1066 break; 1067 1068 /* 1069 * EAS cache updates (not modeled) 1070 */ 1071 /* case VC_EASC_FLUSH_CTRL: */ 1072 case VC_EASC_FLUSH_POLL: 1073 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; 1074 /* EAS update */ 1075 break; 1076 1077 /* 1078 * END cache updates 1079 */ 1080 case VC_ENDC_WATCH0_SPEC: 1081 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */ 1082 break; 1083 1084 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3: 1085 break; 1086 case VC_ENDC_WATCH0_DATA0: 1087 /* writing to DATA0 triggers the cache write */ 1088 xive->vc_regs[reg] = val; 1089 pnv_xive2_end_update(xive); 1090 break; 1091 1092 1093 /* case VC_ENDC_FLUSH_CTRL: */ 1094 case VC_ENDC_FLUSH_POLL: 1095 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; 1096 break; 1097 1098 /* 1099 * Indirect invalidation 1100 */ 1101 case VC_AT_MACRO_KILL: 1102 case VC_AT_MACRO_KILL_MASK: 1103 break; 1104 1105 /* 1106 * Interrupt fifo overflow in memory backing store (Not modeled) 1107 */ 1108 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6: 1109 break; 1110 1111 /* 1112 * Synchronisation 1113 */ 1114 case VC_ENDC_SYNC_DONE: 1115 break; 1116 1117 default: 1118 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset); 1119 return; 1120 } 1121 1122 xive->vc_regs[reg] = val; 1123 } 1124 1125 static const MemoryRegionOps pnv_xive2_ic_vc_ops = { 1126 .read = pnv_xive2_ic_vc_read, 1127 .write = pnv_xive2_ic_vc_write, 1128 .endianness = DEVICE_BIG_ENDIAN, 1129 .valid = { 1130 .min_access_size = 8, 1131 .max_access_size = 8, 1132 }, 1133 .impl = { 1134 .min_access_size = 8, 1135 .max_access_size = 8, 1136 }, 1137 }; 1138 1139 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset, 1140 unsigned size) 1141 { 1142 PnvXive2 *xive = PNV_XIVE2(opaque); 1143 uint64_t val = -1; 1144 uint32_t reg = offset >> 3; 1145 1146 switch (offset) { 1147 /* 1148 * VSD table settings. 1149 */ 1150 case PC_VSD_TABLE_ADDR: 1151 case PC_VSD_TABLE_DATA: 1152 val = xive->pc_regs[reg]; 1153 break; 1154 1155 /* 1156 * cache updates 1157 */ 1158 case PC_NXC_WATCH0_SPEC: 1159 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); 1160 val = xive->pc_regs[reg]; 1161 break; 1162 1163 case PC_NXC_WATCH0_DATA0: 1164 /* 1165 * Load DATA registers from cache with data requested by the 1166 * SPEC register 1167 */ 1168 pnv_xive2_nvp_cache_load(xive); 1169 val = xive->pc_regs[reg]; 1170 break; 1171 1172 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1173 val = xive->pc_regs[reg]; 1174 break; 1175 1176 case PC_NXC_FLUSH_CTRL: 1177 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; 1178 val = xive->pc_regs[reg]; 1179 break; 1180 1181 /* 1182 * Indirect invalidation 1183 */ 1184 case PC_AT_KILL: 1185 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; 1186 val = xive->pc_regs[reg]; 1187 break; 1188 1189 default: 1190 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset); 1191 } 1192 1193 return val; 1194 } 1195 1196 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset, 1197 uint64_t val, unsigned size) 1198 { 1199 PnvXive2 *xive = PNV_XIVE2(opaque); 1200 uint32_t reg = offset >> 3; 1201 1202 switch (offset) { 1203 1204 /* 1205 * VSD table settings. Only taken into account in the VC 1206 * sub-engine because the Xive2Router model combines both VC and PC 1207 * sub-engines 1208 */ 1209 case PC_VSD_TABLE_ADDR: 1210 case PC_VSD_TABLE_DATA: 1211 break; 1212 1213 /* 1214 * cache updates 1215 */ 1216 case PC_NXC_WATCH0_SPEC: 1217 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */ 1218 break; 1219 1220 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3: 1221 break; 1222 case PC_NXC_WATCH0_DATA0: 1223 /* writing to DATA0 triggers the cache write */ 1224 xive->pc_regs[reg] = val; 1225 pnv_xive2_nvp_update(xive); 1226 break; 1227 1228 /* case PC_NXC_FLUSH_CTRL: */ 1229 case PC_NXC_FLUSH_POLL: 1230 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; 1231 break; 1232 1233 /* 1234 * Indirect invalidation 1235 */ 1236 case PC_AT_KILL: 1237 case PC_AT_KILL_MASK: 1238 break; 1239 1240 default: 1241 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset); 1242 return; 1243 } 1244 1245 xive->pc_regs[reg] = val; 1246 } 1247 1248 static const MemoryRegionOps pnv_xive2_ic_pc_ops = { 1249 .read = pnv_xive2_ic_pc_read, 1250 .write = pnv_xive2_ic_pc_write, 1251 .endianness = DEVICE_BIG_ENDIAN, 1252 .valid = { 1253 .min_access_size = 8, 1254 .max_access_size = 8, 1255 }, 1256 .impl = { 1257 .min_access_size = 8, 1258 .max_access_size = 8, 1259 }, 1260 }; 1261 1262 1263 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset, 1264 unsigned size) 1265 { 1266 PnvXive2 *xive = PNV_XIVE2(opaque); 1267 uint64_t val = -1; 1268 uint32_t reg = offset >> 3; 1269 1270 switch (offset) { 1271 /* 1272 * XIVE2 hardware thread enablement 1273 */ 1274 case TCTXT_EN0: 1275 case TCTXT_EN1: 1276 val = xive->tctxt_regs[reg]; 1277 break; 1278 1279 case TCTXT_EN0_SET: 1280 case TCTXT_EN0_RESET: 1281 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; 1282 break; 1283 case TCTXT_EN1_SET: 1284 case TCTXT_EN1_RESET: 1285 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; 1286 break; 1287 default: 1288 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset); 1289 } 1290 1291 return val; 1292 } 1293 1294 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset, 1295 uint64_t val, unsigned size) 1296 { 1297 PnvXive2 *xive = PNV_XIVE2(opaque); 1298 1299 switch (offset) { 1300 /* 1301 * XIVE2 hardware thread enablement 1302 */ 1303 case TCTXT_EN0: /* Physical Thread Enable */ 1304 case TCTXT_EN1: /* Physical Thread Enable (fused core) */ 1305 break; 1306 1307 case TCTXT_EN0_SET: 1308 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; 1309 break; 1310 case TCTXT_EN1_SET: 1311 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; 1312 break; 1313 case TCTXT_EN0_RESET: 1314 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; 1315 break; 1316 case TCTXT_EN1_RESET: 1317 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; 1318 break; 1319 1320 default: 1321 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset); 1322 return; 1323 } 1324 } 1325 1326 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = { 1327 .read = pnv_xive2_ic_tctxt_read, 1328 .write = pnv_xive2_ic_tctxt_write, 1329 .endianness = DEVICE_BIG_ENDIAN, 1330 .valid = { 1331 .min_access_size = 8, 1332 .max_access_size = 8, 1333 }, 1334 .impl = { 1335 .min_access_size = 8, 1336 .max_access_size = 8, 1337 }, 1338 }; 1339 1340 /* 1341 * Redirect XSCOM to MMIO handlers 1342 */ 1343 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset, 1344 unsigned size) 1345 { 1346 PnvXive2 *xive = PNV_XIVE2(opaque); 1347 uint64_t val = -1; 1348 uint32_t xscom_reg = offset >> 3; 1349 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1350 1351 switch (xscom_reg) { 1352 case 0x000 ... 0x0FF: 1353 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size); 1354 break; 1355 case 0x100 ... 0x1FF: 1356 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size); 1357 break; 1358 case 0x200 ... 0x2FF: 1359 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size); 1360 break; 1361 case 0x300 ... 0x3FF: 1362 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size); 1363 break; 1364 default: 1365 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset); 1366 } 1367 1368 return val; 1369 } 1370 1371 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset, 1372 uint64_t val, unsigned size) 1373 { 1374 PnvXive2 *xive = PNV_XIVE2(opaque); 1375 uint32_t xscom_reg = offset >> 3; 1376 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3; 1377 1378 switch (xscom_reg) { 1379 case 0x000 ... 0x0FF: 1380 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size); 1381 break; 1382 case 0x100 ... 0x1FF: 1383 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size); 1384 break; 1385 case 0x200 ... 0x2FF: 1386 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size); 1387 break; 1388 case 0x300 ... 0x3FF: 1389 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size); 1390 break; 1391 default: 1392 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset); 1393 } 1394 } 1395 1396 static const MemoryRegionOps pnv_xive2_xscom_ops = { 1397 .read = pnv_xive2_xscom_read, 1398 .write = pnv_xive2_xscom_write, 1399 .endianness = DEVICE_BIG_ENDIAN, 1400 .valid = { 1401 .min_access_size = 8, 1402 .max_access_size = 8, 1403 }, 1404 .impl = { 1405 .min_access_size = 8, 1406 .max_access_size = 8, 1407 }, 1408 }; 1409 1410 /* 1411 * Notify port page. The layout is compatible between 4K and 64K pages : 1412 * 1413 * Page 1 Notify page (writes only) 1414 * 0x000 - 0x7FF IPI interrupt (NPU) 1415 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB) 1416 */ 1417 1418 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr, 1419 uint64_t val) 1420 { 1421 uint8_t blk; 1422 uint32_t idx; 1423 1424 if (val & XIVE_TRIGGER_END) { 1425 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, 1426 addr, val); 1427 return; 1428 } 1429 1430 /* 1431 * Forward the source event notification directly to the Router. 1432 * The source interrupt number should already be correctly encoded 1433 * with the chip block id by the sending device (PHB, PSI). 1434 */ 1435 blk = XIVE_EAS_BLOCK(val); 1436 idx = XIVE_EAS_INDEX(val); 1437 1438 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx), 1439 !!(val & XIVE_TRIGGER_PQ)); 1440 } 1441 1442 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset, 1443 uint64_t val, unsigned size) 1444 { 1445 PnvXive2 *xive = PNV_XIVE2(opaque); 1446 1447 /* VC: IPI triggers */ 1448 switch (offset) { 1449 case 0x000 ... 0x7FF: 1450 /* TODO: check IPI notify sub-page routing */ 1451 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1452 break; 1453 1454 /* VC: HW triggers */ 1455 case 0x800 ... 0xFFF: 1456 pnv_xive2_ic_hw_trigger(opaque, offset, val); 1457 break; 1458 1459 default: 1460 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset); 1461 } 1462 } 1463 1464 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset, 1465 unsigned size) 1466 { 1467 PnvXive2 *xive = PNV_XIVE2(opaque); 1468 1469 /* loads are invalid */ 1470 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset); 1471 return -1; 1472 } 1473 1474 static const MemoryRegionOps pnv_xive2_ic_notify_ops = { 1475 .read = pnv_xive2_ic_notify_read, 1476 .write = pnv_xive2_ic_notify_write, 1477 .endianness = DEVICE_BIG_ENDIAN, 1478 .valid = { 1479 .min_access_size = 8, 1480 .max_access_size = 8, 1481 }, 1482 .impl = { 1483 .min_access_size = 8, 1484 .max_access_size = 8, 1485 }, 1486 }; 1487 1488 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset, 1489 unsigned size) 1490 { 1491 PnvXive2 *xive = PNV_XIVE2(opaque); 1492 1493 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset); 1494 return -1; 1495 } 1496 1497 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset, 1498 uint64_t val, unsigned size) 1499 { 1500 PnvXive2 *xive = PNV_XIVE2(opaque); 1501 1502 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset); 1503 } 1504 1505 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = { 1506 .read = pnv_xive2_ic_lsi_read, 1507 .write = pnv_xive2_ic_lsi_write, 1508 .endianness = DEVICE_BIG_ENDIAN, 1509 .valid = { 1510 .min_access_size = 8, 1511 .max_access_size = 8, 1512 }, 1513 .impl = { 1514 .min_access_size = 8, 1515 .max_access_size = 8, 1516 }, 1517 }; 1518 1519 /* 1520 * Sync MMIO page (write only) 1521 */ 1522 #define PNV_XIVE2_SYNC_IPI 0x000 1523 #define PNV_XIVE2_SYNC_HW 0x080 1524 #define PNV_XIVE2_SYNC_NxC 0x100 1525 #define PNV_XIVE2_SYNC_INT 0x180 1526 #define PNV_XIVE2_SYNC_OS_ESC 0x200 1527 #define PNV_XIVE2_SYNC_POOL_ESC 0x280 1528 #define PNV_XIVE2_SYNC_HARD_ESC 0x300 1529 1530 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset, 1531 unsigned size) 1532 { 1533 PnvXive2 *xive = PNV_XIVE2(opaque); 1534 1535 /* loads are invalid */ 1536 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset); 1537 return -1; 1538 } 1539 1540 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset, 1541 uint64_t val, unsigned size) 1542 { 1543 PnvXive2 *xive = PNV_XIVE2(opaque); 1544 1545 switch (offset) { 1546 case PNV_XIVE2_SYNC_IPI: 1547 case PNV_XIVE2_SYNC_HW: 1548 case PNV_XIVE2_SYNC_NxC: 1549 case PNV_XIVE2_SYNC_INT: 1550 case PNV_XIVE2_SYNC_OS_ESC: 1551 case PNV_XIVE2_SYNC_POOL_ESC: 1552 case PNV_XIVE2_SYNC_HARD_ESC: 1553 break; 1554 default: 1555 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset); 1556 } 1557 } 1558 1559 static const MemoryRegionOps pnv_xive2_ic_sync_ops = { 1560 .read = pnv_xive2_ic_sync_read, 1561 .write = pnv_xive2_ic_sync_write, 1562 .endianness = DEVICE_BIG_ENDIAN, 1563 .valid = { 1564 .min_access_size = 8, 1565 .max_access_size = 8, 1566 }, 1567 .impl = { 1568 .min_access_size = 8, 1569 .max_access_size = 8, 1570 }, 1571 }; 1572 1573 /* 1574 * When the TM direct pages of the IC controller are accessed, the 1575 * target HW thread is deduced from the page offset. 1576 */ 1577 static uint32_t pnv_xive2_ic_tm_get_pir(PnvXive2 *xive, hwaddr offset) 1578 { 1579 /* On P10, the node ID shift in the PIR register is 8 bits */ 1580 return xive->chip->chip_id << 8 | offset >> xive->ic_shift; 1581 } 1582 1583 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) 1584 { 1585 PnvChip *chip = xive->chip; 1586 PowerPCCPU *cpu = NULL; 1587 1588 cpu = pnv_chip_find_cpu(chip, pir); 1589 if (!cpu) { 1590 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir); 1591 return NULL; 1592 } 1593 1594 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) { 1595 xive2_error(xive, "IC: CPU %x is not enabled", pir); 1596 } 1597 1598 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1599 } 1600 1601 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset, 1602 unsigned size) 1603 { 1604 PnvXive2 *xive = PNV_XIVE2(opaque); 1605 uint32_t pir; 1606 XiveTCTX *tctx; 1607 uint64_t val = -1; 1608 1609 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 1610 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1611 if (tctx) { 1612 val = xive_tctx_tm_read(NULL, tctx, offset, size); 1613 } 1614 1615 return val; 1616 } 1617 1618 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset, 1619 uint64_t val, unsigned size) 1620 { 1621 PnvXive2 *xive = PNV_XIVE2(opaque); 1622 uint32_t pir; 1623 XiveTCTX *tctx; 1624 1625 pir = pnv_xive2_ic_tm_get_pir(xive, offset); 1626 tctx = pnv_xive2_get_indirect_tctx(xive, pir); 1627 if (tctx) { 1628 xive_tctx_tm_write(NULL, tctx, offset, val, size); 1629 } 1630 } 1631 1632 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = { 1633 .read = pnv_xive2_ic_tm_indirect_read, 1634 .write = pnv_xive2_ic_tm_indirect_write, 1635 .endianness = DEVICE_BIG_ENDIAN, 1636 .valid = { 1637 .min_access_size = 8, 1638 .max_access_size = 8, 1639 }, 1640 .impl = { 1641 .min_access_size = 8, 1642 .max_access_size = 8, 1643 }, 1644 }; 1645 1646 /* 1647 * TIMA ops 1648 */ 1649 1650 /* 1651 * Special TIMA offsets to handle accesses in a POWER10 way. 1652 * 1653 * Only the CAM line updates done by the hypervisor should be handled 1654 * specifically. 1655 */ 1656 #define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT) 1657 #define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2)) 1658 #define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX) 1659 1660 static void pnv_xive2_tm_write(void *opaque, hwaddr offset, 1661 uint64_t value, unsigned size) 1662 { 1663 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1664 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1665 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1666 XivePresenter *xptr = XIVE_PRESENTER(xive); 1667 bool gen1_tima_os = 1668 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1669 1670 /* TODO: should we switch the TM ops table instead ? */ 1671 if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) { 1672 xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); 1673 return; 1674 } 1675 1676 /* Other TM ops are the same as XIVE1 */ 1677 xive_tctx_tm_write(xptr, tctx, offset, value, size); 1678 } 1679 1680 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) 1681 { 1682 PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 1683 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu); 1684 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); 1685 XivePresenter *xptr = XIVE_PRESENTER(xive); 1686 bool gen1_tima_os = 1687 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; 1688 1689 /* TODO: should we switch the TM ops table instead ? */ 1690 if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) { 1691 return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); 1692 } 1693 1694 /* Other TM ops are the same as XIVE1 */ 1695 return xive_tctx_tm_read(xptr, tctx, offset, size); 1696 } 1697 1698 static const MemoryRegionOps pnv_xive2_tm_ops = { 1699 .read = pnv_xive2_tm_read, 1700 .write = pnv_xive2_tm_write, 1701 .endianness = DEVICE_BIG_ENDIAN, 1702 .valid = { 1703 .min_access_size = 1, 1704 .max_access_size = 8, 1705 }, 1706 .impl = { 1707 .min_access_size = 1, 1708 .max_access_size = 8, 1709 }, 1710 }; 1711 1712 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset, 1713 unsigned size) 1714 { 1715 PnvXive2 *xive = PNV_XIVE2(opaque); 1716 1717 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset); 1718 return -1; 1719 } 1720 1721 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset, 1722 uint64_t val, unsigned size) 1723 { 1724 PnvXive2 *xive = PNV_XIVE2(opaque); 1725 1726 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset); 1727 } 1728 1729 static const MemoryRegionOps pnv_xive2_nvc_ops = { 1730 .read = pnv_xive2_nvc_read, 1731 .write = pnv_xive2_nvc_write, 1732 .endianness = DEVICE_BIG_ENDIAN, 1733 .valid = { 1734 .min_access_size = 8, 1735 .max_access_size = 8, 1736 }, 1737 .impl = { 1738 .min_access_size = 8, 1739 .max_access_size = 8, 1740 }, 1741 }; 1742 1743 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset, 1744 unsigned size) 1745 { 1746 PnvXive2 *xive = PNV_XIVE2(opaque); 1747 1748 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset); 1749 return -1; 1750 } 1751 1752 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset, 1753 uint64_t val, unsigned size) 1754 { 1755 PnvXive2 *xive = PNV_XIVE2(opaque); 1756 1757 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset); 1758 } 1759 1760 static const MemoryRegionOps pnv_xive2_nvpg_ops = { 1761 .read = pnv_xive2_nvpg_read, 1762 .write = pnv_xive2_nvpg_write, 1763 .endianness = DEVICE_BIG_ENDIAN, 1764 .valid = { 1765 .min_access_size = 8, 1766 .max_access_size = 8, 1767 }, 1768 .impl = { 1769 .min_access_size = 8, 1770 .max_access_size = 8, 1771 }, 1772 }; 1773 1774 /* 1775 * POWER10 default capabilities: 0x2000120076f000FC 1776 */ 1777 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC 1778 1779 /* 1780 * POWER10 default configuration: 0x0030000033000000 1781 * 1782 * 8bits thread id was dropped for P10 1783 */ 1784 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000 1785 1786 static void pnv_xive2_reset(void *dev) 1787 { 1788 PnvXive2 *xive = PNV_XIVE2(dev); 1789 XiveSource *xsrc = &xive->ipi_source; 1790 Xive2EndSource *end_xsrc = &xive->end_source; 1791 1792 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; 1793 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; 1794 1795 /* HW hardwires the #Topology of the chip in the block field */ 1796 xive->cq_regs[CQ_XIVE_CFG >> 3] |= 1797 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); 1798 1799 /* Set default page size to 64k */ 1800 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; 1801 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; 1802 1803 /* Clear source MMIOs */ 1804 if (memory_region_is_mapped(&xsrc->esb_mmio)) { 1805 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); 1806 } 1807 1808 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { 1809 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); 1810 } 1811 } 1812 1813 /* 1814 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by 1815 * software. 1816 */ 1817 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1818 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE)) 1819 1820 static void pnv_xive2_realize(DeviceState *dev, Error **errp) 1821 { 1822 PnvXive2 *xive = PNV_XIVE2(dev); 1823 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev); 1824 XiveSource *xsrc = &xive->ipi_source; 1825 Xive2EndSource *end_xsrc = &xive->end_source; 1826 Error *local_err = NULL; 1827 int i; 1828 1829 pxc->parent_realize(dev, &local_err); 1830 if (local_err) { 1831 error_propagate(errp, local_err); 1832 return; 1833 } 1834 1835 assert(xive->chip); 1836 1837 /* 1838 * The XiveSource and Xive2EndSource objects are realized with the 1839 * maximum allowed HW configuration. The ESB MMIO regions will be 1840 * resized dynamically when the controller is configured by the FW 1841 * to limit accesses to resources not provisioned. 1842 */ 1843 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI, 1844 &error_fatal); 1845 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, 1846 &error_fatal); 1847 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive), 1848 &error_fatal); 1849 qdev_realize(DEVICE(xsrc), NULL, &local_err); 1850 if (local_err) { 1851 error_propagate(errp, local_err); 1852 return; 1853 } 1854 1855 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, 1856 &error_fatal); 1857 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive), 1858 &error_abort); 1859 qdev_realize(DEVICE(end_xsrc), NULL, &local_err); 1860 if (local_err) { 1861 error_propagate(errp, local_err); 1862 return; 1863 } 1864 1865 /* XSCOM region, used for initial configuration of the BARs */ 1866 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), 1867 &pnv_xive2_xscom_ops, xive, "xscom-xive", 1868 PNV10_XSCOM_XIVE2_SIZE << 3); 1869 1870 /* Interrupt controller MMIO regions */ 1871 xive->ic_shift = 16; 1872 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", 1873 PNV10_XIVE2_IC_SIZE); 1874 1875 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { 1876 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), 1877 pnv_xive2_ic_regions[i].ops, xive, 1878 pnv_xive2_ic_regions[i].name, 1879 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); 1880 } 1881 1882 /* 1883 * VC MMIO regions. 1884 */ 1885 xive->esb_shift = 16; 1886 xive->end_shift = 16; 1887 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", 1888 PNV10_XIVE2_ESB_SIZE); 1889 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", 1890 PNV10_XIVE2_END_SIZE); 1891 1892 /* Presenter Controller MMIO region (not modeled) */ 1893 xive->nvc_shift = 16; 1894 xive->nvpg_shift = 16; 1895 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), 1896 &pnv_xive2_nvc_ops, xive, 1897 "xive-nvc", PNV10_XIVE2_NVC_SIZE); 1898 1899 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), 1900 &pnv_xive2_nvpg_ops, xive, 1901 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); 1902 1903 /* Thread Interrupt Management Area (Direct) */ 1904 xive->tm_shift = 16; 1905 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, 1906 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); 1907 1908 qemu_register_reset(pnv_xive2_reset, dev); 1909 } 1910 1911 static Property pnv_xive2_properties[] = { 1912 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0), 1913 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0), 1914 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0), 1915 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0), 1916 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0), 1917 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0), 1918 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities, 1919 PNV_XIVE2_CAPABILITIES), 1920 DEFINE_PROP_UINT64("config", PnvXive2, config, 1921 PNV_XIVE2_CONFIGURATION), 1922 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), 1923 DEFINE_PROP_END_OF_LIST(), 1924 }; 1925 1926 static void pnv_xive2_instance_init(Object *obj) 1927 { 1928 PnvXive2 *xive = PNV_XIVE2(obj); 1929 1930 object_initialize_child(obj, "ipi_source", &xive->ipi_source, 1931 TYPE_XIVE_SOURCE); 1932 object_initialize_child(obj, "end_source", &xive->end_source, 1933 TYPE_XIVE2_END_SOURCE); 1934 } 1935 1936 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt, 1937 int xscom_offset) 1938 { 1939 const char compat_p10[] = "ibm,power10-xive-x"; 1940 char *name; 1941 int offset; 1942 uint32_t reg[] = { 1943 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE), 1944 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE) 1945 }; 1946 1947 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE); 1948 offset = fdt_add_subnode(fdt, xscom_offset, name); 1949 _FDT(offset); 1950 g_free(name); 1951 1952 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 1953 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, 1954 sizeof(compat_p10))); 1955 return 0; 1956 } 1957 1958 static void pnv_xive2_class_init(ObjectClass *klass, void *data) 1959 { 1960 DeviceClass *dc = DEVICE_CLASS(klass); 1961 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 1962 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass); 1963 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1964 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); 1965 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass); 1966 1967 xdc->dt_xscom = pnv_xive2_dt_xscom; 1968 1969 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; 1970 device_class_set_parent_realize(dc, pnv_xive2_realize, 1971 &pxc->parent_realize); 1972 device_class_set_props(dc, pnv_xive2_properties); 1973 1974 xrc->get_eas = pnv_xive2_get_eas; 1975 xrc->get_pq = pnv_xive2_get_pq; 1976 xrc->set_pq = pnv_xive2_set_pq; 1977 xrc->get_end = pnv_xive2_get_end; 1978 xrc->write_end = pnv_xive2_write_end; 1979 xrc->get_nvp = pnv_xive2_get_nvp; 1980 xrc->write_nvp = pnv_xive2_write_nvp; 1981 xrc->get_config = pnv_xive2_get_config; 1982 xrc->get_block_id = pnv_xive2_get_block_id; 1983 1984 xnc->notify = pnv_xive2_notify; 1985 1986 xpc->match_nvt = pnv_xive2_match_nvt; 1987 }; 1988 1989 static const TypeInfo pnv_xive2_info = { 1990 .name = TYPE_PNV_XIVE2, 1991 .parent = TYPE_XIVE2_ROUTER, 1992 .instance_init = pnv_xive2_instance_init, 1993 .instance_size = sizeof(PnvXive2), 1994 .class_init = pnv_xive2_class_init, 1995 .class_size = sizeof(PnvXive2Class), 1996 .interfaces = (InterfaceInfo[]) { 1997 { TYPE_PNV_XSCOM_INTERFACE }, 1998 { } 1999 } 2000 }; 2001 2002 static void pnv_xive2_register_types(void) 2003 { 2004 type_register_static(&pnv_xive2_info); 2005 } 2006 2007 type_init(pnv_xive2_register_types) 2008 2009 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, 2010 Monitor *mon) 2011 { 2012 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 2013 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 2014 2015 if (!xive2_nvp_is_valid(nvp)) { 2016 return; 2017 } 2018 2019 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x", 2020 nvp_idx, eq_blk, eq_idx, 2021 xive_get_field32(NVP2_W2_IPB, nvp->w2)); 2022 /* 2023 * When the NVP is HW controlled, more fields are updated 2024 */ 2025 if (xive2_nvp_is_hw(nvp)) { 2026 monitor_printf(mon, " CPPR:%02x", 2027 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 2028 if (xive2_nvp_is_co(nvp)) { 2029 monitor_printf(mon, " CO:%04x", 2030 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 2031 } 2032 } 2033 monitor_printf(mon, "\n"); 2034 } 2035 2036 /* 2037 * If the table is direct, we can compute the number of PQ entries 2038 * provisioned by FW. 2039 */ 2040 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive) 2041 { 2042 uint8_t blk = pnv_xive2_block_id(xive); 2043 uint64_t vsd = xive->vsds[VST_ESB][blk]; 2044 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12); 2045 2046 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE; 2047 } 2048 2049 /* 2050 * Compute the number of entries per indirect subpage. 2051 */ 2052 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type) 2053 { 2054 uint8_t blk = pnv_xive2_block_id(xive); 2055 uint64_t vsd = xive->vsds[type][blk]; 2056 const XiveVstInfo *info = &vst_infos[type]; 2057 uint64_t vsd_addr; 2058 uint32_t page_shift; 2059 2060 /* For direct tables, fake a valid value */ 2061 if (!(VSD_INDIRECT & vsd)) { 2062 return 1; 2063 } 2064 2065 /* Get the page size of the indirect table. */ 2066 vsd_addr = vsd & VSD_ADDRESS_MASK; 2067 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED); 2068 2069 if (!(vsd & VSD_ADDRESS_MASK)) { 2070 #ifdef XIVE2_DEBUG 2071 xive2_error(xive, "VST: invalid %s entry!?", info->name); 2072 #endif 2073 return 0; 2074 } 2075 2076 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12; 2077 2078 if (!pnv_xive2_vst_page_size_allowed(page_shift)) { 2079 xive2_error(xive, "VST: invalid %s page shift %d", info->name, 2080 page_shift); 2081 return 0; 2082 } 2083 2084 return (1ull << page_shift) / info->size; 2085 } 2086 2087 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon) 2088 { 2089 Xive2Router *xrtr = XIVE2_ROUTER(xive); 2090 uint8_t blk = pnv_xive2_block_id(xive); 2091 uint8_t chip_id = xive->chip->chip_id; 2092 uint32_t srcno0 = XIVE_EAS(blk, 0); 2093 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive); 2094 Xive2Eas eas; 2095 Xive2End end; 2096 Xive2Nvp nvp; 2097 int i; 2098 uint64_t xive_nvp_per_subpage; 2099 2100 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0, 2101 srcno0 + nr_esbs - 1); 2102 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon); 2103 2104 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0, 2105 srcno0 + nr_esbs - 1); 2106 for (i = 0; i < nr_esbs; i++) { 2107 if (xive2_router_get_eas(xrtr, blk, i, &eas)) { 2108 break; 2109 } 2110 if (!xive2_eas_is_masked(&eas)) { 2111 xive2_eas_pic_print_info(&eas, i, mon); 2112 } 2113 } 2114 2115 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk); 2116 i = 0; 2117 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2118 xive2_end_eas_pic_print_info(&end, i++, mon); 2119 } 2120 2121 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk); 2122 i = 0; 2123 while (!xive2_router_get_end(xrtr, blk, i, &end)) { 2124 xive2_end_pic_print_info(&end, i++, mon); 2125 } 2126 2127 monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk, 2128 0, XIVE2_NVP_COUNT - 1); 2129 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP); 2130 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) { 2131 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) { 2132 xive2_nvp_pic_print_info(&nvp, i++, mon); 2133 } 2134 } 2135 } 2136