1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Loongson ipi interrupt support 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "hw/intc/loongson_ipi.h" 10 #include "hw/qdev-properties.h" 11 #include "qapi/error.h" 12 #include "target/mips/cpu.h" 13 14 static AddressSpace *get_iocsr_as(CPUState *cpu) 15 { 16 if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) { 17 return &MIPS_CPU(cpu)->env.iocsr.as; 18 } 19 20 return NULL; 21 } 22 23 static const MemoryRegionOps loongson_ipi_core_ops = { 24 .read_with_attrs = loongson_ipi_core_readl, 25 .write_with_attrs = loongson_ipi_core_writel, 26 .impl.min_access_size = 4, 27 .impl.max_access_size = 4, 28 .valid.min_access_size = 4, 29 .valid.max_access_size = 8, 30 .endianness = DEVICE_LITTLE_ENDIAN, 31 }; 32 33 static void loongson_ipi_realize(DeviceState *dev, Error **errp) 34 { 35 LoongsonIPICommonState *sc = LOONGSON_IPI_COMMON(dev); 36 LoongsonIPIState *s = LOONGSON_IPI(dev); 37 LoongsonIPIClass *lic = LOONGSON_IPI_GET_CLASS(dev); 38 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 39 Error *local_err = NULL; 40 int i; 41 42 lic->parent_realize(dev, &local_err); 43 if (local_err) { 44 error_propagate(errp, local_err); 45 return; 46 } 47 48 if (sc->num_cpu == 0) { 49 error_setg(errp, "num-cpu must be at least 1"); 50 return; 51 } 52 53 sc->cpu = g_new0(IPICore, sc->num_cpu); 54 for (i = 0; i < sc->num_cpu; i++) { 55 sc->cpu[i].ipi = sc; 56 qdev_init_gpio_out(dev, &sc->cpu[i].irq, 1); 57 } 58 59 s->ipi_mmio_mem = g_new0(MemoryRegion, sc->num_cpu); 60 for (i = 0; i < sc->num_cpu; i++) { 61 g_autofree char *name = g_strdup_printf("loongson_ipi_cpu%d_mmio", i); 62 63 memory_region_init_io(&s->ipi_mmio_mem[i], OBJECT(dev), 64 &loongson_ipi_core_ops, &sc->cpu[i], name, 0x48); 65 sysbus_init_mmio(sbd, &s->ipi_mmio_mem[i]); 66 } 67 } 68 69 static void loongson_ipi_unrealize(DeviceState *dev) 70 { 71 LoongsonIPIState *s = LOONGSON_IPI(dev); 72 LoongsonIPIClass *k = LOONGSON_IPI_GET_CLASS(dev); 73 74 g_free(s->ipi_mmio_mem); 75 76 k->parent_unrealize(dev); 77 } 78 79 static const Property loongson_ipi_properties[] = { 80 DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), 81 }; 82 83 static void loongson_ipi_class_init(ObjectClass *klass, void *data) 84 { 85 DeviceClass *dc = DEVICE_CLASS(klass); 86 LoongsonIPIClass *lic = LOONGSON_IPI_CLASS(klass); 87 LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); 88 89 device_class_set_parent_realize(dc, loongson_ipi_realize, 90 &lic->parent_realize); 91 device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, 92 &lic->parent_unrealize); 93 device_class_set_props(dc, loongson_ipi_properties); 94 licc->get_iocsr_as = get_iocsr_as; 95 licc->cpu_by_arch_id = cpu_by_arch_id; 96 } 97 98 static const TypeInfo loongson_ipi_types[] = { 99 { 100 .name = TYPE_LOONGSON_IPI, 101 .parent = TYPE_LOONGSON_IPI_COMMON, 102 .instance_size = sizeof(LoongsonIPIState), 103 .class_size = sizeof(LoongsonIPIClass), 104 .class_init = loongson_ipi_class_init, 105 } 106 }; 107 108 DEFINE_TYPES(loongson_ipi_types) 109