1 /* 2 * DesignWare I3C Controller 3 * 4 * Copyright (C) 2021 ASPEED Technology Inc. 5 * Copyright (C) 2025 Google, LLC 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/error-report.h" 13 #include "hw/i3c/i3c.h" 14 #include "hw/i3c/dw-i3c.h" 15 #include "hw/registerfields.h" 16 #include "hw/qdev-properties.h" 17 #include "qapi/error.h" 18 #include "migration/vmstate.h" 19 #include "trace.h" 20 #include "hw/irq.h" 21 22 REG32(DEVICE_CTRL, 0x00) 23 FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) 24 FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) 25 FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1) 26 FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2) 27 FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1) 28 FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1) 29 FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1) 30 FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1) 31 FIELD(DEVICE_CTRL, I3C_EN, 31, 1) 32 REG32(DEVICE_ADDR, 0x04) 33 FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7) 34 FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1) 35 FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7) 36 FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 15, 1) 37 REG32(HW_CAPABILITY, 0x08) 38 FIELD(HW_CAPABILITY, DEVICE_ROLE_CONFIG, 0, 2) 39 FIELD(HW_CAPABILITY, HDR_DDR, 3, 1) 40 FIELD(HW_CAPABILITY, HDR_TS, 4, 1) 41 REG32(COMMAND_QUEUE_PORT, 0x0c) 42 FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3) 43 /* Transfer command structure */ 44 FIELD(COMMAND_QUEUE_PORT, TID, 3, 4) 45 FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8) 46 FIELD(COMMAND_QUEUE_PORT, CP, 15, 1) 47 FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5) 48 FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3) 49 FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1) 50 FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1) 51 FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1) 52 FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1) 53 FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1) 54 /* Transfer argument data structure */ 55 FIELD(COMMAND_QUEUE_PORT, DB, 8, 8) 56 FIELD(COMMAND_QUEUE_PORT, DL, 16, 16) 57 /* Short data argument data structure */ 58 FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3) 59 FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8) 60 FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8) 61 FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8) 62 /* Address assignment command structure */ 63 /* 64 * bits 3..21 and 26..31 are the same as the transfer command structure, or 65 * marked as reserved. 66 */ 67 FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3) 68 REG32(RESPONSE_QUEUE_PORT, 0x10) 69 FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16) 70 FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8) 71 FIELD(RESPONSE_QUEUE_PORT, TID, 24, 4) 72 FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4) 73 REG32(RX_TX_DATA_PORT, 0x14) 74 REG32(IBI_QUEUE_STATUS, 0x18) 75 FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8) 76 FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8) 77 FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1) 78 FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1) 79 FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1) 80 REG32(IBI_QUEUE_DATA, 0x18) 81 REG32(QUEUE_THLD_CTRL, 0x1c) 82 FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8); 83 FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8); 84 FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 8); 85 FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8); 86 REG32(DATA_BUFFER_THLD_CTRL, 0x20) 87 FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3) 88 FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 10, 3) 89 FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3) 90 FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3) 91 REG32(IBI_QUEUE_CTRL, 0x24) 92 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1) 93 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1) 94 FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1) 95 REG32(IBI_MR_REQ_REJECT, 0x2c) 96 REG32(IBI_SIR_REQ_REJECT, 0x30) 97 REG32(RESET_CTRL, 0x34) 98 FIELD(RESET_CTRL, CORE_RESET, 0, 1) 99 FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1) 100 FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1) 101 FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1) 102 FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1) 103 FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1) 104 REG32(SLV_EVENT_CTRL, 0x38) 105 FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1) 106 FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1) 107 FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1) 108 FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2) 109 FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1) 110 FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1) 111 REG32(INTR_STATUS, 0x3c) 112 FIELD(INTR_STATUS, TX_THLD, 0, 1) 113 FIELD(INTR_STATUS, RX_THLD, 1, 1) 114 FIELD(INTR_STATUS, IBI_THLD, 2, 1) 115 FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1) 116 FIELD(INTR_STATUS, RESP_RDY, 4, 1) 117 FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1) 118 FIELD(INTR_STATUS, CCC_UPDATED, 6, 1) 119 FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1) 120 FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1) 121 FIELD(INTR_STATUS, DEFSLV, 10, 1) 122 FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1) 123 FIELD(INTR_STATUS, IBI_UPDATED, 12, 1) 124 FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1) 125 REG32(INTR_STATUS_EN, 0x40) 126 FIELD(INTR_STATUS_EN, TX_THLD, 0, 1) 127 FIELD(INTR_STATUS_EN, RX_THLD, 1, 1) 128 FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1) 129 FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1) 130 FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1) 131 FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1) 132 FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1) 133 FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1) 134 FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1) 135 FIELD(INTR_STATUS_EN, DEFSLV, 10, 1) 136 FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1) 137 FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1) 138 FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1) 139 REG32(INTR_SIGNAL_EN, 0x44) 140 FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1) 141 FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1) 142 FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1) 143 FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1) 144 FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1) 145 FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1) 146 FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1) 147 FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1) 148 FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1) 149 FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1) 150 FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1) 151 FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1) 152 FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1) 153 REG32(INTR_FORCE, 0x48) 154 FIELD(INTR_FORCE, TX_THLD, 0, 1) 155 FIELD(INTR_FORCE, RX_THLD, 1, 1) 156 FIELD(INTR_FORCE, IBI_THLD, 2, 1) 157 FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1) 158 FIELD(INTR_FORCE, RESP_RDY, 4, 1) 159 FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1) 160 FIELD(INTR_FORCE, CCC_UPDATED, 6, 1) 161 FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1) 162 FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1) 163 FIELD(INTR_FORCE, DEFSLV, 10, 1) 164 FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1) 165 FIELD(INTR_FORCE, IBI_UPDATED, 12, 1) 166 FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1) 167 REG32(QUEUE_STATUS_LEVEL, 0x4c) 168 FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8) 169 FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8) 170 FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8) 171 FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5) 172 REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) 173 FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8) 174 FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8) 175 REG32(PRESENT_STATE, 0x54) 176 FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1) 177 FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1) 178 FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1) 179 FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6) 180 FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6) 181 FIELD(PRESENT_STATE, CMD_TID, 24, 4) 182 REG32(CCC_DEVICE_STATUS, 0x58) 183 FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4) 184 FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 4, 2) 185 FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2) 186 FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1) 187 FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1) 188 FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1) 189 FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1) 190 FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1) 191 REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) 192 FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) 193 FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) 194 REG32(DEV_CHAR_TABLE_POINTER, 0x60) 195 FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12) 196 FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7) 197 FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3) 198 REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) 199 FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16) 200 REG32(SLV_MIPI_PID_VALUE, 0x70) 201 REG32(SLV_PID_VALUE, 0x74) 202 FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12) 203 FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4) 204 FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16) 205 REG32(SLV_CHAR_CTRL, 0x78) 206 FIELD(SLV_CHAR_CTRL, BCR, 0, 8) 207 FIELD(SLV_CHAR_CTRL, DCR, 8, 8) 208 FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8) 209 REG32(SLV_MAX_LEN, 0x7c) 210 FIELD(SLV_MAX_LEN, MWL, 0, 16) 211 FIELD(SLV_MAX_LEN, MRL, 16, 16) 212 REG32(MAX_READ_TURNAROUND, 0x80) 213 REG32(MAX_DATA_SPEED, 0x84) 214 REG32(SLV_DEBUG_STATUS, 0x88) 215 REG32(SLV_INTR_REQ, 0x8c) 216 FIELD(SLV_INTR_REQ, SIR, 0, 1) 217 FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2) 218 FIELD(SLV_INTR_REQ, MIR, 3, 1) 219 FIELD(SLV_INTR_REQ, TS, 4, 1) 220 FIELD(SLV_INTR_REQ, IBI_STS, 8, 2) 221 FIELD(SLV_INTR_REQ, MDB, 8, 8) 222 FIELD(SLV_INTR_REQ, SIR_DATA_LEN, 16, 8) 223 REG32(SLV_TSX_SYMBL_TIMING, 0x90) 224 FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6) 225 REG32(SLV_SIR_DATA, 0x94) 226 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE0, 0, 8) 227 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE1, 8, 8) 228 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE2, 16, 8) 229 FIELD(SLV_SIR_DATA, SIR_DATA_BYTE3, 24, 8) 230 REG32(SLV_IBI_RESP, 0x98) 231 FIELD(SLV_IBI_RESP, IBI_STS, 0, 2) 232 FIELD(SLV_IBI_RESP, SIR_RESP_DATA_LEN, 8, 16) 233 REG32(DEVICE_CTRL_EXTENDED, 0xb0) 234 FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2) 235 FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1) 236 REG32(SCL_I3C_OD_TIMING, 0xb4) 237 FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8) 238 FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8) 239 REG32(SCL_I3C_PP_TIMING, 0xb8) 240 FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8) 241 FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8) 242 REG32(SCL_I2C_FM_TIMING, 0xbc) 243 REG32(SCL_I2C_FMP_TIMING, 0xc0) 244 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16) 245 FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8) 246 REG32(SCL_EXT_LCNT_TIMING, 0xc8) 247 REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) 248 REG32(BUS_FREE_TIMING, 0xd4) 249 REG32(BUS_IDLE_TIMING, 0xd8) 250 FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20) 251 REG32(I3C_VER_ID, 0xe0) 252 REG32(I3C_VER_TYPE, 0xe4) 253 REG32(EXTENDED_CAPABILITY, 0xe8) 254 FIELD(EXTENDED_CAPABILITY, APP_IF_MODE, 0, 2) 255 FIELD(EXTENDED_CAPABILITY, APP_IF_DATA_WIDTH, 2, 2) 256 FIELD(EXTENDED_CAPABILITY, OPERATION_MODE, 4, 2) 257 FIELD(EXTENDED_CAPABILITY, CLK_PERIOD, 8, 6) 258 REG32(SLAVE_CONFIG, 0xec) 259 FIELD(SLAVE_CONFIG, DMA_EN, 0, 1) 260 FIELD(SLAVE_CONFIG, HJ_CAP, 0, 1) 261 FIELD(SLAVE_CONFIG, CLK_PERIOD, 2, 14) 262 /* Device characteristic table fields */ 263 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200) 264 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200) 265 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8) 266 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8) 267 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8) 268 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8) 269 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204) 270 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16) 271 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208) 272 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8) 273 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8) 274 REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c) 275 FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8) 276 /* Dev addr table fields */ 277 REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) 278 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7) 279 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1) 280 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1) 281 FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1) 282 FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1) 283 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8) 284 FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2) 285 FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2) 286 FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) 287 288 static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = { 289 /* Target mode is not supported, don't advertise it for now. */ 290 [R_HW_CAPABILITY] = 0x000e00b9, 291 [R_QUEUE_THLD_CTRL] = 0x01000101, 292 [R_DATA_BUFFER_THLD_CTRL] = 0x01010100, 293 [R_SLV_EVENT_CTRL] = 0x0000000b, 294 [R_QUEUE_STATUS_LEVEL] = 0x00000002, 295 [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010, 296 [R_PRESENT_STATE] = 0x00000003, 297 [R_I3C_VER_ID] = 0x3130302a, 298 [R_I3C_VER_TYPE] = 0x6c633033, 299 [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, 300 [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, 301 [R_SLV_CHAR_CTRL] = 0x00010000, 302 [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, 303 [R_SLV_MAX_LEN] = 0x00ff00ff, 304 [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f, 305 [R_SCL_I3C_OD_TIMING] = 0x000a0010, 306 [R_SCL_I3C_PP_TIMING] = 0x000a000a, 307 [R_SCL_I2C_FM_TIMING] = 0x00100010, 308 [R_SCL_I2C_FMP_TIMING] = 0x00100010, 309 [R_SCL_EXT_LCNT_TIMING] = 0x20202020, 310 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000, 311 [R_BUS_FREE_TIMING] = 0x00200020, 312 [R_BUS_IDLE_TIMING] = 0x00000020, 313 [R_EXTENDED_CAPABILITY] = 0x00000239, 314 [R_SLAVE_CONFIG] = 0x00000023, 315 }; 316 317 static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = { 318 [R_DEVICE_CTRL] = 0x04fffe00, 319 [R_DEVICE_ADDR] = 0x7f807f80, 320 [R_HW_CAPABILITY] = 0xffffffff, 321 [R_IBI_QUEUE_STATUS] = 0xffffffff, 322 [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8, 323 [R_IBI_QUEUE_CTRL] = 0xfffffff0, 324 [R_RESET_CTRL] = 0xffffffc0, 325 [R_SLV_EVENT_CTRL] = 0xffffff3f, 326 [R_INTR_STATUS] = 0xffff809f, 327 [R_INTR_STATUS_EN] = 0xffff8080, 328 [R_INTR_SIGNAL_EN] = 0xffff8080, 329 [R_INTR_FORCE] = 0xffff8000, 330 [R_QUEUE_STATUS_LEVEL] = 0xffffffff, 331 [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff, 332 [R_PRESENT_STATE] = 0xffffffff, 333 [R_CCC_DEVICE_STATUS] = 0xffffffff, 334 [R_I3C_VER_ID] = 0xffffffff, 335 [R_I3C_VER_TYPE] = 0xffffffff, 336 [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff, 337 [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff, 338 [R_SLV_PID_VALUE] = 0xffff0fff, 339 [R_SLV_CHAR_CTRL] = 0xffffffff, 340 [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff, 341 [R_SLV_MAX_LEN] = 0xffffffff, 342 [R_MAX_READ_TURNAROUND] = 0xffffffff, 343 [R_MAX_DATA_SPEED] = 0xffffffff, 344 [R_SLV_INTR_REQ] = 0xfffffff0, 345 [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0, 346 [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8, 347 [R_SCL_I3C_OD_TIMING] = 0xff00ff00, 348 [R_SCL_I3C_PP_TIMING] = 0xff00ff00, 349 [R_SCL_I2C_FMP_TIMING] = 0xff000000, 350 [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0, 351 [R_BUS_IDLE_TIMING] = 0xfff00000, 352 [R_EXTENDED_CAPABILITY] = 0xffffffff, 353 [R_SLAVE_CONFIG] = 0xffffffff, 354 }; 355 356 static inline bool dw_i3c_has_hdr_ts(DWI3C *s) 357 { 358 return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS); 359 } 360 361 static inline bool dw_i3c_has_hdr_ddr(DWI3C *s) 362 { 363 return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_DDR); 364 } 365 366 static inline bool dw_i3c_can_transmit(DWI3C *s) 367 { 368 /* 369 * We can only transmit if we're enabled and the resume bit is cleared. 370 * The resume bit is set on a transaction error, and software must clear it. 371 */ 372 return ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_EN) && 373 !ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_RESUME); 374 } 375 376 static inline uint8_t dw_i3c_fifo_threshold_from_reg(uint8_t regval) 377 { 378 return regval = regval ? (2 << regval) : 1; 379 } 380 381 static void dw_i3c_update_irq(DWI3C *s) 382 { 383 bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); 384 qemu_set_irq(s->irq, level); 385 } 386 387 static void dw_i3c_end_transfer(DWI3C *s, bool is_i2c) 388 { 389 if (is_i2c) { 390 legacy_i2c_end_transfer(s->bus); 391 } else { 392 i3c_end_transfer(s->bus); 393 } 394 } 395 396 static int dw_i3c_send_start(DWI3C *s, uint8_t addr, bool is_recv, bool is_i2c) 397 { 398 int ret; 399 400 if (is_i2c) { 401 ret = legacy_i2c_start_transfer(s->bus, addr, is_recv); 402 } else { 403 ret = i3c_start_transfer(s->bus, addr, is_recv); 404 } 405 if (ret) { 406 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 407 qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed on TX with addr 0x%.2x\n", 408 path, addr); 409 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 410 DW_I3C_TRANSFER_STATE_HALT); 411 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, 412 DW_I3C_TRANSFER_STATUS_HALT); 413 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); 414 ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); 415 } 416 417 return ret; 418 } 419 420 static int dw_i3c_send(DWI3C *s, const uint8_t *data, uint32_t num_to_send, 421 uint32_t *num_sent, bool is_i2c) 422 { 423 int ret; 424 uint32_t i; 425 426 *num_sent = 0; 427 if (is_i2c) { 428 /* Legacy I2C must be byte-by-byte. */ 429 for (i = 0; i < num_to_send; i++) { 430 ret = legacy_i2c_send(s->bus, data[i]); 431 if (ret) { 432 break; 433 } 434 (*num_sent)++; 435 } 436 } else { 437 ret = i3c_send(s->bus, data, num_to_send, num_sent); 438 } 439 if (ret) { 440 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 441 qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed sending byte 0x%.2x\n", 442 path, data[*num_sent]); 443 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 444 DW_I3C_TRANSFER_STATE_HALT); 445 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, 446 DW_I3C_TRANSFER_STATUS_HALT); 447 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); 448 ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); 449 } 450 451 trace_dw_i3c_send(s->cfg.id, *num_sent); 452 453 return ret; 454 } 455 456 static int dw_i3c_send_byte(DWI3C *s, uint8_t byte, bool is_i2c) 457 { 458 /* 459 * Ignored, the caller will know if we sent 0 or 1 bytes depending on if 460 * we were ACKed/NACKed. 461 */ 462 uint32_t num_sent; 463 return dw_i3c_send(s, &byte, 1, &num_sent, is_i2c); 464 } 465 466 static int dw_i3c_recv_data(DWI3C *s, bool is_i2c, uint8_t *data, 467 uint16_t num_to_read, uint32_t *num_read) 468 { 469 int ret; 470 471 if (is_i2c) { 472 for (uint16_t i = 0; i < num_to_read; i++) { 473 data[i] = legacy_i2c_recv(s->bus); 474 } 475 /* I2C devices can neither NACK a read, nor end transfers early. */ 476 *num_read = num_to_read; 477 trace_dw_i3c_recv_data(s->cfg.id, *num_read); 478 return 0; 479 } 480 /* I3C devices can NACK if the controller sends an unsupported CCC. */ 481 ret = i3c_recv(s->bus, data, num_to_read, num_read); 482 if (ret) { 483 qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed receiving byte\n", 484 object_get_canonical_path(OBJECT(s))); 485 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 486 DW_I3C_TRANSFER_STATE_HALT); 487 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, 488 DW_I3C_TRANSFER_STATUS_HALT); 489 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); 490 ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); 491 } 492 493 trace_dw_i3c_recv_data(s->cfg.id, *num_read); 494 495 return ret; 496 } 497 498 static inline bool dw_i3c_target_is_i2c(DWI3C *s, uint16_t offset) 499 { 500 /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ 501 uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, 502 ADDR) / sizeof(uint32_t)) + offset; 503 return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, 504 LEGACY_I2C_DEVICE); 505 } 506 507 static uint8_t dw_i3c_target_addr(DWI3C *s, uint16_t offset) 508 { 509 if (offset > s->cfg.num_addressable_devices) { 510 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 511 qemu_log_mask(LOG_GUEST_ERROR, "%s: Device addr table offset %d out of " 512 "bounds\n", path, offset); 513 /* If we're out of bounds, return an address of 0. */ 514 return 0; 515 } 516 517 /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ 518 uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, 519 ADDR) / sizeof(uint32_t)) + offset; 520 /* I2C devices use a static address. */ 521 if (dw_i3c_target_is_i2c(s, offset)) { 522 return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, 523 DEV_STATIC_ADDR); 524 } 525 return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, 526 DEV_DYNAMIC_ADDR); 527 } 528 529 static uint32_t dw_i3c_intr_status_r(DWI3C *s) 530 { 531 /* Only return the status whose corresponding EN bits are set. */ 532 return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; 533 } 534 535 static void dw_i3c_intr_status_w(DWI3C *s, uint32_t val) 536 { 537 /* INTR_STATUS[13:5] is w1c, other bits are RO. */ 538 val &= 0x3fe0; 539 s->regs[R_INTR_STATUS] &= ~val; 540 541 dw_i3c_update_irq(s); 542 } 543 544 static void dw_i3c_intr_status_en_w(DWI3C *s, uint32_t val) 545 { 546 s->regs[R_INTR_STATUS_EN] = val; 547 dw_i3c_update_irq(s); 548 } 549 550 static void dw_i3c_intr_signal_en_w(DWI3C *s, uint32_t val) 551 { 552 s->regs[R_INTR_SIGNAL_EN] = val; 553 dw_i3c_update_irq(s); 554 } 555 556 static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val) 557 { 558 /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */ 559 s->regs[R_INTR_STATUS] = val; 560 dw_i3c_update_irq(s); 561 } 562 563 static uint32_t dw_i3c_pop_rx(DWI3C *s) 564 { 565 if (fifo32_is_empty(&s->rx_queue)) { 566 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 567 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to read RX FIFO when empty\n", 568 path); 569 return 0; 570 } 571 572 uint32_t val = fifo32_pop(&s->rx_queue); 573 ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 574 fifo32_num_used(&s->rx_queue)); 575 576 /* Threshold is 2^RX_BUF_THLD. */ 577 uint8_t threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, 578 RX_BUF_THLD); 579 threshold = dw_i3c_fifo_threshold_from_reg(threshold); 580 if (fifo32_num_used(&s->rx_queue) < threshold) { 581 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0); 582 dw_i3c_update_irq(s); 583 } 584 585 trace_dw_i3c_pop_rx(s->cfg.id, val); 586 return val; 587 } 588 589 static uint32_t dw_i3c_resp_queue_port_r(DWI3C *s) 590 { 591 if (fifo32_is_empty(&s->resp_queue)) { 592 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 593 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to read response FIFO when " 594 "empty\n", path); 595 return 0; 596 } 597 598 uint32_t val = fifo32_pop(&s->resp_queue); 599 ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 600 fifo32_num_used(&s->resp_queue)); 601 602 /* Threshold is the register value + 1. */ 603 uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, 604 RESP_BUF_THLD) + 1; 605 if (fifo32_num_used(&s->resp_queue) < threshold) { 606 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0); 607 dw_i3c_update_irq(s); 608 } 609 610 return val; 611 } 612 613 static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) 614 { 615 DWI3C *s = DW_I3C(opaque); 616 uint32_t addr = offset >> 2; 617 uint64_t value; 618 619 switch (addr) { 620 /* RAZ */ 621 case R_COMMAND_QUEUE_PORT: 622 case R_RESET_CTRL: 623 case R_INTR_FORCE: 624 value = 0; 625 break; 626 case R_INTR_STATUS: 627 value = dw_i3c_intr_status_r(s); 628 break; 629 case R_RX_TX_DATA_PORT: 630 value = dw_i3c_pop_rx(s); 631 break; 632 case R_RESPONSE_QUEUE_PORT: 633 value = dw_i3c_resp_queue_port_r(s); 634 break; 635 default: 636 value = s->regs[addr]; 637 break; 638 } 639 640 trace_dw_i3c_read(s->cfg.id, offset, value); 641 642 return value; 643 } 644 645 static void dw_i3c_resp_queue_push(DWI3C *s, uint8_t err, uint8_t tid, 646 uint8_t ccc_type, uint16_t data_len) 647 { 648 uint32_t val = 0; 649 val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, ERR_STATUS, err); 650 val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, TID, tid); 651 val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, CCCT, ccc_type); 652 val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, DL, data_len); 653 if (!fifo32_is_full(&s->resp_queue)) { 654 trace_dw_i3c_resp_queue_push(s->cfg.id, val); 655 fifo32_push(&s->resp_queue, val); 656 } 657 658 ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 659 fifo32_num_used(&s->resp_queue)); 660 /* Threshold is the register value + 1. */ 661 uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, 662 RESP_BUF_THLD) + 1; 663 if (fifo32_num_used(&s->resp_queue) >= threshold) { 664 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 1); 665 dw_i3c_update_irq(s); 666 } 667 } 668 669 static void dw_i3c_push_tx(DWI3C *s, uint32_t val) 670 { 671 if (fifo32_is_full(&s->tx_queue)) { 672 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to push to TX FIFO when " 673 "full\n", object_get_canonical_path(OBJECT(s))); 674 return; 675 } 676 677 trace_dw_i3c_push_tx(s->cfg.id, val); 678 fifo32_push(&s->tx_queue, val); 679 ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 680 fifo32_num_free(&s->tx_queue)); 681 682 /* Threshold is 2^TX_BUF_THLD. */ 683 uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, 684 TX_BUF_THLD); 685 empty_threshold = 686 dw_i3c_fifo_threshold_from_reg(empty_threshold); 687 if (fifo32_num_free(&s->tx_queue) < empty_threshold) { 688 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 0); 689 dw_i3c_update_irq(s); 690 } 691 } 692 693 static uint32_t dw_i3c_pop_tx(DWI3C *s) 694 { 695 if (fifo32_is_empty(&s->tx_queue)) { 696 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 697 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to pop from TX FIFO when " 698 "empty\n", path); 699 return 0; 700 } 701 702 uint32_t val = fifo32_pop(&s->tx_queue); 703 trace_dw_i3c_pop_tx(s->cfg.id, val); 704 ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 705 fifo32_num_free(&s->tx_queue)); 706 707 /* Threshold is 2^TX_BUF_THLD. */ 708 uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, 709 TX_BUF_THLD); 710 empty_threshold = 711 dw_i3c_fifo_threshold_from_reg(empty_threshold); 712 if (fifo32_num_free(&s->tx_queue) >= empty_threshold) { 713 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1); 714 dw_i3c_update_irq(s); 715 } 716 return val; 717 } 718 719 static void dw_i3c_push_rx(DWI3C *s, uint32_t val) 720 { 721 if (fifo32_is_full(&s->rx_queue)) { 722 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 723 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to push to RX FIFO when " 724 "full\n", path); 725 return; 726 } 727 trace_dw_i3c_push_rx(s->cfg.id, val); 728 fifo32_push(&s->rx_queue, val); 729 730 ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 731 fifo32_num_used(&s->rx_queue)); 732 /* Threshold is 2^RX_BUF_THLD. */ 733 uint8_t threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, 734 RX_BUF_THLD); 735 threshold = dw_i3c_fifo_threshold_from_reg(threshold); 736 if (fifo32_num_used(&s->rx_queue) >= threshold) { 737 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 1); 738 dw_i3c_update_irq(s); 739 } 740 } 741 742 static void dw_i3c_short_transfer(DWI3C *s, DWI3CTransferCmd cmd, 743 DWI3CShortArg arg) 744 { 745 uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; 746 uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); 747 bool is_i2c = dw_i3c_target_is_i2c(s, cmd.dev_index); 748 uint8_t data[4]; /* Max we can send on a short transfer is 4 bytes. */ 749 uint8_t len = 0; 750 uint32_t bytes_sent; /* Ignored on short transfers. */ 751 752 /* Can't do reads on a short transfer. */ 753 if (cmd.rnw) { 754 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 755 qemu_log_mask(LOG_GUEST_ERROR, "%s: Cannot do a read on a short " 756 "transfer\n", path); 757 return; 758 } 759 760 if (dw_i3c_send_start(s, addr, /*is_recv=*/false, is_i2c)) { 761 err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; 762 goto transfer_done; 763 } 764 765 /* Are we sending a command? */ 766 if (cmd.cp) { 767 data[len] = cmd.cmd; 768 len++; 769 /* 770 * byte0 is the defining byte for a command, and is only sent if a 771 * command is present and if the command has a defining byte present. 772 * (byte_strb & 0x01) is always treated as set by the controller, and is 773 * ignored. 774 */ 775 if (cmd.dbp) { 776 data[len] += arg.byte0; 777 len++; 778 } 779 } 780 781 /* Send the bytes passed in the argument. */ 782 if (arg.byte_strb & 0x02) { 783 data[len] = arg.byte1; 784 len++; 785 } 786 if (arg.byte_strb & 0x04) { 787 data[len] = arg.byte2; 788 len++; 789 } 790 791 if (dw_i3c_send(s, data, len, &bytes_sent, is_i2c)) { 792 err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; 793 } else { 794 /* Only go to an idle state on a successful transfer. */ 795 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 796 DW_I3C_TRANSFER_STATE_IDLE); 797 } 798 799 transfer_done: 800 if (cmd.toc) { 801 dw_i3c_end_transfer(s, is_i2c); 802 } 803 if (cmd.roc) { 804 /* 805 * ccc_type is always 0 in controller mode, data_len is 0 in short 806 * transfers. 807 */ 808 dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, 809 /*data_len=*/0); 810 } 811 } 812 813 /* Returns number of bytes transmitted. */ 814 static uint16_t dw_i3c_tx(DWI3C *s, uint16_t num, bool is_i2c) 815 { 816 uint16_t bytes_sent = 0; 817 union { 818 uint8_t b[sizeof(uint32_t)]; 819 uint32_t val; 820 } val32; 821 822 while (bytes_sent < num) { 823 val32.val = dw_i3c_pop_tx(s); 824 for (uint8_t i = 0; i < sizeof(val32.val); i++) { 825 if (dw_i3c_send_byte(s, val32.b[i], is_i2c)) { 826 return bytes_sent; 827 } 828 bytes_sent++; 829 830 /* We're not sending the full 32-bits, break early. */ 831 if (bytes_sent >= num) { 832 break; 833 } 834 } 835 } 836 837 return bytes_sent; 838 } 839 840 /* Returns number of bytes received. */ 841 static uint16_t dw_i3c_rx(DWI3C *s, uint16_t num, bool is_i2c) 842 { 843 /* 844 * Allocate a temporary buffer to read data from the target. 845 * Zero it and word-align it as well in case we're reading unaligned data. 846 */ 847 g_autofree uint8_t *data = g_new0(uint8_t, num + (4 - (num & 0x03))); 848 uint32_t *data32 = (uint32_t *)data; 849 /* 850 * 32-bits since the I3C API wants a 32-bit number, even though the 851 * controller can only do 16-bit transfers. 852 */ 853 uint32_t num_read = 0; 854 855 /* Can NACK if the target receives an unsupported CCC. */ 856 if (dw_i3c_recv_data(s, is_i2c, data, num, &num_read)) { 857 return 0; 858 } 859 860 for (uint16_t i = 0; i < num_read / 4; i++) { 861 dw_i3c_push_rx(s, *data32); 862 data32++; 863 } 864 /* 865 * If we're pushing data that isn't 32-bit aligned, push what's left. 866 * It's software's responsibility to know what bits are valid in the partial 867 * data. 868 */ 869 if (num_read & 0x03) { 870 dw_i3c_push_rx(s, *data32); 871 } 872 873 return num_read; 874 } 875 876 static int dw_i3c_transfer_ccc(DWI3C *s, DWI3CTransferCmd cmd, 877 DWI3CTransferArg arg) 878 { 879 /* CCC start is always a write. CCCs cannot be done on I2C devices. */ 880 if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, 881 /*is_i2c=*/false)) { 882 return DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; 883 } 884 trace_dw_i3c_transfer_ccc(s->cfg.id, cmd.cmd); 885 if (dw_i3c_send_byte(s, cmd.cmd, /*is_i2c=*/false)) { 886 return DW_I3C_RESP_QUEUE_ERR_I2C_NACK; 887 } 888 889 /* On a direct CCC, we do a restart and then send the target's address. */ 890 if (CCC_IS_DIRECT(cmd.cmd)) { 891 bool is_recv = cmd.rnw; 892 uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); 893 if (dw_i3c_send_start(s, addr, is_recv, /*is_i2c=*/false)) { 894 return DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; 895 } 896 } 897 898 return DW_I3C_RESP_QUEUE_ERR_NONE; 899 } 900 901 static void dw_i3c_transfer(DWI3C *s, DWI3CTransferCmd cmd, 902 DWI3CTransferArg arg) 903 { 904 bool is_recv = cmd.rnw; 905 uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; 906 uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); 907 bool is_i2c = dw_i3c_target_is_i2c(s, cmd.dev_index); 908 uint16_t bytes_transferred = 0; 909 910 if (cmd.cp) { 911 /* We're sending a CCC. */ 912 err = dw_i3c_transfer_ccc(s, cmd, arg); 913 if (err != DW_I3C_RESP_QUEUE_ERR_NONE) { 914 goto transfer_done; 915 } 916 } else { 917 if (ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_BROADCAST_ADDR_INC) && 918 is_i2c == false) { 919 if (dw_i3c_send_start(s, I3C_BROADCAST, 920 /*is_recv=*/false, is_i2c)) { 921 err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; 922 goto transfer_done; 923 } 924 } 925 /* Otherwise we're doing a private transfer. */ 926 if (dw_i3c_send_start(s, addr, is_recv, is_i2c)) { 927 err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; 928 goto transfer_done; 929 } 930 } 931 932 if (is_recv) { 933 bytes_transferred = dw_i3c_rx(s, arg.data_len, is_i2c); 934 } else { 935 bytes_transferred = dw_i3c_tx(s, arg.data_len, is_i2c); 936 } 937 938 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 939 DW_I3C_TRANSFER_STATE_IDLE); 940 941 transfer_done: 942 if (cmd.toc) { 943 dw_i3c_end_transfer(s, is_i2c); 944 } 945 if (cmd.roc) { 946 /* 947 * data_len is the number of bytes that still need to be TX'd, or the 948 * number of bytes RX'd. 949 */ 950 uint16_t data_len = is_recv ? bytes_transferred : arg.data_len - 951 bytes_transferred; 952 /* CCCT is always 0 in controller mode. */ 953 dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, 954 data_len); 955 } 956 957 dw_i3c_update_irq(s); 958 } 959 960 static void dw_i3c_transfer_cmd(DWI3C *s, DWI3CTransferCmd cmd, 961 DWI3CCmdQueueData arg) 962 { 963 uint8_t arg_attr = FIELD_EX32(arg.word, COMMAND_QUEUE_PORT, CMD_ATTR); 964 965 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CMD_TID, cmd.tid); 966 967 /* User is trying to do HDR transfers, see if we can do them. */ 968 if (cmd.speed == 0x06 && !dw_i3c_has_hdr_ddr(s)) { 969 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 970 qemu_log_mask(LOG_GUEST_ERROR, "%s: HDR DDR is not supported\n", path); 971 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 972 DW_I3C_TRANSFER_STATE_HALT); 973 return; 974 } 975 if (cmd.speed == 0x05 && !dw_i3c_has_hdr_ts(s)) { 976 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 977 qemu_log_mask(LOG_GUEST_ERROR, "%s: HDR TS is not supported\n", path); 978 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 979 DW_I3C_TRANSFER_STATE_HALT); 980 return; 981 } 982 983 if (arg_attr == DW_I3C_CMD_ATTR_TRANSFER_ARG) { 984 dw_i3c_transfer(s, cmd, arg.transfer_arg); 985 } else if (arg_attr == DW_I3C_CMD_ATTR_SHORT_DATA_ARG) { 986 dw_i3c_short_transfer(s, cmd, arg.short_arg); 987 } else { 988 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 989 qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown command queue cmd_attr 0x%x" 990 "\n", path, arg_attr); 991 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 992 DW_I3C_TRANSFER_STATE_HALT); 993 } 994 } 995 996 static void dw_i3c_update_char_table(DWI3C *s, uint8_t offset, uint64_t pid, 997 uint8_t bcr, uint8_t dcr, uint8_t addr) 998 { 999 if (offset > s->cfg.num_addressable_devices) { 1000 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1001 qemu_log_mask(LOG_GUEST_ERROR, "%s: Device char table offset %d out of " 1002 "bounds\n", path, offset); 1003 /* If we're out of bounds, do nothing. */ 1004 return; 1005 } 1006 1007 /* 1008 * Each device offset is 128 bits apart in the table, since each device gets 1009 * 4 * 32-bits of entries in the table. 1010 * / sizeof(uint32_t) because we're indexing into our 32-bit reg array. 1011 */ 1012 uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, 1013 P_DEV_CHAR_TABLE_START_ADDR) / 1014 sizeof(uint32_t)) + 1015 (offset * sizeof(uint32_t)); 1016 s->regs[dev_index] = pid & 0xffffffff; 1017 pid >>= 32; 1018 s->regs[dev_index + 1] = FIELD_DP32(s->regs[dev_index + 1], 1019 DEVICE_CHARACTERISTIC_TABLE_LOC2, 1020 MSB_PID, pid); 1021 s->regs[dev_index + 2] = FIELD_DP32(s->regs[dev_index + 2], 1022 DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 1023 dcr); 1024 s->regs[dev_index + 2] = FIELD_DP32(s->regs[dev_index + 2], 1025 DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 1026 bcr); 1027 s->regs[dev_index + 3] = FIELD_DP32(s->regs[dev_index + 3], 1028 DEVICE_CHARACTERISTIC_TABLE_LOC4, 1029 DEV_DYNAMIC_ADDR, addr); 1030 1031 /* Increment PRESENT_DEV_CHAR_TABLE_INDEX. */ 1032 uint8_t idx = ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, 1033 PRESENT_DEV_CHAR_TABLE_INDEX); 1034 /* Increment and rollover. */ 1035 idx++; 1036 if (idx >= ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, 1037 DEV_CHAR_TABLE_DEPTH) / 4) { 1038 idx = 0; 1039 } 1040 ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, 1041 PRESENT_DEV_CHAR_TABLE_INDEX, idx); 1042 } 1043 1044 static void dw_i3c_addr_assign_cmd(DWI3C *s, DWI3CAddrAssignCmd cmd) 1045 { 1046 uint8_t i = 0; 1047 uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; 1048 1049 /* Tell everyone to ENTDAA. If these error, no one is on the bus. */ 1050 if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, 1051 /*is_i2c=*/false)) { 1052 err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; 1053 goto transfer_done; 1054 } 1055 if (dw_i3c_send_byte(s, cmd.cmd, /*is_i2c=*/false)) { 1056 err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; 1057 goto transfer_done; 1058 } 1059 1060 /* Go through each device in the table and assign it an address. */ 1061 for (i = 0; i < cmd.dev_count; i++) { 1062 uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index + i); 1063 union { 1064 uint64_t pid:48; 1065 uint8_t bcr; 1066 uint8_t dcr; 1067 uint32_t w[2]; 1068 uint8_t b[8]; 1069 } target_info; 1070 1071 /* If this fails, there was no one left to ENTDAA. */ 1072 if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, 1073 /*is_i2c=*/false)) { 1074 err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; 1075 break; 1076 } 1077 1078 /* 1079 * In ENTDAA, we read 8 bytes from the target, which will be the 1080 * target's PID, BCR, and DCR. After that, we send it the dynamic 1081 * address. 1082 * Don't bother checking the number of bytes received, it must send 8 1083 * bytes during ENTDAA. 1084 */ 1085 uint32_t num_read; 1086 if (dw_i3c_recv_data(s, /*is_i2c=*/false, target_info.b, 1087 I3C_ENTDAA_SIZE, &num_read)) { 1088 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1089 qemu_log_mask(LOG_GUEST_ERROR, "%s: Target NACKed ENTDAA CCC\n", 1090 path); 1091 err = DW_I3C_RESP_QUEUE_ERR_DAA_NACK; 1092 goto transfer_done; 1093 } 1094 if (dw_i3c_send_byte(s, addr, /*is_i2c=*/false)) { 1095 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1096 qemu_log_mask(LOG_GUEST_ERROR, "%s: Target NACKed addr 0x%.2x " 1097 "during ENTDAA\n", path, addr); 1098 err = DW_I3C_RESP_QUEUE_ERR_DAA_NACK; 1099 break; 1100 } 1101 dw_i3c_update_char_table(s, cmd.dev_index + i, 1102 target_info.pid, target_info.bcr, 1103 target_info.dcr, addr); 1104 1105 /* Push the PID, BCR, and DCR to the RX queue. */ 1106 dw_i3c_push_rx(s, target_info.w[0]); 1107 dw_i3c_push_rx(s, target_info.w[1]); 1108 } 1109 1110 transfer_done: 1111 /* Do we send a STOP? */ 1112 if (cmd.toc) { 1113 dw_i3c_end_transfer(s, /*is_i2c=*/false); 1114 } 1115 /* 1116 * For addr assign commands, the length field is the number of devices 1117 * left to assign. CCCT is always 0 in controller mode. 1118 */ 1119 if (cmd.roc) { 1120 dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, 1121 cmd.dev_count - i); 1122 } 1123 } 1124 1125 static uint32_t dw_i3c_cmd_queue_pop(DWI3C *s) 1126 { 1127 if (fifo32_is_empty(&s->cmd_queue)) { 1128 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1129 qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to dequeue command queue " 1130 "when it was empty\n", path); 1131 return 0; 1132 } 1133 uint32_t val = fifo32_pop(&s->cmd_queue); 1134 1135 uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, 1136 CMD_BUF_EMPTY_THLD); 1137 uint8_t cmd_queue_empty_loc = ARRAY_FIELD_EX32(s->regs, 1138 QUEUE_STATUS_LEVEL, 1139 CMD_QUEUE_EMPTY_LOC); 1140 cmd_queue_empty_loc++; 1141 ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 1142 cmd_queue_empty_loc); 1143 if (cmd_queue_empty_loc >= empty_threshold) { 1144 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1); 1145 dw_i3c_update_irq(s); 1146 } 1147 1148 return val; 1149 } 1150 1151 static void dw_i3c_cmd_queue_execute(DWI3C *s) 1152 { 1153 ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, 1154 DW_I3C_TRANSFER_STATE_IDLE); 1155 if (!dw_i3c_can_transmit(s)) { 1156 return; 1157 } 1158 1159 /* 1160 * We only start executing when a command is passed into the FIFO. 1161 * We expect there to be a multiple of 2 items in the queue. The first item 1162 * should be an argument to a command, and the command should be the second 1163 * item. 1164 */ 1165 if (fifo32_num_used(&s->cmd_queue) & 1) { 1166 return; 1167 } 1168 1169 while (!fifo32_is_empty(&s->cmd_queue)) { 1170 DWI3CCmdQueueData arg; 1171 arg.word = dw_i3c_cmd_queue_pop(s); 1172 DWI3CCmdQueueData cmd; 1173 cmd.word = dw_i3c_cmd_queue_pop(s); 1174 trace_dw_i3c_cmd_queue_execute(s->cfg.id, cmd.word, arg.word); 1175 1176 uint8_t cmd_attr = FIELD_EX32(cmd.word, COMMAND_QUEUE_PORT, CMD_ATTR); 1177 switch (cmd_attr) { 1178 case DW_I3C_CMD_ATTR_TRANSFER_CMD: 1179 dw_i3c_transfer_cmd(s, cmd.transfer_cmd, arg); 1180 break; 1181 case DW_I3C_CMD_ATTR_ADDR_ASSIGN_CMD: 1182 /* Arg is discarded for addr assign commands. */ 1183 dw_i3c_addr_assign_cmd(s, cmd.addr_assign_cmd); 1184 break; 1185 case DW_I3C_CMD_ATTR_TRANSFER_ARG: 1186 case DW_I3C_CMD_ATTR_SHORT_DATA_ARG: 1187 { 1188 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1189 qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received " 1190 "argument packet when it expected a command " 1191 "packet\n", path); 1192 } 1193 break; 1194 default: 1195 /* 1196 * The caller's check before queueing an item should prevent this 1197 * from happening. 1198 */ 1199 g_assert_not_reached(); 1200 break; 1201 } 1202 } 1203 } 1204 1205 static void dw_i3c_cmd_queue_push(DWI3C *s, uint32_t val) 1206 { 1207 if (fifo32_is_full(&s->cmd_queue)) { 1208 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1209 qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received packet when " 1210 "already full\n", path); 1211 return; 1212 } 1213 trace_dw_i3c_cmd_queue_push(s->cfg.id, val); 1214 fifo32_push(&s->cmd_queue, val); 1215 1216 uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, 1217 CMD_BUF_EMPTY_THLD); 1218 uint8_t cmd_queue_empty_loc = ARRAY_FIELD_EX32(s->regs, 1219 QUEUE_STATUS_LEVEL, 1220 CMD_QUEUE_EMPTY_LOC); 1221 if (cmd_queue_empty_loc) { 1222 cmd_queue_empty_loc--; 1223 ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 1224 cmd_queue_empty_loc); 1225 } 1226 if (cmd_queue_empty_loc < empty_threshold) { 1227 ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 0); 1228 dw_i3c_update_irq(s); 1229 } 1230 } 1231 1232 static void dw_i3c_cmd_queue_port_w(DWI3C *s, uint32_t val) 1233 { 1234 uint8_t cmd_attr = FIELD_EX32(val, COMMAND_QUEUE_PORT, CMD_ATTR); 1235 1236 switch (cmd_attr) { 1237 /* If a command is received we can start executing it. */ 1238 case DW_I3C_CMD_ATTR_TRANSFER_CMD: 1239 case DW_I3C_CMD_ATTR_ADDR_ASSIGN_CMD: 1240 dw_i3c_cmd_queue_push(s, val); 1241 dw_i3c_cmd_queue_execute(s); 1242 break; 1243 /* If we get an argument just push it. */ 1244 case DW_I3C_CMD_ATTR_TRANSFER_ARG: 1245 case DW_I3C_CMD_ATTR_SHORT_DATA_ARG: 1246 dw_i3c_cmd_queue_push(s, val); 1247 break; 1248 default: 1249 { 1250 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1251 qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received packet " 1252 "with unknown cmd attr 0x%x\n", path, cmd_attr); 1253 } 1254 break; 1255 } 1256 } 1257 1258 static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, 1259 unsigned size) 1260 { 1261 DWI3C *s = DW_I3C(opaque); 1262 uint32_t addr = offset >> 2; 1263 uint32_t val32 = (uint32_t)value; 1264 1265 trace_dw_i3c_write(s->cfg.id, offset, value); 1266 1267 val32 &= ~dw_i3c_ro[addr]; 1268 switch (addr) { 1269 case R_HW_CAPABILITY: 1270 case R_RESPONSE_QUEUE_PORT: 1271 case R_IBI_QUEUE_DATA: 1272 case R_QUEUE_STATUS_LEVEL: 1273 case R_PRESENT_STATE: 1274 case R_CCC_DEVICE_STATUS: 1275 case R_DEVICE_ADDR_TABLE_POINTER: 1276 case R_VENDOR_SPECIFIC_REG_POINTER: 1277 case R_SLV_CHAR_CTRL: 1278 case R_SLV_MAX_LEN: 1279 case R_MAX_READ_TURNAROUND: 1280 case R_I3C_VER_ID: 1281 case R_I3C_VER_TYPE: 1282 case R_EXTENDED_CAPABILITY: 1283 qemu_log_mask(LOG_GUEST_ERROR, 1284 "%s: write to readonly register[0x%02" HWADDR_PRIx 1285 "] = 0x%08" PRIx64 "\n", 1286 __func__, offset, value); 1287 break; 1288 case R_RX_TX_DATA_PORT: 1289 dw_i3c_push_tx(s, val32); 1290 break; 1291 case R_COMMAND_QUEUE_PORT: 1292 dw_i3c_cmd_queue_port_w(s, val32); 1293 break; 1294 case R_RESET_CTRL: 1295 break; 1296 case R_INTR_STATUS: 1297 dw_i3c_intr_status_w(s, val32); 1298 break; 1299 case R_INTR_STATUS_EN: 1300 dw_i3c_intr_status_en_w(s, val32); 1301 break; 1302 case R_INTR_SIGNAL_EN: 1303 dw_i3c_intr_signal_en_w(s, val32); 1304 break; 1305 case R_INTR_FORCE: 1306 dw_i3c_intr_force_w(s, val32); 1307 break; 1308 default: 1309 s->regs[addr] = val32; 1310 break; 1311 } 1312 } 1313 1314 const VMStateDescription vmstate_dw_i3c = { 1315 .name = TYPE_DW_I3C, 1316 .version_id = 1, 1317 .minimum_version_id = 1, 1318 .fields = (VMStateField[]){ 1319 VMSTATE_UINT32_ARRAY(regs, DWI3C, DW_I3C_NR_REGS), 1320 VMSTATE_END_OF_LIST(), 1321 } 1322 }; 1323 1324 static const MemoryRegionOps dw_i3c_ops = { 1325 .read = dw_i3c_read, 1326 .write = dw_i3c_write, 1327 .endianness = DEVICE_LITTLE_ENDIAN, 1328 }; 1329 1330 static void dw_i3c_reset_enter(Object *obj, ResetType type) 1331 { 1332 DWI3C *s = DW_I3C(obj); 1333 1334 memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); 1335 /* 1336 * The user config for these may differ from our resets array, set them 1337 * manually. 1338 */ 1339 ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR, 1340 s->cfg.dev_addr_table_pointer); 1341 ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH, 1342 s->cfg.dev_addr_table_depth); 1343 ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, 1344 P_DEV_CHAR_TABLE_START_ADDR, 1345 s->cfg.dev_char_table_pointer); 1346 ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 1347 s->cfg.dev_char_table_depth); 1348 } 1349 1350 static void dw_i3c_realize(DeviceState *dev, Error **errp) 1351 { 1352 DWI3C *s = DW_I3C(dev); 1353 g_autofree char *name = g_strdup_printf(TYPE_DW_I3C ".%d", s->cfg.id); 1354 1355 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); 1356 1357 memory_region_init_io(&s->mr, OBJECT(s), &dw_i3c_ops, s, name, 1358 DW_I3C_NR_REGS << 2); 1359 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); 1360 1361 fifo32_create(&s->cmd_queue, s->cfg.cmd_resp_queue_capacity_bytes); 1362 fifo32_create(&s->resp_queue, s->cfg.cmd_resp_queue_capacity_bytes); 1363 fifo32_create(&s->tx_queue, s->cfg.tx_rx_queue_capacity_bytes); 1364 fifo32_create(&s->rx_queue, s->cfg.tx_rx_queue_capacity_bytes); 1365 1366 s->bus = i3c_init_bus(DEVICE(s), name); 1367 } 1368 1369 static const Property dw_i3c_properties[] = { 1370 DEFINE_PROP_UINT8("device-id", DWI3C, cfg.id, 0), 1371 DEFINE_PROP_UINT8("command-response-queue-capacity-bytes", DWI3C, 1372 cfg.cmd_resp_queue_capacity_bytes, 0x10), 1373 DEFINE_PROP_UINT16("tx-rx-queue-capacity-bytes", DWI3C, 1374 cfg.tx_rx_queue_capacity_bytes, 0x40), 1375 DEFINE_PROP_UINT8("num-addressable-devices", DWI3C, 1376 cfg.num_addressable_devices, 8), 1377 DEFINE_PROP_UINT16("dev-addr-table-pointer", DWI3C, 1378 cfg.dev_addr_table_pointer, 0x280), 1379 DEFINE_PROP_UINT16("dev-addr-table-depth", DWI3C, 1380 cfg.dev_addr_table_depth, 0x08), 1381 DEFINE_PROP_UINT16("dev-char-table-pointer", DWI3C, 1382 cfg.dev_char_table_pointer, 0x200), 1383 DEFINE_PROP_UINT16("dev-char-table-depth", DWI3C, 1384 cfg.dev_char_table_depth, 0x20), 1385 }; 1386 1387 static void dw_i3c_class_init(ObjectClass *klass, const void *data) 1388 { 1389 DeviceClass *dc = DEVICE_CLASS(klass); 1390 ResettableClass *rc = RESETTABLE_CLASS(klass); 1391 1392 rc->phases.enter = dw_i3c_reset_enter; 1393 1394 dc->desc = "DesignWare I3C Controller"; 1395 dc->realize = dw_i3c_realize; 1396 dc->vmsd = &vmstate_dw_i3c; 1397 device_class_set_props(dc, dw_i3c_properties); 1398 } 1399 1400 static const TypeInfo dw_i3c_info = { 1401 .name = TYPE_DW_I3C, 1402 .parent = TYPE_SYS_BUS_DEVICE, 1403 .instance_size = sizeof(DWI3C), 1404 .class_init = dw_i3c_class_init, 1405 }; 1406 1407 static void dw_i3c_register_types(void) 1408 { 1409 type_register_static(&dw_i3c_info); 1410 } 1411 1412 type_init(dw_i3c_register_types); 1413