xref: /openbmc/qemu/hw/i2c/arm_sbcon_i2c.c (revision 500a64d8)
1 /*
2  * ARM SBCon two-wire serial bus interface (I2C bitbang)
3  * a.k.a. ARM Versatile I2C controller
4  *
5  * Copyright (c) 2006-2007 CodeSourcery.
6  * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
7  *
8  * This file is derived from hw/realview.c by Paul Brook
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version 2
13  * of the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, see <http://www.gnu.org/licenses/>.
22  *
23  */
24 
25 #include "qemu/osdep.h"
26 #include "hw/i2c/arm_sbcon_i2c.h"
27 #include "hw/registerfields.h"
28 #include "qemu/log.h"
29 #include "qemu/module.h"
30 #include "qom/object.h"
31 
32 
33 REG32(CONTROL_GET, 0)
34 REG32(CONTROL_SET, 0)
35 REG32(CONTROL_CLR, 4)
36 
37 #define SCL BIT(0)
38 #define SDA BIT(1)
39 
arm_sbcon_i2c_read(void * opaque,hwaddr offset,unsigned size)40 static uint64_t arm_sbcon_i2c_read(void *opaque, hwaddr offset,
41                                    unsigned size)
42 {
43     ArmSbconI2CState *s = opaque;
44 
45     switch (offset) {
46     case A_CONTROL_SET:
47         return (s->out & 1) | (s->in << 1);
48     default:
49         qemu_log_mask(LOG_GUEST_ERROR,
50                       "%s: Bad offset 0x%x\n", __func__, (int)offset);
51         return -1;
52     }
53 }
54 
arm_sbcon_i2c_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)55 static void arm_sbcon_i2c_write(void *opaque, hwaddr offset,
56                                 uint64_t value, unsigned size)
57 {
58     ArmSbconI2CState *s = opaque;
59 
60     switch (offset) {
61     case A_CONTROL_SET:
62         s->out |= value & 3;
63         break;
64     case A_CONTROL_CLR:
65         s->out &= ~value;
66         break;
67     default:
68         qemu_log_mask(LOG_GUEST_ERROR,
69                       "%s: Bad offset 0x%x\n", __func__, (int)offset);
70     }
71     bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0);
72     s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
73 }
74 
75 static const MemoryRegionOps arm_sbcon_i2c_ops = {
76     .read = arm_sbcon_i2c_read,
77     .write = arm_sbcon_i2c_write,
78     .endianness = DEVICE_NATIVE_ENDIAN,
79 };
80 
arm_sbcon_i2c_init(Object * obj)81 static void arm_sbcon_i2c_init(Object *obj)
82 {
83     DeviceState *dev = DEVICE(obj);
84     ArmSbconI2CState *s = ARM_SBCON_I2C(obj);
85     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
86     I2CBus *bus;
87 
88     bus = i2c_init_bus(dev, "i2c");
89     bitbang_i2c_init(&s->bitbang, bus);
90     memory_region_init_io(&s->iomem, obj, &arm_sbcon_i2c_ops, s,
91                           "arm_sbcon_i2c", 0x1000);
92     sysbus_init_mmio(sbd, &s->iomem);
93 }
94 
95 static const TypeInfo arm_sbcon_i2c_info = {
96     .name          = TYPE_ARM_SBCON_I2C,
97     .parent        = TYPE_SYS_BUS_DEVICE,
98     .instance_size = sizeof(ArmSbconI2CState),
99     .instance_init = arm_sbcon_i2c_init,
100 };
101 
arm_sbcon_i2c_register_types(void)102 static void arm_sbcon_i2c_register_types(void)
103 {
104     type_register_static(&arm_sbcon_i2c_info);
105 }
106 
107 type_init(arm_sbcon_i2c_register_types)
108