1 /*
2 * HP Diva GSP controller
3 *
4 * The Diva PCI boards are Remote Management cards for PA-RISC machines.
5 * They come with built-in 16550A multi UARTs for serial consoles
6 * and a mailbox-like memory area for hardware auto-reboot functionality.
7 * GSP stands for "Guardian Service Processor". Later products were marketed
8 * "Management Processor" (MP).
9 *
10 * Diva cards are multifunctional cards. The first part, the aux port,
11 * is on physical machines not useable but we still try to mimic it here.
12 *
13 * SPDX-License-Identifier: GPL-2.0-or-later
14 *
15 * Copyright (c) 2025 Helge Deller <deller@gmx.de>
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/units.h"
20 #include "hw/char/serial.h"
21 #include "hw/irq.h"
22 #include "hw/pci/pci_device.h"
23 #include "hw/qdev-properties.h"
24 #include "hw/qdev-properties-system.h"
25 #include "migration/vmstate.h"
26
27 #define PCI_DEVICE_ID_HP_DIVA 0x1048
28 /* various DIVA GSP cards: */
29 #define PCI_DEVICE_ID_HP_DIVA_TOSCA1 0x1049
30 #define PCI_DEVICE_ID_HP_DIVA_TOSCA2 0x104A
31 #define PCI_DEVICE_ID_HP_DIVA_MAESTRO 0x104B
32 #define PCI_DEVICE_ID_HP_REO_IOC 0x10f1
33 #define PCI_DEVICE_ID_HP_DIVA_HALFDOME 0x1223
34 #define PCI_DEVICE_ID_HP_DIVA_KEYSTONE 0x1226
35 #define PCI_DEVICE_ID_HP_DIVA_POWERBAR 0x1227
36 #define PCI_DEVICE_ID_HP_DIVA_EVEREST 0x1282
37 #define PCI_DEVICE_ID_HP_DIVA_AUX 0x1290
38 #define PCI_DEVICE_ID_HP_DIVA_RMP3 0x1301
39 #define PCI_DEVICE_ID_HP_DIVA_HURRICANE 0x132a
40
41
42 #define PCI_SERIAL_MAX_PORTS 4
43
44 typedef struct PCIDivaSerialState {
45 PCIDevice dev;
46 MemoryRegion membar; /* for serial ports */
47 MemoryRegion mailboxbar; /* for hardware mailbox */
48 uint32_t subvendor;
49 uint32_t ports;
50 char *name[PCI_SERIAL_MAX_PORTS];
51 SerialState state[PCI_SERIAL_MAX_PORTS];
52 uint32_t level[PCI_SERIAL_MAX_PORTS];
53 qemu_irq *irqs;
54 uint8_t prog_if;
55 bool disable;
56 } PCIDivaSerialState;
57
diva_pci_exit(PCIDevice * dev)58 static void diva_pci_exit(PCIDevice *dev)
59 {
60 PCIDivaSerialState *pci = DO_UPCAST(PCIDivaSerialState, dev, dev);
61 SerialState *s;
62 int i;
63
64 for (i = 0; i < pci->ports; i++) {
65 s = pci->state + i;
66 qdev_unrealize(DEVICE(s));
67 memory_region_del_subregion(&pci->membar, &s->io);
68 g_free(pci->name[i]);
69 }
70 qemu_free_irqs(pci->irqs, pci->ports);
71 }
72
multi_serial_irq_mux(void * opaque,int n,int level)73 static void multi_serial_irq_mux(void *opaque, int n, int level)
74 {
75 PCIDivaSerialState *pci = opaque;
76 int i, pending = 0;
77
78 pci->level[n] = level;
79 for (i = 0; i < pci->ports; i++) {
80 if (pci->level[i]) {
81 pending = 1;
82 }
83 }
84 pci_set_irq(&pci->dev, pending);
85 }
86
87 struct diva_info {
88 unsigned int nports:4; /* number of serial ports */
89 unsigned int omask:12; /* offset mask: BIT(1) -> offset 8 */
90 };
91
diva_get_diva_info(PCIDeviceClass * pc)92 static struct diva_info diva_get_diva_info(PCIDeviceClass *pc)
93 {
94 switch (pc->subsystem_id) {
95 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
96 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
97 return (struct diva_info) { .nports = 1,
98 .omask = BIT(0) };
99 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
100 return (struct diva_info) { .nports = 2,
101 .omask = BIT(0) | BIT(1) };
102 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
103 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
104 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
105 return (struct diva_info) { .nports = 3,
106 .omask = BIT(0) | BIT(1) | BIT(2) };
107 case PCI_DEVICE_ID_HP_DIVA_EVEREST: /* e.g. in rp3410 */
108 return (struct diva_info) { .nports = 3,
109 .omask = BIT(0) | BIT(2) | BIT(7) };
110 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
111 return (struct diva_info) { .nports = 4,
112 .omask = BIT(0) | BIT(1) | BIT(2) | BIT(7) };
113 }
114 g_assert_not_reached();
115 }
116
117
diva_pci_realize(PCIDevice * dev,Error ** errp)118 static void diva_pci_realize(PCIDevice *dev, Error **errp)
119 {
120 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
121 PCIDivaSerialState *pci = DO_UPCAST(PCIDivaSerialState, dev, dev);
122 SerialState *s;
123 struct diva_info di = diva_get_diva_info(pc);
124 size_t i, offset = 0;
125 size_t portmask = di.omask;
126
127 pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
128 pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
129 memory_region_init(&pci->membar, OBJECT(pci), "serial_ports", 4096);
130 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &pci->membar);
131 pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, di.nports);
132
133 for (i = 0; i < di.nports; i++) {
134 s = pci->state + i;
135 if (!qdev_realize(DEVICE(s), NULL, errp)) {
136 diva_pci_exit(dev);
137 return;
138 }
139 s->irq = pci->irqs[i];
140 pci->name[i] = g_strdup_printf("uart #%zu", i + 1);
141 memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
142 pci->name[i], 8);
143
144 /* calculate offset of given port based on bitmask */
145 while ((portmask & BIT(0)) == 0) {
146 offset += 8;
147 portmask >>= 1;
148 }
149 memory_region_add_subregion(&pci->membar, offset, &s->io);
150 offset += 8;
151 portmask >>= 1;
152 pci->ports++;
153 }
154
155 /* mailbox bar */
156 memory_region_init(&pci->mailboxbar, OBJECT(pci), "mailbox", 128 * KiB);
157 pci_register_bar(&pci->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY |
158 PCI_BASE_ADDRESS_MEM_PREFETCH, &pci->mailboxbar);
159 }
160
161 static const VMStateDescription vmstate_pci_diva = {
162 .name = "pci-diva-serial",
163 .version_id = 1,
164 .minimum_version_id = 1,
165 .fields = (const VMStateField[]) {
166 VMSTATE_PCI_DEVICE(dev, PCIDivaSerialState),
167 VMSTATE_STRUCT_ARRAY(state, PCIDivaSerialState, PCI_SERIAL_MAX_PORTS,
168 0, vmstate_serial, SerialState),
169 VMSTATE_UINT32_ARRAY(level, PCIDivaSerialState, PCI_SERIAL_MAX_PORTS),
170 VMSTATE_BOOL(disable, PCIDivaSerialState),
171 VMSTATE_END_OF_LIST()
172 }
173 };
174
175 static const Property diva_serial_properties[] = {
176 DEFINE_PROP_BOOL("disable", PCIDivaSerialState, disable, false),
177 DEFINE_PROP_CHR("chardev1", PCIDivaSerialState, state[0].chr),
178 DEFINE_PROP_CHR("chardev2", PCIDivaSerialState, state[1].chr),
179 DEFINE_PROP_CHR("chardev3", PCIDivaSerialState, state[2].chr),
180 DEFINE_PROP_CHR("chardev4", PCIDivaSerialState, state[3].chr),
181 DEFINE_PROP_UINT8("prog_if", PCIDivaSerialState, prog_if, 0x02),
182 DEFINE_PROP_UINT32("subvendor", PCIDivaSerialState, subvendor,
183 PCI_DEVICE_ID_HP_DIVA_TOSCA1),
184 };
185
diva_serial_class_initfn(ObjectClass * klass,void * data)186 static void diva_serial_class_initfn(ObjectClass *klass, void *data)
187 {
188 DeviceClass *dc = DEVICE_CLASS(klass);
189 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
190 pc->realize = diva_pci_realize;
191 pc->exit = diva_pci_exit;
192 pc->vendor_id = PCI_VENDOR_ID_HP;
193 pc->device_id = PCI_DEVICE_ID_HP_DIVA;
194 pc->subsystem_vendor_id = PCI_VENDOR_ID_HP;
195 pc->subsystem_id = PCI_DEVICE_ID_HP_DIVA_TOSCA1;
196 pc->revision = 3;
197 pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
198 dc->vmsd = &vmstate_pci_diva;
199 device_class_set_props(dc, diva_serial_properties);
200 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
201 }
202
diva_serial_init(Object * o)203 static void diva_serial_init(Object *o)
204 {
205 PCIDevice *dev = PCI_DEVICE(o);
206 PCIDivaSerialState *pms = DO_UPCAST(PCIDivaSerialState, dev, dev);
207 struct diva_info di = diva_get_diva_info(PCI_DEVICE_GET_CLASS(dev));
208 size_t i;
209
210 for (i = 0; i < di.nports; i++) {
211 object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL);
212 }
213 }
214
215
216 /* Diva-aux is the driver for portion 0 of the multifunction PCI device */
217
218 struct DivaAuxState {
219 PCIDevice dev;
220 MemoryRegion mem;
221 qemu_irq irq;
222 };
223
224 #define TYPE_DIVA_AUX "diva-aux"
OBJECT_DECLARE_SIMPLE_TYPE(DivaAuxState,DIVA_AUX)225 OBJECT_DECLARE_SIMPLE_TYPE(DivaAuxState, DIVA_AUX)
226
227 static void diva_aux_realize(PCIDevice *dev, Error **errp)
228 {
229 DivaAuxState *pci = DO_UPCAST(DivaAuxState, dev, dev);
230
231 pci->dev.config[PCI_CLASS_PROG] = 0x02;
232 pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
233 pci->irq = pci_allocate_irq(&pci->dev);
234
235 memory_region_init(&pci->mem, OBJECT(pci), "mem", 16);
236 pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &pci->mem);
237 }
238
diva_aux_exit(PCIDevice * dev)239 static void diva_aux_exit(PCIDevice *dev)
240 {
241 DivaAuxState *pci = DO_UPCAST(DivaAuxState, dev, dev);
242 qemu_free_irq(pci->irq);
243 }
244
diva_aux_class_initfn(ObjectClass * klass,void * data)245 static void diva_aux_class_initfn(ObjectClass *klass, void *data)
246 {
247 DeviceClass *dc = DEVICE_CLASS(klass);
248 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
249 pc->realize = diva_aux_realize;
250 pc->exit = diva_aux_exit;
251 pc->vendor_id = PCI_VENDOR_ID_HP;
252 pc->device_id = PCI_DEVICE_ID_HP_DIVA_AUX;
253 pc->subsystem_vendor_id = PCI_VENDOR_ID_HP;
254 pc->subsystem_id = 0x1291;
255 pc->revision = 1;
256 pc->class_id = PCI_CLASS_COMMUNICATION_MULTISERIAL;
257 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
258 dc->user_creatable = false;
259 }
260
diva_aux_init(Object * o)261 static void diva_aux_init(Object *o)
262 {
263 }
264
265 static const TypeInfo diva_aux_info = {
266 .name = TYPE_DIVA_AUX,
267 .parent = TYPE_PCI_DEVICE,
268 .instance_size = sizeof(DivaAuxState),
269 .instance_init = diva_aux_init,
270 .class_init = diva_aux_class_initfn,
271 .interfaces = (InterfaceInfo[]) {
272 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
273 { },
274 },
275 };
276
277
278
279 static const TypeInfo diva_serial_pci_info = {
280 .name = "diva-gsp",
281 .parent = TYPE_PCI_DEVICE,
282 .instance_size = sizeof(PCIDivaSerialState),
283 .instance_init = diva_serial_init,
284 .class_init = diva_serial_class_initfn,
285 .interfaces = (InterfaceInfo[]) {
286 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
287 { },
288 },
289 };
290
diva_pci_register_type(void)291 static void diva_pci_register_type(void)
292 {
293 type_register_static(&diva_serial_pci_info);
294 type_register_static(&diva_aux_info);
295 }
296
297 type_init(diva_pci_register_type)
298