1 /* 2 * Xilinx Versal Virtual board. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include "sysemu/device_tree.h" 16 #include "hw/boards.h" 17 #include "hw/sysbus.h" 18 #include "hw/arm/fdt.h" 19 #include "hw/qdev-properties.h" 20 #include "hw/arm/xlnx-versal.h" 21 #include "hw/arm/boot.h" 22 #include "target/arm/multiprocessing.h" 23 #include "qom/object.h" 24 25 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") 26 OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE) 27 28 #define XLNX_VERSAL_NUM_OSPI_FLASH 4 29 30 struct VersalVirt { 31 MachineState parent_obj; 32 33 Versal soc; 34 35 void *fdt; 36 int fdt_size; 37 struct { 38 uint32_t gic; 39 uint32_t ethernet_phy[2]; 40 uint32_t clk_125Mhz; 41 uint32_t clk_25Mhz; 42 uint32_t usb; 43 uint32_t dwc; 44 uint32_t canfd[2]; 45 } phandle; 46 struct arm_boot_info binfo; 47 48 CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; 49 struct { 50 bool secure; 51 } cfg; 52 }; 53 54 static void fdt_create(VersalVirt *s) 55 { 56 MachineClass *mc = MACHINE_GET_CLASS(s); 57 int i; 58 59 s->fdt = create_device_tree(&s->fdt_size); 60 if (!s->fdt) { 61 error_report("create_device_tree() failed"); 62 exit(1); 63 } 64 65 /* Allocate all phandles. */ 66 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); 67 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { 68 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt); 69 } 70 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); 71 s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); 72 73 s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt); 74 s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt); 75 /* Create /chosen node for load_dtb. */ 76 qemu_fdt_add_subnode(s->fdt, "/chosen"); 77 78 /* Header */ 79 qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); 80 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); 81 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); 82 qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc); 83 qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt"); 84 } 85 86 static void fdt_add_clk_node(VersalVirt *s, const char *name, 87 unsigned int freq_hz, uint32_t phandle) 88 { 89 qemu_fdt_add_subnode(s->fdt, name); 90 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 91 qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); 92 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); 93 qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); 94 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 95 } 96 97 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) 98 { 99 int i; 100 101 qemu_fdt_add_subnode(s->fdt, "/cpus"); 102 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); 103 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); 104 105 for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) { 106 char *name = g_strdup_printf("/cpus/cpu@%d", i); 107 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 108 109 qemu_fdt_add_subnode(s->fdt, name); 110 qemu_fdt_setprop_cell(s->fdt, name, "reg", 111 arm_cpu_mp_affinity(armcpu)); 112 if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 113 qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); 114 } 115 qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu"); 116 qemu_fdt_setprop_string(s->fdt, name, "compatible", 117 armcpu->dtb_compatible); 118 g_free(name); 119 } 120 } 121 122 static void fdt_add_gic_nodes(VersalVirt *s) 123 { 124 char *nodename; 125 126 nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); 127 qemu_fdt_add_subnode(s->fdt, nodename); 128 qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); 129 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", 130 GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, 131 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 132 qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); 133 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", 134 2, MM_GIC_APU_DIST_MAIN, 135 2, MM_GIC_APU_DIST_MAIN_SIZE, 136 2, MM_GIC_APU_REDIST_0, 137 2, MM_GIC_APU_REDIST_0_SIZE); 138 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); 139 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); 140 g_free(nodename); 141 } 142 143 static void fdt_add_timer_nodes(VersalVirt *s) 144 { 145 const char compat[] = "arm,armv8-timer"; 146 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 147 148 qemu_fdt_add_subnode(s->fdt, "/timer"); 149 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", 150 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, 151 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, 152 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, 153 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); 154 qemu_fdt_setprop(s->fdt, "/timer", "compatible", 155 compat, sizeof(compat)); 156 } 157 158 static void fdt_add_usb_xhci_nodes(VersalVirt *s) 159 { 160 const char clocknames[] = "bus_clk\0ref_clk"; 161 const char irq_name[] = "dwc_usb3"; 162 const char compatVersalDWC3[] = "xlnx,versal-dwc3"; 163 const char compatDWC3[] = "snps,dwc3"; 164 char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); 165 166 qemu_fdt_add_subnode(s->fdt, name); 167 qemu_fdt_setprop(s->fdt, name, "compatible", 168 compatVersalDWC3, sizeof(compatVersalDWC3)); 169 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 170 2, MM_USB2_CTRL_REGS, 171 2, MM_USB2_CTRL_REGS_SIZE); 172 qemu_fdt_setprop(s->fdt, name, "clock-names", 173 clocknames, sizeof(clocknames)); 174 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 175 s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); 176 qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); 177 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); 178 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); 179 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); 180 g_free(name); 181 182 name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, 183 MM_USB2_CTRL_REGS, MM_USB_0); 184 qemu_fdt_add_subnode(s->fdt, name); 185 qemu_fdt_setprop(s->fdt, name, "compatible", 186 compatDWC3, sizeof(compatDWC3)); 187 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 188 2, MM_USB_0, 2, MM_USB_0_SIZE); 189 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 190 irq_name, sizeof(irq_name)); 191 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 192 GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, 193 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 194 qemu_fdt_setprop_cell(s->fdt, name, 195 "snps,quirk-frame-length-adjustment", 0x20); 196 qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); 197 qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); 198 qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); 199 qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); 200 qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); 201 qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); 202 qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); 203 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); 204 qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); 205 g_free(name); 206 } 207 208 static void fdt_add_uart_nodes(VersalVirt *s) 209 { 210 uint64_t addrs[] = { MM_UART1, MM_UART0 }; 211 unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; 212 const char compat[] = "arm,pl011\0arm,sbsa-uart"; 213 const char clocknames[] = "uartclk\0apb_pclk"; 214 int i; 215 216 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 217 char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]); 218 qemu_fdt_add_subnode(s->fdt, name); 219 qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); 220 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 221 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 222 qemu_fdt_setprop(s->fdt, name, "clock-names", 223 clocknames, sizeof(clocknames)); 224 225 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 226 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 227 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 228 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 229 2, addrs[i], 2, 0x1000); 230 qemu_fdt_setprop(s->fdt, name, "compatible", 231 compat, sizeof(compat)); 232 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 233 234 if (addrs[i] == MM_UART0) { 235 /* Select UART0. */ 236 qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name); 237 } 238 g_free(name); 239 } 240 } 241 242 static void fdt_add_canfd_nodes(VersalVirt *s) 243 { 244 uint64_t addrs[] = { MM_CANFD1, MM_CANFD0 }; 245 uint32_t size[] = { MM_CANFD1_SIZE, MM_CANFD0_SIZE }; 246 unsigned int irqs[] = { VERSAL_CANFD1_IRQ_0, VERSAL_CANFD0_IRQ_0 }; 247 const char clocknames[] = "can_clk\0s_axi_aclk"; 248 int i; 249 250 /* Create and connect CANFD0 and CANFD1 nodes to canbus0. */ 251 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 252 char *name = g_strdup_printf("/canfd@%" PRIx64, addrs[i]); 253 qemu_fdt_add_subnode(s->fdt, name); 254 255 qemu_fdt_setprop_cell(s->fdt, name, "rx-fifo-depth", 0x40); 256 qemu_fdt_setprop_cell(s->fdt, name, "tx-mailbox-count", 0x20); 257 258 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 259 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 260 qemu_fdt_setprop(s->fdt, name, "clock-names", 261 clocknames, sizeof(clocknames)); 262 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 263 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 264 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 265 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 266 2, addrs[i], 2, size[i]); 267 qemu_fdt_setprop_string(s->fdt, name, "compatible", 268 "xlnx,canfd-2.0"); 269 270 g_free(name); 271 } 272 } 273 274 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, 275 uint32_t phandle) 276 { 277 char *name = g_strdup_printf("%s/fixed-link", gemname); 278 279 qemu_fdt_add_subnode(s->fdt, name); 280 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 281 qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); 282 qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); 283 g_free(name); 284 } 285 286 static void fdt_add_gem_nodes(VersalVirt *s) 287 { 288 uint64_t addrs[] = { MM_GEM1, MM_GEM0 }; 289 unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; 290 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; 291 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; 292 int i; 293 294 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 295 char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); 296 qemu_fdt_add_subnode(s->fdt, name); 297 298 fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); 299 qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); 300 qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", 301 s->phandle.ethernet_phy[i]); 302 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 303 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, 304 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 305 qemu_fdt_setprop(s->fdt, name, "clock-names", 306 clocknames, sizeof(clocknames)); 307 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 308 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 309 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 310 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 311 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 312 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 313 2, addrs[i], 2, 0x1000); 314 qemu_fdt_setprop(s->fdt, name, "compatible", 315 compat_gem, sizeof(compat_gem)); 316 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); 317 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); 318 g_free(name); 319 } 320 } 321 322 static void fdt_add_zdma_nodes(VersalVirt *s) 323 { 324 const char clocknames[] = "clk_main\0clk_apb"; 325 const char compat[] = "xlnx,zynqmp-dma-1.0"; 326 int i; 327 328 for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) { 329 uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i; 330 char *name = g_strdup_printf("/dma@%" PRIx64, addr); 331 332 qemu_fdt_add_subnode(s->fdt, name); 333 334 qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64); 335 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 336 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 337 qemu_fdt_setprop(s->fdt, name, "clock-names", 338 clocknames, sizeof(clocknames)); 339 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 340 GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i, 341 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 342 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 343 2, addr, 2, 0x1000); 344 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 345 g_free(name); 346 } 347 } 348 349 static void fdt_add_sd_nodes(VersalVirt *s) 350 { 351 const char clocknames[] = "clk_xin\0clk_ahb"; 352 const char compat[] = "arasan,sdhci-8.9a"; 353 int i; 354 355 for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) { 356 uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i; 357 char *name = g_strdup_printf("/sdhci@%" PRIx64, addr); 358 359 qemu_fdt_add_subnode(s->fdt, name); 360 361 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 362 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 363 qemu_fdt_setprop(s->fdt, name, "clock-names", 364 clocknames, sizeof(clocknames)); 365 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 366 GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2, 367 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 368 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 369 2, addr, 2, MM_PMC_SD0_SIZE); 370 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 371 g_free(name); 372 } 373 } 374 375 static void fdt_add_rtc_node(VersalVirt *s) 376 { 377 const char compat[] = "xlnx,zynqmp-rtc"; 378 const char interrupt_names[] = "alarm\0sec"; 379 char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC); 380 381 qemu_fdt_add_subnode(s->fdt, name); 382 383 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 384 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ, 385 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 386 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ, 387 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 388 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 389 interrupt_names, sizeof(interrupt_names)); 390 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 391 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE); 392 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 393 g_free(name); 394 } 395 396 static void fdt_add_bbram_node(VersalVirt *s) 397 { 398 const char compat[] = TYPE_XLNX_BBRAM; 399 const char interrupt_names[] = "bbram-error"; 400 char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL); 401 402 qemu_fdt_add_subnode(s->fdt, name); 403 404 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 405 GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ, 406 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 407 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 408 interrupt_names, sizeof(interrupt_names)); 409 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 410 2, MM_PMC_BBRAM_CTRL, 411 2, MM_PMC_BBRAM_CTRL_SIZE); 412 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 413 g_free(name); 414 } 415 416 static void fdt_add_efuse_ctrl_node(VersalVirt *s) 417 { 418 const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL; 419 const char interrupt_names[] = "pmc_efuse"; 420 char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL); 421 422 qemu_fdt_add_subnode(s->fdt, name); 423 424 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 425 GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ, 426 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 427 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 428 interrupt_names, sizeof(interrupt_names)); 429 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 430 2, MM_PMC_EFUSE_CTRL, 431 2, MM_PMC_EFUSE_CTRL_SIZE); 432 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 433 g_free(name); 434 } 435 436 static void fdt_add_efuse_cache_node(VersalVirt *s) 437 { 438 const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE; 439 char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x", 440 MM_PMC_EFUSE_CACHE); 441 442 qemu_fdt_add_subnode(s->fdt, name); 443 444 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 445 2, MM_PMC_EFUSE_CACHE, 446 2, MM_PMC_EFUSE_CACHE_SIZE); 447 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 448 g_free(name); 449 } 450 451 static void fdt_nop_memory_nodes(void *fdt, Error **errp) 452 { 453 Error *err = NULL; 454 char **node_path; 455 int n = 0; 456 457 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 458 if (err) { 459 error_propagate(errp, err); 460 return; 461 } 462 while (node_path[n]) { 463 if (g_str_has_prefix(node_path[n], "/memory")) { 464 qemu_fdt_nop_node(fdt, node_path[n]); 465 } 466 n++; 467 } 468 g_strfreev(node_path); 469 } 470 471 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size) 472 { 473 /* Describes the various split DDR access regions. */ 474 static const struct { 475 uint64_t base; 476 uint64_t size; 477 } addr_ranges[] = { 478 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 479 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 480 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 481 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 482 }; 483 uint64_t mem_reg_prop[8] = {0}; 484 uint64_t size = ram_size; 485 Error *err = NULL; 486 char *name; 487 int i; 488 489 fdt_nop_memory_nodes(fdt, &err); 490 if (err) { 491 error_report_err(err); 492 return; 493 } 494 495 name = g_strdup_printf("/memory@%x", MM_TOP_DDR); 496 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 497 uint64_t mapsize; 498 499 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 500 501 mem_reg_prop[i * 2] = addr_ranges[i].base; 502 mem_reg_prop[i * 2 + 1] = mapsize; 503 size -= mapsize; 504 } 505 qemu_fdt_add_subnode(fdt, name); 506 qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); 507 508 switch (i) { 509 case 1: 510 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 511 2, mem_reg_prop[0], 512 2, mem_reg_prop[1]); 513 break; 514 case 2: 515 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 516 2, mem_reg_prop[0], 517 2, mem_reg_prop[1], 518 2, mem_reg_prop[2], 519 2, mem_reg_prop[3]); 520 break; 521 case 3: 522 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 523 2, mem_reg_prop[0], 524 2, mem_reg_prop[1], 525 2, mem_reg_prop[2], 526 2, mem_reg_prop[3], 527 2, mem_reg_prop[4], 528 2, mem_reg_prop[5]); 529 break; 530 case 4: 531 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 532 2, mem_reg_prop[0], 533 2, mem_reg_prop[1], 534 2, mem_reg_prop[2], 535 2, mem_reg_prop[3], 536 2, mem_reg_prop[4], 537 2, mem_reg_prop[5], 538 2, mem_reg_prop[6], 539 2, mem_reg_prop[7]); 540 break; 541 default: 542 g_assert_not_reached(); 543 } 544 g_free(name); 545 } 546 547 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, 548 void *fdt) 549 { 550 VersalVirt *s = container_of(binfo, VersalVirt, binfo); 551 552 fdt_add_memory_nodes(s, fdt, binfo->ram_size); 553 } 554 555 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, 556 int *fdt_size) 557 { 558 const VersalVirt *board = container_of(binfo, VersalVirt, binfo); 559 560 *fdt_size = board->fdt_size; 561 return board->fdt; 562 } 563 564 #define NUM_VIRTIO_TRANSPORT 8 565 static void create_virtio_regions(VersalVirt *s) 566 { 567 int virtio_mmio_size = 0x200; 568 int i; 569 570 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 571 char *name = g_strdup_printf("virtio%d", i); 572 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 573 int irq = VERSAL_RSVD_IRQ_FIRST + i; 574 MemoryRegion *mr; 575 DeviceState *dev; 576 qemu_irq pic_irq; 577 578 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 579 dev = qdev_new("virtio-mmio"); 580 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 581 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 582 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 583 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 584 memory_region_add_subregion(&s->soc.mr_ps, base, mr); 585 g_free(name); 586 } 587 588 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 589 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 590 int irq = VERSAL_RSVD_IRQ_FIRST + i; 591 char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 592 593 qemu_fdt_add_subnode(s->fdt, name); 594 qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); 595 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 596 GIC_FDT_IRQ_TYPE_SPI, irq, 597 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 598 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 599 2, base, 2, virtio_mmio_size); 600 qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); 601 g_free(name); 602 } 603 } 604 605 static void bbram_attach_drive(XlnxBBRam *dev) 606 { 607 DriveInfo *dinfo; 608 BlockBackend *blk; 609 610 dinfo = drive_get_by_index(IF_PFLASH, 0); 611 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 612 if (blk) { 613 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 614 } 615 } 616 617 static void efuse_attach_drive(XlnxEFuse *dev) 618 { 619 DriveInfo *dinfo; 620 BlockBackend *blk; 621 622 dinfo = drive_get_by_index(IF_PFLASH, 1); 623 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 624 if (blk) { 625 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 626 } 627 } 628 629 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) 630 { 631 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 632 DeviceState *card; 633 634 card = qdev_new(TYPE_SD_CARD); 635 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card)); 636 qdev_prop_set_drive_err(card, "drive", blk, &error_fatal); 637 qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"), 638 &error_fatal); 639 } 640 641 static void versal_virt_init(MachineState *machine) 642 { 643 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine); 644 int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 645 int i; 646 647 /* 648 * If the user provides an Operating System to be loaded, we expect them 649 * to use the -kernel command line option. 650 * 651 * Users can load firmware or boot-loaders with the -device loader options. 652 * 653 * When loading an OS, we generate a dtb and let arm_load_kernel() select 654 * where it gets loaded. This dtb will be passed to the kernel in x0. 655 * 656 * If there's no -kernel option, we generate a DTB and place it at 0x1000 657 * for the bootloaders or firmware to pick up. 658 * 659 * If users want to provide their own DTB, they can use the -dtb option. 660 * These dtb's will have their memory nodes modified to match QEMU's 661 * selected ram_size option before they get passed to the kernel or fw. 662 * 663 * When loading an OS, we turn on QEMU's PSCI implementation with SMC 664 * as the PSCI conduit. When there's no -kernel, we assume the user 665 * provides EL3 firmware to handle PSCI. 666 * 667 * Even if the user provides a kernel filename, arm_load_kernel() 668 * may suppress PSCI if it's going to boot that guest code at EL3. 669 */ 670 if (machine->kernel_filename) { 671 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 672 } 673 674 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 675 TYPE_XLNX_VERSAL); 676 object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), 677 &error_abort); 678 object_property_set_link(OBJECT(&s->soc), "canbus0", OBJECT(s->canbus[0]), 679 &error_abort); 680 object_property_set_link(OBJECT(&s->soc), "canbus1", OBJECT(s->canbus[1]), 681 &error_abort); 682 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 683 684 fdt_create(s); 685 create_virtio_regions(s); 686 fdt_add_gem_nodes(s); 687 fdt_add_uart_nodes(s); 688 fdt_add_canfd_nodes(s); 689 fdt_add_gic_nodes(s); 690 fdt_add_timer_nodes(s); 691 fdt_add_zdma_nodes(s); 692 fdt_add_usb_xhci_nodes(s); 693 fdt_add_sd_nodes(s); 694 fdt_add_rtc_node(s); 695 fdt_add_bbram_node(s); 696 fdt_add_efuse_ctrl_node(s); 697 fdt_add_efuse_cache_node(s); 698 fdt_add_cpu_nodes(s, psci_conduit); 699 fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); 700 fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); 701 702 /* Make the APU cpu address space visible to virtio and other 703 * modules unaware of multiple address-spaces. */ 704 memory_region_add_subregion_overlap(get_system_memory(), 705 0, &s->soc.fpd.apu.mr, 0); 706 707 /* Attach bbram backend, if given */ 708 bbram_attach_drive(&s->soc.pmc.bbram); 709 710 /* Attach efuse backend, if given */ 711 efuse_attach_drive(&s->soc.pmc.efuse); 712 713 /* Plugin SD cards. */ 714 for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { 715 sd_plugin_card(&s->soc.pmc.iou.sd[i], 716 drive_get(IF_SD, 0, i)); 717 } 718 719 s->binfo.ram_size = machine->ram_size; 720 s->binfo.loader_start = 0x0; 721 s->binfo.get_dtb = versal_virt_get_dtb; 722 s->binfo.modify_dtb = versal_virt_modify_dtb; 723 s->binfo.psci_conduit = psci_conduit; 724 if (!machine->kernel_filename) { 725 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL). 726 * Offset things by 4K. */ 727 s->binfo.loader_start = 0x1000; 728 s->binfo.dtb_limit = 0x1000000; 729 } 730 arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); 731 732 for (i = 0; i < XLNX_VERSAL_NUM_OSPI_FLASH; i++) { 733 BusState *spi_bus; 734 DeviceState *flash_dev; 735 qemu_irq cs_line; 736 DriveInfo *dinfo = drive_get(IF_MTD, 0, i); 737 738 spi_bus = qdev_get_child_bus(DEVICE(&s->soc.pmc.iou.ospi), "spi0"); 739 740 flash_dev = qdev_new("mt35xu01g"); 741 if (dinfo) { 742 qdev_prop_set_drive_err(flash_dev, "drive", 743 blk_by_legacy_dinfo(dinfo), &error_fatal); 744 } 745 qdev_prop_set_uint8(flash_dev, "cs", i); 746 qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); 747 748 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 749 750 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.pmc.iou.ospi), 751 i + 1, cs_line); 752 } 753 } 754 755 static void versal_virt_machine_instance_init(Object *obj) 756 { 757 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(obj); 758 759 /* 760 * User can set canbus0 and canbus1 properties to can-bus object and connect 761 * to socketcan(optional) interface via command line. 762 */ 763 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 764 (Object **)&s->canbus[0], 765 object_property_allow_set_link, 766 0); 767 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 768 (Object **)&s->canbus[1], 769 object_property_allow_set_link, 770 0); 771 } 772 773 static void versal_virt_machine_class_init(ObjectClass *oc, void *data) 774 { 775 MachineClass *mc = MACHINE_CLASS(oc); 776 777 mc->desc = "Xilinx Versal Virtual development board"; 778 mc->init = versal_virt_init; 779 mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 780 mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 781 mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 782 mc->no_cdrom = true; 783 mc->default_ram_id = "ddr"; 784 } 785 786 static const TypeInfo versal_virt_machine_init_typeinfo = { 787 .name = TYPE_XLNX_VERSAL_VIRT_MACHINE, 788 .parent = TYPE_MACHINE, 789 .class_init = versal_virt_machine_class_init, 790 .instance_init = versal_virt_machine_instance_init, 791 .instance_size = sizeof(VersalVirt), 792 }; 793 794 static void versal_virt_machine_init_register_types(void) 795 { 796 type_register_static(&versal_virt_machine_init_typeinfo); 797 } 798 799 type_init(versal_virt_machine_init_register_types) 800 801