1 /* 2 * Xilinx Versal Virtual board. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include "sysemu/device_tree.h" 16 #include "hw/boards.h" 17 #include "hw/sysbus.h" 18 #include "hw/arm/fdt.h" 19 #include "cpu.h" 20 #include "hw/qdev-properties.h" 21 #include "hw/arm/xlnx-versal.h" 22 #include "qom/object.h" 23 24 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") 25 OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE) 26 27 #define XLNX_VERSAL_NUM_OSPI_FLASH 4 28 29 struct VersalVirt { 30 MachineState parent_obj; 31 32 Versal soc; 33 34 void *fdt; 35 int fdt_size; 36 struct { 37 uint32_t gic; 38 uint32_t ethernet_phy[2]; 39 uint32_t clk_125Mhz; 40 uint32_t clk_25Mhz; 41 uint32_t usb; 42 uint32_t dwc; 43 uint32_t canfd[2]; 44 } phandle; 45 struct arm_boot_info binfo; 46 47 CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; 48 struct { 49 bool secure; 50 } cfg; 51 }; 52 53 static void fdt_create(VersalVirt *s) 54 { 55 MachineClass *mc = MACHINE_GET_CLASS(s); 56 int i; 57 58 s->fdt = create_device_tree(&s->fdt_size); 59 if (!s->fdt) { 60 error_report("create_device_tree() failed"); 61 exit(1); 62 } 63 64 /* Allocate all phandles. */ 65 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); 66 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { 67 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt); 68 } 69 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); 70 s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); 71 72 s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt); 73 s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt); 74 /* Create /chosen node for load_dtb. */ 75 qemu_fdt_add_subnode(s->fdt, "/chosen"); 76 77 /* Header */ 78 qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); 79 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); 80 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); 81 qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc); 82 qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt"); 83 } 84 85 static void fdt_add_clk_node(VersalVirt *s, const char *name, 86 unsigned int freq_hz, uint32_t phandle) 87 { 88 qemu_fdt_add_subnode(s->fdt, name); 89 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 90 qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); 91 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); 92 qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); 93 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 94 } 95 96 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) 97 { 98 int i; 99 100 qemu_fdt_add_subnode(s->fdt, "/cpus"); 101 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); 102 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); 103 104 for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) { 105 char *name = g_strdup_printf("/cpus/cpu@%d", i); 106 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 107 108 qemu_fdt_add_subnode(s->fdt, name); 109 qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); 110 if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 111 qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); 112 } 113 qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu"); 114 qemu_fdt_setprop_string(s->fdt, name, "compatible", 115 armcpu->dtb_compatible); 116 g_free(name); 117 } 118 } 119 120 static void fdt_add_gic_nodes(VersalVirt *s) 121 { 122 char *nodename; 123 124 nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); 125 qemu_fdt_add_subnode(s->fdt, nodename); 126 qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); 127 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", 128 GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, 129 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 130 qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); 131 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", 132 2, MM_GIC_APU_DIST_MAIN, 133 2, MM_GIC_APU_DIST_MAIN_SIZE, 134 2, MM_GIC_APU_REDIST_0, 135 2, MM_GIC_APU_REDIST_0_SIZE); 136 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); 137 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); 138 g_free(nodename); 139 } 140 141 static void fdt_add_timer_nodes(VersalVirt *s) 142 { 143 const char compat[] = "arm,armv8-timer"; 144 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 145 146 qemu_fdt_add_subnode(s->fdt, "/timer"); 147 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", 148 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, 149 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, 150 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, 151 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); 152 qemu_fdt_setprop(s->fdt, "/timer", "compatible", 153 compat, sizeof(compat)); 154 } 155 156 static void fdt_add_usb_xhci_nodes(VersalVirt *s) 157 { 158 const char clocknames[] = "bus_clk\0ref_clk"; 159 const char irq_name[] = "dwc_usb3"; 160 const char compatVersalDWC3[] = "xlnx,versal-dwc3"; 161 const char compatDWC3[] = "snps,dwc3"; 162 char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); 163 164 qemu_fdt_add_subnode(s->fdt, name); 165 qemu_fdt_setprop(s->fdt, name, "compatible", 166 compatVersalDWC3, sizeof(compatVersalDWC3)); 167 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 168 2, MM_USB2_CTRL_REGS, 169 2, MM_USB2_CTRL_REGS_SIZE); 170 qemu_fdt_setprop(s->fdt, name, "clock-names", 171 clocknames, sizeof(clocknames)); 172 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 173 s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); 174 qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); 175 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); 176 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); 177 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); 178 g_free(name); 179 180 name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, 181 MM_USB2_CTRL_REGS, MM_USB_0); 182 qemu_fdt_add_subnode(s->fdt, name); 183 qemu_fdt_setprop(s->fdt, name, "compatible", 184 compatDWC3, sizeof(compatDWC3)); 185 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 186 2, MM_USB_0, 2, MM_USB_0_SIZE); 187 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 188 irq_name, sizeof(irq_name)); 189 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 190 GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, 191 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 192 qemu_fdt_setprop_cell(s->fdt, name, 193 "snps,quirk-frame-length-adjustment", 0x20); 194 qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); 195 qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); 196 qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); 197 qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); 198 qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); 199 qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); 200 qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); 201 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); 202 qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); 203 g_free(name); 204 } 205 206 static void fdt_add_uart_nodes(VersalVirt *s) 207 { 208 uint64_t addrs[] = { MM_UART1, MM_UART0 }; 209 unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; 210 const char compat[] = "arm,pl011\0arm,sbsa-uart"; 211 const char clocknames[] = "uartclk\0apb_pclk"; 212 int i; 213 214 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 215 char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]); 216 qemu_fdt_add_subnode(s->fdt, name); 217 qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); 218 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 219 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 220 qemu_fdt_setprop(s->fdt, name, "clock-names", 221 clocknames, sizeof(clocknames)); 222 223 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 224 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 225 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 226 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 227 2, addrs[i], 2, 0x1000); 228 qemu_fdt_setprop(s->fdt, name, "compatible", 229 compat, sizeof(compat)); 230 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 231 232 if (addrs[i] == MM_UART0) { 233 /* Select UART0. */ 234 qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name); 235 } 236 g_free(name); 237 } 238 } 239 240 static void fdt_add_canfd_nodes(VersalVirt *s) 241 { 242 uint64_t addrs[] = { MM_CANFD1, MM_CANFD0 }; 243 uint32_t size[] = { MM_CANFD1_SIZE, MM_CANFD0_SIZE }; 244 unsigned int irqs[] = { VERSAL_CANFD1_IRQ_0, VERSAL_CANFD0_IRQ_0 }; 245 const char clocknames[] = "can_clk\0s_axi_aclk"; 246 int i; 247 248 /* Create and connect CANFD0 and CANFD1 nodes to canbus0. */ 249 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 250 char *name = g_strdup_printf("/canfd@%" PRIx64, addrs[i]); 251 qemu_fdt_add_subnode(s->fdt, name); 252 253 qemu_fdt_setprop_cell(s->fdt, name, "rx-fifo-depth", 0x40); 254 qemu_fdt_setprop_cell(s->fdt, name, "tx-mailbox-count", 0x20); 255 256 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 257 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 258 qemu_fdt_setprop(s->fdt, name, "clock-names", 259 clocknames, sizeof(clocknames)); 260 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 261 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 262 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 263 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 264 2, addrs[i], 2, size[i]); 265 qemu_fdt_setprop_string(s->fdt, name, "compatible", 266 "xlnx,canfd-2.0"); 267 268 g_free(name); 269 } 270 } 271 272 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, 273 uint32_t phandle) 274 { 275 char *name = g_strdup_printf("%s/fixed-link", gemname); 276 277 qemu_fdt_add_subnode(s->fdt, name); 278 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 279 qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); 280 qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); 281 g_free(name); 282 } 283 284 static void fdt_add_gem_nodes(VersalVirt *s) 285 { 286 uint64_t addrs[] = { MM_GEM1, MM_GEM0 }; 287 unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; 288 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; 289 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; 290 int i; 291 292 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 293 char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); 294 qemu_fdt_add_subnode(s->fdt, name); 295 296 fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); 297 qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); 298 qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", 299 s->phandle.ethernet_phy[i]); 300 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 301 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, 302 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 303 qemu_fdt_setprop(s->fdt, name, "clock-names", 304 clocknames, sizeof(clocknames)); 305 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 306 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 307 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 308 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 309 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 310 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 311 2, addrs[i], 2, 0x1000); 312 qemu_fdt_setprop(s->fdt, name, "compatible", 313 compat_gem, sizeof(compat_gem)); 314 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); 315 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); 316 g_free(name); 317 } 318 } 319 320 static void fdt_add_zdma_nodes(VersalVirt *s) 321 { 322 const char clocknames[] = "clk_main\0clk_apb"; 323 const char compat[] = "xlnx,zynqmp-dma-1.0"; 324 int i; 325 326 for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) { 327 uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i; 328 char *name = g_strdup_printf("/dma@%" PRIx64, addr); 329 330 qemu_fdt_add_subnode(s->fdt, name); 331 332 qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64); 333 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 334 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 335 qemu_fdt_setprop(s->fdt, name, "clock-names", 336 clocknames, sizeof(clocknames)); 337 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 338 GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i, 339 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 340 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 341 2, addr, 2, 0x1000); 342 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 343 g_free(name); 344 } 345 } 346 347 static void fdt_add_sd_nodes(VersalVirt *s) 348 { 349 const char clocknames[] = "clk_xin\0clk_ahb"; 350 const char compat[] = "arasan,sdhci-8.9a"; 351 int i; 352 353 for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) { 354 uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i; 355 char *name = g_strdup_printf("/sdhci@%" PRIx64, addr); 356 357 qemu_fdt_add_subnode(s->fdt, name); 358 359 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 360 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 361 qemu_fdt_setprop(s->fdt, name, "clock-names", 362 clocknames, sizeof(clocknames)); 363 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 364 GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2, 365 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 366 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 367 2, addr, 2, MM_PMC_SD0_SIZE); 368 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 369 g_free(name); 370 } 371 } 372 373 static void fdt_add_rtc_node(VersalVirt *s) 374 { 375 const char compat[] = "xlnx,zynqmp-rtc"; 376 const char interrupt_names[] = "alarm\0sec"; 377 char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC); 378 379 qemu_fdt_add_subnode(s->fdt, name); 380 381 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 382 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ, 383 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 384 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ, 385 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 386 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 387 interrupt_names, sizeof(interrupt_names)); 388 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 389 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE); 390 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 391 g_free(name); 392 } 393 394 static void fdt_add_bbram_node(VersalVirt *s) 395 { 396 const char compat[] = TYPE_XLNX_BBRAM; 397 const char interrupt_names[] = "bbram-error"; 398 char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL); 399 400 qemu_fdt_add_subnode(s->fdt, name); 401 402 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 403 GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ, 404 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 405 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 406 interrupt_names, sizeof(interrupt_names)); 407 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 408 2, MM_PMC_BBRAM_CTRL, 409 2, MM_PMC_BBRAM_CTRL_SIZE); 410 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 411 g_free(name); 412 } 413 414 static void fdt_add_efuse_ctrl_node(VersalVirt *s) 415 { 416 const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL; 417 const char interrupt_names[] = "pmc_efuse"; 418 char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL); 419 420 qemu_fdt_add_subnode(s->fdt, name); 421 422 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 423 GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ, 424 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 425 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 426 interrupt_names, sizeof(interrupt_names)); 427 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 428 2, MM_PMC_EFUSE_CTRL, 429 2, MM_PMC_EFUSE_CTRL_SIZE); 430 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 431 g_free(name); 432 } 433 434 static void fdt_add_efuse_cache_node(VersalVirt *s) 435 { 436 const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE; 437 char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x", 438 MM_PMC_EFUSE_CACHE); 439 440 qemu_fdt_add_subnode(s->fdt, name); 441 442 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 443 2, MM_PMC_EFUSE_CACHE, 444 2, MM_PMC_EFUSE_CACHE_SIZE); 445 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 446 g_free(name); 447 } 448 449 static void fdt_nop_memory_nodes(void *fdt, Error **errp) 450 { 451 Error *err = NULL; 452 char **node_path; 453 int n = 0; 454 455 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 456 if (err) { 457 error_propagate(errp, err); 458 return; 459 } 460 while (node_path[n]) { 461 if (g_str_has_prefix(node_path[n], "/memory")) { 462 qemu_fdt_nop_node(fdt, node_path[n]); 463 } 464 n++; 465 } 466 g_strfreev(node_path); 467 } 468 469 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size) 470 { 471 /* Describes the various split DDR access regions. */ 472 static const struct { 473 uint64_t base; 474 uint64_t size; 475 } addr_ranges[] = { 476 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 477 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 478 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 479 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 480 }; 481 uint64_t mem_reg_prop[8] = {0}; 482 uint64_t size = ram_size; 483 Error *err = NULL; 484 char *name; 485 int i; 486 487 fdt_nop_memory_nodes(fdt, &err); 488 if (err) { 489 error_report_err(err); 490 return; 491 } 492 493 name = g_strdup_printf("/memory@%x", MM_TOP_DDR); 494 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 495 uint64_t mapsize; 496 497 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 498 499 mem_reg_prop[i * 2] = addr_ranges[i].base; 500 mem_reg_prop[i * 2 + 1] = mapsize; 501 size -= mapsize; 502 } 503 qemu_fdt_add_subnode(fdt, name); 504 qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); 505 506 switch (i) { 507 case 1: 508 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 509 2, mem_reg_prop[0], 510 2, mem_reg_prop[1]); 511 break; 512 case 2: 513 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 514 2, mem_reg_prop[0], 515 2, mem_reg_prop[1], 516 2, mem_reg_prop[2], 517 2, mem_reg_prop[3]); 518 break; 519 case 3: 520 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 521 2, mem_reg_prop[0], 522 2, mem_reg_prop[1], 523 2, mem_reg_prop[2], 524 2, mem_reg_prop[3], 525 2, mem_reg_prop[4], 526 2, mem_reg_prop[5]); 527 break; 528 case 4: 529 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 530 2, mem_reg_prop[0], 531 2, mem_reg_prop[1], 532 2, mem_reg_prop[2], 533 2, mem_reg_prop[3], 534 2, mem_reg_prop[4], 535 2, mem_reg_prop[5], 536 2, mem_reg_prop[6], 537 2, mem_reg_prop[7]); 538 break; 539 default: 540 g_assert_not_reached(); 541 } 542 g_free(name); 543 } 544 545 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, 546 void *fdt) 547 { 548 VersalVirt *s = container_of(binfo, VersalVirt, binfo); 549 550 fdt_add_memory_nodes(s, fdt, binfo->ram_size); 551 } 552 553 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, 554 int *fdt_size) 555 { 556 const VersalVirt *board = container_of(binfo, VersalVirt, binfo); 557 558 *fdt_size = board->fdt_size; 559 return board->fdt; 560 } 561 562 #define NUM_VIRTIO_TRANSPORT 8 563 static void create_virtio_regions(VersalVirt *s) 564 { 565 int virtio_mmio_size = 0x200; 566 int i; 567 568 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 569 char *name = g_strdup_printf("virtio%d", i); 570 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 571 int irq = VERSAL_RSVD_IRQ_FIRST + i; 572 MemoryRegion *mr; 573 DeviceState *dev; 574 qemu_irq pic_irq; 575 576 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 577 dev = qdev_new("virtio-mmio"); 578 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 579 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 580 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 581 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 582 memory_region_add_subregion(&s->soc.mr_ps, base, mr); 583 g_free(name); 584 } 585 586 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 587 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 588 int irq = VERSAL_RSVD_IRQ_FIRST + i; 589 char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 590 591 qemu_fdt_add_subnode(s->fdt, name); 592 qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); 593 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 594 GIC_FDT_IRQ_TYPE_SPI, irq, 595 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 596 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 597 2, base, 2, virtio_mmio_size); 598 qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); 599 g_free(name); 600 } 601 } 602 603 static void bbram_attach_drive(XlnxBBRam *dev) 604 { 605 DriveInfo *dinfo; 606 BlockBackend *blk; 607 608 dinfo = drive_get_by_index(IF_PFLASH, 0); 609 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 610 if (blk) { 611 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 612 } 613 } 614 615 static void efuse_attach_drive(XlnxEFuse *dev) 616 { 617 DriveInfo *dinfo; 618 BlockBackend *blk; 619 620 dinfo = drive_get_by_index(IF_PFLASH, 1); 621 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 622 if (blk) { 623 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 624 } 625 } 626 627 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) 628 { 629 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 630 DeviceState *card; 631 632 card = qdev_new(TYPE_SD_CARD); 633 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card)); 634 qdev_prop_set_drive_err(card, "drive", blk, &error_fatal); 635 qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"), 636 &error_fatal); 637 } 638 639 static void versal_virt_init(MachineState *machine) 640 { 641 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine); 642 int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 643 int i; 644 645 /* 646 * If the user provides an Operating System to be loaded, we expect them 647 * to use the -kernel command line option. 648 * 649 * Users can load firmware or boot-loaders with the -device loader options. 650 * 651 * When loading an OS, we generate a dtb and let arm_load_kernel() select 652 * where it gets loaded. This dtb will be passed to the kernel in x0. 653 * 654 * If there's no -kernel option, we generate a DTB and place it at 0x1000 655 * for the bootloaders or firmware to pick up. 656 * 657 * If users want to provide their own DTB, they can use the -dtb option. 658 * These dtb's will have their memory nodes modified to match QEMU's 659 * selected ram_size option before they get passed to the kernel or fw. 660 * 661 * When loading an OS, we turn on QEMU's PSCI implementation with SMC 662 * as the PSCI conduit. When there's no -kernel, we assume the user 663 * provides EL3 firmware to handle PSCI. 664 * 665 * Even if the user provides a kernel filename, arm_load_kernel() 666 * may suppress PSCI if it's going to boot that guest code at EL3. 667 */ 668 if (machine->kernel_filename) { 669 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 670 } 671 672 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 673 TYPE_XLNX_VERSAL); 674 object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), 675 &error_abort); 676 object_property_set_link(OBJECT(&s->soc), "canbus0", OBJECT(s->canbus[0]), 677 &error_abort); 678 object_property_set_link(OBJECT(&s->soc), "canbus1", OBJECT(s->canbus[1]), 679 &error_abort); 680 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 681 682 fdt_create(s); 683 create_virtio_regions(s); 684 fdt_add_gem_nodes(s); 685 fdt_add_uart_nodes(s); 686 fdt_add_canfd_nodes(s); 687 fdt_add_gic_nodes(s); 688 fdt_add_timer_nodes(s); 689 fdt_add_zdma_nodes(s); 690 fdt_add_usb_xhci_nodes(s); 691 fdt_add_sd_nodes(s); 692 fdt_add_rtc_node(s); 693 fdt_add_bbram_node(s); 694 fdt_add_efuse_ctrl_node(s); 695 fdt_add_efuse_cache_node(s); 696 fdt_add_cpu_nodes(s, psci_conduit); 697 fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); 698 fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); 699 700 /* Make the APU cpu address space visible to virtio and other 701 * modules unaware of multiple address-spaces. */ 702 memory_region_add_subregion_overlap(get_system_memory(), 703 0, &s->soc.fpd.apu.mr, 0); 704 705 /* Attach bbram backend, if given */ 706 bbram_attach_drive(&s->soc.pmc.bbram); 707 708 /* Attach efuse backend, if given */ 709 efuse_attach_drive(&s->soc.pmc.efuse); 710 711 /* Plugin SD cards. */ 712 for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { 713 sd_plugin_card(&s->soc.pmc.iou.sd[i], 714 drive_get(IF_SD, 0, i)); 715 } 716 717 s->binfo.ram_size = machine->ram_size; 718 s->binfo.loader_start = 0x0; 719 s->binfo.get_dtb = versal_virt_get_dtb; 720 s->binfo.modify_dtb = versal_virt_modify_dtb; 721 s->binfo.psci_conduit = psci_conduit; 722 if (!machine->kernel_filename) { 723 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL). 724 * Offset things by 4K. */ 725 s->binfo.loader_start = 0x1000; 726 s->binfo.dtb_limit = 0x1000000; 727 } 728 arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); 729 730 for (i = 0; i < XLNX_VERSAL_NUM_OSPI_FLASH; i++) { 731 BusState *spi_bus; 732 DeviceState *flash_dev; 733 qemu_irq cs_line; 734 DriveInfo *dinfo = drive_get(IF_MTD, 0, i); 735 736 spi_bus = qdev_get_child_bus(DEVICE(&s->soc.pmc.iou.ospi), "spi0"); 737 738 flash_dev = qdev_new("mt35xu01g"); 739 if (dinfo) { 740 qdev_prop_set_drive_err(flash_dev, "drive", 741 blk_by_legacy_dinfo(dinfo), &error_fatal); 742 } 743 qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); 744 745 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 746 747 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.pmc.iou.ospi), 748 i + 1, cs_line); 749 } 750 } 751 752 static void versal_virt_machine_instance_init(Object *obj) 753 { 754 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(obj); 755 756 /* 757 * User can set canbus0 and canbus1 properties to can-bus object and connect 758 * to socketcan(optional) interface via command line. 759 */ 760 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 761 (Object **)&s->canbus[0], 762 object_property_allow_set_link, 763 0); 764 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 765 (Object **)&s->canbus[1], 766 object_property_allow_set_link, 767 0); 768 } 769 770 static void versal_virt_machine_class_init(ObjectClass *oc, void *data) 771 { 772 MachineClass *mc = MACHINE_CLASS(oc); 773 774 mc->desc = "Xilinx Versal Virtual development board"; 775 mc->init = versal_virt_init; 776 mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 777 mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 778 mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 779 mc->no_cdrom = true; 780 mc->default_ram_id = "ddr"; 781 } 782 783 static const TypeInfo versal_virt_machine_init_typeinfo = { 784 .name = TYPE_XLNX_VERSAL_VIRT_MACHINE, 785 .parent = TYPE_MACHINE, 786 .class_init = versal_virt_machine_class_init, 787 .instance_init = versal_virt_machine_instance_init, 788 .instance_size = sizeof(VersalVirt), 789 }; 790 791 static void versal_virt_machine_init_register_types(void) 792 { 793 type_register_static(&versal_virt_machine_init_typeinfo); 794 } 795 796 type_init(versal_virt_machine_init_register_types) 797 798