1 /* 2 * Xilinx Versal Virtual board. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include "sysemu/device_tree.h" 16 #include "hw/boards.h" 17 #include "hw/sysbus.h" 18 #include "hw/arm/fdt.h" 19 #include "cpu.h" 20 #include "hw/qdev-properties.h" 21 #include "hw/arm/xlnx-versal.h" 22 #include "hw/arm/boot.h" 23 #include "qom/object.h" 24 25 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") 26 OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE) 27 28 #define XLNX_VERSAL_NUM_OSPI_FLASH 4 29 30 struct VersalVirt { 31 MachineState parent_obj; 32 33 Versal soc; 34 35 void *fdt; 36 int fdt_size; 37 struct { 38 uint32_t gic; 39 uint32_t ethernet_phy[2]; 40 uint32_t clk_125Mhz; 41 uint32_t clk_25Mhz; 42 uint32_t usb; 43 uint32_t dwc; 44 uint32_t canfd[2]; 45 } phandle; 46 struct arm_boot_info binfo; 47 48 CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; 49 struct { 50 bool secure; 51 } cfg; 52 }; 53 54 static void fdt_create(VersalVirt *s) 55 { 56 MachineClass *mc = MACHINE_GET_CLASS(s); 57 int i; 58 59 s->fdt = create_device_tree(&s->fdt_size); 60 if (!s->fdt) { 61 error_report("create_device_tree() failed"); 62 exit(1); 63 } 64 65 /* Allocate all phandles. */ 66 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); 67 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { 68 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt); 69 } 70 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); 71 s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); 72 73 s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt); 74 s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt); 75 /* Create /chosen node for load_dtb. */ 76 qemu_fdt_add_subnode(s->fdt, "/chosen"); 77 78 /* Header */ 79 qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); 80 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); 81 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); 82 qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc); 83 qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt"); 84 } 85 86 static void fdt_add_clk_node(VersalVirt *s, const char *name, 87 unsigned int freq_hz, uint32_t phandle) 88 { 89 qemu_fdt_add_subnode(s->fdt, name); 90 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 91 qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); 92 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); 93 qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); 94 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 95 } 96 97 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) 98 { 99 int i; 100 101 qemu_fdt_add_subnode(s->fdt, "/cpus"); 102 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); 103 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); 104 105 for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) { 106 char *name = g_strdup_printf("/cpus/cpu@%d", i); 107 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 108 109 qemu_fdt_add_subnode(s->fdt, name); 110 qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); 111 if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 112 qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); 113 } 114 qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu"); 115 qemu_fdt_setprop_string(s->fdt, name, "compatible", 116 armcpu->dtb_compatible); 117 g_free(name); 118 } 119 } 120 121 static void fdt_add_gic_nodes(VersalVirt *s) 122 { 123 char *nodename; 124 125 nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); 126 qemu_fdt_add_subnode(s->fdt, nodename); 127 qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); 128 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", 129 GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, 130 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 131 qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); 132 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", 133 2, MM_GIC_APU_DIST_MAIN, 134 2, MM_GIC_APU_DIST_MAIN_SIZE, 135 2, MM_GIC_APU_REDIST_0, 136 2, MM_GIC_APU_REDIST_0_SIZE); 137 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); 138 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); 139 g_free(nodename); 140 } 141 142 static void fdt_add_timer_nodes(VersalVirt *s) 143 { 144 const char compat[] = "arm,armv8-timer"; 145 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 146 147 qemu_fdt_add_subnode(s->fdt, "/timer"); 148 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", 149 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, 150 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, 151 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, 152 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); 153 qemu_fdt_setprop(s->fdt, "/timer", "compatible", 154 compat, sizeof(compat)); 155 } 156 157 static void fdt_add_usb_xhci_nodes(VersalVirt *s) 158 { 159 const char clocknames[] = "bus_clk\0ref_clk"; 160 const char irq_name[] = "dwc_usb3"; 161 const char compatVersalDWC3[] = "xlnx,versal-dwc3"; 162 const char compatDWC3[] = "snps,dwc3"; 163 char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); 164 165 qemu_fdt_add_subnode(s->fdt, name); 166 qemu_fdt_setprop(s->fdt, name, "compatible", 167 compatVersalDWC3, sizeof(compatVersalDWC3)); 168 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 169 2, MM_USB2_CTRL_REGS, 170 2, MM_USB2_CTRL_REGS_SIZE); 171 qemu_fdt_setprop(s->fdt, name, "clock-names", 172 clocknames, sizeof(clocknames)); 173 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 174 s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); 175 qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); 176 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); 177 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); 178 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); 179 g_free(name); 180 181 name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, 182 MM_USB2_CTRL_REGS, MM_USB_0); 183 qemu_fdt_add_subnode(s->fdt, name); 184 qemu_fdt_setprop(s->fdt, name, "compatible", 185 compatDWC3, sizeof(compatDWC3)); 186 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 187 2, MM_USB_0, 2, MM_USB_0_SIZE); 188 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 189 irq_name, sizeof(irq_name)); 190 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 191 GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, 192 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 193 qemu_fdt_setprop_cell(s->fdt, name, 194 "snps,quirk-frame-length-adjustment", 0x20); 195 qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); 196 qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); 197 qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); 198 qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); 199 qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); 200 qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); 201 qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); 202 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); 203 qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); 204 g_free(name); 205 } 206 207 static void fdt_add_uart_nodes(VersalVirt *s) 208 { 209 uint64_t addrs[] = { MM_UART1, MM_UART0 }; 210 unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; 211 const char compat[] = "arm,pl011\0arm,sbsa-uart"; 212 const char clocknames[] = "uartclk\0apb_pclk"; 213 int i; 214 215 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 216 char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]); 217 qemu_fdt_add_subnode(s->fdt, name); 218 qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); 219 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 220 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 221 qemu_fdt_setprop(s->fdt, name, "clock-names", 222 clocknames, sizeof(clocknames)); 223 224 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 225 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 226 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 227 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 228 2, addrs[i], 2, 0x1000); 229 qemu_fdt_setprop(s->fdt, name, "compatible", 230 compat, sizeof(compat)); 231 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 232 233 if (addrs[i] == MM_UART0) { 234 /* Select UART0. */ 235 qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name); 236 } 237 g_free(name); 238 } 239 } 240 241 static void fdt_add_canfd_nodes(VersalVirt *s) 242 { 243 uint64_t addrs[] = { MM_CANFD1, MM_CANFD0 }; 244 uint32_t size[] = { MM_CANFD1_SIZE, MM_CANFD0_SIZE }; 245 unsigned int irqs[] = { VERSAL_CANFD1_IRQ_0, VERSAL_CANFD0_IRQ_0 }; 246 const char clocknames[] = "can_clk\0s_axi_aclk"; 247 int i; 248 249 /* Create and connect CANFD0 and CANFD1 nodes to canbus0. */ 250 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 251 char *name = g_strdup_printf("/canfd@%" PRIx64, addrs[i]); 252 qemu_fdt_add_subnode(s->fdt, name); 253 254 qemu_fdt_setprop_cell(s->fdt, name, "rx-fifo-depth", 0x40); 255 qemu_fdt_setprop_cell(s->fdt, name, "tx-mailbox-count", 0x20); 256 257 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 258 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 259 qemu_fdt_setprop(s->fdt, name, "clock-names", 260 clocknames, sizeof(clocknames)); 261 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 262 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 263 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 264 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 265 2, addrs[i], 2, size[i]); 266 qemu_fdt_setprop_string(s->fdt, name, "compatible", 267 "xlnx,canfd-2.0"); 268 269 g_free(name); 270 } 271 } 272 273 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, 274 uint32_t phandle) 275 { 276 char *name = g_strdup_printf("%s/fixed-link", gemname); 277 278 qemu_fdt_add_subnode(s->fdt, name); 279 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 280 qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); 281 qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); 282 g_free(name); 283 } 284 285 static void fdt_add_gem_nodes(VersalVirt *s) 286 { 287 uint64_t addrs[] = { MM_GEM1, MM_GEM0 }; 288 unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; 289 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; 290 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; 291 int i; 292 293 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 294 char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); 295 qemu_fdt_add_subnode(s->fdt, name); 296 297 fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); 298 qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); 299 qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", 300 s->phandle.ethernet_phy[i]); 301 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 302 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, 303 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 304 qemu_fdt_setprop(s->fdt, name, "clock-names", 305 clocknames, sizeof(clocknames)); 306 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 307 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 308 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 309 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 310 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 311 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 312 2, addrs[i], 2, 0x1000); 313 qemu_fdt_setprop(s->fdt, name, "compatible", 314 compat_gem, sizeof(compat_gem)); 315 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); 316 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); 317 g_free(name); 318 } 319 } 320 321 static void fdt_add_zdma_nodes(VersalVirt *s) 322 { 323 const char clocknames[] = "clk_main\0clk_apb"; 324 const char compat[] = "xlnx,zynqmp-dma-1.0"; 325 int i; 326 327 for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) { 328 uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i; 329 char *name = g_strdup_printf("/dma@%" PRIx64, addr); 330 331 qemu_fdt_add_subnode(s->fdt, name); 332 333 qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64); 334 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 335 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 336 qemu_fdt_setprop(s->fdt, name, "clock-names", 337 clocknames, sizeof(clocknames)); 338 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 339 GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i, 340 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 341 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 342 2, addr, 2, 0x1000); 343 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 344 g_free(name); 345 } 346 } 347 348 static void fdt_add_sd_nodes(VersalVirt *s) 349 { 350 const char clocknames[] = "clk_xin\0clk_ahb"; 351 const char compat[] = "arasan,sdhci-8.9a"; 352 int i; 353 354 for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) { 355 uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i; 356 char *name = g_strdup_printf("/sdhci@%" PRIx64, addr); 357 358 qemu_fdt_add_subnode(s->fdt, name); 359 360 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 361 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 362 qemu_fdt_setprop(s->fdt, name, "clock-names", 363 clocknames, sizeof(clocknames)); 364 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 365 GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2, 366 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 367 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 368 2, addr, 2, MM_PMC_SD0_SIZE); 369 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 370 g_free(name); 371 } 372 } 373 374 static void fdt_add_rtc_node(VersalVirt *s) 375 { 376 const char compat[] = "xlnx,zynqmp-rtc"; 377 const char interrupt_names[] = "alarm\0sec"; 378 char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC); 379 380 qemu_fdt_add_subnode(s->fdt, name); 381 382 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 383 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ, 384 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 385 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ, 386 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 387 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 388 interrupt_names, sizeof(interrupt_names)); 389 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 390 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE); 391 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 392 g_free(name); 393 } 394 395 static void fdt_add_bbram_node(VersalVirt *s) 396 { 397 const char compat[] = TYPE_XLNX_BBRAM; 398 const char interrupt_names[] = "bbram-error"; 399 char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL); 400 401 qemu_fdt_add_subnode(s->fdt, name); 402 403 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 404 GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ, 405 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 406 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 407 interrupt_names, sizeof(interrupt_names)); 408 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 409 2, MM_PMC_BBRAM_CTRL, 410 2, MM_PMC_BBRAM_CTRL_SIZE); 411 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 412 g_free(name); 413 } 414 415 static void fdt_add_efuse_ctrl_node(VersalVirt *s) 416 { 417 const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL; 418 const char interrupt_names[] = "pmc_efuse"; 419 char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL); 420 421 qemu_fdt_add_subnode(s->fdt, name); 422 423 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 424 GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ, 425 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 426 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 427 interrupt_names, sizeof(interrupt_names)); 428 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 429 2, MM_PMC_EFUSE_CTRL, 430 2, MM_PMC_EFUSE_CTRL_SIZE); 431 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 432 g_free(name); 433 } 434 435 static void fdt_add_efuse_cache_node(VersalVirt *s) 436 { 437 const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE; 438 char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x", 439 MM_PMC_EFUSE_CACHE); 440 441 qemu_fdt_add_subnode(s->fdt, name); 442 443 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 444 2, MM_PMC_EFUSE_CACHE, 445 2, MM_PMC_EFUSE_CACHE_SIZE); 446 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 447 g_free(name); 448 } 449 450 static void fdt_nop_memory_nodes(void *fdt, Error **errp) 451 { 452 Error *err = NULL; 453 char **node_path; 454 int n = 0; 455 456 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 457 if (err) { 458 error_propagate(errp, err); 459 return; 460 } 461 while (node_path[n]) { 462 if (g_str_has_prefix(node_path[n], "/memory")) { 463 qemu_fdt_nop_node(fdt, node_path[n]); 464 } 465 n++; 466 } 467 g_strfreev(node_path); 468 } 469 470 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size) 471 { 472 /* Describes the various split DDR access regions. */ 473 static const struct { 474 uint64_t base; 475 uint64_t size; 476 } addr_ranges[] = { 477 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 478 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 479 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 480 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 481 }; 482 uint64_t mem_reg_prop[8] = {0}; 483 uint64_t size = ram_size; 484 Error *err = NULL; 485 char *name; 486 int i; 487 488 fdt_nop_memory_nodes(fdt, &err); 489 if (err) { 490 error_report_err(err); 491 return; 492 } 493 494 name = g_strdup_printf("/memory@%x", MM_TOP_DDR); 495 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 496 uint64_t mapsize; 497 498 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 499 500 mem_reg_prop[i * 2] = addr_ranges[i].base; 501 mem_reg_prop[i * 2 + 1] = mapsize; 502 size -= mapsize; 503 } 504 qemu_fdt_add_subnode(fdt, name); 505 qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); 506 507 switch (i) { 508 case 1: 509 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 510 2, mem_reg_prop[0], 511 2, mem_reg_prop[1]); 512 break; 513 case 2: 514 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 515 2, mem_reg_prop[0], 516 2, mem_reg_prop[1], 517 2, mem_reg_prop[2], 518 2, mem_reg_prop[3]); 519 break; 520 case 3: 521 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 522 2, mem_reg_prop[0], 523 2, mem_reg_prop[1], 524 2, mem_reg_prop[2], 525 2, mem_reg_prop[3], 526 2, mem_reg_prop[4], 527 2, mem_reg_prop[5]); 528 break; 529 case 4: 530 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 531 2, mem_reg_prop[0], 532 2, mem_reg_prop[1], 533 2, mem_reg_prop[2], 534 2, mem_reg_prop[3], 535 2, mem_reg_prop[4], 536 2, mem_reg_prop[5], 537 2, mem_reg_prop[6], 538 2, mem_reg_prop[7]); 539 break; 540 default: 541 g_assert_not_reached(); 542 } 543 g_free(name); 544 } 545 546 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, 547 void *fdt) 548 { 549 VersalVirt *s = container_of(binfo, VersalVirt, binfo); 550 551 fdt_add_memory_nodes(s, fdt, binfo->ram_size); 552 } 553 554 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, 555 int *fdt_size) 556 { 557 const VersalVirt *board = container_of(binfo, VersalVirt, binfo); 558 559 *fdt_size = board->fdt_size; 560 return board->fdt; 561 } 562 563 #define NUM_VIRTIO_TRANSPORT 8 564 static void create_virtio_regions(VersalVirt *s) 565 { 566 int virtio_mmio_size = 0x200; 567 int i; 568 569 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 570 char *name = g_strdup_printf("virtio%d", i); 571 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 572 int irq = VERSAL_RSVD_IRQ_FIRST + i; 573 MemoryRegion *mr; 574 DeviceState *dev; 575 qemu_irq pic_irq; 576 577 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 578 dev = qdev_new("virtio-mmio"); 579 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 580 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 581 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 582 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 583 memory_region_add_subregion(&s->soc.mr_ps, base, mr); 584 g_free(name); 585 } 586 587 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 588 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 589 int irq = VERSAL_RSVD_IRQ_FIRST + i; 590 char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 591 592 qemu_fdt_add_subnode(s->fdt, name); 593 qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); 594 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 595 GIC_FDT_IRQ_TYPE_SPI, irq, 596 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 597 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 598 2, base, 2, virtio_mmio_size); 599 qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); 600 g_free(name); 601 } 602 } 603 604 static void bbram_attach_drive(XlnxBBRam *dev) 605 { 606 DriveInfo *dinfo; 607 BlockBackend *blk; 608 609 dinfo = drive_get_by_index(IF_PFLASH, 0); 610 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 611 if (blk) { 612 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 613 } 614 } 615 616 static void efuse_attach_drive(XlnxEFuse *dev) 617 { 618 DriveInfo *dinfo; 619 BlockBackend *blk; 620 621 dinfo = drive_get_by_index(IF_PFLASH, 1); 622 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 623 if (blk) { 624 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 625 } 626 } 627 628 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) 629 { 630 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 631 DeviceState *card; 632 633 card = qdev_new(TYPE_SD_CARD); 634 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card)); 635 qdev_prop_set_drive_err(card, "drive", blk, &error_fatal); 636 qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"), 637 &error_fatal); 638 } 639 640 static void versal_virt_init(MachineState *machine) 641 { 642 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine); 643 int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 644 int i; 645 646 /* 647 * If the user provides an Operating System to be loaded, we expect them 648 * to use the -kernel command line option. 649 * 650 * Users can load firmware or boot-loaders with the -device loader options. 651 * 652 * When loading an OS, we generate a dtb and let arm_load_kernel() select 653 * where it gets loaded. This dtb will be passed to the kernel in x0. 654 * 655 * If there's no -kernel option, we generate a DTB and place it at 0x1000 656 * for the bootloaders or firmware to pick up. 657 * 658 * If users want to provide their own DTB, they can use the -dtb option. 659 * These dtb's will have their memory nodes modified to match QEMU's 660 * selected ram_size option before they get passed to the kernel or fw. 661 * 662 * When loading an OS, we turn on QEMU's PSCI implementation with SMC 663 * as the PSCI conduit. When there's no -kernel, we assume the user 664 * provides EL3 firmware to handle PSCI. 665 * 666 * Even if the user provides a kernel filename, arm_load_kernel() 667 * may suppress PSCI if it's going to boot that guest code at EL3. 668 */ 669 if (machine->kernel_filename) { 670 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 671 } 672 673 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 674 TYPE_XLNX_VERSAL); 675 object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), 676 &error_abort); 677 object_property_set_link(OBJECT(&s->soc), "canbus0", OBJECT(s->canbus[0]), 678 &error_abort); 679 object_property_set_link(OBJECT(&s->soc), "canbus1", OBJECT(s->canbus[1]), 680 &error_abort); 681 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 682 683 fdt_create(s); 684 create_virtio_regions(s); 685 fdt_add_gem_nodes(s); 686 fdt_add_uart_nodes(s); 687 fdt_add_canfd_nodes(s); 688 fdt_add_gic_nodes(s); 689 fdt_add_timer_nodes(s); 690 fdt_add_zdma_nodes(s); 691 fdt_add_usb_xhci_nodes(s); 692 fdt_add_sd_nodes(s); 693 fdt_add_rtc_node(s); 694 fdt_add_bbram_node(s); 695 fdt_add_efuse_ctrl_node(s); 696 fdt_add_efuse_cache_node(s); 697 fdt_add_cpu_nodes(s, psci_conduit); 698 fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); 699 fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); 700 701 /* Make the APU cpu address space visible to virtio and other 702 * modules unaware of multiple address-spaces. */ 703 memory_region_add_subregion_overlap(get_system_memory(), 704 0, &s->soc.fpd.apu.mr, 0); 705 706 /* Attach bbram backend, if given */ 707 bbram_attach_drive(&s->soc.pmc.bbram); 708 709 /* Attach efuse backend, if given */ 710 efuse_attach_drive(&s->soc.pmc.efuse); 711 712 /* Plugin SD cards. */ 713 for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { 714 sd_plugin_card(&s->soc.pmc.iou.sd[i], 715 drive_get(IF_SD, 0, i)); 716 } 717 718 s->binfo.ram_size = machine->ram_size; 719 s->binfo.loader_start = 0x0; 720 s->binfo.get_dtb = versal_virt_get_dtb; 721 s->binfo.modify_dtb = versal_virt_modify_dtb; 722 s->binfo.psci_conduit = psci_conduit; 723 if (!machine->kernel_filename) { 724 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL). 725 * Offset things by 4K. */ 726 s->binfo.loader_start = 0x1000; 727 s->binfo.dtb_limit = 0x1000000; 728 } 729 arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); 730 731 for (i = 0; i < XLNX_VERSAL_NUM_OSPI_FLASH; i++) { 732 BusState *spi_bus; 733 DeviceState *flash_dev; 734 qemu_irq cs_line; 735 DriveInfo *dinfo = drive_get(IF_MTD, 0, i); 736 737 spi_bus = qdev_get_child_bus(DEVICE(&s->soc.pmc.iou.ospi), "spi0"); 738 739 flash_dev = qdev_new("mt35xu01g"); 740 if (dinfo) { 741 qdev_prop_set_drive_err(flash_dev, "drive", 742 blk_by_legacy_dinfo(dinfo), &error_fatal); 743 } 744 qdev_prop_set_uint8(flash_dev, "cs", i); 745 qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); 746 747 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 748 749 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.pmc.iou.ospi), 750 i + 1, cs_line); 751 } 752 } 753 754 static void versal_virt_machine_instance_init(Object *obj) 755 { 756 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(obj); 757 758 /* 759 * User can set canbus0 and canbus1 properties to can-bus object and connect 760 * to socketcan(optional) interface via command line. 761 */ 762 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 763 (Object **)&s->canbus[0], 764 object_property_allow_set_link, 765 0); 766 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 767 (Object **)&s->canbus[1], 768 object_property_allow_set_link, 769 0); 770 } 771 772 static void versal_virt_machine_class_init(ObjectClass *oc, void *data) 773 { 774 MachineClass *mc = MACHINE_CLASS(oc); 775 776 mc->desc = "Xilinx Versal Virtual development board"; 777 mc->init = versal_virt_init; 778 mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 779 mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 780 mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; 781 mc->no_cdrom = true; 782 mc->default_ram_id = "ddr"; 783 } 784 785 static const TypeInfo versal_virt_machine_init_typeinfo = { 786 .name = TYPE_XLNX_VERSAL_VIRT_MACHINE, 787 .parent = TYPE_MACHINE, 788 .class_init = versal_virt_machine_class_init, 789 .instance_init = versal_virt_machine_instance_init, 790 .instance_size = sizeof(VersalVirt), 791 }; 792 793 static void versal_virt_machine_init_register_types(void) 794 { 795 type_register_static(&versal_virt_machine_init_typeinfo); 796 } 797 798 type_init(versal_virt_machine_init_register_types) 799 800