1 /* 2 * Xilinx Versal Virtual board. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include "sysemu/device_tree.h" 16 #include "hw/boards.h" 17 #include "hw/sysbus.h" 18 #include "hw/arm/sysbus-fdt.h" 19 #include "hw/arm/fdt.h" 20 #include "cpu.h" 21 #include "hw/qdev-properties.h" 22 #include "hw/arm/xlnx-versal.h" 23 #include "qom/object.h" 24 25 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") 26 OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE) 27 28 #define XLNX_VERSAL_NUM_OSPI_FLASH 4 29 30 struct VersalVirt { 31 MachineState parent_obj; 32 33 Versal soc; 34 35 void *fdt; 36 int fdt_size; 37 struct { 38 uint32_t gic; 39 uint32_t ethernet_phy[2]; 40 uint32_t clk_125Mhz; 41 uint32_t clk_25Mhz; 42 uint32_t usb; 43 uint32_t dwc; 44 } phandle; 45 struct arm_boot_info binfo; 46 47 struct { 48 bool secure; 49 } cfg; 50 }; 51 52 static void fdt_create(VersalVirt *s) 53 { 54 MachineClass *mc = MACHINE_GET_CLASS(s); 55 int i; 56 57 s->fdt = create_device_tree(&s->fdt_size); 58 if (!s->fdt) { 59 error_report("create_device_tree() failed"); 60 exit(1); 61 } 62 63 /* Allocate all phandles. */ 64 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); 65 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { 66 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt); 67 } 68 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); 69 s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); 70 71 s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt); 72 s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt); 73 /* Create /chosen node for load_dtb. */ 74 qemu_fdt_add_subnode(s->fdt, "/chosen"); 75 76 /* Header */ 77 qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); 78 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); 79 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); 80 qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc); 81 qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt"); 82 } 83 84 static void fdt_add_clk_node(VersalVirt *s, const char *name, 85 unsigned int freq_hz, uint32_t phandle) 86 { 87 qemu_fdt_add_subnode(s->fdt, name); 88 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 89 qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); 90 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); 91 qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); 92 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 93 } 94 95 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) 96 { 97 int i; 98 99 qemu_fdt_add_subnode(s->fdt, "/cpus"); 100 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); 101 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); 102 103 for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) { 104 char *name = g_strdup_printf("/cpus/cpu@%d", i); 105 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 106 107 qemu_fdt_add_subnode(s->fdt, name); 108 qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); 109 if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 110 qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); 111 } 112 qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu"); 113 qemu_fdt_setprop_string(s->fdt, name, "compatible", 114 armcpu->dtb_compatible); 115 g_free(name); 116 } 117 } 118 119 static void fdt_add_gic_nodes(VersalVirt *s) 120 { 121 char *nodename; 122 123 nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); 124 qemu_fdt_add_subnode(s->fdt, nodename); 125 qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); 126 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", 127 GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, 128 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 129 qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); 130 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", 131 2, MM_GIC_APU_DIST_MAIN, 132 2, MM_GIC_APU_DIST_MAIN_SIZE, 133 2, MM_GIC_APU_REDIST_0, 134 2, MM_GIC_APU_REDIST_0_SIZE); 135 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); 136 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); 137 g_free(nodename); 138 } 139 140 static void fdt_add_timer_nodes(VersalVirt *s) 141 { 142 const char compat[] = "arm,armv8-timer"; 143 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 144 145 qemu_fdt_add_subnode(s->fdt, "/timer"); 146 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", 147 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, 148 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, 149 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, 150 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); 151 qemu_fdt_setprop(s->fdt, "/timer", "compatible", 152 compat, sizeof(compat)); 153 } 154 155 static void fdt_add_usb_xhci_nodes(VersalVirt *s) 156 { 157 const char clocknames[] = "bus_clk\0ref_clk"; 158 const char irq_name[] = "dwc_usb3"; 159 const char compatVersalDWC3[] = "xlnx,versal-dwc3"; 160 const char compatDWC3[] = "snps,dwc3"; 161 char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); 162 163 qemu_fdt_add_subnode(s->fdt, name); 164 qemu_fdt_setprop(s->fdt, name, "compatible", 165 compatVersalDWC3, sizeof(compatVersalDWC3)); 166 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 167 2, MM_USB2_CTRL_REGS, 168 2, MM_USB2_CTRL_REGS_SIZE); 169 qemu_fdt_setprop(s->fdt, name, "clock-names", 170 clocknames, sizeof(clocknames)); 171 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 172 s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); 173 qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); 174 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); 175 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); 176 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); 177 g_free(name); 178 179 name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, 180 MM_USB2_CTRL_REGS, MM_USB_0); 181 qemu_fdt_add_subnode(s->fdt, name); 182 qemu_fdt_setprop(s->fdt, name, "compatible", 183 compatDWC3, sizeof(compatDWC3)); 184 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 185 2, MM_USB_0, 2, MM_USB_0_SIZE); 186 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 187 irq_name, sizeof(irq_name)); 188 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 189 GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, 190 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 191 qemu_fdt_setprop_cell(s->fdt, name, 192 "snps,quirk-frame-length-adjustment", 0x20); 193 qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); 194 qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); 195 qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); 196 qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); 197 qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); 198 qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); 199 qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); 200 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); 201 qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); 202 g_free(name); 203 } 204 205 static void fdt_add_uart_nodes(VersalVirt *s) 206 { 207 uint64_t addrs[] = { MM_UART1, MM_UART0 }; 208 unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; 209 const char compat[] = "arm,pl011\0arm,sbsa-uart"; 210 const char clocknames[] = "uartclk\0apb_pclk"; 211 int i; 212 213 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 214 char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]); 215 qemu_fdt_add_subnode(s->fdt, name); 216 qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); 217 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 218 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 219 qemu_fdt_setprop(s->fdt, name, "clock-names", 220 clocknames, sizeof(clocknames)); 221 222 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 223 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 224 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 225 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 226 2, addrs[i], 2, 0x1000); 227 qemu_fdt_setprop(s->fdt, name, "compatible", 228 compat, sizeof(compat)); 229 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 230 231 if (addrs[i] == MM_UART0) { 232 /* Select UART0. */ 233 qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name); 234 } 235 g_free(name); 236 } 237 } 238 239 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, 240 uint32_t phandle) 241 { 242 char *name = g_strdup_printf("%s/fixed-link", gemname); 243 244 qemu_fdt_add_subnode(s->fdt, name); 245 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 246 qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); 247 qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); 248 g_free(name); 249 } 250 251 static void fdt_add_gem_nodes(VersalVirt *s) 252 { 253 uint64_t addrs[] = { MM_GEM1, MM_GEM0 }; 254 unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; 255 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; 256 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; 257 int i; 258 259 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 260 char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); 261 qemu_fdt_add_subnode(s->fdt, name); 262 263 fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); 264 qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); 265 qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", 266 s->phandle.ethernet_phy[i]); 267 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 268 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, 269 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 270 qemu_fdt_setprop(s->fdt, name, "clock-names", 271 clocknames, sizeof(clocknames)); 272 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 273 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 274 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 275 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 276 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 277 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 278 2, addrs[i], 2, 0x1000); 279 qemu_fdt_setprop(s->fdt, name, "compatible", 280 compat_gem, sizeof(compat_gem)); 281 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); 282 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); 283 g_free(name); 284 } 285 } 286 287 static void fdt_add_zdma_nodes(VersalVirt *s) 288 { 289 const char clocknames[] = "clk_main\0clk_apb"; 290 const char compat[] = "xlnx,zynqmp-dma-1.0"; 291 int i; 292 293 for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) { 294 uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i; 295 char *name = g_strdup_printf("/dma@%" PRIx64, addr); 296 297 qemu_fdt_add_subnode(s->fdt, name); 298 299 qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64); 300 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 301 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 302 qemu_fdt_setprop(s->fdt, name, "clock-names", 303 clocknames, sizeof(clocknames)); 304 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 305 GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i, 306 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 307 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 308 2, addr, 2, 0x1000); 309 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 310 g_free(name); 311 } 312 } 313 314 static void fdt_add_sd_nodes(VersalVirt *s) 315 { 316 const char clocknames[] = "clk_xin\0clk_ahb"; 317 const char compat[] = "arasan,sdhci-8.9a"; 318 int i; 319 320 for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) { 321 uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i; 322 char *name = g_strdup_printf("/sdhci@%" PRIx64, addr); 323 324 qemu_fdt_add_subnode(s->fdt, name); 325 326 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 327 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 328 qemu_fdt_setprop(s->fdt, name, "clock-names", 329 clocknames, sizeof(clocknames)); 330 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 331 GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2, 332 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 333 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 334 2, addr, 2, MM_PMC_SD0_SIZE); 335 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 336 g_free(name); 337 } 338 } 339 340 static void fdt_add_rtc_node(VersalVirt *s) 341 { 342 const char compat[] = "xlnx,zynqmp-rtc"; 343 const char interrupt_names[] = "alarm\0sec"; 344 char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC); 345 346 qemu_fdt_add_subnode(s->fdt, name); 347 348 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 349 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ, 350 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 351 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ, 352 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 353 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 354 interrupt_names, sizeof(interrupt_names)); 355 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 356 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE); 357 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 358 g_free(name); 359 } 360 361 static void fdt_add_bbram_node(VersalVirt *s) 362 { 363 const char compat[] = TYPE_XLNX_BBRAM; 364 const char interrupt_names[] = "bbram-error"; 365 char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL); 366 367 qemu_fdt_add_subnode(s->fdt, name); 368 369 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 370 GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ, 371 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 372 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 373 interrupt_names, sizeof(interrupt_names)); 374 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 375 2, MM_PMC_BBRAM_CTRL, 376 2, MM_PMC_BBRAM_CTRL_SIZE); 377 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 378 g_free(name); 379 } 380 381 static void fdt_add_efuse_ctrl_node(VersalVirt *s) 382 { 383 const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL; 384 const char interrupt_names[] = "pmc_efuse"; 385 char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL); 386 387 qemu_fdt_add_subnode(s->fdt, name); 388 389 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 390 GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ, 391 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 392 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 393 interrupt_names, sizeof(interrupt_names)); 394 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 395 2, MM_PMC_EFUSE_CTRL, 396 2, MM_PMC_EFUSE_CTRL_SIZE); 397 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 398 g_free(name); 399 } 400 401 static void fdt_add_efuse_cache_node(VersalVirt *s) 402 { 403 const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE; 404 char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x", 405 MM_PMC_EFUSE_CACHE); 406 407 qemu_fdt_add_subnode(s->fdt, name); 408 409 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 410 2, MM_PMC_EFUSE_CACHE, 411 2, MM_PMC_EFUSE_CACHE_SIZE); 412 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 413 g_free(name); 414 } 415 416 static void fdt_nop_memory_nodes(void *fdt, Error **errp) 417 { 418 Error *err = NULL; 419 char **node_path; 420 int n = 0; 421 422 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 423 if (err) { 424 error_propagate(errp, err); 425 return; 426 } 427 while (node_path[n]) { 428 if (g_str_has_prefix(node_path[n], "/memory")) { 429 qemu_fdt_nop_node(fdt, node_path[n]); 430 } 431 n++; 432 } 433 g_strfreev(node_path); 434 } 435 436 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size) 437 { 438 /* Describes the various split DDR access regions. */ 439 static const struct { 440 uint64_t base; 441 uint64_t size; 442 } addr_ranges[] = { 443 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 444 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 445 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 446 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 447 }; 448 uint64_t mem_reg_prop[8] = {0}; 449 uint64_t size = ram_size; 450 Error *err = NULL; 451 char *name; 452 int i; 453 454 fdt_nop_memory_nodes(fdt, &err); 455 if (err) { 456 error_report_err(err); 457 return; 458 } 459 460 name = g_strdup_printf("/memory@%x", MM_TOP_DDR); 461 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 462 uint64_t mapsize; 463 464 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 465 466 mem_reg_prop[i * 2] = addr_ranges[i].base; 467 mem_reg_prop[i * 2 + 1] = mapsize; 468 size -= mapsize; 469 } 470 qemu_fdt_add_subnode(fdt, name); 471 qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); 472 473 switch (i) { 474 case 1: 475 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 476 2, mem_reg_prop[0], 477 2, mem_reg_prop[1]); 478 break; 479 case 2: 480 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 481 2, mem_reg_prop[0], 482 2, mem_reg_prop[1], 483 2, mem_reg_prop[2], 484 2, mem_reg_prop[3]); 485 break; 486 case 3: 487 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 488 2, mem_reg_prop[0], 489 2, mem_reg_prop[1], 490 2, mem_reg_prop[2], 491 2, mem_reg_prop[3], 492 2, mem_reg_prop[4], 493 2, mem_reg_prop[5]); 494 break; 495 case 4: 496 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 497 2, mem_reg_prop[0], 498 2, mem_reg_prop[1], 499 2, mem_reg_prop[2], 500 2, mem_reg_prop[3], 501 2, mem_reg_prop[4], 502 2, mem_reg_prop[5], 503 2, mem_reg_prop[6], 504 2, mem_reg_prop[7]); 505 break; 506 default: 507 g_assert_not_reached(); 508 } 509 g_free(name); 510 } 511 512 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, 513 void *fdt) 514 { 515 VersalVirt *s = container_of(binfo, VersalVirt, binfo); 516 517 fdt_add_memory_nodes(s, fdt, binfo->ram_size); 518 } 519 520 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, 521 int *fdt_size) 522 { 523 const VersalVirt *board = container_of(binfo, VersalVirt, binfo); 524 525 *fdt_size = board->fdt_size; 526 return board->fdt; 527 } 528 529 #define NUM_VIRTIO_TRANSPORT 8 530 static void create_virtio_regions(VersalVirt *s) 531 { 532 int virtio_mmio_size = 0x200; 533 int i; 534 535 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 536 char *name = g_strdup_printf("virtio%d", i); 537 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 538 int irq = VERSAL_RSVD_IRQ_FIRST + i; 539 MemoryRegion *mr; 540 DeviceState *dev; 541 qemu_irq pic_irq; 542 543 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 544 dev = qdev_new("virtio-mmio"); 545 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 546 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 547 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 548 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 549 memory_region_add_subregion(&s->soc.mr_ps, base, mr); 550 g_free(name); 551 } 552 553 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 554 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 555 int irq = VERSAL_RSVD_IRQ_FIRST + i; 556 char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 557 558 qemu_fdt_add_subnode(s->fdt, name); 559 qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); 560 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 561 GIC_FDT_IRQ_TYPE_SPI, irq, 562 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 563 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 564 2, base, 2, virtio_mmio_size); 565 qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); 566 g_free(name); 567 } 568 } 569 570 static void bbram_attach_drive(XlnxBBRam *dev) 571 { 572 DriveInfo *dinfo; 573 BlockBackend *blk; 574 575 dinfo = drive_get_by_index(IF_PFLASH, 0); 576 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 577 if (blk) { 578 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 579 } 580 } 581 582 static void efuse_attach_drive(XlnxEFuse *dev) 583 { 584 DriveInfo *dinfo; 585 BlockBackend *blk; 586 587 dinfo = drive_get_by_index(IF_PFLASH, 1); 588 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 589 if (blk) { 590 qdev_prop_set_drive(DEVICE(dev), "drive", blk); 591 } 592 } 593 594 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) 595 { 596 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 597 DeviceState *card; 598 599 card = qdev_new(TYPE_SD_CARD); 600 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card)); 601 qdev_prop_set_drive_err(card, "drive", blk, &error_fatal); 602 qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"), 603 &error_fatal); 604 } 605 606 static void versal_virt_init(MachineState *machine) 607 { 608 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine); 609 int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 610 int i; 611 612 /* 613 * If the user provides an Operating System to be loaded, we expect them 614 * to use the -kernel command line option. 615 * 616 * Users can load firmware or boot-loaders with the -device loader options. 617 * 618 * When loading an OS, we generate a dtb and let arm_load_kernel() select 619 * where it gets loaded. This dtb will be passed to the kernel in x0. 620 * 621 * If there's no -kernel option, we generate a DTB and place it at 0x1000 622 * for the bootloaders or firmware to pick up. 623 * 624 * If users want to provide their own DTB, they can use the -dtb option. 625 * These dtb's will have their memory nodes modified to match QEMU's 626 * selected ram_size option before they get passed to the kernel or fw. 627 * 628 * When loading an OS, we turn on QEMU's PSCI implementation with SMC 629 * as the PSCI conduit. When there's no -kernel, we assume the user 630 * provides EL3 firmware to handle PSCI. 631 * 632 * Even if the user provides a kernel filename, arm_load_kernel() 633 * may suppress PSCI if it's going to boot that guest code at EL3. 634 */ 635 if (machine->kernel_filename) { 636 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 637 } 638 639 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 640 TYPE_XLNX_VERSAL); 641 object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), 642 &error_abort); 643 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 644 645 fdt_create(s); 646 create_virtio_regions(s); 647 fdt_add_gem_nodes(s); 648 fdt_add_uart_nodes(s); 649 fdt_add_gic_nodes(s); 650 fdt_add_timer_nodes(s); 651 fdt_add_zdma_nodes(s); 652 fdt_add_usb_xhci_nodes(s); 653 fdt_add_sd_nodes(s); 654 fdt_add_rtc_node(s); 655 fdt_add_bbram_node(s); 656 fdt_add_efuse_ctrl_node(s); 657 fdt_add_efuse_cache_node(s); 658 fdt_add_cpu_nodes(s, psci_conduit); 659 fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); 660 fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); 661 662 /* Make the APU cpu address space visible to virtio and other 663 * modules unaware of muliple address-spaces. */ 664 memory_region_add_subregion_overlap(get_system_memory(), 665 0, &s->soc.fpd.apu.mr, 0); 666 667 /* Attach bbram backend, if given */ 668 bbram_attach_drive(&s->soc.pmc.bbram); 669 670 /* Attach efuse backend, if given */ 671 efuse_attach_drive(&s->soc.pmc.efuse); 672 673 /* Plugin SD cards. */ 674 for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { 675 sd_plugin_card(&s->soc.pmc.iou.sd[i], 676 drive_get(IF_SD, 0, i)); 677 } 678 679 s->binfo.ram_size = machine->ram_size; 680 s->binfo.loader_start = 0x0; 681 s->binfo.get_dtb = versal_virt_get_dtb; 682 s->binfo.modify_dtb = versal_virt_modify_dtb; 683 s->binfo.psci_conduit = psci_conduit; 684 if (!machine->kernel_filename) { 685 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL). 686 * Offset things by 4K. */ 687 s->binfo.loader_start = 0x1000; 688 s->binfo.dtb_limit = 0x1000000; 689 } 690 arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); 691 692 for (i = 0; i < XLNX_VERSAL_NUM_OSPI_FLASH; i++) { 693 BusState *spi_bus; 694 DeviceState *flash_dev; 695 qemu_irq cs_line; 696 DriveInfo *dinfo = drive_get(IF_MTD, 0, i); 697 698 spi_bus = qdev_get_child_bus(DEVICE(&s->soc.pmc.iou.ospi), "spi0"); 699 700 flash_dev = qdev_new("mt35xu01g"); 701 if (dinfo) { 702 qdev_prop_set_drive_err(flash_dev, "drive", 703 blk_by_legacy_dinfo(dinfo), &error_fatal); 704 } 705 qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); 706 707 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 708 709 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.pmc.iou.ospi), 710 i + 1, cs_line); 711 } 712 } 713 714 static void versal_virt_machine_instance_init(Object *obj) 715 { 716 } 717 718 static void versal_virt_machine_class_init(ObjectClass *oc, void *data) 719 { 720 MachineClass *mc = MACHINE_CLASS(oc); 721 722 mc->desc = "Xilinx Versal Virtual development board"; 723 mc->init = versal_virt_init; 724 mc->min_cpus = XLNX_VERSAL_NR_ACPUS; 725 mc->max_cpus = XLNX_VERSAL_NR_ACPUS; 726 mc->default_cpus = XLNX_VERSAL_NR_ACPUS; 727 mc->no_cdrom = true; 728 mc->default_ram_id = "ddr"; 729 } 730 731 static const TypeInfo versal_virt_machine_init_typeinfo = { 732 .name = TYPE_XLNX_VERSAL_VIRT_MACHINE, 733 .parent = TYPE_MACHINE, 734 .class_init = versal_virt_machine_class_init, 735 .instance_init = versal_virt_machine_instance_init, 736 .instance_size = sizeof(VersalVirt), 737 }; 738 739 static void versal_virt_machine_init_register_types(void) 740 { 741 type_register_static(&versal_virt_machine_init_typeinfo); 742 } 743 744 type_init(versal_virt_machine_init_register_types) 745 746