1 /* 2 * Xilinx Versal Virtual board. 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qemu/error-report.h" 14 #include "qapi/error.h" 15 #include "sysemu/device_tree.h" 16 #include "hw/boards.h" 17 #include "hw/sysbus.h" 18 #include "hw/arm/sysbus-fdt.h" 19 #include "hw/arm/fdt.h" 20 #include "cpu.h" 21 #include "hw/qdev-properties.h" 22 #include "hw/arm/xlnx-versal.h" 23 #include "qom/object.h" 24 25 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") 26 OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE) 27 28 struct VersalVirt { 29 MachineState parent_obj; 30 31 Versal soc; 32 33 void *fdt; 34 int fdt_size; 35 struct { 36 uint32_t gic; 37 uint32_t ethernet_phy[2]; 38 uint32_t clk_125Mhz; 39 uint32_t clk_25Mhz; 40 uint32_t usb; 41 uint32_t dwc; 42 } phandle; 43 struct arm_boot_info binfo; 44 45 struct { 46 bool secure; 47 } cfg; 48 }; 49 50 static void fdt_create(VersalVirt *s) 51 { 52 MachineClass *mc = MACHINE_GET_CLASS(s); 53 int i; 54 55 s->fdt = create_device_tree(&s->fdt_size); 56 if (!s->fdt) { 57 error_report("create_device_tree() failed"); 58 exit(1); 59 } 60 61 /* Allocate all phandles. */ 62 s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt); 63 for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { 64 s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt); 65 } 66 s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt); 67 s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt); 68 69 s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt); 70 s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt); 71 /* Create /chosen node for load_dtb. */ 72 qemu_fdt_add_subnode(s->fdt, "/chosen"); 73 74 /* Header */ 75 qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic); 76 qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2); 77 qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2); 78 qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc); 79 qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt"); 80 } 81 82 static void fdt_add_clk_node(VersalVirt *s, const char *name, 83 unsigned int freq_hz, uint32_t phandle) 84 { 85 qemu_fdt_add_subnode(s->fdt, name); 86 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 87 qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz); 88 qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0); 89 qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock"); 90 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 91 } 92 93 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) 94 { 95 int i; 96 97 qemu_fdt_add_subnode(s->fdt, "/cpus"); 98 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0); 99 qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1); 100 101 for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) { 102 char *name = g_strdup_printf("/cpus/cpu@%d", i); 103 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); 104 105 qemu_fdt_add_subnode(s->fdt, name); 106 qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); 107 if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { 108 qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); 109 } 110 qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu"); 111 qemu_fdt_setprop_string(s->fdt, name, "compatible", 112 armcpu->dtb_compatible); 113 g_free(name); 114 } 115 } 116 117 static void fdt_add_gic_nodes(VersalVirt *s) 118 { 119 char *nodename; 120 121 nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN); 122 qemu_fdt_add_subnode(s->fdt, nodename); 123 qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic); 124 qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts", 125 GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, 126 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 127 qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0); 128 qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", 129 2, MM_GIC_APU_DIST_MAIN, 130 2, MM_GIC_APU_DIST_MAIN_SIZE, 131 2, MM_GIC_APU_REDIST_0, 132 2, MM_GIC_APU_REDIST_0_SIZE); 133 qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); 134 qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); 135 g_free(nodename); 136 } 137 138 static void fdt_add_timer_nodes(VersalVirt *s) 139 { 140 const char compat[] = "arm,armv8-timer"; 141 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; 142 143 qemu_fdt_add_subnode(s->fdt, "/timer"); 144 qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts", 145 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags, 146 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags, 147 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags, 148 GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags); 149 qemu_fdt_setprop(s->fdt, "/timer", "compatible", 150 compat, sizeof(compat)); 151 } 152 153 static void fdt_add_usb_xhci_nodes(VersalVirt *s) 154 { 155 const char clocknames[] = "bus_clk\0ref_clk"; 156 const char irq_name[] = "dwc_usb3"; 157 const char compatVersalDWC3[] = "xlnx,versal-dwc3"; 158 const char compatDWC3[] = "snps,dwc3"; 159 char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); 160 161 qemu_fdt_add_subnode(s->fdt, name); 162 qemu_fdt_setprop(s->fdt, name, "compatible", 163 compatVersalDWC3, sizeof(compatVersalDWC3)); 164 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 165 2, MM_USB2_CTRL_REGS, 166 2, MM_USB2_CTRL_REGS_SIZE); 167 qemu_fdt_setprop(s->fdt, name, "clock-names", 168 clocknames, sizeof(clocknames)); 169 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 170 s->phandle.clk_25Mhz, s->phandle.clk_125Mhz); 171 qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); 172 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); 173 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); 174 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); 175 g_free(name); 176 177 name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, 178 MM_USB2_CTRL_REGS, MM_USB_0); 179 qemu_fdt_add_subnode(s->fdt, name); 180 qemu_fdt_setprop(s->fdt, name, "compatible", 181 compatDWC3, sizeof(compatDWC3)); 182 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 183 2, MM_USB_0, 2, MM_USB_0_SIZE); 184 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 185 irq_name, sizeof(irq_name)); 186 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 187 GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, 188 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 189 qemu_fdt_setprop_cell(s->fdt, name, 190 "snps,quirk-frame-length-adjustment", 0x20); 191 qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); 192 qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); 193 qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); 194 qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); 195 qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); 196 qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); 197 qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); 198 qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); 199 qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); 200 g_free(name); 201 } 202 203 static void fdt_add_uart_nodes(VersalVirt *s) 204 { 205 uint64_t addrs[] = { MM_UART1, MM_UART0 }; 206 unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 }; 207 const char compat[] = "arm,pl011\0arm,sbsa-uart"; 208 const char clocknames[] = "uartclk\0apb_pclk"; 209 int i; 210 211 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 212 char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]); 213 qemu_fdt_add_subnode(s->fdt, name); 214 qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200); 215 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 216 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 217 qemu_fdt_setprop(s->fdt, name, "clock-names", 218 clocknames, sizeof(clocknames)); 219 220 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 221 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 222 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 223 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 224 2, addrs[i], 2, 0x1000); 225 qemu_fdt_setprop(s->fdt, name, "compatible", 226 compat, sizeof(compat)); 227 qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0); 228 229 if (addrs[i] == MM_UART0) { 230 /* Select UART0. */ 231 qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name); 232 } 233 g_free(name); 234 } 235 } 236 237 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, 238 uint32_t phandle) 239 { 240 char *name = g_strdup_printf("%s/fixed-link", gemname); 241 242 qemu_fdt_add_subnode(s->fdt, name); 243 qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); 244 qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); 245 qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); 246 g_free(name); 247 } 248 249 static void fdt_add_gem_nodes(VersalVirt *s) 250 { 251 uint64_t addrs[] = { MM_GEM1, MM_GEM0 }; 252 unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; 253 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; 254 const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem"; 255 int i; 256 257 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 258 char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); 259 qemu_fdt_add_subnode(s->fdt, name); 260 261 fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); 262 qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); 263 qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", 264 s->phandle.ethernet_phy[i]); 265 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 266 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, 267 s->phandle.clk_125Mhz, s->phandle.clk_125Mhz); 268 qemu_fdt_setprop(s->fdt, name, "clock-names", 269 clocknames, sizeof(clocknames)); 270 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 271 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 272 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 273 GIC_FDT_IRQ_TYPE_SPI, irqs[i], 274 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 275 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 276 2, addrs[i], 2, 0x1000); 277 qemu_fdt_setprop(s->fdt, name, "compatible", 278 compat_gem, sizeof(compat_gem)); 279 qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); 280 qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); 281 g_free(name); 282 } 283 } 284 285 static void fdt_add_zdma_nodes(VersalVirt *s) 286 { 287 const char clocknames[] = "clk_main\0clk_apb"; 288 const char compat[] = "xlnx,zynqmp-dma-1.0"; 289 int i; 290 291 for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) { 292 uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i; 293 char *name = g_strdup_printf("/dma@%" PRIx64, addr); 294 295 qemu_fdt_add_subnode(s->fdt, name); 296 297 qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64); 298 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 299 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 300 qemu_fdt_setprop(s->fdt, name, "clock-names", 301 clocknames, sizeof(clocknames)); 302 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 303 GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i, 304 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 305 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 306 2, addr, 2, 0x1000); 307 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 308 g_free(name); 309 } 310 } 311 312 static void fdt_add_sd_nodes(VersalVirt *s) 313 { 314 const char clocknames[] = "clk_xin\0clk_ahb"; 315 const char compat[] = "arasan,sdhci-8.9a"; 316 int i; 317 318 for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) { 319 uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i; 320 char *name = g_strdup_printf("/sdhci@%" PRIx64, addr); 321 322 qemu_fdt_add_subnode(s->fdt, name); 323 324 qemu_fdt_setprop_cells(s->fdt, name, "clocks", 325 s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); 326 qemu_fdt_setprop(s->fdt, name, "clock-names", 327 clocknames, sizeof(clocknames)); 328 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 329 GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2, 330 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 331 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 332 2, addr, 2, MM_PMC_SD0_SIZE); 333 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 334 g_free(name); 335 } 336 } 337 338 static void fdt_add_rtc_node(VersalVirt *s) 339 { 340 const char compat[] = "xlnx,zynqmp-rtc"; 341 const char interrupt_names[] = "alarm\0sec"; 342 char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC); 343 344 qemu_fdt_add_subnode(s->fdt, name); 345 346 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 347 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ, 348 GIC_FDT_IRQ_FLAGS_LEVEL_HI, 349 GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ, 350 GIC_FDT_IRQ_FLAGS_LEVEL_HI); 351 qemu_fdt_setprop(s->fdt, name, "interrupt-names", 352 interrupt_names, sizeof(interrupt_names)); 353 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 354 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE); 355 qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); 356 g_free(name); 357 } 358 359 static void fdt_nop_memory_nodes(void *fdt, Error **errp) 360 { 361 Error *err = NULL; 362 char **node_path; 363 int n = 0; 364 365 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err); 366 if (err) { 367 error_propagate(errp, err); 368 return; 369 } 370 while (node_path[n]) { 371 if (g_str_has_prefix(node_path[n], "/memory")) { 372 qemu_fdt_nop_node(fdt, node_path[n]); 373 } 374 n++; 375 } 376 g_strfreev(node_path); 377 } 378 379 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size) 380 { 381 /* Describes the various split DDR access regions. */ 382 static const struct { 383 uint64_t base; 384 uint64_t size; 385 } addr_ranges[] = { 386 { MM_TOP_DDR, MM_TOP_DDR_SIZE }, 387 { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, 388 { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, 389 { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } 390 }; 391 uint64_t mem_reg_prop[8] = {0}; 392 uint64_t size = ram_size; 393 Error *err = NULL; 394 char *name; 395 int i; 396 397 fdt_nop_memory_nodes(fdt, &err); 398 if (err) { 399 error_report_err(err); 400 return; 401 } 402 403 name = g_strdup_printf("/memory@%x", MM_TOP_DDR); 404 for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { 405 uint64_t mapsize; 406 407 mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; 408 409 mem_reg_prop[i * 2] = addr_ranges[i].base; 410 mem_reg_prop[i * 2 + 1] = mapsize; 411 size -= mapsize; 412 } 413 qemu_fdt_add_subnode(fdt, name); 414 qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); 415 416 switch (i) { 417 case 1: 418 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 419 2, mem_reg_prop[0], 420 2, mem_reg_prop[1]); 421 break; 422 case 2: 423 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 424 2, mem_reg_prop[0], 425 2, mem_reg_prop[1], 426 2, mem_reg_prop[2], 427 2, mem_reg_prop[3]); 428 break; 429 case 3: 430 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 431 2, mem_reg_prop[0], 432 2, mem_reg_prop[1], 433 2, mem_reg_prop[2], 434 2, mem_reg_prop[3], 435 2, mem_reg_prop[4], 436 2, mem_reg_prop[5]); 437 break; 438 case 4: 439 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 440 2, mem_reg_prop[0], 441 2, mem_reg_prop[1], 442 2, mem_reg_prop[2], 443 2, mem_reg_prop[3], 444 2, mem_reg_prop[4], 445 2, mem_reg_prop[5], 446 2, mem_reg_prop[6], 447 2, mem_reg_prop[7]); 448 break; 449 default: 450 g_assert_not_reached(); 451 } 452 g_free(name); 453 } 454 455 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, 456 void *fdt) 457 { 458 VersalVirt *s = container_of(binfo, VersalVirt, binfo); 459 460 fdt_add_memory_nodes(s, fdt, binfo->ram_size); 461 } 462 463 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, 464 int *fdt_size) 465 { 466 const VersalVirt *board = container_of(binfo, VersalVirt, binfo); 467 468 *fdt_size = board->fdt_size; 469 return board->fdt; 470 } 471 472 #define NUM_VIRTIO_TRANSPORT 8 473 static void create_virtio_regions(VersalVirt *s) 474 { 475 int virtio_mmio_size = 0x200; 476 int i; 477 478 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 479 char *name = g_strdup_printf("virtio%d", i); 480 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 481 int irq = VERSAL_RSVD_IRQ_FIRST + i; 482 MemoryRegion *mr; 483 DeviceState *dev; 484 qemu_irq pic_irq; 485 486 pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq); 487 dev = qdev_new("virtio-mmio"); 488 object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev)); 489 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 490 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); 491 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 492 memory_region_add_subregion(&s->soc.mr_ps, base, mr); 493 g_free(name); 494 } 495 496 for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { 497 hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size; 498 int irq = VERSAL_RSVD_IRQ_FIRST + i; 499 char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base); 500 501 qemu_fdt_add_subnode(s->fdt, name); 502 qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0); 503 qemu_fdt_setprop_cells(s->fdt, name, "interrupts", 504 GIC_FDT_IRQ_TYPE_SPI, irq, 505 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); 506 qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", 507 2, base, 2, virtio_mmio_size); 508 qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio"); 509 g_free(name); 510 } 511 } 512 513 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) 514 { 515 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; 516 DeviceState *card; 517 518 card = qdev_new(TYPE_SD_CARD); 519 object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card)); 520 qdev_prop_set_drive_err(card, "drive", blk, &error_fatal); 521 qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"), 522 &error_fatal); 523 } 524 525 static void versal_virt_init(MachineState *machine) 526 { 527 VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine); 528 int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; 529 int i; 530 531 /* 532 * If the user provides an Operating System to be loaded, we expect them 533 * to use the -kernel command line option. 534 * 535 * Users can load firmware or boot-loaders with the -device loader options. 536 * 537 * When loading an OS, we generate a dtb and let arm_load_kernel() select 538 * where it gets loaded. This dtb will be passed to the kernel in x0. 539 * 540 * If there's no -kernel option, we generate a DTB and place it at 0x1000 541 * for the bootloaders or firmware to pick up. 542 * 543 * If users want to provide their own DTB, they can use the -dtb option. 544 * These dtb's will have their memory nodes modified to match QEMU's 545 * selected ram_size option before they get passed to the kernel or fw. 546 * 547 * When loading an OS, we turn on QEMU's PSCI implementation with SMC 548 * as the PSCI conduit. When there's no -kernel, we assume the user 549 * provides EL3 firmware to handle PSCI. 550 */ 551 if (machine->kernel_filename) { 552 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 553 } 554 555 object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 556 TYPE_XLNX_VERSAL); 557 object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), 558 &error_abort); 559 object_property_set_int(OBJECT(&s->soc), "psci-conduit", psci_conduit, 560 &error_abort); 561 sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 562 563 fdt_create(s); 564 create_virtio_regions(s); 565 fdt_add_gem_nodes(s); 566 fdt_add_uart_nodes(s); 567 fdt_add_gic_nodes(s); 568 fdt_add_timer_nodes(s); 569 fdt_add_zdma_nodes(s); 570 fdt_add_usb_xhci_nodes(s); 571 fdt_add_sd_nodes(s); 572 fdt_add_rtc_node(s); 573 fdt_add_cpu_nodes(s, psci_conduit); 574 fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); 575 fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); 576 577 /* Make the APU cpu address space visible to virtio and other 578 * modules unaware of muliple address-spaces. */ 579 memory_region_add_subregion_overlap(get_system_memory(), 580 0, &s->soc.fpd.apu.mr, 0); 581 582 /* Plugin SD cards. */ 583 for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { 584 sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); 585 } 586 587 s->binfo.ram_size = machine->ram_size; 588 s->binfo.loader_start = 0x0; 589 s->binfo.get_dtb = versal_virt_get_dtb; 590 s->binfo.modify_dtb = versal_virt_modify_dtb; 591 if (machine->kernel_filename) { 592 arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); 593 } else { 594 AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0], 595 &s->binfo); 596 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL). 597 * Offset things by 4K. */ 598 s->binfo.loader_start = 0x1000; 599 s->binfo.dtb_limit = 0x1000000; 600 if (arm_load_dtb(s->binfo.loader_start, 601 &s->binfo, s->binfo.dtb_limit, as, machine) < 0) { 602 exit(EXIT_FAILURE); 603 } 604 } 605 } 606 607 static void versal_virt_machine_instance_init(Object *obj) 608 { 609 } 610 611 static void versal_virt_machine_class_init(ObjectClass *oc, void *data) 612 { 613 MachineClass *mc = MACHINE_CLASS(oc); 614 615 mc->desc = "Xilinx Versal Virtual development board"; 616 mc->init = versal_virt_init; 617 mc->min_cpus = XLNX_VERSAL_NR_ACPUS; 618 mc->max_cpus = XLNX_VERSAL_NR_ACPUS; 619 mc->default_cpus = XLNX_VERSAL_NR_ACPUS; 620 mc->no_cdrom = true; 621 mc->default_ram_id = "ddr"; 622 } 623 624 static const TypeInfo versal_virt_machine_init_typeinfo = { 625 .name = TYPE_XLNX_VERSAL_VIRT_MACHINE, 626 .parent = TYPE_MACHINE, 627 .class_init = versal_virt_machine_class_init, 628 .instance_init = versal_virt_machine_instance_init, 629 .instance_size = sizeof(VersalVirt), 630 }; 631 632 static void versal_virt_machine_init_register_types(void) 633 { 634 type_register_static(&versal_virt_machine_init_typeinfo); 635 } 636 637 type_init(versal_virt_machine_init_register_types) 638 639